sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.all_ip_placed == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_10 == E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_11 == E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_13 == E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_14 == E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_16 == E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_17 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_18 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_19 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_20 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_21 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_22 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_8 == E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_duplex_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_duplex_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_duplex_10 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_duplex_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_duplex_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_duplex_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_duplex_14 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_duplex_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_duplex_16 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_duplex_17 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_duplex_18 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_duplex_19 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_duplex_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_duplex_20 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_duplex_21 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_duplex_22 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_duplex_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_duplex_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_duplex_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_duplex_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_duplex_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_duplex_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_duplex_8 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_duplex_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_rx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_rx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_rx_10 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_rx_11 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_rx_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_rx_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_rx_14 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_rx_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_rx_16 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_rx_17 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_rx_18 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_rx_19 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_rx_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_rx_20 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_rx_21 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_rx_22 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_rx_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_rx_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_rx_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_rx_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_rx_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_rx_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_rx_8 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_rx_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_tx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_tx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_tx_10 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_tx_11 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_tx_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_tx_13 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_tx_14 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_tx_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_tx_16 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_tx_17 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_tx_18 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_tx_19 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_tx_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_tx_20 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_tx_21 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_tx_22 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_tx_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_tx_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_tx_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_tx_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_tx_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_tx_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_tx_8 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_maib_tx_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_rx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_rx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_rx_10 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_rx_11 == E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_rx_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_rx_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_rx_14 == E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_rx_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_rx_16 == E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_rx_17 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_rx_18 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_rx_19 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_rx_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_rx_20 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_rx_21 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_rx_22 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_rx_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_rx_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_rx_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_rx_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_rx_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_rx_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_rx_8 == E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_rx_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_tx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_tx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_tx_10 == E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_tx_11 == E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_tx_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_tx_13 == E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_tx_14 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_tx_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_tx_16 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_tx_17 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_tx_18 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_tx_19 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_tx_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_tx_20 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_tx_21 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_tx_22 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_tx_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_tx_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_tx_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_tx_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_tx_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_tx_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_tx_8 == E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_aib_tx_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_rx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_rx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_rx_10 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_rx_11 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_rx_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_rx_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_rx_14 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_rx_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_rx_16 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_rx_17 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_rx_18 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_rx_19 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_rx_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_rx_20 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_rx_21 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_rx_22 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_rx_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_rx_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_rx_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_rx_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_rx_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_rx_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_rx_8 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_rx_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_tx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_tx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_tx_10 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_tx_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_tx_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_tx_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_tx_14 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_tx_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_tx_16 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_tx_17 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_tx_18 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_tx_19 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_tx_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_tx_20 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_tx_21 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_tx_22 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_tx_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_tx_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_tx_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_tx_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_tx_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_tx_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_tx_8 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_aib_tx_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e200g_rx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e200g_rx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e200g_rx_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e200g_rx_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e200g_rx_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e200g_rx_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e200g_rx_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e200g_rx_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e200g_tx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e200g_tx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e200g_tx_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e200g_tx_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e200g_tx_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e200g_tx_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e200g_tx_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e200g_tx_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e400g_rx_10 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e400g_rx_11 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e400g_rx_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e400g_rx_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e400g_rx_14 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e400g_rx_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e400g_rx_16 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e400g_rx_17 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e400g_rx_18 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e400g_rx_19 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e400g_rx_20 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e400g_rx_21 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e400g_rx_22 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e400g_rx_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e400g_rx_8 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e400g_rx_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e400g_tx_10 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e400g_tx_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e400g_tx_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e400g_tx_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e400g_tx_14 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e400g_tx_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e400g_tx_16 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e400g_tx_17 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e400g_tx_18 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e400g_tx_19 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e400g_tx_20 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e400g_tx_21 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e400g_tx_22 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e400g_tx_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e400g_tx_8 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_e400g_tx_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_rx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_rx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_rx_10 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_rx_11 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_rx_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_rx_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_rx_14 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_rx_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_rx_16 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_rx_17 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_rx_18 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_rx_19 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_rx_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_rx_20 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_rx_21 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_rx_22 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_rx_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_rx_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_rx_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_rx_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_rx_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_rx_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_rx_8 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_rx_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_tx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_tx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_tx_10 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_tx_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_tx_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_tx_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_tx_14 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_tx_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_tx_16 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_tx_17 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_tx_18 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_tx_19 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_tx_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_tx_20 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_tx_21 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_tx_22 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_tx_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_tx_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_tx_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_tx_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_tx_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_tx_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_tx_8 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_hdpldadapt_tx_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_rx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_rx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_rx_10 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_rx_11 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_rx_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_rx_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_rx_14 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_rx_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_rx_16 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_rx_17 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_rx_18 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_rx_19 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_rx_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_rx_20 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_rx_21 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_rx_22 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_rx_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_rx_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_rx_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_rx_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_rx_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_rx_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_rx_8 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_rx_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_tx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_tx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_tx_10 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_tx_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_tx_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_tx_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_tx_14 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_tx_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_tx_16 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_tx_17 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_tx_18 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_tx_19 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_tx_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_tx_20 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_tx_21 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_tx_22 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_tx_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_tx_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_tx_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_tx_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_tx_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_tx_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_tx_8 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm1_maib_tx_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_bk_20 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_bk_21 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_bk_22 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_bk_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_pcie_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_pcie_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_pcie_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_pcie_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_ux_rx_10 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_ux_rx_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_ux_rx_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_ux_rx_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_ux_rx_14 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_ux_rx_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_ux_rx_16 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_ux_rx_17 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_ux_rx_18 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_ux_rx_19 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_ux_rx_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_ux_rx_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_ux_rx_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_ux_rx_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_ux_rx_8 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_ux_rx_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_ux_tx_10 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_ux_tx_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_ux_tx_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_ux_tx_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_ux_tx_14 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_ux_tx_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_ux_tx_16 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_ux_tx_17 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_ux_tx_18 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_ux_tx_19 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_ux_tx_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_ux_tx_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_ux_tx_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_ux_tx_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_ux_tx_8 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_avmm2_ux_tx_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_bk_0_bk_cmnpll == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_bk_1_bk_cmnpll == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_bk_2_bk_cmnpll == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_bk_3_bk_cmnpll == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_bk_bonding_1_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_bk_bonding_2_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_bk_bonding_3_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_bk_common_pll_a_refclk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_bk_common_pll_b_refclk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_bundle_100g_rx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_bundle_100g_rx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_bundle_100g_tx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_bundle_100g_tx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_bundle_150g_rx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_bundle_150g_rx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_bundle_150g_tx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_bundle_150g_tx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_bundle_200g_rx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_bundle_200g_tx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_bundle_50g_rx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_bundle_50g_rx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_bundle_50g_rx_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_bundle_50g_rx_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_bundle_50g_tx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_bundle_50g_tx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_bundle_50g_tx_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_bundle_50g_tx_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f100g_duplex_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f100g_duplex_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f150g_duplex_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f150g_duplex_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f200g_duplex_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f25g_duplex_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f25g_duplex_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f25g_duplex_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f25g_duplex_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f25g_duplex_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f25g_duplex_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f25g_duplex_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f25g_duplex_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f25g_rx_bonding_0_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f25g_rx_bonding_1_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f25g_rx_bonding_2_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f25g_rx_bonding_3_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f25g_rx_bonding_4_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f25g_rx_bonding_5_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f25g_rx_bonding_6_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f25g_tx_bonding_0_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f25g_tx_bonding_1_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f25g_tx_bonding_2_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f25g_tx_bonding_3_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f25g_tx_bonding_4_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f25g_tx_bonding_5_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f25g_tx_bonding_6_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f50g_duplex_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f50g_duplex_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f50g_duplex_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f50g_duplex_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f50g_rx_bonding_0_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f50g_rx_bonding_1_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f50g_rx_bonding_2_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f50g_tx_bonding_0_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f50g_tx_bonding_1_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_f50g_tx_bonding_2_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_ux_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_ux_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_ux_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_ux_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_ux_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_ux_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_ux_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_ux_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_ux_rx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_ux_rx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_ux_rx_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_ux_rx_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_ux_rx_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_ux_rx_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_ux_rx_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_ux_rx_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_ux_tx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_ux_tx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_ux_tx_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_ux_tx_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_ux_tx_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_ux_tx_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_ux_tx_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e200g_ux_tx_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bk_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bk_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bk_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bk_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bk_rx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bk_rx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bk_rx_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bk_rx_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bk_tx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bk_tx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bk_tx_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bk_tx_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_100g_rx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_100g_rx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_100g_rx_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_100g_rx_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_100g_tx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_100g_tx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_100g_tx_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_100g_tx_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_150g_rx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_150g_rx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_150g_rx_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_150g_rx_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_150g_tx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_150g_tx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_150g_tx_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_150g_tx_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_200g_rx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_200g_rx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_200g_tx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_200g_tx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_300g_rx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_300g_rx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_300g_tx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_300g_tx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_400g_rx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_400g_tx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_50g_rx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_50g_rx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_50g_rx_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_50g_rx_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_50g_rx_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_50g_rx_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_50g_rx_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_50g_rx_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_50g_tx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_50g_tx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_50g_tx_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_50g_tx_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_50g_tx_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_50g_tx_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_50g_tx_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_bundle_50g_tx_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f100g_duplex_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f100g_duplex_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f100g_duplex_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f100g_duplex_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f100g_rx_bonding_0_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f100g_rx_bonding_1_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f100g_rx_bonding_2_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f100g_tx_bonding_0_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f100g_tx_bonding_1_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f100g_tx_bonding_2_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f150g_duplex_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f150g_duplex_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f150g_duplex_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f150g_duplex_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f200g_duplex_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f200g_duplex_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_duplex_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_duplex_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_duplex_10 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_duplex_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_duplex_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_duplex_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_duplex_14 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_duplex_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_duplex_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_duplex_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_duplex_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_duplex_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_duplex_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_duplex_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_duplex_8 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_duplex_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_rx_bonding_0_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_rx_bonding_10_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_rx_bonding_11_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_rx_bonding_12_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_rx_bonding_13_14 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_rx_bonding_14_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_rx_bonding_1_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_rx_bonding_2_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_rx_bonding_3_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_rx_bonding_4_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_rx_bonding_5_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_rx_bonding_6_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_rx_bonding_7_8 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_rx_bonding_8_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_rx_bonding_9_10 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_tx_bonding_0_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_tx_bonding_10_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_tx_bonding_11_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_tx_bonding_12_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_tx_bonding_13_14 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_tx_bonding_14_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_tx_bonding_1_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_tx_bonding_2_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_tx_bonding_3_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_tx_bonding_4_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_tx_bonding_5_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_tx_bonding_6_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_tx_bonding_7_8 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_tx_bonding_8_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f25g_tx_bonding_9_10 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f300g_duplex_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f300g_duplex_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f400g_duplex_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f50g_duplex_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f50g_duplex_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f50g_duplex_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f50g_duplex_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f50g_duplex_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f50g_duplex_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f50g_duplex_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f50g_duplex_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f50g_rx_bonding_0_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f50g_rx_bonding_1_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f50g_rx_bonding_2_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f50g_rx_bonding_3_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f50g_rx_bonding_4_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f50g_rx_bonding_5_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f50g_rx_bonding_6_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f50g_tx_bonding_0_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f50g_tx_bonding_1_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f50g_tx_bonding_2_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f50g_tx_bonding_3_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f50g_tx_bonding_4_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f50g_tx_bonding_5_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_f50g_tx_bonding_6_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_0 == ENABLE_25E4X15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_10 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_14 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_2 == ENABLE_25E4X13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_3 == ENABLE_25E4X12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_5 == ENABLE_25E4X10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_6 == ENABLE_25E4X9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_8 == ENABLE_25E4X7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_rx_0 == ENABLE_25E4X15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_rx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_rx_10 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_rx_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_rx_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_rx_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_rx_14 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_rx_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_rx_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_rx_3 == ENABLE_25E4X12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_rx_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_rx_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_rx_6 == ENABLE_25E4X9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_rx_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_rx_8 == ENABLE_25E4X7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_rx_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_tx_0 == ENABLE_25E4X15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_tx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_tx_10 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_tx_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_tx_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_tx_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_tx_14 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_tx_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_tx_2 == ENABLE_25E4X13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_tx_3 == ENABLE_25E4X12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_tx_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_tx_5 == ENABLE_25E4X10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_tx_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_tx_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_tx_8 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_e400g_ux_tx_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_rx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_rx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_rx_10 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_rx_11 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_rx_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_rx_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_rx_14 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_rx_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_rx_16 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_rx_17 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_rx_18 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_rx_19 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_rx_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_rx_20 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_rx_21 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_rx_22 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_rx_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_rx_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_rx_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_rx_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_rx_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_rx_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_rx_8 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_rx_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_tx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_tx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_tx_10 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_tx_11 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_tx_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_tx_13 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_tx_14 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_tx_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_tx_16 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_tx_17 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_tx_18 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_tx_19 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_tx_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_tx_20 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_tx_21 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_tx_22 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_tx_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_tx_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_tx_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_tx_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_tx_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_tx_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_tx_8 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_maib_hdpldadapt_tx_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_pcie_syspll == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ptp_10 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ptp_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ptp_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ptp_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ptp_14 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ptp_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ptp_16 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ptp_17 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ptp_18 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ptp_19 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ptp_20 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ptp_21 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ptp_22 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ptp_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ptp_8 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ptp_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ptp_pairing == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_0_refclk == REF_CLK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_1_refclk == REF_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_2_refclk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e200g_stream_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e200g_stream_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e200g_stream_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e200g_stream_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e200g_stream_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e200g_stream_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e200g_stream_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e200g_stream_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e200g_stream_rx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e200g_stream_rx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e200g_stream_rx_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e200g_stream_rx_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e200g_stream_rx_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e200g_stream_rx_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e200g_stream_rx_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e200g_stream_rx_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e200g_stream_tx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e200g_stream_tx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e200g_stream_tx_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e200g_stream_tx_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e200g_stream_tx_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e200g_stream_tx_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e200g_stream_tx_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e200g_stream_tx_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_10 == SYSPLL_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_12 == SYSPLL_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_13 == SYSPLL_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_14 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_15 == SYSPLL_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_7 == SYSPLL_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_8 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_9 == SYSPLL_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_rx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_rx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_rx_10 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_rx_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_rx_12 == SYSPLL_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_rx_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_rx_14 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_rx_15 == SYSPLL_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_rx_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_rx_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_rx_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_rx_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_rx_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_rx_7 == SYSPLL_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_rx_8 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_rx_9 == SYSPLL_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_tx_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_tx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_tx_10 == SYSPLL_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_tx_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_tx_12 == SYSPLL_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_tx_13 == SYSPLL_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_tx_14 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_tx_15 == SYSPLL_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_tx_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_tx_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_tx_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_tx_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_tx_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_tx_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_tx_8 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_syspll_e400g_stream_tx_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_topology == UX16E400GPTP_XX_DISABLED_XX_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_0 == E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_10 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_14 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_2 == E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_3 == E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_5 == E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_6 == E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_8 == E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_12ch_rx_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_12ch_rx_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_12ch_tx_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_12ch_tx_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_16ch_rx_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_16ch_tx_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_2ch_rx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_2ch_rx_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_2ch_rx_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_2ch_rx_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_2ch_rx_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_2ch_rx_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_2ch_rx_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_2ch_rx_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_2ch_tx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_2ch_tx_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_2ch_tx_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_2ch_tx_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_2ch_tx_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_2ch_tx_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_2ch_tx_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_2ch_tx_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_4ch_rx_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_4ch_rx_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_4ch_rx_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_4ch_rx_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_4ch_tx_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_4ch_tx_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_4ch_tx_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_4ch_tx_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_6ch_rx_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_6ch_rx_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_6ch_rx_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_6ch_rx_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_6ch_rx_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_6ch_tx_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_6ch_tx_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_6ch_tx_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_6ch_tx_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_6ch_tx_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_8ch_rx_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_8ch_rx_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_8ch_rx_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_8ch_tx_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_8ch_tx_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_bundle_8ch_tx_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_dpma_refclk_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_dpma_refclk_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_dpma_refclk_10 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_dpma_refclk_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_dpma_refclk_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_dpma_refclk_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_dpma_refclk_14 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_dpma_refclk_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_dpma_refclk_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_dpma_refclk_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_dpma_refclk_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_dpma_refclk_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_dpma_refclk_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_dpma_refclk_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_dpma_refclk_8 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_dpma_refclk_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_duplex_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_duplex_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_duplex_10 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_duplex_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_duplex_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_duplex_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_duplex_14 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_duplex_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_duplex_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_duplex_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_duplex_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_duplex_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_duplex_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_duplex_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_duplex_8 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_duplex_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_refclk_global_q1b_passthru_refclkin == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_refclk_global_q1t_passthru_refclkin == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_refclk_global_q2b_passthru_refclkin == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_refclk_global_q2t_passthru_refclkin == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_refclk_regional_q0b_passthru_refclkin == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_refclk_regional_q0t_passthru_refclkin == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_refclk_regional_q3b_passthru_refclkin == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_refclk_regional_q3t_passthru_refclkin == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_0 == E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_10 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_14 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_3 == E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_6 == E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_8 == E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_bonding_10_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_bonding_11_10 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_bonding_12_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_bonding_13_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_bonding_14_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_bonding_15_14 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_bonding_1_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_bonding_2_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_bonding_3_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_bonding_4_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_bonding_5_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_bonding_6_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_bonding_7_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_bonding_8_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_bonding_9_8 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_dpma_refclk_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_dpma_refclk_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_dpma_refclk_10 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_dpma_refclk_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_dpma_refclk_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_dpma_refclk_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_dpma_refclk_14 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_dpma_refclk_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_dpma_refclk_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_dpma_refclk_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_dpma_refclk_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_dpma_refclk_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_dpma_refclk_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_dpma_refclk_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_dpma_refclk_8 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_dpma_refclk_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_rx_cdr_divclk_10 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_rx_cdr_divclk_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_rx_cdr_divclk_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_rx_cdr_divclk_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_rx_cdr_divclk_14 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_rx_cdr_divclk_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_rx_cdr_divclk_8 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_rx_cdr_divclk_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_rx_cdr_refclk_0 == GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_rx_cdr_refclk_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_rx_cdr_refclk_10 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_rx_cdr_refclk_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_rx_cdr_refclk_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_rx_cdr_refclk_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_rx_cdr_refclk_14 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_rx_cdr_refclk_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_rx_cdr_refclk_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_rx_cdr_refclk_3 == GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_rx_cdr_refclk_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_rx_cdr_refclk_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_rx_cdr_refclk_6 == GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_rx_cdr_refclk_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_rx_cdr_refclk_8 == GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_rx_rx_cdr_refclk_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_0 == E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_10 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_14 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_2 == E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_3 == E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_5 == E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_8 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_bonding_10_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_bonding_11_10 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_bonding_12_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_bonding_13_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_bonding_14_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_bonding_15_14 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_bonding_1_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_bonding_2_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_bonding_3_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_bonding_4_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_bonding_5_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_bonding_6_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_bonding_7_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_bonding_8_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_bonding_9_8 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_core_pll_refclk_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_core_pll_refclk_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_core_pll_refclk_10 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_core_pll_refclk_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_core_pll_refclk_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_core_pll_refclk_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_core_pll_refclk_14 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_core_pll_refclk_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_core_pll_refclk_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_core_pll_refclk_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_core_pll_refclk_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_core_pll_refclk_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_core_pll_refclk_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_core_pll_refclk_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_core_pll_refclk_8 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_core_pll_refclk_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_dpma_refclk_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_dpma_refclk_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_dpma_refclk_10 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_dpma_refclk_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_dpma_refclk_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_dpma_refclk_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_dpma_refclk_14 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_dpma_refclk_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_dpma_refclk_2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_dpma_refclk_3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_dpma_refclk_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_dpma_refclk_5 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_dpma_refclk_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_dpma_refclk_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_dpma_refclk_8 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_dpma_refclk_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_tx_pll_refclk_0 == GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_tx_pll_refclk_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_tx_pll_refclk_10 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_tx_pll_refclk_11 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_tx_pll_refclk_12 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_tx_pll_refclk_13 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_tx_pll_refclk_14 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_tx_pll_refclk_15 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_tx_pll_refclk_2 == GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_tx_pll_refclk_3 == GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_tx_pll_refclk_4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_tx_pll_refclk_5 == GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_tx_pll_refclk_6 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_tx_pll_refclk_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_tx_pll_refclk_8 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.sw_ux_tx_tx_pll_refclk_9 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[0].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[0].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[0].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[0].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[1].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[1].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[1].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[1].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[1].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[2].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[2].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[2].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[2].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[2].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[3].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[3].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[3].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[3].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[3].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[4].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[4].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[4].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[4].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[4].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[5].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[5].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[5].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[5].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[5].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[6].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[6].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[6].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[6].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[6].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[7].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[7].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[7].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[7].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[7].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[8].aib_rx_data_link_net_id == 32'd27
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[8].avmm1_link_net_id == 32'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[8].bbi_id == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[8].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[8].ip_data_link_net_id == 32'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[9].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[9].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[9].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[9].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[9].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[10].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[10].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[10].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[10].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[10].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[11].aib_rx_data_link_net_id == 32'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[11].avmm1_link_net_id == 32'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[11].bbi_id == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[11].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[11].ip_data_link_net_id == 32'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[12].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[12].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[12].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[12].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[12].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[13].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[13].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[13].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[13].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[13].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[14].aib_rx_data_link_net_id == 32'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[14].avmm1_link_net_id == 32'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[14].bbi_id == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[14].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[14].ip_data_link_net_id == 32'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[15].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[15].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[15].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[15].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[15].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[16].aib_rx_data_link_net_id == 32'd17
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[16].avmm1_link_net_id == 32'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[16].bbi_id == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[16].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[16].ip_data_link_net_id == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[17].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[17].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[17].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[17].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[17].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[18].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[18].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[18].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[18].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[18].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[19].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[19].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[19].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[19].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[19].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[20].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[20].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[20].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[20].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[20].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[21].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[21].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[21].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[21].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[21].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[22].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[22].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[22].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[22].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[22].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[23].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[23].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[23].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[23].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_rx[23].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[0].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[0].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[0].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[0].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[1].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[1].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[1].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[1].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[1].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[2].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[2].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[2].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[2].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[2].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[3].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[3].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[3].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[3].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[3].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[4].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[4].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[4].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[4].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[4].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[5].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[5].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[5].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[5].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[5].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[6].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[6].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[6].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[6].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[6].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[7].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[7].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[7].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[7].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[7].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[8].aib_tx_data_link_net_id == 32'd39
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[8].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[8].bbi_id == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[8].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[8].ip_data_link_net_id == 32'd37
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[9].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[9].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[9].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[9].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[9].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[10].aib_tx_data_link_net_id == 32'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[10].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[10].bbi_id == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[10].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[10].ip_data_link_net_id == 32'd29
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[11].aib_tx_data_link_net_id == 32'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[11].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[11].bbi_id == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[11].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[11].ip_data_link_net_id == 32'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[12].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[12].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[12].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[12].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[12].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[13].aib_tx_data_link_net_id == 32'd35
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[13].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[13].bbi_id == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[13].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[13].ip_data_link_net_id == 32'd33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[14].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[14].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[14].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[14].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[14].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[15].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[15].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[15].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[15].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[15].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[16].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[16].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[16].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[16].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[16].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[17].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[17].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[17].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[17].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[17].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[18].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[18].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[18].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[18].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[18].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[19].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[19].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[19].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[19].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[19].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[20].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[20].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[20].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[20].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[20].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[21].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[21].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[21].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[21].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[21].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[22].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[22].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[22].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[22].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[22].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[23].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[23].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[23].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[23].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.aib_tx[23].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk[0].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk[0].bbi_id == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk[0].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk[0].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk[0].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk[0].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk[0].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk[0].xcvr_data2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk[0].xcvr_data3_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk[1].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk[1].bbi_id == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk[1].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk[1].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk[1].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk[1].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk[1].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk[1].xcvr_data2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk[1].xcvr_data3_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk[2].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk[2].bbi_id == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk[2].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk[2].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk[2].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk[2].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk[2].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk[2].xcvr_data2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk[2].xcvr_data3_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk[3].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk[3].bbi_id == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk[3].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk[3].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk[3].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk[3].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk[3].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk[3].xcvr_data2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk[3].xcvr_data3_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk_common_pll_a.bbi_id == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk_common_pll_a.pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk_common_pll_a.refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk_common_pll_b.bbi_id == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk_common_pll_b.pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk_common_pll_b.refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk_refclk1.bbi_id == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk_refclk1.refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk_refclk2.bbi_id == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.bk_refclk2.refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[0].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_rx[1].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[0].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f100g_tx[1].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[0].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_rx[1].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[0].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f150g_tx[1].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_rx[0].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f200g_tx[0].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[0].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[1].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[2].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[3].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[4].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[5].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[6].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_rx[7].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[0].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[1].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[2].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[3].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[4].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[5].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[6].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f25g_tx[7].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[0].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[1].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[2].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_rx[3].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[0].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[1].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[2].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.f50g_tx[3].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[0].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[0].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[0].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[0].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[0].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[1].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[1].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[1].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[1].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[1].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[1].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[2].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[2].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[2].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[2].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[2].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[2].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[3].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[3].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[3].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[3].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[3].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[3].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[4].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[4].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[4].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[4].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[4].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[4].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[5].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[5].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[5].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[5].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[5].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[5].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[6].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[6].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[6].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[6].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[6].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[6].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[7].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[7].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[7].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[7].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[7].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_rx[7].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[0].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[0].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[0].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[0].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[0].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[1].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[1].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[1].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[1].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[1].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[1].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[2].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[2].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[2].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[2].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[2].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[2].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[3].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[3].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[3].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[3].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[3].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[3].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[4].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[4].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[4].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[4].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[4].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[4].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[5].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[5].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[5].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[5].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[5].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[5].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[6].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[6].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[6].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[6].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[6].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[6].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[7].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[7].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[7].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[7].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[7].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e200g.stream_tx[7].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[0].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[1].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[2].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_rx[3].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[0].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[1].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[2].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f100g_tx[3].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[0].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[1].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[2].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_rx[3].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[0].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[1].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[2].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f150g_tx[3].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[0].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_rx[1].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[0].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f200g_tx[1].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[0].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[1].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[2].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[3].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[4].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[5].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[6].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].avmm1_link_net_id == 32'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].bbi_id == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].ip_data_link_0_net_id == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].pll_link_net_id == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].xcvr_data_link_0_net_id == 32'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[7].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[8].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].avmm1_link_net_id == 32'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].bbi_id == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].ip_data_link_0_net_id == 32'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].pll_link_net_id == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].xcvr_data_link_0_net_id == 32'd21
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[9].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[10].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[11].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].avmm1_link_net_id == 32'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].bbi_id == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].ip_data_link_0_net_id == 32'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].pll_link_net_id == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].xcvr_data_link_0_net_id == 32'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[12].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[13].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[14].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].avmm1_link_net_id == 32'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].bbi_id == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].ip_data_link_0_net_id == 32'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].pll_link_net_id == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].xcvr_data_link_0_net_id == 32'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_rx[15].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[0].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[1].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[2].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[3].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[4].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[5].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[6].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[7].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[8].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[9].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].bbi_id == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].ip_data_link_0_net_id == 32'd33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].pll_link_net_id == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].xcvr_data_link_0_net_id == 32'd34
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[10].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[11].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].bbi_id == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].ip_data_link_0_net_id == 32'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].pll_link_net_id == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].xcvr_data_link_0_net_id == 32'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[12].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].bbi_id == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].ip_data_link_0_net_id == 32'd29
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].pll_link_net_id == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].xcvr_data_link_0_net_id == 32'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[13].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[14].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].bbi_id == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].ip_data_link_0_net_id == 32'd37
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].pll_link_net_id == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].xcvr_data_link_0_net_id == 32'd38
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f25g_tx[15].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[0].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_rx[1].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[0].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f300g_tx[1].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_rx[0].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f400g_tx[0].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[0].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[1].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[2].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[3].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[4].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[5].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[6].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_rx[7].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[0].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[1].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[2].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[3].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[4].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[5].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[6].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.f50g_tx[7].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[0].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[0].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[0].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[0].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[0].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[1].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[1].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[1].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[1].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[1].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[1].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[2].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[2].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[2].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[2].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[2].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[2].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[3].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[3].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[3].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[3].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[3].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[3].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[4].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[4].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[4].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[4].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[4].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[4].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[5].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[5].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[5].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[5].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[5].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[5].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[6].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[6].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[6].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[6].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[6].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[6].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[7].avmm1_link_net_id == 32'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[7].ip_data_link_net_id == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[7].pll_link_net_id == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[7].used_by_frac_bbi_id == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[7].xcvr_data_link_net_id == 32'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[7].xcvr_idx == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[8].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[8].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[8].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[8].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[8].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[8].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[9].avmm1_link_net_id == 32'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[9].ip_data_link_net_id == 32'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[9].pll_link_net_id == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[9].used_by_frac_bbi_id == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[9].xcvr_data_link_net_id == 32'd21
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[9].xcvr_idx == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[10].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[10].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[10].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[10].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[10].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[10].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[11].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[11].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[11].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[11].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[11].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[11].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[12].avmm1_link_net_id == 32'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[12].ip_data_link_net_id == 32'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[12].pll_link_net_id == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[12].used_by_frac_bbi_id == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[12].xcvr_data_link_net_id == 32'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[12].xcvr_idx == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[13].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[13].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[13].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[13].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[13].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[13].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[14].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[14].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[14].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[14].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[14].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[14].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[15].avmm1_link_net_id == 32'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[15].ip_data_link_net_id == 32'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[15].pll_link_net_id == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[15].used_by_frac_bbi_id == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[15].xcvr_data_link_net_id == 32'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_rx[15].xcvr_idx == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[0].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[0].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[0].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[0].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[0].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[1].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[1].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[1].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[1].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[1].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[1].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[2].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[2].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[2].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[2].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[2].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[2].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[3].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[3].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[3].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[3].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[3].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[3].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[4].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[4].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[4].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[4].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[4].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[4].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[5].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[5].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[5].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[5].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[5].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[5].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[6].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[6].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[6].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[6].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[6].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[6].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[7].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[7].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[7].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[7].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[7].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[7].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[8].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[8].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[8].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[8].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[8].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[8].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[9].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[9].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[9].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[9].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[9].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[9].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[10].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[10].ip_data_link_net_id == 32'd33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[10].pll_link_net_id == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[10].used_by_frac_bbi_id == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[10].xcvr_data_link_net_id == 32'd34
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[10].xcvr_idx == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[11].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[11].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[11].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[11].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[11].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[11].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[12].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[12].ip_data_link_net_id == 32'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[12].pll_link_net_id == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[12].used_by_frac_bbi_id == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[12].xcvr_data_link_net_id == 32'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[12].xcvr_idx == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[13].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[13].ip_data_link_net_id == 32'd29
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[13].pll_link_net_id == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[13].used_by_frac_bbi_id == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[13].xcvr_data_link_net_id == 32'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[13].xcvr_idx == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[14].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[14].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[14].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[14].used_by_frac_bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[14].xcvr_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[14].xcvr_idx == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[15].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[15].ip_data_link_net_id == 32'd37
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[15].pll_link_net_id == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[15].used_by_frac_bbi_id == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[15].xcvr_data_link_net_id == 32'd38
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.e400g.stream_tx[15].xcvr_idx == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[0].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[1].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[1].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[2].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[2].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[3].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[3].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[4].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[4].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[5].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[5].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[6].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[6].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[7].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[7].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[8].avmm1_link_net_id == 32'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[8].bbi_id == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[9].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[9].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[10].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[10].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[11].avmm1_link_net_id == 32'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[11].bbi_id == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[12].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[12].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[13].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[13].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[14].avmm1_link_net_id == 32'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[14].bbi_id == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[15].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[15].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[16].avmm1_link_net_id == 32'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[16].bbi_id == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[17].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[17].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[18].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[18].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[19].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[19].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[20].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[20].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[21].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[21].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[22].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[22].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[23].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm1[23].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[0].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[0].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[1].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[1].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[2].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[2].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[3].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[3].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[4].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[4].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[5].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[5].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[6].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[6].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[7].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[7].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[8].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[8].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[9].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[9].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[10].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[10].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[11].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[11].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[12].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[12].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[13].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[13].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[14].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[14].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[15].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[15].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[16].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[16].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[17].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[17].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[18].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[18].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[19].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[19].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[20].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[20].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[21].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[21].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[22].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[22].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[23].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_avmm2[23].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[0].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[0].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[0].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[0].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[0].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[1].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[1].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[1].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[1].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[1].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[1].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[2].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[2].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[2].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[2].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[2].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[2].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[3].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[3].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[3].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[3].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[3].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[3].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[4].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[4].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[4].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[4].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[4].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[4].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[5].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[5].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[5].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[5].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[5].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[5].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[6].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[6].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[6].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[6].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[6].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[6].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[7].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[7].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[7].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[7].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[7].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[7].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[8].adapt_rx_data_link_net_id == 32'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[8].avmm1_link_net_id == 32'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[8].bbi_id == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[8].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[8].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[8].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[9].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[9].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[9].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[9].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[9].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[9].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[10].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[10].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[10].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[10].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[10].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[10].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[11].adapt_rx_data_link_net_id == 32'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[11].avmm1_link_net_id == 32'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[11].bbi_id == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[11].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[11].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[11].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[12].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[12].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[12].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[12].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[12].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[12].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[13].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[13].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[13].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[13].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[13].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[13].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[14].adapt_rx_data_link_net_id == 32'd23
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[14].avmm1_link_net_id == 32'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[14].bbi_id == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[14].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[14].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[14].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[15].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[15].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[15].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[15].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[15].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[15].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[16].adapt_rx_data_link_net_id == 32'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[16].avmm1_link_net_id == 32'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[16].bbi_id == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[16].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[16].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[16].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[17].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[17].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[17].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[17].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[17].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[17].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[18].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[18].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[18].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[18].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[18].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[18].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[19].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[19].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[19].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[19].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[19].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[19].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[20].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[20].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[20].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[20].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[20].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[20].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[21].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[21].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[21].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[21].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[21].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[21].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[22].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[22].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[22].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[22].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[22].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[22].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[23].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[23].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[23].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[23].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[23].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_rx[23].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[0].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[0].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[1].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[1].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[1].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[2].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[2].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[2].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[3].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[3].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[3].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[4].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[4].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[4].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[5].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[5].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[5].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[6].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[6].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[6].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[7].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[7].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[7].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[8].adapt_tx_data_link_net_id == 32'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[8].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[8].bbi_id == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[9].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[9].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[9].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[10].adapt_tx_data_link_net_id == 32'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[10].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[10].bbi_id == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[11].adapt_tx_data_link_net_id == 32'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[11].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[11].bbi_id == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[12].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[12].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[12].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[13].adapt_tx_data_link_net_id == 32'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[13].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[13].bbi_id == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[14].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[14].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[14].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[15].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[15].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[15].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[16].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[16].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[16].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[17].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[17].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[17].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[18].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[18].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[18].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[19].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[19].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[19].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[20].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[20].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[20].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[21].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[21].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[21].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[22].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[22].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[22].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[23].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[23].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.hdpldadapt_tx[23].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[0].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[0].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[0].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[1].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[1].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[1].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[1].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[2].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[2].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[2].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[2].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[3].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[3].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[3].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[3].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[4].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[4].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[4].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[4].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[5].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[5].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[5].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[5].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[6].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[6].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[6].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[6].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[7].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[7].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[7].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[7].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[8].adapt_rx_data_link_net_id == 32'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[8].aib_rx_data_link_net_id == 32'd27
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[8].avmm1_link_net_id == 32'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[8].bbi_id == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[9].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[9].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[9].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[9].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[10].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[10].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[10].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[10].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[11].adapt_rx_data_link_net_id == 32'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[11].aib_rx_data_link_net_id == 32'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[11].avmm1_link_net_id == 32'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[11].bbi_id == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[12].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[12].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[12].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[12].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[13].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[13].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[13].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[13].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[14].adapt_rx_data_link_net_id == 32'd23
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[14].aib_rx_data_link_net_id == 32'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[14].avmm1_link_net_id == 32'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[14].bbi_id == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[15].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[15].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[15].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[15].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[16].adapt_rx_data_link_net_id == 32'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[16].aib_rx_data_link_net_id == 32'd17
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[16].avmm1_link_net_id == 32'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[16].bbi_id == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[17].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[17].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[17].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[17].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[18].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[18].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[18].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[18].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[19].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[19].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[19].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[19].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[20].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[20].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[20].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[20].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[21].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[21].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[21].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[21].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[22].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[22].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[22].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[22].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[23].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[23].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[23].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_rx[23].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[0].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[0].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[0].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[1].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[1].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[1].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[1].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[2].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[2].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[2].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[2].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[3].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[3].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[3].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[3].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[4].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[4].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[4].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[4].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[5].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[5].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[5].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[5].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[6].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[6].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[6].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[6].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[7].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[7].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[7].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[7].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[8].adapt_tx_data_link_net_id == 32'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[8].aib_tx_data_link_net_id == 32'd39
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[8].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[8].bbi_id == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[9].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[9].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[9].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[9].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[10].adapt_tx_data_link_net_id == 32'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[10].aib_tx_data_link_net_id == 32'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[10].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[10].bbi_id == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[11].adapt_tx_data_link_net_id == 32'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[11].aib_tx_data_link_net_id == 32'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[11].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[11].bbi_id == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[12].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[12].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[12].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[12].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[13].adapt_tx_data_link_net_id == 32'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[13].aib_tx_data_link_net_id == 32'd35
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[13].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[13].bbi_id == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[14].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[14].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[14].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[14].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[15].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[15].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[15].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[15].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[16].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[16].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[16].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[16].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[17].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[17].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[17].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[17].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[18].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[18].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[18].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[18].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[19].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[19].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[19].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[19].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[20].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[20].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[20].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[20].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[21].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[21].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[21].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[21].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[22].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[22].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[22].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[22].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[23].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[23].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[23].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.maib_tx[23].bbi_id == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].avmm2_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].avmm2_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].avmm2_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].avmm2_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].bbi_id == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].ip_data_link_16_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].ip_data_link_17_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].ip_data_link_18_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].ip_data_link_19_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].ip_data_link_20_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].ip_data_link_21_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].ip_data_link_22_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].ip_data_link_23_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.pcie[0].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.system_pll[0].bbi_id == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.system_pll[0].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.system_pll[0].refclk_link_net_id == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.system_pll[1].bbi_id == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.system_pll[1].pll_link_net_id == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.system_pll[1].refclk_link_net_id == 32'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.system_pll[2].bbi_id == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.system_pll[2].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.system_pll[2].refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_global_q1b.bbi_id == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_global_q1b.passthru_refclkin_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_global_q1b.refclk_link_net_id == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_global_q1b.rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_global_q1t.bbi_id == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_global_q1t.passthru_refclkin_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_global_q1t.refclk_link_net_id == 32'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_global_q1t.rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_global_q2b.bbi_id == 6'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_global_q2b.passthru_refclkin_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_global_q2b.refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_global_q2b.rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_global_q2t.bbi_id == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_global_q2t.passthru_refclkin_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_global_q2t.refclk_link_net_id == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_global_q2t.rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_local_q2.bbi_id == 6'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_local_q2.passthru_refclkin_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_local_q2.refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_local_q2.rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_local_q3.bbi_id == 6'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_local_q3.passthru_refclkin_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_local_q3.refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_local_q3.rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_regional_q0b.bbi_id == 6'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_regional_q0b.passthru_refclkin_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_regional_q0b.refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_regional_q0b.rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_regional_q0t.bbi_id == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_regional_q0t.passthru_refclkin_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_regional_q0t.refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_regional_q0t.rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_regional_q3b.bbi_id == 6'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_regional_q3b.passthru_refclkin_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_regional_q3b.refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_regional_q3b.rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_regional_q3t.bbi_id == 6'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_regional_q3t.passthru_refclkin_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_regional_q3t.refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_refclk_regional_q3t.rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[0].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[0].bbi_id == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[0].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[0].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[0].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[0].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[0].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[0].rx_cdr_refclk_link_net_id == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[0].xcvr_data0_link_net_id == 32'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[0].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[1].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[1].bbi_id == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[1].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[1].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[1].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[1].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[1].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[1].rx_cdr_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[1].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[1].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[2].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[2].bbi_id == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[2].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[2].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[2].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[2].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[2].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[2].rx_cdr_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[2].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[2].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[3].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[3].bbi_id == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[3].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[3].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[3].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[3].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[3].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[3].rx_cdr_refclk_link_net_id == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[3].xcvr_data0_link_net_id == 32'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[3].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[4].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[4].bbi_id == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[4].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[4].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[4].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[4].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[4].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[4].rx_cdr_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[4].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[4].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[5].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[5].bbi_id == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[5].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[5].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[5].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[5].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[5].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[5].rx_cdr_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[5].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[5].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[6].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[6].bbi_id == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[6].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[6].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[6].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[6].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[6].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[6].rx_cdr_refclk_link_net_id == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[6].xcvr_data0_link_net_id == 32'd21
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[6].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[7].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[7].bbi_id == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[7].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[7].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[7].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[7].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[7].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[7].rx_cdr_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[7].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[7].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[8].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[8].bbi_id == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[8].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[8].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[8].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[8].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[8].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[8].rx_cdr_refclk_link_net_id == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[8].xcvr_data0_link_net_id == 32'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[8].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[9].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[9].bbi_id == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[9].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[9].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[9].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[9].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[9].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[9].rx_cdr_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[9].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[9].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[10].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[10].bbi_id == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[10].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[10].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[10].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[10].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[10].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[10].rx_cdr_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[10].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[10].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[11].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[11].bbi_id == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[11].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[11].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[11].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[11].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[11].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[11].rx_cdr_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[11].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[11].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[12].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[12].bbi_id == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[12].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[12].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[12].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[12].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[12].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[12].rx_cdr_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[12].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[12].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[13].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[13].bbi_id == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[13].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[13].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[13].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[13].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[13].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[13].rx_cdr_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[13].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[13].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[14].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[14].bbi_id == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[14].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[14].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[14].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[14].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[14].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[14].rx_cdr_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[14].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[14].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[15].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[15].bbi_id == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[15].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[15].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[15].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[15].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[15].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[15].rx_cdr_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[15].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_rx[15].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[0].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[0].bbi_id == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[0].core_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[0].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[0].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[0].lc_cascade_out_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[0].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[0].passthru_refclkout_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[0].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[0].tx_pll_refclk_link_net_id == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[0].xcvr_data0_link_net_id == 32'd38
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[0].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[1].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[1].bbi_id == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[1].core_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[1].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[1].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[1].lc_cascade_out_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[1].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[1].passthru_refclkout_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[1].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[1].tx_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[1].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[1].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[2].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[2].bbi_id == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[2].core_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[2].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[2].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[2].lc_cascade_out_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[2].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[2].passthru_refclkout_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[2].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[2].tx_pll_refclk_link_net_id == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[2].xcvr_data0_link_net_id == 32'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[2].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[3].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[3].bbi_id == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[3].core_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[3].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[3].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[3].lc_cascade_out_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[3].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[3].passthru_refclkout_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[3].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[3].tx_pll_refclk_link_net_id == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[3].xcvr_data0_link_net_id == 32'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[3].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[4].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[4].bbi_id == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[4].core_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[4].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[4].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[4].lc_cascade_out_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[4].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[4].passthru_refclkout_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[4].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[4].tx_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[4].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[4].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[5].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[5].bbi_id == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[5].core_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[5].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[5].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[5].lc_cascade_out_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[5].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[5].passthru_refclkout_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[5].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[5].tx_pll_refclk_link_net_id == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[5].xcvr_data0_link_net_id == 32'd34
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[5].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[6].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[6].bbi_id == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[6].core_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[6].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[6].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[6].lc_cascade_out_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[6].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[6].passthru_refclkout_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[6].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[6].tx_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[6].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[6].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[7].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[7].bbi_id == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[7].core_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[7].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[7].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[7].lc_cascade_out_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[7].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[7].passthru_refclkout_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[7].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[7].tx_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[7].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[7].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[8].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[8].bbi_id == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[8].core_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[8].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[8].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[8].lc_cascade_out_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[8].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[8].passthru_refclkout_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[8].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[8].tx_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[8].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[8].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[9].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[9].bbi_id == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[9].core_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[9].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[9].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[9].lc_cascade_out_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[9].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[9].passthru_refclkout_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[9].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[9].tx_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[9].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[9].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[10].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[10].bbi_id == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[10].core_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[10].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[10].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[10].lc_cascade_out_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[10].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[10].passthru_refclkout_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[10].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[10].tx_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[10].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[10].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[11].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[11].bbi_id == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[11].core_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[11].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[11].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[11].lc_cascade_out_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[11].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[11].passthru_refclkout_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[11].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[11].tx_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[11].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[11].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[12].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[12].bbi_id == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[12].core_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[12].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[12].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[12].lc_cascade_out_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[12].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[12].passthru_refclkout_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[12].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[12].tx_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[12].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[12].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[13].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[13].bbi_id == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[13].core_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[13].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[13].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[13].lc_cascade_out_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[13].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[13].passthru_refclkout_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[13].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[13].tx_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[13].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[13].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[14].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[14].bbi_id == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[14].core_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[14].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[14].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[14].lc_cascade_out_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[14].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[14].passthru_refclkout_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[14].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[14].tx_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[14].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[14].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[15].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[15].bbi_id == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[15].core_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[15].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[15].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[15].lc_cascade_out_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[15].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[15].passthru_refclkout_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[15].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[15].tx_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[15].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.as.ux_tx[15].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xavmm1.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xavmm1.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xavmm1.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xavmm2.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xavmm2.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xavmm2.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_ber_margining_ctrl == AIB_BER_MARGINING_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_hps_ctrl_en == AIB_DLLSTR_ALIGN_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.aib_red_shift_en == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.op_mode == RX_DLL_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_HIGH_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr3 == AIB_DATASEL3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_red_pout_shiften == AIB_RED_POUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_tx_clkdiv == AIB_TX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp == AIB_TX_DCC_BYP_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp_iocsr_unused == AIB_TX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal == AIB_TX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal_iocsr_unused == AIB_TX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft == AIB_TX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft_sel == AIB_TX_DCC_DFT_MODE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_dft_sel == AIB_TX_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_entest == AIB_TX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctl_static == AIB_TX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctlsel == AIB_TX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en == AIB_TX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en_iocsr_unused == AIB_TX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_dn == AIB_TX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_up == AIB_TX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_rst_prgmnvrt == AIB_TX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_dn_prgmnvrt == AIB_TX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_up_prgmnvrt == AIB_TX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_updnen == AIB_TX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dftmuxsel == AIB_TX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dly_pst == AIB_TX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_en == AIB_TX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_hps_ctrl_en == AIB_TX_DCC_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_lockreq_muxsel == AIB_TX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_new_dll == AIB_TX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_rst == AIB_TX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_test_clk_pll_en_n == AIB_TX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_tx_halfcode == AIB_TX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.aib_tx_selflock == AIB_TX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.op_mode == TX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_HIGH_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_0.xaibnd_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.aib_fabric_pma_aib_tx_clk_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.aib_fabric_rx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.aib_fabric_rx_transfer_clk_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.aib_fabric_tx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.csr_clk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.pld_avmm1_clk_rowclk_hz == 31'd35996493
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.pld_rx_clk1_dcm_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.pld_rx_clk1_rowclk_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.pld_tx_clk1_dcm_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.pld_tx_clk1_rowclk_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.pld_tx_clk2_dcm_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.pld_tx_clk2_rowclk_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.speed_grade == DASH_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.adapter_base_addr == 10'd768
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_read == AVMM1_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_write == AVMM1_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.avmm1_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.avmm1_nfhssi_calibratio_feature_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_dft_broadcast_en == DISABLE_ONLY_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_force_mdio_dis_csr_ctrl == DISABLE_ONLY_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.avmm1_read_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.avmm1_uc_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_read == AVMM2_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_write == AVMM2_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.avmm2_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.avmm2_hip_sel == AVMM2_FOR_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.nfhssi_base_addr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_RX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_RX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.asn_bypass_pma_pcie_sw_done == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.asn_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_dll_reset_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_fifo_flush_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_pma_pcie_sw_done_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.duplex_mode == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.dv_mode == DV_MODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_double_read == FIFO_DOUBLE_READ_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_ins_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_sel == FIFO_RD_CLK_PLD_RX_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_del_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_sel == FIFO_WR_CLK_RX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rst_sm_dis == ENABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel1 == PMA_CLKS_OR_TXFIFORD_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel2 == PMA_CLKS_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel2 == PMA_CLKS_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_sel == DELAY_PATH3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.pma_hclk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_pld_rx_clk1_dcm == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_wren == WREN_DS_DEL_US_DEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_power_mode == FULL_WIDTH_PS_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_ctrl == BLKLOCK_IGNORE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_8g_eidleinfersel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_eye_monitor_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_pcie_switch_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_reser_out_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.rx_prbs_flags_sr_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.rx_true_b2b == B2B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.rx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_empty == EMPTY_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_full == FULL_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_mode == RXPHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pempty == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pfull == 6'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.rxfiford_post_ct_sel == RXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifowr_post_ct_sel == RXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.sclk_sel == SCLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.txfiford_post_ct_sel == TXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.txfifowr_post_ct_sel == TXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.word_align == WA_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_rx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_sr.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_sr.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_sr.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_sr.sr_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_sr.sr_testbus_sel == SSR_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_TX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_TX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.duplex_mode == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.dv_bond == DV_BOND_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.dv_gen == DV_GEN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_frm_gen_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_sel == FIFO_RD_PMA_AIB_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.fpll_shared_direct_async_in_sel == FPLL_SHARED_DIRECT_ASYNC_IN_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_burst == FRMGEN_BURST_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_bypass == FRMGEN_BYPASS_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_mfrm_length == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pipeln == FRMGEN_PIPELN_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pyld_ins == FRMGEN_PYLD_INS_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_wordslip == FRMGEN_WORDSLIP_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rst_sm_dis == ENABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_sel == DELAY_PATH3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk2_sel == PLD_CLK2_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.pma_aib_tx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_pld_tx_clk1_dcm == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.sh_err == SH_ERR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.tx_datapath_tb_sel == TX_FIFO_TB1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_wren == WREN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_power_mode == FULL_WIDTH_PS_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.tx_hip_aib_ssr_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_10g_tx_bitslip_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_8g_tx_boundary_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_cnt_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_num_phase_shifts_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.tx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_full == FULL_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_mode == TXPHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pfull == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u10_2.hdpldadapt.hdpldadapt_tx_chnl.word_mark == WM_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xavmm1.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xavmm1.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xavmm1.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xavmm2.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xavmm2.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xavmm2.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_ber_margining_ctrl == AIB_BER_MARGINING_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_hps_ctrl_en == AIB_DLLSTR_ALIGN_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.aib_red_shift_en == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.op_mode == RX_DLL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr3 == AIB_DATASEL3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_red_pout_shiften == AIB_RED_POUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_tx_clkdiv == AIB_TX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp == AIB_TX_DCC_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp_iocsr_unused == AIB_TX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal == AIB_TX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal_iocsr_unused == AIB_TX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft == AIB_TX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft_sel == AIB_TX_DCC_DFT_MODE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_dft_sel == AIB_TX_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_entest == AIB_TX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctl_static == AIB_TX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctlsel == AIB_TX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en == AIB_TX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en_iocsr_unused == AIB_TX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_dn == AIB_TX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_up == AIB_TX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_rst_prgmnvrt == AIB_TX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_dn_prgmnvrt == AIB_TX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_up_prgmnvrt == AIB_TX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_updnen == AIB_TX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dftmuxsel == AIB_TX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dly_pst == AIB_TX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_en == AIB_TX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_hps_ctrl_en == AIB_TX_DCC_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_lockreq_muxsel == AIB_TX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_new_dll == AIB_TX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_rst == AIB_TX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_test_clk_pll_en_n == AIB_TX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_tx_halfcode == AIB_TX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.aib_tx_selflock == AIB_TX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.op_mode == TX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_0.xaibnd_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.aib_fabric_pma_aib_tx_clk_hz == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.aib_fabric_rx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.aib_fabric_rx_transfer_clk_hz == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.aib_fabric_tx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.csr_clk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.speed_grade == DASH_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.adapter_base_addr == 10'd768
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_read == AVMM1_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_write == AVMM1_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.avmm1_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.avmm1_nfhssi_calibratio_feature_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_dft_broadcast_en == DISABLE_ONLY_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_force_mdio_dis_csr_ctrl == DISABLE_ONLY_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.avmm1_read_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.avmm1_uc_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_read == AVMM2_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_write == AVMM2_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.avmm2_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.avmm2_hip_sel == AVMM2_FOR_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.nfhssi_base_addr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_RX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_RX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.asn_bypass_pma_pcie_sw_done == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.asn_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_dll_reset_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_fifo_flush_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_pma_pcie_sw_done_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.dv_mode == DV_MODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_double_read == FIFO_DOUBLE_READ_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_ins_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_sel == FIFO_RD_CLK_PLD_RX_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_del_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_sel == FIFO_WR_CLK_RX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rst_sm_dis == ENABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel1 == PMA_CLKS_OR_TXFIFORD_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel2 == PMA_CLKS_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel2 == PMA_CLKS_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_sel == DELAY_PATH3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.pma_hclk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_pld_rx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_wren == WREN_DS_DEL_US_DEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_power_mode == FULL_WIDTH_PS_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_ctrl == BLKLOCK_IGNORE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_8g_eidleinfersel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_eye_monitor_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_pcie_switch_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_reser_out_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.rx_prbs_flags_sr_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.rx_true_b2b == B2B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.rx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_empty == EMPTY_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_full == FULL_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_mode == RXPHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pempty == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pfull == 6'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.rxfiford_post_ct_sel == RXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifowr_post_ct_sel == RXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.sclk_sel == SCLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.txfiford_post_ct_sel == TXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.txfifowr_post_ct_sel == TXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.word_align == WA_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_rx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_sr.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_sr.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_sr.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_sr.sr_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_sr.sr_testbus_sel == SSR_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_TX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_TX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.dv_bond == DV_BOND_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.dv_gen == DV_GEN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_frm_gen_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_sel == FIFO_RD_PMA_AIB_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.fpll_shared_direct_async_in_sel == FPLL_SHARED_DIRECT_ASYNC_IN_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_burst == FRMGEN_BURST_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_bypass == FRMGEN_BYPASS_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_mfrm_length == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pipeln == FRMGEN_PIPELN_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pyld_ins == FRMGEN_PYLD_INS_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_wordslip == FRMGEN_WORDSLIP_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rst_sm_dis == ENABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_sel == DELAY_PATH3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk2_sel == PLD_CLK2_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.pma_aib_tx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_pld_tx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.sh_err == SH_ERR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.tx_datapath_tb_sel == TX_FIFO_TB1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_wren == WREN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_power_mode == FULL_WIDTH_PS_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.tx_hip_aib_ssr_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_10g_tx_bitslip_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_8g_tx_boundary_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_cnt_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_num_phase_shifts_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.tx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_full == FULL_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_mode == TXPHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pfull == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u11_2.hdpldadapt.hdpldadapt_tx_chnl.word_mark == WM_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xavmm1.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xavmm1.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xavmm1.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xavmm2.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xavmm2.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xavmm2.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_ber_margining_ctrl == AIB_BER_MARGINING_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_hps_ctrl_en == AIB_DLLSTR_ALIGN_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.aib_red_shift_en == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.op_mode == RX_DLL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr3 == AIB_DATASEL3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_red_pout_shiften == AIB_RED_POUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_tx_clkdiv == AIB_TX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp == AIB_TX_DCC_BYP_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp_iocsr_unused == AIB_TX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal == AIB_TX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal_iocsr_unused == AIB_TX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft == AIB_TX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft_sel == AIB_TX_DCC_DFT_MODE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_dft_sel == AIB_TX_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_entest == AIB_TX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctl_static == AIB_TX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctlsel == AIB_TX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en == AIB_TX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en_iocsr_unused == AIB_TX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_dn == AIB_TX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_up == AIB_TX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_rst_prgmnvrt == AIB_TX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_dn_prgmnvrt == AIB_TX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_up_prgmnvrt == AIB_TX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_updnen == AIB_TX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dftmuxsel == AIB_TX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dly_pst == AIB_TX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_en == AIB_TX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_hps_ctrl_en == AIB_TX_DCC_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_lockreq_muxsel == AIB_TX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_new_dll == AIB_TX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_rst == AIB_TX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_test_clk_pll_en_n == AIB_TX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_tx_halfcode == AIB_TX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.aib_tx_selflock == AIB_TX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.op_mode == TX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_HIGH_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_0.xaibnd_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.aib_fabric_pma_aib_tx_clk_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.aib_fabric_rx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.aib_fabric_rx_transfer_clk_hz == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.aib_fabric_tx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.csr_clk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.pld_tx_clk1_dcm_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.pld_tx_clk1_rowclk_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.pld_tx_clk2_dcm_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.pld_tx_clk2_rowclk_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.speed_grade == DASH_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.adapter_base_addr == 10'd768
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_read == AVMM1_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_write == AVMM1_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.avmm1_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.avmm1_nfhssi_calibratio_feature_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_dft_broadcast_en == DISABLE_ONLY_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_force_mdio_dis_csr_ctrl == DISABLE_ONLY_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.avmm1_read_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.avmm1_uc_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_read == AVMM2_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_write == AVMM2_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.avmm2_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.avmm2_hip_sel == AVMM2_FOR_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.nfhssi_base_addr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_RX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_RX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.asn_bypass_pma_pcie_sw_done == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.asn_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_dll_reset_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_fifo_flush_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_pma_pcie_sw_done_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.duplex_mode == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.dv_mode == DV_MODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_double_read == FIFO_DOUBLE_READ_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_ins_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_sel == FIFO_RD_CLK_PLD_RX_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_del_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_sel == FIFO_WR_CLK_RX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rst_sm_dis == ENABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel1 == PMA_CLKS_OR_TXFIFORD_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel2 == PMA_CLKS_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel2 == PMA_CLKS_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_sel == DELAY_PATH3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.pma_hclk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_pld_rx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_wren == WREN_DS_DEL_US_DEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_power_mode == FULL_WIDTH_PS_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_ctrl == BLKLOCK_IGNORE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_8g_eidleinfersel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_eye_monitor_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_pcie_switch_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_reser_out_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.rx_prbs_flags_sr_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.rx_true_b2b == B2B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.rx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_empty == EMPTY_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_full == FULL_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_mode == RXPHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pempty == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pfull == 6'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.rxfiford_post_ct_sel == RXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifowr_post_ct_sel == RXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.sclk_sel == SCLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.txfiford_post_ct_sel == TXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.txfifowr_post_ct_sel == TXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.word_align == WA_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_rx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_sr.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_sr.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_sr.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_sr.sr_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_sr.sr_testbus_sel == SSR_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_TX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_TX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.duplex_mode == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.dv_bond == DV_BOND_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.dv_gen == DV_GEN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_frm_gen_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_sel == FIFO_RD_PMA_AIB_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.fpll_shared_direct_async_in_sel == FPLL_SHARED_DIRECT_ASYNC_IN_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_burst == FRMGEN_BURST_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_bypass == FRMGEN_BYPASS_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_mfrm_length == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pipeln == FRMGEN_PIPELN_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pyld_ins == FRMGEN_PYLD_INS_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_wordslip == FRMGEN_WORDSLIP_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rst_sm_dis == ENABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_sel == DELAY_PATH3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk2_sel == PLD_CLK2_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.pma_aib_tx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_pld_tx_clk1_dcm == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.sh_err == SH_ERR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.tx_datapath_tb_sel == TX_FIFO_TB1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_wren == WREN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_power_mode == FULL_WIDTH_PS_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.tx_hip_aib_ssr_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_10g_tx_bitslip_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_8g_tx_boundary_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_cnt_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_num_phase_shifts_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.tx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_full == FULL_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_mode == TXPHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pfull == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u12_2.hdpldadapt.hdpldadapt_tx_chnl.word_mark == WM_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xavmm1.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xavmm1.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xavmm1.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xavmm2.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xavmm2.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xavmm2.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_ber_margining_ctrl == AIB_BER_MARGINING_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_hps_ctrl_en == AIB_DLLSTR_ALIGN_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.aib_red_shift_en == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.op_mode == RX_DLL_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_HIGH_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr3 == AIB_DATASEL3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_red_pout_shiften == AIB_RED_POUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_tx_clkdiv == AIB_TX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp == AIB_TX_DCC_BYP_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp_iocsr_unused == AIB_TX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal == AIB_TX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal_iocsr_unused == AIB_TX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft == AIB_TX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft_sel == AIB_TX_DCC_DFT_MODE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_dft_sel == AIB_TX_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_entest == AIB_TX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctl_static == AIB_TX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctlsel == AIB_TX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en == AIB_TX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en_iocsr_unused == AIB_TX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_dn == AIB_TX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_up == AIB_TX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_rst_prgmnvrt == AIB_TX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_dn_prgmnvrt == AIB_TX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_up_prgmnvrt == AIB_TX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_updnen == AIB_TX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dftmuxsel == AIB_TX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dly_pst == AIB_TX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_en == AIB_TX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_hps_ctrl_en == AIB_TX_DCC_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_lockreq_muxsel == AIB_TX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_new_dll == AIB_TX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_rst == AIB_TX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_test_clk_pll_en_n == AIB_TX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_tx_halfcode == AIB_TX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.aib_tx_selflock == AIB_TX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.op_mode == TX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_HIGH_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_0.xaibnd_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.aib_fabric_pma_aib_tx_clk_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.aib_fabric_rx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.aib_fabric_rx_transfer_clk_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.aib_fabric_tx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.csr_clk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.pld_avmm1_clk_rowclk_hz == 31'd35996493
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.pld_rx_clk1_dcm_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.pld_rx_clk1_rowclk_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.pld_tx_clk1_dcm_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.pld_tx_clk1_rowclk_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.pld_tx_clk2_dcm_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.pld_tx_clk2_rowclk_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.speed_grade == DASH_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.adapter_base_addr == 10'd768
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_read == AVMM1_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_write == AVMM1_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.avmm1_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.avmm1_nfhssi_calibratio_feature_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_dft_broadcast_en == DISABLE_ONLY_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_force_mdio_dis_csr_ctrl == DISABLE_ONLY_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.avmm1_read_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.avmm1_uc_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_read == AVMM2_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_write == AVMM2_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.avmm2_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.avmm2_hip_sel == AVMM2_FOR_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.nfhssi_base_addr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_RX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_RX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.asn_bypass_pma_pcie_sw_done == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.asn_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_dll_reset_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_fifo_flush_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_pma_pcie_sw_done_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.duplex_mode == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.dv_mode == DV_MODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_double_read == FIFO_DOUBLE_READ_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_ins_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_sel == FIFO_RD_CLK_PLD_RX_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_del_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_sel == FIFO_WR_CLK_RX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rst_sm_dis == ENABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel1 == PMA_CLKS_OR_TXFIFORD_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel2 == PMA_CLKS_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel2 == PMA_CLKS_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_sel == DELAY_PATH3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.pma_hclk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_pld_rx_clk1_dcm == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_wren == WREN_DS_DEL_US_DEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_power_mode == FULL_WIDTH_PS_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_ctrl == BLKLOCK_IGNORE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_8g_eidleinfersel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_eye_monitor_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_pcie_switch_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_reser_out_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.rx_prbs_flags_sr_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.rx_true_b2b == B2B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.rx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_empty == EMPTY_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_full == FULL_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_mode == RXPHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pempty == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pfull == 6'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.rxfiford_post_ct_sel == RXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifowr_post_ct_sel == RXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.sclk_sel == SCLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.txfiford_post_ct_sel == TXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.txfifowr_post_ct_sel == TXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.word_align == WA_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_rx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_sr.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_sr.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_sr.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_sr.sr_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_sr.sr_testbus_sel == SSR_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_TX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_TX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.duplex_mode == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.dv_bond == DV_BOND_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.dv_gen == DV_GEN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_frm_gen_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_sel == FIFO_RD_PMA_AIB_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.fpll_shared_direct_async_in_sel == FPLL_SHARED_DIRECT_ASYNC_IN_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_burst == FRMGEN_BURST_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_bypass == FRMGEN_BYPASS_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_mfrm_length == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pipeln == FRMGEN_PIPELN_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pyld_ins == FRMGEN_PYLD_INS_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_wordslip == FRMGEN_WORDSLIP_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rst_sm_dis == ENABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_sel == DELAY_PATH3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk2_sel == PLD_CLK2_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.pma_aib_tx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_pld_tx_clk1_dcm == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.sh_err == SH_ERR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.tx_datapath_tb_sel == TX_FIFO_TB1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_wren == WREN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_power_mode == FULL_WIDTH_PS_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.tx_hip_aib_ssr_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_10g_tx_bitslip_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_8g_tx_boundary_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_cnt_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_num_phase_shifts_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.tx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_full == FULL_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_mode == TXPHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pfull == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u13_2.hdpldadapt.hdpldadapt_tx_chnl.word_mark == WM_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xavmm1.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xavmm1.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xavmm1.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xavmm2.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xavmm2.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xavmm2.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_ber_margining_ctrl == AIB_BER_MARGINING_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_hps_ctrl_en == AIB_DLLSTR_ALIGN_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.aib_red_shift_en == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.op_mode == RX_DLL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr3 == AIB_DATASEL3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_red_pout_shiften == AIB_RED_POUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_tx_clkdiv == AIB_TX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp == AIB_TX_DCC_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp_iocsr_unused == AIB_TX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal == AIB_TX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal_iocsr_unused == AIB_TX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft == AIB_TX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft_sel == AIB_TX_DCC_DFT_MODE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_dft_sel == AIB_TX_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_entest == AIB_TX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctl_static == AIB_TX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctlsel == AIB_TX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en == AIB_TX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en_iocsr_unused == AIB_TX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_dn == AIB_TX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_up == AIB_TX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_rst_prgmnvrt == AIB_TX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_dn_prgmnvrt == AIB_TX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_up_prgmnvrt == AIB_TX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_updnen == AIB_TX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dftmuxsel == AIB_TX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dly_pst == AIB_TX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_en == AIB_TX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_hps_ctrl_en == AIB_TX_DCC_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_lockreq_muxsel == AIB_TX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_new_dll == AIB_TX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_rst == AIB_TX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_test_clk_pll_en_n == AIB_TX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_tx_halfcode == AIB_TX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.aib_tx_selflock == AIB_TX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.op_mode == TX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_0.xaibnd_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.aib_fabric_pma_aib_tx_clk_hz == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.aib_fabric_rx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.aib_fabric_rx_transfer_clk_hz == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.aib_fabric_tx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.csr_clk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.speed_grade == DASH_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.adapter_base_addr == 10'd768
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_read == AVMM1_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_write == AVMM1_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.avmm1_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.avmm1_nfhssi_calibratio_feature_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_dft_broadcast_en == DISABLE_ONLY_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_force_mdio_dis_csr_ctrl == DISABLE_ONLY_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.avmm1_read_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.avmm1_uc_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_read == AVMM2_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_write == AVMM2_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.avmm2_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.avmm2_hip_sel == AVMM2_FOR_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.nfhssi_base_addr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_RX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_RX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.asn_bypass_pma_pcie_sw_done == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.asn_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_dll_reset_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_fifo_flush_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_pma_pcie_sw_done_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.dv_mode == DV_MODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_double_read == FIFO_DOUBLE_READ_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_ins_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_sel == FIFO_RD_CLK_PLD_RX_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_del_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_sel == FIFO_WR_CLK_RX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rst_sm_dis == ENABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel1 == PMA_CLKS_OR_TXFIFORD_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel2 == PMA_CLKS_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel2 == PMA_CLKS_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_sel == DELAY_PATH3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.pma_hclk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_pld_rx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_wren == WREN_DS_DEL_US_DEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_power_mode == FULL_WIDTH_PS_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_ctrl == BLKLOCK_IGNORE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_8g_eidleinfersel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_eye_monitor_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_pcie_switch_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_reser_out_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.rx_prbs_flags_sr_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.rx_true_b2b == B2B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.rx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_empty == EMPTY_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_full == FULL_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_mode == RXPHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pempty == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pfull == 6'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.rxfiford_post_ct_sel == RXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifowr_post_ct_sel == RXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.sclk_sel == SCLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.txfiford_post_ct_sel == TXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.txfifowr_post_ct_sel == TXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.word_align == WA_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_rx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_sr.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_sr.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_sr.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_sr.sr_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_sr.sr_testbus_sel == SSR_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_TX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_TX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.dv_bond == DV_BOND_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.dv_gen == DV_GEN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_frm_gen_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_sel == FIFO_RD_PMA_AIB_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.fpll_shared_direct_async_in_sel == FPLL_SHARED_DIRECT_ASYNC_IN_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_burst == FRMGEN_BURST_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_bypass == FRMGEN_BYPASS_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_mfrm_length == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pipeln == FRMGEN_PIPELN_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pyld_ins == FRMGEN_PYLD_INS_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_wordslip == FRMGEN_WORDSLIP_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rst_sm_dis == ENABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_sel == DELAY_PATH3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk2_sel == PLD_CLK2_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.pma_aib_tx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_pld_tx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.sh_err == SH_ERR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.tx_datapath_tb_sel == TX_FIFO_TB1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_wren == WREN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_power_mode == FULL_WIDTH_PS_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.tx_hip_aib_ssr_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_10g_tx_bitslip_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_8g_tx_boundary_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_cnt_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_num_phase_shifts_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.tx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_full == FULL_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_mode == TXPHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pfull == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u14_2.hdpldadapt.hdpldadapt_tx_chnl.word_mark == WM_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xavmm1.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xavmm1.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xavmm1.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xavmm2.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xavmm2.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xavmm2.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_ber_margining_ctrl == AIB_BER_MARGINING_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_hps_ctrl_en == AIB_DLLSTR_ALIGN_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.aib_red_shift_en == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.op_mode == RX_DLL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr3 == AIB_DATASEL3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_red_pout_shiften == AIB_RED_POUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_tx_clkdiv == AIB_TX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp == AIB_TX_DCC_BYP_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp_iocsr_unused == AIB_TX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal == AIB_TX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal_iocsr_unused == AIB_TX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft == AIB_TX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft_sel == AIB_TX_DCC_DFT_MODE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_dft_sel == AIB_TX_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_entest == AIB_TX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctl_static == AIB_TX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctlsel == AIB_TX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en == AIB_TX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en_iocsr_unused == AIB_TX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_dn == AIB_TX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_up == AIB_TX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_rst_prgmnvrt == AIB_TX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_dn_prgmnvrt == AIB_TX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_up_prgmnvrt == AIB_TX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_updnen == AIB_TX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dftmuxsel == AIB_TX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dly_pst == AIB_TX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_en == AIB_TX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_hps_ctrl_en == AIB_TX_DCC_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_lockreq_muxsel == AIB_TX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_new_dll == AIB_TX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_rst == AIB_TX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_test_clk_pll_en_n == AIB_TX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_tx_halfcode == AIB_TX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.aib_tx_selflock == AIB_TX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.op_mode == TX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_HIGH_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_0.xaibnd_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.aib_fabric_pma_aib_tx_clk_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.aib_fabric_rx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.aib_fabric_rx_transfer_clk_hz == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.aib_fabric_tx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.csr_clk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.pld_tx_clk1_dcm_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.pld_tx_clk1_rowclk_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.pld_tx_clk2_dcm_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.pld_tx_clk2_rowclk_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.speed_grade == DASH_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.adapter_base_addr == 10'd768
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_read == AVMM1_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_write == AVMM1_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.avmm1_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.avmm1_nfhssi_calibratio_feature_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_dft_broadcast_en == DISABLE_ONLY_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_force_mdio_dis_csr_ctrl == DISABLE_ONLY_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.avmm1_read_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.avmm1_uc_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_read == AVMM2_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_write == AVMM2_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.avmm2_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.avmm2_hip_sel == AVMM2_FOR_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.nfhssi_base_addr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_RX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_RX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.asn_bypass_pma_pcie_sw_done == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.asn_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_dll_reset_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_fifo_flush_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_pma_pcie_sw_done_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.duplex_mode == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.dv_mode == DV_MODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_double_read == FIFO_DOUBLE_READ_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_ins_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_sel == FIFO_RD_CLK_PLD_RX_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_del_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_sel == FIFO_WR_CLK_RX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rst_sm_dis == ENABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel1 == PMA_CLKS_OR_TXFIFORD_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel2 == PMA_CLKS_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel2 == PMA_CLKS_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_sel == DELAY_PATH3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.pma_hclk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_pld_rx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_wren == WREN_DS_DEL_US_DEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_power_mode == FULL_WIDTH_PS_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_ctrl == BLKLOCK_IGNORE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_8g_eidleinfersel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_eye_monitor_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_pcie_switch_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_reser_out_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.rx_prbs_flags_sr_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.rx_true_b2b == B2B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.rx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_empty == EMPTY_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_full == FULL_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_mode == RXPHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pempty == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pfull == 6'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.rxfiford_post_ct_sel == RXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifowr_post_ct_sel == RXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.sclk_sel == SCLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.txfiford_post_ct_sel == TXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.txfifowr_post_ct_sel == TXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.word_align == WA_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_rx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_sr.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_sr.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_sr.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_sr.sr_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_sr.sr_testbus_sel == SSR_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_TX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_TX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.duplex_mode == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.dv_bond == DV_BOND_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.dv_gen == DV_GEN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_frm_gen_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_sel == FIFO_RD_PMA_AIB_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.fpll_shared_direct_async_in_sel == FPLL_SHARED_DIRECT_ASYNC_IN_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_burst == FRMGEN_BURST_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_bypass == FRMGEN_BYPASS_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_mfrm_length == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pipeln == FRMGEN_PIPELN_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pyld_ins == FRMGEN_PYLD_INS_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_wordslip == FRMGEN_WORDSLIP_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rst_sm_dis == ENABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_sel == DELAY_PATH3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk2_sel == PLD_CLK2_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.pma_aib_tx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_pld_tx_clk1_dcm == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.sh_err == SH_ERR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.tx_datapath_tb_sel == TX_FIFO_TB1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_wren == WREN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_power_mode == FULL_WIDTH_PS_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.tx_hip_aib_ssr_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_10g_tx_bitslip_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_8g_tx_boundary_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_cnt_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_num_phase_shifts_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.tx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_full == FULL_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_mode == TXPHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pfull == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u15_2.hdpldadapt.hdpldadapt_tx_chnl.word_mark == WM_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xavmm1.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xavmm1.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xavmm1.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xavmm2.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xavmm2.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xavmm2.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_ber_margining_ctrl == AIB_BER_MARGINING_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_hps_ctrl_en == AIB_DLLSTR_ALIGN_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.aib_red_shift_en == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.op_mode == RX_DLL_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_HIGH_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr3 == AIB_DATASEL3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_red_pout_shiften == AIB_RED_POUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_tx_clkdiv == AIB_TX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp == AIB_TX_DCC_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp_iocsr_unused == AIB_TX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal == AIB_TX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal_iocsr_unused == AIB_TX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft == AIB_TX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft_sel == AIB_TX_DCC_DFT_MODE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_dft_sel == AIB_TX_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_entest == AIB_TX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctl_static == AIB_TX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctlsel == AIB_TX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en == AIB_TX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en_iocsr_unused == AIB_TX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_dn == AIB_TX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_up == AIB_TX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_rst_prgmnvrt == AIB_TX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_dn_prgmnvrt == AIB_TX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_up_prgmnvrt == AIB_TX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_updnen == AIB_TX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dftmuxsel == AIB_TX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dly_pst == AIB_TX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_en == AIB_TX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_hps_ctrl_en == AIB_TX_DCC_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_lockreq_muxsel == AIB_TX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_new_dll == AIB_TX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_rst == AIB_TX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_test_clk_pll_en_n == AIB_TX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_tx_halfcode == AIB_TX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.aib_tx_selflock == AIB_TX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.op_mode == TX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_0.xaibnd_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.aib_fabric_pma_aib_tx_clk_hz == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.aib_fabric_rx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.aib_fabric_rx_transfer_clk_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.aib_fabric_tx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.csr_clk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.pld_avmm1_clk_rowclk_hz == 31'd35996493
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.pld_rx_clk1_dcm_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.pld_rx_clk1_rowclk_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.speed_grade == DASH_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.adapter_base_addr == 10'd768
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_read == AVMM1_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_write == AVMM1_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.avmm1_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.avmm1_nfhssi_calibratio_feature_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_dft_broadcast_en == DISABLE_ONLY_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_force_mdio_dis_csr_ctrl == DISABLE_ONLY_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.avmm1_read_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.avmm1_uc_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_read == AVMM2_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_write == AVMM2_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.avmm2_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.avmm2_hip_sel == AVMM2_FOR_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.nfhssi_base_addr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_RX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_RX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.asn_bypass_pma_pcie_sw_done == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.asn_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_dll_reset_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_fifo_flush_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_pma_pcie_sw_done_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.dv_mode == DV_MODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_double_read == FIFO_DOUBLE_READ_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_ins_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_sel == FIFO_RD_CLK_PLD_RX_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_del_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_sel == FIFO_WR_CLK_RX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rst_sm_dis == ENABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel1 == PMA_CLKS_OR_TXFIFORD_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel2 == PMA_CLKS_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel2 == PMA_CLKS_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_sel == DELAY_PATH3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.pma_hclk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_pld_rx_clk1_dcm == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_wren == WREN_DS_DEL_US_DEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_power_mode == FULL_WIDTH_PS_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_ctrl == BLKLOCK_IGNORE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_8g_eidleinfersel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_eye_monitor_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_pcie_switch_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_reser_out_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.rx_prbs_flags_sr_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.rx_true_b2b == B2B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.rx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_empty == EMPTY_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_full == FULL_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_mode == RXPHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pempty == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pfull == 6'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.rxfiford_post_ct_sel == RXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifowr_post_ct_sel == RXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.sclk_sel == SCLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.txfiford_post_ct_sel == TXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.txfifowr_post_ct_sel == TXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.word_align == WA_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_rx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_sr.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_sr.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_sr.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_sr.sr_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_sr.sr_testbus_sel == SSR_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_TX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_TX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.dv_bond == DV_BOND_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.dv_gen == DV_GEN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_frm_gen_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_sel == FIFO_RD_PMA_AIB_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.fpll_shared_direct_async_in_sel == FPLL_SHARED_DIRECT_ASYNC_IN_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_burst == FRMGEN_BURST_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_bypass == FRMGEN_BYPASS_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_mfrm_length == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pipeln == FRMGEN_PIPELN_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pyld_ins == FRMGEN_PYLD_INS_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_wordslip == FRMGEN_WORDSLIP_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rst_sm_dis == ENABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_sel == DELAY_PATH3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk2_sel == PLD_CLK2_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.pma_aib_tx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_pld_tx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.sh_err == SH_ERR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.tx_datapath_tb_sel == TX_FIFO_TB1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_wren == WREN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_power_mode == FULL_WIDTH_PS_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.tx_hip_aib_ssr_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_10g_tx_bitslip_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_8g_tx_boundary_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_cnt_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_num_phase_shifts_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.tx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_full == FULL_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_mode == TXPHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pfull == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u16_2.hdpldadapt.hdpldadapt_tx_chnl.word_mark == WM_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xavmm1.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xavmm1.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xavmm1.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xavmm2.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xavmm2.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xavmm2.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_ber_margining_ctrl == AIB_BER_MARGINING_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_hps_ctrl_en == AIB_DLLSTR_ALIGN_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.aib_red_shift_en == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.op_mode == RX_DLL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr3 == AIB_DATASEL3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_red_pout_shiften == AIB_RED_POUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_tx_clkdiv == AIB_TX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp == AIB_TX_DCC_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp_iocsr_unused == AIB_TX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal == AIB_TX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal_iocsr_unused == AIB_TX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft == AIB_TX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft_sel == AIB_TX_DCC_DFT_MODE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_dft_sel == AIB_TX_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_entest == AIB_TX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctl_static == AIB_TX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctlsel == AIB_TX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en == AIB_TX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en_iocsr_unused == AIB_TX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_dn == AIB_TX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_up == AIB_TX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_rst_prgmnvrt == AIB_TX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_dn_prgmnvrt == AIB_TX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_up_prgmnvrt == AIB_TX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_updnen == AIB_TX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dftmuxsel == AIB_TX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dly_pst == AIB_TX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_en == AIB_TX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_hps_ctrl_en == AIB_TX_DCC_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_lockreq_muxsel == AIB_TX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_new_dll == AIB_TX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_rst == AIB_TX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_test_clk_pll_en_n == AIB_TX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_tx_halfcode == AIB_TX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.aib_tx_selflock == AIB_TX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.op_mode == TX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_0.xaibnd_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.aib_fabric_pma_aib_tx_clk_hz == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.aib_fabric_rx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.aib_fabric_rx_transfer_clk_hz == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.aib_fabric_tx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.csr_clk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.speed_grade == DASH_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.adapter_base_addr == 10'd768
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_read == AVMM1_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_write == AVMM1_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.avmm1_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.avmm1_nfhssi_calibratio_feature_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_dft_broadcast_en == DISABLE_ONLY_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_force_mdio_dis_csr_ctrl == DISABLE_ONLY_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.avmm1_read_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.avmm1_uc_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_read == AVMM2_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_write == AVMM2_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.avmm2_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.avmm2_hip_sel == AVMM2_FOR_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.nfhssi_base_addr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_RX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_RX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.asn_bypass_pma_pcie_sw_done == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.asn_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_dll_reset_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_fifo_flush_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_pma_pcie_sw_done_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.dv_mode == DV_MODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_double_read == FIFO_DOUBLE_READ_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_ins_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_sel == FIFO_RD_CLK_PLD_RX_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_del_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_sel == FIFO_WR_CLK_RX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rst_sm_dis == ENABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel1 == PMA_CLKS_OR_TXFIFORD_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel2 == PMA_CLKS_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel2 == PMA_CLKS_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_sel == DELAY_PATH3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.pma_hclk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_pld_rx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_wren == WREN_DS_DEL_US_DEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_power_mode == FULL_WIDTH_PS_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_ctrl == BLKLOCK_IGNORE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_8g_eidleinfersel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_eye_monitor_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_pcie_switch_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_reser_out_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.rx_prbs_flags_sr_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.rx_true_b2b == B2B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.rx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_empty == EMPTY_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_full == FULL_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_mode == RXPHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pempty == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pfull == 6'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.rxfiford_post_ct_sel == RXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifowr_post_ct_sel == RXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.sclk_sel == SCLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.txfiford_post_ct_sel == TXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.txfifowr_post_ct_sel == TXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.word_align == WA_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_rx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_sr.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_sr.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_sr.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_sr.sr_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_sr.sr_testbus_sel == SSR_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_TX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_TX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.dv_bond == DV_BOND_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.dv_gen == DV_GEN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_frm_gen_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_sel == FIFO_RD_PMA_AIB_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.fpll_shared_direct_async_in_sel == FPLL_SHARED_DIRECT_ASYNC_IN_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_burst == FRMGEN_BURST_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_bypass == FRMGEN_BYPASS_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_mfrm_length == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pipeln == FRMGEN_PIPELN_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pyld_ins == FRMGEN_PYLD_INS_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_wordslip == FRMGEN_WORDSLIP_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rst_sm_dis == ENABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_sel == DELAY_PATH3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk2_sel == PLD_CLK2_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.pma_aib_tx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_pld_tx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.sh_err == SH_ERR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.tx_datapath_tb_sel == TX_FIFO_TB1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_wren == WREN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_power_mode == FULL_WIDTH_PS_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.tx_hip_aib_ssr_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_10g_tx_bitslip_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_8g_tx_boundary_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_cnt_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_num_phase_shifts_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.tx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_full == FULL_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_mode == TXPHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pfull == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u17_2.hdpldadapt.hdpldadapt_tx_chnl.word_mark == WM_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xavmm1.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xavmm1.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xavmm1.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xavmm2.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xavmm2.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xavmm2.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_ber_margining_ctrl == AIB_BER_MARGINING_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_hps_ctrl_en == AIB_DLLSTR_ALIGN_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.aib_red_shift_en == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.op_mode == RX_DLL_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_HIGH_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr3 == AIB_DATASEL3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_red_pout_shiften == AIB_RED_POUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_tx_clkdiv == AIB_TX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp == AIB_TX_DCC_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp_iocsr_unused == AIB_TX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal == AIB_TX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal_iocsr_unused == AIB_TX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft == AIB_TX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft_sel == AIB_TX_DCC_DFT_MODE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_dft_sel == AIB_TX_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_entest == AIB_TX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctl_static == AIB_TX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctlsel == AIB_TX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en == AIB_TX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en_iocsr_unused == AIB_TX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_dn == AIB_TX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_up == AIB_TX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_rst_prgmnvrt == AIB_TX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_dn_prgmnvrt == AIB_TX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_up_prgmnvrt == AIB_TX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_updnen == AIB_TX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dftmuxsel == AIB_TX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dly_pst == AIB_TX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_en == AIB_TX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_hps_ctrl_en == AIB_TX_DCC_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_lockreq_muxsel == AIB_TX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_new_dll == AIB_TX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_rst == AIB_TX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_test_clk_pll_en_n == AIB_TX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_tx_halfcode == AIB_TX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.aib_tx_selflock == AIB_TX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.op_mode == TX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_0.xaibnd_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.aib_fabric_pma_aib_tx_clk_hz == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.aib_fabric_rx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.aib_fabric_rx_transfer_clk_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.aib_fabric_tx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.csr_clk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.pld_avmm1_clk_rowclk_hz == 31'd35996493
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.pld_rx_clk1_dcm_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.pld_rx_clk1_rowclk_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.speed_grade == DASH_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.adapter_base_addr == 10'd768
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_read == AVMM1_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_write == AVMM1_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.avmm1_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.avmm1_nfhssi_calibratio_feature_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_dft_broadcast_en == DISABLE_ONLY_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_force_mdio_dis_csr_ctrl == DISABLE_ONLY_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.avmm1_read_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.avmm1_uc_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_read == AVMM2_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_write == AVMM2_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.avmm2_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.avmm2_hip_sel == AVMM2_FOR_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.nfhssi_base_addr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_RX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_RX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.asn_bypass_pma_pcie_sw_done == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.asn_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_dll_reset_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_fifo_flush_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_pma_pcie_sw_done_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.dv_mode == DV_MODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_double_read == FIFO_DOUBLE_READ_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_ins_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_sel == FIFO_RD_CLK_PLD_RX_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_del_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_sel == FIFO_WR_CLK_RX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rst_sm_dis == ENABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel1 == PMA_CLKS_OR_TXFIFORD_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel2 == PMA_CLKS_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel2 == PMA_CLKS_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_sel == DELAY_PATH3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.pma_hclk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_pld_rx_clk1_dcm == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_wren == WREN_DS_DEL_US_DEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_power_mode == FULL_WIDTH_PS_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_ctrl == BLKLOCK_IGNORE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_8g_eidleinfersel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_eye_monitor_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_pcie_switch_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_reser_out_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.rx_prbs_flags_sr_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.rx_true_b2b == B2B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.rx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_empty == EMPTY_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_full == FULL_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_mode == RXPHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pempty == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pfull == 6'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.rxfiford_post_ct_sel == RXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifowr_post_ct_sel == RXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.sclk_sel == SCLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.txfiford_post_ct_sel == TXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.txfifowr_post_ct_sel == TXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.word_align == WA_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_rx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_sr.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_sr.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_sr.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_sr.sr_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_sr.sr_testbus_sel == SSR_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_TX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_TX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.dv_bond == DV_BOND_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.dv_gen == DV_GEN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_frm_gen_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_sel == FIFO_RD_PMA_AIB_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.fpll_shared_direct_async_in_sel == FPLL_SHARED_DIRECT_ASYNC_IN_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_burst == FRMGEN_BURST_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_bypass == FRMGEN_BYPASS_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_mfrm_length == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pipeln == FRMGEN_PIPELN_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pyld_ins == FRMGEN_PYLD_INS_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_wordslip == FRMGEN_WORDSLIP_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rst_sm_dis == ENABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_sel == DELAY_PATH3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk2_sel == PLD_CLK2_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.pma_aib_tx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_pld_tx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.sh_err == SH_ERR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.tx_datapath_tb_sel == TX_FIFO_TB1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_wren == WREN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_power_mode == FULL_WIDTH_PS_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.tx_hip_aib_ssr_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_10g_tx_bitslip_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_8g_tx_boundary_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_cnt_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_num_phase_shifts_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.tx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_full == FULL_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_mode == TXPHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pfull == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u18_2.hdpldadapt.hdpldadapt_tx_chnl.word_mark == WM_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xavmm1.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xavmm1.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xavmm1.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xavmm2.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xavmm2.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xavmm2.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_ber_margining_ctrl == AIB_BER_MARGINING_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_hps_ctrl_en == AIB_DLLSTR_ALIGN_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.aib_red_shift_en == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.op_mode == RX_DLL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr3 == AIB_DATASEL3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_red_pout_shiften == AIB_RED_POUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_tx_clkdiv == AIB_TX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp == AIB_TX_DCC_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp_iocsr_unused == AIB_TX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal == AIB_TX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal_iocsr_unused == AIB_TX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft == AIB_TX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft_sel == AIB_TX_DCC_DFT_MODE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_dft_sel == AIB_TX_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_entest == AIB_TX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctl_static == AIB_TX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctlsel == AIB_TX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en == AIB_TX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en_iocsr_unused == AIB_TX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_dn == AIB_TX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_up == AIB_TX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_rst_prgmnvrt == AIB_TX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_dn_prgmnvrt == AIB_TX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_up_prgmnvrt == AIB_TX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_updnen == AIB_TX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dftmuxsel == AIB_TX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dly_pst == AIB_TX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_en == AIB_TX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_hps_ctrl_en == AIB_TX_DCC_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_lockreq_muxsel == AIB_TX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_new_dll == AIB_TX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_rst == AIB_TX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_test_clk_pll_en_n == AIB_TX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_tx_halfcode == AIB_TX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.aib_tx_selflock == AIB_TX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.op_mode == TX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_0.xaibnd_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.aib_fabric_pma_aib_tx_clk_hz == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.aib_fabric_rx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.aib_fabric_rx_transfer_clk_hz == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.aib_fabric_tx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.csr_clk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.speed_grade == DASH_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.adapter_base_addr == 10'd768
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_read == AVMM1_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_write == AVMM1_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.avmm1_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.avmm1_nfhssi_calibratio_feature_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_dft_broadcast_en == DISABLE_ONLY_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_force_mdio_dis_csr_ctrl == DISABLE_ONLY_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.avmm1_read_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.avmm1_uc_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_read == AVMM2_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_write == AVMM2_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.avmm2_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.avmm2_hip_sel == AVMM2_FOR_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.nfhssi_base_addr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_RX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_RX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.asn_bypass_pma_pcie_sw_done == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.asn_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_dll_reset_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_fifo_flush_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_pma_pcie_sw_done_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.dv_mode == DV_MODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_double_read == FIFO_DOUBLE_READ_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_ins_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_sel == FIFO_RD_CLK_PLD_RX_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_del_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_sel == FIFO_WR_CLK_RX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rst_sm_dis == ENABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel1 == PMA_CLKS_OR_TXFIFORD_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel2 == PMA_CLKS_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel2 == PMA_CLKS_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_sel == DELAY_PATH3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.pma_hclk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_pld_rx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_wren == WREN_DS_DEL_US_DEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_power_mode == FULL_WIDTH_PS_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_ctrl == BLKLOCK_IGNORE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_8g_eidleinfersel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_eye_monitor_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_pcie_switch_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_reser_out_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.rx_prbs_flags_sr_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.rx_true_b2b == B2B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.rx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_empty == EMPTY_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_full == FULL_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_mode == RXPHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pempty == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pfull == 6'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.rxfiford_post_ct_sel == RXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifowr_post_ct_sel == RXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.sclk_sel == SCLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.txfiford_post_ct_sel == TXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.txfifowr_post_ct_sel == TXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.word_align == WA_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_rx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_sr.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_sr.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_sr.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_sr.sr_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_sr.sr_testbus_sel == SSR_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_TX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_TX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.dv_bond == DV_BOND_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.dv_gen == DV_GEN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_frm_gen_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_sel == FIFO_RD_PMA_AIB_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.fpll_shared_direct_async_in_sel == FPLL_SHARED_DIRECT_ASYNC_IN_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_burst == FRMGEN_BURST_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_bypass == FRMGEN_BYPASS_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_mfrm_length == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pipeln == FRMGEN_PIPELN_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pyld_ins == FRMGEN_PYLD_INS_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_wordslip == FRMGEN_WORDSLIP_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rst_sm_dis == ENABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_sel == DELAY_PATH3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk2_sel == PLD_CLK2_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.pma_aib_tx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_pld_tx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.sh_err == SH_ERR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.tx_datapath_tb_sel == TX_FIFO_TB1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_wren == WREN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_power_mode == FULL_WIDTH_PS_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.tx_hip_aib_ssr_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_10g_tx_bitslip_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_8g_tx_boundary_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_cnt_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_num_phase_shifts_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.tx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_full == FULL_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_mode == TXPHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pfull == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u19_2.hdpldadapt.hdpldadapt_tx_chnl.word_mark == WM_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xavmm1.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xavmm1.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xavmm1.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xavmm2.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xavmm2.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xavmm2.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_ber_margining_ctrl == AIB_BER_MARGINING_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_hps_ctrl_en == AIB_DLLSTR_ALIGN_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.aib_red_shift_en == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.op_mode == RX_DLL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr3 == AIB_DATASEL3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_red_pout_shiften == AIB_RED_POUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_tx_clkdiv == AIB_TX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp == AIB_TX_DCC_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp_iocsr_unused == AIB_TX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal == AIB_TX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal_iocsr_unused == AIB_TX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft == AIB_TX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft_sel == AIB_TX_DCC_DFT_MODE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_dft_sel == AIB_TX_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_entest == AIB_TX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctl_static == AIB_TX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctlsel == AIB_TX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en == AIB_TX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en_iocsr_unused == AIB_TX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_dn == AIB_TX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_up == AIB_TX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_rst_prgmnvrt == AIB_TX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_dn_prgmnvrt == AIB_TX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_up_prgmnvrt == AIB_TX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_updnen == AIB_TX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dftmuxsel == AIB_TX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dly_pst == AIB_TX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_en == AIB_TX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_hps_ctrl_en == AIB_TX_DCC_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_lockreq_muxsel == AIB_TX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_new_dll == AIB_TX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_rst == AIB_TX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_test_clk_pll_en_n == AIB_TX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_tx_halfcode == AIB_TX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.aib_tx_selflock == AIB_TX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.op_mode == TX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_0.xaibnd_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.aib_fabric_pma_aib_tx_clk_hz == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.aib_fabric_rx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.aib_fabric_rx_transfer_clk_hz == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.aib_fabric_tx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.csr_clk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.speed_grade == DASH_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.adapter_base_addr == 10'd768
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_read == AVMM1_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_write == AVMM1_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.avmm1_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.avmm1_nfhssi_calibratio_feature_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_dft_broadcast_en == DISABLE_ONLY_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_force_mdio_dis_csr_ctrl == DISABLE_ONLY_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.avmm1_read_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.avmm1_uc_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_read == AVMM2_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_write == AVMM2_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.avmm2_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.avmm2_hip_sel == AVMM2_FOR_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.nfhssi_base_addr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_RX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_RX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.asn_bypass_pma_pcie_sw_done == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.asn_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_dll_reset_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_fifo_flush_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_pma_pcie_sw_done_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.dv_mode == DV_MODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_double_read == FIFO_DOUBLE_READ_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_ins_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_sel == FIFO_RD_CLK_PLD_RX_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_del_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_sel == FIFO_WR_CLK_RX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rst_sm_dis == ENABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel1 == PMA_CLKS_OR_TXFIFORD_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel2 == PMA_CLKS_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel2 == PMA_CLKS_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_sel == DELAY_PATH3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.pma_hclk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_pld_rx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_wren == WREN_DS_DEL_US_DEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_power_mode == FULL_WIDTH_PS_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_ctrl == BLKLOCK_IGNORE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_8g_eidleinfersel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_eye_monitor_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_pcie_switch_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_reser_out_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.rx_prbs_flags_sr_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.rx_true_b2b == B2B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.rx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_empty == EMPTY_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_full == FULL_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_mode == RXPHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pempty == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pfull == 6'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.rxfiford_post_ct_sel == RXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifowr_post_ct_sel == RXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.sclk_sel == SCLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.txfiford_post_ct_sel == TXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.txfifowr_post_ct_sel == TXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.word_align == WA_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_rx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_sr.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_sr.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_sr.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_sr.sr_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_sr.sr_testbus_sel == SSR_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_TX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_TX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.dv_bond == DV_BOND_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.dv_gen == DV_GEN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_frm_gen_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_sel == FIFO_RD_PMA_AIB_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.fpll_shared_direct_async_in_sel == FPLL_SHARED_DIRECT_ASYNC_IN_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_burst == FRMGEN_BURST_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_bypass == FRMGEN_BYPASS_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_mfrm_length == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pipeln == FRMGEN_PIPELN_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pyld_ins == FRMGEN_PYLD_INS_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_wordslip == FRMGEN_WORDSLIP_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rst_sm_dis == ENABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_sel == DELAY_PATH3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk2_sel == PLD_CLK2_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.pma_aib_tx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_pld_tx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.sh_err == SH_ERR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.tx_datapath_tb_sel == TX_FIFO_TB1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_wren == WREN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_power_mode == FULL_WIDTH_PS_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.tx_hip_aib_ssr_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_10g_tx_bitslip_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_8g_tx_boundary_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_cnt_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_num_phase_shifts_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.tx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_full == FULL_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_mode == TXPHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pfull == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u20_2.hdpldadapt.hdpldadapt_tx_chnl.word_mark == WM_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xavmm1.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xavmm1.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xavmm1.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xavmm2.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xavmm2.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xavmm2.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_ber_margining_ctrl == AIB_BER_MARGINING_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_hps_ctrl_en == AIB_DLLSTR_ALIGN_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.aib_red_shift_en == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.op_mode == RX_DLL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr3 == AIB_DATASEL3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_red_pout_shiften == AIB_RED_POUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_tx_clkdiv == AIB_TX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp == AIB_TX_DCC_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp_iocsr_unused == AIB_TX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal == AIB_TX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal_iocsr_unused == AIB_TX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft == AIB_TX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft_sel == AIB_TX_DCC_DFT_MODE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_dft_sel == AIB_TX_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_entest == AIB_TX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctl_static == AIB_TX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctlsel == AIB_TX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en == AIB_TX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en_iocsr_unused == AIB_TX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_dn == AIB_TX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_up == AIB_TX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_rst_prgmnvrt == AIB_TX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_dn_prgmnvrt == AIB_TX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_up_prgmnvrt == AIB_TX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_updnen == AIB_TX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dftmuxsel == AIB_TX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dly_pst == AIB_TX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_en == AIB_TX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_hps_ctrl_en == AIB_TX_DCC_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_lockreq_muxsel == AIB_TX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_new_dll == AIB_TX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_rst == AIB_TX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_test_clk_pll_en_n == AIB_TX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_tx_halfcode == AIB_TX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.aib_tx_selflock == AIB_TX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.op_mode == TX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_0.xaibnd_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.aib_fabric_pma_aib_tx_clk_hz == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.aib_fabric_rx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.aib_fabric_rx_transfer_clk_hz == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.aib_fabric_tx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.csr_clk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.speed_grade == DASH_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.adapter_base_addr == 10'd768
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_read == AVMM1_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_write == AVMM1_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.avmm1_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.avmm1_nfhssi_calibratio_feature_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_dft_broadcast_en == DISABLE_ONLY_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_force_mdio_dis_csr_ctrl == DISABLE_ONLY_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.avmm1_read_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.avmm1_uc_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_read == AVMM2_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_write == AVMM2_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.avmm2_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.avmm2_hip_sel == AVMM2_FOR_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.nfhssi_base_addr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_RX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_RX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.asn_bypass_pma_pcie_sw_done == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.asn_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_dll_reset_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_fifo_flush_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_pma_pcie_sw_done_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.dv_mode == DV_MODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_double_read == FIFO_DOUBLE_READ_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_ins_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_sel == FIFO_RD_CLK_PLD_RX_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_del_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_sel == FIFO_WR_CLK_RX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rst_sm_dis == ENABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel1 == PMA_CLKS_OR_TXFIFORD_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel2 == PMA_CLKS_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel2 == PMA_CLKS_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_sel == DELAY_PATH3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.pma_hclk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_pld_rx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_wren == WREN_DS_DEL_US_DEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_power_mode == FULL_WIDTH_PS_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_ctrl == BLKLOCK_IGNORE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_8g_eidleinfersel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_eye_monitor_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_pcie_switch_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_reser_out_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.rx_prbs_flags_sr_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.rx_true_b2b == B2B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.rx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_empty == EMPTY_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_full == FULL_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_mode == RXPHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pempty == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pfull == 6'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.rxfiford_post_ct_sel == RXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifowr_post_ct_sel == RXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.sclk_sel == SCLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.txfiford_post_ct_sel == TXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.txfifowr_post_ct_sel == TXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.word_align == WA_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_rx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_sr.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_sr.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_sr.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_sr.sr_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_sr.sr_testbus_sel == SSR_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_TX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_TX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.dv_bond == DV_BOND_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.dv_gen == DV_GEN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_frm_gen_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_sel == FIFO_RD_PMA_AIB_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.fpll_shared_direct_async_in_sel == FPLL_SHARED_DIRECT_ASYNC_IN_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_burst == FRMGEN_BURST_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_bypass == FRMGEN_BYPASS_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_mfrm_length == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pipeln == FRMGEN_PIPELN_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pyld_ins == FRMGEN_PYLD_INS_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_wordslip == FRMGEN_WORDSLIP_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rst_sm_dis == ENABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_sel == DELAY_PATH3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk2_sel == PLD_CLK2_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.pma_aib_tx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_pld_tx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.sh_err == SH_ERR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.tx_datapath_tb_sel == TX_FIFO_TB1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_wren == WREN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_power_mode == FULL_WIDTH_PS_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.tx_hip_aib_ssr_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_10g_tx_bitslip_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_8g_tx_boundary_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_cnt_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_num_phase_shifts_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.tx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_full == FULL_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_mode == TXPHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pfull == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u21_2.hdpldadapt.hdpldadapt_tx_chnl.word_mark == WM_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xavmm1.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xavmm1.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xavmm1.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xavmm2.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xavmm2.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xavmm2.op_mode == PWR_DOWN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xavmm2.powermode_dc == POWERDOWN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_ber_margining_ctrl == AIB_BER_MARGINING_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_hps_ctrl_en == AIB_DLLSTR_ALIGN_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.aib_red_shift_en == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.op_mode == RX_DLL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr3 == AIB_DATASEL3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_red_pout_shiften == AIB_RED_POUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_tx_clkdiv == AIB_TX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp == AIB_TX_DCC_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp_iocsr_unused == AIB_TX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal == AIB_TX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal_iocsr_unused == AIB_TX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft == AIB_TX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft_sel == AIB_TX_DCC_DFT_MODE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_dft_sel == AIB_TX_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_entest == AIB_TX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctl_static == AIB_TX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctlsel == AIB_TX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en == AIB_TX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en_iocsr_unused == AIB_TX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_dn == AIB_TX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_up == AIB_TX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_rst_prgmnvrt == AIB_TX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_dn_prgmnvrt == AIB_TX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_up_prgmnvrt == AIB_TX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_updnen == AIB_TX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dftmuxsel == AIB_TX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dly_pst == AIB_TX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_en == AIB_TX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_hps_ctrl_en == AIB_TX_DCC_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_lockreq_muxsel == AIB_TX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_new_dll == AIB_TX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_rst == AIB_TX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_test_clk_pll_en_n == AIB_TX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_tx_halfcode == AIB_TX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.aib_tx_selflock == AIB_TX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.op_mode == TX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_0.xaibnd_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.aib_fabric_pma_aib_tx_clk_hz == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.aib_fabric_rx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.aib_fabric_rx_transfer_clk_hz == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.aib_fabric_tx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.csr_clk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.speed_grade == DASH_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.adapter_base_addr == 10'd768
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_read == AVMM1_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_write == AVMM1_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.avmm1_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.avmm1_nfhssi_calibratio_feature_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_dft_broadcast_en == DISABLE_ONLY_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_force_mdio_dis_csr_ctrl == DISABLE_ONLY_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.avmm1_read_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.avmm1_uc_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.avmm2_avmm_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_read == AVMM2_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_write == AVMM2_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.avmm2_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.avmm2_hip_sel == AVMM2_FOR_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.avmm2_osc_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.nfhssi_base_addr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_RX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_RX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.asn_bypass_pma_pcie_sw_done == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.asn_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_dll_reset_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_fifo_flush_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_pma_pcie_sw_done_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.dv_mode == DV_MODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_double_read == FIFO_DOUBLE_READ_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_ins_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_sel == FIFO_RD_CLK_PLD_RX_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_del_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_sel == FIFO_WR_CLK_RX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rst_sm_dis == ENABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel1 == PMA_CLKS_OR_TXFIFORD_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel2 == PMA_CLKS_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel2 == PMA_CLKS_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_sel == DELAY_PATH3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.pma_hclk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_pld_rx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_wren == WREN_DS_DEL_US_DEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_power_mode == FULL_WIDTH_PS_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_ctrl == BLKLOCK_IGNORE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_8g_eidleinfersel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_eye_monitor_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_pcie_switch_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_reser_out_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.rx_prbs_flags_sr_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.rx_true_b2b == B2B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.rx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_empty == EMPTY_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_full == FULL_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_mode == RXPHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pempty == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pfull == 6'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.rxfiford_post_ct_sel == RXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifowr_post_ct_sel == RXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.sclk_sel == SCLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.txfiford_post_ct_sel == TXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.txfifowr_post_ct_sel == TXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.word_align == WA_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_rx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_sr.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_sr.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_sr.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_sr.sr_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_sr.sr_testbus_sel == SSR_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_TX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_TX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.dv_bond == DV_BOND_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.dv_gen == DV_GEN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_frm_gen_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_sel == FIFO_RD_PMA_AIB_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.fpll_shared_direct_async_in_sel == FPLL_SHARED_DIRECT_ASYNC_IN_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_burst == FRMGEN_BURST_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_bypass == FRMGEN_BYPASS_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_mfrm_length == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pipeln == FRMGEN_PIPELN_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pyld_ins == FRMGEN_PYLD_INS_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_wordslip == FRMGEN_WORDSLIP_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rst_sm_dis == ENABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_sel == DELAY_PATH3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk2_sel == PLD_CLK2_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.pma_aib_tx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_pld_tx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.sh_err == SH_ERR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.tx_datapath_tb_sel == TX_FIFO_TB1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_wren == WREN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_power_mode == FULL_WIDTH_PS_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.tx_hip_aib_ssr_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_10g_tx_bitslip_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_8g_tx_boundary_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_cnt_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_num_phase_shifts_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.tx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_full == FULL_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_mode == TXPHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pfull == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u22_2.hdpldadapt.hdpldadapt_tx_chnl.word_mark == WM_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xavmm1.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xavmm1.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xavmm1.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xavmm2.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xavmm2.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xavmm2.op_mode == PWR_DOWN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xavmm2.powermode_dc == POWERDOWN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_ber_margining_ctrl == AIB_BER_MARGINING_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_hps_ctrl_en == AIB_DLLSTR_ALIGN_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.aib_red_shift_en == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.op_mode == RX_DLL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr3 == AIB_DATASEL3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_red_pout_shiften == AIB_RED_POUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_tx_clkdiv == AIB_TX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp == AIB_TX_DCC_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp_iocsr_unused == AIB_TX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal == AIB_TX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal_iocsr_unused == AIB_TX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft == AIB_TX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft_sel == AIB_TX_DCC_DFT_MODE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_dft_sel == AIB_TX_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_entest == AIB_TX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctl_static == AIB_TX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctlsel == AIB_TX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en == AIB_TX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en_iocsr_unused == AIB_TX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_dn == AIB_TX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_up == AIB_TX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_rst_prgmnvrt == AIB_TX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_dn_prgmnvrt == AIB_TX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_up_prgmnvrt == AIB_TX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_updnen == AIB_TX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dftmuxsel == AIB_TX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dly_pst == AIB_TX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_en == AIB_TX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_hps_ctrl_en == AIB_TX_DCC_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_lockreq_muxsel == AIB_TX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_new_dll == AIB_TX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_rst == AIB_TX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_test_clk_pll_en_n == AIB_TX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_tx_halfcode == AIB_TX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.aib_tx_selflock == AIB_TX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.op_mode == TX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_0.xaibnd_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.aib_fabric_pma_aib_tx_clk_hz == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.aib_fabric_rx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.aib_fabric_rx_transfer_clk_hz == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.aib_fabric_tx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.csr_clk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.speed_grade == DASH_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.adapter_base_addr == 10'd768
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_read == AVMM1_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_write == AVMM1_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.avmm1_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.avmm1_nfhssi_calibratio_feature_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_dft_broadcast_en == DISABLE_ONLY_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_force_mdio_dis_csr_ctrl == DISABLE_ONLY_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.avmm1_read_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.avmm1_uc_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.avmm2_avmm_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_read == AVMM2_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_write == AVMM2_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.avmm2_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.avmm2_hip_sel == AVMM2_FOR_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.avmm2_osc_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.nfhssi_base_addr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_RX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_RX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.asn_bypass_pma_pcie_sw_done == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.asn_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_dll_reset_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_fifo_flush_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_pma_pcie_sw_done_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.dv_mode == DV_MODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_double_read == FIFO_DOUBLE_READ_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_ins_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_sel == FIFO_RD_CLK_PLD_RX_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_del_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_sel == FIFO_WR_CLK_RX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rst_sm_dis == ENABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel1 == PMA_CLKS_OR_TXFIFORD_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel2 == PMA_CLKS_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel2 == PMA_CLKS_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_sel == DELAY_PATH3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.pma_hclk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_pld_rx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_wren == WREN_DS_DEL_US_DEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_power_mode == FULL_WIDTH_PS_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_ctrl == BLKLOCK_IGNORE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_8g_eidleinfersel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_eye_monitor_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_pcie_switch_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_reser_out_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.rx_prbs_flags_sr_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.rx_true_b2b == B2B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.rx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_empty == EMPTY_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_full == FULL_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_mode == RXPHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pempty == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pfull == 6'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.rxfiford_post_ct_sel == RXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifowr_post_ct_sel == RXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.sclk_sel == SCLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.txfiford_post_ct_sel == TXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.txfifowr_post_ct_sel == TXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.word_align == WA_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_rx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_sr.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_sr.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_sr.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_sr.sr_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_sr.sr_testbus_sel == SSR_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_TX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_TX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.dv_bond == DV_BOND_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.dv_gen == DV_GEN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_frm_gen_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_sel == FIFO_RD_PMA_AIB_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.fpll_shared_direct_async_in_sel == FPLL_SHARED_DIRECT_ASYNC_IN_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_burst == FRMGEN_BURST_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_bypass == FRMGEN_BYPASS_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_mfrm_length == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pipeln == FRMGEN_PIPELN_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pyld_ins == FRMGEN_PYLD_INS_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_wordslip == FRMGEN_WORDSLIP_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rst_sm_dis == ENABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_sel == DELAY_PATH3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk2_sel == PLD_CLK2_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.pma_aib_tx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_pld_tx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.sh_err == SH_ERR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.tx_datapath_tb_sel == TX_FIFO_TB1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_wren == WREN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_power_mode == FULL_WIDTH_PS_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.tx_hip_aib_ssr_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_10g_tx_bitslip_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_8g_tx_boundary_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_cnt_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_num_phase_shifts_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.tx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_full == FULL_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_mode == TXPHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pfull == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u23_2.hdpldadapt.hdpldadapt_tx_chnl.word_mark == WM_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xavmm1.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xavmm1.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xavmm1.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xavmm2.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xavmm2.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xavmm2.op_mode == PWR_DOWN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xavmm2.powermode_dc == POWERDOWN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_ber_margining_ctrl == AIB_BER_MARGINING_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_hps_ctrl_en == AIB_DLLSTR_ALIGN_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.aib_red_shift_en == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.op_mode == RX_DLL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr3 == AIB_DATASEL3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_red_pout_shiften == AIB_RED_POUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_tx_clkdiv == AIB_TX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp == AIB_TX_DCC_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp_iocsr_unused == AIB_TX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal == AIB_TX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal_iocsr_unused == AIB_TX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft == AIB_TX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft_sel == AIB_TX_DCC_DFT_MODE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_dft_sel == AIB_TX_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_entest == AIB_TX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctl_static == AIB_TX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctlsel == AIB_TX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en == AIB_TX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en_iocsr_unused == AIB_TX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_dn == AIB_TX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_up == AIB_TX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_rst_prgmnvrt == AIB_TX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_dn_prgmnvrt == AIB_TX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_up_prgmnvrt == AIB_TX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_updnen == AIB_TX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dftmuxsel == AIB_TX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dly_pst == AIB_TX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_en == AIB_TX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_hps_ctrl_en == AIB_TX_DCC_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_lockreq_muxsel == AIB_TX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_new_dll == AIB_TX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_rst == AIB_TX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_test_clk_pll_en_n == AIB_TX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_tx_halfcode == AIB_TX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.aib_tx_selflock == AIB_TX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.op_mode == TX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_0.xaibnd_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.aib_fabric_pma_aib_tx_clk_hz == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.aib_fabric_rx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.aib_fabric_rx_transfer_clk_hz == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.aib_fabric_tx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.csr_clk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.speed_grade == DASH_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.adapter_base_addr == 10'd768
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_read == AVMM1_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_write == AVMM1_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.avmm1_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.avmm1_nfhssi_calibratio_feature_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_dft_broadcast_en == DISABLE_ONLY_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_force_mdio_dis_csr_ctrl == DISABLE_ONLY_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.avmm1_read_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.avmm1_uc_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.avmm2_avmm_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_read == AVMM2_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_write == AVMM2_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.avmm2_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.avmm2_hip_sel == AVMM2_FOR_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.avmm2_osc_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.nfhssi_base_addr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_RX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_RX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.asn_bypass_pma_pcie_sw_done == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.asn_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_dll_reset_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_fifo_flush_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_pma_pcie_sw_done_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.dv_mode == DV_MODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_double_read == FIFO_DOUBLE_READ_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_ins_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_sel == FIFO_RD_CLK_PLD_RX_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_del_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_sel == FIFO_WR_CLK_RX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rst_sm_dis == ENABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel1 == PMA_CLKS_OR_TXFIFORD_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel2 == PMA_CLKS_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel2 == PMA_CLKS_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_sel == DELAY_PATH3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.pma_hclk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_pld_rx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_wren == WREN_DS_DEL_US_DEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_power_mode == FULL_WIDTH_PS_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_ctrl == BLKLOCK_IGNORE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_8g_eidleinfersel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_eye_monitor_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_pcie_switch_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_reser_out_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.rx_prbs_flags_sr_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.rx_true_b2b == B2B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.rx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_empty == EMPTY_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_full == FULL_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_mode == RXPHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pempty == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pfull == 6'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.rxfiford_post_ct_sel == RXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifowr_post_ct_sel == RXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.sclk_sel == SCLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.txfiford_post_ct_sel == TXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.txfifowr_post_ct_sel == TXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.word_align == WA_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_rx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_sr.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_sr.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_sr.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_sr.sr_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_sr.sr_testbus_sel == SSR_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_TX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_TX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.dv_bond == DV_BOND_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.dv_gen == DV_GEN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_frm_gen_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_sel == FIFO_RD_PMA_AIB_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.fpll_shared_direct_async_in_sel == FPLL_SHARED_DIRECT_ASYNC_IN_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_burst == FRMGEN_BURST_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_bypass == FRMGEN_BYPASS_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_mfrm_length == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pipeln == FRMGEN_PIPELN_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pyld_ins == FRMGEN_PYLD_INS_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_wordslip == FRMGEN_WORDSLIP_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rst_sm_dis == ENABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_sel == DELAY_PATH3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk2_sel == PLD_CLK2_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.pma_aib_tx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_pld_tx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.sh_err == SH_ERR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.tx_datapath_tb_sel == TX_FIFO_TB1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_wren == WREN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_power_mode == FULL_WIDTH_PS_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.tx_hip_aib_ssr_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_10g_tx_bitslip_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_8g_tx_boundary_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_cnt_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_num_phase_shifts_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.tx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_full == FULL_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_mode == TXPHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pfull == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u24_2.hdpldadapt.hdpldadapt_tx_chnl.word_mark == WM_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xavmm1.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xavmm1.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xavmm1.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xavmm2.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xavmm2.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xavmm2.op_mode == PWR_DOWN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xavmm2.powermode_dc == POWERDOWN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_ber_margining_ctrl == AIB_BER_MARGINING_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_hps_ctrl_en == AIB_DLLSTR_ALIGN_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.aib_red_shift_en == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.op_mode == RX_DLL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr3 == AIB_DATASEL3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_red_pout_shiften == AIB_RED_POUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_tx_clkdiv == AIB_TX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp == AIB_TX_DCC_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp_iocsr_unused == AIB_TX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal == AIB_TX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal_iocsr_unused == AIB_TX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft == AIB_TX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft_sel == AIB_TX_DCC_DFT_MODE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_dft_sel == AIB_TX_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_entest == AIB_TX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctl_static == AIB_TX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctlsel == AIB_TX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en == AIB_TX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en_iocsr_unused == AIB_TX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_dn == AIB_TX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_up == AIB_TX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_rst_prgmnvrt == AIB_TX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_dn_prgmnvrt == AIB_TX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_up_prgmnvrt == AIB_TX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_updnen == AIB_TX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dftmuxsel == AIB_TX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dly_pst == AIB_TX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_en == AIB_TX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_hps_ctrl_en == AIB_TX_DCC_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_lockreq_muxsel == AIB_TX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_new_dll == AIB_TX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_rst == AIB_TX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_test_clk_pll_en_n == AIB_TX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_tx_halfcode == AIB_TX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.aib_tx_selflock == AIB_TX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.op_mode == TX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_0.xaibnd_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.aib_fabric_pma_aib_tx_clk_hz == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.aib_fabric_rx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.aib_fabric_rx_transfer_clk_hz == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.aib_fabric_tx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.csr_clk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.speed_grade == DASH_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.adapter_base_addr == 10'd768
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_read == AVMM1_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_write == AVMM1_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.avmm1_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.avmm1_nfhssi_calibratio_feature_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_dft_broadcast_en == DISABLE_ONLY_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_force_mdio_dis_csr_ctrl == DISABLE_ONLY_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.avmm1_read_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.avmm1_uc_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.avmm2_avmm_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_read == AVMM2_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_write == AVMM2_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.avmm2_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.avmm2_hip_sel == AVMM2_FOR_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.avmm2_osc_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.nfhssi_base_addr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_RX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_RX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.asn_bypass_pma_pcie_sw_done == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.asn_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_dll_reset_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_fifo_flush_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_pma_pcie_sw_done_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.dv_mode == DV_MODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_double_read == FIFO_DOUBLE_READ_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_ins_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_sel == FIFO_RD_CLK_PLD_RX_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_del_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_sel == FIFO_WR_CLK_RX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rst_sm_dis == ENABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel1 == PMA_CLKS_OR_TXFIFORD_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel2 == PMA_CLKS_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel2 == PMA_CLKS_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_sel == DELAY_PATH3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.pma_hclk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_pld_rx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_wren == WREN_DS_DEL_US_DEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_power_mode == FULL_WIDTH_PS_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_ctrl == BLKLOCK_IGNORE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_8g_eidleinfersel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_eye_monitor_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_pcie_switch_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_reser_out_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.rx_prbs_flags_sr_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.rx_true_b2b == B2B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.rx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_empty == EMPTY_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_full == FULL_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_mode == RXPHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pempty == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pfull == 6'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.rxfiford_post_ct_sel == RXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifowr_post_ct_sel == RXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.sclk_sel == SCLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.txfiford_post_ct_sel == TXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.txfifowr_post_ct_sel == TXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.word_align == WA_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_rx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_sr.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_sr.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_sr.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_sr.sr_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_sr.sr_testbus_sel == SSR_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_TX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_TX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.dv_bond == DV_BOND_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.dv_gen == DV_GEN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_frm_gen_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_sel == FIFO_RD_PMA_AIB_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.fpll_shared_direct_async_in_sel == FPLL_SHARED_DIRECT_ASYNC_IN_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_burst == FRMGEN_BURST_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_bypass == FRMGEN_BYPASS_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_mfrm_length == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pipeln == FRMGEN_PIPELN_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pyld_ins == FRMGEN_PYLD_INS_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_wordslip == FRMGEN_WORDSLIP_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rst_sm_dis == ENABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_sel == DELAY_PATH3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk2_sel == PLD_CLK2_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.pma_aib_tx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_pld_tx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.sh_err == SH_ERR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.tx_datapath_tb_sel == TX_FIFO_TB1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_wren == WREN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_power_mode == FULL_WIDTH_PS_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.tx_hip_aib_ssr_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_10g_tx_bitslip_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_8g_tx_boundary_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_cnt_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_num_phase_shifts_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.tx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_full == FULL_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_mode == TXPHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pfull == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u25_2.hdpldadapt.hdpldadapt_tx_chnl.word_mark == WM_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xavmm1.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xavmm1.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xavmm1.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xavmm2.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xavmm2.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xavmm2.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_ber_margining_ctrl == AIB_BER_MARGINING_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_hps_ctrl_en == AIB_DLLSTR_ALIGN_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.aib_red_shift_en == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.op_mode == RX_DLL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr3 == AIB_DATASEL3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_red_pout_shiften == AIB_RED_POUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_tx_clkdiv == AIB_TX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp == AIB_TX_DCC_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp_iocsr_unused == AIB_TX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal == AIB_TX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal_iocsr_unused == AIB_TX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft == AIB_TX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft_sel == AIB_TX_DCC_DFT_MODE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_dft_sel == AIB_TX_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_entest == AIB_TX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctl_static == AIB_TX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctlsel == AIB_TX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en == AIB_TX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en_iocsr_unused == AIB_TX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_dn == AIB_TX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_up == AIB_TX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_rst_prgmnvrt == AIB_TX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_dn_prgmnvrt == AIB_TX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_up_prgmnvrt == AIB_TX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_updnen == AIB_TX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dftmuxsel == AIB_TX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dly_pst == AIB_TX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_en == AIB_TX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_hps_ctrl_en == AIB_TX_DCC_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_lockreq_muxsel == AIB_TX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_new_dll == AIB_TX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_rst == AIB_TX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_test_clk_pll_en_n == AIB_TX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_tx_halfcode == AIB_TX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.aib_tx_selflock == AIB_TX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.op_mode == TX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_0.xaibnd_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.aib_fabric_pma_aib_tx_clk_hz == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.aib_fabric_rx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.aib_fabric_rx_transfer_clk_hz == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.aib_fabric_tx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.csr_clk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.speed_grade == DASH_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.adapter_base_addr == 10'd768
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_read == AVMM1_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_write == AVMM1_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.avmm1_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.avmm1_nfhssi_calibratio_feature_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_dft_broadcast_en == DISABLE_ONLY_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_force_mdio_dis_csr_ctrl == DISABLE_ONLY_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.avmm1_read_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.avmm1_uc_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_read == AVMM2_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_write == AVMM2_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.avmm2_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.avmm2_hip_sel == AVMM2_FOR_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.nfhssi_base_addr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_RX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_RX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.asn_bypass_pma_pcie_sw_done == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.asn_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_dll_reset_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_fifo_flush_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_pma_pcie_sw_done_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.duplex_mode == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.dv_mode == DV_MODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_double_read == FIFO_DOUBLE_READ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_mode == GENERIC_BASIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_ins_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_sel == FIFO_RD_CLK_PLD_RX_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_rd == N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_del_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_sel == FIFO_WR_CLK_RX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rst_sm_dis == ENABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel1 == PMA_CLKS_OR_TXFIFORD_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel2 == PMA_CLKS_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel2 == PMA_CLKS_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_sel == DELAY_PATH0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.pma_hclk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_pld_rx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_wren == WREN_DS_DEL_US_DEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_power_mode == FULL_WIDTH_FULL_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_ctrl == BLKLOCK_IGNORE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_8g_eidleinfersel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_eye_monitor_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_pcie_switch_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_reser_out_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.rx_prbs_flags_sr_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.rx_true_b2b == B2B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.rx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_empty == EMPTY_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_full == FULL_NON_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_mode == RXGENERIC_BASIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pempty == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pfull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.rxfiford_post_ct_sel == RXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifowr_post_ct_sel == RXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.sclk_sel == SCLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.stretch_num_stages == ONE_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.txfiford_post_ct_sel == TXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.txfifowr_post_ct_sel == TXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_rx_chnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_sr.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_sr.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_sr.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_sr.sr_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_sr.sr_testbus_sel == SSR_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_TX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_TX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.duplex_mode == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.dv_bond == DV_BOND_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.dv_gen == DV_GEN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_mode == GENERIC_BASIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_frm_gen_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_sel == FIFO_RD_PMA_AIB_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_rd == N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.fpll_shared_direct_async_in_sel == FPLL_SHARED_DIRECT_ASYNC_IN_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_burst == FRMGEN_BURST_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_bypass == FRMGEN_BYPASS_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_mfrm_length == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pipeln == FRMGEN_PIPELN_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pyld_ins == FRMGEN_PYLD_INS_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_wordslip == FRMGEN_WORDSLIP_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rst_sm_dis == ENABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_sel == DELAY_PATH0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk2_sel == PLD_CLK2_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.pma_aib_tx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_pld_tx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.sh_err == SH_ERR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.tx_datapath_tb_sel == TX_FIFO_TB1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_wren == WREN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_power_mode == FULL_WIDTH_FULL_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.tx_hip_aib_ssr_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_10g_tx_bitslip_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_8g_tx_boundary_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_cnt_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_num_phase_shifts_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.tx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_full == FULL_NON_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_mode == TXGENERIC_BASIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pfull == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u2_2.hdpldadapt.hdpldadapt_tx_chnl.word_mark == WM_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xavmm1.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xavmm1.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xavmm1.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xavmm2.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xavmm2.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xavmm2.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_ber_margining_ctrl == AIB_BER_MARGINING_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_hps_ctrl_en == AIB_DLLSTR_ALIGN_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.aib_red_shift_en == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.op_mode == RX_DLL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr3 == AIB_DATASEL3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_red_pout_shiften == AIB_RED_POUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_tx_clkdiv == AIB_TX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp == AIB_TX_DCC_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp_iocsr_unused == AIB_TX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal == AIB_TX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal_iocsr_unused == AIB_TX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft == AIB_TX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft_sel == AIB_TX_DCC_DFT_MODE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_dft_sel == AIB_TX_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_entest == AIB_TX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctl_static == AIB_TX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctlsel == AIB_TX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en == AIB_TX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en_iocsr_unused == AIB_TX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_dn == AIB_TX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_up == AIB_TX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_rst_prgmnvrt == AIB_TX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_dn_prgmnvrt == AIB_TX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_up_prgmnvrt == AIB_TX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_updnen == AIB_TX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dftmuxsel == AIB_TX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dly_pst == AIB_TX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_en == AIB_TX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_hps_ctrl_en == AIB_TX_DCC_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_lockreq_muxsel == AIB_TX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_new_dll == AIB_TX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_rst == AIB_TX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_test_clk_pll_en_n == AIB_TX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_tx_halfcode == AIB_TX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.aib_tx_selflock == AIB_TX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.op_mode == TX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_0.xaibnd_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.aib_fabric_pma_aib_tx_clk_hz == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.aib_fabric_rx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.aib_fabric_rx_transfer_clk_hz == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.aib_fabric_tx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.csr_clk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.speed_grade == DASH_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.adapter_base_addr == 10'd768
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_read == AVMM1_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_write == AVMM1_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.avmm1_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.avmm1_nfhssi_calibratio_feature_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_dft_broadcast_en == DISABLE_ONLY_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_force_mdio_dis_csr_ctrl == DISABLE_ONLY_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.avmm1_read_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.avmm1_uc_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_read == AVMM2_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_write == AVMM2_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.avmm2_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.avmm2_hip_sel == AVMM2_FOR_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.nfhssi_base_addr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_RX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_RX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.asn_bypass_pma_pcie_sw_done == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.asn_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_dll_reset_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_fifo_flush_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_pma_pcie_sw_done_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.duplex_mode == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.dv_mode == DV_MODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_double_read == FIFO_DOUBLE_READ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_mode == GENERIC_BASIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_ins_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_sel == FIFO_RD_CLK_PLD_RX_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_rd == N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_del_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_sel == FIFO_WR_CLK_RX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rst_sm_dis == ENABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel1 == PMA_CLKS_OR_TXFIFORD_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel2 == PMA_CLKS_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel2 == PMA_CLKS_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_sel == DELAY_PATH0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.pma_hclk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_pld_rx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_wren == WREN_DS_DEL_US_DEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_power_mode == FULL_WIDTH_FULL_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_ctrl == BLKLOCK_IGNORE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_8g_eidleinfersel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_eye_monitor_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_pcie_switch_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_reser_out_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.rx_prbs_flags_sr_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.rx_true_b2b == B2B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.rx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_empty == EMPTY_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_full == FULL_NON_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_mode == RXGENERIC_BASIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pempty == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pfull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.rxfiford_post_ct_sel == RXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifowr_post_ct_sel == RXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.sclk_sel == SCLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.stretch_num_stages == ONE_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.txfiford_post_ct_sel == TXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.txfifowr_post_ct_sel == TXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_rx_chnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_sr.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_sr.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_sr.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_sr.sr_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_sr.sr_testbus_sel == SSR_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_TX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_TX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.duplex_mode == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.dv_bond == DV_BOND_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.dv_gen == DV_GEN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_mode == GENERIC_BASIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_frm_gen_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_sel == FIFO_RD_PMA_AIB_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_rd == N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.fpll_shared_direct_async_in_sel == FPLL_SHARED_DIRECT_ASYNC_IN_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_burst == FRMGEN_BURST_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_bypass == FRMGEN_BYPASS_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_mfrm_length == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pipeln == FRMGEN_PIPELN_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pyld_ins == FRMGEN_PYLD_INS_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_wordslip == FRMGEN_WORDSLIP_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rst_sm_dis == ENABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_sel == DELAY_PATH0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk2_sel == PLD_CLK2_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.pma_aib_tx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_pld_tx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.sh_err == SH_ERR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.tx_datapath_tb_sel == TX_FIFO_TB1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_wren == WREN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_power_mode == FULL_WIDTH_FULL_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.tx_hip_aib_ssr_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_10g_tx_bitslip_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_8g_tx_boundary_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_cnt_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_num_phase_shifts_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.tx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_full == FULL_NON_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_mode == TXGENERIC_BASIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pfull == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u3_2.hdpldadapt.hdpldadapt_tx_chnl.word_mark == WM_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xavmm1.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xavmm1.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xavmm1.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xavmm2.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xavmm2.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xavmm2.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_ber_margining_ctrl == AIB_BER_MARGINING_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_hps_ctrl_en == AIB_DLLSTR_ALIGN_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.aib_red_shift_en == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.op_mode == RX_DLL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr3 == AIB_DATASEL3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_red_pout_shiften == AIB_RED_POUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_tx_clkdiv == AIB_TX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp == AIB_TX_DCC_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp_iocsr_unused == AIB_TX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal == AIB_TX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal_iocsr_unused == AIB_TX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft == AIB_TX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft_sel == AIB_TX_DCC_DFT_MODE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_dft_sel == AIB_TX_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_entest == AIB_TX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctl_static == AIB_TX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctlsel == AIB_TX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en == AIB_TX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en_iocsr_unused == AIB_TX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_dn == AIB_TX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_up == AIB_TX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_rst_prgmnvrt == AIB_TX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_dn_prgmnvrt == AIB_TX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_up_prgmnvrt == AIB_TX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_updnen == AIB_TX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dftmuxsel == AIB_TX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dly_pst == AIB_TX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_en == AIB_TX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_hps_ctrl_en == AIB_TX_DCC_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_lockreq_muxsel == AIB_TX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_new_dll == AIB_TX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_rst == AIB_TX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_test_clk_pll_en_n == AIB_TX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_tx_halfcode == AIB_TX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.aib_tx_selflock == AIB_TX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.op_mode == TX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_0.xaibnd_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.aib_fabric_pma_aib_tx_clk_hz == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.aib_fabric_rx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.aib_fabric_rx_transfer_clk_hz == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.aib_fabric_tx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.csr_clk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.speed_grade == DASH_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.adapter_base_addr == 10'd768
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_read == AVMM1_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_write == AVMM1_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.avmm1_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.avmm1_nfhssi_calibratio_feature_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_dft_broadcast_en == DISABLE_ONLY_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_force_mdio_dis_csr_ctrl == DISABLE_ONLY_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.avmm1_read_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.avmm1_uc_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_read == AVMM2_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_write == AVMM2_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.avmm2_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.avmm2_hip_sel == AVMM2_FOR_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.nfhssi_base_addr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_RX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_RX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.asn_bypass_pma_pcie_sw_done == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.asn_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_dll_reset_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_fifo_flush_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_pma_pcie_sw_done_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.duplex_mode == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.dv_mode == DV_MODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_double_read == FIFO_DOUBLE_READ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_mode == GENERIC_BASIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_ins_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_sel == FIFO_RD_CLK_PLD_RX_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_rd == N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_del_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_sel == FIFO_WR_CLK_RX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rst_sm_dis == ENABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel1 == PMA_CLKS_OR_TXFIFORD_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel2 == PMA_CLKS_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel2 == PMA_CLKS_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_sel == DELAY_PATH0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.pma_hclk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_pld_rx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_wren == WREN_DS_DEL_US_DEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_power_mode == FULL_WIDTH_FULL_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_ctrl == BLKLOCK_IGNORE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_8g_eidleinfersel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_eye_monitor_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_pcie_switch_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_reser_out_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.rx_prbs_flags_sr_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.rx_true_b2b == B2B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.rx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_empty == EMPTY_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_full == FULL_NON_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_mode == RXGENERIC_BASIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pempty == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pfull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.rxfiford_post_ct_sel == RXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifowr_post_ct_sel == RXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.sclk_sel == SCLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.stretch_num_stages == ONE_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.txfiford_post_ct_sel == TXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.txfifowr_post_ct_sel == TXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_rx_chnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_sr.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_sr.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_sr.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_sr.sr_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_sr.sr_testbus_sel == SSR_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_TX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_TX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.duplex_mode == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.dv_bond == DV_BOND_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.dv_gen == DV_GEN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_mode == GENERIC_BASIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_frm_gen_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_sel == FIFO_RD_PMA_AIB_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_rd == N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.fpll_shared_direct_async_in_sel == FPLL_SHARED_DIRECT_ASYNC_IN_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_burst == FRMGEN_BURST_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_bypass == FRMGEN_BYPASS_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_mfrm_length == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pipeln == FRMGEN_PIPELN_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pyld_ins == FRMGEN_PYLD_INS_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_wordslip == FRMGEN_WORDSLIP_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rst_sm_dis == ENABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_sel == DELAY_PATH0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk2_sel == PLD_CLK2_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.pma_aib_tx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_pld_tx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.sh_err == SH_ERR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.tx_datapath_tb_sel == TX_FIFO_TB1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_wren == WREN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_power_mode == FULL_WIDTH_FULL_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.tx_hip_aib_ssr_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_10g_tx_bitslip_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_8g_tx_boundary_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_cnt_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_num_phase_shifts_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.tx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_full == FULL_NON_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_mode == TXGENERIC_BASIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pfull == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u4_2.hdpldadapt.hdpldadapt_tx_chnl.word_mark == WM_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xavmm1.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xavmm1.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xavmm1.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xavmm2.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xavmm2.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xavmm2.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_ber_margining_ctrl == AIB_BER_MARGINING_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_hps_ctrl_en == AIB_DLLSTR_ALIGN_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.aib_red_shift_en == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.op_mode == RX_DLL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr3 == AIB_DATASEL3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_red_pout_shiften == AIB_RED_POUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_tx_clkdiv == AIB_TX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp == AIB_TX_DCC_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp_iocsr_unused == AIB_TX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal == AIB_TX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal_iocsr_unused == AIB_TX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft == AIB_TX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft_sel == AIB_TX_DCC_DFT_MODE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_dft_sel == AIB_TX_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_entest == AIB_TX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctl_static == AIB_TX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctlsel == AIB_TX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en == AIB_TX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en_iocsr_unused == AIB_TX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_dn == AIB_TX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_up == AIB_TX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_rst_prgmnvrt == AIB_TX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_dn_prgmnvrt == AIB_TX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_up_prgmnvrt == AIB_TX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_updnen == AIB_TX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dftmuxsel == AIB_TX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dly_pst == AIB_TX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_en == AIB_TX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_hps_ctrl_en == AIB_TX_DCC_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_lockreq_muxsel == AIB_TX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_new_dll == AIB_TX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_rst == AIB_TX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_test_clk_pll_en_n == AIB_TX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_tx_halfcode == AIB_TX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.aib_tx_selflock == AIB_TX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.op_mode == TX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_0.xaibnd_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.aib_fabric_pma_aib_tx_clk_hz == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.aib_fabric_rx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.aib_fabric_rx_transfer_clk_hz == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.aib_fabric_tx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.csr_clk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.speed_grade == DASH_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.adapter_base_addr == 10'd768
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_read == AVMM1_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_write == AVMM1_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.avmm1_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.avmm1_nfhssi_calibratio_feature_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_dft_broadcast_en == DISABLE_ONLY_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_force_mdio_dis_csr_ctrl == DISABLE_ONLY_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.avmm1_read_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.avmm1_uc_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_read == AVMM2_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_write == AVMM2_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.avmm2_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.avmm2_hip_sel == AVMM2_FOR_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.nfhssi_base_addr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_RX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_RX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.asn_bypass_pma_pcie_sw_done == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.asn_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_dll_reset_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_fifo_flush_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_pma_pcie_sw_done_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.duplex_mode == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.dv_mode == DV_MODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_double_read == FIFO_DOUBLE_READ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_mode == GENERIC_BASIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_ins_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_sel == FIFO_RD_CLK_PLD_RX_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_rd == N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_del_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_sel == FIFO_WR_CLK_RX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rst_sm_dis == ENABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel1 == PMA_CLKS_OR_TXFIFORD_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel2 == PMA_CLKS_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel2 == PMA_CLKS_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_sel == DELAY_PATH0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.pma_hclk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_pld_rx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_wren == WREN_DS_DEL_US_DEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_power_mode == FULL_WIDTH_FULL_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_ctrl == BLKLOCK_IGNORE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_8g_eidleinfersel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_eye_monitor_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_pcie_switch_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_reser_out_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.rx_prbs_flags_sr_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.rx_true_b2b == B2B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.rx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_empty == EMPTY_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_full == FULL_NON_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_mode == RXGENERIC_BASIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pempty == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pfull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.rxfiford_post_ct_sel == RXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifowr_post_ct_sel == RXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.sclk_sel == SCLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.stretch_num_stages == ONE_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.txfiford_post_ct_sel == TXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.txfifowr_post_ct_sel == TXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_rx_chnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_sr.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_sr.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_sr.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_sr.sr_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_sr.sr_testbus_sel == SSR_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_TX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_TX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.duplex_mode == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.dv_bond == DV_BOND_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.dv_gen == DV_GEN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_mode == GENERIC_BASIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_frm_gen_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_sel == FIFO_RD_PMA_AIB_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_rd == N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.fpll_shared_direct_async_in_sel == FPLL_SHARED_DIRECT_ASYNC_IN_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_burst == FRMGEN_BURST_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_bypass == FRMGEN_BYPASS_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_mfrm_length == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pipeln == FRMGEN_PIPELN_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pyld_ins == FRMGEN_PYLD_INS_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_wordslip == FRMGEN_WORDSLIP_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rst_sm_dis == ENABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_sel == DELAY_PATH0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk2_sel == PLD_CLK2_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.pma_aib_tx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_pld_tx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.sh_err == SH_ERR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.tx_datapath_tb_sel == TX_FIFO_TB1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_wren == WREN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_power_mode == FULL_WIDTH_FULL_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.tx_hip_aib_ssr_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_10g_tx_bitslip_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_8g_tx_boundary_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_cnt_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_num_phase_shifts_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.tx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_full == FULL_NON_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_mode == TXGENERIC_BASIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pfull == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u5_2.hdpldadapt.hdpldadapt_tx_chnl.word_mark == WM_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xavmm1.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xavmm1.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xavmm1.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xavmm2.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xavmm2.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xavmm2.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_ber_margining_ctrl == AIB_BER_MARGINING_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_hps_ctrl_en == AIB_DLLSTR_ALIGN_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.aib_red_shift_en == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.op_mode == RX_DLL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr3 == AIB_DATASEL3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_red_pout_shiften == AIB_RED_POUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_tx_clkdiv == AIB_TX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp == AIB_TX_DCC_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp_iocsr_unused == AIB_TX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal == AIB_TX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal_iocsr_unused == AIB_TX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft == AIB_TX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft_sel == AIB_TX_DCC_DFT_MODE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_dft_sel == AIB_TX_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_entest == AIB_TX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctl_static == AIB_TX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctlsel == AIB_TX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en == AIB_TX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en_iocsr_unused == AIB_TX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_dn == AIB_TX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_up == AIB_TX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_rst_prgmnvrt == AIB_TX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_dn_prgmnvrt == AIB_TX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_up_prgmnvrt == AIB_TX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_updnen == AIB_TX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dftmuxsel == AIB_TX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dly_pst == AIB_TX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_en == AIB_TX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_hps_ctrl_en == AIB_TX_DCC_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_lockreq_muxsel == AIB_TX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_new_dll == AIB_TX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_rst == AIB_TX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_test_clk_pll_en_n == AIB_TX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_tx_halfcode == AIB_TX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.aib_tx_selflock == AIB_TX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.op_mode == TX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_0.xaibnd_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.aib_fabric_pma_aib_tx_clk_hz == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.aib_fabric_rx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.aib_fabric_rx_transfer_clk_hz == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.aib_fabric_tx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.csr_clk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.speed_grade == DASH_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.adapter_base_addr == 10'd768
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_read == AVMM1_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_write == AVMM1_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.avmm1_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.avmm1_nfhssi_calibratio_feature_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_dft_broadcast_en == DISABLE_ONLY_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_force_mdio_dis_csr_ctrl == DISABLE_ONLY_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.avmm1_read_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.avmm1_uc_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_read == AVMM2_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_write == AVMM2_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.avmm2_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.avmm2_hip_sel == AVMM2_FOR_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.nfhssi_base_addr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_RX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_RX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.asn_bypass_pma_pcie_sw_done == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.asn_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_dll_reset_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_fifo_flush_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_pma_pcie_sw_done_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.duplex_mode == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.dv_mode == DV_MODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_double_read == FIFO_DOUBLE_READ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_mode == GENERIC_BASIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_ins_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_sel == FIFO_RD_CLK_PLD_RX_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_rd == N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_del_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_sel == FIFO_WR_CLK_RX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rst_sm_dis == ENABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel1 == PMA_CLKS_OR_TXFIFORD_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel2 == PMA_CLKS_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel2 == PMA_CLKS_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_sel == DELAY_PATH0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.pma_hclk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_pld_rx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_wren == WREN_DS_DEL_US_DEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_power_mode == FULL_WIDTH_FULL_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_ctrl == BLKLOCK_IGNORE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_8g_eidleinfersel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_eye_monitor_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_pcie_switch_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_reser_out_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.rx_prbs_flags_sr_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.rx_true_b2b == B2B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.rx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_empty == EMPTY_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_full == FULL_NON_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_mode == RXGENERIC_BASIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pempty == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pfull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.rxfiford_post_ct_sel == RXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifowr_post_ct_sel == RXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.sclk_sel == SCLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.stretch_num_stages == ONE_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.txfiford_post_ct_sel == TXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.txfifowr_post_ct_sel == TXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_rx_chnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_sr.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_sr.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_sr.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_sr.sr_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_sr.sr_testbus_sel == SSR_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_TX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_TX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.duplex_mode == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.dv_bond == DV_BOND_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.dv_gen == DV_GEN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_mode == GENERIC_BASIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_frm_gen_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_sel == FIFO_RD_PMA_AIB_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_rd == N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.fpll_shared_direct_async_in_sel == FPLL_SHARED_DIRECT_ASYNC_IN_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_burst == FRMGEN_BURST_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_bypass == FRMGEN_BYPASS_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_mfrm_length == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pipeln == FRMGEN_PIPELN_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pyld_ins == FRMGEN_PYLD_INS_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_wordslip == FRMGEN_WORDSLIP_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rst_sm_dis == ENABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_sel == DELAY_PATH0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk2_sel == PLD_CLK2_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.pma_aib_tx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_pld_tx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.sh_err == SH_ERR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.tx_datapath_tb_sel == TX_FIFO_TB1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_wren == WREN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_power_mode == FULL_WIDTH_FULL_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.tx_hip_aib_ssr_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_10g_tx_bitslip_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_8g_tx_boundary_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_cnt_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_num_phase_shifts_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.tx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_full == FULL_NON_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_mode == TXGENERIC_BASIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pfull == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u6_2.hdpldadapt.hdpldadapt_tx_chnl.word_mark == WM_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xavmm1.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xavmm1.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xavmm1.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xavmm2.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xavmm2.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xavmm2.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_ber_margining_ctrl == AIB_BER_MARGINING_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_hps_ctrl_en == AIB_DLLSTR_ALIGN_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.aib_red_shift_en == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.op_mode == RX_DLL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr3 == AIB_DATASEL3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_red_pout_shiften == AIB_RED_POUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_tx_clkdiv == AIB_TX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp == AIB_TX_DCC_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp_iocsr_unused == AIB_TX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal == AIB_TX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal_iocsr_unused == AIB_TX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft == AIB_TX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft_sel == AIB_TX_DCC_DFT_MODE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_dft_sel == AIB_TX_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_entest == AIB_TX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctl_static == AIB_TX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctlsel == AIB_TX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en == AIB_TX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en_iocsr_unused == AIB_TX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_dn == AIB_TX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_up == AIB_TX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_rst_prgmnvrt == AIB_TX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_dn_prgmnvrt == AIB_TX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_up_prgmnvrt == AIB_TX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_updnen == AIB_TX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dftmuxsel == AIB_TX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dly_pst == AIB_TX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_en == AIB_TX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_hps_ctrl_en == AIB_TX_DCC_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_lockreq_muxsel == AIB_TX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_new_dll == AIB_TX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_rst == AIB_TX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_test_clk_pll_en_n == AIB_TX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_tx_halfcode == AIB_TX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.aib_tx_selflock == AIB_TX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.op_mode == TX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_0.xaibnd_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.aib_fabric_pma_aib_tx_clk_hz == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.aib_fabric_rx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.aib_fabric_rx_transfer_clk_hz == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.aib_fabric_tx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.csr_clk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.speed_grade == DASH_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.adapter_base_addr == 10'd768
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_read == AVMM1_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_write == AVMM1_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.avmm1_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.avmm1_nfhssi_calibratio_feature_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_dft_broadcast_en == DISABLE_ONLY_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_force_mdio_dis_csr_ctrl == DISABLE_ONLY_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.avmm1_read_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.avmm1_uc_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_read == AVMM2_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_write == AVMM2_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.avmm2_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.avmm2_hip_sel == AVMM2_FOR_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.nfhssi_base_addr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_RX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_RX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.asn_bypass_pma_pcie_sw_done == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.asn_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_dll_reset_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_fifo_flush_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_pma_pcie_sw_done_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.duplex_mode == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.dv_mode == DV_MODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_double_read == FIFO_DOUBLE_READ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_mode == GENERIC_BASIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_ins_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_sel == FIFO_RD_CLK_PLD_RX_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_rd == N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_del_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_sel == FIFO_WR_CLK_RX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rst_sm_dis == ENABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel1 == PMA_CLKS_OR_TXFIFORD_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel2 == PMA_CLKS_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel2 == PMA_CLKS_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_sel == DELAY_PATH0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.pma_hclk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_pld_rx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_wren == WREN_DS_DEL_US_DEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_power_mode == FULL_WIDTH_FULL_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_ctrl == BLKLOCK_IGNORE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_8g_eidleinfersel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_eye_monitor_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_pcie_switch_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_reser_out_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.rx_prbs_flags_sr_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.rx_true_b2b == B2B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.rx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_empty == EMPTY_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_full == FULL_NON_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_mode == RXGENERIC_BASIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pempty == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pfull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.rxfiford_post_ct_sel == RXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifowr_post_ct_sel == RXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.sclk_sel == SCLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.stretch_num_stages == ONE_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.txfiford_post_ct_sel == TXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.txfifowr_post_ct_sel == TXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_rx_chnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_sr.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_sr.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_sr.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_sr.sr_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_sr.sr_testbus_sel == SSR_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_TX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_TX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.duplex_mode == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.dv_bond == DV_BOND_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.dv_gen == DV_GEN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_mode == GENERIC_BASIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_frm_gen_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_sel == FIFO_RD_PMA_AIB_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_rd == N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.fpll_shared_direct_async_in_sel == FPLL_SHARED_DIRECT_ASYNC_IN_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_burst == FRMGEN_BURST_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_bypass == FRMGEN_BYPASS_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_mfrm_length == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pipeln == FRMGEN_PIPELN_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pyld_ins == FRMGEN_PYLD_INS_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_wordslip == FRMGEN_WORDSLIP_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rst_sm_dis == ENABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_sel == DELAY_PATH0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk2_sel == PLD_CLK2_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.pma_aib_tx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_pld_tx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.sh_err == SH_ERR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.tx_datapath_tb_sel == TX_FIFO_TB1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_wren == WREN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_power_mode == FULL_WIDTH_FULL_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.tx_hip_aib_ssr_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_10g_tx_bitslip_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_8g_tx_boundary_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_cnt_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_num_phase_shifts_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.tx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_full == FULL_NON_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_mode == TXGENERIC_BASIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pfull == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u7_2.hdpldadapt.hdpldadapt_tx_chnl.word_mark == WM_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xavmm1.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xavmm1.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xavmm1.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xavmm2.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xavmm2.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xavmm2.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_ber_margining_ctrl == AIB_BER_MARGINING_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_hps_ctrl_en == AIB_DLLSTR_ALIGN_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.aib_red_shift_en == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.op_mode == RX_DLL_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_HIGH_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr3 == AIB_DATASEL3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_red_pout_shiften == AIB_RED_POUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_tx_clkdiv == AIB_TX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp == AIB_TX_DCC_BYP_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp_iocsr_unused == AIB_TX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal == AIB_TX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal_iocsr_unused == AIB_TX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft == AIB_TX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft_sel == AIB_TX_DCC_DFT_MODE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_dft_sel == AIB_TX_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_entest == AIB_TX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctl_static == AIB_TX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctlsel == AIB_TX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en == AIB_TX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en_iocsr_unused == AIB_TX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_dn == AIB_TX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_up == AIB_TX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_rst_prgmnvrt == AIB_TX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_dn_prgmnvrt == AIB_TX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_up_prgmnvrt == AIB_TX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_updnen == AIB_TX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dftmuxsel == AIB_TX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dly_pst == AIB_TX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_en == AIB_TX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_hps_ctrl_en == AIB_TX_DCC_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_lockreq_muxsel == AIB_TX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_new_dll == AIB_TX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_rst == AIB_TX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_test_clk_pll_en_n == AIB_TX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_tx_halfcode == AIB_TX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.aib_tx_selflock == AIB_TX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.op_mode == TX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_HIGH_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_0.xaibnd_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.aib_fabric_pma_aib_tx_clk_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.aib_fabric_rx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.aib_fabric_rx_transfer_clk_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.aib_fabric_tx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.csr_clk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.speed_grade == DASH_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.adapter_base_addr == 10'd768
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_read == AVMM1_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_write == AVMM1_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.avmm1_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.avmm1_nfhssi_calibratio_feature_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_dft_broadcast_en == DISABLE_ONLY_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_force_mdio_dis_csr_ctrl == DISABLE_ONLY_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.avmm1_read_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.avmm1_uc_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_read == AVMM2_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_write == AVMM2_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.avmm2_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.avmm2_hip_sel == AVMM2_FOR_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.nfhssi_base_addr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_RX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_RX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.asn_bypass_pma_pcie_sw_done == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.asn_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_dll_reset_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_fifo_flush_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_pma_pcie_sw_done_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.duplex_mode == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.dv_mode == DV_MODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_double_read == FIFO_DOUBLE_READ_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_ins_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_sel == FIFO_RD_CLK_PLD_RX_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_del_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_sel == FIFO_WR_CLK_RX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rst_sm_dis == ENABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel1 == PMA_CLKS_OR_TXFIFORD_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel2 == PMA_CLKS_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel2 == PMA_CLKS_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_sel == DELAY_PATH3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.pma_hclk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_pld_rx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_wren == WREN_DS_DEL_US_DEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_power_mode == FULL_WIDTH_PS_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_ctrl == BLKLOCK_IGNORE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_8g_eidleinfersel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_eye_monitor_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_pcie_switch_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_reser_out_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.rx_prbs_flags_sr_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.rx_true_b2b == B2B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.rx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_empty == EMPTY_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_full == FULL_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_mode == RXPHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pempty == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pfull == 6'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.rxfiford_post_ct_sel == RXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifowr_post_ct_sel == RXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.sclk_sel == SCLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.txfiford_post_ct_sel == TXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.txfifowr_post_ct_sel == TXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.word_align == WA_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_rx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_sr.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_sr.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_sr.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_sr.sr_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_sr.sr_testbus_sel == SSR_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_TX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_TX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.duplex_mode == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.dv_bond == DV_BOND_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.dv_gen == DV_GEN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_frm_gen_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_sel == FIFO_RD_PMA_AIB_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.fpll_shared_direct_async_in_sel == FPLL_SHARED_DIRECT_ASYNC_IN_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_burst == FRMGEN_BURST_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_bypass == FRMGEN_BYPASS_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_mfrm_length == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pipeln == FRMGEN_PIPELN_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pyld_ins == FRMGEN_PYLD_INS_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_wordslip == FRMGEN_WORDSLIP_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rst_sm_dis == ENABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_sel == DELAY_PATH3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk2_sel == PLD_CLK2_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.pma_aib_tx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_pld_tx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.sh_err == SH_ERR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.tx_datapath_tb_sel == TX_FIFO_TB1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_wren == WREN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_power_mode == FULL_WIDTH_PS_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.tx_hip_aib_ssr_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_10g_tx_bitslip_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_8g_tx_boundary_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_cnt_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_num_phase_shifts_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.tx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_full == FULL_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_mode == TXPHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pfull == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u8_2.hdpldadapt.hdpldadapt_tx_chnl.word_mark == WM_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xavmm1.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xavmm1.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xavmm1.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xavmm2.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xavmm2.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xavmm2.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_ber_margining_ctrl == AIB_BER_MARGINING_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_hps_ctrl_en == AIB_DLLSTR_ALIGN_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.aib_red_shift_en == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.op_mode == RX_DLL_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_HIGH_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_datasel_gr3 == AIB_DATASEL3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_red_pout_shiften == AIB_RED_POUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_tx_clkdiv == AIB_TX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp == AIB_TX_DCC_BYP_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_byp_iocsr_unused == AIB_TX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal == AIB_TX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_cont_cal_iocsr_unused == AIB_TX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft == AIB_TX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dft_sel == AIB_TX_DCC_DFT_MODE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_dft_sel == AIB_TX_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dll_entest == AIB_TX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctl_static == AIB_TX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_dy_ctlsel == AIB_TX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en == AIB_TX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_en_iocsr_unused == AIB_TX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_dn == AIB_TX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_manual_up == AIB_TX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_rst_prgmnvrt == AIB_TX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_dn_prgmnvrt == AIB_TX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_up_prgmnvrt == AIB_TX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_core_updnen == AIB_TX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dftmuxsel == AIB_TX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_dly_pst == AIB_TX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_en == AIB_TX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_hps_ctrl_en == AIB_TX_DCC_HPS_CTRL_EN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_lockreq_muxsel == AIB_TX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_new_dll == AIB_TX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_st_rst == AIB_TX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_tx_dcc_test_clk_pll_en_n == AIB_TX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_tx_halfcode == AIB_TX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.aib_tx_selflock == AIB_TX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.op_mode == TX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_HIGH_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_0.xaibnd_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.aib_fabric_pma_aib_tx_clk_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.aib_fabric_rx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.aib_fabric_rx_transfer_clk_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.aib_fabric_tx_sr_clk_in_hz == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.csr_clk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.speed_grade == DASH_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.adapter_base_addr == 10'd768
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_read == AVMM1_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.avmm1_cmdfifo_stop_write == AVMM1_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.avmm1_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.avmm1_nfhssi_calibratio_feature_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_dft_broadcast_en == DISABLE_ONLY_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.avmm1_pcs_force_mdio_dis_csr_ctrl == DISABLE_ONLY_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.avmm1_read_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.avmm1_uc_blocking_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_pfull == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_read == AVMM2_CMDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.avmm2_cmdfifo_stop_write == AVMM2_CMDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.avmm2_gate_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.avmm2_hip_sel == AVMM2_FOR_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_empty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_full == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.nfhssi_base_addr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_RX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_RX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.asn_bypass_pma_pcie_sw_done == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.asn_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_dll_reset_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_fifo_flush_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.asn_wait_for_pma_pcie_sw_done_cnt == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.duplex_mode == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.dv_mode == DV_MODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_double_read == FIFO_DOUBLE_READ_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_ins_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_rd_clk_sel == FIFO_RD_CLK_PLD_RX_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_del_sm_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.fifo_wr_clk_sel == FIFO_WR_CLK_RX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.gb_rx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rst_sm_dis == ENABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel1 == PMA_CLKS_OR_TXFIFORD_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk1_sel2 == PMA_CLKS_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.internal_clk2_sel2 == PMA_CLKS_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_delay_sel == DELAY_PATH3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.pma_hclk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.powermode_freq_hz_pld_rx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fastbond_wren == WREN_DS_DEL_US_DEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_power_mode == FULL_WIDTH_PS_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_ctrl == BLKLOCK_IGNORE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_8g_eidleinfersel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_eye_monitor_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_pcie_switch_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.rx_pld_pma_reser_out_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.rx_prbs_flags_sr_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.rx_true_b2b == B2B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.rx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_empty == EMPTY_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_full == FULL_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_mode == RXPHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pempty == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifo_pfull == 6'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.rxfiford_post_ct_sel == RXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.rxfifowr_post_ct_sel == RXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.sclk_sel == SCLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.txfiford_post_ct_sel == TXFIFORD_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.txfifowr_post_ct_sel == TXFIFOWR_SCLK_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.word_align == WA_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_rx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_sr.hip_mode == USER_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_sr.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_sr.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_sr.sr_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_sr.sr_testbus_sel == SSR_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk1_sel == AIB_CLK1_PLD_PCS_TX_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.aib_clk2_sel == AIB_CLK2_PLD_PMA_CLKDIV_TX_USER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_en == DFT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.bonding_dft_val == DFT_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.chnl_bonding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.comp_cnt == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.compin_sel == COMPIN_MASTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.ctrl_plane_bonding == INDIVIDUAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.ds_bypass_pipeln == DS_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.ds_last_chnl == DS_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.ds_master == DS_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.duplex_mode == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.dv_bond == DV_BOND_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.dv_gen == DV_GEN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_frm_gen_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_rd_clk_sel == FIFO_RD_PMA_AIB_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.fpll_shared_direct_async_in_sel == FPLL_SHARED_DIRECT_ASYNC_IN_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_burst == FRMGEN_BURST_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_bypass == FRMGEN_BYPASS_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_mfrm_length == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pipeln == FRMGEN_PIPELN_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_pyld_ins == FRMGEN_PYLD_INS_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.frmgen_wordslip == FRMGEN_WORDSLIP_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_idwidth == IDWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.gb_tx_odwidth == ODWIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.hip_mode == DISABLE_HIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rst_sm_dis == ENABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.indv == INDV_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.is_paired_with == Z1577B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.loopback_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.low_latency_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.pipe_mode == DISABLE_PIPE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_delay_sel == DELAY_PATH3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_inv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.pld_clk2_sel == PLD_CLK2_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.pma_aib_tx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_aib_fabric_rx_sr_clk_in == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.powermode_freq_hz_pld_tx_clk1_dcm == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.sh_err == SH_ERR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.stretch_num_stages == TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.tx_datapath_tb_sel == TX_FIFO_TB1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_rden == RDEN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fastbond_wren == WREN_DS_FAST_US_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_power_mode == FULL_WIDTH_PS_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.tx_hip_aib_ssr_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_10g_tx_bitslip_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_8g_tx_boundary_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_cnt_sel_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.tx_pld_pma_fpll_num_phase_shifts_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.tx_usertest_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_full == FULL_PC_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_mode == TXPHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.txfifo_pfull == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.us_bypass_pipeln == US_BYPASS_PIPELN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.us_last_chnl == US_LAST_CHNL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.us_master == US_MASTER_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.word_align_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.maib_ss_lib.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.word_mark == WM_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.barak_es_limit == BARAK_ES_LIMIT_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.bk0_tx_linerate_actual == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.force_sup_mode_to_usermode_for_all == EACH_SS_CHOOSES
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.is_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.is_cvp_capable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.is_cvp_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.is_present == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.speed_grade == SPEED_GRADE_DASH2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.topology == UX16E400GPTP_XX_DISABLED_XX_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.ux0_tx_linerate_actual == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.aib_hssi_rx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.aib_hssi_rx_transfer_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.aib_hssi_tx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.aib_hssi_tx_sr_clk_out_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.aib_hssi_tx_transfer_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.bti_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.direct_sel0 == DIRECT_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.e200g_aib1_tx_st_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.e200g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.e200g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.e200g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.e200g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.e200g_rx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.e200g_tx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.e400g_aib1_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.e400g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.e400g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.e400g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.e400g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.e400g_rx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.e400g_tx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.global_avmm_clk_hz == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.internal_clk1_source == INTERNAL_CLK1_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.internal_clk2_source == INTERNAL_CLK2_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.pcie_pld_2x_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.pcie_pld_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.pcie_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.pcie_tx_transfer_div2_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.pld_pcs_rx_clk_out_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.pld_pcs_tx_clk_out_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.pma_aib_tx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.powermode_ac_avmm1 == AC_AVMM1_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.powermode_ac_avmm2 == AC_AVMM2_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.powermode_ac_global_avmm == GLOBAL_AVMM_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.powermode_ac_rx_datapath == AC_RX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.powermode_ac_sr == AC_SR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.powermode_ac_tx_datapath == AC_TX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.powermode_dc == POWERUP_DC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.powermode_freq_hz_aib_rx_sr_clk_in == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.powermode_freq_hz_aib_rx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.powermode_freq_hz_aib_tx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.powermode_freq_hz_global_avmm_clk == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.sr_prot_mode == SR_PROT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.async_direct_sel0 == DIRECT_SEL0_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.async_direct_sel1 == DIRECT_SEL1_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.async_direct_sel2 == DIRECT_SEL2_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.async_direct_sel3 == DIRECT_SEL3_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.avmm1_free_run_div_clk == AVMM1_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.avmm1_write_resp_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.avmm2_free_run_div_clk == AVMM2_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.avmm2_global_usr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.dfd_cntr_inc_value == 9'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.dfd_cntr_rst_b == CNTR_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_ch_sel == GP0_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_cntr_data_sel == GP0_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_rsvd == GP0_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_testbus_sel == GP0_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_ch_sel == GP1_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_cntr_data_sel == GP1_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_rsvd == GP1_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_testbus_sel == GP1_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.dfd_mux_rst_b == MUX_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.hwcfg_adpt_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.hwcfg_aib_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.hwcfg_mode == BLOCK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.sr_prot_map_mode == MAP_SR_PROT_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.sr_test_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.sr_xcvr_map_mode == MAP_SR_XCVR_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.adapter_lpbk_mode == LOOPBACK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.aib_lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.async_direct_hip_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.datapath_mapping_mode == MAP_RX_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_sel == FIFO_RD_BTI_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_sel == FIFO_WR_PCIE_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.hrdrst_rst_sm_dis == DISABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel == FEEDTHRU_CLK1_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel0 == TXFIFOWR_FROM_AIB_MUX_CLK1_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel1 == FEEDTHRU_CLKS_OR_TXFIFORD_PRE_OR_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel2 == PMA_CLKS_OR_TXFIFORD_PRE_CT_MUX_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel3 == PMA_CLKS_CLK1_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel == FEEDTHRU_CLK0_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel0 == RXFIFORD_TO_AIB_MUX_CLK2_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_PRE_OR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel2 == PMA_CLKS_OR_RXFIFOWR_PRE_CT_MUX_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel3 == PMA_CLKS_CLK2_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.msb_pipeline_byp == MSB_PIPE_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.pld_pcs_rx_clk_out_sel == PLD_PCS_RX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.pma_aib_rx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.pma_coreclkin_sel == PMA_CORECLKIN_PLD_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.rx_10g_krfec_rx_diag_data_status_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.rx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.rx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.rx_parity_sel == FUNC_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.rx_pcs_testbus_sel == DIRECT_TR_TB_BIT0_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.rx_pcspma_testbus_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_a1a2_k1k2_flag_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_wa_boundary_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_pcie_sw_done_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_reser_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_testbus_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.rx_pld_test_data_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_num_stages == RMFFLAG_TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.rx_user_clk_rst_sel == RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.rx_user_clk_sel == RX_USER_CLK_E400G_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.rx_usertest_sel == DIRECT_TR_USERTEST3_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.rxfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.rxfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.rxfifo_mode == RXBYPASS_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.rxfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.rxfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.rxfiford_post_ct_sel == RXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.rxfiford_to_aib_sel == RXFIFORD_SCLK_TO_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.rxfifowr_post_ct_sel == RXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.rxfifowr_pre_ct_sel == RXFIFOWR_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.txfiford_post_ct_sel == TXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.txfiford_pre_ct_sel == TXFIFORD_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.txfifowr_from_aib_sel == TXFIFOWR_SCLK_FROM_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.txfifowr_post_ct_sel == TXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_rxchnl.word_mark == WM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_sr.sr_free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_sr.sr_osc_clk_div_sel == NON_DIV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.datapath_mapping_mode == MAP_TX_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.dv_gating == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.fifo_double_read == FIFO_DOUBLE_READ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_sel == FIFO_RD_PCIE_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.hrdrst_rst_sm_dis == DISABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.pld_pcs_tx_clk_out_sel == PLD_PCS_TX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.pma_aib_tx_clk_sel == PMA_AIB_TX_CLK_BTI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.tx_datapath_tb_sel == WA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.tx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.tx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.tx_latency_src_xcvrif == LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.tx_rev_lpbk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e200g_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e400g_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.tx_transfer_div2_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.tx_user_clk_rst_sel == TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.tx_user_clk_sel == TX_USER_CLK_E400G_DIV4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.tx_usertest_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.txfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.txfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.gdr_aibadapter.adapt_txchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_dc == AVMM1_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_dc == AVMM2_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr1 == AIB_DDR1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_clkdiv == AIB_RX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp == AIB_RX_DCC_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp_iocsr_unused == AIB_RX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal == AIB_RX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal_iocsr_unused == AIB_RX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft == AIB_RX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft_sel == AIB_RX_DCC_DFT_MODE1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dll_entest == AIB_RX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctl_static == AIB_RX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctlsel == AIB_RX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en == AIB_RX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en_iocsr_unused == AIB_RX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_dn == AIB_RX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_up == AIB_RX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_pi_slw == AIB_RX_DCC_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_rst_prgmnvrt == AIB_RX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_dn_prgmnvrt == AIB_RX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_up_prgmnvrt == AIB_RX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_updnen == AIB_RX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dftmuxsel == AIB_RX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dly_pst == AIB_RX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_en == AIB_RX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_lockreq_muxsel == AIB_RX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll == AIB_RX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll2 == AIB_RX_DCC_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_rst == AIB_RX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_test_clk_pll_en_n == AIB_RX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_halfcode == AIB_RX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_selflock == AIB_RX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.op_mode == RX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_dc == RXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dcc_dll_dft_sel == AIB_DLLSTR_ALIGN_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dft_ch_muxsel == AIB_DLLSTR_ALIGN_DFT_CH_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_pi_slw == AIB_DLLSTR_ALIGN_PI_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll == AIB_DLLSTR_ALIGN_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll2 == AIB_DLLSTR_ALIGN_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_pinp_shiften == AIB_RED_PINP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.op_mode == TX_DLL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_dc == TXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_0.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.aib_hssi_rx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.aib_hssi_rx_transfer_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.aib_hssi_tx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.aib_hssi_tx_sr_clk_out_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.aib_hssi_tx_transfer_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.bti_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.direct_sel0 == DIRECT_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.e200g_aib1_tx_st_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.e200g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.e200g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.e200g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.e200g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.e200g_rx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.e200g_tx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.e400g_aib1_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.e400g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.e400g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.e400g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.e400g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.e400g_rx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.e400g_tx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.global_avmm_clk_hz == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.internal_clk1_source == INTERNAL_CLK1_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.internal_clk2_source == INTERNAL_CLK2_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.pcie_pld_2x_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.pcie_pld_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.pcie_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.pcie_tx_transfer_div2_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.pld_pcs_rx_clk_out_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.pld_pcs_tx_clk_out_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.pma_aib_tx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.powermode_ac_avmm1 == AC_AVMM1_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.powermode_ac_avmm2 == AC_AVMM2_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.powermode_ac_global_avmm == GLOBAL_AVMM_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.powermode_ac_rx_datapath == AC_RX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.powermode_ac_sr == AC_SR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.powermode_ac_tx_datapath == AC_TX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.powermode_dc == POWERUP_DC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.powermode_freq_hz_aib_rx_sr_clk_in == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.powermode_freq_hz_aib_rx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.powermode_freq_hz_aib_tx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.powermode_freq_hz_global_avmm_clk == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.sr_prot_mode == SR_PROT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.async_direct_sel0 == DIRECT_SEL0_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.async_direct_sel1 == DIRECT_SEL1_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.async_direct_sel2 == DIRECT_SEL2_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.async_direct_sel3 == DIRECT_SEL3_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.avmm1_free_run_div_clk == AVMM1_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.avmm1_write_resp_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.avmm2_free_run_div_clk == AVMM2_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.avmm2_global_usr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.dfd_cntr_inc_value == 9'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.dfd_cntr_rst_b == CNTR_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_ch_sel == GP0_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_cntr_data_sel == GP0_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_rsvd == GP0_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_testbus_sel == GP0_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_ch_sel == GP1_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_cntr_data_sel == GP1_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_rsvd == GP1_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_testbus_sel == GP1_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.dfd_mux_rst_b == MUX_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.hwcfg_adpt_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.hwcfg_aib_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.hwcfg_mode == BLOCK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.sr_prot_map_mode == MAP_SR_PROT_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.sr_test_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.sr_xcvr_map_mode == MAP_SR_XCVR_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.adapter_lpbk_mode == LOOPBACK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.aib_lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.async_direct_hip_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.datapath_mapping_mode == MAP_RX_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_sel == FIFO_RD_BTI_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_sel == FIFO_WR_PCIE_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.hrdrst_rst_sm_dis == DISABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel == FEEDTHRU_CLK1_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel0 == TXFIFOWR_FROM_AIB_MUX_CLK1_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel1 == FEEDTHRU_CLKS_OR_TXFIFORD_PRE_OR_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel2 == PMA_CLKS_OR_TXFIFORD_PRE_CT_MUX_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel3 == PMA_CLKS_CLK1_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel == FEEDTHRU_CLK0_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel0 == RXFIFORD_TO_AIB_MUX_CLK2_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_PRE_OR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel2 == PMA_CLKS_OR_RXFIFOWR_PRE_CT_MUX_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel3 == PMA_CLKS_CLK2_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.msb_pipeline_byp == MSB_PIPE_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.pld_pcs_rx_clk_out_sel == PLD_PCS_RX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.pma_aib_rx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.pma_coreclkin_sel == PMA_CORECLKIN_PLD_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.rx_10g_krfec_rx_diag_data_status_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.rx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.rx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.rx_parity_sel == FUNC_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.rx_pcs_testbus_sel == DIRECT_TR_TB_BIT0_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.rx_pcspma_testbus_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_a1a2_k1k2_flag_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_wa_boundary_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_pcie_sw_done_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_reser_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_testbus_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.rx_pld_test_data_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_num_stages == RMFFLAG_TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.rx_user_clk_rst_sel == RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.rx_user_clk_sel == RX_USER_CLK_E400G_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.rx_usertest_sel == DIRECT_TR_USERTEST3_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.rxfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.rxfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.rxfifo_mode == RXBYPASS_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.rxfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.rxfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.rxfiford_post_ct_sel == RXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.rxfiford_to_aib_sel == RXFIFORD_SCLK_TO_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.rxfifowr_post_ct_sel == RXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.rxfifowr_pre_ct_sel == RXFIFOWR_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.txfiford_post_ct_sel == TXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.txfiford_pre_ct_sel == TXFIFORD_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.txfifowr_from_aib_sel == TXFIFOWR_SCLK_FROM_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.txfifowr_post_ct_sel == TXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_rxchnl.word_mark == WM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_sr.sr_free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_sr.sr_osc_clk_div_sel == NON_DIV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.datapath_mapping_mode == MAP_TX_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.dv_gating == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.fifo_double_read == FIFO_DOUBLE_READ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_sel == FIFO_RD_PCIE_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.hrdrst_rst_sm_dis == DISABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.pld_pcs_tx_clk_out_sel == PLD_PCS_TX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.pma_aib_tx_clk_sel == PMA_AIB_TX_CLK_BTI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.tx_datapath_tb_sel == WA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.tx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.tx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.tx_latency_src_xcvrif == LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.tx_rev_lpbk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e200g_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e400g_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.tx_transfer_div2_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.tx_user_clk_rst_sel == TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.tx_user_clk_sel == TX_USER_CLK_E400G_DIV4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.tx_usertest_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.txfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.txfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.gdr_aibadapter.adapt_txchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_dc == AVMM1_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_dc == AVMM2_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr1 == AIB_DDR1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_clkdiv == AIB_RX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp == AIB_RX_DCC_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp_iocsr_unused == AIB_RX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal == AIB_RX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal_iocsr_unused == AIB_RX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft == AIB_RX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft_sel == AIB_RX_DCC_DFT_MODE1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dll_entest == AIB_RX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctl_static == AIB_RX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctlsel == AIB_RX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en == AIB_RX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en_iocsr_unused == AIB_RX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_dn == AIB_RX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_up == AIB_RX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_pi_slw == AIB_RX_DCC_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_rst_prgmnvrt == AIB_RX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_dn_prgmnvrt == AIB_RX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_up_prgmnvrt == AIB_RX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_updnen == AIB_RX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dftmuxsel == AIB_RX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dly_pst == AIB_RX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_en == AIB_RX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_lockreq_muxsel == AIB_RX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll == AIB_RX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll2 == AIB_RX_DCC_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_rst == AIB_RX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_test_clk_pll_en_n == AIB_RX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_halfcode == AIB_RX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_selflock == AIB_RX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.op_mode == RX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_dc == RXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dcc_dll_dft_sel == AIB_DLLSTR_ALIGN_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dft_ch_muxsel == AIB_DLLSTR_ALIGN_DFT_CH_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_pi_slw == AIB_DLLSTR_ALIGN_PI_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll == AIB_DLLSTR_ALIGN_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll2 == AIB_DLLSTR_ALIGN_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_pinp_shiften == AIB_RED_PINP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.op_mode == TX_DLL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_dc == TXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_1.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.aib_hssi_rx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.aib_hssi_rx_transfer_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.aib_hssi_tx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.aib_hssi_tx_sr_clk_out_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.aib_hssi_tx_transfer_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.aib_tx_user_clk_hz == 32'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.bti_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.direct_sel0 == DIRECT_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.e200g_aib1_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.e200g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.e200g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.e200g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.e200g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.e200g_rx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.e200g_tx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.e400g_aib1_tx_st_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.e400g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.e400g_aib2_tx_st_clk_hz == 32'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.e400g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.e400g_aib3_tx_st_clk_hz == 32'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.e400g_rx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.e400g_tx_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.global_avmm_clk_hz == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.internal_clk1_source == INTERNAL_CLK1_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.internal_clk2_source == INTERNAL_CLK2_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.pcie_pld_2x_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.pcie_pld_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.pcie_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.pcie_tx_transfer_div2_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.pld_pcs_rx_clk_out_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.pld_pcs_tx_clk_out_hz == 32'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.pma_aib_tx_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.powermode_ac_avmm1 == AC_AVMM1_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.powermode_ac_avmm2 == AC_AVMM2_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.powermode_ac_global_avmm == GLOBAL_AVMM_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.powermode_ac_rx_datapath == AC_RX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.powermode_ac_sr == AC_SR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.powermode_ac_tx_datapath == AC_TX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.powermode_dc == POWERUP_DC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.powermode_freq_hz_aib_rx_sr_clk_in == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.powermode_freq_hz_aib_rx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.powermode_freq_hz_aib_tx_transfer_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.powermode_freq_hz_global_avmm_clk == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.sr_prot_mode == SR_PROT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.async_direct_sel0 == DIRECT_SEL0_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.async_direct_sel1 == DIRECT_SEL1_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.async_direct_sel2 == DIRECT_SEL2_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.async_direct_sel3 == DIRECT_SEL3_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.avmm1_free_run_div_clk == AVMM1_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.avmm1_write_resp_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.avmm2_free_run_div_clk == AVMM2_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.avmm2_global_usr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.dfd_cntr_inc_value == 9'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.dfd_cntr_rst_b == CNTR_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_ch_sel == GP0_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_cntr_data_sel == GP0_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_rsvd == GP0_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_testbus_sel == GP0_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_ch_sel == GP1_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_cntr_data_sel == GP1_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_rsvd == GP1_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_testbus_sel == GP1_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.dfd_mux_rst_b == MUX_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.hwcfg_adpt_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.hwcfg_aib_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.hwcfg_mode == BLOCK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.sr_prot_map_mode == MAP_SR_PROT_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.sr_test_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.sr_xcvr_map_mode == MAP_SR_XCVR_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.adapter_lpbk_mode == LOOPBACK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.aib_lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.async_direct_hip_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.datapath_mapping_mode == MAP_RX_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_sel == FIFO_RD_BTI_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_sel == FIFO_WR_PCIE_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.hrdrst_rst_sm_dis == DISABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel == FEEDTHRU_CLK1_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel0 == TXFIFOWR_FROM_AIB_MUX_CLK1_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel1 == FEEDTHRU_CLKS_OR_TXFIFORD_PRE_OR_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel2 == PMA_CLKS_OR_TXFIFORD_PRE_CT_MUX_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel3 == PMA_CLKS_CLK1_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel == FEEDTHRU_CLK0_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel0 == RXFIFORD_TO_AIB_MUX_CLK2_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_PRE_OR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel2 == PMA_CLKS_OR_RXFIFOWR_PRE_CT_MUX_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel3 == PMA_CLKS_CLK2_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.msb_pipeline_byp == MSB_PIPE_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.pld_pcs_rx_clk_out_sel == PLD_PCS_RX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.pma_aib_rx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.pma_coreclkin_sel == PMA_CORECLKIN_PLD_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.rx_10g_krfec_rx_diag_data_status_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.rx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.rx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.rx_parity_sel == FUNC_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.rx_pcs_testbus_sel == DIRECT_TR_TB_BIT0_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.rx_pcspma_testbus_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_a1a2_k1k2_flag_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_wa_boundary_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_pcie_sw_done_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_reser_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_testbus_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.rx_pld_test_data_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_num_stages == RMFFLAG_TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.rx_user_clk_rst_sel == RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.rx_user_clk_sel == RX_USER_CLK_E400G_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.rx_usertest_sel == DIRECT_TR_USERTEST3_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.rxfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.rxfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.rxfifo_mode == RXBYPASS_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.rxfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.rxfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.rxfiford_post_ct_sel == RXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.rxfiford_to_aib_sel == RXFIFORD_SCLK_TO_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.rxfifowr_post_ct_sel == RXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.rxfifowr_pre_ct_sel == RXFIFOWR_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.txfiford_post_ct_sel == TXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.txfiford_pre_ct_sel == TXFIFORD_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.txfifowr_from_aib_sel == TXFIFOWR_SCLK_FROM_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.txfifowr_post_ct_sel == TXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_rxchnl.word_mark == WM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_sr.sr_free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_sr.sr_osc_clk_div_sel == NON_DIV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.datapath_mapping_mode == MAP_TX_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.dv_gating == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.fifo_double_read == FIFO_DOUBLE_READ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_sel == FIFO_RD_PCIE_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.hrdrst_rst_sm_dis == ENABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.pld_pcs_tx_clk_out_sel == PLD_PCS_TX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.pma_aib_tx_clk_sel == PMA_AIB_TX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.tx_datapath_tb_sel == WA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.tx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.tx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.tx_latency_src_xcvrif == LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.tx_rev_lpbk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e200g_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e400g_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.tx_transfer_div2_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.tx_user_clk_rst_sel == TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.tx_user_clk_sel == TX_USER_CLK_E400G_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.tx_usertest_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.txfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.txfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.gdr_aibadapter.adapt_txchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_dc == AVMM1_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_dc == AVMM2_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr1 == AIB_DDR1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_clkdiv == AIB_RX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp == AIB_RX_DCC_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp_iocsr_unused == AIB_RX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal == AIB_RX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal_iocsr_unused == AIB_RX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft == AIB_RX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft_sel == AIB_RX_DCC_DFT_MODE1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dll_entest == AIB_RX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctl_static == AIB_RX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctlsel == AIB_RX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en == AIB_RX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en_iocsr_unused == AIB_RX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_dn == AIB_RX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_up == AIB_RX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_pi_slw == AIB_RX_DCC_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_rst_prgmnvrt == AIB_RX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_dn_prgmnvrt == AIB_RX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_up_prgmnvrt == AIB_RX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_updnen == AIB_RX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dftmuxsel == AIB_RX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dly_pst == AIB_RX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_en == AIB_RX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_lockreq_muxsel == AIB_RX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll == AIB_RX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll2 == AIB_RX_DCC_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_rst == AIB_RX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_test_clk_pll_en_n == AIB_RX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_halfcode == AIB_RX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_selflock == AIB_RX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.op_mode == RX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_dc == RXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dcc_dll_dft_sel == AIB_DLLSTR_ALIGN_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dft_ch_muxsel == AIB_DLLSTR_ALIGN_DFT_CH_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_pi_slw == AIB_DLLSTR_ALIGN_PI_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll == AIB_DLLSTR_ALIGN_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll2 == AIB_DLLSTR_ALIGN_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_pinp_shiften == AIB_RED_PINP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.op_mode == TX_DLL_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_HIGH_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_dc == TXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_10.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.aib_hssi_rx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.aib_hssi_rx_transfer_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.aib_hssi_tx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.aib_hssi_tx_sr_clk_out_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.aib_hssi_tx_transfer_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.aib_rx_user_clk_hz == 32'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.aib_tx_user_clk_hz == 32'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.bti_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.direct_sel0 == DIRECT_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.e200g_aib1_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.e200g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.e200g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.e200g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.e200g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.e200g_rx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.e200g_tx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.e400g_aib1_tx_st_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.e400g_aib2_rx_st_clk_hz == 32'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.e400g_aib2_tx_st_clk_hz == 32'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.e400g_aib3_rx_st_clk_hz == 32'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.e400g_aib3_tx_st_clk_hz == 32'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.e400g_rx_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.e400g_tx_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.global_avmm_clk_hz == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.internal_clk1_source == INTERNAL_CLK1_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.internal_clk2_source == INTERNAL_CLK2_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.pcie_pld_2x_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.pcie_pld_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.pcie_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.pcie_tx_transfer_div2_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.pld_pcs_rx_clk_out_hz == 32'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.pld_pcs_tx_clk_out_hz == 32'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.pma_aib_tx_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.powermode_ac_avmm1 == AC_AVMM1_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.powermode_ac_avmm2 == AC_AVMM2_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.powermode_ac_global_avmm == GLOBAL_AVMM_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.powermode_ac_rx_datapath == AC_RX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.powermode_ac_sr == AC_SR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.powermode_ac_tx_datapath == AC_TX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.powermode_dc == POWERUP_DC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.powermode_freq_hz_aib_rx_sr_clk_in == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.powermode_freq_hz_aib_rx_transfer_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.powermode_freq_hz_aib_tx_transfer_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.powermode_freq_hz_global_avmm_clk == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.sr_prot_mode == SR_PROT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.async_direct_sel0 == DIRECT_SEL0_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.async_direct_sel1 == DIRECT_SEL1_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.async_direct_sel2 == DIRECT_SEL2_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.async_direct_sel3 == DIRECT_SEL3_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.avmm1_free_run_div_clk == AVMM1_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.avmm1_write_resp_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.avmm2_free_run_div_clk == AVMM2_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.avmm2_global_usr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.dfd_cntr_inc_value == 9'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.dfd_cntr_rst_b == CNTR_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_ch_sel == GP0_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_cntr_data_sel == GP0_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_rsvd == GP0_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_testbus_sel == GP0_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_ch_sel == GP1_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_cntr_data_sel == GP1_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_rsvd == GP1_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_testbus_sel == GP1_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.dfd_mux_rst_b == MUX_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.hwcfg_adpt_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.hwcfg_aib_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.hwcfg_mode == BLOCK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.sr_prot_map_mode == MAP_SR_PROT_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.sr_test_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.sr_xcvr_map_mode == MAP_SR_XCVR_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.adapter_lpbk_mode == LOOPBACK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.aib_lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.async_direct_hip_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.datapath_mapping_mode == MAP_RX_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_sel == FIFO_RD_E400G_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_sel == FIFO_WR_PCIE_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.hrdrst_rst_sm_dis == ENABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel == FEEDTHRU_CLK1_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel0 == TXFIFOWR_FROM_AIB_MUX_CLK1_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel1 == FEEDTHRU_CLKS_OR_TXFIFORD_PRE_OR_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel2 == PMA_CLKS_OR_TXFIFORD_PRE_CT_MUX_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel3 == PMA_CLKS_CLK1_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel == FEEDTHRU_CLK0_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel0 == RXFIFORD_TO_AIB_MUX_CLK2_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_PRE_OR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel2 == PMA_CLKS_OR_RXFIFOWR_PRE_CT_MUX_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel3 == PMA_CLKS_CLK2_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.msb_pipeline_byp == MSB_PIPE_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.pld_pcs_rx_clk_out_sel == PLD_PCS_RX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.pma_aib_rx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.pma_coreclkin_sel == PMA_CORECLKIN_PLD_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.rx_10g_krfec_rx_diag_data_status_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.rx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.rx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.rx_parity_sel == FUNC_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.rx_pcs_testbus_sel == DIRECT_TR_TB_BIT0_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.rx_pcspma_testbus_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_a1a2_k1k2_flag_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_wa_boundary_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_pcie_sw_done_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_reser_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_testbus_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.rx_pld_test_data_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_num_stages == RMFFLAG_TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.rx_user_clk_rst_sel == RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.rx_user_clk_sel == RX_USER_CLK_E400G_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.rx_usertest_sel == DIRECT_TR_USERTEST3_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.rxfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.rxfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.rxfifo_mode == RXBYPASS_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.rxfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.rxfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.rxfiford_post_ct_sel == RXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.rxfiford_to_aib_sel == RXFIFORD_SCLK_TO_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.rxfifowr_post_ct_sel == RXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.rxfifowr_pre_ct_sel == RXFIFOWR_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.txfiford_post_ct_sel == TXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.txfiford_pre_ct_sel == TXFIFORD_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.txfifowr_from_aib_sel == TXFIFOWR_SCLK_FROM_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.txfifowr_post_ct_sel == TXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_rxchnl.word_mark == WM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_sr.sr_free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_sr.sr_osc_clk_div_sel == NON_DIV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.datapath_mapping_mode == MAP_TX_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.dv_gating == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.fifo_double_read == FIFO_DOUBLE_READ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_sel == FIFO_RD_PCIE_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.hrdrst_rst_sm_dis == ENABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.pld_pcs_tx_clk_out_sel == PLD_PCS_TX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.pma_aib_tx_clk_sel == PMA_AIB_TX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.tx_datapath_tb_sel == WA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.tx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.tx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.tx_latency_src_xcvrif == LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.tx_rev_lpbk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e200g_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e400g_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.tx_transfer_div2_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.tx_user_clk_rst_sel == TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.tx_user_clk_sel == TX_USER_CLK_E400G_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.tx_usertest_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.txfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.txfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.gdr_aibadapter.adapt_txchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_dc == AVMM1_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_dc == AVMM2_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr1 == AIB_DDR1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_clkdiv == AIB_RX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp == AIB_RX_DCC_BYP_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp_iocsr_unused == AIB_RX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal == AIB_RX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal_iocsr_unused == AIB_RX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft == AIB_RX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft_sel == AIB_RX_DCC_DFT_MODE1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dll_entest == AIB_RX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctl_static == AIB_RX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctlsel == AIB_RX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en == AIB_RX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en_iocsr_unused == AIB_RX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_dn == AIB_RX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_up == AIB_RX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_pi_slw == AIB_RX_DCC_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_rst_prgmnvrt == AIB_RX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_dn_prgmnvrt == AIB_RX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_up_prgmnvrt == AIB_RX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_updnen == AIB_RX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dftmuxsel == AIB_RX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dly_pst == AIB_RX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_en == AIB_RX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_lockreq_muxsel == AIB_RX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll == AIB_RX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll2 == AIB_RX_DCC_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_rst == AIB_RX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_test_clk_pll_en_n == AIB_RX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_halfcode == AIB_RX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_selflock == AIB_RX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.op_mode == RX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_HIGH_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_dc == RXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dcc_dll_dft_sel == AIB_DLLSTR_ALIGN_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dft_ch_muxsel == AIB_DLLSTR_ALIGN_DFT_CH_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_pi_slw == AIB_DLLSTR_ALIGN_PI_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll == AIB_DLLSTR_ALIGN_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll2 == AIB_DLLSTR_ALIGN_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_pinp_shiften == AIB_RED_PINP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.op_mode == TX_DLL_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_HIGH_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_dc == TXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_11.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.aib_hssi_rx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.aib_hssi_rx_transfer_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.aib_hssi_tx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.aib_hssi_tx_sr_clk_out_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.aib_hssi_tx_transfer_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.bti_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.direct_sel0 == DIRECT_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.e200g_aib1_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.e200g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.e200g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.e200g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.e200g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.e200g_rx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.e200g_tx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.e400g_aib1_tx_st_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.e400g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.e400g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.e400g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.e400g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.e400g_rx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.e400g_tx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.global_avmm_clk_hz == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.internal_clk1_source == INTERNAL_CLK1_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.internal_clk2_source == INTERNAL_CLK2_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.pcie_pld_2x_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.pcie_pld_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.pcie_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.pcie_tx_transfer_div2_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.pld_pcs_rx_clk_out_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.pld_pcs_tx_clk_out_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.pma_aib_tx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.powermode_ac_avmm1 == AC_AVMM1_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.powermode_ac_avmm2 == AC_AVMM2_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.powermode_ac_global_avmm == GLOBAL_AVMM_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.powermode_ac_rx_datapath == AC_RX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.powermode_ac_sr == AC_SR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.powermode_ac_tx_datapath == AC_TX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.powermode_dc == POWERUP_DC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.powermode_freq_hz_aib_rx_sr_clk_in == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.powermode_freq_hz_aib_rx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.powermode_freq_hz_aib_tx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.powermode_freq_hz_global_avmm_clk == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.sr_prot_mode == SR_PROT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.async_direct_sel0 == DIRECT_SEL0_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.async_direct_sel1 == DIRECT_SEL1_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.async_direct_sel2 == DIRECT_SEL2_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.async_direct_sel3 == DIRECT_SEL3_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.avmm1_free_run_div_clk == AVMM1_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.avmm1_write_resp_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.avmm2_free_run_div_clk == AVMM2_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.avmm2_global_usr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.dfd_cntr_inc_value == 9'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.dfd_cntr_rst_b == CNTR_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_ch_sel == GP0_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_cntr_data_sel == GP0_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_rsvd == GP0_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_testbus_sel == GP0_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_ch_sel == GP1_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_cntr_data_sel == GP1_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_rsvd == GP1_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_testbus_sel == GP1_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.dfd_mux_rst_b == MUX_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.hwcfg_adpt_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.hwcfg_aib_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.hwcfg_mode == BLOCK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.sr_prot_map_mode == MAP_SR_PROT_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.sr_test_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.sr_xcvr_map_mode == MAP_SR_XCVR_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.adapter_lpbk_mode == LOOPBACK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.aib_lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.async_direct_hip_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.datapath_mapping_mode == MAP_RX_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_sel == FIFO_RD_BTI_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_sel == FIFO_WR_PCIE_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.hrdrst_rst_sm_dis == DISABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel == FEEDTHRU_CLK1_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel0 == TXFIFOWR_FROM_AIB_MUX_CLK1_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel1 == FEEDTHRU_CLKS_OR_TXFIFORD_PRE_OR_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel2 == PMA_CLKS_OR_TXFIFORD_PRE_CT_MUX_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel3 == PMA_CLKS_CLK1_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel == FEEDTHRU_CLK0_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel0 == RXFIFORD_TO_AIB_MUX_CLK2_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_PRE_OR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel2 == PMA_CLKS_OR_RXFIFOWR_PRE_CT_MUX_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel3 == PMA_CLKS_CLK2_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.msb_pipeline_byp == MSB_PIPE_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.pld_pcs_rx_clk_out_sel == PLD_PCS_RX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.pma_aib_rx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.pma_coreclkin_sel == PMA_CORECLKIN_PLD_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.rx_10g_krfec_rx_diag_data_status_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.rx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.rx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.rx_parity_sel == FUNC_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.rx_pcs_testbus_sel == DIRECT_TR_TB_BIT0_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.rx_pcspma_testbus_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_a1a2_k1k2_flag_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_wa_boundary_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_pcie_sw_done_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_reser_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_testbus_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.rx_pld_test_data_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_num_stages == RMFFLAG_TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.rx_user_clk_rst_sel == RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.rx_user_clk_sel == RX_USER_CLK_E400G_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.rx_usertest_sel == DIRECT_TR_USERTEST3_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.rxfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.rxfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.rxfifo_mode == RXBYPASS_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.rxfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.rxfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.rxfiford_post_ct_sel == RXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.rxfiford_to_aib_sel == RXFIFORD_SCLK_TO_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.rxfifowr_post_ct_sel == RXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.rxfifowr_pre_ct_sel == RXFIFOWR_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.txfiford_post_ct_sel == TXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.txfiford_pre_ct_sel == TXFIFORD_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.txfifowr_from_aib_sel == TXFIFOWR_SCLK_FROM_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.txfifowr_post_ct_sel == TXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_rxchnl.word_mark == WM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_sr.sr_free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_sr.sr_osc_clk_div_sel == NON_DIV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.datapath_mapping_mode == MAP_TX_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.dv_gating == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.fifo_double_read == FIFO_DOUBLE_READ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_sel == FIFO_RD_PCIE_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.hrdrst_rst_sm_dis == DISABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.pld_pcs_tx_clk_out_sel == PLD_PCS_TX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.pma_aib_tx_clk_sel == PMA_AIB_TX_CLK_BTI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.tx_datapath_tb_sel == WA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.tx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.tx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.tx_latency_src_xcvrif == LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.tx_rev_lpbk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e200g_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e400g_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.tx_transfer_div2_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.tx_user_clk_rst_sel == TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.tx_user_clk_sel == TX_USER_CLK_E400G_DIV4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.tx_usertest_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.txfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.txfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.gdr_aibadapter.adapt_txchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_dc == AVMM1_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_dc == AVMM2_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr1 == AIB_DDR1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_clkdiv == AIB_RX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp == AIB_RX_DCC_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp_iocsr_unused == AIB_RX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal == AIB_RX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal_iocsr_unused == AIB_RX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft == AIB_RX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft_sel == AIB_RX_DCC_DFT_MODE1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dll_entest == AIB_RX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctl_static == AIB_RX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctlsel == AIB_RX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en == AIB_RX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en_iocsr_unused == AIB_RX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_dn == AIB_RX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_up == AIB_RX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_pi_slw == AIB_RX_DCC_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_rst_prgmnvrt == AIB_RX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_dn_prgmnvrt == AIB_RX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_up_prgmnvrt == AIB_RX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_updnen == AIB_RX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dftmuxsel == AIB_RX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dly_pst == AIB_RX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_en == AIB_RX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_lockreq_muxsel == AIB_RX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll == AIB_RX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll2 == AIB_RX_DCC_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_rst == AIB_RX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_test_clk_pll_en_n == AIB_RX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_halfcode == AIB_RX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_selflock == AIB_RX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.op_mode == RX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_dc == RXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dcc_dll_dft_sel == AIB_DLLSTR_ALIGN_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dft_ch_muxsel == AIB_DLLSTR_ALIGN_DFT_CH_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_pi_slw == AIB_DLLSTR_ALIGN_PI_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll == AIB_DLLSTR_ALIGN_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll2 == AIB_DLLSTR_ALIGN_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_pinp_shiften == AIB_RED_PINP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.op_mode == TX_DLL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_dc == TXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_12.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.aib_hssi_rx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.aib_hssi_rx_transfer_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.aib_hssi_tx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.aib_hssi_tx_sr_clk_out_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.aib_hssi_tx_transfer_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.aib_tx_user_clk_hz == 32'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.bti_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.direct_sel0 == DIRECT_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.e200g_aib1_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.e200g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.e200g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.e200g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.e200g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.e200g_rx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.e200g_tx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.e400g_aib1_tx_st_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.e400g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.e400g_aib2_tx_st_clk_hz == 32'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.e400g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.e400g_aib3_tx_st_clk_hz == 32'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.e400g_rx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.e400g_tx_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.global_avmm_clk_hz == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.internal_clk1_source == INTERNAL_CLK1_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.internal_clk2_source == INTERNAL_CLK2_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.pcie_pld_2x_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.pcie_pld_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.pcie_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.pcie_tx_transfer_div2_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.pld_pcs_rx_clk_out_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.pld_pcs_tx_clk_out_hz == 32'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.pma_aib_tx_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.powermode_ac_avmm1 == AC_AVMM1_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.powermode_ac_avmm2 == AC_AVMM2_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.powermode_ac_global_avmm == GLOBAL_AVMM_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.powermode_ac_rx_datapath == AC_RX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.powermode_ac_sr == AC_SR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.powermode_ac_tx_datapath == AC_TX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.powermode_dc == POWERUP_DC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.powermode_freq_hz_aib_rx_sr_clk_in == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.powermode_freq_hz_aib_rx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.powermode_freq_hz_aib_tx_transfer_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.powermode_freq_hz_global_avmm_clk == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.sr_prot_mode == SR_PROT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.async_direct_sel0 == DIRECT_SEL0_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.async_direct_sel1 == DIRECT_SEL1_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.async_direct_sel2 == DIRECT_SEL2_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.async_direct_sel3 == DIRECT_SEL3_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.avmm1_free_run_div_clk == AVMM1_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.avmm1_write_resp_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.avmm2_free_run_div_clk == AVMM2_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.avmm2_global_usr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.dfd_cntr_inc_value == 9'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.dfd_cntr_rst_b == CNTR_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_ch_sel == GP0_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_cntr_data_sel == GP0_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_rsvd == GP0_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_testbus_sel == GP0_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_ch_sel == GP1_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_cntr_data_sel == GP1_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_rsvd == GP1_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_testbus_sel == GP1_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.dfd_mux_rst_b == MUX_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.hwcfg_adpt_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.hwcfg_aib_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.hwcfg_mode == BLOCK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.sr_prot_map_mode == MAP_SR_PROT_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.sr_test_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.sr_xcvr_map_mode == MAP_SR_XCVR_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.adapter_lpbk_mode == LOOPBACK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.aib_lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.async_direct_hip_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.datapath_mapping_mode == MAP_RX_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_sel == FIFO_RD_BTI_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_sel == FIFO_WR_PCIE_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.hrdrst_rst_sm_dis == DISABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel == FEEDTHRU_CLK1_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel0 == TXFIFOWR_FROM_AIB_MUX_CLK1_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel1 == FEEDTHRU_CLKS_OR_TXFIFORD_PRE_OR_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel2 == PMA_CLKS_OR_TXFIFORD_PRE_CT_MUX_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel3 == PMA_CLKS_CLK1_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel == FEEDTHRU_CLK0_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel0 == RXFIFORD_TO_AIB_MUX_CLK2_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_PRE_OR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel2 == PMA_CLKS_OR_RXFIFOWR_PRE_CT_MUX_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel3 == PMA_CLKS_CLK2_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.msb_pipeline_byp == MSB_PIPE_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.pld_pcs_rx_clk_out_sel == PLD_PCS_RX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.pma_aib_rx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.pma_coreclkin_sel == PMA_CORECLKIN_PLD_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.rx_10g_krfec_rx_diag_data_status_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.rx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.rx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.rx_parity_sel == FUNC_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.rx_pcs_testbus_sel == DIRECT_TR_TB_BIT0_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.rx_pcspma_testbus_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_a1a2_k1k2_flag_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_wa_boundary_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_pcie_sw_done_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_reser_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_testbus_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.rx_pld_test_data_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_num_stages == RMFFLAG_TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.rx_user_clk_rst_sel == RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.rx_user_clk_sel == RX_USER_CLK_E400G_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.rx_usertest_sel == DIRECT_TR_USERTEST3_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.rxfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.rxfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.rxfifo_mode == RXBYPASS_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.rxfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.rxfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.rxfiford_post_ct_sel == RXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.rxfiford_to_aib_sel == RXFIFORD_SCLK_TO_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.rxfifowr_post_ct_sel == RXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.rxfifowr_pre_ct_sel == RXFIFOWR_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.txfiford_post_ct_sel == TXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.txfiford_pre_ct_sel == TXFIFORD_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.txfifowr_from_aib_sel == TXFIFOWR_SCLK_FROM_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.txfifowr_post_ct_sel == TXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_rxchnl.word_mark == WM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_sr.sr_free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_sr.sr_osc_clk_div_sel == NON_DIV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.datapath_mapping_mode == MAP_TX_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.dv_gating == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.fifo_double_read == FIFO_DOUBLE_READ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_sel == FIFO_RD_PCIE_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.hrdrst_rst_sm_dis == ENABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.pld_pcs_tx_clk_out_sel == PLD_PCS_TX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.pma_aib_tx_clk_sel == PMA_AIB_TX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.tx_datapath_tb_sel == WA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.tx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.tx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.tx_latency_src_xcvrif == LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.tx_rev_lpbk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e200g_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e400g_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.tx_transfer_div2_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.tx_user_clk_rst_sel == TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.tx_user_clk_sel == TX_USER_CLK_E400G_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.tx_usertest_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.txfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.txfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.gdr_aibadapter.adapt_txchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_dc == AVMM1_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_dc == AVMM2_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr1 == AIB_DDR1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_clkdiv == AIB_RX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp == AIB_RX_DCC_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp_iocsr_unused == AIB_RX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal == AIB_RX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal_iocsr_unused == AIB_RX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft == AIB_RX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft_sel == AIB_RX_DCC_DFT_MODE1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dll_entest == AIB_RX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctl_static == AIB_RX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctlsel == AIB_RX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en == AIB_RX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en_iocsr_unused == AIB_RX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_dn == AIB_RX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_up == AIB_RX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_pi_slw == AIB_RX_DCC_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_rst_prgmnvrt == AIB_RX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_dn_prgmnvrt == AIB_RX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_up_prgmnvrt == AIB_RX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_updnen == AIB_RX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dftmuxsel == AIB_RX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dly_pst == AIB_RX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_en == AIB_RX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_lockreq_muxsel == AIB_RX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll == AIB_RX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll2 == AIB_RX_DCC_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_rst == AIB_RX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_test_clk_pll_en_n == AIB_RX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_halfcode == AIB_RX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_selflock == AIB_RX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.op_mode == RX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_dc == RXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dcc_dll_dft_sel == AIB_DLLSTR_ALIGN_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dft_ch_muxsel == AIB_DLLSTR_ALIGN_DFT_CH_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_pi_slw == AIB_DLLSTR_ALIGN_PI_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll == AIB_DLLSTR_ALIGN_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll2 == AIB_DLLSTR_ALIGN_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_pinp_shiften == AIB_RED_PINP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.op_mode == TX_DLL_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_HIGH_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_dc == TXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_13.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.aib_hssi_rx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.aib_hssi_rx_transfer_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.aib_hssi_tx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.aib_hssi_tx_sr_clk_out_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.aib_hssi_tx_transfer_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.aib_rx_user_clk_hz == 32'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.bti_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.direct_sel0 == DIRECT_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.e200g_aib1_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.e200g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.e200g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.e200g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.e200g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.e200g_rx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.e200g_tx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.e400g_aib1_tx_st_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.e400g_aib2_rx_st_clk_hz == 32'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.e400g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.e400g_aib3_rx_st_clk_hz == 32'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.e400g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.e400g_rx_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.e400g_tx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.global_avmm_clk_hz == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.internal_clk1_source == INTERNAL_CLK1_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.internal_clk2_source == INTERNAL_CLK2_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.pcie_pld_2x_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.pcie_pld_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.pcie_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.pcie_tx_transfer_div2_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.pld_pcs_rx_clk_out_hz == 32'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.pld_pcs_tx_clk_out_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.pma_aib_tx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.powermode_ac_avmm1 == AC_AVMM1_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.powermode_ac_avmm2 == AC_AVMM2_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.powermode_ac_global_avmm == GLOBAL_AVMM_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.powermode_ac_rx_datapath == AC_RX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.powermode_ac_sr == AC_SR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.powermode_ac_tx_datapath == AC_TX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.powermode_dc == POWERUP_DC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.powermode_freq_hz_aib_rx_sr_clk_in == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.powermode_freq_hz_aib_rx_transfer_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.powermode_freq_hz_aib_tx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.powermode_freq_hz_global_avmm_clk == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.sr_prot_mode == SR_PROT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.async_direct_sel0 == DIRECT_SEL0_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.async_direct_sel1 == DIRECT_SEL1_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.async_direct_sel2 == DIRECT_SEL2_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.async_direct_sel3 == DIRECT_SEL3_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.avmm1_free_run_div_clk == AVMM1_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.avmm1_write_resp_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.avmm2_free_run_div_clk == AVMM2_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.avmm2_global_usr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.dfd_cntr_inc_value == 9'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.dfd_cntr_rst_b == CNTR_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_ch_sel == GP0_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_cntr_data_sel == GP0_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_rsvd == GP0_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_testbus_sel == GP0_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_ch_sel == GP1_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_cntr_data_sel == GP1_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_rsvd == GP1_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_testbus_sel == GP1_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.dfd_mux_rst_b == MUX_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.hwcfg_adpt_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.hwcfg_aib_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.hwcfg_mode == BLOCK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.sr_prot_map_mode == MAP_SR_PROT_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.sr_test_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.sr_xcvr_map_mode == MAP_SR_XCVR_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.adapter_lpbk_mode == LOOPBACK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.aib_lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.async_direct_hip_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.datapath_mapping_mode == MAP_RX_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_sel == FIFO_RD_E400G_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_sel == FIFO_WR_PCIE_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.hrdrst_rst_sm_dis == ENABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel == FEEDTHRU_CLK1_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel0 == TXFIFOWR_FROM_AIB_MUX_CLK1_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel1 == FEEDTHRU_CLKS_OR_TXFIFORD_PRE_OR_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel2 == PMA_CLKS_OR_TXFIFORD_PRE_CT_MUX_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel3 == PMA_CLKS_CLK1_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel == FEEDTHRU_CLK0_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel0 == RXFIFORD_TO_AIB_MUX_CLK2_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_PRE_OR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel2 == PMA_CLKS_OR_RXFIFOWR_PRE_CT_MUX_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel3 == PMA_CLKS_CLK2_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.msb_pipeline_byp == MSB_PIPE_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.pld_pcs_rx_clk_out_sel == PLD_PCS_RX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.pma_aib_rx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.pma_coreclkin_sel == PMA_CORECLKIN_PLD_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.rx_10g_krfec_rx_diag_data_status_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.rx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.rx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.rx_parity_sel == FUNC_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.rx_pcs_testbus_sel == DIRECT_TR_TB_BIT0_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.rx_pcspma_testbus_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_a1a2_k1k2_flag_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_wa_boundary_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_pcie_sw_done_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_reser_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_testbus_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.rx_pld_test_data_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_num_stages == RMFFLAG_TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.rx_user_clk_rst_sel == RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.rx_user_clk_sel == RX_USER_CLK_E400G_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.rx_usertest_sel == DIRECT_TR_USERTEST3_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.rxfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.rxfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.rxfifo_mode == RXBYPASS_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.rxfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.rxfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.rxfiford_post_ct_sel == RXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.rxfiford_to_aib_sel == RXFIFORD_SCLK_TO_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.rxfifowr_post_ct_sel == RXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.rxfifowr_pre_ct_sel == RXFIFOWR_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.txfiford_post_ct_sel == TXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.txfiford_pre_ct_sel == TXFIFORD_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.txfifowr_from_aib_sel == TXFIFOWR_SCLK_FROM_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.txfifowr_post_ct_sel == TXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_rxchnl.word_mark == WM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_sr.sr_free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_sr.sr_osc_clk_div_sel == NON_DIV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.datapath_mapping_mode == MAP_TX_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.dv_gating == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.fifo_double_read == FIFO_DOUBLE_READ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_sel == FIFO_RD_PCIE_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.hrdrst_rst_sm_dis == DISABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.pld_pcs_tx_clk_out_sel == PLD_PCS_TX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.pma_aib_tx_clk_sel == PMA_AIB_TX_CLK_BTI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.tx_datapath_tb_sel == WA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.tx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.tx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.tx_latency_src_xcvrif == LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.tx_rev_lpbk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e200g_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e400g_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.tx_transfer_div2_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.tx_user_clk_rst_sel == TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.tx_user_clk_sel == TX_USER_CLK_E400G_DIV4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.tx_usertest_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.txfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.txfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.gdr_aibadapter.adapt_txchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_dc == AVMM1_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_dc == AVMM2_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr1 == AIB_DDR1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_clkdiv == AIB_RX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp == AIB_RX_DCC_BYP_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp_iocsr_unused == AIB_RX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal == AIB_RX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal_iocsr_unused == AIB_RX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft == AIB_RX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft_sel == AIB_RX_DCC_DFT_MODE1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dll_entest == AIB_RX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctl_static == AIB_RX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctlsel == AIB_RX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en == AIB_RX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en_iocsr_unused == AIB_RX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_dn == AIB_RX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_up == AIB_RX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_pi_slw == AIB_RX_DCC_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_rst_prgmnvrt == AIB_RX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_dn_prgmnvrt == AIB_RX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_up_prgmnvrt == AIB_RX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_updnen == AIB_RX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dftmuxsel == AIB_RX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dly_pst == AIB_RX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_en == AIB_RX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_lockreq_muxsel == AIB_RX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll == AIB_RX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll2 == AIB_RX_DCC_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_rst == AIB_RX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_test_clk_pll_en_n == AIB_RX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_halfcode == AIB_RX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_selflock == AIB_RX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.op_mode == RX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_HIGH_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_dc == RXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dcc_dll_dft_sel == AIB_DLLSTR_ALIGN_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dft_ch_muxsel == AIB_DLLSTR_ALIGN_DFT_CH_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_pi_slw == AIB_DLLSTR_ALIGN_PI_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll == AIB_DLLSTR_ALIGN_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll2 == AIB_DLLSTR_ALIGN_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_pinp_shiften == AIB_RED_PINP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.op_mode == TX_DLL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_dc == TXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_14.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.aib_hssi_rx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.aib_hssi_rx_transfer_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.aib_hssi_tx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.aib_hssi_tx_sr_clk_out_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.aib_hssi_tx_transfer_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.bti_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.direct_sel0 == DIRECT_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.e200g_aib1_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.e200g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.e200g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.e200g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.e200g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.e200g_rx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.e200g_tx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.e400g_aib1_tx_st_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.e400g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.e400g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.e400g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.e400g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.e400g_rx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.e400g_tx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.global_avmm_clk_hz == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.internal_clk1_source == INTERNAL_CLK1_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.internal_clk2_source == INTERNAL_CLK2_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.pcie_pld_2x_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.pcie_pld_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.pcie_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.pcie_tx_transfer_div2_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.pld_pcs_rx_clk_out_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.pld_pcs_tx_clk_out_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.pma_aib_tx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.powermode_ac_avmm1 == AC_AVMM1_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.powermode_ac_avmm2 == AC_AVMM2_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.powermode_ac_global_avmm == GLOBAL_AVMM_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.powermode_ac_rx_datapath == AC_RX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.powermode_ac_sr == AC_SR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.powermode_ac_tx_datapath == AC_TX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.powermode_dc == POWERUP_DC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.powermode_freq_hz_aib_rx_sr_clk_in == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.powermode_freq_hz_aib_rx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.powermode_freq_hz_aib_tx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.powermode_freq_hz_global_avmm_clk == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.sr_prot_mode == SR_PROT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.async_direct_sel0 == DIRECT_SEL0_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.async_direct_sel1 == DIRECT_SEL1_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.async_direct_sel2 == DIRECT_SEL2_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.async_direct_sel3 == DIRECT_SEL3_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.avmm1_free_run_div_clk == AVMM1_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.avmm1_write_resp_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.avmm2_free_run_div_clk == AVMM2_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.avmm2_global_usr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.dfd_cntr_inc_value == 9'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.dfd_cntr_rst_b == CNTR_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_ch_sel == GP0_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_cntr_data_sel == GP0_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_rsvd == GP0_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_testbus_sel == GP0_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_ch_sel == GP1_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_cntr_data_sel == GP1_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_rsvd == GP1_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_testbus_sel == GP1_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.dfd_mux_rst_b == MUX_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.hwcfg_adpt_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.hwcfg_aib_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.hwcfg_mode == BLOCK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.sr_prot_map_mode == MAP_SR_PROT_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.sr_test_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.sr_xcvr_map_mode == MAP_SR_XCVR_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.adapter_lpbk_mode == LOOPBACK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.aib_lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.async_direct_hip_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.datapath_mapping_mode == MAP_RX_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_sel == FIFO_RD_BTI_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_sel == FIFO_WR_PCIE_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.hrdrst_rst_sm_dis == DISABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel == FEEDTHRU_CLK1_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel0 == TXFIFOWR_FROM_AIB_MUX_CLK1_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel1 == FEEDTHRU_CLKS_OR_TXFIFORD_PRE_OR_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel2 == PMA_CLKS_OR_TXFIFORD_PRE_CT_MUX_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel3 == PMA_CLKS_CLK1_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel == FEEDTHRU_CLK0_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel0 == RXFIFORD_TO_AIB_MUX_CLK2_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_PRE_OR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel2 == PMA_CLKS_OR_RXFIFOWR_PRE_CT_MUX_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel3 == PMA_CLKS_CLK2_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.msb_pipeline_byp == MSB_PIPE_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.pld_pcs_rx_clk_out_sel == PLD_PCS_RX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.pma_aib_rx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.pma_coreclkin_sel == PMA_CORECLKIN_PLD_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.rx_10g_krfec_rx_diag_data_status_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.rx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.rx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.rx_parity_sel == FUNC_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.rx_pcs_testbus_sel == DIRECT_TR_TB_BIT0_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.rx_pcspma_testbus_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_a1a2_k1k2_flag_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_wa_boundary_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_pcie_sw_done_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_reser_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_testbus_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.rx_pld_test_data_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_num_stages == RMFFLAG_TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.rx_user_clk_rst_sel == RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.rx_user_clk_sel == RX_USER_CLK_E400G_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.rx_usertest_sel == DIRECT_TR_USERTEST3_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.rxfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.rxfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.rxfifo_mode == RXBYPASS_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.rxfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.rxfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.rxfiford_post_ct_sel == RXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.rxfiford_to_aib_sel == RXFIFORD_SCLK_TO_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.rxfifowr_post_ct_sel == RXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.rxfifowr_pre_ct_sel == RXFIFOWR_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.txfiford_post_ct_sel == TXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.txfiford_pre_ct_sel == TXFIFORD_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.txfifowr_from_aib_sel == TXFIFOWR_SCLK_FROM_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.txfifowr_post_ct_sel == TXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_rxchnl.word_mark == WM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_sr.sr_free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_sr.sr_osc_clk_div_sel == NON_DIV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.datapath_mapping_mode == MAP_TX_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.dv_gating == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.fifo_double_read == FIFO_DOUBLE_READ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_sel == FIFO_RD_PCIE_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.hrdrst_rst_sm_dis == DISABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.pld_pcs_tx_clk_out_sel == PLD_PCS_TX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.pma_aib_tx_clk_sel == PMA_AIB_TX_CLK_BTI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.tx_datapath_tb_sel == WA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.tx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.tx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.tx_latency_src_xcvrif == LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.tx_rev_lpbk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e200g_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e400g_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.tx_transfer_div2_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.tx_user_clk_rst_sel == TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.tx_user_clk_sel == TX_USER_CLK_E400G_DIV4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.tx_usertest_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.txfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.txfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.gdr_aibadapter.adapt_txchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_dc == AVMM1_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_dc == AVMM2_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr1 == AIB_DDR1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_clkdiv == AIB_RX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp == AIB_RX_DCC_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp_iocsr_unused == AIB_RX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal == AIB_RX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal_iocsr_unused == AIB_RX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft == AIB_RX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft_sel == AIB_RX_DCC_DFT_MODE1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dll_entest == AIB_RX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctl_static == AIB_RX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctlsel == AIB_RX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en == AIB_RX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en_iocsr_unused == AIB_RX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_dn == AIB_RX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_up == AIB_RX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_pi_slw == AIB_RX_DCC_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_rst_prgmnvrt == AIB_RX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_dn_prgmnvrt == AIB_RX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_up_prgmnvrt == AIB_RX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_updnen == AIB_RX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dftmuxsel == AIB_RX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dly_pst == AIB_RX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_en == AIB_RX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_lockreq_muxsel == AIB_RX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll == AIB_RX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll2 == AIB_RX_DCC_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_rst == AIB_RX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_test_clk_pll_en_n == AIB_RX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_halfcode == AIB_RX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_selflock == AIB_RX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.op_mode == RX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_dc == RXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dcc_dll_dft_sel == AIB_DLLSTR_ALIGN_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dft_ch_muxsel == AIB_DLLSTR_ALIGN_DFT_CH_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_pi_slw == AIB_DLLSTR_ALIGN_PI_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll == AIB_DLLSTR_ALIGN_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll2 == AIB_DLLSTR_ALIGN_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_pinp_shiften == AIB_RED_PINP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.op_mode == TX_DLL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_dc == TXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_15.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.aib_hssi_rx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.aib_hssi_rx_transfer_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.aib_hssi_tx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.aib_hssi_tx_sr_clk_out_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.aib_hssi_tx_transfer_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.aib_rx_user_clk_hz == 32'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.bti_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.direct_sel0 == DIRECT_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.e200g_aib1_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.e200g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.e200g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.e200g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.e200g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.e200g_rx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.e200g_tx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.e400g_aib1_tx_st_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.e400g_aib2_rx_st_clk_hz == 32'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.e400g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.e400g_aib3_rx_st_clk_hz == 32'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.e400g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.e400g_rx_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.e400g_tx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.global_avmm_clk_hz == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.internal_clk1_source == INTERNAL_CLK1_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.internal_clk2_source == INTERNAL_CLK2_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.pcie_pld_2x_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.pcie_pld_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.pcie_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.pcie_tx_transfer_div2_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.pld_pcs_rx_clk_out_hz == 32'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.pld_pcs_tx_clk_out_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.pma_aib_tx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.powermode_ac_avmm1 == AC_AVMM1_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.powermode_ac_avmm2 == AC_AVMM2_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.powermode_ac_global_avmm == GLOBAL_AVMM_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.powermode_ac_rx_datapath == AC_RX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.powermode_ac_sr == AC_SR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.powermode_ac_tx_datapath == AC_TX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.powermode_dc == POWERUP_DC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.powermode_freq_hz_aib_rx_sr_clk_in == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.powermode_freq_hz_aib_rx_transfer_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.powermode_freq_hz_aib_tx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.powermode_freq_hz_global_avmm_clk == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.sr_prot_mode == SR_PROT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.async_direct_sel0 == DIRECT_SEL0_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.async_direct_sel1 == DIRECT_SEL1_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.async_direct_sel2 == DIRECT_SEL2_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.async_direct_sel3 == DIRECT_SEL3_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.avmm1_free_run_div_clk == AVMM1_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.avmm1_write_resp_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.avmm2_free_run_div_clk == AVMM2_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.avmm2_global_usr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.dfd_cntr_inc_value == 9'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.dfd_cntr_rst_b == CNTR_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_ch_sel == GP0_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_cntr_data_sel == GP0_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_rsvd == GP0_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_testbus_sel == GP0_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_ch_sel == GP1_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_cntr_data_sel == GP1_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_rsvd == GP1_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_testbus_sel == GP1_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.dfd_mux_rst_b == MUX_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.hwcfg_adpt_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.hwcfg_aib_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.hwcfg_mode == BLOCK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.sr_prot_map_mode == MAP_SR_PROT_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.sr_test_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.sr_xcvr_map_mode == MAP_SR_XCVR_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.adapter_lpbk_mode == LOOPBACK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.aib_lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.async_direct_hip_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.datapath_mapping_mode == MAP_RX_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_sel == FIFO_RD_E400G_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_sel == FIFO_WR_PCIE_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.hrdrst_rst_sm_dis == ENABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel == FEEDTHRU_CLK1_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel0 == TXFIFOWR_FROM_AIB_MUX_CLK1_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel1 == FEEDTHRU_CLKS_OR_TXFIFORD_PRE_OR_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel2 == PMA_CLKS_OR_TXFIFORD_PRE_CT_MUX_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel3 == PMA_CLKS_CLK1_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel == FEEDTHRU_CLK0_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel0 == RXFIFORD_TO_AIB_MUX_CLK2_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_PRE_OR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel2 == PMA_CLKS_OR_RXFIFOWR_PRE_CT_MUX_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel3 == PMA_CLKS_CLK2_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.msb_pipeline_byp == MSB_PIPE_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.pld_pcs_rx_clk_out_sel == PLD_PCS_RX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.pma_aib_rx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.pma_coreclkin_sel == PMA_CORECLKIN_PLD_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.rx_10g_krfec_rx_diag_data_status_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.rx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.rx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.rx_parity_sel == FUNC_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.rx_pcs_testbus_sel == DIRECT_TR_TB_BIT0_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.rx_pcspma_testbus_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_a1a2_k1k2_flag_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_wa_boundary_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_pcie_sw_done_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_reser_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_testbus_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.rx_pld_test_data_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_num_stages == RMFFLAG_TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.rx_user_clk_rst_sel == RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.rx_user_clk_sel == RX_USER_CLK_E400G_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.rx_usertest_sel == DIRECT_TR_USERTEST3_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.rxfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.rxfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.rxfifo_mode == RXBYPASS_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.rxfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.rxfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.rxfiford_post_ct_sel == RXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.rxfiford_to_aib_sel == RXFIFORD_SCLK_TO_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.rxfifowr_post_ct_sel == RXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.rxfifowr_pre_ct_sel == RXFIFOWR_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.txfiford_post_ct_sel == TXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.txfiford_pre_ct_sel == TXFIFORD_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.txfifowr_from_aib_sel == TXFIFOWR_SCLK_FROM_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.txfifowr_post_ct_sel == TXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_rxchnl.word_mark == WM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_sr.sr_free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_sr.sr_osc_clk_div_sel == NON_DIV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.datapath_mapping_mode == MAP_TX_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.dv_gating == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.fifo_double_read == FIFO_DOUBLE_READ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_sel == FIFO_RD_PCIE_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.hrdrst_rst_sm_dis == DISABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.pld_pcs_tx_clk_out_sel == PLD_PCS_TX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.pma_aib_tx_clk_sel == PMA_AIB_TX_CLK_BTI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.tx_datapath_tb_sel == WA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.tx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.tx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.tx_latency_src_xcvrif == LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.tx_rev_lpbk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e200g_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e400g_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.tx_transfer_div2_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.tx_user_clk_rst_sel == TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.tx_user_clk_sel == TX_USER_CLK_E400G_DIV4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.tx_usertest_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.txfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.txfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.gdr_aibadapter.adapt_txchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_dc == AVMM1_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_dc == AVMM2_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr1 == AIB_DDR1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_clkdiv == AIB_RX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp == AIB_RX_DCC_BYP_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp_iocsr_unused == AIB_RX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal == AIB_RX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal_iocsr_unused == AIB_RX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft == AIB_RX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft_sel == AIB_RX_DCC_DFT_MODE1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dll_entest == AIB_RX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctl_static == AIB_RX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctlsel == AIB_RX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en == AIB_RX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en_iocsr_unused == AIB_RX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_dn == AIB_RX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_up == AIB_RX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_pi_slw == AIB_RX_DCC_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_rst_prgmnvrt == AIB_RX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_dn_prgmnvrt == AIB_RX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_up_prgmnvrt == AIB_RX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_updnen == AIB_RX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dftmuxsel == AIB_RX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dly_pst == AIB_RX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_en == AIB_RX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_lockreq_muxsel == AIB_RX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll == AIB_RX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll2 == AIB_RX_DCC_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_rst == AIB_RX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_test_clk_pll_en_n == AIB_RX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_halfcode == AIB_RX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_selflock == AIB_RX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.op_mode == RX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_HIGH_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_dc == RXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dcc_dll_dft_sel == AIB_DLLSTR_ALIGN_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dft_ch_muxsel == AIB_DLLSTR_ALIGN_DFT_CH_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_pi_slw == AIB_DLLSTR_ALIGN_PI_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll == AIB_DLLSTR_ALIGN_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll2 == AIB_DLLSTR_ALIGN_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_pinp_shiften == AIB_RED_PINP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.op_mode == TX_DLL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_dc == TXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_16.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.aib_hssi_rx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.aib_hssi_rx_transfer_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.aib_hssi_tx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.aib_hssi_tx_sr_clk_out_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.aib_hssi_tx_transfer_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.bti_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.direct_sel0 == DIRECT_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.e200g_aib1_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.e200g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.e200g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.e200g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.e200g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.e200g_rx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.e200g_tx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.e400g_aib1_tx_st_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.e400g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.e400g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.e400g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.e400g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.e400g_rx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.e400g_tx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.global_avmm_clk_hz == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.internal_clk1_source == INTERNAL_CLK1_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.internal_clk2_source == INTERNAL_CLK2_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.pcie_pld_2x_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.pcie_pld_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.pcie_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.pcie_tx_transfer_div2_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.pld_pcs_rx_clk_out_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.pld_pcs_tx_clk_out_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.pma_aib_tx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.powermode_ac_avmm1 == AC_AVMM1_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.powermode_ac_avmm2 == AC_AVMM2_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.powermode_ac_global_avmm == GLOBAL_AVMM_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.powermode_ac_rx_datapath == AC_RX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.powermode_ac_sr == AC_SR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.powermode_ac_tx_datapath == AC_TX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.powermode_dc == POWERUP_DC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.powermode_freq_hz_aib_rx_sr_clk_in == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.powermode_freq_hz_aib_rx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.powermode_freq_hz_aib_tx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.powermode_freq_hz_global_avmm_clk == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.sr_prot_mode == SR_PROT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.async_direct_sel0 == DIRECT_SEL0_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.async_direct_sel1 == DIRECT_SEL1_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.async_direct_sel2 == DIRECT_SEL2_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.async_direct_sel3 == DIRECT_SEL3_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.avmm1_free_run_div_clk == AVMM1_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.avmm1_write_resp_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.avmm2_free_run_div_clk == AVMM2_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.avmm2_global_usr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.dfd_cntr_inc_value == 9'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.dfd_cntr_rst_b == CNTR_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_ch_sel == GP0_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_cntr_data_sel == GP0_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_rsvd == GP0_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_testbus_sel == GP0_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_ch_sel == GP1_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_cntr_data_sel == GP1_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_rsvd == GP1_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_testbus_sel == GP1_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.dfd_mux_rst_b == MUX_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.hwcfg_adpt_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.hwcfg_aib_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.hwcfg_mode == BLOCK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.sr_prot_map_mode == MAP_SR_PROT_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.sr_test_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.sr_xcvr_map_mode == MAP_SR_XCVR_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.adapter_lpbk_mode == LOOPBACK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.aib_lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.async_direct_hip_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.datapath_mapping_mode == MAP_RX_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_sel == FIFO_RD_BTI_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_sel == FIFO_WR_PCIE_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.hrdrst_rst_sm_dis == DISABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel == FEEDTHRU_CLK1_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel0 == TXFIFOWR_FROM_AIB_MUX_CLK1_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel1 == FEEDTHRU_CLKS_OR_TXFIFORD_PRE_OR_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel2 == PMA_CLKS_OR_TXFIFORD_PRE_CT_MUX_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel3 == PMA_CLKS_CLK1_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel == FEEDTHRU_CLK0_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel0 == RXFIFORD_TO_AIB_MUX_CLK2_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_PRE_OR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel2 == PMA_CLKS_OR_RXFIFOWR_PRE_CT_MUX_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel3 == PMA_CLKS_CLK2_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.msb_pipeline_byp == MSB_PIPE_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.pld_pcs_rx_clk_out_sel == PLD_PCS_RX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.pma_aib_rx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.pma_coreclkin_sel == PMA_CORECLKIN_PLD_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.rx_10g_krfec_rx_diag_data_status_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.rx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.rx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.rx_parity_sel == FUNC_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.rx_pcs_testbus_sel == DIRECT_TR_TB_BIT0_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.rx_pcspma_testbus_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_a1a2_k1k2_flag_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_wa_boundary_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_pcie_sw_done_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_reser_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_testbus_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.rx_pld_test_data_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_num_stages == RMFFLAG_TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.rx_user_clk_rst_sel == RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.rx_user_clk_sel == RX_USER_CLK_E400G_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.rx_usertest_sel == DIRECT_TR_USERTEST3_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.rxfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.rxfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.rxfifo_mode == RXBYPASS_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.rxfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.rxfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.rxfiford_post_ct_sel == RXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.rxfiford_to_aib_sel == RXFIFORD_SCLK_TO_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.rxfifowr_post_ct_sel == RXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.rxfifowr_pre_ct_sel == RXFIFOWR_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.txfiford_post_ct_sel == TXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.txfiford_pre_ct_sel == TXFIFORD_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.txfifowr_from_aib_sel == TXFIFOWR_SCLK_FROM_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.txfifowr_post_ct_sel == TXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_rxchnl.word_mark == WM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_sr.sr_free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_sr.sr_osc_clk_div_sel == NON_DIV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.datapath_mapping_mode == MAP_TX_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.dv_gating == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.fifo_double_read == FIFO_DOUBLE_READ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_sel == FIFO_RD_PCIE_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.hrdrst_rst_sm_dis == DISABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.pld_pcs_tx_clk_out_sel == PLD_PCS_TX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.pma_aib_tx_clk_sel == PMA_AIB_TX_CLK_BTI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.tx_datapath_tb_sel == WA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.tx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.tx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.tx_latency_src_xcvrif == LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.tx_rev_lpbk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e200g_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e400g_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.tx_transfer_div2_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.tx_user_clk_rst_sel == TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.tx_user_clk_sel == TX_USER_CLK_E400G_DIV4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.tx_usertest_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.txfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.txfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.gdr_aibadapter.adapt_txchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_dc == AVMM1_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_dc == AVMM2_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr1 == AIB_DDR1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_clkdiv == AIB_RX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp == AIB_RX_DCC_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp_iocsr_unused == AIB_RX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal == AIB_RX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal_iocsr_unused == AIB_RX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft == AIB_RX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft_sel == AIB_RX_DCC_DFT_MODE1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dll_entest == AIB_RX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctl_static == AIB_RX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctlsel == AIB_RX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en == AIB_RX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en_iocsr_unused == AIB_RX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_dn == AIB_RX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_up == AIB_RX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_pi_slw == AIB_RX_DCC_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_rst_prgmnvrt == AIB_RX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_dn_prgmnvrt == AIB_RX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_up_prgmnvrt == AIB_RX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_updnen == AIB_RX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dftmuxsel == AIB_RX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dly_pst == AIB_RX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_en == AIB_RX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_lockreq_muxsel == AIB_RX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll == AIB_RX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll2 == AIB_RX_DCC_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_rst == AIB_RX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_test_clk_pll_en_n == AIB_RX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_halfcode == AIB_RX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_selflock == AIB_RX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.op_mode == RX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_dc == RXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dcc_dll_dft_sel == AIB_DLLSTR_ALIGN_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dft_ch_muxsel == AIB_DLLSTR_ALIGN_DFT_CH_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_pi_slw == AIB_DLLSTR_ALIGN_PI_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll == AIB_DLLSTR_ALIGN_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll2 == AIB_DLLSTR_ALIGN_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_pinp_shiften == AIB_RED_PINP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.op_mode == TX_DLL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_dc == TXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_17.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.aib_hssi_rx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.aib_hssi_rx_transfer_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.aib_hssi_tx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.aib_hssi_tx_sr_clk_out_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.aib_hssi_tx_transfer_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.bti_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.direct_sel0 == DIRECT_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.e200g_aib1_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.e200g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.e200g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.e200g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.e200g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.e200g_rx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.e200g_tx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.e400g_aib1_tx_st_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.e400g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.e400g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.e400g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.e400g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.e400g_rx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.e400g_tx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.global_avmm_clk_hz == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.internal_clk1_source == INTERNAL_CLK1_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.internal_clk2_source == INTERNAL_CLK2_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.pcie_pld_2x_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.pcie_pld_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.pcie_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.pcie_tx_transfer_div2_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.pld_pcs_rx_clk_out_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.pld_pcs_tx_clk_out_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.pma_aib_tx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.powermode_ac_avmm1 == AC_AVMM1_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.powermode_ac_avmm2 == AC_AVMM2_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.powermode_ac_global_avmm == GLOBAL_AVMM_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.powermode_ac_rx_datapath == AC_RX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.powermode_ac_sr == AC_SR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.powermode_ac_tx_datapath == AC_TX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.powermode_dc == POWERUP_DC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.powermode_freq_hz_aib_rx_sr_clk_in == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.powermode_freq_hz_aib_rx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.powermode_freq_hz_aib_tx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.powermode_freq_hz_global_avmm_clk == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.sr_prot_mode == SR_PROT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.async_direct_sel0 == DIRECT_SEL0_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.async_direct_sel1 == DIRECT_SEL1_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.async_direct_sel2 == DIRECT_SEL2_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.async_direct_sel3 == DIRECT_SEL3_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.avmm1_free_run_div_clk == AVMM1_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.avmm1_write_resp_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.avmm2_free_run_div_clk == AVMM2_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.avmm2_global_usr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.dfd_cntr_inc_value == 9'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.dfd_cntr_rst_b == CNTR_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_ch_sel == GP0_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_cntr_data_sel == GP0_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_rsvd == GP0_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_testbus_sel == GP0_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_ch_sel == GP1_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_cntr_data_sel == GP1_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_rsvd == GP1_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_testbus_sel == GP1_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.dfd_mux_rst_b == MUX_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.hwcfg_adpt_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.hwcfg_aib_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.hwcfg_mode == BLOCK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.sr_prot_map_mode == MAP_SR_PROT_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.sr_test_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.sr_xcvr_map_mode == MAP_SR_XCVR_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.adapter_lpbk_mode == LOOPBACK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.aib_lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.async_direct_hip_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.datapath_mapping_mode == MAP_RX_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_sel == FIFO_RD_BTI_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_sel == FIFO_WR_PCIE_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.hrdrst_rst_sm_dis == DISABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel == FEEDTHRU_CLK1_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel0 == TXFIFOWR_FROM_AIB_MUX_CLK1_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel1 == FEEDTHRU_CLKS_OR_TXFIFORD_PRE_OR_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel2 == PMA_CLKS_OR_TXFIFORD_PRE_CT_MUX_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel3 == PMA_CLKS_CLK1_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel == FEEDTHRU_CLK0_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel0 == RXFIFORD_TO_AIB_MUX_CLK2_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_PRE_OR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel2 == PMA_CLKS_OR_RXFIFOWR_PRE_CT_MUX_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel3 == PMA_CLKS_CLK2_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.msb_pipeline_byp == MSB_PIPE_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.pld_pcs_rx_clk_out_sel == PLD_PCS_RX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.pma_aib_rx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.pma_coreclkin_sel == PMA_CORECLKIN_PLD_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.rx_10g_krfec_rx_diag_data_status_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.rx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.rx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.rx_parity_sel == FUNC_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.rx_pcs_testbus_sel == DIRECT_TR_TB_BIT0_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.rx_pcspma_testbus_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_a1a2_k1k2_flag_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_wa_boundary_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_pcie_sw_done_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_reser_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_testbus_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.rx_pld_test_data_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_num_stages == RMFFLAG_TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.rx_user_clk_rst_sel == RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.rx_user_clk_sel == RX_USER_CLK_E400G_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.rx_usertest_sel == DIRECT_TR_USERTEST3_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.rxfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.rxfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.rxfifo_mode == RXBYPASS_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.rxfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.rxfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.rxfiford_post_ct_sel == RXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.rxfiford_to_aib_sel == RXFIFORD_SCLK_TO_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.rxfifowr_post_ct_sel == RXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.rxfifowr_pre_ct_sel == RXFIFOWR_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.txfiford_post_ct_sel == TXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.txfiford_pre_ct_sel == TXFIFORD_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.txfifowr_from_aib_sel == TXFIFOWR_SCLK_FROM_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.txfifowr_post_ct_sel == TXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_rxchnl.word_mark == WM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_sr.sr_free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_sr.sr_osc_clk_div_sel == NON_DIV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.datapath_mapping_mode == MAP_TX_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.dv_gating == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.fifo_double_read == FIFO_DOUBLE_READ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_sel == FIFO_RD_PCIE_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.hrdrst_rst_sm_dis == DISABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.pld_pcs_tx_clk_out_sel == PLD_PCS_TX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.pma_aib_tx_clk_sel == PMA_AIB_TX_CLK_BTI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.tx_datapath_tb_sel == WA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.tx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.tx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.tx_latency_src_xcvrif == LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.tx_rev_lpbk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e200g_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e400g_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.tx_transfer_div2_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.tx_user_clk_rst_sel == TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.tx_user_clk_sel == TX_USER_CLK_E400G_DIV4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.tx_usertest_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.txfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.txfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.gdr_aibadapter.adapt_txchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_dc == AVMM1_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_dc == AVMM2_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr1 == AIB_DDR1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_clkdiv == AIB_RX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp == AIB_RX_DCC_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp_iocsr_unused == AIB_RX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal == AIB_RX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal_iocsr_unused == AIB_RX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft == AIB_RX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft_sel == AIB_RX_DCC_DFT_MODE1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dll_entest == AIB_RX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctl_static == AIB_RX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctlsel == AIB_RX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en == AIB_RX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en_iocsr_unused == AIB_RX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_dn == AIB_RX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_up == AIB_RX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_pi_slw == AIB_RX_DCC_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_rst_prgmnvrt == AIB_RX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_dn_prgmnvrt == AIB_RX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_up_prgmnvrt == AIB_RX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_updnen == AIB_RX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dftmuxsel == AIB_RX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dly_pst == AIB_RX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_en == AIB_RX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_lockreq_muxsel == AIB_RX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll == AIB_RX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll2 == AIB_RX_DCC_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_rst == AIB_RX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_test_clk_pll_en_n == AIB_RX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_halfcode == AIB_RX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_selflock == AIB_RX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.op_mode == RX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_dc == RXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dcc_dll_dft_sel == AIB_DLLSTR_ALIGN_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dft_ch_muxsel == AIB_DLLSTR_ALIGN_DFT_CH_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_pi_slw == AIB_DLLSTR_ALIGN_PI_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll == AIB_DLLSTR_ALIGN_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll2 == AIB_DLLSTR_ALIGN_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_pinp_shiften == AIB_RED_PINP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.op_mode == TX_DLL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_dc == TXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_18.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.aib_hssi_rx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.aib_hssi_rx_transfer_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.aib_hssi_tx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.aib_hssi_tx_sr_clk_out_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.aib_hssi_tx_transfer_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.bti_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.direct_sel0 == DIRECT_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.e200g_aib1_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.e200g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.e200g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.e200g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.e200g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.e200g_rx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.e200g_tx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.e400g_aib1_tx_st_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.e400g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.e400g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.e400g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.e400g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.e400g_rx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.e400g_tx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.global_avmm_clk_hz == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.internal_clk1_source == INTERNAL_CLK1_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.internal_clk2_source == INTERNAL_CLK2_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.pcie_pld_2x_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.pcie_pld_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.pcie_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.pcie_tx_transfer_div2_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.pld_pcs_rx_clk_out_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.pld_pcs_tx_clk_out_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.pma_aib_tx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.powermode_ac_avmm1 == AC_AVMM1_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.powermode_ac_avmm2 == AC_AVMM2_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.powermode_ac_global_avmm == GLOBAL_AVMM_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.powermode_ac_rx_datapath == AC_RX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.powermode_ac_sr == AC_SR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.powermode_ac_tx_datapath == AC_TX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.powermode_dc == POWERUP_DC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.powermode_freq_hz_aib_rx_sr_clk_in == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.powermode_freq_hz_aib_rx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.powermode_freq_hz_aib_tx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.powermode_freq_hz_global_avmm_clk == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.sr_prot_mode == SR_PROT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.async_direct_sel0 == DIRECT_SEL0_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.async_direct_sel1 == DIRECT_SEL1_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.async_direct_sel2 == DIRECT_SEL2_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.async_direct_sel3 == DIRECT_SEL3_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.avmm1_free_run_div_clk == AVMM1_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.avmm1_write_resp_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.avmm2_free_run_div_clk == AVMM2_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.avmm2_global_usr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.dfd_cntr_inc_value == 9'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.dfd_cntr_rst_b == CNTR_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_ch_sel == GP0_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_cntr_data_sel == GP0_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_rsvd == GP0_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_testbus_sel == GP0_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_ch_sel == GP1_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_cntr_data_sel == GP1_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_rsvd == GP1_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_testbus_sel == GP1_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.dfd_mux_rst_b == MUX_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.hwcfg_adpt_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.hwcfg_aib_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.hwcfg_mode == BLOCK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.sr_prot_map_mode == MAP_SR_PROT_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.sr_test_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.sr_xcvr_map_mode == MAP_SR_XCVR_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.adapter_lpbk_mode == LOOPBACK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.aib_lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.async_direct_hip_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.datapath_mapping_mode == MAP_RX_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_sel == FIFO_RD_BTI_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_sel == FIFO_WR_PCIE_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.hrdrst_rst_sm_dis == DISABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel == FEEDTHRU_CLK1_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel0 == TXFIFOWR_FROM_AIB_MUX_CLK1_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel1 == FEEDTHRU_CLKS_OR_TXFIFORD_PRE_OR_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel2 == PMA_CLKS_OR_TXFIFORD_PRE_CT_MUX_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel3 == PMA_CLKS_CLK1_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel == FEEDTHRU_CLK0_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel0 == RXFIFORD_TO_AIB_MUX_CLK2_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_PRE_OR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel2 == PMA_CLKS_OR_RXFIFOWR_PRE_CT_MUX_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel3 == PMA_CLKS_CLK2_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.msb_pipeline_byp == MSB_PIPE_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.pld_pcs_rx_clk_out_sel == PLD_PCS_RX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.pma_aib_rx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.pma_coreclkin_sel == PMA_CORECLKIN_PLD_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.rx_10g_krfec_rx_diag_data_status_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.rx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.rx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.rx_parity_sel == FUNC_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.rx_pcs_testbus_sel == DIRECT_TR_TB_BIT0_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.rx_pcspma_testbus_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_a1a2_k1k2_flag_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_wa_boundary_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_pcie_sw_done_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_reser_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_testbus_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.rx_pld_test_data_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_num_stages == RMFFLAG_TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.rx_user_clk_rst_sel == RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.rx_user_clk_sel == RX_USER_CLK_E400G_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.rx_usertest_sel == DIRECT_TR_USERTEST3_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.rxfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.rxfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.rxfifo_mode == RXBYPASS_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.rxfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.rxfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.rxfiford_post_ct_sel == RXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.rxfiford_to_aib_sel == RXFIFORD_SCLK_TO_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.rxfifowr_post_ct_sel == RXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.rxfifowr_pre_ct_sel == RXFIFOWR_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.txfiford_post_ct_sel == TXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.txfiford_pre_ct_sel == TXFIFORD_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.txfifowr_from_aib_sel == TXFIFOWR_SCLK_FROM_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.txfifowr_post_ct_sel == TXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_rxchnl.word_mark == WM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_sr.sr_free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_sr.sr_osc_clk_div_sel == NON_DIV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.datapath_mapping_mode == MAP_TX_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.dv_gating == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.fifo_double_read == FIFO_DOUBLE_READ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_sel == FIFO_RD_PCIE_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.hrdrst_rst_sm_dis == DISABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.pld_pcs_tx_clk_out_sel == PLD_PCS_TX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.pma_aib_tx_clk_sel == PMA_AIB_TX_CLK_BTI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.tx_datapath_tb_sel == WA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.tx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.tx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.tx_latency_src_xcvrif == LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.tx_rev_lpbk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e200g_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e400g_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.tx_transfer_div2_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.tx_user_clk_rst_sel == TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.tx_user_clk_sel == TX_USER_CLK_E400G_DIV4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.tx_usertest_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.txfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.txfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.gdr_aibadapter.adapt_txchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_dc == AVMM1_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_dc == AVMM2_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr1 == AIB_DDR1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_clkdiv == AIB_RX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp == AIB_RX_DCC_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp_iocsr_unused == AIB_RX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal == AIB_RX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal_iocsr_unused == AIB_RX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft == AIB_RX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft_sel == AIB_RX_DCC_DFT_MODE1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dll_entest == AIB_RX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctl_static == AIB_RX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctlsel == AIB_RX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en == AIB_RX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en_iocsr_unused == AIB_RX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_dn == AIB_RX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_up == AIB_RX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_pi_slw == AIB_RX_DCC_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_rst_prgmnvrt == AIB_RX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_dn_prgmnvrt == AIB_RX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_up_prgmnvrt == AIB_RX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_updnen == AIB_RX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dftmuxsel == AIB_RX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dly_pst == AIB_RX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_en == AIB_RX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_lockreq_muxsel == AIB_RX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll == AIB_RX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll2 == AIB_RX_DCC_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_rst == AIB_RX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_test_clk_pll_en_n == AIB_RX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_halfcode == AIB_RX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_selflock == AIB_RX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.op_mode == RX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_dc == RXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dcc_dll_dft_sel == AIB_DLLSTR_ALIGN_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dft_ch_muxsel == AIB_DLLSTR_ALIGN_DFT_CH_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_pi_slw == AIB_DLLSTR_ALIGN_PI_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll == AIB_DLLSTR_ALIGN_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll2 == AIB_DLLSTR_ALIGN_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_pinp_shiften == AIB_RED_PINP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.op_mode == TX_DLL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_dc == TXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_19.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.aib_hssi_rx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.aib_hssi_rx_transfer_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.aib_hssi_tx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.aib_hssi_tx_sr_clk_out_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.aib_hssi_tx_transfer_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.bti_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.direct_sel0 == DIRECT_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.e200g_aib1_tx_st_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.e200g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.e200g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.e200g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.e200g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.e200g_rx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.e200g_tx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.e400g_aib1_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.e400g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.e400g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.e400g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.e400g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.e400g_rx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.e400g_tx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.global_avmm_clk_hz == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.internal_clk1_source == INTERNAL_CLK1_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.internal_clk2_source == INTERNAL_CLK2_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.pcie_pld_2x_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.pcie_pld_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.pcie_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.pcie_tx_transfer_div2_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.pld_pcs_rx_clk_out_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.pld_pcs_tx_clk_out_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.pma_aib_tx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.powermode_ac_avmm1 == AC_AVMM1_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.powermode_ac_avmm2 == AC_AVMM2_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.powermode_ac_global_avmm == GLOBAL_AVMM_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.powermode_ac_rx_datapath == AC_RX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.powermode_ac_sr == AC_SR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.powermode_ac_tx_datapath == AC_TX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.powermode_dc == POWERUP_DC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.powermode_freq_hz_aib_rx_sr_clk_in == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.powermode_freq_hz_aib_rx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.powermode_freq_hz_aib_tx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.powermode_freq_hz_global_avmm_clk == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.sr_prot_mode == SR_PROT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.async_direct_sel0 == DIRECT_SEL0_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.async_direct_sel1 == DIRECT_SEL1_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.async_direct_sel2 == DIRECT_SEL2_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.async_direct_sel3 == DIRECT_SEL3_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.avmm1_free_run_div_clk == AVMM1_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.avmm1_write_resp_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.avmm2_free_run_div_clk == AVMM2_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.avmm2_global_usr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.dfd_cntr_inc_value == 9'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.dfd_cntr_rst_b == CNTR_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_ch_sel == GP0_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_cntr_data_sel == GP0_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_rsvd == GP0_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_testbus_sel == GP0_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_ch_sel == GP1_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_cntr_data_sel == GP1_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_rsvd == GP1_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_testbus_sel == GP1_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.dfd_mux_rst_b == MUX_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.hwcfg_adpt_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.hwcfg_aib_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.hwcfg_mode == BLOCK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.sr_prot_map_mode == MAP_SR_PROT_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.sr_test_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.sr_xcvr_map_mode == MAP_SR_XCVR_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.adapter_lpbk_mode == LOOPBACK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.aib_lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.async_direct_hip_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.datapath_mapping_mode == MAP_RX_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_sel == FIFO_RD_BTI_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_sel == FIFO_WR_PCIE_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.hrdrst_rst_sm_dis == DISABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel == FEEDTHRU_CLK1_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel0 == TXFIFOWR_FROM_AIB_MUX_CLK1_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel1 == FEEDTHRU_CLKS_OR_TXFIFORD_PRE_OR_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel2 == PMA_CLKS_OR_TXFIFORD_PRE_CT_MUX_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel3 == PMA_CLKS_CLK1_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel == FEEDTHRU_CLK0_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel0 == RXFIFORD_TO_AIB_MUX_CLK2_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_PRE_OR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel2 == PMA_CLKS_OR_RXFIFOWR_PRE_CT_MUX_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel3 == PMA_CLKS_CLK2_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.msb_pipeline_byp == MSB_PIPE_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.pld_pcs_rx_clk_out_sel == PLD_PCS_RX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.pma_aib_rx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.pma_coreclkin_sel == PMA_CORECLKIN_PLD_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.rx_10g_krfec_rx_diag_data_status_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.rx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.rx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.rx_parity_sel == FUNC_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.rx_pcs_testbus_sel == DIRECT_TR_TB_BIT0_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.rx_pcspma_testbus_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_a1a2_k1k2_flag_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_wa_boundary_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_pcie_sw_done_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_reser_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_testbus_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.rx_pld_test_data_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_num_stages == RMFFLAG_TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.rx_user_clk_rst_sel == RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.rx_user_clk_sel == RX_USER_CLK_E400G_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.rx_usertest_sel == DIRECT_TR_USERTEST3_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.rxfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.rxfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.rxfifo_mode == RXBYPASS_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.rxfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.rxfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.rxfiford_post_ct_sel == RXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.rxfiford_to_aib_sel == RXFIFORD_SCLK_TO_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.rxfifowr_post_ct_sel == RXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.rxfifowr_pre_ct_sel == RXFIFOWR_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.txfiford_post_ct_sel == TXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.txfiford_pre_ct_sel == TXFIFORD_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.txfifowr_from_aib_sel == TXFIFOWR_SCLK_FROM_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.txfifowr_post_ct_sel == TXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_rxchnl.word_mark == WM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_sr.sr_free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_sr.sr_osc_clk_div_sel == NON_DIV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.datapath_mapping_mode == MAP_TX_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.dv_gating == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.fifo_double_read == FIFO_DOUBLE_READ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_sel == FIFO_RD_PCIE_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.hrdrst_rst_sm_dis == DISABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.pld_pcs_tx_clk_out_sel == PLD_PCS_TX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.pma_aib_tx_clk_sel == PMA_AIB_TX_CLK_BTI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.tx_datapath_tb_sel == WA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.tx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.tx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.tx_latency_src_xcvrif == LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.tx_rev_lpbk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e200g_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e400g_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.tx_transfer_div2_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.tx_user_clk_rst_sel == TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.tx_user_clk_sel == TX_USER_CLK_E400G_DIV4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.tx_usertest_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.txfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.txfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.gdr_aibadapter.adapt_txchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_dc == AVMM1_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_dc == AVMM2_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr1 == AIB_DDR1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_clkdiv == AIB_RX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp == AIB_RX_DCC_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp_iocsr_unused == AIB_RX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal == AIB_RX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal_iocsr_unused == AIB_RX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft == AIB_RX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft_sel == AIB_RX_DCC_DFT_MODE1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dll_entest == AIB_RX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctl_static == AIB_RX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctlsel == AIB_RX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en == AIB_RX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en_iocsr_unused == AIB_RX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_dn == AIB_RX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_up == AIB_RX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_pi_slw == AIB_RX_DCC_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_rst_prgmnvrt == AIB_RX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_dn_prgmnvrt == AIB_RX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_up_prgmnvrt == AIB_RX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_updnen == AIB_RX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dftmuxsel == AIB_RX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dly_pst == AIB_RX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_en == AIB_RX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_lockreq_muxsel == AIB_RX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll == AIB_RX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll2 == AIB_RX_DCC_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_rst == AIB_RX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_test_clk_pll_en_n == AIB_RX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_halfcode == AIB_RX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_selflock == AIB_RX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.op_mode == RX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_dc == RXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dcc_dll_dft_sel == AIB_DLLSTR_ALIGN_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dft_ch_muxsel == AIB_DLLSTR_ALIGN_DFT_CH_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_pi_slw == AIB_DLLSTR_ALIGN_PI_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll == AIB_DLLSTR_ALIGN_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll2 == AIB_DLLSTR_ALIGN_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_pinp_shiften == AIB_RED_PINP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.op_mode == TX_DLL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_dc == TXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_2.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.aib_hssi_rx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.aib_hssi_rx_transfer_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.aib_hssi_tx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.aib_hssi_tx_sr_clk_out_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.aib_hssi_tx_transfer_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.bti_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.direct_sel0 == DIRECT_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.e200g_aib1_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.e200g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.e200g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.e200g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.e200g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.e200g_rx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.e200g_tx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.e400g_aib1_tx_st_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.e400g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.e400g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.e400g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.e400g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.e400g_rx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.e400g_tx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.global_avmm_clk_hz == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.internal_clk1_source == INTERNAL_CLK1_XCVR_REFCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.internal_clk2_source == INTERNAL_CLK2_XCVR_REFCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.pcie_pld_2x_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.pcie_pld_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.pcie_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.pcie_tx_transfer_div2_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.pld_pcs_rx_clk_out_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.pld_pcs_tx_clk_out_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.pma_aib_tx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.powermode_ac_avmm1 == AC_AVMM1_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.powermode_ac_avmm2 == AC_AVMM2_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.powermode_ac_global_avmm == GLOBAL_AVMM_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.powermode_ac_rx_datapath == AC_RX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.powermode_ac_sr == AC_SR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.powermode_ac_tx_datapath == AC_TX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.powermode_dc == POWERUP_DC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.powermode_freq_hz_aib_rx_sr_clk_in == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.powermode_freq_hz_aib_rx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.powermode_freq_hz_aib_tx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.powermode_freq_hz_global_avmm_clk == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.sr_prot_mode == SR_PROT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.async_direct_sel0 == DIRECT_SEL0_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.async_direct_sel1 == DIRECT_SEL1_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.async_direct_sel2 == DIRECT_SEL2_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.async_direct_sel3 == DIRECT_SEL3_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.avmm1_free_run_div_clk == AVMM1_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.avmm1_write_resp_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.avmm2_free_run_div_clk == AVMM2_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.avmm2_global_usr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.avmm2_osc_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.dfd_cntr_inc_value == 9'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.dfd_cntr_rst_b == CNTR_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_ch_sel == GP0_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_cntr_data_sel == GP0_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_rsvd == GP0_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_testbus_sel == GP0_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_ch_sel == GP1_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_cntr_data_sel == GP1_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_rsvd == GP1_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_testbus_sel == GP1_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.dfd_mux_rst_b == MUX_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.hwcfg_adpt_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.hwcfg_aib_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.hwcfg_mode == BLOCK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.sr_prot_map_mode == MAP_SR_PROT_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.sr_test_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.sr_xcvr_map_mode == MAP_SR_XCVR_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.adapter_lpbk_mode == LOOPBACK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.aib_lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.async_direct_hip_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.datapath_mapping_mode == MAP_RX_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_sel == FIFO_RD_BTI_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_sel == FIFO_WR_PCIE_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.hrdrst_rst_sm_dis == DISABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel == FEEDTHRU_CLK1_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel0 == FEEDTHRU_CLKS_OR_TXFIFOWR_POST_CT_OR_TXFIFORD_PRE_OR_POST_CT_MUX_CLK1_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel1 == FEEDTHRU_CLKS_OR_TXFIFORD_PRE_OR_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel2 == PMA_CLKS_OR_TXFIFORD_PRE_CT_MUX_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel3 == PMA_CLKS_CLK1_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel == FEEDTHRU_CLK0_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel0 == PMA_CLKS_OR_RXFIFORD_POST_CT_OR_RXFIFOWR_PRE_OR_POST_CT_MUX_CLK2_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_PRE_OR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel2 == PMA_CLKS_OR_RXFIFOWR_PRE_CT_MUX_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel3 == PMA_CLKS_CLK2_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.msb_pipeline_byp == MSB_PIPE_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.pld_pcs_rx_clk_out_sel == PLD_PCS_RX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.pma_aib_rx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.pma_coreclkin_sel == PMA_CORECLKIN_PLD_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.rx_10g_krfec_rx_diag_data_status_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.rx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.rx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.rx_parity_sel == FUNC_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.rx_pcs_testbus_sel == DIRECT_TR_TB_BIT0_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.rx_pcspma_testbus_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_a1a2_k1k2_flag_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_wa_boundary_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_pcie_sw_done_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_reser_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_testbus_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.rx_pld_test_data_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_num_stages == RMFFLAG_TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.rx_user_clk_rst_sel == RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.rx_user_clk_sel == RX_USER_CLK_E400G_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.rx_usertest_sel == DIRECT_TR_USERTEST3_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.rxfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.rxfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.rxfifo_mode == RXBYPASS_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.rxfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.rxfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.rxfiford_post_ct_sel == RXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.rxfiford_to_aib_sel == RXFIFORD_SCLK_TO_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.rxfifowr_post_ct_sel == RXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.rxfifowr_pre_ct_sel == RXFIFOWR_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.txfiford_post_ct_sel == TXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.txfiford_pre_ct_sel == TXFIFORD_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.txfifowr_from_aib_sel == TXFIFOWR_SCLK_FROM_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.txfifowr_post_ct_sel == TXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_rxchnl.word_mark == WM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_sr.sr_free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_sr.sr_osc_clk_div_sel == NON_DIV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.datapath_mapping_mode == MAP_TX_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.dv_gating == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.fifo_double_read == FIFO_DOUBLE_READ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_sel == FIFO_RD_PCIE_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.hrdrst_rst_sm_dis == DISABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.pld_pcs_tx_clk_out_sel == PLD_PCS_TX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.pma_aib_tx_clk_sel == PMA_AIB_TX_CLK_BTI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.tx_datapath_tb_sel == WA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.tx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.tx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.tx_latency_src_xcvrif == LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.tx_rev_lpbk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e200g_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e400g_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.tx_transfer_div2_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.tx_user_clk_rst_sel == TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.tx_user_clk_sel == TX_USER_CLK_E400G_DIV4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.tx_usertest_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.txfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.txfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.gdr_aibadapter.adapt_txchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_dc == AVMM1_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.op_mode == PWR_DOWN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_ac == POWERDOWN_AC_AVMM2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_dc == POWERDOWN_DC_AVMM2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr1 == AIB_DDR1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_clkdiv == AIB_RX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp == AIB_RX_DCC_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp_iocsr_unused == AIB_RX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal == AIB_RX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal_iocsr_unused == AIB_RX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft == AIB_RX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft_sel == AIB_RX_DCC_DFT_MODE1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dll_entest == AIB_RX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctl_static == AIB_RX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctlsel == AIB_RX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en == AIB_RX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en_iocsr_unused == AIB_RX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_dn == AIB_RX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_up == AIB_RX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_pi_slw == AIB_RX_DCC_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_rst_prgmnvrt == AIB_RX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_dn_prgmnvrt == AIB_RX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_up_prgmnvrt == AIB_RX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_updnen == AIB_RX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dftmuxsel == AIB_RX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dly_pst == AIB_RX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_en == AIB_RX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_lockreq_muxsel == AIB_RX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll == AIB_RX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll2 == AIB_RX_DCC_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_rst == AIB_RX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_test_clk_pll_en_n == AIB_RX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_halfcode == AIB_RX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_selflock == AIB_RX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.op_mode == RX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_dc == RXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dcc_dll_dft_sel == AIB_DLLSTR_ALIGN_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dft_ch_muxsel == AIB_DLLSTR_ALIGN_DFT_CH_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_pi_slw == AIB_DLLSTR_ALIGN_PI_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll == AIB_DLLSTR_ALIGN_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll2 == AIB_DLLSTR_ALIGN_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_pinp_shiften == AIB_RED_PINP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.op_mode == TX_DLL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_dc == TXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_20.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.aib_hssi_rx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.aib_hssi_rx_transfer_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.aib_hssi_tx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.aib_hssi_tx_sr_clk_out_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.aib_hssi_tx_transfer_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.bti_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.direct_sel0 == DIRECT_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.e200g_aib1_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.e200g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.e200g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.e200g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.e200g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.e200g_rx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.e200g_tx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.e400g_aib1_tx_st_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.e400g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.e400g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.e400g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.e400g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.e400g_rx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.e400g_tx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.global_avmm_clk_hz == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.internal_clk1_source == INTERNAL_CLK1_XCVR_REFCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.internal_clk2_source == INTERNAL_CLK2_XCVR_REFCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.pcie_pld_2x_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.pcie_pld_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.pcie_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.pcie_tx_transfer_div2_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.pld_pcs_rx_clk_out_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.pld_pcs_tx_clk_out_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.pma_aib_tx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.powermode_ac_avmm1 == AC_AVMM1_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.powermode_ac_avmm2 == AC_AVMM2_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.powermode_ac_global_avmm == GLOBAL_AVMM_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.powermode_ac_rx_datapath == AC_RX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.powermode_ac_sr == AC_SR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.powermode_ac_tx_datapath == AC_TX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.powermode_dc == POWERUP_DC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.powermode_freq_hz_aib_rx_sr_clk_in == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.powermode_freq_hz_aib_rx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.powermode_freq_hz_aib_tx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.powermode_freq_hz_global_avmm_clk == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.sr_prot_mode == SR_PROT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.async_direct_sel0 == DIRECT_SEL0_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.async_direct_sel1 == DIRECT_SEL1_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.async_direct_sel2 == DIRECT_SEL2_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.async_direct_sel3 == DIRECT_SEL3_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.avmm1_free_run_div_clk == AVMM1_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.avmm1_write_resp_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.avmm2_free_run_div_clk == AVMM2_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.avmm2_global_usr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.avmm2_osc_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.dfd_cntr_inc_value == 9'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.dfd_cntr_rst_b == CNTR_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_ch_sel == GP0_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_cntr_data_sel == GP0_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_rsvd == GP0_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_testbus_sel == GP0_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_ch_sel == GP1_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_cntr_data_sel == GP1_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_rsvd == GP1_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_testbus_sel == GP1_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.dfd_mux_rst_b == MUX_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.hwcfg_adpt_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.hwcfg_aib_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.hwcfg_mode == BLOCK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.sr_prot_map_mode == MAP_SR_PROT_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.sr_test_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.sr_xcvr_map_mode == MAP_SR_XCVR_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.adapter_lpbk_mode == LOOPBACK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.aib_lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.async_direct_hip_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.datapath_mapping_mode == MAP_RX_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_sel == FIFO_RD_BTI_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_sel == FIFO_WR_PCIE_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.hrdrst_rst_sm_dis == DISABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel == FEEDTHRU_CLK1_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel0 == FEEDTHRU_CLKS_OR_TXFIFOWR_POST_CT_OR_TXFIFORD_PRE_OR_POST_CT_MUX_CLK1_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel1 == FEEDTHRU_CLKS_OR_TXFIFORD_PRE_OR_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel2 == PMA_CLKS_OR_TXFIFORD_PRE_CT_MUX_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel3 == PMA_CLKS_CLK1_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel == FEEDTHRU_CLK0_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel0 == PMA_CLKS_OR_RXFIFORD_POST_CT_OR_RXFIFOWR_PRE_OR_POST_CT_MUX_CLK2_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_PRE_OR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel2 == PMA_CLKS_OR_RXFIFOWR_PRE_CT_MUX_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel3 == PMA_CLKS_CLK2_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.msb_pipeline_byp == MSB_PIPE_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.pld_pcs_rx_clk_out_sel == PLD_PCS_RX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.pma_aib_rx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.pma_coreclkin_sel == PMA_CORECLKIN_PLD_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.rx_10g_krfec_rx_diag_data_status_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.rx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.rx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.rx_parity_sel == FUNC_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.rx_pcs_testbus_sel == DIRECT_TR_TB_BIT0_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.rx_pcspma_testbus_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_a1a2_k1k2_flag_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_wa_boundary_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_pcie_sw_done_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_reser_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_testbus_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.rx_pld_test_data_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_num_stages == RMFFLAG_TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.rx_user_clk_rst_sel == RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.rx_user_clk_sel == RX_USER_CLK_E400G_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.rx_usertest_sel == DIRECT_TR_USERTEST3_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.rxfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.rxfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.rxfifo_mode == RXBYPASS_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.rxfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.rxfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.rxfiford_post_ct_sel == RXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.rxfiford_to_aib_sel == RXFIFORD_SCLK_TO_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.rxfifowr_post_ct_sel == RXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.rxfifowr_pre_ct_sel == RXFIFOWR_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.txfiford_post_ct_sel == TXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.txfiford_pre_ct_sel == TXFIFORD_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.txfifowr_from_aib_sel == TXFIFOWR_SCLK_FROM_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.txfifowr_post_ct_sel == TXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_rxchnl.word_mark == WM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_sr.sr_free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_sr.sr_osc_clk_div_sel == NON_DIV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.datapath_mapping_mode == MAP_TX_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.dv_gating == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.fifo_double_read == FIFO_DOUBLE_READ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_sel == FIFO_RD_PCIE_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.hrdrst_rst_sm_dis == DISABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.pld_pcs_tx_clk_out_sel == PLD_PCS_TX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.pma_aib_tx_clk_sel == PMA_AIB_TX_CLK_BTI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.tx_datapath_tb_sel == WA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.tx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.tx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.tx_latency_src_xcvrif == LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.tx_rev_lpbk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e200g_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e400g_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.tx_transfer_div2_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.tx_user_clk_rst_sel == TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.tx_user_clk_sel == TX_USER_CLK_E400G_DIV4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.tx_usertest_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.txfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.txfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.gdr_aibadapter.adapt_txchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_dc == AVMM1_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.op_mode == PWR_DOWN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_ac == POWERDOWN_AC_AVMM2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_dc == POWERDOWN_DC_AVMM2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr1 == AIB_DDR1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_clkdiv == AIB_RX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp == AIB_RX_DCC_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp_iocsr_unused == AIB_RX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal == AIB_RX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal_iocsr_unused == AIB_RX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft == AIB_RX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft_sel == AIB_RX_DCC_DFT_MODE1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dll_entest == AIB_RX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctl_static == AIB_RX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctlsel == AIB_RX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en == AIB_RX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en_iocsr_unused == AIB_RX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_dn == AIB_RX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_up == AIB_RX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_pi_slw == AIB_RX_DCC_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_rst_prgmnvrt == AIB_RX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_dn_prgmnvrt == AIB_RX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_up_prgmnvrt == AIB_RX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_updnen == AIB_RX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dftmuxsel == AIB_RX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dly_pst == AIB_RX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_en == AIB_RX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_lockreq_muxsel == AIB_RX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll == AIB_RX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll2 == AIB_RX_DCC_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_rst == AIB_RX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_test_clk_pll_en_n == AIB_RX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_halfcode == AIB_RX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_selflock == AIB_RX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.op_mode == RX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_dc == RXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dcc_dll_dft_sel == AIB_DLLSTR_ALIGN_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dft_ch_muxsel == AIB_DLLSTR_ALIGN_DFT_CH_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_pi_slw == AIB_DLLSTR_ALIGN_PI_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll == AIB_DLLSTR_ALIGN_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll2 == AIB_DLLSTR_ALIGN_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_pinp_shiften == AIB_RED_PINP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.op_mode == TX_DLL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_dc == TXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_21.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.aib_hssi_rx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.aib_hssi_rx_transfer_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.aib_hssi_tx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.aib_hssi_tx_sr_clk_out_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.aib_hssi_tx_transfer_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.bti_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.direct_sel0 == DIRECT_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.e200g_aib1_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.e200g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.e200g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.e200g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.e200g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.e200g_rx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.e200g_tx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.e400g_aib1_tx_st_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.e400g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.e400g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.e400g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.e400g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.e400g_rx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.e400g_tx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.global_avmm_clk_hz == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.internal_clk1_source == INTERNAL_CLK1_XCVR_REFCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.internal_clk2_source == INTERNAL_CLK2_XCVR_REFCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.pcie_pld_2x_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.pcie_pld_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.pcie_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.pcie_tx_transfer_div2_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.pld_pcs_rx_clk_out_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.pld_pcs_tx_clk_out_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.pma_aib_tx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.powermode_ac_avmm1 == AC_AVMM1_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.powermode_ac_avmm2 == AC_AVMM2_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.powermode_ac_global_avmm == GLOBAL_AVMM_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.powermode_ac_rx_datapath == AC_RX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.powermode_ac_sr == AC_SR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.powermode_ac_tx_datapath == AC_TX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.powermode_dc == POWERUP_DC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.powermode_freq_hz_aib_rx_sr_clk_in == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.powermode_freq_hz_aib_rx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.powermode_freq_hz_aib_tx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.powermode_freq_hz_global_avmm_clk == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.sr_prot_mode == SR_PROT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.async_direct_sel0 == DIRECT_SEL0_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.async_direct_sel1 == DIRECT_SEL1_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.async_direct_sel2 == DIRECT_SEL2_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.async_direct_sel3 == DIRECT_SEL3_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.avmm1_free_run_div_clk == AVMM1_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.avmm1_write_resp_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.avmm2_free_run_div_clk == AVMM2_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.avmm2_global_usr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.avmm2_osc_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.dfd_cntr_inc_value == 9'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.dfd_cntr_rst_b == CNTR_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_ch_sel == GP0_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_cntr_data_sel == GP0_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_rsvd == GP0_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_testbus_sel == GP0_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_ch_sel == GP1_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_cntr_data_sel == GP1_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_rsvd == GP1_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_testbus_sel == GP1_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.dfd_mux_rst_b == MUX_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.hwcfg_adpt_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.hwcfg_aib_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.hwcfg_mode == BLOCK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.sr_prot_map_mode == MAP_SR_PROT_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.sr_test_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.sr_xcvr_map_mode == MAP_SR_XCVR_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.adapter_lpbk_mode == LOOPBACK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.aib_lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.async_direct_hip_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.datapath_mapping_mode == MAP_RX_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_sel == FIFO_RD_BTI_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_sel == FIFO_WR_PCIE_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.hrdrst_rst_sm_dis == DISABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel == FEEDTHRU_CLK1_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel0 == FEEDTHRU_CLKS_OR_TXFIFOWR_POST_CT_OR_TXFIFORD_PRE_OR_POST_CT_MUX_CLK1_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel1 == FEEDTHRU_CLKS_OR_TXFIFORD_PRE_OR_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel2 == PMA_CLKS_OR_TXFIFORD_PRE_CT_MUX_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel3 == PMA_CLKS_CLK1_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel == FEEDTHRU_CLK0_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel0 == PMA_CLKS_OR_RXFIFORD_POST_CT_OR_RXFIFOWR_PRE_OR_POST_CT_MUX_CLK2_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_PRE_OR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel2 == PMA_CLKS_OR_RXFIFOWR_PRE_CT_MUX_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel3 == PMA_CLKS_CLK2_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.msb_pipeline_byp == MSB_PIPE_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.pld_pcs_rx_clk_out_sel == PLD_PCS_RX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.pma_aib_rx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.pma_coreclkin_sel == PMA_CORECLKIN_PLD_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.rx_10g_krfec_rx_diag_data_status_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.rx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.rx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.rx_parity_sel == FUNC_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.rx_pcs_testbus_sel == DIRECT_TR_TB_BIT0_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.rx_pcspma_testbus_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_a1a2_k1k2_flag_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_wa_boundary_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_pcie_sw_done_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_reser_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_testbus_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.rx_pld_test_data_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_num_stages == RMFFLAG_TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.rx_user_clk_rst_sel == RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.rx_user_clk_sel == RX_USER_CLK_E400G_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.rx_usertest_sel == DIRECT_TR_USERTEST3_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.rxfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.rxfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.rxfifo_mode == RXBYPASS_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.rxfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.rxfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.rxfiford_post_ct_sel == RXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.rxfiford_to_aib_sel == RXFIFORD_SCLK_TO_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.rxfifowr_post_ct_sel == RXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.rxfifowr_pre_ct_sel == RXFIFOWR_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.txfiford_post_ct_sel == TXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.txfiford_pre_ct_sel == TXFIFORD_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.txfifowr_from_aib_sel == TXFIFOWR_SCLK_FROM_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.txfifowr_post_ct_sel == TXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_rxchnl.word_mark == WM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_sr.sr_free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_sr.sr_osc_clk_div_sel == NON_DIV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.datapath_mapping_mode == MAP_TX_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.dv_gating == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.fifo_double_read == FIFO_DOUBLE_READ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_sel == FIFO_RD_PCIE_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.hrdrst_rst_sm_dis == DISABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.pld_pcs_tx_clk_out_sel == PLD_PCS_TX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.pma_aib_tx_clk_sel == PMA_AIB_TX_CLK_BTI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.tx_datapath_tb_sel == WA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.tx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.tx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.tx_latency_src_xcvrif == LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.tx_rev_lpbk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e200g_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e400g_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.tx_transfer_div2_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.tx_user_clk_rst_sel == TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.tx_user_clk_sel == TX_USER_CLK_E400G_DIV4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.tx_usertest_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.txfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.txfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.gdr_aibadapter.adapt_txchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_dc == AVMM1_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.op_mode == PWR_DOWN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_ac == POWERDOWN_AC_AVMM2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_dc == POWERDOWN_DC_AVMM2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr1 == AIB_DDR1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_clkdiv == AIB_RX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp == AIB_RX_DCC_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp_iocsr_unused == AIB_RX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal == AIB_RX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal_iocsr_unused == AIB_RX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft == AIB_RX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft_sel == AIB_RX_DCC_DFT_MODE1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dll_entest == AIB_RX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctl_static == AIB_RX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctlsel == AIB_RX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en == AIB_RX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en_iocsr_unused == AIB_RX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_dn == AIB_RX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_up == AIB_RX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_pi_slw == AIB_RX_DCC_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_rst_prgmnvrt == AIB_RX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_dn_prgmnvrt == AIB_RX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_up_prgmnvrt == AIB_RX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_updnen == AIB_RX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dftmuxsel == AIB_RX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dly_pst == AIB_RX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_en == AIB_RX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_lockreq_muxsel == AIB_RX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll == AIB_RX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll2 == AIB_RX_DCC_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_rst == AIB_RX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_test_clk_pll_en_n == AIB_RX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_halfcode == AIB_RX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_selflock == AIB_RX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.op_mode == RX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_dc == RXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dcc_dll_dft_sel == AIB_DLLSTR_ALIGN_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dft_ch_muxsel == AIB_DLLSTR_ALIGN_DFT_CH_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_pi_slw == AIB_DLLSTR_ALIGN_PI_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll == AIB_DLLSTR_ALIGN_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll2 == AIB_DLLSTR_ALIGN_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_pinp_shiften == AIB_RED_PINP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.op_mode == TX_DLL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_dc == TXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_22.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.aib_hssi_rx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.aib_hssi_rx_transfer_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.aib_hssi_tx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.aib_hssi_tx_sr_clk_out_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.aib_hssi_tx_transfer_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.bti_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.direct_sel0 == DIRECT_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.e200g_aib1_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.e200g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.e200g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.e200g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.e200g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.e200g_rx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.e200g_tx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.e400g_aib1_tx_st_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.e400g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.e400g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.e400g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.e400g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.e400g_rx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.e400g_tx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.global_avmm_clk_hz == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.internal_clk1_source == INTERNAL_CLK1_XCVR_REFCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.internal_clk2_source == INTERNAL_CLK2_XCVR_REFCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.pcie_pld_2x_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.pcie_pld_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.pcie_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.pcie_tx_transfer_div2_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.pld_pcs_rx_clk_out_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.pld_pcs_tx_clk_out_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.pma_aib_tx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.powermode_ac_avmm1 == AC_AVMM1_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.powermode_ac_avmm2 == AC_AVMM2_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.powermode_ac_global_avmm == GLOBAL_AVMM_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.powermode_ac_rx_datapath == AC_RX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.powermode_ac_sr == AC_SR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.powermode_ac_tx_datapath == AC_TX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.powermode_dc == POWERUP_DC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.powermode_freq_hz_aib_rx_sr_clk_in == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.powermode_freq_hz_aib_rx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.powermode_freq_hz_aib_tx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.powermode_freq_hz_global_avmm_clk == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.sr_prot_mode == SR_PROT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.async_direct_sel0 == DIRECT_SEL0_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.async_direct_sel1 == DIRECT_SEL1_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.async_direct_sel2 == DIRECT_SEL2_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.async_direct_sel3 == DIRECT_SEL3_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.avmm1_free_run_div_clk == AVMM1_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.avmm1_write_resp_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.avmm2_free_run_div_clk == AVMM2_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.avmm2_global_usr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.avmm2_osc_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.dfd_cntr_inc_value == 9'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.dfd_cntr_rst_b == CNTR_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_ch_sel == GP0_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_cntr_data_sel == GP0_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_rsvd == GP0_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_testbus_sel == GP0_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_ch_sel == GP1_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_cntr_data_sel == GP1_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_rsvd == GP1_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_testbus_sel == GP1_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.dfd_mux_rst_b == MUX_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.hwcfg_adpt_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.hwcfg_aib_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.hwcfg_mode == BLOCK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.sr_prot_map_mode == MAP_SR_PROT_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.sr_test_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.sr_xcvr_map_mode == MAP_SR_XCVR_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.adapter_lpbk_mode == LOOPBACK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.aib_lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.async_direct_hip_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.datapath_mapping_mode == MAP_RX_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_sel == FIFO_RD_BTI_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_sel == FIFO_WR_PCIE_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.hrdrst_rst_sm_dis == DISABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel == FEEDTHRU_CLK1_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel0 == FEEDTHRU_CLKS_OR_TXFIFOWR_POST_CT_OR_TXFIFORD_PRE_OR_POST_CT_MUX_CLK1_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel1 == FEEDTHRU_CLKS_OR_TXFIFORD_PRE_OR_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel2 == PMA_CLKS_OR_TXFIFORD_PRE_CT_MUX_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel3 == PMA_CLKS_CLK1_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel == FEEDTHRU_CLK0_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel0 == PMA_CLKS_OR_RXFIFORD_POST_CT_OR_RXFIFOWR_PRE_OR_POST_CT_MUX_CLK2_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_PRE_OR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel2 == PMA_CLKS_OR_RXFIFOWR_PRE_CT_MUX_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel3 == PMA_CLKS_CLK2_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.msb_pipeline_byp == MSB_PIPE_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.pld_pcs_rx_clk_out_sel == PLD_PCS_RX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.pma_aib_rx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.pma_coreclkin_sel == PMA_CORECLKIN_PLD_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.rx_10g_krfec_rx_diag_data_status_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.rx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.rx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.rx_parity_sel == FUNC_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.rx_pcs_testbus_sel == DIRECT_TR_TB_BIT0_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.rx_pcspma_testbus_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_a1a2_k1k2_flag_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_wa_boundary_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_pcie_sw_done_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_reser_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_testbus_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.rx_pld_test_data_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_num_stages == RMFFLAG_TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.rx_user_clk_rst_sel == RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.rx_user_clk_sel == RX_USER_CLK_E400G_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.rx_usertest_sel == DIRECT_TR_USERTEST3_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.rxfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.rxfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.rxfifo_mode == RXBYPASS_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.rxfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.rxfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.rxfiford_post_ct_sel == RXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.rxfiford_to_aib_sel == RXFIFORD_SCLK_TO_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.rxfifowr_post_ct_sel == RXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.rxfifowr_pre_ct_sel == RXFIFOWR_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.txfiford_post_ct_sel == TXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.txfiford_pre_ct_sel == TXFIFORD_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.txfifowr_from_aib_sel == TXFIFOWR_SCLK_FROM_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.txfifowr_post_ct_sel == TXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_rxchnl.word_mark == WM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_sr.sr_free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_sr.sr_osc_clk_div_sel == NON_DIV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.datapath_mapping_mode == MAP_TX_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.dv_gating == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.fifo_double_read == FIFO_DOUBLE_READ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_sel == FIFO_RD_PCIE_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.hrdrst_rst_sm_dis == DISABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.pld_pcs_tx_clk_out_sel == PLD_PCS_TX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.pma_aib_tx_clk_sel == PMA_AIB_TX_CLK_BTI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.tx_datapath_tb_sel == WA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.tx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.tx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.tx_latency_src_xcvrif == LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.tx_rev_lpbk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e200g_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e400g_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.tx_transfer_div2_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.tx_user_clk_rst_sel == TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.tx_user_clk_sel == TX_USER_CLK_E400G_DIV4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.tx_usertest_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.txfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.txfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.gdr_aibadapter.adapt_txchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_dc == AVMM1_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.op_mode == PWR_DOWN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_ac == POWERDOWN_AC_AVMM2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_dc == POWERDOWN_DC_AVMM2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr1 == AIB_DDR1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_clkdiv == AIB_RX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp == AIB_RX_DCC_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp_iocsr_unused == AIB_RX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal == AIB_RX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal_iocsr_unused == AIB_RX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft == AIB_RX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft_sel == AIB_RX_DCC_DFT_MODE1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dll_entest == AIB_RX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctl_static == AIB_RX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctlsel == AIB_RX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en == AIB_RX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en_iocsr_unused == AIB_RX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_dn == AIB_RX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_up == AIB_RX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_pi_slw == AIB_RX_DCC_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_rst_prgmnvrt == AIB_RX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_dn_prgmnvrt == AIB_RX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_up_prgmnvrt == AIB_RX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_updnen == AIB_RX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dftmuxsel == AIB_RX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dly_pst == AIB_RX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_en == AIB_RX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_lockreq_muxsel == AIB_RX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll == AIB_RX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll2 == AIB_RX_DCC_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_rst == AIB_RX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_test_clk_pll_en_n == AIB_RX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_halfcode == AIB_RX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_selflock == AIB_RX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.op_mode == RX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_dc == RXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dcc_dll_dft_sel == AIB_DLLSTR_ALIGN_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dft_ch_muxsel == AIB_DLLSTR_ALIGN_DFT_CH_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_pi_slw == AIB_DLLSTR_ALIGN_PI_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll == AIB_DLLSTR_ALIGN_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll2 == AIB_DLLSTR_ALIGN_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_pinp_shiften == AIB_RED_PINP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.op_mode == TX_DLL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_dc == TXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_23.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.aib_hssi_rx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.aib_hssi_rx_transfer_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.aib_hssi_tx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.aib_hssi_tx_sr_clk_out_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.aib_hssi_tx_transfer_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.bti_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.direct_sel0 == DIRECT_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.e200g_aib1_tx_st_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.e200g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.e200g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.e200g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.e200g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.e200g_rx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.e200g_tx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.e400g_aib1_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.e400g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.e400g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.e400g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.e400g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.e400g_rx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.e400g_tx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.global_avmm_clk_hz == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.internal_clk1_source == INTERNAL_CLK1_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.internal_clk2_source == INTERNAL_CLK2_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.pcie_pld_2x_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.pcie_pld_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.pcie_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.pcie_tx_transfer_div2_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.pld_pcs_rx_clk_out_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.pld_pcs_tx_clk_out_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.pma_aib_tx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.powermode_ac_avmm1 == AC_AVMM1_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.powermode_ac_avmm2 == AC_AVMM2_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.powermode_ac_global_avmm == GLOBAL_AVMM_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.powermode_ac_rx_datapath == AC_RX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.powermode_ac_sr == AC_SR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.powermode_ac_tx_datapath == AC_TX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.powermode_dc == POWERUP_DC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.powermode_freq_hz_aib_rx_sr_clk_in == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.powermode_freq_hz_aib_rx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.powermode_freq_hz_aib_tx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.powermode_freq_hz_global_avmm_clk == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.sr_prot_mode == SR_PROT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.async_direct_sel0 == DIRECT_SEL0_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.async_direct_sel1 == DIRECT_SEL1_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.async_direct_sel2 == DIRECT_SEL2_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.async_direct_sel3 == DIRECT_SEL3_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.avmm1_free_run_div_clk == AVMM1_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.avmm1_write_resp_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.avmm2_free_run_div_clk == AVMM2_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.avmm2_global_usr_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.dfd_cntr_inc_value == 9'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.dfd_cntr_rst_b == CNTR_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_ch_sel == GP0_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_cntr_data_sel == GP0_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_rsvd == GP0_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_testbus_sel == GP0_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_ch_sel == GP1_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_cntr_data_sel == GP1_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_rsvd == GP1_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_testbus_sel == GP1_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.dfd_mux_rst_b == MUX_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.hwcfg_adpt_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.hwcfg_aib_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.hwcfg_mode == BLOCK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.sr_prot_map_mode == MAP_SR_PROT_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.sr_test_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.sr_xcvr_map_mode == MAP_SR_XCVR_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.adapter_lpbk_mode == LOOPBACK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.aib_lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.async_direct_hip_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.datapath_mapping_mode == MAP_RX_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_sel == FIFO_RD_BTI_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_sel == FIFO_WR_PCIE_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.hrdrst_rst_sm_dis == DISABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel == FEEDTHRU_CLK1_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel0 == TXFIFOWR_FROM_AIB_MUX_CLK1_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel1 == FEEDTHRU_CLKS_OR_TXFIFORD_PRE_OR_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel2 == PMA_CLKS_OR_TXFIFORD_PRE_CT_MUX_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel3 == PMA_CLKS_CLK1_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel == FEEDTHRU_CLK0_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel0 == RXFIFORD_TO_AIB_MUX_CLK2_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_PRE_OR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel2 == PMA_CLKS_OR_RXFIFOWR_PRE_CT_MUX_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel3 == PMA_CLKS_CLK2_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.msb_pipeline_byp == MSB_PIPE_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.pld_pcs_rx_clk_out_sel == PLD_PCS_RX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.pma_aib_rx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.pma_coreclkin_sel == PMA_CORECLKIN_PLD_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.rx_10g_krfec_rx_diag_data_status_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.rx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.rx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.rx_parity_sel == FUNC_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.rx_pcs_testbus_sel == DIRECT_TR_TB_BIT0_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.rx_pcspma_testbus_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_a1a2_k1k2_flag_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_wa_boundary_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_pcie_sw_done_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_reser_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_testbus_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.rx_pld_test_data_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_num_stages == RMFFLAG_TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.rx_user_clk_rst_sel == RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.rx_user_clk_sel == RX_USER_CLK_E400G_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.rx_usertest_sel == DIRECT_TR_USERTEST3_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.rxfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.rxfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.rxfifo_mode == RXBYPASS_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.rxfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.rxfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.rxfiford_post_ct_sel == RXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.rxfiford_to_aib_sel == RXFIFORD_SCLK_TO_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.rxfifowr_post_ct_sel == RXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.rxfifowr_pre_ct_sel == RXFIFOWR_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.txfiford_post_ct_sel == TXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.txfiford_pre_ct_sel == TXFIFORD_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.txfifowr_from_aib_sel == TXFIFOWR_SCLK_FROM_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.txfifowr_post_ct_sel == TXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_rxchnl.word_mark == WM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_sr.sr_free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_sr.sr_osc_clk_div_sel == NON_DIV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.datapath_mapping_mode == MAP_TX_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.dv_gating == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.fifo_double_read == FIFO_DOUBLE_READ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_sel == FIFO_RD_PCIE_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.hrdrst_rst_sm_dis == DISABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.pld_pcs_tx_clk_out_sel == PLD_PCS_TX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.pma_aib_tx_clk_sel == PMA_AIB_TX_CLK_BTI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.tx_datapath_tb_sel == WA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.tx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.tx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.tx_latency_src_xcvrif == LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.tx_rev_lpbk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e200g_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e400g_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.tx_transfer_div2_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.tx_user_clk_rst_sel == TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.tx_user_clk_sel == TX_USER_CLK_E400G_DIV4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.tx_usertest_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.txfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.txfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.gdr_aibadapter.adapt_txchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_dc == AVMM1_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_dc == AVMM2_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr1 == AIB_DDR1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_clkdiv == AIB_RX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp == AIB_RX_DCC_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp_iocsr_unused == AIB_RX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal == AIB_RX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal_iocsr_unused == AIB_RX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft == AIB_RX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft_sel == AIB_RX_DCC_DFT_MODE1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dll_entest == AIB_RX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctl_static == AIB_RX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctlsel == AIB_RX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en == AIB_RX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en_iocsr_unused == AIB_RX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_dn == AIB_RX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_up == AIB_RX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_pi_slw == AIB_RX_DCC_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_rst_prgmnvrt == AIB_RX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_dn_prgmnvrt == AIB_RX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_up_prgmnvrt == AIB_RX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_updnen == AIB_RX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dftmuxsel == AIB_RX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dly_pst == AIB_RX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_en == AIB_RX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_lockreq_muxsel == AIB_RX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll == AIB_RX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll2 == AIB_RX_DCC_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_rst == AIB_RX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_test_clk_pll_en_n == AIB_RX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_halfcode == AIB_RX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_selflock == AIB_RX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.op_mode == RX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_dc == RXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dcc_dll_dft_sel == AIB_DLLSTR_ALIGN_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dft_ch_muxsel == AIB_DLLSTR_ALIGN_DFT_CH_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_pi_slw == AIB_DLLSTR_ALIGN_PI_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll == AIB_DLLSTR_ALIGN_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll2 == AIB_DLLSTR_ALIGN_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_pinp_shiften == AIB_RED_PINP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.op_mode == TX_DLL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_dc == TXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_3.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.aib_hssi_rx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.aib_hssi_rx_transfer_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.aib_hssi_tx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.aib_hssi_tx_sr_clk_out_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.aib_hssi_tx_transfer_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.bti_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.direct_sel0 == DIRECT_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.e200g_aib1_tx_st_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.e200g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.e200g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.e200g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.e200g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.e200g_rx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.e200g_tx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.e400g_aib1_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.e400g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.e400g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.e400g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.e400g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.e400g_rx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.e400g_tx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.global_avmm_clk_hz == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.internal_clk1_source == INTERNAL_CLK1_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.internal_clk2_source == INTERNAL_CLK2_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.pcie_pld_2x_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.pcie_pld_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.pcie_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.pcie_tx_transfer_div2_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.pld_pcs_rx_clk_out_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.pld_pcs_tx_clk_out_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.pma_aib_tx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.powermode_ac_avmm1 == AC_AVMM1_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.powermode_ac_avmm2 == AC_AVMM2_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.powermode_ac_global_avmm == GLOBAL_AVMM_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.powermode_ac_rx_datapath == AC_RX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.powermode_ac_sr == AC_SR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.powermode_ac_tx_datapath == AC_TX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.powermode_dc == POWERUP_DC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.powermode_freq_hz_aib_rx_sr_clk_in == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.powermode_freq_hz_aib_rx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.powermode_freq_hz_aib_tx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.powermode_freq_hz_global_avmm_clk == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.sr_prot_mode == SR_PROT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.async_direct_sel0 == DIRECT_SEL0_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.async_direct_sel1 == DIRECT_SEL1_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.async_direct_sel2 == DIRECT_SEL2_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.async_direct_sel3 == DIRECT_SEL3_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.avmm1_free_run_div_clk == AVMM1_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.avmm1_write_resp_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.avmm2_free_run_div_clk == AVMM2_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.avmm2_global_usr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.dfd_cntr_inc_value == 9'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.dfd_cntr_rst_b == CNTR_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_ch_sel == GP0_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_cntr_data_sel == GP0_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_rsvd == GP0_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_testbus_sel == GP0_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_ch_sel == GP1_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_cntr_data_sel == GP1_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_rsvd == GP1_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_testbus_sel == GP1_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.dfd_mux_rst_b == MUX_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.hwcfg_adpt_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.hwcfg_aib_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.hwcfg_mode == BLOCK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.sr_prot_map_mode == MAP_SR_PROT_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.sr_test_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.sr_xcvr_map_mode == MAP_SR_XCVR_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.adapter_lpbk_mode == LOOPBACK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.aib_lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.async_direct_hip_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.datapath_mapping_mode == MAP_RX_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_sel == FIFO_RD_BTI_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_sel == FIFO_WR_PCIE_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.hrdrst_rst_sm_dis == DISABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel == FEEDTHRU_CLK1_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel0 == TXFIFOWR_FROM_AIB_MUX_CLK1_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel1 == FEEDTHRU_CLKS_OR_TXFIFORD_PRE_OR_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel2 == PMA_CLKS_OR_TXFIFORD_PRE_CT_MUX_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel3 == PMA_CLKS_CLK1_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel == FEEDTHRU_CLK0_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel0 == RXFIFORD_TO_AIB_MUX_CLK2_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_PRE_OR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel2 == PMA_CLKS_OR_RXFIFOWR_PRE_CT_MUX_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel3 == PMA_CLKS_CLK2_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.msb_pipeline_byp == MSB_PIPE_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.pld_pcs_rx_clk_out_sel == PLD_PCS_RX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.pma_aib_rx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.pma_coreclkin_sel == PMA_CORECLKIN_PLD_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.rx_10g_krfec_rx_diag_data_status_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.rx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.rx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.rx_parity_sel == FUNC_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.rx_pcs_testbus_sel == DIRECT_TR_TB_BIT0_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.rx_pcspma_testbus_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_a1a2_k1k2_flag_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_wa_boundary_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_pcie_sw_done_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_reser_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_testbus_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.rx_pld_test_data_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_num_stages == RMFFLAG_TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.rx_user_clk_rst_sel == RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.rx_user_clk_sel == RX_USER_CLK_E400G_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.rx_usertest_sel == DIRECT_TR_USERTEST3_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.rxfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.rxfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.rxfifo_mode == RXBYPASS_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.rxfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.rxfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.rxfiford_post_ct_sel == RXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.rxfiford_to_aib_sel == RXFIFORD_SCLK_TO_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.rxfifowr_post_ct_sel == RXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.rxfifowr_pre_ct_sel == RXFIFOWR_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.txfiford_post_ct_sel == TXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.txfiford_pre_ct_sel == TXFIFORD_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.txfifowr_from_aib_sel == TXFIFOWR_SCLK_FROM_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.txfifowr_post_ct_sel == TXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_rxchnl.word_mark == WM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_sr.sr_free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_sr.sr_osc_clk_div_sel == NON_DIV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.datapath_mapping_mode == MAP_TX_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.dv_gating == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.fifo_double_read == FIFO_DOUBLE_READ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_sel == FIFO_RD_PCIE_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.hrdrst_rst_sm_dis == DISABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.pld_pcs_tx_clk_out_sel == PLD_PCS_TX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.pma_aib_tx_clk_sel == PMA_AIB_TX_CLK_BTI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.tx_datapath_tb_sel == WA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.tx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.tx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.tx_latency_src_xcvrif == LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.tx_rev_lpbk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e200g_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e400g_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.tx_transfer_div2_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.tx_user_clk_rst_sel == TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.tx_user_clk_sel == TX_USER_CLK_E400G_DIV4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.tx_usertest_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.txfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.txfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.gdr_aibadapter.adapt_txchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_dc == AVMM1_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_dc == AVMM2_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr1 == AIB_DDR1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_clkdiv == AIB_RX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp == AIB_RX_DCC_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp_iocsr_unused == AIB_RX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal == AIB_RX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal_iocsr_unused == AIB_RX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft == AIB_RX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft_sel == AIB_RX_DCC_DFT_MODE1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dll_entest == AIB_RX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctl_static == AIB_RX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctlsel == AIB_RX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en == AIB_RX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en_iocsr_unused == AIB_RX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_dn == AIB_RX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_up == AIB_RX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_pi_slw == AIB_RX_DCC_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_rst_prgmnvrt == AIB_RX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_dn_prgmnvrt == AIB_RX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_up_prgmnvrt == AIB_RX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_updnen == AIB_RX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dftmuxsel == AIB_RX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dly_pst == AIB_RX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_en == AIB_RX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_lockreq_muxsel == AIB_RX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll == AIB_RX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll2 == AIB_RX_DCC_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_rst == AIB_RX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_test_clk_pll_en_n == AIB_RX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_halfcode == AIB_RX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_selflock == AIB_RX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.op_mode == RX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_dc == RXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dcc_dll_dft_sel == AIB_DLLSTR_ALIGN_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dft_ch_muxsel == AIB_DLLSTR_ALIGN_DFT_CH_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_pi_slw == AIB_DLLSTR_ALIGN_PI_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll == AIB_DLLSTR_ALIGN_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll2 == AIB_DLLSTR_ALIGN_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_pinp_shiften == AIB_RED_PINP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.op_mode == TX_DLL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_dc == TXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_4.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.aib_hssi_rx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.aib_hssi_rx_transfer_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.aib_hssi_tx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.aib_hssi_tx_sr_clk_out_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.aib_hssi_tx_transfer_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.bti_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.direct_sel0 == DIRECT_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.e200g_aib1_tx_st_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.e200g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.e200g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.e200g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.e200g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.e200g_rx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.e200g_tx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.e400g_aib1_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.e400g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.e400g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.e400g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.e400g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.e400g_rx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.e400g_tx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.global_avmm_clk_hz == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.internal_clk1_source == INTERNAL_CLK1_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.internal_clk2_source == INTERNAL_CLK2_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.pcie_pld_2x_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.pcie_pld_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.pcie_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.pcie_tx_transfer_div2_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.pld_pcs_rx_clk_out_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.pld_pcs_tx_clk_out_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.pma_aib_tx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.powermode_ac_avmm1 == AC_AVMM1_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.powermode_ac_avmm2 == AC_AVMM2_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.powermode_ac_global_avmm == GLOBAL_AVMM_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.powermode_ac_rx_datapath == AC_RX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.powermode_ac_sr == AC_SR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.powermode_ac_tx_datapath == AC_TX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.powermode_dc == POWERUP_DC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.powermode_freq_hz_aib_rx_sr_clk_in == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.powermode_freq_hz_aib_rx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.powermode_freq_hz_aib_tx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.powermode_freq_hz_global_avmm_clk == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.sr_prot_mode == SR_PROT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.async_direct_sel0 == DIRECT_SEL0_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.async_direct_sel1 == DIRECT_SEL1_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.async_direct_sel2 == DIRECT_SEL2_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.async_direct_sel3 == DIRECT_SEL3_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.avmm1_free_run_div_clk == AVMM1_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.avmm1_write_resp_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.avmm2_free_run_div_clk == AVMM2_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.avmm2_global_usr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.dfd_cntr_inc_value == 9'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.dfd_cntr_rst_b == CNTR_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_ch_sel == GP0_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_cntr_data_sel == GP0_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_rsvd == GP0_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_testbus_sel == GP0_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_ch_sel == GP1_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_cntr_data_sel == GP1_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_rsvd == GP1_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_testbus_sel == GP1_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.dfd_mux_rst_b == MUX_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.hwcfg_adpt_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.hwcfg_aib_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.hwcfg_mode == BLOCK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.sr_prot_map_mode == MAP_SR_PROT_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.sr_test_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.sr_xcvr_map_mode == MAP_SR_XCVR_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.adapter_lpbk_mode == LOOPBACK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.aib_lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.async_direct_hip_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.datapath_mapping_mode == MAP_RX_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_sel == FIFO_RD_BTI_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_sel == FIFO_WR_PCIE_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.hrdrst_rst_sm_dis == DISABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel == FEEDTHRU_CLK1_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel0 == TXFIFOWR_FROM_AIB_MUX_CLK1_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel1 == FEEDTHRU_CLKS_OR_TXFIFORD_PRE_OR_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel2 == PMA_CLKS_OR_TXFIFORD_PRE_CT_MUX_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel3 == PMA_CLKS_CLK1_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel == FEEDTHRU_CLK0_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel0 == RXFIFORD_TO_AIB_MUX_CLK2_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_PRE_OR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel2 == PMA_CLKS_OR_RXFIFOWR_PRE_CT_MUX_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel3 == PMA_CLKS_CLK2_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.msb_pipeline_byp == MSB_PIPE_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.pld_pcs_rx_clk_out_sel == PLD_PCS_RX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.pma_aib_rx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.pma_coreclkin_sel == PMA_CORECLKIN_PLD_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.rx_10g_krfec_rx_diag_data_status_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.rx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.rx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.rx_parity_sel == FUNC_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.rx_pcs_testbus_sel == DIRECT_TR_TB_BIT0_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.rx_pcspma_testbus_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_a1a2_k1k2_flag_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_wa_boundary_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_pcie_sw_done_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_reser_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_testbus_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.rx_pld_test_data_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_num_stages == RMFFLAG_TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.rx_user_clk_rst_sel == RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.rx_user_clk_sel == RX_USER_CLK_E400G_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.rx_usertest_sel == DIRECT_TR_USERTEST3_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.rxfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.rxfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.rxfifo_mode == RXBYPASS_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.rxfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.rxfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.rxfiford_post_ct_sel == RXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.rxfiford_to_aib_sel == RXFIFORD_SCLK_TO_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.rxfifowr_post_ct_sel == RXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.rxfifowr_pre_ct_sel == RXFIFOWR_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.txfiford_post_ct_sel == TXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.txfiford_pre_ct_sel == TXFIFORD_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.txfifowr_from_aib_sel == TXFIFOWR_SCLK_FROM_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.txfifowr_post_ct_sel == TXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_rxchnl.word_mark == WM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_sr.sr_free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_sr.sr_osc_clk_div_sel == NON_DIV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.datapath_mapping_mode == MAP_TX_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.dv_gating == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.fifo_double_read == FIFO_DOUBLE_READ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_sel == FIFO_RD_PCIE_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.hrdrst_rst_sm_dis == DISABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.pld_pcs_tx_clk_out_sel == PLD_PCS_TX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.pma_aib_tx_clk_sel == PMA_AIB_TX_CLK_BTI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.tx_datapath_tb_sel == WA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.tx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.tx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.tx_latency_src_xcvrif == LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.tx_rev_lpbk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e200g_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e400g_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.tx_transfer_div2_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.tx_user_clk_rst_sel == TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.tx_user_clk_sel == TX_USER_CLK_E400G_DIV4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.tx_usertest_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.txfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.txfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.gdr_aibadapter.adapt_txchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_dc == AVMM1_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_dc == AVMM2_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr1 == AIB_DDR1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_clkdiv == AIB_RX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp == AIB_RX_DCC_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp_iocsr_unused == AIB_RX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal == AIB_RX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal_iocsr_unused == AIB_RX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft == AIB_RX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft_sel == AIB_RX_DCC_DFT_MODE1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dll_entest == AIB_RX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctl_static == AIB_RX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctlsel == AIB_RX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en == AIB_RX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en_iocsr_unused == AIB_RX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_dn == AIB_RX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_up == AIB_RX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_pi_slw == AIB_RX_DCC_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_rst_prgmnvrt == AIB_RX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_dn_prgmnvrt == AIB_RX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_up_prgmnvrt == AIB_RX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_updnen == AIB_RX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dftmuxsel == AIB_RX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dly_pst == AIB_RX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_en == AIB_RX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_lockreq_muxsel == AIB_RX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll == AIB_RX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll2 == AIB_RX_DCC_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_rst == AIB_RX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_test_clk_pll_en_n == AIB_RX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_halfcode == AIB_RX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_selflock == AIB_RX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.op_mode == RX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_dc == RXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dcc_dll_dft_sel == AIB_DLLSTR_ALIGN_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dft_ch_muxsel == AIB_DLLSTR_ALIGN_DFT_CH_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_pi_slw == AIB_DLLSTR_ALIGN_PI_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll == AIB_DLLSTR_ALIGN_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll2 == AIB_DLLSTR_ALIGN_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_pinp_shiften == AIB_RED_PINP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.op_mode == TX_DLL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_dc == TXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_5.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.aib_hssi_rx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.aib_hssi_rx_transfer_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.aib_hssi_tx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.aib_hssi_tx_sr_clk_out_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.aib_hssi_tx_transfer_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.aib_rx_user_clk_hz == 32'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.aib_tx_user_clk_hz == 32'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.bti_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.direct_sel0 == DIRECT_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.e200g_aib1_tx_st_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.e200g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.e200g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.e200g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.e200g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.e200g_rx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.e200g_tx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.e400g_aib1_tx_st_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.e400g_aib2_rx_st_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.e400g_aib2_tx_st_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.e400g_aib3_rx_st_clk_hz == 32'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.e400g_aib3_tx_st_clk_hz == 32'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.e400g_rx_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.e400g_tx_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.global_avmm_clk_hz == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.internal_clk1_source == INTERNAL_CLK1_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.internal_clk2_source == INTERNAL_CLK2_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.pcie_pld_2x_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.pcie_pld_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.pcie_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.pcie_tx_transfer_div2_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.pld_pcs_rx_clk_out_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.pld_pcs_tx_clk_out_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.pma_aib_tx_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.powermode_ac_avmm1 == AC_AVMM1_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.powermode_ac_avmm2 == AC_AVMM2_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.powermode_ac_global_avmm == GLOBAL_AVMM_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.powermode_ac_rx_datapath == AC_RX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.powermode_ac_sr == AC_SR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.powermode_ac_tx_datapath == AC_TX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.powermode_dc == POWERUP_DC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.powermode_freq_hz_aib_rx_sr_clk_in == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.powermode_freq_hz_aib_rx_transfer_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.powermode_freq_hz_aib_tx_transfer_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.powermode_freq_hz_global_avmm_clk == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.sr_prot_mode == SR_PROT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.async_direct_sel0 == DIRECT_SEL0_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.async_direct_sel1 == DIRECT_SEL1_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.async_direct_sel2 == DIRECT_SEL2_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.async_direct_sel3 == DIRECT_SEL3_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.avmm1_free_run_div_clk == AVMM1_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.avmm1_write_resp_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.avmm2_free_run_div_clk == AVMM2_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.avmm2_global_usr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.dfd_cntr_inc_value == 9'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.dfd_cntr_rst_b == CNTR_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_ch_sel == GP0_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_cntr_data_sel == GP0_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_rsvd == GP0_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_testbus_sel == GP0_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_ch_sel == GP1_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_cntr_data_sel == GP1_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_rsvd == GP1_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_testbus_sel == GP1_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.dfd_mux_rst_b == MUX_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.hwcfg_adpt_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.hwcfg_aib_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.hwcfg_mode == BLOCK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.sr_prot_map_mode == MAP_SR_PROT_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.sr_test_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.sr_xcvr_map_mode == MAP_SR_XCVR_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.adapter_lpbk_mode == LOOPBACK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.aib_lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.async_direct_hip_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.datapath_mapping_mode == MAP_RX_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_sel == FIFO_RD_E400G_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_sel == FIFO_WR_PCIE_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.hrdrst_rst_sm_dis == ENABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel == FEEDTHRU_CLK1_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel0 == TXFIFOWR_FROM_AIB_MUX_CLK1_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel1 == FEEDTHRU_CLKS_OR_TXFIFORD_PRE_OR_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel2 == PMA_CLKS_OR_TXFIFORD_PRE_CT_MUX_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel3 == PMA_CLKS_CLK1_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel == FEEDTHRU_CLK0_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel0 == RXFIFORD_TO_AIB_MUX_CLK2_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_PRE_OR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel2 == PMA_CLKS_OR_RXFIFOWR_PRE_CT_MUX_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel3 == PMA_CLKS_CLK2_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.msb_pipeline_byp == MSB_PIPE_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.pld_pcs_rx_clk_out_sel == PLD_PCS_RX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.pma_aib_rx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.pma_coreclkin_sel == PMA_CORECLKIN_PLD_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.rx_10g_krfec_rx_diag_data_status_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.rx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.rx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.rx_parity_sel == FUNC_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.rx_pcs_testbus_sel == DIRECT_TR_TB_BIT0_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.rx_pcspma_testbus_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_a1a2_k1k2_flag_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_wa_boundary_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_pcie_sw_done_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_reser_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_testbus_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.rx_pld_test_data_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_num_stages == RMFFLAG_TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.rx_user_clk_rst_sel == RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.rx_user_clk_sel == RX_USER_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.rx_usertest_sel == DIRECT_TR_USERTEST3_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.rxfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.rxfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.rxfifo_mode == RXBYPASS_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.rxfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.rxfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.rxfiford_post_ct_sel == RXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.rxfiford_to_aib_sel == RXFIFORD_SCLK_TO_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.rxfifowr_post_ct_sel == RXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.rxfifowr_pre_ct_sel == RXFIFOWR_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.txfiford_post_ct_sel == TXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.txfiford_pre_ct_sel == TXFIFORD_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.txfifowr_from_aib_sel == TXFIFOWR_SCLK_FROM_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.txfifowr_post_ct_sel == TXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_rxchnl.word_mark == WM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_sr.sr_free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_sr.sr_osc_clk_div_sel == NON_DIV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.datapath_mapping_mode == MAP_TX_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.dv_gating == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.fifo_double_read == FIFO_DOUBLE_READ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_sel == FIFO_RD_PCIE_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.hrdrst_rst_sm_dis == ENABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.pld_pcs_tx_clk_out_sel == PLD_PCS_TX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.pma_aib_tx_clk_sel == PMA_AIB_TX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.tx_datapath_tb_sel == WA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.tx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.tx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.tx_latency_src_xcvrif == LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.tx_rev_lpbk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e200g_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e400g_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.tx_transfer_div2_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.tx_user_clk_rst_sel == TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.tx_user_clk_sel == TX_USER_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.tx_usertest_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.txfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.txfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.gdr_aibadapter.adapt_txchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_dc == AVMM1_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_dc == AVMM2_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr1 == AIB_DDR1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_clkdiv == AIB_RX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp == AIB_RX_DCC_BYP_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp_iocsr_unused == AIB_RX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal == AIB_RX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal_iocsr_unused == AIB_RX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft == AIB_RX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft_sel == AIB_RX_DCC_DFT_MODE1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dll_entest == AIB_RX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctl_static == AIB_RX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctlsel == AIB_RX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en == AIB_RX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en_iocsr_unused == AIB_RX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_dn == AIB_RX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_up == AIB_RX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_pi_slw == AIB_RX_DCC_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_rst_prgmnvrt == AIB_RX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_dn_prgmnvrt == AIB_RX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_up_prgmnvrt == AIB_RX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_updnen == AIB_RX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dftmuxsel == AIB_RX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dly_pst == AIB_RX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_en == AIB_RX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_lockreq_muxsel == AIB_RX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll == AIB_RX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll2 == AIB_RX_DCC_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_rst == AIB_RX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_test_clk_pll_en_n == AIB_RX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_halfcode == AIB_RX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_selflock == AIB_RX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.op_mode == RX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_HIGH_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_dc == RXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dcc_dll_dft_sel == AIB_DLLSTR_ALIGN_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dft_ch_muxsel == AIB_DLLSTR_ALIGN_DFT_CH_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_pi_slw == AIB_DLLSTR_ALIGN_PI_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll == AIB_DLLSTR_ALIGN_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll2 == AIB_DLLSTR_ALIGN_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_pinp_shiften == AIB_RED_PINP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.op_mode == TX_DLL_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_HIGH_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_dc == TXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_6.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.aib_hssi_rx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.aib_hssi_rx_transfer_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.aib_hssi_tx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.aib_hssi_tx_sr_clk_out_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.aib_hssi_tx_transfer_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.aib_rx_user_clk_hz == 32'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.aib_tx_user_clk_hz == 32'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.bti_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.direct_sel0 == DIRECT_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.e200g_aib1_tx_st_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.e200g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.e200g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.e200g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.e200g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.e200g_rx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.e200g_tx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.e400g_aib1_tx_st_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.e400g_aib2_rx_st_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.e400g_aib2_tx_st_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.e400g_aib3_rx_st_clk_hz == 32'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.e400g_aib3_tx_st_clk_hz == 32'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.e400g_rx_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.e400g_tx_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.global_avmm_clk_hz == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.internal_clk1_source == INTERNAL_CLK1_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.internal_clk2_source == INTERNAL_CLK2_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.pcie_pld_2x_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.pcie_pld_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.pcie_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.pcie_tx_transfer_div2_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.pld_pcs_rx_clk_out_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.pld_pcs_tx_clk_out_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.pma_aib_tx_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.powermode_ac_avmm1 == AC_AVMM1_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.powermode_ac_avmm2 == AC_AVMM2_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.powermode_ac_global_avmm == GLOBAL_AVMM_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.powermode_ac_rx_datapath == AC_RX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.powermode_ac_sr == AC_SR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.powermode_ac_tx_datapath == AC_TX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.powermode_dc == POWERUP_DC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.powermode_freq_hz_aib_rx_sr_clk_in == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.powermode_freq_hz_aib_rx_transfer_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.powermode_freq_hz_aib_tx_transfer_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.powermode_freq_hz_global_avmm_clk == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.sr_prot_mode == SR_PROT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.async_direct_sel0 == DIRECT_SEL0_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.async_direct_sel1 == DIRECT_SEL1_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.async_direct_sel2 == DIRECT_SEL2_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.async_direct_sel3 == DIRECT_SEL3_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.avmm1_free_run_div_clk == AVMM1_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.avmm1_write_resp_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.avmm2_free_run_div_clk == AVMM2_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.avmm2_global_usr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.dfd_cntr_inc_value == 9'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.dfd_cntr_rst_b == CNTR_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_ch_sel == GP0_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_cntr_data_sel == GP0_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_rsvd == GP0_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_testbus_sel == GP0_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_ch_sel == GP1_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_cntr_data_sel == GP1_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_rsvd == GP1_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_testbus_sel == GP1_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.dfd_mux_rst_b == MUX_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.hwcfg_adpt_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.hwcfg_aib_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.hwcfg_mode == BLOCK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.sr_prot_map_mode == MAP_SR_PROT_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.sr_test_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.sr_xcvr_map_mode == MAP_SR_XCVR_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.adapter_lpbk_mode == LOOPBACK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.aib_lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.async_direct_hip_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.datapath_mapping_mode == MAP_RX_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_sel == FIFO_RD_E400G_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_sel == FIFO_WR_PCIE_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.hrdrst_rst_sm_dis == ENABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel == FEEDTHRU_CLK1_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel0 == TXFIFOWR_FROM_AIB_MUX_CLK1_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel1 == FEEDTHRU_CLKS_OR_TXFIFORD_PRE_OR_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel2 == PMA_CLKS_OR_TXFIFORD_PRE_CT_MUX_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel3 == PMA_CLKS_CLK1_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel == FEEDTHRU_CLK0_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel0 == RXFIFORD_TO_AIB_MUX_CLK2_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_PRE_OR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel2 == PMA_CLKS_OR_RXFIFOWR_PRE_CT_MUX_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel3 == PMA_CLKS_CLK2_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.msb_pipeline_byp == MSB_PIPE_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.pld_pcs_rx_clk_out_sel == PLD_PCS_RX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.pma_aib_rx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.pma_coreclkin_sel == PMA_CORECLKIN_PLD_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.rx_10g_krfec_rx_diag_data_status_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.rx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.rx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.rx_parity_sel == FUNC_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.rx_pcs_testbus_sel == DIRECT_TR_TB_BIT0_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.rx_pcspma_testbus_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_a1a2_k1k2_flag_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_wa_boundary_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_pcie_sw_done_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_reser_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_testbus_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.rx_pld_test_data_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_num_stages == RMFFLAG_TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.rx_user_clk_rst_sel == RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.rx_user_clk_sel == RX_USER_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.rx_usertest_sel == DIRECT_TR_USERTEST3_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.rxfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.rxfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.rxfifo_mode == RXBYPASS_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.rxfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.rxfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.rxfiford_post_ct_sel == RXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.rxfiford_to_aib_sel == RXFIFORD_SCLK_TO_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.rxfifowr_post_ct_sel == RXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.rxfifowr_pre_ct_sel == RXFIFOWR_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.txfiford_post_ct_sel == TXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.txfiford_pre_ct_sel == TXFIFORD_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.txfifowr_from_aib_sel == TXFIFOWR_SCLK_FROM_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.txfifowr_post_ct_sel == TXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_rxchnl.word_mark == WM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_sr.sr_free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_sr.sr_osc_clk_div_sel == NON_DIV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.datapath_mapping_mode == MAP_TX_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.dv_gating == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.fifo_double_read == FIFO_DOUBLE_READ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_sel == FIFO_RD_PCIE_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.hrdrst_rst_sm_dis == ENABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.pld_pcs_tx_clk_out_sel == PLD_PCS_TX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.pma_aib_tx_clk_sel == PMA_AIB_TX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.tx_datapath_tb_sel == WA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.tx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.tx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.tx_latency_src_xcvrif == LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.tx_rev_lpbk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e200g_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e400g_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.tx_transfer_div2_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.tx_user_clk_rst_sel == TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.tx_user_clk_sel == TX_USER_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.tx_usertest_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.txfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.txfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.gdr_aibadapter.adapt_txchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_dc == AVMM1_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_dc == AVMM2_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr1 == AIB_DDR1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_clkdiv == AIB_RX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp == AIB_RX_DCC_BYP_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp_iocsr_unused == AIB_RX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal == AIB_RX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal_iocsr_unused == AIB_RX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft == AIB_RX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft_sel == AIB_RX_DCC_DFT_MODE1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dll_entest == AIB_RX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctl_static == AIB_RX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctlsel == AIB_RX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en == AIB_RX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en_iocsr_unused == AIB_RX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_dn == AIB_RX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_up == AIB_RX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_pi_slw == AIB_RX_DCC_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_rst_prgmnvrt == AIB_RX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_dn_prgmnvrt == AIB_RX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_up_prgmnvrt == AIB_RX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_updnen == AIB_RX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dftmuxsel == AIB_RX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dly_pst == AIB_RX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_en == AIB_RX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_lockreq_muxsel == AIB_RX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll == AIB_RX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll2 == AIB_RX_DCC_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_rst == AIB_RX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_test_clk_pll_en_n == AIB_RX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_halfcode == AIB_RX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_selflock == AIB_RX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.op_mode == RX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_HIGH_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_dc == RXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dcc_dll_dft_sel == AIB_DLLSTR_ALIGN_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dft_ch_muxsel == AIB_DLLSTR_ALIGN_DFT_CH_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_pi_slw == AIB_DLLSTR_ALIGN_PI_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll == AIB_DLLSTR_ALIGN_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll2 == AIB_DLLSTR_ALIGN_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_pinp_shiften == AIB_RED_PINP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.op_mode == TX_DLL_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_HIGH_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_dc == TXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_7.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.aib_hssi_rx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.aib_hssi_rx_transfer_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.aib_hssi_tx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.aib_hssi_tx_sr_clk_out_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.aib_hssi_tx_transfer_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.aib_rx_user_clk_hz == 32'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.aib_tx_user_clk_hz == 32'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.bti_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.direct_sel0 == DIRECT_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.e200g_aib1_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.e200g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.e200g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.e200g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.e200g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.e200g_rx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.e200g_tx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.e400g_aib1_tx_st_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.e400g_aib2_rx_st_clk_hz == 32'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.e400g_aib2_tx_st_clk_hz == 32'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.e400g_aib3_rx_st_clk_hz == 32'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.e400g_aib3_tx_st_clk_hz == 32'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.e400g_rx_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.e400g_tx_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.global_avmm_clk_hz == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.internal_clk1_source == INTERNAL_CLK1_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.internal_clk2_source == INTERNAL_CLK2_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.pcie_pld_2x_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.pcie_pld_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.pcie_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.pcie_tx_transfer_div2_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.pld_pcs_rx_clk_out_hz == 32'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.pld_pcs_tx_clk_out_hz == 32'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.pma_aib_tx_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.powermode_ac_avmm1 == AC_AVMM1_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.powermode_ac_avmm2 == AC_AVMM2_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.powermode_ac_global_avmm == GLOBAL_AVMM_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.powermode_ac_rx_datapath == AC_RX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.powermode_ac_sr == AC_SR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.powermode_ac_tx_datapath == AC_TX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.powermode_dc == POWERUP_DC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.powermode_freq_hz_aib_rx_sr_clk_in == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.powermode_freq_hz_aib_rx_transfer_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.powermode_freq_hz_aib_tx_transfer_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.powermode_freq_hz_global_avmm_clk == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.sr_prot_mode == SR_PROT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.async_direct_sel0 == DIRECT_SEL0_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.async_direct_sel1 == DIRECT_SEL1_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.async_direct_sel2 == DIRECT_SEL2_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.async_direct_sel3 == DIRECT_SEL3_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.avmm1_free_run_div_clk == AVMM1_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.avmm1_write_resp_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.avmm2_free_run_div_clk == AVMM2_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.avmm2_global_usr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.dfd_cntr_inc_value == 9'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.dfd_cntr_rst_b == CNTR_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_ch_sel == GP0_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_cntr_data_sel == GP0_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_rsvd == GP0_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_testbus_sel == GP0_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_ch_sel == GP1_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_cntr_data_sel == GP1_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_rsvd == GP1_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_testbus_sel == GP1_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.dfd_mux_rst_b == MUX_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.hwcfg_adpt_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.hwcfg_aib_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.hwcfg_mode == BLOCK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.sr_prot_map_mode == MAP_SR_PROT_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.sr_test_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.sr_xcvr_map_mode == MAP_SR_XCVR_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.adapter_lpbk_mode == LOOPBACK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.aib_lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.async_direct_hip_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.datapath_mapping_mode == MAP_RX_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_sel == FIFO_RD_E400G_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_sel == FIFO_WR_PCIE_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.hrdrst_rst_sm_dis == ENABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel == FEEDTHRU_CLK1_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel0 == TXFIFOWR_FROM_AIB_MUX_CLK1_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel1 == FEEDTHRU_CLKS_OR_TXFIFORD_PRE_OR_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel2 == PMA_CLKS_OR_TXFIFORD_PRE_CT_MUX_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel3 == PMA_CLKS_CLK1_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel == FEEDTHRU_CLK0_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel0 == RXFIFORD_TO_AIB_MUX_CLK2_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_PRE_OR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel2 == PMA_CLKS_OR_RXFIFOWR_PRE_CT_MUX_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel3 == PMA_CLKS_CLK2_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.msb_pipeline_byp == MSB_PIPE_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.pld_pcs_rx_clk_out_sel == PLD_PCS_RX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.pma_aib_rx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.pma_coreclkin_sel == PMA_CORECLKIN_PLD_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.rx_10g_krfec_rx_diag_data_status_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.rx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.rx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.rx_parity_sel == FUNC_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.rx_pcs_testbus_sel == DIRECT_TR_TB_BIT0_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.rx_pcspma_testbus_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_a1a2_k1k2_flag_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_wa_boundary_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_pcie_sw_done_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_reser_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_testbus_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.rx_pld_test_data_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_num_stages == RMFFLAG_TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.rx_user_clk_rst_sel == RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.rx_user_clk_sel == RX_USER_CLK_E400G_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.rx_usertest_sel == DIRECT_TR_USERTEST3_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.rxfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.rxfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.rxfifo_mode == RXBYPASS_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.rxfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.rxfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.rxfiford_post_ct_sel == RXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.rxfiford_to_aib_sel == RXFIFORD_SCLK_TO_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.rxfifowr_post_ct_sel == RXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.rxfifowr_pre_ct_sel == RXFIFOWR_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.txfiford_post_ct_sel == TXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.txfiford_pre_ct_sel == TXFIFORD_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.txfifowr_from_aib_sel == TXFIFOWR_SCLK_FROM_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.txfifowr_post_ct_sel == TXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_rxchnl.word_mark == WM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_sr.sr_free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_sr.sr_osc_clk_div_sel == NON_DIV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.datapath_mapping_mode == MAP_TX_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.dv_gating == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.fifo_double_read == FIFO_DOUBLE_READ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_sel == FIFO_RD_PCIE_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.hrdrst_rst_sm_dis == ENABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.pld_pcs_tx_clk_out_sel == PLD_PCS_TX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.pma_aib_tx_clk_sel == PMA_AIB_TX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.tx_datapath_tb_sel == WA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.tx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.tx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.tx_latency_src_xcvrif == LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.tx_rev_lpbk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e200g_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e400g_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.tx_transfer_div2_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.tx_user_clk_rst_sel == TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.tx_user_clk_sel == TX_USER_CLK_E400G_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.tx_usertest_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.txfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.txfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.gdr_aibadapter.adapt_txchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_dc == AVMM1_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_dc == AVMM2_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr1 == AIB_DDR1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_clkdiv == AIB_RX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp == AIB_RX_DCC_BYP_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp_iocsr_unused == AIB_RX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal == AIB_RX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal_iocsr_unused == AIB_RX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft == AIB_RX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft_sel == AIB_RX_DCC_DFT_MODE1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dll_entest == AIB_RX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctl_static == AIB_RX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctlsel == AIB_RX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en == AIB_RX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en_iocsr_unused == AIB_RX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_dn == AIB_RX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_up == AIB_RX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_pi_slw == AIB_RX_DCC_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_rst_prgmnvrt == AIB_RX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_dn_prgmnvrt == AIB_RX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_up_prgmnvrt == AIB_RX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_updnen == AIB_RX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dftmuxsel == AIB_RX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dly_pst == AIB_RX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_en == AIB_RX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_lockreq_muxsel == AIB_RX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll == AIB_RX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll2 == AIB_RX_DCC_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_rst == AIB_RX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_test_clk_pll_en_n == AIB_RX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_halfcode == AIB_RX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_selflock == AIB_RX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.op_mode == RX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_HIGH_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_dc == RXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dcc_dll_dft_sel == AIB_DLLSTR_ALIGN_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dft_ch_muxsel == AIB_DLLSTR_ALIGN_DFT_CH_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_pi_slw == AIB_DLLSTR_ALIGN_PI_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll == AIB_DLLSTR_ALIGN_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll2 == AIB_DLLSTR_ALIGN_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_pinp_shiften == AIB_RED_PINP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.op_mode == TX_DLL_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_HIGH_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_dc == TXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_8.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.aib_hssi_rx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.aib_hssi_rx_transfer_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.aib_hssi_tx_sr_clk_in_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.aib_hssi_tx_sr_clk_out_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.aib_hssi_tx_transfer_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.bti_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.direct_sel0 == DIRECT_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.e200g_aib1_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.e200g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.e200g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.e200g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.e200g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.e200g_rx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.e200g_tx_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.e400g_aib1_tx_st_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.e400g_aib2_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.e400g_aib2_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.e400g_aib3_rx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.e400g_aib3_tx_st_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.e400g_rx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.e400g_tx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.global_avmm_clk_hz == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.internal_clk1_source == INTERNAL_CLK1_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.internal_clk2_source == INTERNAL_CLK2_DL_RETURN_PATH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.pcie_pld_2x_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.pcie_pld_clk_hz == 32'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.pcie_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.pcie_tx_transfer_div2_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.pld_pcs_rx_clk_out_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.pld_pcs_tx_clk_out_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.pma_aib_tx_clk_hz == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.powermode_ac_avmm1 == AC_AVMM1_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.powermode_ac_avmm2 == AC_AVMM2_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.powermode_ac_global_avmm == GLOBAL_AVMM_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.powermode_ac_rx_datapath == AC_RX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.powermode_ac_sr == AC_SR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.powermode_ac_tx_datapath == AC_TX_DATAPATH_FIFO_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.powermode_dc == POWERUP_DC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.powermode_freq_hz_aib_rx_sr_clk_in == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.powermode_freq_hz_aib_rx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.powermode_freq_hz_aib_tx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.powermode_freq_hz_global_avmm_clk == 32'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.sr_prot_mode == SR_PROT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.async_direct_sel0 == DIRECT_SEL0_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.async_direct_sel1 == DIRECT_SEL1_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.async_direct_sel2 == DIRECT_SEL2_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.async_direct_sel3 == DIRECT_SEL3_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.avmm1_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.avmm1_free_run_div_clk == AVMM1_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.avmm1_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_read == AVMM1_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.avmm1_rdfifo_stop_write == AVMM1_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.avmm1_write_resp_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_dcg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.avmm2_avmm_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.avmm2_free_run_div_clk == AVMM2_OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.avmm2_global_usr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.avmm2_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_empty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_full == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_read == AVMM2_RDFIFO_N_RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.avmm2_rdfifo_stop_write == AVMM2_RDFIFO_N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.avmm_hrdrst_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.avmm_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.avmm_testbus_sel == AVMM1_TRANSFER_TESTBUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.dfd_cntr_inc_value == 9'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.dfd_cntr_rst_b == CNTR_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_ch_sel == GP0_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_cntr_data_sel == GP0_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_rsvd == GP0_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.dfd_mux_gp0_testbus_sel == GP0_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_ch_sel == GP1_CH_SEL_PREV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_cntr_data_sel == GP1_SEL_DATA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_rsvd == GP1_RSVD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.dfd_mux_gp1_testbus_sel == GP1_TX_FIFO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.dfd_mux_rst_b == MUX_RESET_ASSERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.hwcfg_adpt_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.hwcfg_aib_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.hwcfg_mode == BLOCK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.sr_prot_map_mode == MAP_SR_PROT_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.sr_test_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.sr_xcvr_map_mode == MAP_SR_XCVR_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_avmm.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.adapter_lpbk_mode == LOOPBACK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.aib_lpbk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.async_direct_hip_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.clock_del_measure_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.datapath_mapping_mode == MAP_RX_E400G_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.fifo_double_write == FIFO_DOUBLE_WRITE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.fifo_rd_clk_sel == FIFO_RD_BTI_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.fifo_wr_clk_sel == FIFO_WR_PCIE_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.fsr_pld_10g_rx_crc32_err_rst_val == RESET_TO_ZERO_CRC32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.fsr_pld_8g_sigdet_out_rst_val == RESET_TO_ZERO_SIGDET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltd_b_rst_val == RESET_TO_ONE_LTDB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.fsr_pld_ltr_rst_val == RESET_TO_ZERO_LTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.fsr_pld_rx_fifo_align_clr_rst_val == RESET_TO_ZERO_ALIGNCLR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.hrdrst_rst_sm_dis == DISABLE_RX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel == FEEDTHRU_CLK1_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel0 == TXFIFOWR_FROM_AIB_MUX_CLK1_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel1 == FEEDTHRU_CLKS_OR_TXFIFORD_PRE_OR_POST_CT_MUX_CLK1_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel2 == PMA_CLKS_OR_TXFIFORD_PRE_CT_MUX_CLK1_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.internal_clk1_sel3 == PMA_CLKS_CLK1_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel == FEEDTHRU_CLK0_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel0 == RXFIFORD_TO_AIB_MUX_CLK2_MUX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel1 == PMA_CLKS_OR_RXFIFOWR_PRE_OR_POST_CT_MUX_CLK2_MUX1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel2 == PMA_CLKS_OR_RXFIFOWR_PRE_CT_MUX_CLK2_MUX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.internal_clk2_sel3 == PMA_CLKS_CLK2_MUX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.msb_pipeline_byp == MSB_PIPE_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.pld_pcs_rx_clk_out_sel == PLD_PCS_RX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.pma_aib_rx_clk_expected_setting == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.pma_coreclkin_sel == PMA_CORECLKIN_PLD_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.rx_10g_krfec_rx_diag_data_status_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.rx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.rx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.rx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.rx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.rx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.rx_parity_sel == FUNC_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.rx_pcs_testbus_sel == DIRECT_TR_TB_BIT0_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.rx_pcspma_testbus_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_a1a2_k1k2_flag_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.rx_pld_8g_wa_boundary_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_pcie_sw_done_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_reser_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.rx_pld_pma_testbus_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.rx_pld_test_data_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.rx_rmfflag_stretch_num_stages == RMFFLAG_TWO_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.rx_user_clk_rst_sel == RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.rx_user_clk_sel == RX_USER_CLK_E400G_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.rx_usertest_sel == DIRECT_TR_USERTEST3_SEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.rxfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.rxfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.rxfifo_mode == RXBYPASS_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.rxfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.rxfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.rxfiford_post_ct_sel == RXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.rxfiford_to_aib_sel == RXFIFORD_SCLK_TO_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.rxfifowr_post_ct_sel == RXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.rxfifowr_pre_ct_sel == RXFIFOWR_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.txfiford_post_ct_sel == TXFIFORD_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.txfiford_pre_ct_sel == TXFIFORD_PRE_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.txfifowr_from_aib_sel == TXFIFOWR_SCLK_FROM_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.txfifowr_post_ct_sel == TXFIFOWR_POST_CT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_rxchnl.word_mark == WM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_sr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_sr.sr_free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_sr.sr_hip_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_sr.sr_osc_clk_div_sel == NON_DIV
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_sr.sr_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_sr.sr_parity_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_sr.sr_reserved_in_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_sr.sr_reserved_out_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_sr.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.datapath_mapping_mode == MAP_TX_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.dv_gating == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.fifo_double_read == FIFO_DOUBLE_READ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.fifo_mode == BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.fifo_rd_clk_sel == FIFO_RD_PCIE_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.free_run_div_clk == OUT_OF_RESET_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit0_rst_val == RESET_TO_ONE_HFSRIN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit1_rst_val == RESET_TO_ONE_HFSRIN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit2_rst_val == RESET_TO_ONE_HFSRIN2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_in_bit3_rst_val == RESET_TO_ZERO_HFSRIN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit0_rst_val == RESET_TO_ONE_HFSROUT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit1_rst_val == RESET_TO_ONE_HFSROUT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit2_rst_val == RESET_TO_ZERO_HFSROUT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.fsr_hip_fsr_out_bit3_rst_val == RESET_TO_ZERO_HFSROUT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.fsr_mask_tx_pll_rst_val == RESET_TO_ZERO_MASKPLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.fsr_pld_txelecidle_rst_val == RESET_TO_ZERO_TXELEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.func_mode == GDRADPT_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.hip_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.hrdrst_align_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.hrdrst_dcd_cal_done_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.hrdrst_dll_lock_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.hrdrst_rst_sm_dis == DISABLE_TX_RST_SM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.hrdrst_rx_osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.hrdrst_user_ctl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.loopback_mode == LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.osc_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.phcomp_rd_del == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.pld_pcs_tx_clk_out_sel == PLD_PCS_TX_CLK_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.pma_aib_tx_clk_sel == PMA_AIB_TX_CLK_BTI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.stretch_num_stages == SEVEN_STAGE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.tx_datapath_tb_sel == WA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.tx_fifo_power_mode == HALF_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.tx_fifo_read_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.tx_fifo_write_latency_adjust == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.tx_latency_pls_sel == LATENCY_PLS_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.tx_latency_src_xcvrif == LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.tx_osc_clock_setting == OSC_CLK_DIV_BY1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.tx_rev_lpbk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e200g_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_e400g_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.tx_transfer_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.tx_transfer_div2_clk_pcie_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.tx_user_clk_rst_sel == TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.tx_user_clk_sel == TX_USER_CLK_E400G_DIV4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.tx_usertest_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.txfifo_full == FULL_DW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.txfifo_pfull == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.gdr_aibadapter.adapt_txchnl.word_align_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr0 == AIB_INCTRL0_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_inctrl_gr2 == AIB_INCTRL2_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.aib_red_avm1_shiften == AIB_RED_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.op_mode == AVMM1_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_ac == AVMM1_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_dc == AVMM1_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.powermode_freq_hz_aib_hssi_avmm1_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_datasel == AIB_DATASEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_inctrl == AIB_INCTRL_SETTING4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outctrl == AIB_OUTEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.op_mode == AVMM2_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_ac == AVMM2_OSC_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_dc == AVMM2_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.powermode_freq_hz_aib_hssi_avmm2_clk == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xavmm2.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr1 == AIB_DATASEL1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_datasel_gr2 == AIB_DATASEL2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr0 == AIB_DDR0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_ddrctrl_gr1 == AIB_DDR1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinasyncen == AIB_INASYNCEN_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_iinclken == AIB_INCLKEN_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outctrl_gr3 == AIB_OUTEN3_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_clkdiv == AIB_RX_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp == AIB_RX_DCC_BYP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_byp_iocsr_unused == AIB_RX_DCC_BYP_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal == AIB_RX_DCC_CAL_CONT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_cont_cal_iocsr_unused == AIB_RX_DCC_CAL_SINGLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft == AIB_RX_DCC_DFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dft_sel == AIB_RX_DCC_DFT_MODE1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dll_entest == AIB_RX_DCC_DLL_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctl_static == AIB_RX_DCC_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_dy_ctlsel == AIB_RX_DCC_DY_CTLSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en == AIB_RX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_en_iocsr_unused == AIB_RX_DCC_DISABLE_IOCSR_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_dn == AIB_RX_DCC_MANUAL_DN0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_manual_up == AIB_RX_DCC_MANUAL_UP0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_pi_slw == AIB_RX_DCC_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_rst_prgmnvrt == AIB_RX_DCC_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_dn_prgmnvrt == AIB_RX_DCC_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_up_prgmnvrt == AIB_RX_DCC_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_core_updnen == AIB_RX_DCC_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dftmuxsel == AIB_RX_DCC_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_dly_pst == AIB_RX_DCC_ST_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_en == AIB_RX_DCC_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_lockreq_muxsel == AIB_RX_DCC_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll == AIB_RX_DCC_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_new_dll2 == AIB_RX_DCC_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_st_rst == AIB_RX_DCC_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_dcc_test_clk_pll_en_n == AIB_RX_DCC_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_halfcode == AIB_RX_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.aib_rx_selflock == AIB_RX_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.op_mode == RX_DCC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_ac == RXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_dc == RXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.powermode_freq_hz_aib_hssi_rx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xrxdatapath_rx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr0 == AIB_DATASEL0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr1 == AIB_DATASEL1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_datasel_gr2 == AIB_DATASEL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_clkdiv == AIB_DLLSTR_ALIGN_CLKDIV_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dcc_dll_dft_sel == AIB_DLLSTR_ALIGN_DCC_DLL_DFT_SEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dft_ch_muxsel == AIB_DLLSTR_ALIGN_DFT_CH_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dly_pst == AIB_DLLSTR_ALIGN_DLY_PST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctl_static == AIB_DLLSTR_ALIGN_DY_CTL_STATIC_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_dy_ctlsel == AIB_DLLSTR_ALIGN_DY_CTLSEL_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_entest == AIB_DLLSTR_ALIGN_TEST_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_halfcode == AIB_DLLSTR_ALIGN_HALFCODE_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_pi_slw == AIB_DLLSTR_ALIGN_PI_SLW_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_selflock == AIB_DLLSTR_ALIGN_SELFLOCK_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_dn_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_DN_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_up_prgmnvrt == AIB_DLLSTR_ALIGN_ST_CORE_UP_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_core_updnen == AIB_DLLSTR_ALIGN_ST_CORE_UPDNEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_dftmuxsel == AIB_DLLSTR_ALIGN_ST_DFTMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_en == AIB_DLLSTR_ALIGN_ST_EN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_lockreq_muxsel == AIB_DLLSTR_ALIGN_ST_LOCKREQ_MUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll == AIB_DLLSTR_ALIGN_NEW_DLL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_new_dll2 == AIB_DLLSTR_ALIGN_NEW_DLL2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst == AIB_DLLSTR_ALIGN_ST_RST_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_st_rst_prgmnvrt == AIB_DLLSTR_ALIGN_ST_RST_PRGMNVRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_dllstr_align_test_clk_pll_en_n == AIB_DLLSTR_ALIGN_TEST_CLK_PLL_EN_N_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr0 == AIB_INCTRL0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr1 == AIB_INCTRL1_SETTING3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr2 == AIB_INCTRL2_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_inctrl_gr3 == AIB_INCTRL3_SETTING2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr0 == AIB_OUTEN0_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr1 == AIB_OUTEN1_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outctrl_gr2 == AIB_OUTEN2_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r12 == AIB_NDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r34 == AIB_NDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r56 == AIB_NDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outndrv_r78 == AIB_NDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r12 == AIB_PDRV12_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r34 == AIB_PDRV34_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r56 == AIB_PDRV56_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_outpdrv_r78 == AIB_PDRV78_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkn_shiften == AIB_RED_DIRCLKN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dirclkp_shiften == AIB_RED_DIRCLKP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_drx_shiften == AIB_RED_DRX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_dtx_shiften == AIB_RED_DTX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_pinp_shiften == AIB_RED_PINP_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_rx_shiften == AIB_RED_RX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_tx_shiften == AIB_RED_TX_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkout_shiften == AIB_RED_TXFERCLKOUT_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.aib_red_txferclkoutn_shiften == AIB_RED_TXFERCLKOUTN_SHIFT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dfd_dll_dcc_en == DISABLE_DFD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.dft_hssitestip_dll_dcc_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.op_mode == TX_DLL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_ac == TXDATAPATH_LOW_SPEED_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_dc == TXDATAPATH_POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.powermode_freq_hz_aib_hssi_tx_transfer_clk == 32'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_aibadapt_wrap_9.xgdr_aibchl_top_wrp.xgdr_aibchl_top.xtxdatapath_tx.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.barak_es_limit == BARAK_ES_LIMIT_R1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_an_mode == BK0_AN_MODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_bti_protected == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_ext_ac_cap == BK0_EXTERNAL_AC_CAP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_loopback_mode == BK0_LPBK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_pam4_rxgrey_code == BK0_PAM4_RXGREY_IS_B4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_rx_bond_size == BK0_RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_rx_bond_size_sd == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_rx_invert_p_and_n == BK0_RX_INVERT_PN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_rx_line_rate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_rx_line_rate_actual == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_rx_master_bond_chnl == BK0_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_rx_o_clk_e4_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_rx_o_usr_clk_1_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_rx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_rx_precode_en == BK0_RX_PRECODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_rx_protocol == BK0_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_rx_swizzle_mode == LANE0_RX_SWIZZLE_MODE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_rx_termination == BK0_RXTERM_OFFSET_P0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_rx_which_lane_to_copy == BK0_RX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_rx_width == BK0_RX_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_rx_width_sd == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_rxterm_sd == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_tx_bond_size == BK0_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_tx_bond_size_sd == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_tx_ffe_output_swizzle == BK0_TXFFE_OUTPUT_SWIZZLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_tx_i_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_tx_invert_p_and_n == BK0_TX_INVERT_PN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_tx_line_rate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_tx_line_rate_actual == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_tx_master_bond_chnl == BK0_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_tx_o_clk_e4_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_tx_o_usr_clk_1_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_tx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_tx_precode_en == BK0_TX_PRECODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_tx_protocol == BK0_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_tx_rdfifo_master_bond_chnl == BK0_TX_RDFIFO_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_tx_termination == BK0_TXTERM_OFFSET_P0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_tx_which_lane_to_copy == BK0_TX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_tx_width == BK0_TX_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_tx_width_sd == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_txeq_cmod == 9'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_txeq_main_tap == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_txeq_post_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_txeq_post_tap_2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_txeq_post_tap_3 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_txeq_post_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_txeq_pre_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_txeq_pre_tap_2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_txeq_pre_tap_3 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_txout_tristate_en == BK0_TXOUT_TRISTATE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_txrx_line_encoding_type == BK0_TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_txrx_xcvr_speed_bucket == BK0_TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk0_txterm_sd == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_an_mode == BK1_AN_MODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_bti_protected == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_ext_ac_cap == BK1_EXTERNAL_AC_CAP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_loopback_mode == BK1_LPBK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_pam4_rxgrey_code == BK1_PAM4_RXGREY_IS_B4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_rx_bond_size == BK1_RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_rx_bond_size_sd == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_rx_invert_p_and_n == BK1_RX_INVERT_PN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_rx_line_rate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_rx_line_rate_actual == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_rx_master_bond_chnl == BK1_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_rx_o_clk_e4_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_rx_o_usr_clk_1_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_rx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_rx_precode_en == BK1_RX_PRECODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_rx_protocol == BK1_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_rx_swizzle_mode == LANE1_RX_SWIZZLE_MODE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_rx_termination == BK1_RXTERM_OFFSET_P0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_rx_which_lane_to_copy == BK1_RX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_rx_width == BK1_RX_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_rx_width_sd == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_rxterm_sd == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_tx_bond_size == BK1_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_tx_bond_size_sd == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_tx_ffe_output_swizzle == BK1_TXFFE_OUTPUT_SWIZZLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_tx_i_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_tx_invert_p_and_n == BK1_TX_INVERT_PN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_tx_line_rate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_tx_line_rate_actual == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_tx_master_bond_chnl == BK1_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_tx_o_clk_e4_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_tx_o_usr_clk_1_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_tx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_tx_precode_en == BK1_TX_PRECODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_tx_protocol == BK1_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_tx_rdfifo_master_bond_chnl == BK1_TX_RDFIFO_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_tx_termination == BK1_TXTERM_OFFSET_P0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_tx_which_lane_to_copy == BK1_TX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_tx_width == BK1_TX_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_tx_width_sd == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_txeq_cmod == 9'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_txeq_main_tap == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_txeq_post_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_txeq_post_tap_2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_txeq_post_tap_3 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_txeq_post_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_txeq_pre_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_txeq_pre_tap_2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_txeq_pre_tap_3 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_txout_tristate_en == BK1_TXOUT_TRISTATE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_txrx_line_encoding_type == BK1_TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_txrx_xcvr_speed_bucket == BK1_TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk1_txterm_sd == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_an_mode == BK2_AN_MODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_bti_protected == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_ext_ac_cap == BK2_EXTERNAL_AC_CAP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_loopback_mode == BK2_LPBK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_pam4_rxgrey_code == BK2_PAM4_RXGREY_IS_B4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_rx_bond_size == BK2_RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_rx_bond_size_sd == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_rx_invert_p_and_n == BK2_RX_INVERT_PN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_rx_line_rate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_rx_line_rate_actual == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_rx_master_bond_chnl == BK2_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_rx_o_clk_e4_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_rx_o_usr_clk_1_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_rx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_rx_precode_en == BK2_RX_PRECODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_rx_protocol == BK2_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_rx_swizzle_mode == LANE2_RX_SWIZZLE_MODE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_rx_termination == BK2_RXTERM_OFFSET_P0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_rx_which_lane_to_copy == BK2_RX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_rx_width == BK2_RX_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_rx_width_sd == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_rxterm_sd == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_tx_bond_size == BK2_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_tx_bond_size_sd == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_tx_ffe_output_swizzle == BK2_TXFFE_OUTPUT_SWIZZLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_tx_i_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_tx_invert_p_and_n == BK2_TX_INVERT_PN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_tx_line_rate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_tx_line_rate_actual == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_tx_master_bond_chnl == BK2_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_tx_o_clk_e4_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_tx_o_usr_clk_1_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_tx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_tx_precode_en == BK2_TX_PRECODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_tx_protocol == BK2_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_tx_rdfifo_master_bond_chnl == BK2_TX_RDFIFO_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_tx_termination == BK2_TXTERM_OFFSET_P0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_tx_which_lane_to_copy == BK2_TX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_tx_width == BK2_TX_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_tx_width_sd == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_txeq_cmod == 9'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_txeq_main_tap == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_txeq_post_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_txeq_post_tap_2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_txeq_post_tap_3 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_txeq_post_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_txeq_pre_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_txeq_pre_tap_2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_txeq_pre_tap_3 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_txout_tristate_en == BK2_TXOUT_TRISTATE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_txrx_line_encoding_type == BK2_TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_txrx_xcvr_speed_bucket == BK2_TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk2_txterm_sd == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_an_mode == BK3_AN_MODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_bti_protected == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_ext_ac_cap == BK3_EXTERNAL_AC_CAP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_loopback_mode == BK3_LPBK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_pam4_rxgrey_code == BK3_PAM4_RXGREY_IS_B4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_rx_bond_size == BK3_RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_rx_bond_size_sd == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_rx_invert_p_and_n == BK3_RX_INVERT_PN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_rx_line_rate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_rx_line_rate_actual == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_rx_master_bond_chnl == BK3_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_rx_o_clk_e4_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_rx_o_usr_clk_1_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_rx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_rx_precode_en == BK3_RX_PRECODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_rx_protocol == BK3_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_rx_swizzle_mode == LANE3_RX_SWIZZLE_MODE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_rx_termination == BK3_RXTERM_OFFSET_P0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_rx_which_lane_to_copy == BK3_RX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_rx_width == BK3_RX_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_rx_width_sd == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_rxterm_sd == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_tx_bond_size == BK3_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_tx_bond_size_sd == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_tx_ffe_output_swizzle == BK3_TXFFE_OUTPUT_SWIZZLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_tx_i_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_tx_invert_p_and_n == BK3_TX_INVERT_PN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_tx_line_rate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_tx_line_rate_actual == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_tx_master_bond_chnl == BK3_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_tx_o_clk_e4_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_tx_o_usr_clk_1_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_tx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_tx_precode_en == BK3_TX_PRECODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_tx_protocol == BK3_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_tx_rdfifo_master_bond_chnl == BK3_TX_RDFIFO_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_tx_termination == BK3_TXTERM_OFFSET_P0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_tx_which_lane_to_copy == BK3_TX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_tx_width == BK3_TX_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_tx_width_sd == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_txeq_cmod == 9'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_txeq_main_tap == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_txeq_post_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_txeq_post_tap_2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_txeq_post_tap_3 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_txeq_post_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_txeq_pre_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_txeq_pre_tap_2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_txeq_pre_tap_3 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_txout_tristate_en == BK3_TXOUT_TRISTATE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_txrx_line_encoding_type == BK3_TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_txrx_xcvr_speed_bucket == BK3_TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk3_txterm_sd == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_2nd_cbpll_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_aonclk_mstclk_sel == SEL_REFCLKA_FOR_AON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_bitprog_gray == BK_BITPROG_NOGRAY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_bitprog_invert == BK_BITPROG_NOINVERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_bitprog_lane_mode == BK_BITPROG_LANE_MODE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_bitprog_lane_mode_sd == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_bitprog_lane_sel == BK_BITPROG_SEL_L0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_bitprog_lane_sel_sd == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_bitprog_opcode == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_bitprog_pllrate_sel == BK_BITPROG_PLLRATE_12G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_bitprog_pllrate_sel_sd == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_bitprog_prbssel_berthld_ppmsrc_pattype_netsel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_bitprog_reg == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_bitprog_swl == BK_BITPROG_SWL_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_bitprog_swl_sd == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_bitprog_tx_fail_thld == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_bitprog_tx_preset_sel == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_bitprog_tx_test_length == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_bitprog_update_cfg == BK_BITPROG_NOUPDATE_CFG
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_bticlk_rclk_ln0_feature_on == BK0_BTICLK_RCLK_FEATUR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_bticlk_rclk_ln0_force_on == BK0_BTICLK_RCLK_FRC_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_bticlk_rclk_ln1_feature_on == BK1_BTICLK_RCLK_FEATUR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_bticlk_rclk_ln1_force_on == BK1_BTICLK_RCLK_FRC_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_bticlk_rclk_ln2_feature_on == BK2_BTICLK_RCLK_FEATUR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_bticlk_rclk_ln2_force_on == BK2_BTICLK_RCLK_FRC_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_bticlk_rclk_ln3_feature_on == BK3_BTICLK_RCLK_FEATUR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_bticlk_rclk_ln3_force_on == BK3_BTICLK_RCLK_FRC_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_bticlk_tclk_ln0_feature_on == BK0_BTICLK_TCLK_FEATUR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_bticlk_tclk_ln0_force_on == BK0_BTICLK_TCLK_FRC_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_bticlk_tclk_ln1_feature_on == BK1_BTICLK_TCLK_FEATUR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_bticlk_tclk_ln1_force_on == BK1_BTICLK_TCLK_FRC_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_bticlk_tclk_ln2_feature_on == BK2_BTICLK_TCLK_FEATUR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_bticlk_tclk_ln2_force_on == BK2_BTICLK_TCLK_FRC_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_bticlk_tclk_ln3_feature_on == BK3_BTICLK_TCLK_FEATUR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_bticlk_tclk_ln3_force_on == BK3_BTICLK_TCLK_FRC_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_car_tx_clk_src_sel == BK_CAR_TX_CLK_SRC_SEL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_clk_en_plla_cmos_refclk_out == CLKEN_CMOS_PLLA_REFCLKO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_clk_en_pllb_cmos_refclk_out == CLKEN_CMOS_PLLB_REFCLKO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_f_max_pfd_pll_a_hz == 36'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_f_max_pfd_pll_b_hz == 36'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_f_max_ref_pll_a_hz == 36'd200000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_f_max_ref_pll_b_hz == 36'd8589934592
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_f_max_vco_pll_a_hz == 36'd14500000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_f_max_vco_pll_b_hz == 36'd14500000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_f_min_pfd_pll_a_hz == 36'd25000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_f_min_pfd_pll_b_hz == 36'd25000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_f_min_ref_pll_a_hz == 36'd25000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_f_min_ref_pll_b_hz == 36'd25000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_f_min_vco_pll_a_hz == 36'd12000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_f_min_vco_pll_b_hz == 36'd12000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_f_ref_pll_a_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_f_ref_pll_b_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_a_bypass_refclk == BK_COMMON_PLL_A_BYPASS_REFCLK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_a_cfg_clkouten_cb == BK_COMMON_PLL_A_CFG_CLKOUTEN_CB_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_a_cfg_clkouten_lane == BK_COMMON_PLL_A_CFG_CLKOUTEN_LANE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_a_cfg_filter_boostfade_fine_en == BK_COMMON_PLL_A_CFG_FILTER_BOOSTFADE_FINE_EN_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_a_cfg_fine_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_a_cfg_force_kvcc_done == BK_COMMON_PLL_A_CFG_FORCE_KVCC_DONE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_a_cfg_kvcc_code_ovrd == BK_COMMON_PLL_A_CFG_KVCC_CODE_OVRD_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_a_cfg_kvcc_code_val == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_a_cfg_kvcc_settle_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_a_cfg_kvcc_vreg_offset_en_ovrd == BK_COMMON_PLL_A_CFG_KVCC_VREG_OFFSET_EN_OVRD_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_a_cfg_kvcc_vreg_offset_en_val == BK_COMMON_PLL_A_CFG_KVCC_VREG_OFFSET_EN_VAL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_a_cfg_kvcccalib_vreg_offset == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_a_cfg_obsmux0_del == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_a_cfg_obsmux1_del == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_a_cfg_pcs3334div_en == BK_COMMON_PLL_A_CFG_PCS3334DIV_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_a_cfg_pcs40div_en == BK_COMMON_PLL_A_CFG_PCS40DIV_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_a_cfg_ref156div_rat0p5 == BK_COMMON_PLL_A_CFG_REF156DIV_RAT0P5_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_a_cfg_ref156div_ratio == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_a_cfg_refclk100div_en == BK_COMMON_PLL_A_CFG_REFCLK100DIV_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_a_cfg_refclk156div_en == BK_COMMON_PLL_A_CFG_REFCLK156DIV_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_a_cfg_refclk_cnt_limit == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_a_cfg_refclk_cycles_per_1us_maxcnt == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_a_cfg_tdcrefclkcnt == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_a_cfg_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_a_cfg_vregcomp_average_cnt == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_a_fbdiv_strobe_h == BK_COMMON_PLL_A_FBDIV_STROBE_H_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_a_feedfwrdgain == 50'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_a_fraction_div == 60'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_a_m_counter == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_a_n_counter == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_a_pcs3334_ratio == PLL_A_DIV_33_BY_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_a_tdc_fine_res == BK_COMMON_PLL_A_TDC_FINE_RES_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_a_tdctargetcnt == 70'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_b_bypass_refclk == BK_COMMON_PLL_B_BYPASS_REFCLK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_b_cfg_clkouten_cb == BK_COMMON_PLL_B_CFG_CLKOUTEN_CB_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_b_cfg_clkouten_lane == BK_COMMON_PLL_B_CFG_CLKOUTEN_LANE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_b_cfg_filter_boostfade_fine_en == BK_COMMON_PLL_B_CFG_FILTER_BOOSTFADE_FINE_EN_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_b_cfg_fine_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_b_cfg_force_kvcc_done == BK_COMMON_PLL_B_CFG_FORCE_KVCC_DONE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_b_cfg_kvcc_code_ovrd == BK_COMMON_PLL_B_CFG_KVCC_CODE_OVRD_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_b_cfg_kvcc_code_val == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_b_cfg_kvcc_settle_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_b_cfg_kvcc_vreg_offset_en_ovrd == BK_COMMON_PLL_B_CFG_KVCC_VREG_OFFSET_EN_OVRD_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_b_cfg_kvcc_vreg_offset_en_val == BK_COMMON_PLL_B_CFG_KVCC_VREG_OFFSET_EN_VAL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_b_cfg_kvcccalib_vreg_offset == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_b_cfg_obsmux0_del == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_b_cfg_obsmux1_del == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_b_cfg_pcs3334div_en == BK_COMMON_PLL_B_CFG_PCS3334DIV_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_b_cfg_pcs40div_en == BK_COMMON_PLL_B_CFG_PCS40DIV_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_b_cfg_ref156div_rat0p5 == BK_COMMON_PLL_B_CFG_REF156DIV_RAT0P5_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_b_cfg_ref156div_ratio == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_b_cfg_refclk100div_en == BK_COMMON_PLL_B_CFG_REFCLK100DIV_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_b_cfg_refclk156div_en == BK_COMMON_PLL_B_CFG_REFCLK156DIV_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_b_cfg_refclk_cnt_limit == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_b_cfg_refclk_cycles_per_1us_maxcnt == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_b_cfg_tdcrefclkcnt == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_b_cfg_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_b_cfg_vregcomp_average_cnt == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_b_fbdiv_strobe_h == BK_COMMON_PLL_B_FBDIV_STROBE_H_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_b_feedfwrdgain == 50'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_b_fraction_div == 60'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_b_m_counter == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_b_n_counter == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_b_pcs3334_ratio == PLL_B_DIV_33_BY_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_b_tdc_fine_res == BK_COMMON_PLL_B_TDC_FINE_RES_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_b_tdctargetcnt == 70'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_freq_a_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_freq_a_pfd_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_freq_b_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pll_freq_b_pfd_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_plla_cfg_propotional_constant == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_plla_emb_mult == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_plla_fractional_mode == BK_COMMON_PLLA_FRACTIONAL_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_plla_fullrate == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pllb_cfg_propotional_constant == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pllb_emb_mult == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pllb_fractional_mode == BK_COMMON_PLLB_FRACTIONAL_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_pllb_fullrate == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_refclk_source_pll_a == GND_TO_PLLA_REFCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_refclk_source_pll_b == GND_TO_PLLB_REFCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_vco_freq_pll_a_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_common_vco_freq_pll_b_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_cpu_lane0_en == BK_CPU_LANE0_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_cpu_lane1_en == BK_CPU_LANE1_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_cpu_lane2_en == BK_CPU_LANE2_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_cpu_lane3_en == BK_CPU_LANE3_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_cpu_runstall_en == BK_CPU_RUNSTALL_EN_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_dl_enable_lane0 == BK0_DETLAT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_dl_enable_lane1 == BK1_DETLAT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_dl_enable_lane2 == BK2_DETLAT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_dl_enable_lane3 == BK3_DETLAT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_en_rxdat_profile_ln0 == BK0_RXDAT_PROF_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_en_rxdat_profile_ln1 == BK1_RXDAT_PROF_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_en_rxdat_profile_ln2 == BK2_RXDAT_PROF_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_en_rxdat_profile_ln3 == BK3_RXDAT_PROF_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_fast_clk_sel == BK_FAST_CLK_SEL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_ber_clear == BK_LANE0_BER_CLEAR_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_ber_start == BK_LANE0_BER_START_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_ber_stop == BK_LANE0_BER_STOP_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_emb_mult == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_f_max_pfd_lane_pll_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_f_max_ref_lane_pll_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_f_max_vco_lane_pll_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_f_min_pfd_lane_pll_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_f_min_ref_lane_pll_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_f_min_vco_lane_pll_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_f_ref_lane_pll_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_grey_sum_lut == 8'd228
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_lane_pll_pfd_freq_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_bypass_refclk == BK_LANE0_PLL_BYPASS_REFCLK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_cfg_clkouten_cb == BK_LANE0_PLL_CFG_CLKOUTEN_CB_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_cfg_clkouten_lane == BK_LANE0_PLL_CFG_CLKOUTEN_LANE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_cfg_filter_boostfade_fine_en == BK_LANE0_PLL_CFG_FILTER_BOOSTFADE_FINE_EN_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_cfg_fine_prop_coeff == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_cfg_force_kvcc_done == BK_LANE0_PLL_CFG_FORCE_KVCC_DONE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_cfg_kvcc_code_ovrd == BK_LANE0_PLL_CFG_KVCC_CODE_OVRD_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_cfg_kvcc_code_val == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_cfg_kvcc_settle_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_cfg_kvcc_vreg_offset_en_ovrd == BK_LANE0_PLL_CFG_KVCC_VREG_OFFSET_EN_OVRD_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_cfg_kvcc_vreg_offset_en_val == BK_LANE0_PLL_CFG_KVCC_VREG_OFFSET_EN_VAL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_cfg_kvcccalib_vreg_offset == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_cfg_obsmux0_del == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_cfg_obsmux1_del == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_cfg_pcs3334div_en == BK_LANE0_PLL_CFG_PCS3334DIV_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_cfg_pcs40div_en == BK_LANE0_PLL_CFG_PCS40DIV_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_cfg_propotional_constant == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_cfg_ref156div_rat0p5 == BK_LANE0_PLL_CFG_REF156DIV_RAT0P5_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_cfg_ref156div_ratio == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_cfg_refclk100div_en == BK_LANE0_PLL_CFG_REFCLK100DIV_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_cfg_refclk156div_en == BK_LANE0_PLL_CFG_REFCLK156DIV_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_cfg_refclk_cnt_limit == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_cfg_refclk_cycles_per_1us_maxcnt == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_cfg_tdcrefclkcnt == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_cfg_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_cfg_vregcomp_average_cnt == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_fbdiv_strobe_h == BK_LANE0_PLL_FBDIV_STROBE_H_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_feedfwrdgain == 50'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_fraction_div == 60'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_fractional_mode == BK_LANE0_PLL_FRACTIONAL_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_fullrate == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_m_counter == 38'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_n_counter == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_pcs3334_ratio == LANE0_DIV_33_BY_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_rx_pcs3334_ratio == LANE0_RX_DIV_33_BY_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_tdc_fine_res == BK_LANE0_PLL_TDC_FINE_RES_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_pll_tdctargetcnt == 70'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_refclk_source_lane_pll == BK_LANE0_REF_TO_GND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_rx_ber_cnt_en == BK_LANE0_RX_BER_CNT_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_rx_ber_cnt_limit_lsb == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_rx_ber_cnt_limit_msb == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_rx_ber_cnt_mask_0_31 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_rx_ber_cnt_mask_32_63 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_rx_ber_cnt_mask_64_95 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_rx_ber_cnt_mask_96_127 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_rx_prbs_common_en == BK_LANE0_RX_PRBS_COMMON_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_rx_prbs_data_sel == LANE0_PRBS_DATA_SOURCE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_rx_prbs_mode == LANE0_RX_PRBS_7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_rx_user_clk1_en == BK0_RX_USRCLK1_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_rx_user_clk1_sel == BK0_RX_USRCLK1SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_rx_user_clk2_en == BK0_RX_USRCLK2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_rx_user_clk2_sel == BK0_RX_USRCLK2SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_tx_bus_take == BK_LANE0_TX_BUS_TAKE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_tx_prbs_en == BK_LANE0_TX_PRBS_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_tx_prbs_init == BK_LANE0_TX_PRBS_INIT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_tx_prbs_mode == LANE0_TX_PRBS_7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_tx_swizzle_mode == LANE0_SWIZZLE_MODE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_tx_user_clk1_en == BK0_TX_USRCLK1_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_tx_user_clk1_sel == BK0_TX_USRCLK1SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_tx_user_clk2_en == BK0_TX_USRCLK2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_tx_user_clk2_sel == BK0_TX_USRCLK2SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_vco_freq_lane_pll_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane0_xcvr_lane_mode == BK_LANE0_NO_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_ber_clear == BK_LANE1_BER_CLEAR_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_ber_start == BK_LANE1_BER_START_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_ber_stop == BK_LANE1_BER_STOP_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_emb_mult == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_f_max_pfd_lane_pll_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_f_max_ref_lane_pll_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_f_max_vco_lane_pll_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_f_min_pfd_lane_pll_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_f_min_ref_lane_pll_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_f_min_vco_lane_pll_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_f_ref_lane_pll_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_grey_sum_lut == 8'd228
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_lane_pll_pfd_freq_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_bypass_refclk == BK_LANE1_PLL_BYPASS_REFCLK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_cfg_clkouten_cb == BK_LANE1_PLL_CFG_CLKOUTEN_CB_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_cfg_clkouten_lane == BK_LANE1_PLL_CFG_CLKOUTEN_LANE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_cfg_filter_boostfade_fine_en == BK_LANE1_PLL_CFG_FILTER_BOOSTFADE_FINE_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_cfg_fine_prop_coeff == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_cfg_force_kvcc_done == BK_LANE1_PLL_CFG_FORCE_KVCC_DONE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_cfg_kvcc_code_ovrd == BK_LANE1_PLL_CFG_KVCC_CODE_OVRD_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_cfg_kvcc_code_val == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_cfg_kvcc_settle_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_cfg_kvcc_vreg_offset_en_ovrd == BK_LANE1_PLL_CFG_KVCC_VREG_OFFSET_EN_OVRD_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_cfg_kvcc_vreg_offset_en_val == BK_LANE1_PLL_CFG_KVCC_VREG_OFFSET_EN_VAL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_cfg_kvcccalib_vreg_offset == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_cfg_obsmux0_del == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_cfg_obsmux1_del == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_cfg_pcs3334div_en == BK_LANE1_PLL_CFG_PCS3334DIV_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_cfg_pcs40div_en == BK_LANE1_PLL_CFG_PCS40DIV_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_cfg_propotional_constant == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_cfg_ref156div_rat0p5 == BK_LANE1_PLL_CFG_REF156DIV_RAT0P5_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_cfg_ref156div_ratio == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_cfg_refclk100div_en == BK_LANE1_PLL_CFG_REFCLK100DIV_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_cfg_refclk156div_en == BK_LANE1_PLL_CFG_REFCLK156DIV_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_cfg_refclk_cnt_limit == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_cfg_refclk_cycles_per_1us_maxcnt == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_cfg_tdcrefclkcnt == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_cfg_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_cfg_vregcomp_average_cnt == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_fbdiv_strobe_h == BK_LANE1_PLL_FBDIV_STROBE_H_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_feedfwrdgain == 50'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_fraction_div == 60'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_fractional_mode == BK_LANE1_PLL_FRACTIONAL_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_fullrate == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_m_counter == 38'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_n_counter == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_pcs3334_ratio == LANE1_DIV_33_BY_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_rx_pcs3334_ratio == LANE1_RX_DIV_33_BY_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_tdc_fine_res == BK_LANE1_PLL_TDC_FINE_RES_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_pll_tdctargetcnt == 70'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_refclk_source_lane_pll == BK_LANE1_REF_TO_GND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_rx_ber_cnt_en == BK_LANE1_RX_BER_CNT_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_rx_ber_cnt_limit_lsb == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_rx_ber_cnt_limit_msb == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_rx_ber_cnt_mask_0_31 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_rx_ber_cnt_mask_32_63 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_rx_ber_cnt_mask_64_95 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_rx_ber_cnt_mask_96_127 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_rx_prbs_common_en == BK_LANE1_RX_PRBS_COMMON_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_rx_prbs_data_sel == LANE1_PRBS_DATA_SOURCE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_rx_prbs_mode == LANE1_RX_PRBS_7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_rx_user_clk1_en == BK1_RX_USRCLK1_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_rx_user_clk1_sel == BK1_RX_USRCLK1SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_rx_user_clk2_en == BK1_RX_USRCLK2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_rx_user_clk2_sel == BK1_RX_USRCLK2SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_tx_bus_take == BK_LANE1_TX_BUS_TAKE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_tx_prbs_en == BK_LANE1_TX_PRBS_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_tx_prbs_init == BK_LANE1_TX_PRBS_INIT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_tx_prbs_mode == LANE1_TX_PRBS_7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_tx_swizzle_mode == LANE1_SWIZZLE_MODE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_tx_user_clk1_en == BK1_TX_USRCLK1_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_tx_user_clk1_sel == BK1_TX_USRCLK1SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_tx_user_clk2_en == BK1_TX_USRCLK2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_tx_user_clk2_sel == BK1_TX_USRCLK2SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_vco_freq_lane_pll_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane1_xcvr_lane_mode == BK_LANE1_NO_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_ber_clear == BK_LANE2_BER_CLEAR_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_ber_start == BK_LANE2_BER_START_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_ber_stop == BK_LANE2_BER_STOP_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_emb_mult == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_f_max_pfd_lane_pll_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_f_max_ref_lane_pll_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_f_max_vco_lane_pll_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_f_min_pfd_lane_pll_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_f_min_ref_lane_pll_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_f_min_vco_lane_pll_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_f_ref_lane_pll_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_grey_sum_lut == 8'd228
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_lane_pll_pfd_freq_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_bypass_refclk == BK_LANE2_PLL_BYPASS_REFCLK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_cfg_clkouten_cb == BK_LANE2_PLL_CFG_CLKOUTEN_CB_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_cfg_clkouten_lane == BK_LANE2_PLL_CFG_CLKOUTEN_LANE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_cfg_filter_boostfade_fine_en == BK_LANE2_PLL_CFG_FILTER_BOOSTFADE_FINE_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_cfg_fine_prop_coeff == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_cfg_force_kvcc_done == BK_LANE2_PLL_CFG_FORCE_KVCC_DONE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_cfg_kvcc_code_ovrd == BK_LANE2_PLL_CFG_KVCC_CODE_OVRD_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_cfg_kvcc_code_val == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_cfg_kvcc_settle_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_cfg_kvcc_vreg_offset_en_ovrd == BK_LANE2_PLL_CFG_KVCC_VREG_OFFSET_EN_OVRD_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_cfg_kvcc_vreg_offset_en_val == BK_LANE2_PLL_CFG_KVCC_VREG_OFFSET_EN_VAL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_cfg_kvcccalib_vreg_offset == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_cfg_obsmux0_del == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_cfg_obsmux1_del == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_cfg_pcs3334div_en == BK_LANE2_PLL_CFG_PCS3334DIV_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_cfg_pcs40div_en == BK_LANE2_PLL_CFG_PCS40DIV_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_cfg_propotional_constant == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_cfg_ref156div_rat0p5 == BK_LANE2_PLL_CFG_REF156DIV_RAT0P5_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_cfg_ref156div_ratio == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_cfg_refclk100div_en == BK_LANE2_PLL_CFG_REFCLK100DIV_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_cfg_refclk156div_en == BK_LANE2_PLL_CFG_REFCLK156DIV_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_cfg_refclk_cnt_limit == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_cfg_refclk_cycles_per_1us_maxcnt == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_cfg_tdcrefclkcnt == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_cfg_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_cfg_vregcomp_average_cnt == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_fbdiv_strobe_h == BK_LANE2_PLL_FBDIV_STROBE_H_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_feedfwrdgain == 50'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_fraction_div == 60'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_fractional_mode == BK_LANE2_PLL_FRACTIONAL_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_fullrate == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_m_counter == 38'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_n_counter == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_pcs3334_ratio == LANE2_DIV_33_BY_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_rx_pcs3334_ratio == LANE2_RX_DIV_33_BY_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_tdc_fine_res == BK_LANE2_PLL_TDC_FINE_RES_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_pll_tdctargetcnt == 70'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_refclk_source_lane_pll == BK_LANE2_REF_TO_GND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_rx_ber_cnt_en == BK_LANE2_RX_BER_CNT_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_rx_ber_cnt_limit_lsb == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_rx_ber_cnt_limit_msb == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_rx_ber_cnt_mask_0_31 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_rx_ber_cnt_mask_32_63 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_rx_ber_cnt_mask_64_95 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_rx_ber_cnt_mask_96_127 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_rx_prbs_common_en == BK_LANE2_RX_PRBS_COMMON_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_rx_prbs_data_sel == LANE2_PRBS_DATA_SOURCE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_rx_prbs_mode == LANE2_RX_PRBS_7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_rx_user_clk1_en == BK2_RX_USRCLK1_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_rx_user_clk1_sel == BK2_RX_USRCLK1SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_rx_user_clk2_en == BK2_RX_USRCLK2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_rx_user_clk2_sel == BK2_RX_USRCLK2SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_tx_bus_take == BK_LANE2_TX_BUS_TAKE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_tx_prbs_en == BK_LANE2_TX_PRBS_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_tx_prbs_init == BK_LANE2_TX_PRBS_INIT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_tx_prbs_mode == LANE2_TX_PRBS_7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_tx_swizzle_mode == LANE2_SWIZZLE_MODE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_tx_user_clk1_en == BK2_TX_USRCLK1_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_tx_user_clk1_sel == BK2_TX_USRCLK1SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_tx_user_clk2_en == BK2_TX_USRCLK2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_tx_user_clk2_sel == BK2_TX_USRCLK2SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_vco_freq_lane_pll_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane2_xcvr_lane_mode == BK_LANE2_NO_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_ber_clear == BK_LANE3_BER_CLEAR_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_ber_start == BK_LANE3_BER_START_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_ber_stop == BK_LANE3_BER_STOP_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_emb_mult == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_f_max_pfd_lane_pll_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_f_max_ref_lane_pll_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_f_max_vco_lane_pll_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_f_min_pfd_lane_pll_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_f_min_ref_lane_pll_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_f_min_vco_lane_pll_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_f_ref_lane_pll_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_grey_sum_lut == 8'd228
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_lane_pll_pfd_freq_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_bypass_refclk == BK_LANE3_PLL_BYPASS_REFCLK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_cfg_clkouten_cb == BK_LANE3_PLL_CFG_CLKOUTEN_CB_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_cfg_clkouten_lane == BK_LANE3_PLL_CFG_CLKOUTEN_LANE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_cfg_filter_boostfade_fine_en == BK_LANE3_PLL_CFG_FILTER_BOOSTFADE_FINE_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_cfg_fine_prop_coeff == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_cfg_force_kvcc_done == BK_LANE3_PLL_CFG_FORCE_KVCC_DONE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_cfg_kvcc_code_ovrd == BK_LANE3_PLL_CFG_KVCC_CODE_OVRD_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_cfg_kvcc_code_val == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_cfg_kvcc_settle_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_cfg_kvcc_vreg_offset_en_ovrd == BK_LANE3_PLL_CFG_KVCC_VREG_OFFSET_EN_OVRD_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_cfg_kvcc_vreg_offset_en_val == BK_LANE3_PLL_CFG_KVCC_VREG_OFFSET_EN_VAL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_cfg_kvcccalib_vreg_offset == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_cfg_obsmux0_del == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_cfg_obsmux1_del == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_cfg_pcs3334div_en == BK_LANE3_PLL_CFG_PCS3334DIV_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_cfg_pcs40div_en == BK_LANE3_PLL_CFG_PCS40DIV_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_cfg_propotional_constant == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_cfg_ref156div_rat0p5 == BK_LANE3_PLL_CFG_REF156DIV_RAT0P5_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_cfg_ref156div_ratio == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_cfg_refclk100div_en == BK_LANE3_PLL_CFG_REFCLK100DIV_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_cfg_refclk156div_en == BK_LANE3_PLL_CFG_REFCLK156DIV_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_cfg_refclk_cnt_limit == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_cfg_refclk_cycles_per_1us_maxcnt == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_cfg_tdcrefclkcnt == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_cfg_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_cfg_vregcomp_average_cnt == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_fbdiv_strobe_h == BK_LANE3_PLL_FBDIV_STROBE_H_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_feedfwrdgain == 50'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_fraction_div == 60'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_fractional_mode == BK_LANE3_PLL_FRACTIONAL_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_fullrate == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_m_counter == 38'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_n_counter == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_pcs3334_ratio == LANE3_DIV_33_BY_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_rx_pcs3334_ratio == LANE3_RX_DIV_33_BY_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_tdc_fine_res == BK_LANE3_PLL_TDC_FINE_RES_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_pll_tdctargetcnt == 70'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_refclk_source_lane_pll == BK_LANE3_REF_TO_GND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_rx_ber_cnt_en == BK_LANE3_RX_BER_CNT_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_rx_ber_cnt_limit_lsb == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_rx_ber_cnt_limit_msb == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_rx_ber_cnt_mask_0_31 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_rx_ber_cnt_mask_32_63 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_rx_ber_cnt_mask_64_95 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_rx_ber_cnt_mask_96_127 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_rx_prbs_common_en == BK_LANE3_RX_PRBS_COMMON_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_rx_prbs_data_sel == LANE3_PRBS_DATA_SOURCE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_rx_prbs_mode == LANE3_RX_PRBS_7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_rx_user_clk1_en == BK3_RX_USRCLK1_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_rx_user_clk1_sel == BK3_RX_USRCLK1SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_rx_user_clk2_en == BK3_RX_USRCLK2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_rx_user_clk2_sel == BK3_RX_USRCLK2SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_tx_bus_take == BK_LANE3_TX_BUS_TAKE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_tx_prbs_en == BK_LANE3_TX_PRBS_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_tx_prbs_init == BK_LANE3_TX_PRBS_INIT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_tx_prbs_mode == LANE3_TX_PRBS_7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_tx_swizzle_mode == LANE3_SWIZZLE_MODE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_tx_user_clk1_en == BK3_TX_USRCLK1_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_tx_user_clk1_sel == BK3_TX_USRCLK1SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_tx_user_clk2_en == BK3_TX_USRCLK2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_tx_user_clk2_sel == BK3_TX_USRCLK2SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_vco_freq_lane_pll_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lane3_xcvr_lane_mode == BK_LANE3_NO_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lnx_txovf_rxbdstb_inten == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_lnx_txudf_pldrstb_inten == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_pll_fullrate == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_rx_bdst_rcon_en_ln0 == BK0_RX_BADST_RCON_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_rx_bdst_rcon_en_ln1 == BK1_RX_BADST_RCON_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_rx_bdst_rcon_en_ln2 == BK2_RX_BADST_RCON_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_rx_bdst_rcon_en_ln3 == BK3_RX_BADST_RCON_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_rx_lat_bit_for_async_lane0 == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_rx_lat_bit_for_async_lane1 == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_rx_lat_bit_for_async_lane2 == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_rx_lat_bit_for_async_lane3 == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_rx_ppmd_rcon_en_ln0 == BK0_RX_PPMD_BADST_RCON_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_rx_ppmd_rcon_en_ln1 == BK1_RX_PPMD_BADST_RCON_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_rx_ppmd_rcon_en_ln2 == BK2_RX_PPMD_BADST_RCON_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_rx_ppmd_rcon_en_ln3 == BK3_RX_PPMD_BADST_RCON_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_rxbit_cntr_pma_lane0 == BK0_RXBIT_CNTR_PMADIR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_rxbit_cntr_pma_lane1 == BK1_RXBIT_CNTR_PMADIR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_rxbit_cntr_pma_lane2 == BK2_RXBIT_CNTR_PMADIR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_rxbit_cntr_pma_lane3 == BK3_RXBIT_CNTR_PMADIR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_rxbit_rollover_lane0 == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_rxbit_rollover_lane1 == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_rxbit_rollover_lane2 == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_rxbit_rollover_lane3 == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_rxdat_1cnt_thld_high_ln0 == 20'd531612
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_rxdat_1cnt_thld_high_ln1 == 20'd531612
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_rxdat_1cnt_thld_high_ln2 == 20'd531612
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_rxdat_1cnt_thld_high_ln3 == 20'd531612
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_rxdat_1cnt_thld_low_ln0 == 20'd516885
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_rxdat_1cnt_thld_low_ln1 == 20'd516885
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_rxdat_1cnt_thld_low_ln2 == 20'd516885
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_rxdat_1cnt_thld_low_ln3 == 20'd516885
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_sel_tx_user_data_ln0 == BK0_TX_USRDATA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_sel_tx_user_data_ln1 == BK1_TX_USRDATA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_sel_tx_user_data_ln2 == BK2_TX_USRDATA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_sel_tx_user_data_ln3 == BK3_TX_USRDATA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq0_enable == SEQ0_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq10_enable == SEQ10_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq11_enable == SEQ11_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq12_enable == SEQ12_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq13_enable == SEQ13_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq14_enable == SEQ14_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq15_enable == SEQ15_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq16_enable == SEQ16_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq17_enable == SEQ17_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq18_enable == SEQ18_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq19_enable == SEQ19_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq1_enable == SEQ1_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq20_enable == SEQ20_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq21_enable == SEQ21_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq22_enable == SEQ22_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq23_enable == SEQ23_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq24_enable == SEQ24_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq25_enable == SEQ25_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq26_enable == SEQ26_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq27_enable == SEQ27_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq28_enable == SEQ28_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq29_enable == SEQ29_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq2_enable == SEQ2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq30_enable == SEQ30_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq31_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq31_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq31_enable == SEQ31_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq31_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq31_rdwrb == SEQ31_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq32_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq32_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq32_enable == SEQ32_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq32_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq32_rdwrb == SEQ32_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq33_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq33_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq33_enable == SEQ33_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq33_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq33_rdwrb == SEQ33_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq34_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq34_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq34_enable == SEQ34_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq34_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq34_rdwrb == SEQ34_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq35_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq35_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq35_enable == SEQ35_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq35_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq35_rdwrb == SEQ35_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq36_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq36_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq36_enable == SEQ36_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq36_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq36_rdwrb == SEQ36_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq37_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq37_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq37_enable == SEQ37_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq37_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq37_rdwrb == SEQ37_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq38_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq38_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq38_enable == SEQ38_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq38_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq38_rdwrb == SEQ38_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq39_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq39_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq39_enable == SEQ39_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq39_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq39_rdwrb == SEQ39_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq3_enable == SEQ3_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq40_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq40_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq40_enable == SEQ40_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq40_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq40_rdwrb == SEQ40_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq41_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq41_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq41_enable == SEQ41_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq41_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq41_rdwrb == SEQ41_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq42_enable == SEQ42_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq43_enable == SEQ43_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq44_enable == SEQ44_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq45_enable == SEQ45_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq46_enable == SEQ46_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq4_enable == SEQ4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq55_enable == SEQ55_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq56_enable == SEQ56_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq57_enable == SEQ57_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq58_enable == SEQ58_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq59_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq59_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq59_enable == SEQ59_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq59_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq59_rdwrb == SEQ59_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq5_enable == SEQ5_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq60_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq60_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq60_enable == SEQ60_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq60_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq60_rdwrb == SEQ60_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq61_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq61_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq61_enable == SEQ61_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq61_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq61_rdwrb == SEQ61_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq62_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq62_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq62_enable == SEQ62_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq62_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq62_rdwrb == SEQ62_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq63_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq63_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq63_enable == SEQ63_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq63_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq63_rdwrb == SEQ63_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq6_enable == SEQ6_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq7_enable == SEQ7_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq8_enable == SEQ8_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_seq9_enable == SEQ9_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_speed_grade == BK_SPEED_GRADE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_tb_reg9 == 32'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_tx_lnx_ovf_inten_dirsignal == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_tx_lnx_rxbadst_inten_dirsignal == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_tx_lnx_udf_inten_dirsignal == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_tx_usr_data_ln0_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_tx_usr_data_ln0_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_tx_usr_data_ln0_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_tx_usr_data_ln0_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_tx_usr_data_ln1_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_tx_usr_data_ln1_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_tx_usr_data_ln1_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_tx_usr_data_ln1_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_tx_usr_data_ln2_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_tx_usr_data_ln2_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_tx_usr_data_ln2_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_tx_usr_data_ln2_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_tx_usr_data_ln3_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_tx_usr_data_ln3_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_tx_usr_data_ln3_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.bk_tx_usr_data_ln3_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.channel_type == CHNL_SIMULATION
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.package_type == HIGHEND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.powermode_ac_bkwrap_l0 == AC_BKWRAP_OFF_L0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.powermode_ac_bkwrap_l1 == AC_BKWRAP_OFF_L1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.powermode_ac_bkwrap_l2 == AC_BKWRAP_OFF_L2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.powermode_ac_bkwrap_l3 == AC_BKWRAP_OFF_L3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.powermode_ac_csr == AC_XCVR_CSR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.powermode_ac_serdes_l0 == AC_SERDES_OFF_L0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.powermode_ac_serdes_l1 == AC_SERDES_OFF_L1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.powermode_ac_serdes_l2 == AC_SERDES_OFF_L2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.powermode_ac_serdes_l3 == AC_SERDES_OFF_L3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.powermode_ac_xtensa_l0 == AC_XTENSA_OFF_L0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.powermode_ac_xtensa_l1 == AC_XTENSA_OFF_L1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.powermode_ac_xtensa_l2 == AC_XTENSA_OFF_L2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.powermode_ac_xtensa_l3 == AC_XTENSA_OFF_L3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.powermode_dc_bkwrap_l0 == POWERDOWN_DC_BKWRAP_L0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.powermode_dc_bkwrap_l1 == POWERDOWN_DC_BKWRAP_L1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.powermode_dc_bkwrap_l2 == POWERDOWN_DC_BKWRAP_L2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.powermode_dc_bkwrap_l3 == POWERDOWN_DC_BKWRAP_L3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.powermode_dc_csr == POWERDOWN_DC_XCVR_CSR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.powermode_dc_dts == POWERDOWN_DC_DTS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.powermode_dc_serdes_l0 == POWERDOWN_DC_SERDES_L0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.powermode_dc_serdes_l1 == POWERDOWN_DC_SERDES_L1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.powermode_dc_serdes_l2 == POWERDOWN_DC_SERDES_L2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.powermode_dc_serdes_l3 == POWERDOWN_DC_SERDES_L3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.powermode_dc_xtensa == POWERDOWN_DC_XTENSA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.powermode_freq_hz_avmm == 36'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.powermode_freq_hz_serdes_l0_par == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.powermode_freq_hz_serdes_l0_ui == 37'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.powermode_freq_hz_serdes_l1_par == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.powermode_freq_hz_serdes_l1_ui == 37'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.powermode_freq_hz_serdes_l2_par == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.powermode_freq_hz_serdes_l2_ui == 37'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.powermode_freq_hz_serdes_l3_par == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.powermode_freq_hz_serdes_l3_ui == 37'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.powermode_freq_hz_xtensa == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.refclk1_freq == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.refclk2_freq == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.rx_termination == RXTERM_OFFSET_P0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.rxterm_sd == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.speed_grade == SPEED_GRADE_56G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.tx_termination == TXTERM_OFFSET_P0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.txterm_sd == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_aonclk_mstclk_sel == SEL_REFCLKA_FOR_AON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_barak_rx_bdst_rcon_en_ln0 == BK0_RX_BADST_RCON_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_barak_rx_bdst_rcon_en_ln1 == BK1_RX_BADST_RCON_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_barak_rx_bdst_rcon_en_ln2 == BK2_RX_BADST_RCON_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_barak_rx_bdst_rcon_en_ln3 == BK3_RX_BADST_RCON_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_barak_rx_ln_swl == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_barak_rx_mute_ln0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_barak_rx_mute_ln1 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_barak_rx_mute_ln2 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_barak_rx_mute_ln3 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_barak_rx_ppmd_rcon_en_ln0 == BK0_RX_PPMD_BADST_RCON_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_barak_rx_ppmd_rcon_en_ln1 == BK1_RX_PPMD_BADST_RCON_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_barak_rx_ppmd_rcon_en_ln2 == BK2_RX_PPMD_BADST_RCON_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_barak_rx_ppmd_rcon_en_ln3 == BK3_RX_PPMD_BADST_RCON_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_barak_tx_ln_swl == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_bond_n_ch_l0 == TX_BOND_SIZE_1_L0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_bond_n_ch_l1 == TX_BOND_SIZE_1_L1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_bond_n_ch_l2 == TX_BOND_SIZE_1_L2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_bond_n_ch_l3 == TX_BOND_SIZE_1_L3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_bti_prot_enable == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_bticlk_rclk_ln0_feature_on == BK0_BTICLK_RCLK_FEATUR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_bticlk_rclk_ln0_force_on == BK0_BTICLK_RCLK_FRC_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_bticlk_rclk_ln1_feature_on == BK1_BTICLK_RCLK_FEATUR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_bticlk_rclk_ln1_force_on == BK1_BTICLK_RCLK_FRC_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_bticlk_rclk_ln2_feature_on == BK2_BTICLK_RCLK_FEATUR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_bticlk_rclk_ln2_force_on == BK2_BTICLK_RCLK_FRC_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_bticlk_rclk_ln3_feature_on == BK3_BTICLK_RCLK_FEATUR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_bticlk_rclk_ln3_force_on == BK3_BTICLK_RCLK_FRC_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_bticlk_tclk_ln0_feature_on == BK0_BTICLK_TCLK_FEATUR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_bticlk_tclk_ln0_force_on == BK0_BTICLK_TCLK_FRC_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_bticlk_tclk_ln1_feature_on == BK1_BTICLK_TCLK_FEATUR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_bticlk_tclk_ln1_force_on == BK1_BTICLK_TCLK_FRC_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_bticlk_tclk_ln2_feature_on == BK2_BTICLK_TCLK_FEATUR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_bticlk_tclk_ln2_force_on == BK2_BTICLK_TCLK_FRC_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_bticlk_tclk_ln3_feature_on == BK3_BTICLK_TCLK_FEATUR_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_bticlk_tclk_ln3_force_on == BK3_BTICLK_TCLK_FRC_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_clk_en_dfd_clk == BK_DFD_CLK_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_clk_en_plla_cmos_refclk_out == CLKEN_CMOS_PLLA_REFCLKO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_clk_en_pllb_cmos_refclk_out == CLKEN_CMOS_PLLB_REFCLKO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_clk_en_rx_clk_lane0 == BARAK_TXRX_CLKEN_CFG_CLK_EN_RX_CLK_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_clk_en_rx_clk_lane1 == BARAK_TXRX_CLKEN_CFG_CLK_EN_RX_CLK_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_clk_en_rx_clk_lane2 == BARAK_TXRX_CLKEN_CFG_CLK_EN_RX_CLK_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_clk_en_rx_clk_lane3 == BARAK_TXRX_CLKEN_CFG_CLK_EN_RX_CLK_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_clk_en_rx_usr_clk1_lane0 == BARAK_TXRX_CLKEN_CFG_CLK_EN_RX_USR_CLK1_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_clk_en_rx_usr_clk1_lane1 == BARAK_TXRX_CLKEN_CFG_CLK_EN_RX_USR_CLK1_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_clk_en_rx_usr_clk1_lane2 == BARAK_TXRX_CLKEN_CFG_CLK_EN_RX_USR_CLK1_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_clk_en_rx_usr_clk1_lane3 == BARAK_TXRX_CLKEN_CFG_CLK_EN_RX_USR_CLK1_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_clk_en_rx_usr_clk2_lane0 == BARAK_TXRX_CLKEN_CFG_CLK_EN_RX_USR_CLK2_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_clk_en_rx_usr_clk2_lane1 == BARAK_TXRX_CLKEN_CFG_CLK_EN_RX_USR_CLK2_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_clk_en_rx_usr_clk2_lane2 == BARAK_TXRX_CLKEN_CFG_CLK_EN_RX_USR_CLK2_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_clk_en_rx_usr_clk2_lane3 == BARAK_TXRX_CLKEN_CFG_CLK_EN_RX_USR_CLK2_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_clk_en_sclk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_clk_en_sys_aon_clk == SYS_AON_CLK_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_clk_en_tx_clki_lane0 == BARAK_TXRX_CLKEN_CFG_CLK_EN_TX_CLKI_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_clk_en_tx_clki_lane1 == BARAK_TXRX_CLKEN_CFG_CLK_EN_TX_CLKI_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_clk_en_tx_clki_lane2 == BARAK_TXRX_CLKEN_CFG_CLK_EN_TX_CLKI_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_clk_en_tx_clki_lane3 == BARAK_TXRX_CLKEN_CFG_CLK_EN_TX_CLKI_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_clk_en_tx_clko_lane0 == BARAK_TXRX_CLKEN_CFG_CLK_EN_TX_CLKO_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_clk_en_tx_clko_lane1 == BARAK_TXRX_CLKEN_CFG_CLK_EN_TX_CLKO_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_clk_en_tx_clko_lane2 == BARAK_TXRX_CLKEN_CFG_CLK_EN_TX_CLKO_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_clk_en_tx_clko_lane3 == BARAK_TXRX_CLKEN_CFG_CLK_EN_TX_CLKO_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_clk_en_tx_usr_clk1_lane0 == BARAK_TXRX_CLKEN_CFG_CLK_EN_TX_USR_CLK1_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_clk_en_tx_usr_clk1_lane1 == BARAK_TXRX_CLKEN_CFG_CLK_EN_TX_USR_CLK1_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_clk_en_tx_usr_clk1_lane2 == BARAK_TXRX_CLKEN_CFG_CLK_EN_TX_USR_CLK1_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_clk_en_tx_usr_clk1_lane3 == BARAK_TXRX_CLKEN_CFG_CLK_EN_TX_USR_CLK1_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_clk_en_tx_usr_clk2_lane0 == BARAK_TXRX_CLKEN_CFG_CLK_EN_TX_USR_CLK2_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_clk_en_tx_usr_clk2_lane1 == BARAK_TXRX_CLKEN_CFG_CLK_EN_TX_USR_CLK2_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_clk_en_tx_usr_clk2_lane2 == BARAK_TXRX_CLKEN_CFG_CLK_EN_TX_USR_CLK2_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_clk_en_tx_usr_clk2_lane3 == BARAK_TXRX_CLKEN_CFG_CLK_EN_TX_USR_CLK2_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_deskew_cnt_lane == BARAK_CNT_MAX7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_dfd_apb_rdata_sel == DFD_APB_RDATA_28_29
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_dfd_extrig_muxsel == DFD_ETMUX_SEL_BY2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_dfd_muxsel == DFD_DMUX_SEL_SIGNATURE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_dfd_rsvd_muxsel == DFD_RSVMUX_SEL_BY2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_empty_thld_lane0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_empty_thld_lane1 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_empty_thld_lane2 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_empty_thld_lane3 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_en_pldrst2srds == DIS_PLDRST_2_SRDS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_en_rxdat_profile_ln0 == BK0_RXDAT_PROF_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_en_rxdat_profile_ln1 == BK1_RXDAT_PROF_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_en_rxdat_profile_ln2 == BK2_RXDAT_PROF_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_en_rxdat_profile_ln3 == BK3_RXDAT_PROF_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_en_tx_deskew_l0 == TX_BOND_LANE0_000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_en_tx_deskew_l1 == TX_BOND_LANE1_000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_en_tx_deskew_l2 == TX_BOND_LANE2_000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_en_tx_deskew_l3 == TX_BOND_LANE3_000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_full_thld_lane0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_full_thld_lane1 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_full_thld_lane2 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_full_thld_lane3 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_fuse_valid == BARAK_FUSE_VALID_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_lane0_rx_user_clk1_sel == BK0_RX_USRCLK1SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_lane0_rx_user_clk2_sel == BK0_RX_USRCLK2SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_lane0_tx_user_clk1_sel == BK0_TX_USRCLK1SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_lane0_tx_user_clk2_sel == BK0_TX_USRCLK2SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_lane1_rx_user_clk1_sel == BK1_RX_USRCLK1SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_lane1_rx_user_clk2_sel == BK1_RX_USRCLK2SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_lane1_tx_user_clk1_sel == BK1_TX_USRCLK1SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_lane1_tx_user_clk2_sel == BK1_TX_USRCLK2SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_lane2_rx_user_clk1_sel == BK2_RX_USRCLK1SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_lane2_rx_user_clk2_sel == BK2_RX_USRCLK2SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_lane2_tx_user_clk1_sel == BK2_TX_USRCLK1SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_lane2_tx_user_clk2_sel == BK2_TX_USRCLK2SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_lane3_rx_user_clk1_sel == BK3_RX_USRCLK1SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_lane3_rx_user_clk2_sel == BK3_RX_USRCLK2SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_lane3_tx_user_clk1_sel == BK3_TX_USRCLK1SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_lane3_tx_user_clk2_sel == BK3_TX_USRCLK2SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_latpls_bw_lane0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_latpls_bw_lane1 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_latpls_bw_lane2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_latpls_bw_lane3 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_lnx_txovf_rxbdstb_inten == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_lnx_txudf_pldrstb_inten == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_mbin_msg_l0 == 30'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_mbin_msg_l1 == 30'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_mbin_msg_l2 == 30'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_mbin_msg_l3 == 30'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_mbout_msg_l0 == 30'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_mbout_msg_l1 == 30'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_mbout_msg_l2 == 30'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_mbout_msg_l3 == 30'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_new_msg_l0 == BARAK_MBOUT_NO_NEWMSG_L0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_new_msg_l1 == BARAK_MBOUT_NO_NEWMSG_L1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_new_msg_l2 == BARAK_MBOUT_NO_NEWMSG_L2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_new_msg_l3 == BARAK_MBOUT_NO_NEWMSG_L3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_nomode_cmd_ch0 == 32'd7423
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_nomode_cmd_ch1 == 32'd7423
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_nomode_cmd_ch2 == 32'd7423
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_nomode_cmd_ch3 == 32'd7423
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_pempty_thld_lane0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_pempty_thld_lane1 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_pempty_thld_lane2 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_pempty_thld_lane3 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_pfull_thld_lane0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_pfull_thld_lane1 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_pfull_thld_lane2 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_pfull_thld_lane3 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_phcomp_rd_delay_lane0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_phcomp_rd_delay_lane1 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_phcomp_rd_delay_lane2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_phcomp_rd_delay_lane3 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_rd_empty_lanex == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_reconverge_cmd_ch0 == 32'd23807
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_reconverge_cmd_ch1 == 32'd23807
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_reconverge_cmd_ch2 == 32'd23807
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_reconverge_cmd_ch3 == 32'd23807
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_restart_seq_sm == RESTART_SEQ_SM_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_rst_dfd_extrig_cntr == BK_DFD_XTRGCNTR_RST_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_rst_dfd_signature_cntr == BK_DFD_SIGCNTR_RST_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_rst_rxbit_cntr_lane0 == BK0_RXBIT_CNTR_RST_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_rst_rxbit_cntr_lane1 == BK1_RXBIT_CNTR_RST_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_rst_rxbit_cntr_lane2 == BK2_RXBIT_CNTR_RST_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_rst_rxbit_cntr_lane3 == BK3_RXBIT_CNTR_RST_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_rstb_dfd_logic == RST_DFD_LOGIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_rx_fifo_lat_en_lanex == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_rx_lat_bit_for_async_lane0 == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_rx_lat_bit_for_async_lane1 == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_rx_lat_bit_for_async_lane2 == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_rx_lat_bit_for_async_lane3 == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_rx_pipeline_brk_lanex == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_rxbit_cntr_pma_lane0 == BK0_RXBIT_CNTR_PMADIR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_rxbit_cntr_pma_lane1 == BK1_RXBIT_CNTR_PMADIR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_rxbit_cntr_pma_lane2 == BK2_RXBIT_CNTR_PMADIR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_rxbit_cntr_pma_lane3 == BK3_RXBIT_CNTR_PMADIR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_rxbit_rollover_lane0 == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_rxbit_rollover_lane1 == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_rxbit_rollover_lane2 == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_rxbit_rollover_lane3 == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_rxdat_1cnt_thld_high_ln0 == 20'd531612
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_rxdat_1cnt_thld_high_ln1 == 20'd531612
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_rxdat_1cnt_thld_high_ln2 == 20'd531612
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_rxdat_1cnt_thld_high_ln3 == 20'd531612
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_rxdat_1cnt_thld_low_ln0 == 20'd516885
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_rxdat_1cnt_thld_low_ln1 == 20'd516885
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_rxdat_1cnt_thld_low_ln2 == 20'd516885
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_rxdat_1cnt_thld_low_ln3 == 20'd516885
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_rxdat_bw_ln0 == BK0_RXD_PROF_BW_128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_rxdat_bw_ln1 == BK1_RXD_PROF_BW_128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_rxdat_bw_ln2 == BK2_RXD_PROF_BW_128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_rxdat_bw_ln3 == BK3_RXD_PROF_BW_128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_sel_bti_clk_sel_refclk == BTI_CLK_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_sel_rxbit_adder_lane0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_sel_rxbit_adder_lane1 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_sel_rxbit_adder_lane2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_sel_rxbit_adder_lane3 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_sel_tx_user_data_ln0 == BK0_TX_USRDATA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_sel_tx_user_data_ln1 == BK1_TX_USRDATA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_sel_tx_user_data_ln2 == BK2_TX_USRDATA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_sel_tx_user_data_ln3 == BK3_TX_USRDATA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_send_msg_l0 == BARAK_MBIN_NOMSG_2_SEND_L0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_send_msg_l1 == BARAK_MBIN_NOMSG_2_SEND_L1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_send_msg_l2 == BARAK_MBIN_NOMSG_2_SEND_L2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_send_msg_l3 == BARAK_MBIN_NOMSG_2_SEND_L3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq0_addr == 20'd401492
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq0_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq10_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq10_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq11_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq11_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq12_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq12_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq13_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq13_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq14_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq14_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq15_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq15_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq16_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq16_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq17_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq17_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq18_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq18_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq19_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq19_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq1_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq1_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq20_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq20_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq21_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq21_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq22_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq22_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq23_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq23_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq24_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq24_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq25_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq25_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq26_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq26_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq27_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq27_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq28_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq28_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq29_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq29_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq2_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq2_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq30_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq30_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq31_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq31_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq31_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq32_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq32_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq32_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq33_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq33_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq33_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq34_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq34_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq34_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq35_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq35_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq35_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq36_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq36_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq36_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq37_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq37_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq37_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq38_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq38_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq38_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq39_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq39_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq39_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq3_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq3_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq40_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq40_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq40_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq41_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq41_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq41_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq42_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq42_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq43_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq43_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq44_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq44_rdata_unmask == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq45_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq45_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq46_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq46_rdata_unmask == 32'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq47_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq47_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq48_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq48_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq49_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq49_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq4_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq4_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq50_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq50_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq51_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq51_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq52_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq52_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq53_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq53_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq53_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq54_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq54_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq54_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq55_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq55_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq56_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq56_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq57_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq57_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq58_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq58_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq59_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq59_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq59_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq5_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq5_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq60_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq60_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq60_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq61_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq61_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq61_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq62_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq62_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq62_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq63_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq63_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq63_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq6_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq6_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq7_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq7_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq8_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq8_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq9_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_seq9_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_sft_rst_rx_n_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_sft_rst_tx_n_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_skip_rdseq_pulse == SKIP_READ_SEQ_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_spare_reg0_resv == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_spare_reg1 == 32'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_spare_reg2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_tx2rx_bypass_brk_lane0 == BK0_TX2RX_SRDS_BYP_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_tx2rx_bypass_brk_lane1 == BK1_TX2RX_SRDS_BYP_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_tx2rx_bypass_brk_lane2 == BK2_TX2RX_SRDS_BYP_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_tx2rx_bypass_brk_lane3 == BK3_TX2RX_SRDS_BYP_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_tx_clk_sel2_lane0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_tx_clk_sel2_lane1 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_tx_clk_sel2_lane2 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_tx_clk_sel2_lane3 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_tx_lnx_ovf_inten_dirsignal == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_tx_lnx_rxbadst_inten_dirsignal == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_tx_lnx_udf_inten_dirsignal == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_tx_min_latency == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_tx_pipeline_brk_lanex == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_tx_usr_data_ln0_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_tx_usr_data_ln0_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_tx_usr_data_ln0_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_tx_usr_data_ln0_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_tx_usr_data_ln1_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_tx_usr_data_ln1_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_tx_usr_data_ln1_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_tx_usr_data_ln1_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_tx_usr_data_ln2_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_tx_usr_data_ln2_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_tx_usr_data_ln2_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_tx_usr_data_ln2_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_tx_usr_data_ln3_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_tx_usr_data_ln3_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_tx_usr_data_ln3_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_tx_usr_data_ln3_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_unfreeze_hard_rst == UNFREEZE_HARDRST_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_unfreeze_rst_rxdl == UNFREEZE_RST_RXDL_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_unfreeze_rst_txdl == UNFREEZE_RST_TXDL_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.cfg_wr_full_lanex == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq0_cbplls_refsel_static_field == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq0_cmn_plla_refclk_sel == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq0_cmn_plla_refclk_sel_ovr == SERDES_SHIM_COMMON_REG_11_CFG_CMN_PLLA_REF_CLK_SEL_OVRD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq0_cmn_pllb_refclk_sel == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq0_cmn_pllb_refclk_sel_ovr == SERDES_SHIM_COMMON_REG_11_CFG_CMN_PLLB_REF_CLK_SEL_OVRD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq0_enable == SEQ0_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq0_rdwrb == SEQ0_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq10_enable == SEQ10_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq10_ln3_pll_refclk_sel == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq10_lsb_static_field == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq10_msb_static_field == 23'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq10_rdwrb == SEQ10_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq11_enable == SEQ11_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq11_ln0_rx_gry_lut == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq11_ln0_rx_inv == SERDES_LANE_LANE_CTRL_LANE0_REG_1_CFG_RX_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq11_ln0_rx_pre == SERDES_LANE_LANE_CTRL_LANE0_REG_1_CFG_RX_PRECODE_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq11_ln0_swl == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq11_ln0_tx2rx_lpbk_en == SERDES_LANE_LANE_CTRL_LANE0_REG_1_CFG_LANE_DIG_TX2RX_LOOPBACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq11_lsb_static_field == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq11_msb_static_field == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq11_rdwrb == SEQ11_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq12_enable == SEQ12_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq12_ln1_rx_gry_lut == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq12_ln1_rx_inv == SERDES_LANE_LANE_CTRL_LANE1_REG_1_CFG_RX_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq12_ln1_rx_pre == SERDES_LANE_LANE_CTRL_LANE1_REG_1_CFG_RX_PRECODE_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq12_ln1_swl == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq12_ln1_tx2rx_lpbk_en == SERDES_LANE_LANE_CTRL_LANE1_REG_1_CFG_LANE_DIG_TX2RX_LOOPBACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq12_lsb_static_field == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq12_msb_static_field == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq12_rdwrb == SEQ12_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq13_enable == SEQ13_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq13_ln2_rx_gry_lut == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq13_ln2_rx_inv == SERDES_LANE_LANE_CTRL_LANE2_REG_1_CFG_RX_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq13_ln2_rx_pre == SERDES_LANE_LANE_CTRL_LANE2_REG_1_CFG_RX_PRECODE_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq13_ln2_swl == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq13_ln2_tx2rx_lpbk_en == SERDES_LANE_LANE_CTRL_LANE2_REG_1_CFG_LANE_DIG_TX2RX_LOOPBACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq13_lsb_static_field == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq13_msb_static_field == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq13_rdwrb == SEQ13_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq14_enable == SEQ14_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq14_ln3_rx_gry_lut == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq14_ln3_rx_inv == SERDES_LANE_LANE_CTRL_LANE3_REG_1_CFG_RX_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq14_ln3_rx_pre == SERDES_LANE_LANE_CTRL_LANE3_REG_1_CFG_RX_PRECODE_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq14_ln3_swl == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq14_ln3_tx2rx_lpbk_en == SERDES_LANE_LANE_CTRL_LANE3_REG_1_CFG_LANE_DIG_TX2RX_LOOPBACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq14_lsb_static_field == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq14_msb_static_field == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq14_rdwrb == SEQ14_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq15_enable == SEQ15_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq15_rdwrb == SEQ15_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq15_static_field == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq15_tx_ln0_ffe_coeff_p2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq15_tx_ln0_ffe_coeff_p3 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq15_tx_ln0_ffe_coeff_p4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq15_tx_ln0_ffe_coeff_p5 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq16_enable == SEQ16_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq16_rdwrb == SEQ16_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq16_static_field == 23'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq16_tx_ln0_ffe_cmod == 9'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq17_enable == SEQ17_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq17_rdwrb == SEQ17_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq17_static_field == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq17_tx_ln0_ffe_coeff_0 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq17_tx_ln0_ffe_coeff_load == SERDES_LANE_ANA_TX_LANE0_REG_7_CSR_TXFFE_COEFF_LOAD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq17_tx_ln0_ffe_coeff_m1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq17_tx_ln0_ffe_coeff_m2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq17_tx_ln0_ffe_coeff_p1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq17_tx_ln0_ffe_mode32ui == SERDES_LANE_ANA_TX_LANE0_REG_7_CSR_TXFFE_MODE32UI_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq17_tx_ln0_ffe_output_swizzle == SERDES_LANE_ANA_TX_LANE0_REG_7_CSR_TXFFE_OUTPUT_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq18_enable == SEQ18_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq18_rdwrb == SEQ18_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq18_static_field == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq18_tx_ln1_ffe_coeff_p2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq18_tx_ln1_ffe_coeff_p3 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq18_tx_ln1_ffe_coeff_p4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq18_tx_ln1_ffe_coeff_p5 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq19_enable == SEQ19_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq19_rdwrb == SEQ19_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq19_static_field == 23'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq19_tx_ln1_ffe_cmod == 9'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq1_cmn_plla_fbdiv_frac == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq1_cmn_plla_fbdiv_fracen == SERDES_SHIM_ANA_PLL_PLL_A_REG_1_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq1_cmn_plla_fbdiv_intgr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq1_enable == SEQ1_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq1_rdwrb == SEQ1_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq20_enable == SEQ20_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq20_rdwrb == SEQ20_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq20_static_field == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq20_tx_ln1_ffe_coeff_0 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq20_tx_ln1_ffe_coeff_load == SERDES_LANE_ANA_TX_LANE1_REG_7_CSR_TXFFE_COEFF_LOAD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq20_tx_ln1_ffe_coeff_m1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq20_tx_ln1_ffe_coeff_m2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq20_tx_ln1_ffe_coeff_p1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq20_tx_ln1_ffe_mode32ui == SERDES_LANE_ANA_TX_LANE1_REG_7_CSR_TXFFE_MODE32UI_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq20_tx_ln1_ffe_output_swizzle == SERDES_LANE_ANA_TX_LANE1_REG_7_CSR_TXFFE_OUTPUT_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq21_enable == SEQ21_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq21_rdwrb == SEQ21_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq21_static_field == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq21_tx_ln2_ffe_coeff_p2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq21_tx_ln2_ffe_coeff_p3 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq21_tx_ln2_ffe_coeff_p4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq21_tx_ln2_ffe_coeff_p5 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq22_enable == SEQ22_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq22_rdwrb == SEQ22_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq22_static_field == 23'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq22_tx_ln2_ffe_cmod == 9'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq23_enable == SEQ23_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq23_rdwrb == SEQ23_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq23_static_field == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq23_tx_ln2_ffe_coeff_0 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq23_tx_ln2_ffe_coeff_load == SERDES_LANE_ANA_TX_LANE2_REG_7_CSR_TXFFE_COEFF_LOAD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq23_tx_ln2_ffe_coeff_m1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq23_tx_ln2_ffe_coeff_m2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq23_tx_ln2_ffe_coeff_p1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq23_tx_ln2_ffe_mode32ui == SERDES_LANE_ANA_TX_LANE2_REG_7_CSR_TXFFE_MODE32UI_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq23_tx_ln2_ffe_output_swizzle == SERDES_LANE_ANA_TX_LANE2_REG_7_CSR_TXFFE_OUTPUT_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq24_enable == SEQ24_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq24_rdwrb == SEQ24_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq24_static_field == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq24_tx_ln3_ffe_coeff_p2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq24_tx_ln3_ffe_coeff_p3 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq24_tx_ln3_ffe_coeff_p4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq24_tx_ln3_ffe_coeff_p5 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq25_enable == SEQ25_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq25_rdwrb == SEQ25_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq25_static_field == 23'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq25_tx_ln3_ffe_cmod == 9'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq26_enable == SEQ26_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq26_rdwrb == SEQ26_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq26_static_field == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq26_tx_ln3_ffe_coeff_0 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq26_tx_ln3_ffe_coeff_load == SERDES_LANE_ANA_TX_LANE3_REG_7_CSR_TXFFE_COEFF_LOAD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq26_tx_ln3_ffe_coeff_m1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq26_tx_ln3_ffe_coeff_m2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq26_tx_ln3_ffe_coeff_p1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq26_tx_ln3_ffe_mode32ui == SERDES_LANE_ANA_TX_LANE3_REG_7_CSR_TXFFE_MODE32UI_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq26_tx_ln3_ffe_output_swizzle == SERDES_LANE_ANA_TX_LANE3_REG_7_CSR_TXFFE_OUTPUT_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq27_enable == SEQ27_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq27_rdwrb == SEQ27_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq27_static_field == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq27_tx_ln0_ffe_coeff_0 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq27_tx_ln0_ffe_coeff_load == DYN_SERDES_LANE_ANA_TX_LANE0_REG_7_CSR_TXFFE_COEFF_LOAD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq27_tx_ln0_ffe_coeff_m1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq27_tx_ln0_ffe_coeff_m2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq27_tx_ln0_ffe_coeff_p1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq27_tx_ln0_ffe_mode32ui == DYN_SERDES_LANE_ANA_TX_LANE0_REG_7_CSR_TXFFE_MODE32UI_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq27_tx_ln0_ffe_output_swizzle == DYN_SERDES_LANE_ANA_TX_LANE0_REG_7_CSR_TXFFE_OUTPUT_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq28_enable == SEQ28_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq28_rdwrb == SEQ28_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq28_static_field == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq28_tx_ln1_ffe_coeff_0 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq28_tx_ln1_ffe_coeff_load == DYN_SERDES_LANE_ANA_TX_LANE1_REG_7_CSR_TXFFE_COEFF_LOAD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq28_tx_ln1_ffe_coeff_m1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq28_tx_ln1_ffe_coeff_m2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq28_tx_ln1_ffe_coeff_p1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq28_tx_ln1_ffe_mode32ui == DYN_SERDES_LANE_ANA_TX_LANE1_REG_7_CSR_TXFFE_MODE32UI_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq28_tx_ln1_ffe_output_swizzle == DYN_SERDES_LANE_ANA_TX_LANE1_REG_7_CSR_TXFFE_OUTPUT_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq29_enable == SEQ29_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq29_rdwrb == SEQ29_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq29_static_field == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq29_tx_ln2_ffe_coeff_0 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq29_tx_ln2_ffe_coeff_load == DYN_SERDES_LANE_ANA_TX_LANE2_REG_7_CSR_TXFFE_COEFF_LOAD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq29_tx_ln2_ffe_coeff_m1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq29_tx_ln2_ffe_coeff_m2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq29_tx_ln2_ffe_coeff_p1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq29_tx_ln2_ffe_mode32ui == DYN_SERDES_LANE_ANA_TX_LANE2_REG_7_CSR_TXFFE_MODE32UI_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq29_tx_ln2_ffe_output_swizzle == DYN_SERDES_LANE_ANA_TX_LANE2_REG_7_CSR_TXFFE_OUTPUT_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq2_cmn_pllb_fbdiv_frac == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq2_cmn_pllb_fbdiv_fracen == SERDES_SHIM_ANA_PLL_PLL_B_REG_1_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq2_cmn_pllb_fbdiv_intgr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq2_enable == SEQ2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq2_rdwrb == SEQ2_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq30_enable == SEQ30_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq30_rdwrb == SEQ30_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq30_static_field == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq30_tx_ln3_ffe_coeff_0 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq30_tx_ln3_ffe_coeff_load == DYN_SERDES_LANE_ANA_TX_LANE3_REG_7_CSR_TXFFE_COEFF_LOAD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq30_tx_ln3_ffe_coeff_m1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq30_tx_ln3_ffe_coeff_m2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq30_tx_ln3_ffe_coeff_p1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq30_tx_ln3_ffe_mode32ui == DYN_SERDES_LANE_ANA_TX_LANE3_REG_7_CSR_TXFFE_MODE32UI_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq30_tx_ln3_ffe_output_swizzle == DYN_SERDES_LANE_ANA_TX_LANE3_REG_7_CSR_TXFFE_OUTPUT_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq31_enable == SEQ31_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq31_rdwrb == SEQ31_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq32_enable == SEQ32_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq32_rdwrb == SEQ32_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq33_enable == SEQ33_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq33_rdwrb == SEQ33_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq34_enable == SEQ34_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq34_rdwrb == SEQ34_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq35_enable == SEQ35_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq35_rdwrb == SEQ35_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq36_enable == SEQ36_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq36_rdwrb == SEQ36_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq37_enable == SEQ37_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq37_rdwrb == SEQ37_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq38_enable == SEQ38_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq38_rdwrb == SEQ38_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq39_enable == SEQ39_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq39_rdwrb == SEQ39_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq3_enable == SEQ3_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq3_ln0_pll_fbdiv_frac == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq3_ln0_pll_fbdiv_fracen == SERDES_LANE_ANA_PLL_LANE0_REG_1_O_FRACNEN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq3_ln0_pll_fbdiv_intgr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq3_rdwrb == SEQ3_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq40_enable == SEQ40_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq40_rdwrb == SEQ40_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq41_enable == SEQ41_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq41_rdwrb == SEQ41_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq42_cbplla_en == SERDES_SHIM_COMMON_REG_13_ICOM_PLLA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq42_cbplla_rstb == SERDES_SHIM_COMMON_REG_13_ICOM_PLLA_RESETB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq42_enable == SEQ42_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq42_msb_static_field == 30'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq42_rdwrb == SEQ42_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq43_cbpllb_en == SERDES_SHIM_COMMON_REG_14_ICOM_PLLB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq43_cbpllb_rstb == SERDES_SHIM_COMMON_REG_14_ICOM_PLLB_RESETB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq43_enable == SEQ43_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq43_msb_static_field == 30'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq43_rdwrb == SEQ43_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq44_cbplls_status == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq44_enable == SEQ44_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq44_rdwrb == SEQ44_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq45_enable == SEQ45_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq45_msb_static_field == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq45_rdwrb == SEQ45_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq45_runstall == SERDES_SHIM_WRAP_CAR_REG_12_CFG_RUN_STALL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq46_bkrdy_status == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq46_enable == SEQ46_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq46_rdwrb == SEQ46_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq47_enable == SEQ47_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq47_lnx_fktfl_en == LNX_FKTFL_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq47_lnx_mode == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq47_lnx_msb_static_field == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq47_lnx_tfl_en == LNX_TFL_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq47_rdwrb == SEQ47_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq48_enable == SEQ48_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq48_lnxp1_fktfl_en == LNXP1_FKTFL_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq48_lnxp1_mode == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq48_lnxp1_msb_static_field == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq48_lnxp1_tfl_en == LNXP1_TFL_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq48_rdwrb == SEQ48_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq49_enable == SEQ49_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq49_lnxp2_fktfl_en == LNXP2_FKTFL_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq49_lnxp2_mode == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq49_lnxp2_msb_static_field == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq49_lnxp2_tfl_en == LNXP2_TFL_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq49_rdwrb == SEQ49_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq4_enable == SEQ4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq4_ln1_pll_fbdiv_frac == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq4_ln1_pll_fbdiv_fracen == SERDES_LANE_ANA_PLL_LANE1_REG_1_O_FRACNEN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq4_ln1_pll_fbdiv_intgr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq4_rdwrb == SEQ4_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq50_enable == SEQ50_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq50_lnxp3_fktfl_en == LNXP3_FKTFL_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq50_lnxp3_mode == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq50_lnxp3_msb_static_field == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq50_lnxp3_tfl_en == LNXP3_TFL_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq50_rdwrb == SEQ50_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq51_enable == SEQ51_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq51_lnxp4_fktfl_en == LNXP4_FKTFL_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq51_lnxp4_mode == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq51_lnxp4_msb_static_field == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq51_lnxp4_tfl_en == LNXP4_TFL_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq51_rdwrb == SEQ51_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq52_enable == SEQ52_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq52_lnxp5_fktfl_en == LNXP5_FKTFL_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq52_lnxp5_mode == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq52_lnxp5_msb_static_field == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq52_lnxp5_tfl_en == LNXP5_TFL_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq52_rdwrb == SEQ52_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq53_enable == SEQ53_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq53_rdwrb == SEQ53_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq54_enable == SEQ54_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq54_rdwrb == SEQ54_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq55_enable == SEQ55_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq55_ln0_rx2tx_lpbk_en == SERDES_LANE_LANE_CTRL_LANE0_REG_2_CFG_LANE_DIG_RX2TX_LOOPBACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq55_ln0_swl == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq55_ln0_tx_bus_take_dft == SERDES_LANE_LANE_CTRL_LANE0_REG_2_CFG_TX_BUS_TAKE_DFT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq55_ln0_tx_gry_lut == 8'd228
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq55_ln0_tx_inv == SERDES_LANE_LANE_CTRL_LANE0_REG_1_CFG_TX_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq55_ln0_tx_pre == SERDES_LANE_LANE_CTRL_LANE0_REG_2_CFG_TX_PRECODE_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq55_lsb_static_field == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq55_msb_static_field == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq55_rdwrb == SEQ55_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq56_enable == SEQ56_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq56_ln1_rx2tx_lpbk_en == SERDES_LANE_LANE_CTRL_LANE1_REG_2_CFG_LANE_DIG_RX2TX_LOOPBACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq56_ln1_swl == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq56_ln1_tx_bus_take_dft == SERDES_LANE_LANE_CTRL_LANE1_REG_2_CFG_TX_BUS_TAKE_DFT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq56_ln1_tx_gry_lut == 8'd228
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq56_ln1_tx_inv == SERDES_LANE_LANE_CTRL_LANE1_REG_1_CFG_TX_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq56_ln1_tx_pre == SERDES_LANE_LANE_CTRL_LANE1_REG_2_CFG_TX_PRECODE_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq56_lsb_static_field == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq56_msb_static_field == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq56_rdwrb == SEQ56_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq57_enable == SEQ57_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq57_ln2_rx2tx_lpbk_en == SERDES_LANE_LANE_CTRL_LANE2_REG_2_CFG_LANE_DIG_RX2TX_LOOPBACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq57_ln2_swl == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq57_ln2_tx_bus_take_dft == SERDES_LANE_LANE_CTRL_LANE2_REG_2_CFG_TX_BUS_TAKE_DFT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq57_ln2_tx_gry_lut == 8'd228
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq57_ln2_tx_inv == SERDES_LANE_LANE_CTRL_LANE2_REG_1_CFG_TX_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq57_ln2_tx_pre == SERDES_LANE_LANE_CTRL_LANE2_REG_2_CFG_TX_PRECODE_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq57_lsb_static_field == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq57_msb_static_field == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq57_rdwrb == SEQ57_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq58_enable == SEQ58_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq58_ln3_rx2tx_lpbk_en == SERDES_LANE_LANE_CTRL_LANE3_REG_2_CFG_LANE_DIG_RX2TX_LOOPBACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq58_ln3_swl == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq58_ln3_tx_bus_take_dft == SERDES_LANE_LANE_CTRL_LANE3_REG_2_CFG_TX_BUS_TAKE_DFT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq58_ln3_tx_gry_lut == 8'd228
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq58_ln3_tx_inv == SERDES_LANE_LANE_CTRL_LANE3_REG_1_CFG_TX_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq58_ln3_tx_pre == SERDES_LANE_LANE_CTRL_LANE3_REG_2_CFG_TX_PRECODE_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq58_lsb_static_field == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq58_msb_static_field == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq58_rdwrb == SEQ58_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq59_enable == SEQ59_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq59_rdwrb == SEQ59_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq5_enable == SEQ5_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq5_ln2_pll_fbdiv_frac == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq5_ln2_pll_fbdiv_fracen == SERDES_LANE_ANA_PLL_LANE2_REG_1_O_FRACNEN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq5_ln2_pll_fbdiv_intgr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq5_rdwrb == SEQ5_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq60_enable == SEQ60_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq60_rdwrb == SEQ60_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq61_enable == SEQ61_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq61_rdwrb == SEQ61_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq62_enable == SEQ62_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq62_rdwrb == SEQ62_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq63_enable == SEQ63_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq63_rdwrb == SEQ63_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq6_enable == SEQ6_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq6_ln3_pll_fbdiv_frac == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq6_ln3_pll_fbdiv_fracen == SERDES_LANE_ANA_PLL_LANE3_REG_1_O_FRACNEN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq6_ln3_pll_fbdiv_intgr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq6_rdwrb == SEQ6_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq7_enable == SEQ7_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq7_ln0_pll_refclk_sel == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq7_lsb_static_field == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq7_msb_static_field == 23'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq7_rdwrb == SEQ7_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq8_enable == SEQ8_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq8_ln1_pll_refclk_sel == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq8_lsb_static_field == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq8_msb_static_field == 23'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq8_rdwrb == SEQ8_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq9_enable == SEQ9_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq9_ln2_pll_refclk_sel == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq9_lsb_static_field == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq9_msb_static_field == 23'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_gdr_barak_quad_cfg_ctrl.u_gdr_barak_quad_avmm_cfgcsr.seq9_rdwrb == SEQ9_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_10_oct2sar2_sar18_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_10_oct2sar2_sar18_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_10_oct2sar3_sar26_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_10_oct2sar3_sar26_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_11_oct2sar4_sar34_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_11_oct2sar4_sar34_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_11_oct2sar5_sar42_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_11_oct2sar5_sar42_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_12_oct2sar6_sar50_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_12_oct2sar6_sar50_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_12_oct2sar7_sar58_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_12_oct2sar7_sar58_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_13_oct3sar0_sar3_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_13_oct3sar0_sar3_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_13_oct3sar1_sar11_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_13_oct3sar1_sar11_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_14_oct3sar2_sar19_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_14_oct3sar2_sar19_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_14_oct3sar3_sar27_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_14_oct3sar3_sar27_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_15_oct3sar4_sar35_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_15_oct3sar4_sar35_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_15_oct3sar5_sar43_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_15_oct3sar5_sar43_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_16_oct3sar6_sar51_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_16_oct3sar6_sar51_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_16_oct3sar7_sar59_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_16_oct3sar7_sar59_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_17_oct4sar0_sar4_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_17_oct4sar0_sar4_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_17_oct4sar1_sar12_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_17_oct4sar1_sar12_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_18_oct4sar2_sar20_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_18_oct4sar2_sar20_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_18_oct4sar3_sar28_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_18_oct4sar3_sar28_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_19_oct4sar4_sar36_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_19_oct4sar4_sar36_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_19_oct4sar5_sar44_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_19_oct4sar5_sar44_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_1_oct0sar0_sar0_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_1_oct0sar0_sar0_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_1_oct0sar1_sar8_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_1_oct0sar1_sar8_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_20_oct4sar6_sar52_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_20_oct4sar6_sar52_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_20_oct4sar7_sar60_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_20_oct4sar7_sar60_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_21_oct5sar0_sar5_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_21_oct5sar0_sar5_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_21_oct5sar1_sar13_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_21_oct5sar1_sar13_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_22_oct5sar2_sar21_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_22_oct5sar2_sar21_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_22_oct5sar3_sar29_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_22_oct5sar3_sar29_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_23_oct5sar4_sar37_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_23_oct5sar4_sar37_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_23_oct5sar5_sar45_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_23_oct5sar5_sar45_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_24_oct5sar6_sar53_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_24_oct5sar6_sar53_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_24_oct5sar7_sar61_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_24_oct5sar7_sar61_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_25_oct6sar0_sar6_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_25_oct6sar0_sar6_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_25_oct6sar1_sar14_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_25_oct6sar1_sar14_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_26_oct6sar2_sar22_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_26_oct6sar2_sar22_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_26_oct6sar3_sar30_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_26_oct6sar3_sar30_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_27_oct6sar4_sar38_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_27_oct6sar4_sar38_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_27_oct6sar5_sar46_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_27_oct6sar5_sar46_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_28_oct6sar6_sar54_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_28_oct6sar6_sar54_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_28_oct6sar7_sar62_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_28_oct6sar7_sar62_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_29_oct7sar0_sar7_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_29_oct7sar0_sar7_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_29_oct7sar1_sar15_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_29_oct7sar1_sar15_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_2_oct0sar2_sar16_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_2_oct0sar2_sar16_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_2_oct0sar3_sar24_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_2_oct0sar3_sar24_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_30_oct7sar2_sar23_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_30_oct7sar2_sar23_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_30_oct7sar3_sar31_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_30_oct7sar3_sar31_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_31_oct7sar4_sar39_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_31_oct7sar4_sar39_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_31_oct7sar5_sar47_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_31_oct7sar5_sar47_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_32_oct7sar6_sar55_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_32_oct7sar6_sar55_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_32_oct7sar7_sar63_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_32_oct7sar7_sar63_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_33_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_33_oct0sar2_sar16_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_33_OCT0SAR2_SAR16_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_33_oct0sar2_sar16_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_33_oct0sar2_sar16_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_33_OCT0SAR2_SAR16_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_33_oct0sar3_sar24_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_33_OCT0SAR3_SAR24_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_33_oct0sar3_sar24_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_33_oct0sar3_sar24_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_33_OCT0SAR3_SAR24_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_33_oct0sar4_sar32_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_33_OCT0SAR4_SAR32_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_33_oct0sar4_sar32_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_33_oct0sar4_sar32_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_33_OCT0SAR4_SAR32_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_33_oct0sar5_sar40_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_33_OCT0SAR5_SAR40_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_33_oct0sar5_sar40_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_33_oct0sar5_sar40_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_33_OCT0SAR5_SAR40_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_34_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_34_oct0sar0_sar0_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_34_OCT0SAR0_SAR0_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_34_oct0sar0_sar0_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_34_oct0sar0_sar0_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_34_OCT0SAR0_SAR0_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_34_oct0sar1_sar8_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_34_OCT0SAR1_SAR8_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_34_oct0sar1_sar8_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_34_oct0sar1_sar8_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_34_OCT0SAR1_SAR8_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_34_oct0sar6_sar48_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_34_OCT0SAR6_SAR48_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_34_oct0sar6_sar48_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_34_oct0sar6_sar48_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_34_OCT0SAR6_SAR48_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_34_oct0sar7_sar56_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_34_OCT0SAR7_SAR56_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_34_oct0sar7_sar56_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_34_oct0sar7_sar56_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_34_OCT0SAR7_SAR56_SHRG_INIT_VAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_35_bonus_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_35_glb_div33_en_fw_attr == SERDES_LANE_ANA_ADC_LANE0_REG_35_GLB_DIV33_EN_FW_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_35_oct1sar2_sar17_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_35_OCT1SAR2_SAR17_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_35_oct1sar2_sar17_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_35_oct1sar2_sar17_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_35_OCT1SAR2_SAR17_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_35_oct1sar3_sar25_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_35_OCT1SAR3_SAR25_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_35_oct1sar3_sar25_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_35_oct1sar3_sar25_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_35_OCT1SAR3_SAR25_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_35_oct1sar4_sar33_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_35_OCT1SAR4_SAR33_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_35_oct1sar4_sar33_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_35_oct1sar4_sar33_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_35_OCT1SAR4_SAR33_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_35_oct1sar5_sar41_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_35_OCT1SAR5_SAR41_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_35_oct1sar5_sar41_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_35_oct1sar5_sar41_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_35_OCT1SAR5_SAR41_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_36_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_36_oct1sar0_sar1_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_36_OCT1SAR0_SAR1_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_36_oct1sar0_sar1_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_36_oct1sar0_sar1_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_36_OCT1SAR0_SAR1_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_36_oct1sar1_sar9_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_36_OCT1SAR1_SAR9_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_36_oct1sar1_sar9_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_36_oct1sar1_sar9_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_36_OCT1SAR1_SAR9_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_36_oct1sar6_sar49_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_36_OCT1SAR6_SAR49_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_36_oct1sar6_sar49_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_36_oct1sar6_sar49_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_36_OCT1SAR6_SAR49_SHRG_INIT_VAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_36_oct1sar7_sar57_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_36_OCT1SAR7_SAR57_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_36_oct1sar7_sar57_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_36_oct1sar7_sar57_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_36_OCT1SAR7_SAR57_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_37_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_37_oct2sar2_sar18_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_37_OCT2SAR2_SAR18_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_37_oct2sar2_sar18_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_37_oct2sar2_sar18_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_37_OCT2SAR2_SAR18_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_37_oct2sar3_sar26_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_37_OCT2SAR3_SAR26_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_37_oct2sar3_sar26_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_37_oct2sar3_sar26_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_37_OCT2SAR3_SAR26_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_37_oct2sar4_sar34_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_37_OCT2SAR4_SAR34_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_37_oct2sar4_sar34_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_37_oct2sar4_sar34_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_37_OCT2SAR4_SAR34_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_37_oct2sar5_sar42_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_37_OCT2SAR5_SAR42_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_37_oct2sar5_sar42_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_37_oct2sar5_sar42_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_37_OCT2SAR5_SAR42_SHRG_INIT_VAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_38_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_38_oct2sar0_sar2_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_38_OCT2SAR0_SAR2_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_38_oct2sar0_sar2_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_38_oct2sar0_sar2_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_38_OCT2SAR0_SAR2_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_38_oct2sar1_sar10_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_38_OCT2SAR1_SAR10_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_38_oct2sar1_sar10_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_38_oct2sar1_sar10_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_38_OCT2SAR1_SAR10_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_38_oct2sar6_sar50_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_38_OCT2SAR6_SAR50_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_38_oct2sar6_sar50_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_38_oct2sar6_sar50_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_38_OCT2SAR6_SAR50_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_38_oct2sar7_sar58_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_38_OCT2SAR7_SAR58_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_38_oct2sar7_sar58_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_38_oct2sar7_sar58_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_38_OCT2SAR7_SAR58_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_39_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_39_oct3sar2_sar19_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_39_OCT3SAR2_SAR19_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_39_oct3sar2_sar19_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_39_oct3sar2_sar19_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_39_OCT3SAR2_SAR19_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_39_oct3sar3_sar27_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_39_OCT3SAR3_SAR27_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_39_oct3sar3_sar27_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_39_oct3sar3_sar27_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_39_OCT3SAR3_SAR27_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_39_oct3sar4_sar35_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_39_OCT3SAR4_SAR35_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_39_oct3sar4_sar35_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_39_oct3sar4_sar35_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_39_OCT3SAR4_SAR35_SHRG_INIT_VAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_39_oct3sar5_sar43_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_39_OCT3SAR5_SAR43_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_39_oct3sar5_sar43_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_39_oct3sar5_sar43_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_39_OCT3SAR5_SAR43_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_3_oct0sar4_sar32_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_3_oct0sar4_sar32_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_3_oct0sar5_sar40_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_3_oct0sar5_sar40_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_40_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_40_oct3sar0_sar3_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_40_OCT3SAR0_SAR3_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_40_oct3sar0_sar3_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_40_oct3sar0_sar3_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_40_OCT3SAR0_SAR3_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_40_oct3sar1_sar11_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_40_OCT3SAR1_SAR11_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_40_oct3sar1_sar11_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_40_oct3sar1_sar11_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_40_OCT3SAR1_SAR11_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_40_oct3sar6_sar51_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_40_OCT3SAR6_SAR51_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_40_oct3sar6_sar51_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_40_oct3sar6_sar51_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_40_OCT3SAR6_SAR51_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_40_oct3sar7_sar59_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_40_OCT3SAR7_SAR59_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_40_oct3sar7_sar59_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_40_oct3sar7_sar59_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_40_OCT3SAR7_SAR59_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_41_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_41_oct4sar2_sar20_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_41_OCT4SAR2_SAR20_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_41_oct4sar2_sar20_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_41_oct4sar2_sar20_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_41_OCT4SAR2_SAR20_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_41_oct4sar3_sar28_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_41_OCT4SAR3_SAR28_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_41_oct4sar3_sar28_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_41_oct4sar3_sar28_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_41_OCT4SAR3_SAR28_SHRG_INIT_VAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_41_oct4sar4_sar36_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_41_OCT4SAR4_SAR36_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_41_oct4sar4_sar36_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_41_oct4sar4_sar36_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_41_OCT4SAR4_SAR36_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_41_oct4sar5_sar44_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_41_OCT4SAR5_SAR44_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_41_oct4sar5_sar44_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_41_oct4sar5_sar44_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_41_OCT4SAR5_SAR44_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_42_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_42_oct4sar0_sar4_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_42_OCT4SAR0_SAR4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_42_oct4sar0_sar4_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_42_oct4sar0_sar4_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_42_OCT4SAR0_SAR4_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_42_oct4sar1_sar12_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_42_OCT4SAR1_SAR12_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_42_oct4sar1_sar12_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_42_oct4sar1_sar12_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_42_OCT4SAR1_SAR12_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_42_oct4sar6_sar52_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_42_OCT4SAR6_SAR52_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_42_oct4sar6_sar52_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_42_oct4sar6_sar52_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_42_OCT4SAR6_SAR52_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_42_oct4sar7_sar60_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_42_OCT4SAR7_SAR60_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_42_oct4sar7_sar60_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_42_oct4sar7_sar60_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_42_OCT4SAR7_SAR60_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_43_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_43_oct5sar2_sar21_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_43_OCT5SAR2_SAR21_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_43_oct5sar2_sar21_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_43_oct5sar2_sar21_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_43_OCT5SAR2_SAR21_SHRG_INIT_VAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_43_oct5sar3_sar29_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_43_OCT5SAR3_SAR29_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_43_oct5sar3_sar29_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_43_oct5sar3_sar29_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_43_OCT5SAR3_SAR29_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_43_oct5sar4_sar37_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_43_OCT5SAR4_SAR37_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_43_oct5sar4_sar37_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_43_oct5sar4_sar37_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_43_OCT5SAR4_SAR37_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_43_oct5sar5_sar45_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_43_OCT5SAR5_SAR45_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_43_oct5sar5_sar45_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_43_oct5sar5_sar45_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_43_OCT5SAR5_SAR45_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_44_glb_div10_en_fw_attr == SERDES_LANE_ANA_ADC_LANE0_REG_44_GLB_DIV10_EN_FW_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_44_glb_div33_frac0p25_fw_attr == SERDES_LANE_ANA_ADC_LANE0_REG_44_GLB_DIV33_FRAC0P25_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_44_glb_div33_frac0p5_fw_attr == SERDES_LANE_ANA_ADC_LANE0_REG_44_GLB_DIV33_FRAC0P5_FW_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_44_glb_div33_ratio_fw_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_44_oct5sar0_sar5_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_44_OCT5SAR0_SAR5_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_44_oct5sar0_sar5_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_44_oct5sar0_sar5_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_44_OCT5SAR0_SAR5_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_44_oct5sar1_sar13_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_44_OCT5SAR1_SAR13_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_44_oct5sar1_sar13_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_44_oct5sar1_sar13_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_44_OCT5SAR1_SAR13_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_44_oct5sar6_sar53_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_44_OCT5SAR6_SAR53_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_44_oct5sar6_sar53_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_44_oct5sar6_sar53_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_44_OCT5SAR6_SAR53_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_44_oct5sar7_sar61_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_44_OCT5SAR7_SAR61_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_44_oct5sar7_sar61_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_44_oct5sar7_sar61_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_44_OCT5SAR7_SAR61_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_45_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_45_oct6sar2_sar22_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_45_OCT6SAR2_SAR22_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_45_oct6sar2_sar22_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_45_oct6sar2_sar22_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_45_OCT6SAR2_SAR22_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_45_oct6sar3_sar30_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_45_OCT6SAR3_SAR30_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_45_oct6sar3_sar30_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_45_oct6sar3_sar30_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_45_OCT6SAR3_SAR30_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_45_oct6sar4_sar38_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_45_OCT6SAR4_SAR38_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_45_oct6sar4_sar38_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_45_oct6sar4_sar38_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_45_OCT6SAR4_SAR38_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_45_oct6sar5_sar46_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_45_OCT6SAR5_SAR46_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_45_oct6sar5_sar46_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_45_oct6sar5_sar46_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_45_OCT6SAR5_SAR46_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_46_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_46_oct6sar0_sar6_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_46_OCT6SAR0_SAR6_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_46_oct6sar0_sar6_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_46_oct6sar0_sar6_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_46_OCT6SAR0_SAR6_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_46_oct6sar1_sar14_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_46_OCT6SAR1_SAR14_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_46_oct6sar1_sar14_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_46_oct6sar1_sar14_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_46_OCT6SAR1_SAR14_SHRG_INIT_VAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_46_oct6sar6_sar54_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_46_OCT6SAR6_SAR54_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_46_oct6sar6_sar54_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_46_oct6sar6_sar54_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_46_OCT6SAR6_SAR54_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_46_oct6sar7_sar62_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_46_OCT6SAR7_SAR62_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_46_oct6sar7_sar62_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_46_oct6sar7_sar62_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_46_OCT6SAR7_SAR62_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_47_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_47_oct7sar2_sar23_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_47_OCT7SAR2_SAR23_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_47_oct7sar2_sar23_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_47_oct7sar2_sar23_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_47_OCT7SAR2_SAR23_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_47_oct7sar3_sar31_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_47_OCT7SAR3_SAR31_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_47_oct7sar3_sar31_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_47_oct7sar3_sar31_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_47_OCT7SAR3_SAR31_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_47_oct7sar4_sar39_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_47_OCT7SAR4_SAR39_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_47_oct7sar4_sar39_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_47_oct7sar4_sar39_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_47_OCT7SAR4_SAR39_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_47_oct7sar5_sar47_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_47_OCT7SAR5_SAR47_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_47_oct7sar5_sar47_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_47_oct7sar5_sar47_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_47_OCT7SAR5_SAR47_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_48_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_48_oct7sar0_sar7_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_48_OCT7SAR0_SAR7_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_48_oct7sar0_sar7_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_48_oct7sar0_sar7_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_48_OCT7SAR0_SAR7_SHRG_INIT_VAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_48_oct7sar1_sar15_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_48_OCT7SAR1_SAR15_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_48_oct7sar1_sar15_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_48_oct7sar1_sar15_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_48_OCT7SAR1_SAR15_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_48_oct7sar6_sar55_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_48_OCT7SAR6_SAR55_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_48_oct7sar6_sar55_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_48_oct7sar6_sar55_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_48_OCT7SAR6_SAR55_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_48_oct7sar7_sar63_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_48_OCT7SAR7_SAR63_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_48_oct7sar7_sar63_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_48_oct7sar7_sar63_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE0_REG_48_OCT7SAR7_SAR63_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_49_dac_clear_dis_attr == SERDES_LANE_ANA_ADC_LANE0_REG_49_DAC_CLEAR_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_49_dac_clear_force_dfx_attr == SERDES_LANE_ANA_ADC_LANE0_REG_49_DAC_CLEAR_FORCE_DFX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_49_dac_reset_force_dfx_attr == SERDES_LANE_ANA_ADC_LANE0_REG_49_DAC_RESET_FORCE_DFX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_49_i_sar_finish_disable_fw_attr == SERDES_LANE_ANA_ADC_LANE0_REG_49_I_SAR_FINISH_DISABLE_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_49_nob_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_49_osc_speed_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_49_refgen_cm_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_49_refgen_dfx_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_49_rstb_attr == SERDES_LANE_ANA_ADC_LANE0_REG_49_RSTB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_49_sar_array_spare_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_49_th2_bypass_attr == SERDES_LANE_ANA_ADC_LANE0_REG_49_TH2_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_49_th_boost_select_attr == SERDES_LANE_ANA_ADC_LANE0_REG_49_TH_BOOST_SELECT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_4_oct0sar6_sar48_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_4_oct0sar6_sar48_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_4_oct0sar7_sar56_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_4_oct0sar7_sar56_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_50_shrg_align_clk2cdrrst_val_attr == 8'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_50_shrg_align_clk2lgcrst_val_attr == 8'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_50_shrg_align_clkrst_val_attr == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_51_current_control_15pc_ctl1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_51_current_control_15pc_ctl2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_51_current_control_3_ctl2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_51_current_control_7_ctl1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_51_o_25pc_ctl_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_51_o_current_base_dis_attr == SERDES_LANE_ANA_ADC_LANE0_REG_51_O_CURRENT_BASE_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_51_o_dcmon_vbpn_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_51_O_DCMON_VBPN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_51_o_dcmon_vref0_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_51_O_DCMON_VREF0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_51_o_dcmon_vref_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_51_O_DCMON_VREF_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_51_o_dcmonp_vref_inp_attr == SERDES_LANE_ANA_ADC_LANE0_REG_51_O_DCMONP_VREF_INP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_51_o_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_51_O_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_51_res_ref_ladder_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_52_current_control_15pc_ctl1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_52_current_control_15pc_ctl2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_52_current_control_3_ctl2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_52_current_control_7_ctl1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_52_o_25pc_ctl_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_52_o_current_base_dis_attr == SERDES_LANE_ANA_ADC_LANE0_REG_52_O_CURRENT_BASE_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_52_o_dcmon_vbpn_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_52_O_DCMON_VBPN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_52_o_dcmon_vref0_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_52_O_DCMON_VREF0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_52_o_dcmon_vref_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_52_O_DCMON_VREF_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_52_o_dcmonp_vref_inp_attr == SERDES_LANE_ANA_ADC_LANE0_REG_52_O_DCMONP_VREF_INP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_52_o_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_52_O_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_52_res_ref_ladder_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_53_current_control_15pc_ctl1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_53_current_control_15pc_ctl2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_53_current_control_3_ctl2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_53_current_control_7_ctl1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_53_o_25pc_ctl_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_53_o_current_base_dis_attr == SERDES_LANE_ANA_ADC_LANE0_REG_53_O_CURRENT_BASE_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_53_o_dcmon_vbpn_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_53_O_DCMON_VBPN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_53_o_dcmon_vref0_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_53_O_DCMON_VREF0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_53_o_dcmon_vref_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_53_O_DCMON_VREF_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_53_o_dcmonp_vref_inp_attr == SERDES_LANE_ANA_ADC_LANE0_REG_53_O_DCMONP_VREF_INP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_53_o_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_53_O_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_53_res_ref_ladder_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_54_current_control_15pc_ctl1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_54_current_control_15pc_ctl2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_54_current_control_3_ctl2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_54_current_control_7_ctl1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_54_o_25pc_ctl_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_54_o_current_base_dis_attr == SERDES_LANE_ANA_ADC_LANE0_REG_54_O_CURRENT_BASE_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_54_o_dcmon_vbpn_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_54_O_DCMON_VBPN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_54_o_dcmon_vref0_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_54_O_DCMON_VREF0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_54_o_dcmon_vref_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_54_O_DCMON_VREF_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_54_o_dcmonp_vref_inp_attr == SERDES_LANE_ANA_ADC_LANE0_REG_54_O_DCMONP_VREF_INP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_54_o_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_54_O_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_54_res_ref_ladder_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_55_current_control_15pc_ctl1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_55_current_control_15pc_ctl2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_55_current_control_3_ctl2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_55_current_control_7_ctl1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_55_o_25pc_ctl_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_55_o_current_base_dis_attr == SERDES_LANE_ANA_ADC_LANE0_REG_55_O_CURRENT_BASE_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_55_o_dcmon_vbpn_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_55_O_DCMON_VBPN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_55_o_dcmon_vref0_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_55_O_DCMON_VREF0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_55_o_dcmon_vref_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_55_O_DCMON_VREF_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_55_o_dcmonp_vref_inp_attr == SERDES_LANE_ANA_ADC_LANE0_REG_55_O_DCMONP_VREF_INP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_55_o_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_55_O_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_55_res_ref_ladder_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_56_current_control_15pc_ctl1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_56_current_control_15pc_ctl2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_56_current_control_3_ctl2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_56_current_control_7_ctl1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_56_o_25pc_ctl_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_56_o_current_base_dis_attr == SERDES_LANE_ANA_ADC_LANE0_REG_56_O_CURRENT_BASE_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_56_o_dcmon_vbpn_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_56_O_DCMON_VBPN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_56_o_dcmon_vref0_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_56_O_DCMON_VREF0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_56_o_dcmon_vref_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_56_O_DCMON_VREF_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_56_o_dcmonp_vref_inp_attr == SERDES_LANE_ANA_ADC_LANE0_REG_56_O_DCMONP_VREF_INP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_56_o_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_56_O_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_56_res_ref_ladder_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_57_current_control_15pc_ctl1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_57_current_control_15pc_ctl2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_57_current_control_3_ctl2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_57_current_control_7_ctl1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_57_o_25pc_ctl_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_57_o_current_base_dis_attr == SERDES_LANE_ANA_ADC_LANE0_REG_57_O_CURRENT_BASE_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_57_o_dcmon_vbpn_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_57_O_DCMON_VBPN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_57_o_dcmon_vref0_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_57_O_DCMON_VREF0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_57_o_dcmon_vref_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_57_O_DCMON_VREF_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_57_o_dcmonp_vref_inp_attr == SERDES_LANE_ANA_ADC_LANE0_REG_57_O_DCMONP_VREF_INP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_57_o_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_57_O_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_57_res_ref_ladder_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_58_current_control_15pc_ctl1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_58_current_control_15pc_ctl2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_58_current_control_3_ctl2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_58_current_control_7_ctl1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_58_o_25pc_ctl_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_58_o_current_base_dis_attr == SERDES_LANE_ANA_ADC_LANE0_REG_58_O_CURRENT_BASE_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_58_o_dcmon_vbpn_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_58_O_DCMON_VBPN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_58_o_dcmon_vref0_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_58_O_DCMON_VREF0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_58_o_dcmon_vref_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_58_O_DCMON_VREF_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_58_o_dcmonp_vref_inp_attr == SERDES_LANE_ANA_ADC_LANE0_REG_58_O_DCMONP_VREF_INP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_58_o_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_58_O_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_58_res_ref_ladder_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_59_i_psf_cur_trim_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_59_i_psf_cur_trim_spare_attr == SERDES_LANE_ANA_ADC_LANE0_REG_59_I_PSF_CUR_TRIM_SPARE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_59_psf_bias_current_mon_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_59_PSF_BIAS_CURRENT_MON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_59_psf_cm_ctrl_reserved_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_59_psf_dcmon_spare1_attr == SERDES_LANE_ANA_ADC_LANE0_REG_59_PSF_DCMON_SPARE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_59_psf_dcmon_spare2_attr == SERDES_LANE_ANA_ADC_LANE0_REG_59_PSF_DCMON_SPARE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_59_psf_dcmon_spare3_attr == SERDES_LANE_ANA_ADC_LANE0_REG_59_PSF_DCMON_SPARE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_59_psf_dfx_int_out_mon_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_59_PSF_DFX_INT_OUT_MON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_59_psf_integrator_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_59_PSF_INTEGRATOR_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_59_psf_pbias_cas_mon_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_59_PSF_PBIAS_CAS_MON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_59_psf_vref_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_59_PSF_VREF_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_59_th0_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_59_TH0_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_59_th1_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_59_TH1_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_59_th2_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_59_TH2_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_59_th3_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_59_TH3_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_59_th4_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_59_TH4_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_59_th5_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_59_TH5_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_59_th6_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_59_TH6_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_59_th7_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_59_TH7_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_59_th_sw_bypass_attr == SERDES_LANE_ANA_ADC_LANE0_REG_59_TH_SW_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_5_oct1sar0_sar1_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_5_oct1sar0_sar1_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_5_oct1sar1_sar9_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_5_oct1sar1_sar9_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_60_th0_cur_trim_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_60_th1_cur_trim_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_60_th2_cur_trim_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_60_th3_cur_trim_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_60_th4_cur_trim_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_60_th5_cur_trim_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_60_th6_cur_trim_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_60_th7_cur_trim_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_61_th0_psf_ofc_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_61_th1_psf_ofc_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_61_th2_psf_ofc_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_61_th3_psf_ofc_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_61_th4_psf_ofc_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_61_th5_psf_ofc_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_61_th6_psf_ofc_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_61_th7_psf_ofc_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_62_bonus_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_62_dfx_en_mon_attr == SERDES_LANE_ANA_ADC_LANE0_REG_62_DFX_EN_MON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_62_dfx_en_slc_attr == SERDES_LANE_ANA_ADC_LANE0_REG_62_DFX_EN_SLC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_62_th0_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_62_TH0_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_62_th1_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_62_TH1_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_62_th2_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_62_TH2_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_62_th3_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_62_TH3_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_62_th4_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_62_TH4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_62_th5_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_62_TH5_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_62_th6_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_62_TH6_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_62_th7_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_62_TH7_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_62_th_bias_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_62_TH_BIAS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_63_bonus_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_63_sar_dfx_en_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_64_ch4_pi_code_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_64_ch5_pi_code_attr == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_64_ch6_pi_code_attr == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_64_ch7_pi_code_attr == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_65_ch0_pi_code_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_65_ch1_pi_code_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_65_ch2_pi_code_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_65_ch3_pi_code_attr == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_66_c2c_en_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_66_ch0_pi_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_66_CH0_PI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_66_ch0_pi_transp_in_attr == SERDES_LANE_ANA_ADC_LANE0_REG_66_CH0_PI_TRANSP_IN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_66_ch1_pi_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_66_CH1_PI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_66_ch1_pi_transp_in_attr == SERDES_LANE_ANA_ADC_LANE0_REG_66_CH1_PI_TRANSP_IN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_66_ch2_pi_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_66_CH2_PI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_66_ch2_pi_transp_in_attr == SERDES_LANE_ANA_ADC_LANE0_REG_66_CH2_PI_TRANSP_IN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_66_ch3_pi_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_66_CH3_PI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_66_ch3_pi_transp_in_attr == SERDES_LANE_ANA_ADC_LANE0_REG_66_CH3_PI_TRANSP_IN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_66_ch4_pi_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_66_CH4_PI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_66_ch4_pi_transp_in_attr == SERDES_LANE_ANA_ADC_LANE0_REG_66_CH4_PI_TRANSP_IN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_66_ch5_pi_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_66_CH5_PI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_66_ch5_pi_transp_in_attr == SERDES_LANE_ANA_ADC_LANE0_REG_66_CH5_PI_TRANSP_IN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_66_ch6_pi_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_66_CH6_PI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_66_ch6_pi_transp_in_attr == SERDES_LANE_ANA_ADC_LANE0_REG_66_CH6_PI_TRANSP_IN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_66_ch7_pi_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_66_CH7_PI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_66_ch7_pi_transp_in_attr == SERDES_LANE_ANA_ADC_LANE0_REG_66_CH7_PI_TRANSP_IN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_67_dispolarity_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_67_i_clkmux_ungate_req_reg_attr == SERDES_LANE_ANA_ADC_LANE0_REG_67_I_CLKMUX_UNGATE_REQ_REG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_67_i_clkmux_ungate_rst_reg_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_67_spare_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_67_td_degen_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_68_clk2td_ch_sel_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_68_pdo_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_68_PDO_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_68_spare_attr == SERDES_LANE_ANA_ADC_LANE0_REG_68_SPARE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_68_td_en_pd_attr == SERDES_LANE_ANA_ADC_LANE0_REG_68_TD_EN_PD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_68_td_i_ctrl_2ui_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_68_td_i_ctrl_4ui_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_68_td_i_sel_count_stop_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_68_td_rstb_attr == SERDES_LANE_ANA_ADC_LANE0_REG_68_TD_RSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_69_dcmon_cmp_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_69_dcmon_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_69_input_cs_trimming_attr == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_69_nc_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_69_nsf_enable_attr == SERDES_LANE_ANA_ADC_LANE0_REG_69_NSF_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_69_nsf_even_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_69_NSF_EVEN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_69_nsf_odd_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_69_NSF_ODD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_6_oct1sar2_sar17_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_6_oct1sar2_sar17_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_6_oct1sar3_sar25_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_6_oct1sar3_sar25_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_70_i_clkmux_hsmonsel_local_reg_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_70_i_clkmux_hsmonsel_next_reg_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_70_i_clkmux_hsmonseln_reg_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_70_i_clkmux_hsmonselp_reg_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_70_ph_out_seln_attr == SERDES_LANE_ANA_ADC_LANE0_REG_70_PH_OUT_SELN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_71_clk_gen_dcmon_n_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_71_CLK_GEN_DCMON_N_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_71_clk_gen_dcmon_p_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_71_CLK_GEN_DCMON_P_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_71_clkgen_and_sar_l_comp_n_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_71_CLKGEN_AND_SAR_L_COMP_N_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_71_clkgen_and_sar_l_comp_p_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_71_CLKGEN_AND_SAR_L_COMP_P_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_71_clkgen_and_sar_l_dcmon_n_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_71_CLKGEN_AND_SAR_L_DCMON_N_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_71_clkgen_and_sar_l_dcmon_p_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_71_CLKGEN_AND_SAR_L_DCMON_P_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_71_i_sararray_vref_n_attr == SERDES_LANE_ANA_ADC_LANE0_REG_71_I_SARARRAY_VREF_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_71_i_sararray_vref_p_attr == SERDES_LANE_ANA_ADC_LANE0_REG_71_I_SARARRAY_VREF_P_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_71_nsf_th_clkmux_comp_n_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_71_NSF_TH_CLKMUX_COMP_N_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_71_nsf_th_clkmux_comp_p_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_71_NSF_TH_CLKMUX_COMP_P_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_71_nsf_th_clkmux_dcmon_n_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_71_NSF_TH_CLKMUX_DCMON_N_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_71_nsf_th_clkmux_dcmon_p_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_71_NSF_TH_CLKMUX_DCMON_P_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_71_o_sar_dft_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_71_oct3_dfx_en_l_attr == SERDES_LANE_ANA_ADC_LANE0_REG_71_OCT3_DFX_EN_L_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_71_oct3_dfx_en_r_attr == SERDES_LANE_ANA_ADC_LANE0_REG_71_OCT3_DFX_EN_R_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_71_oct7_dfx_en_l_attr == SERDES_LANE_ANA_ADC_LANE0_REG_71_OCT7_DFX_EN_L_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_71_oct7_dfx_en_r_attr == SERDES_LANE_ANA_ADC_LANE0_REG_71_OCT7_DFX_EN_R_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_71_spare_dfx_left_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_72_dcmon2slc_attr == SERDES_LANE_ANA_ADC_LANE0_REG_72_DCMON2SLC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_72_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_72_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_72_dcmon_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_72_ph_out_selp_attr == SERDES_LANE_ANA_ADC_LANE0_REG_72_PH_OUT_SELP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_72_spare_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_73_clkgen_comp_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_73_CLKGEN_COMP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_73_o_sar_dft_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_73_oct0_dfx_en_l_attr == SERDES_LANE_ANA_ADC_LANE0_REG_73_OCT0_DFX_EN_L_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_73_oct0_dfx_en_r_attr == SERDES_LANE_ANA_ADC_LANE0_REG_73_OCT0_DFX_EN_R_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_73_oct2_dfx_en_l_attr == SERDES_LANE_ANA_ADC_LANE0_REG_73_OCT2_DFX_EN_L_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_73_oct2_dfx_en_r_attr == SERDES_LANE_ANA_ADC_LANE0_REG_73_OCT2_DFX_EN_R_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_73_oct4_dfx_en_l_attr == SERDES_LANE_ANA_ADC_LANE0_REG_73_OCT4_DFX_EN_L_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_73_oct4_dfx_en_r_attr == SERDES_LANE_ANA_ADC_LANE0_REG_73_OCT4_DFX_EN_R_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_73_oct6_dfx_en_l_attr == SERDES_LANE_ANA_ADC_LANE0_REG_73_OCT6_DFX_EN_L_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_73_sar_r_comp_n_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_73_SAR_R_COMP_N_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_73_sar_r_comp_p_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_73_SAR_R_COMP_P_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_73_sar_r_dcmon_n_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_73_SAR_R_DCMON_N_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_73_sar_r_dcmon_p_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_73_SAR_R_DCMON_P_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_73_spare_dfx_right_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_74_fall_sel3_attr == 7'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_74_fall_sel5_attr == 7'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_74_fall_sel7_attr == 7'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_74_spare1_reg13_attr == SERDES_LANE_ANA_ADC_LANE0_REG_74_SPARE1_REG13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_74_spare2_reg13_attr == SERDES_LANE_ANA_ADC_LANE0_REG_74_SPARE2_REG13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_74_spare3_reg13_attr == SERDES_LANE_ANA_ADC_LANE0_REG_74_SPARE3_REG13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_75_rise_sel0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_75_rise_sel1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_75_rise_sel2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_75_rise_sel3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_76_spare_reg1_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_77_dfx_seln_attr == 17'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_77_spare1_reg2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_77_spare2_reg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_78_dfx_selp_attr == 17'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_78_spare_reg03_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_79_rise_sel4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_79_rise_sel5_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_79_rise_sel6_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_79_rise_sel7_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_7_oct1sar4_sar33_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_7_oct1sar4_sar33_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_7_oct1sar5_sar41_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_7_oct1sar5_sar41_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_80_c2c_en_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_80_clk_sel_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_80_counter_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_80_COUNTER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_80_dcd_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_80_DCD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_80_dcd_sel_attr == SERDES_LANE_ANA_ADC_LANE0_REG_80_DCD_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_80_dfx_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_80_DFX_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_80_en_dfx_attr == SERDES_LANE_ANA_ADC_LANE0_REG_80_EN_DFX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_80_spare5_reg5_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_81_buffer_bias0_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_81_buffer_bias_dfx_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_81_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_81_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_81_sel_c2c_cascode_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_81_sel_c2c_dc_coarse_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_81_sel_c2c_global_i_attr == 7'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_81_spare_reg6_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_82_bw_sel0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_82_i_a2f_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_82_I_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_82_i_dfx_a2f_boost_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_82_I_DFX_A2F_BOOST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_82_idfx_sel_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_82_sel_cgm_en_attr == SERDES_LANE_ANA_ADC_LANE0_REG_82_SEL_CGM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_82_spare_reg07_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_83_bw_sel1_attr == 15'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_83_res_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_83_spare_reg08_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_84_bw_sel2_attr == 15'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_84_clk_2ui_sel_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_84_spare_reg09_attr == SERDES_LANE_ANA_ADC_LANE0_REG_84_SPARE_REG09_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_85_bw_sel3_attr == 15'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_85_spare_reg10_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_86_fall_sel0_attr == 7'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_86_fall_sel1_attr == 7'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_86_spare1_reg11_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_86_spare2_reg11_attr == SERDES_LANE_ANA_ADC_LANE0_REG_86_SPARE2_REG11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_87_fall_sel2_attr == 7'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_87_fall_sel4_attr == 7'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_87_fall_sel6_attr == 7'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_87_spare1_reg12_attr == SERDES_LANE_ANA_ADC_LANE0_REG_87_SPARE1_REG12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_87_spare2_reg12_attr == SERDES_LANE_ANA_ADC_LANE0_REG_87_SPARE2_REG12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_87_spare3_reg12_attr == SERDES_LANE_ANA_ADC_LANE0_REG_87_SPARE3_REG12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_8_oct1sar6_sar49_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_8_oct1sar6_sar49_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_8_oct1sar7_sar57_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_8_oct1sar7_sar57_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_9_oct2sar0_sar2_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_9_oct2sar0_sar2_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_9_oct2sar1_sar10_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane0_reg_9_oct2sar1_sar10_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_10_oct2sar2_sar18_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_10_oct2sar2_sar18_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_10_oct2sar3_sar26_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_10_oct2sar3_sar26_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_11_oct2sar4_sar34_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_11_oct2sar4_sar34_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_11_oct2sar5_sar42_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_11_oct2sar5_sar42_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_12_oct2sar6_sar50_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_12_oct2sar6_sar50_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_12_oct2sar7_sar58_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_12_oct2sar7_sar58_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_13_oct3sar0_sar3_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_13_oct3sar0_sar3_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_13_oct3sar1_sar11_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_13_oct3sar1_sar11_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_14_oct3sar2_sar19_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_14_oct3sar2_sar19_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_14_oct3sar3_sar27_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_14_oct3sar3_sar27_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_15_oct3sar4_sar35_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_15_oct3sar4_sar35_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_15_oct3sar5_sar43_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_15_oct3sar5_sar43_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_16_oct3sar6_sar51_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_16_oct3sar6_sar51_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_16_oct3sar7_sar59_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_16_oct3sar7_sar59_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_17_oct4sar0_sar4_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_17_oct4sar0_sar4_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_17_oct4sar1_sar12_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_17_oct4sar1_sar12_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_18_oct4sar2_sar20_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_18_oct4sar2_sar20_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_18_oct4sar3_sar28_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_18_oct4sar3_sar28_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_19_oct4sar4_sar36_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_19_oct4sar4_sar36_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_19_oct4sar5_sar44_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_19_oct4sar5_sar44_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_1_oct0sar0_sar0_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_1_oct0sar0_sar0_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_1_oct0sar1_sar8_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_1_oct0sar1_sar8_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_20_oct4sar6_sar52_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_20_oct4sar6_sar52_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_20_oct4sar7_sar60_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_20_oct4sar7_sar60_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_21_oct5sar0_sar5_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_21_oct5sar0_sar5_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_21_oct5sar1_sar13_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_21_oct5sar1_sar13_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_22_oct5sar2_sar21_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_22_oct5sar2_sar21_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_22_oct5sar3_sar29_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_22_oct5sar3_sar29_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_23_oct5sar4_sar37_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_23_oct5sar4_sar37_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_23_oct5sar5_sar45_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_23_oct5sar5_sar45_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_24_oct5sar6_sar53_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_24_oct5sar6_sar53_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_24_oct5sar7_sar61_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_24_oct5sar7_sar61_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_25_oct6sar0_sar6_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_25_oct6sar0_sar6_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_25_oct6sar1_sar14_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_25_oct6sar1_sar14_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_26_oct6sar2_sar22_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_26_oct6sar2_sar22_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_26_oct6sar3_sar30_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_26_oct6sar3_sar30_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_27_oct6sar4_sar38_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_27_oct6sar4_sar38_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_27_oct6sar5_sar46_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_27_oct6sar5_sar46_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_28_oct6sar6_sar54_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_28_oct6sar6_sar54_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_28_oct6sar7_sar62_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_28_oct6sar7_sar62_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_29_oct7sar0_sar7_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_29_oct7sar0_sar7_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_29_oct7sar1_sar15_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_29_oct7sar1_sar15_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_2_oct0sar2_sar16_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_2_oct0sar2_sar16_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_2_oct0sar3_sar24_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_2_oct0sar3_sar24_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_30_oct7sar2_sar23_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_30_oct7sar2_sar23_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_30_oct7sar3_sar31_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_30_oct7sar3_sar31_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_31_oct7sar4_sar39_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_31_oct7sar4_sar39_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_31_oct7sar5_sar47_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_31_oct7sar5_sar47_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_32_oct7sar6_sar55_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_32_oct7sar6_sar55_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_32_oct7sar7_sar63_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_32_oct7sar7_sar63_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_33_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_33_oct0sar2_sar16_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_33_OCT0SAR2_SAR16_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_33_oct0sar2_sar16_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_33_oct0sar2_sar16_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_33_OCT0SAR2_SAR16_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_33_oct0sar3_sar24_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_33_OCT0SAR3_SAR24_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_33_oct0sar3_sar24_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_33_oct0sar3_sar24_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_33_OCT0SAR3_SAR24_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_33_oct0sar4_sar32_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_33_OCT0SAR4_SAR32_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_33_oct0sar4_sar32_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_33_oct0sar4_sar32_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_33_OCT0SAR4_SAR32_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_33_oct0sar5_sar40_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_33_OCT0SAR5_SAR40_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_33_oct0sar5_sar40_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_33_oct0sar5_sar40_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_33_OCT0SAR5_SAR40_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_34_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_34_oct0sar0_sar0_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_34_OCT0SAR0_SAR0_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_34_oct0sar0_sar0_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_34_oct0sar0_sar0_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_34_OCT0SAR0_SAR0_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_34_oct0sar1_sar8_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_34_OCT0SAR1_SAR8_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_34_oct0sar1_sar8_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_34_oct0sar1_sar8_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_34_OCT0SAR1_SAR8_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_34_oct0sar6_sar48_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_34_OCT0SAR6_SAR48_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_34_oct0sar6_sar48_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_34_oct0sar6_sar48_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_34_OCT0SAR6_SAR48_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_34_oct0sar7_sar56_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_34_OCT0SAR7_SAR56_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_34_oct0sar7_sar56_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_34_oct0sar7_sar56_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_34_OCT0SAR7_SAR56_SHRG_INIT_VAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_35_bonus_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_35_glb_div33_en_fw_attr == SERDES_LANE_ANA_ADC_LANE1_REG_35_GLB_DIV33_EN_FW_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_35_oct1sar2_sar17_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_35_OCT1SAR2_SAR17_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_35_oct1sar2_sar17_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_35_oct1sar2_sar17_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_35_OCT1SAR2_SAR17_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_35_oct1sar3_sar25_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_35_OCT1SAR3_SAR25_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_35_oct1sar3_sar25_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_35_oct1sar3_sar25_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_35_OCT1SAR3_SAR25_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_35_oct1sar4_sar33_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_35_OCT1SAR4_SAR33_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_35_oct1sar4_sar33_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_35_oct1sar4_sar33_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_35_OCT1SAR4_SAR33_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_35_oct1sar5_sar41_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_35_OCT1SAR5_SAR41_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_35_oct1sar5_sar41_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_35_oct1sar5_sar41_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_35_OCT1SAR5_SAR41_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_36_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_36_oct1sar0_sar1_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_36_OCT1SAR0_SAR1_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_36_oct1sar0_sar1_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_36_oct1sar0_sar1_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_36_OCT1SAR0_SAR1_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_36_oct1sar1_sar9_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_36_OCT1SAR1_SAR9_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_36_oct1sar1_sar9_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_36_oct1sar1_sar9_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_36_OCT1SAR1_SAR9_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_36_oct1sar6_sar49_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_36_OCT1SAR6_SAR49_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_36_oct1sar6_sar49_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_36_oct1sar6_sar49_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_36_OCT1SAR6_SAR49_SHRG_INIT_VAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_36_oct1sar7_sar57_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_36_OCT1SAR7_SAR57_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_36_oct1sar7_sar57_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_36_oct1sar7_sar57_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_36_OCT1SAR7_SAR57_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_37_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_37_oct2sar2_sar18_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_37_OCT2SAR2_SAR18_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_37_oct2sar2_sar18_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_37_oct2sar2_sar18_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_37_OCT2SAR2_SAR18_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_37_oct2sar3_sar26_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_37_OCT2SAR3_SAR26_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_37_oct2sar3_sar26_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_37_oct2sar3_sar26_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_37_OCT2SAR3_SAR26_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_37_oct2sar4_sar34_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_37_OCT2SAR4_SAR34_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_37_oct2sar4_sar34_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_37_oct2sar4_sar34_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_37_OCT2SAR4_SAR34_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_37_oct2sar5_sar42_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_37_OCT2SAR5_SAR42_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_37_oct2sar5_sar42_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_37_oct2sar5_sar42_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_37_OCT2SAR5_SAR42_SHRG_INIT_VAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_38_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_38_oct2sar0_sar2_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_38_OCT2SAR0_SAR2_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_38_oct2sar0_sar2_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_38_oct2sar0_sar2_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_38_OCT2SAR0_SAR2_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_38_oct2sar1_sar10_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_38_OCT2SAR1_SAR10_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_38_oct2sar1_sar10_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_38_oct2sar1_sar10_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_38_OCT2SAR1_SAR10_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_38_oct2sar6_sar50_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_38_OCT2SAR6_SAR50_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_38_oct2sar6_sar50_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_38_oct2sar6_sar50_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_38_OCT2SAR6_SAR50_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_38_oct2sar7_sar58_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_38_OCT2SAR7_SAR58_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_38_oct2sar7_sar58_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_38_oct2sar7_sar58_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_38_OCT2SAR7_SAR58_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_39_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_39_oct3sar2_sar19_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_39_OCT3SAR2_SAR19_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_39_oct3sar2_sar19_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_39_oct3sar2_sar19_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_39_OCT3SAR2_SAR19_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_39_oct3sar3_sar27_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_39_OCT3SAR3_SAR27_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_39_oct3sar3_sar27_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_39_oct3sar3_sar27_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_39_OCT3SAR3_SAR27_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_39_oct3sar4_sar35_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_39_OCT3SAR4_SAR35_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_39_oct3sar4_sar35_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_39_oct3sar4_sar35_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_39_OCT3SAR4_SAR35_SHRG_INIT_VAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_39_oct3sar5_sar43_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_39_OCT3SAR5_SAR43_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_39_oct3sar5_sar43_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_39_oct3sar5_sar43_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_39_OCT3SAR5_SAR43_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_3_oct0sar4_sar32_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_3_oct0sar4_sar32_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_3_oct0sar5_sar40_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_3_oct0sar5_sar40_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_40_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_40_oct3sar0_sar3_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_40_OCT3SAR0_SAR3_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_40_oct3sar0_sar3_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_40_oct3sar0_sar3_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_40_OCT3SAR0_SAR3_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_40_oct3sar1_sar11_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_40_OCT3SAR1_SAR11_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_40_oct3sar1_sar11_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_40_oct3sar1_sar11_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_40_OCT3SAR1_SAR11_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_40_oct3sar6_sar51_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_40_OCT3SAR6_SAR51_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_40_oct3sar6_sar51_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_40_oct3sar6_sar51_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_40_OCT3SAR6_SAR51_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_40_oct3sar7_sar59_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_40_OCT3SAR7_SAR59_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_40_oct3sar7_sar59_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_40_oct3sar7_sar59_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_40_OCT3SAR7_SAR59_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_41_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_41_oct4sar2_sar20_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_41_OCT4SAR2_SAR20_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_41_oct4sar2_sar20_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_41_oct4sar2_sar20_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_41_OCT4SAR2_SAR20_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_41_oct4sar3_sar28_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_41_OCT4SAR3_SAR28_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_41_oct4sar3_sar28_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_41_oct4sar3_sar28_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_41_OCT4SAR3_SAR28_SHRG_INIT_VAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_41_oct4sar4_sar36_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_41_OCT4SAR4_SAR36_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_41_oct4sar4_sar36_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_41_oct4sar4_sar36_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_41_OCT4SAR4_SAR36_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_41_oct4sar5_sar44_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_41_OCT4SAR5_SAR44_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_41_oct4sar5_sar44_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_41_oct4sar5_sar44_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_41_OCT4SAR5_SAR44_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_42_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_42_oct4sar0_sar4_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_42_OCT4SAR0_SAR4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_42_oct4sar0_sar4_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_42_oct4sar0_sar4_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_42_OCT4SAR0_SAR4_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_42_oct4sar1_sar12_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_42_OCT4SAR1_SAR12_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_42_oct4sar1_sar12_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_42_oct4sar1_sar12_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_42_OCT4SAR1_SAR12_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_42_oct4sar6_sar52_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_42_OCT4SAR6_SAR52_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_42_oct4sar6_sar52_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_42_oct4sar6_sar52_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_42_OCT4SAR6_SAR52_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_42_oct4sar7_sar60_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_42_OCT4SAR7_SAR60_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_42_oct4sar7_sar60_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_42_oct4sar7_sar60_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_42_OCT4SAR7_SAR60_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_43_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_43_oct5sar2_sar21_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_43_OCT5SAR2_SAR21_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_43_oct5sar2_sar21_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_43_oct5sar2_sar21_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_43_OCT5SAR2_SAR21_SHRG_INIT_VAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_43_oct5sar3_sar29_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_43_OCT5SAR3_SAR29_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_43_oct5sar3_sar29_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_43_oct5sar3_sar29_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_43_OCT5SAR3_SAR29_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_43_oct5sar4_sar37_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_43_OCT5SAR4_SAR37_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_43_oct5sar4_sar37_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_43_oct5sar4_sar37_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_43_OCT5SAR4_SAR37_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_43_oct5sar5_sar45_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_43_OCT5SAR5_SAR45_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_43_oct5sar5_sar45_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_43_oct5sar5_sar45_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_43_OCT5SAR5_SAR45_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_44_glb_div10_en_fw_attr == SERDES_LANE_ANA_ADC_LANE1_REG_44_GLB_DIV10_EN_FW_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_44_glb_div33_frac0p25_fw_attr == SERDES_LANE_ANA_ADC_LANE1_REG_44_GLB_DIV33_FRAC0P25_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_44_glb_div33_frac0p5_fw_attr == SERDES_LANE_ANA_ADC_LANE1_REG_44_GLB_DIV33_FRAC0P5_FW_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_44_glb_div33_ratio_fw_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_44_oct5sar0_sar5_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_44_OCT5SAR0_SAR5_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_44_oct5sar0_sar5_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_44_oct5sar0_sar5_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_44_OCT5SAR0_SAR5_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_44_oct5sar1_sar13_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_44_OCT5SAR1_SAR13_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_44_oct5sar1_sar13_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_44_oct5sar1_sar13_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_44_OCT5SAR1_SAR13_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_44_oct5sar6_sar53_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_44_OCT5SAR6_SAR53_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_44_oct5sar6_sar53_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_44_oct5sar6_sar53_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_44_OCT5SAR6_SAR53_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_44_oct5sar7_sar61_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_44_OCT5SAR7_SAR61_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_44_oct5sar7_sar61_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_44_oct5sar7_sar61_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_44_OCT5SAR7_SAR61_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_45_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_45_oct6sar2_sar22_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_45_OCT6SAR2_SAR22_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_45_oct6sar2_sar22_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_45_oct6sar2_sar22_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_45_OCT6SAR2_SAR22_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_45_oct6sar3_sar30_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_45_OCT6SAR3_SAR30_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_45_oct6sar3_sar30_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_45_oct6sar3_sar30_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_45_OCT6SAR3_SAR30_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_45_oct6sar4_sar38_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_45_OCT6SAR4_SAR38_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_45_oct6sar4_sar38_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_45_oct6sar4_sar38_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_45_OCT6SAR4_SAR38_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_45_oct6sar5_sar46_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_45_OCT6SAR5_SAR46_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_45_oct6sar5_sar46_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_45_oct6sar5_sar46_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_45_OCT6SAR5_SAR46_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_46_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_46_oct6sar0_sar6_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_46_OCT6SAR0_SAR6_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_46_oct6sar0_sar6_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_46_oct6sar0_sar6_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_46_OCT6SAR0_SAR6_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_46_oct6sar1_sar14_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_46_OCT6SAR1_SAR14_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_46_oct6sar1_sar14_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_46_oct6sar1_sar14_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_46_OCT6SAR1_SAR14_SHRG_INIT_VAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_46_oct6sar6_sar54_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_46_OCT6SAR6_SAR54_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_46_oct6sar6_sar54_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_46_oct6sar6_sar54_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_46_OCT6SAR6_SAR54_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_46_oct6sar7_sar62_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_46_OCT6SAR7_SAR62_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_46_oct6sar7_sar62_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_46_oct6sar7_sar62_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_46_OCT6SAR7_SAR62_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_47_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_47_oct7sar2_sar23_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_47_OCT7SAR2_SAR23_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_47_oct7sar2_sar23_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_47_oct7sar2_sar23_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_47_OCT7SAR2_SAR23_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_47_oct7sar3_sar31_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_47_OCT7SAR3_SAR31_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_47_oct7sar3_sar31_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_47_oct7sar3_sar31_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_47_OCT7SAR3_SAR31_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_47_oct7sar4_sar39_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_47_OCT7SAR4_SAR39_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_47_oct7sar4_sar39_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_47_oct7sar4_sar39_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_47_OCT7SAR4_SAR39_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_47_oct7sar5_sar47_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_47_OCT7SAR5_SAR47_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_47_oct7sar5_sar47_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_47_oct7sar5_sar47_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_47_OCT7SAR5_SAR47_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_48_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_48_oct7sar0_sar7_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_48_OCT7SAR0_SAR7_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_48_oct7sar0_sar7_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_48_oct7sar0_sar7_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_48_OCT7SAR0_SAR7_SHRG_INIT_VAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_48_oct7sar1_sar15_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_48_OCT7SAR1_SAR15_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_48_oct7sar1_sar15_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_48_oct7sar1_sar15_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_48_OCT7SAR1_SAR15_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_48_oct7sar6_sar55_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_48_OCT7SAR6_SAR55_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_48_oct7sar6_sar55_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_48_oct7sar6_sar55_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_48_OCT7SAR6_SAR55_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_48_oct7sar7_sar63_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_48_OCT7SAR7_SAR63_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_48_oct7sar7_sar63_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_48_oct7sar7_sar63_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE1_REG_48_OCT7SAR7_SAR63_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_49_dac_clear_dis_attr == SERDES_LANE_ANA_ADC_LANE1_REG_49_DAC_CLEAR_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_49_dac_clear_force_dfx_attr == SERDES_LANE_ANA_ADC_LANE1_REG_49_DAC_CLEAR_FORCE_DFX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_49_dac_reset_force_dfx_attr == SERDES_LANE_ANA_ADC_LANE1_REG_49_DAC_RESET_FORCE_DFX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_49_i_sar_finish_disable_fw_attr == SERDES_LANE_ANA_ADC_LANE1_REG_49_I_SAR_FINISH_DISABLE_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_49_nob_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_49_osc_speed_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_49_refgen_cm_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_49_refgen_dfx_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_49_rstb_attr == SERDES_LANE_ANA_ADC_LANE1_REG_49_RSTB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_49_sar_array_spare_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_49_th2_bypass_attr == SERDES_LANE_ANA_ADC_LANE1_REG_49_TH2_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_49_th_boost_select_attr == SERDES_LANE_ANA_ADC_LANE1_REG_49_TH_BOOST_SELECT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_4_oct0sar6_sar48_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_4_oct0sar6_sar48_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_4_oct0sar7_sar56_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_4_oct0sar7_sar56_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_50_shrg_align_clk2cdrrst_val_attr == 8'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_50_shrg_align_clk2lgcrst_val_attr == 8'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_50_shrg_align_clkrst_val_attr == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_51_current_control_15pc_ctl1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_51_current_control_15pc_ctl2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_51_current_control_3_ctl2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_51_current_control_7_ctl1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_51_o_25pc_ctl_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_51_o_current_base_dis_attr == SERDES_LANE_ANA_ADC_LANE1_REG_51_O_CURRENT_BASE_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_51_o_dcmon_vbpn_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_51_O_DCMON_VBPN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_51_o_dcmon_vref0_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_51_O_DCMON_VREF0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_51_o_dcmon_vref_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_51_O_DCMON_VREF_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_51_o_dcmonp_vref_inp_attr == SERDES_LANE_ANA_ADC_LANE1_REG_51_O_DCMONP_VREF_INP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_51_o_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_51_O_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_51_res_ref_ladder_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_52_current_control_15pc_ctl1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_52_current_control_15pc_ctl2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_52_current_control_3_ctl2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_52_current_control_7_ctl1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_52_o_25pc_ctl_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_52_o_current_base_dis_attr == SERDES_LANE_ANA_ADC_LANE1_REG_52_O_CURRENT_BASE_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_52_o_dcmon_vbpn_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_52_O_DCMON_VBPN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_52_o_dcmon_vref0_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_52_O_DCMON_VREF0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_52_o_dcmon_vref_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_52_O_DCMON_VREF_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_52_o_dcmonp_vref_inp_attr == SERDES_LANE_ANA_ADC_LANE1_REG_52_O_DCMONP_VREF_INP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_52_o_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_52_O_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_52_res_ref_ladder_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_53_current_control_15pc_ctl1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_53_current_control_15pc_ctl2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_53_current_control_3_ctl2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_53_current_control_7_ctl1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_53_o_25pc_ctl_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_53_o_current_base_dis_attr == SERDES_LANE_ANA_ADC_LANE1_REG_53_O_CURRENT_BASE_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_53_o_dcmon_vbpn_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_53_O_DCMON_VBPN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_53_o_dcmon_vref0_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_53_O_DCMON_VREF0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_53_o_dcmon_vref_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_53_O_DCMON_VREF_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_53_o_dcmonp_vref_inp_attr == SERDES_LANE_ANA_ADC_LANE1_REG_53_O_DCMONP_VREF_INP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_53_o_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_53_O_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_53_res_ref_ladder_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_54_current_control_15pc_ctl1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_54_current_control_15pc_ctl2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_54_current_control_3_ctl2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_54_current_control_7_ctl1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_54_o_25pc_ctl_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_54_o_current_base_dis_attr == SERDES_LANE_ANA_ADC_LANE1_REG_54_O_CURRENT_BASE_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_54_o_dcmon_vbpn_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_54_O_DCMON_VBPN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_54_o_dcmon_vref0_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_54_O_DCMON_VREF0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_54_o_dcmon_vref_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_54_O_DCMON_VREF_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_54_o_dcmonp_vref_inp_attr == SERDES_LANE_ANA_ADC_LANE1_REG_54_O_DCMONP_VREF_INP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_54_o_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_54_O_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_54_res_ref_ladder_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_55_current_control_15pc_ctl1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_55_current_control_15pc_ctl2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_55_current_control_3_ctl2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_55_current_control_7_ctl1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_55_o_25pc_ctl_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_55_o_current_base_dis_attr == SERDES_LANE_ANA_ADC_LANE1_REG_55_O_CURRENT_BASE_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_55_o_dcmon_vbpn_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_55_O_DCMON_VBPN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_55_o_dcmon_vref0_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_55_O_DCMON_VREF0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_55_o_dcmon_vref_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_55_O_DCMON_VREF_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_55_o_dcmonp_vref_inp_attr == SERDES_LANE_ANA_ADC_LANE1_REG_55_O_DCMONP_VREF_INP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_55_o_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_55_O_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_55_res_ref_ladder_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_56_current_control_15pc_ctl1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_56_current_control_15pc_ctl2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_56_current_control_3_ctl2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_56_current_control_7_ctl1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_56_o_25pc_ctl_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_56_o_current_base_dis_attr == SERDES_LANE_ANA_ADC_LANE1_REG_56_O_CURRENT_BASE_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_56_o_dcmon_vbpn_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_56_O_DCMON_VBPN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_56_o_dcmon_vref0_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_56_O_DCMON_VREF0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_56_o_dcmon_vref_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_56_O_DCMON_VREF_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_56_o_dcmonp_vref_inp_attr == SERDES_LANE_ANA_ADC_LANE1_REG_56_O_DCMONP_VREF_INP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_56_o_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_56_O_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_56_res_ref_ladder_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_57_current_control_15pc_ctl1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_57_current_control_15pc_ctl2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_57_current_control_3_ctl2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_57_current_control_7_ctl1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_57_o_25pc_ctl_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_57_o_current_base_dis_attr == SERDES_LANE_ANA_ADC_LANE1_REG_57_O_CURRENT_BASE_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_57_o_dcmon_vbpn_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_57_O_DCMON_VBPN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_57_o_dcmon_vref0_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_57_O_DCMON_VREF0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_57_o_dcmon_vref_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_57_O_DCMON_VREF_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_57_o_dcmonp_vref_inp_attr == SERDES_LANE_ANA_ADC_LANE1_REG_57_O_DCMONP_VREF_INP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_57_o_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_57_O_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_57_res_ref_ladder_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_58_current_control_15pc_ctl1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_58_current_control_15pc_ctl2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_58_current_control_3_ctl2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_58_current_control_7_ctl1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_58_o_25pc_ctl_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_58_o_current_base_dis_attr == SERDES_LANE_ANA_ADC_LANE1_REG_58_O_CURRENT_BASE_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_58_o_dcmon_vbpn_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_58_O_DCMON_VBPN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_58_o_dcmon_vref0_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_58_O_DCMON_VREF0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_58_o_dcmon_vref_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_58_O_DCMON_VREF_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_58_o_dcmonp_vref_inp_attr == SERDES_LANE_ANA_ADC_LANE1_REG_58_O_DCMONP_VREF_INP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_58_o_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_58_O_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_58_res_ref_ladder_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_59_i_psf_cur_trim_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_59_i_psf_cur_trim_spare_attr == SERDES_LANE_ANA_ADC_LANE1_REG_59_I_PSF_CUR_TRIM_SPARE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_59_psf_bias_current_mon_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_59_PSF_BIAS_CURRENT_MON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_59_psf_cm_ctrl_reserved_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_59_psf_dcmon_spare1_attr == SERDES_LANE_ANA_ADC_LANE1_REG_59_PSF_DCMON_SPARE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_59_psf_dcmon_spare2_attr == SERDES_LANE_ANA_ADC_LANE1_REG_59_PSF_DCMON_SPARE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_59_psf_dcmon_spare3_attr == SERDES_LANE_ANA_ADC_LANE1_REG_59_PSF_DCMON_SPARE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_59_psf_dfx_int_out_mon_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_59_PSF_DFX_INT_OUT_MON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_59_psf_integrator_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_59_PSF_INTEGRATOR_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_59_psf_pbias_cas_mon_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_59_PSF_PBIAS_CAS_MON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_59_psf_vref_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_59_PSF_VREF_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_59_th0_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_59_TH0_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_59_th1_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_59_TH1_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_59_th2_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_59_TH2_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_59_th3_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_59_TH3_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_59_th4_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_59_TH4_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_59_th5_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_59_TH5_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_59_th6_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_59_TH6_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_59_th7_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_59_TH7_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_59_th_sw_bypass_attr == SERDES_LANE_ANA_ADC_LANE1_REG_59_TH_SW_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_5_oct1sar0_sar1_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_5_oct1sar0_sar1_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_5_oct1sar1_sar9_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_5_oct1sar1_sar9_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_60_th0_cur_trim_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_60_th1_cur_trim_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_60_th2_cur_trim_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_60_th3_cur_trim_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_60_th4_cur_trim_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_60_th5_cur_trim_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_60_th6_cur_trim_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_60_th7_cur_trim_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_61_th0_psf_ofc_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_61_th1_psf_ofc_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_61_th2_psf_ofc_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_61_th3_psf_ofc_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_61_th4_psf_ofc_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_61_th5_psf_ofc_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_61_th6_psf_ofc_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_61_th7_psf_ofc_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_62_bonus_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_62_dfx_en_mon_attr == SERDES_LANE_ANA_ADC_LANE1_REG_62_DFX_EN_MON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_62_dfx_en_slc_attr == SERDES_LANE_ANA_ADC_LANE1_REG_62_DFX_EN_SLC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_62_th0_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_62_TH0_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_62_th1_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_62_TH1_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_62_th2_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_62_TH2_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_62_th3_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_62_TH3_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_62_th4_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_62_TH4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_62_th5_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_62_TH5_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_62_th6_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_62_TH6_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_62_th7_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_62_TH7_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_62_th_bias_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_62_TH_BIAS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_63_bonus_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_63_sar_dfx_en_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_64_ch4_pi_code_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_64_ch5_pi_code_attr == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_64_ch6_pi_code_attr == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_64_ch7_pi_code_attr == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_65_ch0_pi_code_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_65_ch1_pi_code_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_65_ch2_pi_code_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_65_ch3_pi_code_attr == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_66_c2c_en_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_66_ch0_pi_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_66_CH0_PI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_66_ch0_pi_transp_in_attr == SERDES_LANE_ANA_ADC_LANE1_REG_66_CH0_PI_TRANSP_IN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_66_ch1_pi_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_66_CH1_PI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_66_ch1_pi_transp_in_attr == SERDES_LANE_ANA_ADC_LANE1_REG_66_CH1_PI_TRANSP_IN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_66_ch2_pi_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_66_CH2_PI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_66_ch2_pi_transp_in_attr == SERDES_LANE_ANA_ADC_LANE1_REG_66_CH2_PI_TRANSP_IN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_66_ch3_pi_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_66_CH3_PI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_66_ch3_pi_transp_in_attr == SERDES_LANE_ANA_ADC_LANE1_REG_66_CH3_PI_TRANSP_IN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_66_ch4_pi_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_66_CH4_PI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_66_ch4_pi_transp_in_attr == SERDES_LANE_ANA_ADC_LANE1_REG_66_CH4_PI_TRANSP_IN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_66_ch5_pi_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_66_CH5_PI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_66_ch5_pi_transp_in_attr == SERDES_LANE_ANA_ADC_LANE1_REG_66_CH5_PI_TRANSP_IN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_66_ch6_pi_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_66_CH6_PI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_66_ch6_pi_transp_in_attr == SERDES_LANE_ANA_ADC_LANE1_REG_66_CH6_PI_TRANSP_IN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_66_ch7_pi_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_66_CH7_PI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_66_ch7_pi_transp_in_attr == SERDES_LANE_ANA_ADC_LANE1_REG_66_CH7_PI_TRANSP_IN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_67_dispolarity_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_67_i_clkmux_ungate_req_reg_attr == SERDES_LANE_ANA_ADC_LANE1_REG_67_I_CLKMUX_UNGATE_REQ_REG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_67_i_clkmux_ungate_rst_reg_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_67_spare_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_67_td_degen_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_68_clk2td_ch_sel_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_68_pdo_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_68_PDO_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_68_spare_attr == SERDES_LANE_ANA_ADC_LANE1_REG_68_SPARE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_68_td_en_pd_attr == SERDES_LANE_ANA_ADC_LANE1_REG_68_TD_EN_PD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_68_td_i_ctrl_2ui_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_68_td_i_ctrl_4ui_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_68_td_i_sel_count_stop_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_68_td_rstb_attr == SERDES_LANE_ANA_ADC_LANE1_REG_68_TD_RSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_69_dcmon_cmp_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_69_dcmon_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_69_input_cs_trimming_attr == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_69_nc_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_69_nsf_enable_attr == SERDES_LANE_ANA_ADC_LANE1_REG_69_NSF_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_69_nsf_even_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_69_NSF_EVEN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_69_nsf_odd_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_69_NSF_ODD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_6_oct1sar2_sar17_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_6_oct1sar2_sar17_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_6_oct1sar3_sar25_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_6_oct1sar3_sar25_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_70_i_clkmux_hsmonsel_local_reg_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_70_i_clkmux_hsmonsel_next_reg_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_70_i_clkmux_hsmonseln_reg_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_70_i_clkmux_hsmonselp_reg_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_70_ph_out_seln_attr == SERDES_LANE_ANA_ADC_LANE1_REG_70_PH_OUT_SELN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_71_clk_gen_dcmon_n_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_71_CLK_GEN_DCMON_N_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_71_clk_gen_dcmon_p_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_71_CLK_GEN_DCMON_P_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_71_clkgen_and_sar_l_comp_n_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_71_CLKGEN_AND_SAR_L_COMP_N_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_71_clkgen_and_sar_l_comp_p_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_71_CLKGEN_AND_SAR_L_COMP_P_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_71_clkgen_and_sar_l_dcmon_n_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_71_CLKGEN_AND_SAR_L_DCMON_N_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_71_clkgen_and_sar_l_dcmon_p_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_71_CLKGEN_AND_SAR_L_DCMON_P_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_71_i_sararray_vref_n_attr == SERDES_LANE_ANA_ADC_LANE1_REG_71_I_SARARRAY_VREF_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_71_i_sararray_vref_p_attr == SERDES_LANE_ANA_ADC_LANE1_REG_71_I_SARARRAY_VREF_P_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_71_nsf_th_clkmux_comp_n_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_71_NSF_TH_CLKMUX_COMP_N_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_71_nsf_th_clkmux_comp_p_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_71_NSF_TH_CLKMUX_COMP_P_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_71_nsf_th_clkmux_dcmon_n_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_71_NSF_TH_CLKMUX_DCMON_N_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_71_nsf_th_clkmux_dcmon_p_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_71_NSF_TH_CLKMUX_DCMON_P_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_71_o_sar_dft_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_71_oct3_dfx_en_l_attr == SERDES_LANE_ANA_ADC_LANE1_REG_71_OCT3_DFX_EN_L_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_71_oct3_dfx_en_r_attr == SERDES_LANE_ANA_ADC_LANE1_REG_71_OCT3_DFX_EN_R_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_71_oct7_dfx_en_l_attr == SERDES_LANE_ANA_ADC_LANE1_REG_71_OCT7_DFX_EN_L_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_71_oct7_dfx_en_r_attr == SERDES_LANE_ANA_ADC_LANE1_REG_71_OCT7_DFX_EN_R_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_71_spare_dfx_left_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_72_dcmon2slc_attr == SERDES_LANE_ANA_ADC_LANE1_REG_72_DCMON2SLC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_72_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_72_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_72_dcmon_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_72_ph_out_selp_attr == SERDES_LANE_ANA_ADC_LANE1_REG_72_PH_OUT_SELP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_72_spare_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_73_clkgen_comp_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_73_CLKGEN_COMP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_73_o_sar_dft_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_73_oct0_dfx_en_l_attr == SERDES_LANE_ANA_ADC_LANE1_REG_73_OCT0_DFX_EN_L_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_73_oct0_dfx_en_r_attr == SERDES_LANE_ANA_ADC_LANE1_REG_73_OCT0_DFX_EN_R_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_73_oct2_dfx_en_l_attr == SERDES_LANE_ANA_ADC_LANE1_REG_73_OCT2_DFX_EN_L_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_73_oct2_dfx_en_r_attr == SERDES_LANE_ANA_ADC_LANE1_REG_73_OCT2_DFX_EN_R_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_73_oct4_dfx_en_l_attr == SERDES_LANE_ANA_ADC_LANE1_REG_73_OCT4_DFX_EN_L_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_73_oct4_dfx_en_r_attr == SERDES_LANE_ANA_ADC_LANE1_REG_73_OCT4_DFX_EN_R_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_73_oct6_dfx_en_l_attr == SERDES_LANE_ANA_ADC_LANE1_REG_73_OCT6_DFX_EN_L_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_73_sar_r_comp_n_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_73_SAR_R_COMP_N_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_73_sar_r_comp_p_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_73_SAR_R_COMP_P_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_73_sar_r_dcmon_n_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_73_SAR_R_DCMON_N_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_73_sar_r_dcmon_p_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_73_SAR_R_DCMON_P_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_73_spare_dfx_right_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_74_fall_sel3_attr == 7'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_74_fall_sel5_attr == 7'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_74_fall_sel7_attr == 7'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_74_spare1_reg13_attr == SERDES_LANE_ANA_ADC_LANE1_REG_74_SPARE1_REG13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_74_spare2_reg13_attr == SERDES_LANE_ANA_ADC_LANE1_REG_74_SPARE2_REG13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_74_spare3_reg13_attr == SERDES_LANE_ANA_ADC_LANE1_REG_74_SPARE3_REG13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_75_rise_sel0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_75_rise_sel1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_75_rise_sel2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_75_rise_sel3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_76_spare_reg1_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_77_dfx_seln_attr == 17'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_77_spare1_reg2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_77_spare2_reg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_78_dfx_selp_attr == 17'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_78_spare_reg03_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_79_rise_sel4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_79_rise_sel5_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_79_rise_sel6_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_79_rise_sel7_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_7_oct1sar4_sar33_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_7_oct1sar4_sar33_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_7_oct1sar5_sar41_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_7_oct1sar5_sar41_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_80_c2c_en_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_80_clk_sel_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_80_counter_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_80_COUNTER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_80_dcd_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_80_DCD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_80_dcd_sel_attr == SERDES_LANE_ANA_ADC_LANE1_REG_80_DCD_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_80_dfx_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_80_DFX_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_80_en_dfx_attr == SERDES_LANE_ANA_ADC_LANE1_REG_80_EN_DFX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_80_spare5_reg5_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_81_buffer_bias0_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_81_buffer_bias_dfx_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_81_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_81_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_81_sel_c2c_cascode_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_81_sel_c2c_dc_coarse_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_81_sel_c2c_global_i_attr == 7'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_81_spare_reg6_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_82_bw_sel0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_82_i_a2f_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_82_I_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_82_i_dfx_a2f_boost_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_82_I_DFX_A2F_BOOST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_82_idfx_sel_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_82_sel_cgm_en_attr == SERDES_LANE_ANA_ADC_LANE1_REG_82_SEL_CGM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_82_spare_reg07_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_83_bw_sel1_attr == 15'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_83_res_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_83_spare_reg08_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_84_bw_sel2_attr == 15'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_84_clk_2ui_sel_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_84_spare_reg09_attr == SERDES_LANE_ANA_ADC_LANE1_REG_84_SPARE_REG09_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_85_bw_sel3_attr == 15'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_85_spare_reg10_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_86_fall_sel0_attr == 7'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_86_fall_sel1_attr == 7'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_86_spare1_reg11_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_86_spare2_reg11_attr == SERDES_LANE_ANA_ADC_LANE1_REG_86_SPARE2_REG11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_87_fall_sel2_attr == 7'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_87_fall_sel4_attr == 7'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_87_fall_sel6_attr == 7'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_87_spare1_reg12_attr == SERDES_LANE_ANA_ADC_LANE1_REG_87_SPARE1_REG12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_87_spare2_reg12_attr == SERDES_LANE_ANA_ADC_LANE1_REG_87_SPARE2_REG12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_87_spare3_reg12_attr == SERDES_LANE_ANA_ADC_LANE1_REG_87_SPARE3_REG12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_8_oct1sar6_sar49_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_8_oct1sar6_sar49_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_8_oct1sar7_sar57_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_8_oct1sar7_sar57_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_9_oct2sar0_sar2_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_9_oct2sar0_sar2_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_9_oct2sar1_sar10_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane1_reg_9_oct2sar1_sar10_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_10_oct2sar2_sar18_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_10_oct2sar2_sar18_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_10_oct2sar3_sar26_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_10_oct2sar3_sar26_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_11_oct2sar4_sar34_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_11_oct2sar4_sar34_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_11_oct2sar5_sar42_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_11_oct2sar5_sar42_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_12_oct2sar6_sar50_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_12_oct2sar6_sar50_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_12_oct2sar7_sar58_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_12_oct2sar7_sar58_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_13_oct3sar0_sar3_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_13_oct3sar0_sar3_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_13_oct3sar1_sar11_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_13_oct3sar1_sar11_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_14_oct3sar2_sar19_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_14_oct3sar2_sar19_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_14_oct3sar3_sar27_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_14_oct3sar3_sar27_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_15_oct3sar4_sar35_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_15_oct3sar4_sar35_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_15_oct3sar5_sar43_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_15_oct3sar5_sar43_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_16_oct3sar6_sar51_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_16_oct3sar6_sar51_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_16_oct3sar7_sar59_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_16_oct3sar7_sar59_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_17_oct4sar0_sar4_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_17_oct4sar0_sar4_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_17_oct4sar1_sar12_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_17_oct4sar1_sar12_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_18_oct4sar2_sar20_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_18_oct4sar2_sar20_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_18_oct4sar3_sar28_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_18_oct4sar3_sar28_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_19_oct4sar4_sar36_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_19_oct4sar4_sar36_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_19_oct4sar5_sar44_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_19_oct4sar5_sar44_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_1_oct0sar0_sar0_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_1_oct0sar0_sar0_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_1_oct0sar1_sar8_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_1_oct0sar1_sar8_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_20_oct4sar6_sar52_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_20_oct4sar6_sar52_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_20_oct4sar7_sar60_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_20_oct4sar7_sar60_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_21_oct5sar0_sar5_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_21_oct5sar0_sar5_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_21_oct5sar1_sar13_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_21_oct5sar1_sar13_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_22_oct5sar2_sar21_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_22_oct5sar2_sar21_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_22_oct5sar3_sar29_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_22_oct5sar3_sar29_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_23_oct5sar4_sar37_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_23_oct5sar4_sar37_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_23_oct5sar5_sar45_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_23_oct5sar5_sar45_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_24_oct5sar6_sar53_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_24_oct5sar6_sar53_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_24_oct5sar7_sar61_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_24_oct5sar7_sar61_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_25_oct6sar0_sar6_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_25_oct6sar0_sar6_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_25_oct6sar1_sar14_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_25_oct6sar1_sar14_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_26_oct6sar2_sar22_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_26_oct6sar2_sar22_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_26_oct6sar3_sar30_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_26_oct6sar3_sar30_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_27_oct6sar4_sar38_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_27_oct6sar4_sar38_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_27_oct6sar5_sar46_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_27_oct6sar5_sar46_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_28_oct6sar6_sar54_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_28_oct6sar6_sar54_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_28_oct6sar7_sar62_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_28_oct6sar7_sar62_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_29_oct7sar0_sar7_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_29_oct7sar0_sar7_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_29_oct7sar1_sar15_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_29_oct7sar1_sar15_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_2_oct0sar2_sar16_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_2_oct0sar2_sar16_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_2_oct0sar3_sar24_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_2_oct0sar3_sar24_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_30_oct7sar2_sar23_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_30_oct7sar2_sar23_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_30_oct7sar3_sar31_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_30_oct7sar3_sar31_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_31_oct7sar4_sar39_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_31_oct7sar4_sar39_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_31_oct7sar5_sar47_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_31_oct7sar5_sar47_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_32_oct7sar6_sar55_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_32_oct7sar6_sar55_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_32_oct7sar7_sar63_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_32_oct7sar7_sar63_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_33_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_33_oct0sar2_sar16_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_33_OCT0SAR2_SAR16_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_33_oct0sar2_sar16_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_33_oct0sar2_sar16_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_33_OCT0SAR2_SAR16_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_33_oct0sar3_sar24_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_33_OCT0SAR3_SAR24_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_33_oct0sar3_sar24_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_33_oct0sar3_sar24_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_33_OCT0SAR3_SAR24_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_33_oct0sar4_sar32_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_33_OCT0SAR4_SAR32_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_33_oct0sar4_sar32_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_33_oct0sar4_sar32_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_33_OCT0SAR4_SAR32_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_33_oct0sar5_sar40_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_33_OCT0SAR5_SAR40_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_33_oct0sar5_sar40_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_33_oct0sar5_sar40_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_33_OCT0SAR5_SAR40_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_34_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_34_oct0sar0_sar0_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_34_OCT0SAR0_SAR0_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_34_oct0sar0_sar0_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_34_oct0sar0_sar0_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_34_OCT0SAR0_SAR0_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_34_oct0sar1_sar8_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_34_OCT0SAR1_SAR8_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_34_oct0sar1_sar8_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_34_oct0sar1_sar8_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_34_OCT0SAR1_SAR8_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_34_oct0sar6_sar48_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_34_OCT0SAR6_SAR48_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_34_oct0sar6_sar48_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_34_oct0sar6_sar48_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_34_OCT0SAR6_SAR48_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_34_oct0sar7_sar56_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_34_OCT0SAR7_SAR56_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_34_oct0sar7_sar56_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_34_oct0sar7_sar56_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_34_OCT0SAR7_SAR56_SHRG_INIT_VAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_35_bonus_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_35_glb_div33_en_fw_attr == SERDES_LANE_ANA_ADC_LANE2_REG_35_GLB_DIV33_EN_FW_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_35_oct1sar2_sar17_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_35_OCT1SAR2_SAR17_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_35_oct1sar2_sar17_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_35_oct1sar2_sar17_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_35_OCT1SAR2_SAR17_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_35_oct1sar3_sar25_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_35_OCT1SAR3_SAR25_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_35_oct1sar3_sar25_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_35_oct1sar3_sar25_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_35_OCT1SAR3_SAR25_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_35_oct1sar4_sar33_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_35_OCT1SAR4_SAR33_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_35_oct1sar4_sar33_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_35_oct1sar4_sar33_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_35_OCT1SAR4_SAR33_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_35_oct1sar5_sar41_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_35_OCT1SAR5_SAR41_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_35_oct1sar5_sar41_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_35_oct1sar5_sar41_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_35_OCT1SAR5_SAR41_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_36_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_36_oct1sar0_sar1_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_36_OCT1SAR0_SAR1_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_36_oct1sar0_sar1_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_36_oct1sar0_sar1_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_36_OCT1SAR0_SAR1_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_36_oct1sar1_sar9_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_36_OCT1SAR1_SAR9_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_36_oct1sar1_sar9_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_36_oct1sar1_sar9_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_36_OCT1SAR1_SAR9_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_36_oct1sar6_sar49_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_36_OCT1SAR6_SAR49_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_36_oct1sar6_sar49_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_36_oct1sar6_sar49_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_36_OCT1SAR6_SAR49_SHRG_INIT_VAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_36_oct1sar7_sar57_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_36_OCT1SAR7_SAR57_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_36_oct1sar7_sar57_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_36_oct1sar7_sar57_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_36_OCT1SAR7_SAR57_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_37_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_37_oct2sar2_sar18_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_37_OCT2SAR2_SAR18_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_37_oct2sar2_sar18_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_37_oct2sar2_sar18_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_37_OCT2SAR2_SAR18_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_37_oct2sar3_sar26_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_37_OCT2SAR3_SAR26_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_37_oct2sar3_sar26_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_37_oct2sar3_sar26_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_37_OCT2SAR3_SAR26_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_37_oct2sar4_sar34_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_37_OCT2SAR4_SAR34_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_37_oct2sar4_sar34_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_37_oct2sar4_sar34_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_37_OCT2SAR4_SAR34_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_37_oct2sar5_sar42_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_37_OCT2SAR5_SAR42_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_37_oct2sar5_sar42_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_37_oct2sar5_sar42_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_37_OCT2SAR5_SAR42_SHRG_INIT_VAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_38_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_38_oct2sar0_sar2_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_38_OCT2SAR0_SAR2_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_38_oct2sar0_sar2_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_38_oct2sar0_sar2_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_38_OCT2SAR0_SAR2_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_38_oct2sar1_sar10_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_38_OCT2SAR1_SAR10_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_38_oct2sar1_sar10_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_38_oct2sar1_sar10_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_38_OCT2SAR1_SAR10_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_38_oct2sar6_sar50_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_38_OCT2SAR6_SAR50_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_38_oct2sar6_sar50_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_38_oct2sar6_sar50_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_38_OCT2SAR6_SAR50_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_38_oct2sar7_sar58_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_38_OCT2SAR7_SAR58_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_38_oct2sar7_sar58_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_38_oct2sar7_sar58_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_38_OCT2SAR7_SAR58_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_39_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_39_oct3sar2_sar19_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_39_OCT3SAR2_SAR19_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_39_oct3sar2_sar19_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_39_oct3sar2_sar19_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_39_OCT3SAR2_SAR19_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_39_oct3sar3_sar27_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_39_OCT3SAR3_SAR27_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_39_oct3sar3_sar27_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_39_oct3sar3_sar27_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_39_OCT3SAR3_SAR27_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_39_oct3sar4_sar35_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_39_OCT3SAR4_SAR35_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_39_oct3sar4_sar35_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_39_oct3sar4_sar35_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_39_OCT3SAR4_SAR35_SHRG_INIT_VAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_39_oct3sar5_sar43_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_39_OCT3SAR5_SAR43_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_39_oct3sar5_sar43_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_39_oct3sar5_sar43_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_39_OCT3SAR5_SAR43_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_3_oct0sar4_sar32_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_3_oct0sar4_sar32_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_3_oct0sar5_sar40_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_3_oct0sar5_sar40_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_40_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_40_oct3sar0_sar3_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_40_OCT3SAR0_SAR3_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_40_oct3sar0_sar3_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_40_oct3sar0_sar3_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_40_OCT3SAR0_SAR3_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_40_oct3sar1_sar11_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_40_OCT3SAR1_SAR11_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_40_oct3sar1_sar11_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_40_oct3sar1_sar11_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_40_OCT3SAR1_SAR11_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_40_oct3sar6_sar51_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_40_OCT3SAR6_SAR51_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_40_oct3sar6_sar51_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_40_oct3sar6_sar51_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_40_OCT3SAR6_SAR51_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_40_oct3sar7_sar59_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_40_OCT3SAR7_SAR59_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_40_oct3sar7_sar59_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_40_oct3sar7_sar59_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_40_OCT3SAR7_SAR59_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_41_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_41_oct4sar2_sar20_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_41_OCT4SAR2_SAR20_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_41_oct4sar2_sar20_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_41_oct4sar2_sar20_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_41_OCT4SAR2_SAR20_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_41_oct4sar3_sar28_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_41_OCT4SAR3_SAR28_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_41_oct4sar3_sar28_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_41_oct4sar3_sar28_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_41_OCT4SAR3_SAR28_SHRG_INIT_VAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_41_oct4sar4_sar36_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_41_OCT4SAR4_SAR36_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_41_oct4sar4_sar36_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_41_oct4sar4_sar36_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_41_OCT4SAR4_SAR36_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_41_oct4sar5_sar44_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_41_OCT4SAR5_SAR44_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_41_oct4sar5_sar44_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_41_oct4sar5_sar44_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_41_OCT4SAR5_SAR44_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_42_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_42_oct4sar0_sar4_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_42_OCT4SAR0_SAR4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_42_oct4sar0_sar4_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_42_oct4sar0_sar4_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_42_OCT4SAR0_SAR4_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_42_oct4sar1_sar12_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_42_OCT4SAR1_SAR12_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_42_oct4sar1_sar12_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_42_oct4sar1_sar12_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_42_OCT4SAR1_SAR12_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_42_oct4sar6_sar52_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_42_OCT4SAR6_SAR52_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_42_oct4sar6_sar52_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_42_oct4sar6_sar52_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_42_OCT4SAR6_SAR52_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_42_oct4sar7_sar60_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_42_OCT4SAR7_SAR60_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_42_oct4sar7_sar60_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_42_oct4sar7_sar60_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_42_OCT4SAR7_SAR60_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_43_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_43_oct5sar2_sar21_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_43_OCT5SAR2_SAR21_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_43_oct5sar2_sar21_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_43_oct5sar2_sar21_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_43_OCT5SAR2_SAR21_SHRG_INIT_VAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_43_oct5sar3_sar29_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_43_OCT5SAR3_SAR29_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_43_oct5sar3_sar29_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_43_oct5sar3_sar29_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_43_OCT5SAR3_SAR29_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_43_oct5sar4_sar37_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_43_OCT5SAR4_SAR37_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_43_oct5sar4_sar37_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_43_oct5sar4_sar37_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_43_OCT5SAR4_SAR37_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_43_oct5sar5_sar45_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_43_OCT5SAR5_SAR45_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_43_oct5sar5_sar45_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_43_oct5sar5_sar45_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_43_OCT5SAR5_SAR45_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_44_glb_div10_en_fw_attr == SERDES_LANE_ANA_ADC_LANE2_REG_44_GLB_DIV10_EN_FW_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_44_glb_div33_frac0p25_fw_attr == SERDES_LANE_ANA_ADC_LANE2_REG_44_GLB_DIV33_FRAC0P25_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_44_glb_div33_frac0p5_fw_attr == SERDES_LANE_ANA_ADC_LANE2_REG_44_GLB_DIV33_FRAC0P5_FW_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_44_glb_div33_ratio_fw_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_44_oct5sar0_sar5_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_44_OCT5SAR0_SAR5_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_44_oct5sar0_sar5_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_44_oct5sar0_sar5_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_44_OCT5SAR0_SAR5_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_44_oct5sar1_sar13_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_44_OCT5SAR1_SAR13_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_44_oct5sar1_sar13_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_44_oct5sar1_sar13_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_44_OCT5SAR1_SAR13_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_44_oct5sar6_sar53_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_44_OCT5SAR6_SAR53_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_44_oct5sar6_sar53_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_44_oct5sar6_sar53_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_44_OCT5SAR6_SAR53_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_44_oct5sar7_sar61_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_44_OCT5SAR7_SAR61_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_44_oct5sar7_sar61_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_44_oct5sar7_sar61_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_44_OCT5SAR7_SAR61_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_45_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_45_oct6sar2_sar22_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_45_OCT6SAR2_SAR22_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_45_oct6sar2_sar22_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_45_oct6sar2_sar22_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_45_OCT6SAR2_SAR22_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_45_oct6sar3_sar30_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_45_OCT6SAR3_SAR30_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_45_oct6sar3_sar30_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_45_oct6sar3_sar30_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_45_OCT6SAR3_SAR30_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_45_oct6sar4_sar38_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_45_OCT6SAR4_SAR38_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_45_oct6sar4_sar38_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_45_oct6sar4_sar38_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_45_OCT6SAR4_SAR38_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_45_oct6sar5_sar46_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_45_OCT6SAR5_SAR46_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_45_oct6sar5_sar46_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_45_oct6sar5_sar46_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_45_OCT6SAR5_SAR46_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_46_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_46_oct6sar0_sar6_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_46_OCT6SAR0_SAR6_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_46_oct6sar0_sar6_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_46_oct6sar0_sar6_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_46_OCT6SAR0_SAR6_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_46_oct6sar1_sar14_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_46_OCT6SAR1_SAR14_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_46_oct6sar1_sar14_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_46_oct6sar1_sar14_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_46_OCT6SAR1_SAR14_SHRG_INIT_VAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_46_oct6sar6_sar54_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_46_OCT6SAR6_SAR54_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_46_oct6sar6_sar54_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_46_oct6sar6_sar54_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_46_OCT6SAR6_SAR54_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_46_oct6sar7_sar62_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_46_OCT6SAR7_SAR62_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_46_oct6sar7_sar62_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_46_oct6sar7_sar62_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_46_OCT6SAR7_SAR62_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_47_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_47_oct7sar2_sar23_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_47_OCT7SAR2_SAR23_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_47_oct7sar2_sar23_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_47_oct7sar2_sar23_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_47_OCT7SAR2_SAR23_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_47_oct7sar3_sar31_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_47_OCT7SAR3_SAR31_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_47_oct7sar3_sar31_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_47_oct7sar3_sar31_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_47_OCT7SAR3_SAR31_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_47_oct7sar4_sar39_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_47_OCT7SAR4_SAR39_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_47_oct7sar4_sar39_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_47_oct7sar4_sar39_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_47_OCT7SAR4_SAR39_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_47_oct7sar5_sar47_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_47_OCT7SAR5_SAR47_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_47_oct7sar5_sar47_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_47_oct7sar5_sar47_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_47_OCT7SAR5_SAR47_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_48_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_48_oct7sar0_sar7_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_48_OCT7SAR0_SAR7_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_48_oct7sar0_sar7_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_48_oct7sar0_sar7_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_48_OCT7SAR0_SAR7_SHRG_INIT_VAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_48_oct7sar1_sar15_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_48_OCT7SAR1_SAR15_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_48_oct7sar1_sar15_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_48_oct7sar1_sar15_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_48_OCT7SAR1_SAR15_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_48_oct7sar6_sar55_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_48_OCT7SAR6_SAR55_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_48_oct7sar6_sar55_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_48_oct7sar6_sar55_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_48_OCT7SAR6_SAR55_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_48_oct7sar7_sar63_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_48_OCT7SAR7_SAR63_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_48_oct7sar7_sar63_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_48_oct7sar7_sar63_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE2_REG_48_OCT7SAR7_SAR63_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_49_dac_clear_dis_attr == SERDES_LANE_ANA_ADC_LANE2_REG_49_DAC_CLEAR_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_49_dac_clear_force_dfx_attr == SERDES_LANE_ANA_ADC_LANE2_REG_49_DAC_CLEAR_FORCE_DFX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_49_dac_reset_force_dfx_attr == SERDES_LANE_ANA_ADC_LANE2_REG_49_DAC_RESET_FORCE_DFX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_49_i_sar_finish_disable_fw_attr == SERDES_LANE_ANA_ADC_LANE2_REG_49_I_SAR_FINISH_DISABLE_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_49_nob_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_49_osc_speed_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_49_refgen_cm_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_49_refgen_dfx_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_49_rstb_attr == SERDES_LANE_ANA_ADC_LANE2_REG_49_RSTB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_49_sar_array_spare_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_49_th2_bypass_attr == SERDES_LANE_ANA_ADC_LANE2_REG_49_TH2_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_49_th_boost_select_attr == SERDES_LANE_ANA_ADC_LANE2_REG_49_TH_BOOST_SELECT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_4_oct0sar6_sar48_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_4_oct0sar6_sar48_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_4_oct0sar7_sar56_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_4_oct0sar7_sar56_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_50_shrg_align_clk2cdrrst_val_attr == 8'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_50_shrg_align_clk2lgcrst_val_attr == 8'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_50_shrg_align_clkrst_val_attr == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_51_current_control_15pc_ctl1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_51_current_control_15pc_ctl2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_51_current_control_3_ctl2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_51_current_control_7_ctl1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_51_o_25pc_ctl_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_51_o_current_base_dis_attr == SERDES_LANE_ANA_ADC_LANE2_REG_51_O_CURRENT_BASE_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_51_o_dcmon_vbpn_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_51_O_DCMON_VBPN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_51_o_dcmon_vref0_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_51_O_DCMON_VREF0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_51_o_dcmon_vref_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_51_O_DCMON_VREF_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_51_o_dcmonp_vref_inp_attr == SERDES_LANE_ANA_ADC_LANE2_REG_51_O_DCMONP_VREF_INP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_51_o_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_51_O_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_51_res_ref_ladder_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_52_current_control_15pc_ctl1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_52_current_control_15pc_ctl2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_52_current_control_3_ctl2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_52_current_control_7_ctl1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_52_o_25pc_ctl_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_52_o_current_base_dis_attr == SERDES_LANE_ANA_ADC_LANE2_REG_52_O_CURRENT_BASE_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_52_o_dcmon_vbpn_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_52_O_DCMON_VBPN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_52_o_dcmon_vref0_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_52_O_DCMON_VREF0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_52_o_dcmon_vref_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_52_O_DCMON_VREF_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_52_o_dcmonp_vref_inp_attr == SERDES_LANE_ANA_ADC_LANE2_REG_52_O_DCMONP_VREF_INP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_52_o_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_52_O_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_52_res_ref_ladder_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_53_current_control_15pc_ctl1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_53_current_control_15pc_ctl2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_53_current_control_3_ctl2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_53_current_control_7_ctl1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_53_o_25pc_ctl_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_53_o_current_base_dis_attr == SERDES_LANE_ANA_ADC_LANE2_REG_53_O_CURRENT_BASE_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_53_o_dcmon_vbpn_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_53_O_DCMON_VBPN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_53_o_dcmon_vref0_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_53_O_DCMON_VREF0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_53_o_dcmon_vref_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_53_O_DCMON_VREF_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_53_o_dcmonp_vref_inp_attr == SERDES_LANE_ANA_ADC_LANE2_REG_53_O_DCMONP_VREF_INP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_53_o_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_53_O_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_53_res_ref_ladder_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_54_current_control_15pc_ctl1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_54_current_control_15pc_ctl2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_54_current_control_3_ctl2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_54_current_control_7_ctl1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_54_o_25pc_ctl_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_54_o_current_base_dis_attr == SERDES_LANE_ANA_ADC_LANE2_REG_54_O_CURRENT_BASE_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_54_o_dcmon_vbpn_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_54_O_DCMON_VBPN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_54_o_dcmon_vref0_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_54_O_DCMON_VREF0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_54_o_dcmon_vref_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_54_O_DCMON_VREF_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_54_o_dcmonp_vref_inp_attr == SERDES_LANE_ANA_ADC_LANE2_REG_54_O_DCMONP_VREF_INP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_54_o_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_54_O_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_54_res_ref_ladder_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_55_current_control_15pc_ctl1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_55_current_control_15pc_ctl2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_55_current_control_3_ctl2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_55_current_control_7_ctl1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_55_o_25pc_ctl_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_55_o_current_base_dis_attr == SERDES_LANE_ANA_ADC_LANE2_REG_55_O_CURRENT_BASE_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_55_o_dcmon_vbpn_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_55_O_DCMON_VBPN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_55_o_dcmon_vref0_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_55_O_DCMON_VREF0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_55_o_dcmon_vref_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_55_O_DCMON_VREF_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_55_o_dcmonp_vref_inp_attr == SERDES_LANE_ANA_ADC_LANE2_REG_55_O_DCMONP_VREF_INP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_55_o_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_55_O_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_55_res_ref_ladder_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_56_current_control_15pc_ctl1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_56_current_control_15pc_ctl2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_56_current_control_3_ctl2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_56_current_control_7_ctl1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_56_o_25pc_ctl_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_56_o_current_base_dis_attr == SERDES_LANE_ANA_ADC_LANE2_REG_56_O_CURRENT_BASE_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_56_o_dcmon_vbpn_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_56_O_DCMON_VBPN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_56_o_dcmon_vref0_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_56_O_DCMON_VREF0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_56_o_dcmon_vref_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_56_O_DCMON_VREF_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_56_o_dcmonp_vref_inp_attr == SERDES_LANE_ANA_ADC_LANE2_REG_56_O_DCMONP_VREF_INP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_56_o_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_56_O_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_56_res_ref_ladder_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_57_current_control_15pc_ctl1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_57_current_control_15pc_ctl2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_57_current_control_3_ctl2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_57_current_control_7_ctl1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_57_o_25pc_ctl_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_57_o_current_base_dis_attr == SERDES_LANE_ANA_ADC_LANE2_REG_57_O_CURRENT_BASE_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_57_o_dcmon_vbpn_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_57_O_DCMON_VBPN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_57_o_dcmon_vref0_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_57_O_DCMON_VREF0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_57_o_dcmon_vref_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_57_O_DCMON_VREF_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_57_o_dcmonp_vref_inp_attr == SERDES_LANE_ANA_ADC_LANE2_REG_57_O_DCMONP_VREF_INP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_57_o_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_57_O_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_57_res_ref_ladder_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_58_current_control_15pc_ctl1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_58_current_control_15pc_ctl2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_58_current_control_3_ctl2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_58_current_control_7_ctl1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_58_o_25pc_ctl_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_58_o_current_base_dis_attr == SERDES_LANE_ANA_ADC_LANE2_REG_58_O_CURRENT_BASE_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_58_o_dcmon_vbpn_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_58_O_DCMON_VBPN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_58_o_dcmon_vref0_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_58_O_DCMON_VREF0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_58_o_dcmon_vref_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_58_O_DCMON_VREF_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_58_o_dcmonp_vref_inp_attr == SERDES_LANE_ANA_ADC_LANE2_REG_58_O_DCMONP_VREF_INP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_58_o_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_58_O_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_58_res_ref_ladder_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_59_i_psf_cur_trim_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_59_i_psf_cur_trim_spare_attr == SERDES_LANE_ANA_ADC_LANE2_REG_59_I_PSF_CUR_TRIM_SPARE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_59_psf_bias_current_mon_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_59_PSF_BIAS_CURRENT_MON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_59_psf_cm_ctrl_reserved_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_59_psf_dcmon_spare1_attr == SERDES_LANE_ANA_ADC_LANE2_REG_59_PSF_DCMON_SPARE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_59_psf_dcmon_spare2_attr == SERDES_LANE_ANA_ADC_LANE2_REG_59_PSF_DCMON_SPARE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_59_psf_dcmon_spare3_attr == SERDES_LANE_ANA_ADC_LANE2_REG_59_PSF_DCMON_SPARE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_59_psf_dfx_int_out_mon_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_59_PSF_DFX_INT_OUT_MON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_59_psf_integrator_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_59_PSF_INTEGRATOR_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_59_psf_pbias_cas_mon_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_59_PSF_PBIAS_CAS_MON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_59_psf_vref_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_59_PSF_VREF_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_59_th0_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_59_TH0_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_59_th1_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_59_TH1_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_59_th2_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_59_TH2_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_59_th3_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_59_TH3_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_59_th4_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_59_TH4_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_59_th5_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_59_TH5_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_59_th6_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_59_TH6_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_59_th7_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_59_TH7_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_59_th_sw_bypass_attr == SERDES_LANE_ANA_ADC_LANE2_REG_59_TH_SW_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_5_oct1sar0_sar1_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_5_oct1sar0_sar1_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_5_oct1sar1_sar9_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_5_oct1sar1_sar9_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_60_th0_cur_trim_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_60_th1_cur_trim_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_60_th2_cur_trim_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_60_th3_cur_trim_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_60_th4_cur_trim_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_60_th5_cur_trim_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_60_th6_cur_trim_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_60_th7_cur_trim_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_61_th0_psf_ofc_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_61_th1_psf_ofc_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_61_th2_psf_ofc_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_61_th3_psf_ofc_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_61_th4_psf_ofc_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_61_th5_psf_ofc_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_61_th6_psf_ofc_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_61_th7_psf_ofc_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_62_bonus_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_62_dfx_en_mon_attr == SERDES_LANE_ANA_ADC_LANE2_REG_62_DFX_EN_MON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_62_dfx_en_slc_attr == SERDES_LANE_ANA_ADC_LANE2_REG_62_DFX_EN_SLC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_62_th0_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_62_TH0_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_62_th1_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_62_TH1_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_62_th2_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_62_TH2_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_62_th3_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_62_TH3_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_62_th4_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_62_TH4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_62_th5_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_62_TH5_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_62_th6_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_62_TH6_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_62_th7_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_62_TH7_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_62_th_bias_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_62_TH_BIAS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_63_bonus_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_63_sar_dfx_en_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_64_ch4_pi_code_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_64_ch5_pi_code_attr == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_64_ch6_pi_code_attr == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_64_ch7_pi_code_attr == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_65_ch0_pi_code_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_65_ch1_pi_code_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_65_ch2_pi_code_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_65_ch3_pi_code_attr == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_66_c2c_en_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_66_ch0_pi_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_66_CH0_PI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_66_ch0_pi_transp_in_attr == SERDES_LANE_ANA_ADC_LANE2_REG_66_CH0_PI_TRANSP_IN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_66_ch1_pi_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_66_CH1_PI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_66_ch1_pi_transp_in_attr == SERDES_LANE_ANA_ADC_LANE2_REG_66_CH1_PI_TRANSP_IN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_66_ch2_pi_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_66_CH2_PI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_66_ch2_pi_transp_in_attr == SERDES_LANE_ANA_ADC_LANE2_REG_66_CH2_PI_TRANSP_IN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_66_ch3_pi_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_66_CH3_PI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_66_ch3_pi_transp_in_attr == SERDES_LANE_ANA_ADC_LANE2_REG_66_CH3_PI_TRANSP_IN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_66_ch4_pi_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_66_CH4_PI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_66_ch4_pi_transp_in_attr == SERDES_LANE_ANA_ADC_LANE2_REG_66_CH4_PI_TRANSP_IN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_66_ch5_pi_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_66_CH5_PI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_66_ch5_pi_transp_in_attr == SERDES_LANE_ANA_ADC_LANE2_REG_66_CH5_PI_TRANSP_IN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_66_ch6_pi_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_66_CH6_PI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_66_ch6_pi_transp_in_attr == SERDES_LANE_ANA_ADC_LANE2_REG_66_CH6_PI_TRANSP_IN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_66_ch7_pi_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_66_CH7_PI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_66_ch7_pi_transp_in_attr == SERDES_LANE_ANA_ADC_LANE2_REG_66_CH7_PI_TRANSP_IN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_67_dispolarity_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_67_i_clkmux_ungate_req_reg_attr == SERDES_LANE_ANA_ADC_LANE2_REG_67_I_CLKMUX_UNGATE_REQ_REG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_67_i_clkmux_ungate_rst_reg_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_67_spare_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_67_td_degen_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_68_clk2td_ch_sel_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_68_pdo_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_68_PDO_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_68_spare_attr == SERDES_LANE_ANA_ADC_LANE2_REG_68_SPARE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_68_td_en_pd_attr == SERDES_LANE_ANA_ADC_LANE2_REG_68_TD_EN_PD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_68_td_i_ctrl_2ui_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_68_td_i_ctrl_4ui_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_68_td_i_sel_count_stop_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_68_td_rstb_attr == SERDES_LANE_ANA_ADC_LANE2_REG_68_TD_RSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_69_dcmon_cmp_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_69_dcmon_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_69_input_cs_trimming_attr == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_69_nc_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_69_nsf_enable_attr == SERDES_LANE_ANA_ADC_LANE2_REG_69_NSF_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_69_nsf_even_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_69_NSF_EVEN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_69_nsf_odd_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_69_NSF_ODD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_6_oct1sar2_sar17_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_6_oct1sar2_sar17_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_6_oct1sar3_sar25_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_6_oct1sar3_sar25_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_70_i_clkmux_hsmonsel_local_reg_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_70_i_clkmux_hsmonsel_next_reg_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_70_i_clkmux_hsmonseln_reg_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_70_i_clkmux_hsmonselp_reg_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_70_ph_out_seln_attr == SERDES_LANE_ANA_ADC_LANE2_REG_70_PH_OUT_SELN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_71_clk_gen_dcmon_n_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_71_CLK_GEN_DCMON_N_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_71_clk_gen_dcmon_p_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_71_CLK_GEN_DCMON_P_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_71_clkgen_and_sar_l_comp_n_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_71_CLKGEN_AND_SAR_L_COMP_N_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_71_clkgen_and_sar_l_comp_p_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_71_CLKGEN_AND_SAR_L_COMP_P_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_71_clkgen_and_sar_l_dcmon_n_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_71_CLKGEN_AND_SAR_L_DCMON_N_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_71_clkgen_and_sar_l_dcmon_p_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_71_CLKGEN_AND_SAR_L_DCMON_P_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_71_i_sararray_vref_n_attr == SERDES_LANE_ANA_ADC_LANE2_REG_71_I_SARARRAY_VREF_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_71_i_sararray_vref_p_attr == SERDES_LANE_ANA_ADC_LANE2_REG_71_I_SARARRAY_VREF_P_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_71_nsf_th_clkmux_comp_n_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_71_NSF_TH_CLKMUX_COMP_N_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_71_nsf_th_clkmux_comp_p_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_71_NSF_TH_CLKMUX_COMP_P_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_71_nsf_th_clkmux_dcmon_n_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_71_NSF_TH_CLKMUX_DCMON_N_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_71_nsf_th_clkmux_dcmon_p_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_71_NSF_TH_CLKMUX_DCMON_P_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_71_o_sar_dft_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_71_oct3_dfx_en_l_attr == SERDES_LANE_ANA_ADC_LANE2_REG_71_OCT3_DFX_EN_L_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_71_oct3_dfx_en_r_attr == SERDES_LANE_ANA_ADC_LANE2_REG_71_OCT3_DFX_EN_R_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_71_oct7_dfx_en_l_attr == SERDES_LANE_ANA_ADC_LANE2_REG_71_OCT7_DFX_EN_L_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_71_oct7_dfx_en_r_attr == SERDES_LANE_ANA_ADC_LANE2_REG_71_OCT7_DFX_EN_R_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_71_spare_dfx_left_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_72_dcmon2slc_attr == SERDES_LANE_ANA_ADC_LANE2_REG_72_DCMON2SLC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_72_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_72_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_72_dcmon_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_72_ph_out_selp_attr == SERDES_LANE_ANA_ADC_LANE2_REG_72_PH_OUT_SELP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_72_spare_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_73_clkgen_comp_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_73_CLKGEN_COMP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_73_o_sar_dft_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_73_oct0_dfx_en_l_attr == SERDES_LANE_ANA_ADC_LANE2_REG_73_OCT0_DFX_EN_L_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_73_oct0_dfx_en_r_attr == SERDES_LANE_ANA_ADC_LANE2_REG_73_OCT0_DFX_EN_R_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_73_oct2_dfx_en_l_attr == SERDES_LANE_ANA_ADC_LANE2_REG_73_OCT2_DFX_EN_L_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_73_oct2_dfx_en_r_attr == SERDES_LANE_ANA_ADC_LANE2_REG_73_OCT2_DFX_EN_R_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_73_oct4_dfx_en_l_attr == SERDES_LANE_ANA_ADC_LANE2_REG_73_OCT4_DFX_EN_L_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_73_oct4_dfx_en_r_attr == SERDES_LANE_ANA_ADC_LANE2_REG_73_OCT4_DFX_EN_R_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_73_oct6_dfx_en_l_attr == SERDES_LANE_ANA_ADC_LANE2_REG_73_OCT6_DFX_EN_L_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_73_sar_r_comp_n_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_73_SAR_R_COMP_N_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_73_sar_r_comp_p_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_73_SAR_R_COMP_P_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_73_sar_r_dcmon_n_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_73_SAR_R_DCMON_N_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_73_sar_r_dcmon_p_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_73_SAR_R_DCMON_P_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_73_spare_dfx_right_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_74_fall_sel3_attr == 7'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_74_fall_sel5_attr == 7'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_74_fall_sel7_attr == 7'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_74_spare1_reg13_attr == SERDES_LANE_ANA_ADC_LANE2_REG_74_SPARE1_REG13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_74_spare2_reg13_attr == SERDES_LANE_ANA_ADC_LANE2_REG_74_SPARE2_REG13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_74_spare3_reg13_attr == SERDES_LANE_ANA_ADC_LANE2_REG_74_SPARE3_REG13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_75_rise_sel0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_75_rise_sel1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_75_rise_sel2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_75_rise_sel3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_76_spare_reg1_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_77_dfx_seln_attr == 17'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_77_spare1_reg2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_77_spare2_reg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_78_dfx_selp_attr == 17'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_78_spare_reg03_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_79_rise_sel4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_79_rise_sel5_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_79_rise_sel6_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_79_rise_sel7_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_7_oct1sar4_sar33_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_7_oct1sar4_sar33_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_7_oct1sar5_sar41_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_7_oct1sar5_sar41_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_80_c2c_en_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_80_clk_sel_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_80_counter_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_80_COUNTER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_80_dcd_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_80_DCD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_80_dcd_sel_attr == SERDES_LANE_ANA_ADC_LANE2_REG_80_DCD_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_80_dfx_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_80_DFX_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_80_en_dfx_attr == SERDES_LANE_ANA_ADC_LANE2_REG_80_EN_DFX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_80_spare5_reg5_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_81_buffer_bias0_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_81_buffer_bias_dfx_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_81_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_81_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_81_sel_c2c_cascode_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_81_sel_c2c_dc_coarse_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_81_sel_c2c_global_i_attr == 7'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_81_spare_reg6_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_82_bw_sel0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_82_i_a2f_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_82_I_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_82_i_dfx_a2f_boost_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_82_I_DFX_A2F_BOOST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_82_idfx_sel_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_82_sel_cgm_en_attr == SERDES_LANE_ANA_ADC_LANE2_REG_82_SEL_CGM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_82_spare_reg07_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_83_bw_sel1_attr == 15'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_83_res_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_83_spare_reg08_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_84_bw_sel2_attr == 15'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_84_clk_2ui_sel_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_84_spare_reg09_attr == SERDES_LANE_ANA_ADC_LANE2_REG_84_SPARE_REG09_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_85_bw_sel3_attr == 15'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_85_spare_reg10_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_86_fall_sel0_attr == 7'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_86_fall_sel1_attr == 7'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_86_spare1_reg11_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_86_spare2_reg11_attr == SERDES_LANE_ANA_ADC_LANE2_REG_86_SPARE2_REG11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_87_fall_sel2_attr == 7'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_87_fall_sel4_attr == 7'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_87_fall_sel6_attr == 7'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_87_spare1_reg12_attr == SERDES_LANE_ANA_ADC_LANE2_REG_87_SPARE1_REG12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_87_spare2_reg12_attr == SERDES_LANE_ANA_ADC_LANE2_REG_87_SPARE2_REG12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_87_spare3_reg12_attr == SERDES_LANE_ANA_ADC_LANE2_REG_87_SPARE3_REG12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_8_oct1sar6_sar49_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_8_oct1sar6_sar49_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_8_oct1sar7_sar57_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_8_oct1sar7_sar57_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_9_oct2sar0_sar2_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_9_oct2sar0_sar2_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_9_oct2sar1_sar10_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane2_reg_9_oct2sar1_sar10_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_10_oct2sar2_sar18_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_10_oct2sar2_sar18_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_10_oct2sar3_sar26_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_10_oct2sar3_sar26_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_11_oct2sar4_sar34_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_11_oct2sar4_sar34_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_11_oct2sar5_sar42_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_11_oct2sar5_sar42_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_12_oct2sar6_sar50_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_12_oct2sar6_sar50_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_12_oct2sar7_sar58_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_12_oct2sar7_sar58_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_13_oct3sar0_sar3_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_13_oct3sar0_sar3_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_13_oct3sar1_sar11_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_13_oct3sar1_sar11_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_14_oct3sar2_sar19_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_14_oct3sar2_sar19_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_14_oct3sar3_sar27_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_14_oct3sar3_sar27_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_15_oct3sar4_sar35_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_15_oct3sar4_sar35_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_15_oct3sar5_sar43_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_15_oct3sar5_sar43_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_16_oct3sar6_sar51_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_16_oct3sar6_sar51_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_16_oct3sar7_sar59_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_16_oct3sar7_sar59_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_17_oct4sar0_sar4_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_17_oct4sar0_sar4_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_17_oct4sar1_sar12_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_17_oct4sar1_sar12_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_18_oct4sar2_sar20_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_18_oct4sar2_sar20_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_18_oct4sar3_sar28_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_18_oct4sar3_sar28_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_19_oct4sar4_sar36_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_19_oct4sar4_sar36_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_19_oct4sar5_sar44_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_19_oct4sar5_sar44_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_1_oct0sar0_sar0_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_1_oct0sar0_sar0_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_1_oct0sar1_sar8_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_1_oct0sar1_sar8_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_20_oct4sar6_sar52_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_20_oct4sar6_sar52_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_20_oct4sar7_sar60_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_20_oct4sar7_sar60_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_21_oct5sar0_sar5_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_21_oct5sar0_sar5_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_21_oct5sar1_sar13_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_21_oct5sar1_sar13_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_22_oct5sar2_sar21_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_22_oct5sar2_sar21_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_22_oct5sar3_sar29_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_22_oct5sar3_sar29_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_23_oct5sar4_sar37_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_23_oct5sar4_sar37_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_23_oct5sar5_sar45_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_23_oct5sar5_sar45_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_24_oct5sar6_sar53_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_24_oct5sar6_sar53_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_24_oct5sar7_sar61_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_24_oct5sar7_sar61_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_25_oct6sar0_sar6_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_25_oct6sar0_sar6_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_25_oct6sar1_sar14_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_25_oct6sar1_sar14_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_26_oct6sar2_sar22_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_26_oct6sar2_sar22_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_26_oct6sar3_sar30_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_26_oct6sar3_sar30_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_27_oct6sar4_sar38_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_27_oct6sar4_sar38_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_27_oct6sar5_sar46_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_27_oct6sar5_sar46_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_28_oct6sar6_sar54_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_28_oct6sar6_sar54_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_28_oct6sar7_sar62_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_28_oct6sar7_sar62_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_29_oct7sar0_sar7_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_29_oct7sar0_sar7_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_29_oct7sar1_sar15_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_29_oct7sar1_sar15_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_2_oct0sar2_sar16_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_2_oct0sar2_sar16_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_2_oct0sar3_sar24_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_2_oct0sar3_sar24_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_30_oct7sar2_sar23_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_30_oct7sar2_sar23_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_30_oct7sar3_sar31_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_30_oct7sar3_sar31_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_31_oct7sar4_sar39_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_31_oct7sar4_sar39_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_31_oct7sar5_sar47_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_31_oct7sar5_sar47_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_32_oct7sar6_sar55_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_32_oct7sar6_sar55_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_32_oct7sar7_sar63_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_32_oct7sar7_sar63_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_33_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_33_oct0sar2_sar16_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_33_OCT0SAR2_SAR16_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_33_oct0sar2_sar16_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_33_oct0sar2_sar16_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_33_OCT0SAR2_SAR16_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_33_oct0sar3_sar24_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_33_OCT0SAR3_SAR24_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_33_oct0sar3_sar24_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_33_oct0sar3_sar24_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_33_OCT0SAR3_SAR24_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_33_oct0sar4_sar32_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_33_OCT0SAR4_SAR32_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_33_oct0sar4_sar32_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_33_oct0sar4_sar32_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_33_OCT0SAR4_SAR32_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_33_oct0sar5_sar40_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_33_OCT0SAR5_SAR40_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_33_oct0sar5_sar40_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_33_oct0sar5_sar40_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_33_OCT0SAR5_SAR40_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_34_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_34_oct0sar0_sar0_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_34_OCT0SAR0_SAR0_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_34_oct0sar0_sar0_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_34_oct0sar0_sar0_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_34_OCT0SAR0_SAR0_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_34_oct0sar1_sar8_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_34_OCT0SAR1_SAR8_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_34_oct0sar1_sar8_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_34_oct0sar1_sar8_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_34_OCT0SAR1_SAR8_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_34_oct0sar6_sar48_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_34_OCT0SAR6_SAR48_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_34_oct0sar6_sar48_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_34_oct0sar6_sar48_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_34_OCT0SAR6_SAR48_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_34_oct0sar7_sar56_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_34_OCT0SAR7_SAR56_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_34_oct0sar7_sar56_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_34_oct0sar7_sar56_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_34_OCT0SAR7_SAR56_SHRG_INIT_VAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_35_bonus_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_35_glb_div33_en_fw_attr == SERDES_LANE_ANA_ADC_LANE3_REG_35_GLB_DIV33_EN_FW_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_35_oct1sar2_sar17_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_35_OCT1SAR2_SAR17_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_35_oct1sar2_sar17_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_35_oct1sar2_sar17_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_35_OCT1SAR2_SAR17_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_35_oct1sar3_sar25_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_35_OCT1SAR3_SAR25_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_35_oct1sar3_sar25_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_35_oct1sar3_sar25_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_35_OCT1SAR3_SAR25_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_35_oct1sar4_sar33_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_35_OCT1SAR4_SAR33_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_35_oct1sar4_sar33_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_35_oct1sar4_sar33_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_35_OCT1SAR4_SAR33_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_35_oct1sar5_sar41_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_35_OCT1SAR5_SAR41_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_35_oct1sar5_sar41_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_35_oct1sar5_sar41_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_35_OCT1SAR5_SAR41_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_36_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_36_oct1sar0_sar1_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_36_OCT1SAR0_SAR1_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_36_oct1sar0_sar1_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_36_oct1sar0_sar1_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_36_OCT1SAR0_SAR1_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_36_oct1sar1_sar9_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_36_OCT1SAR1_SAR9_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_36_oct1sar1_sar9_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_36_oct1sar1_sar9_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_36_OCT1SAR1_SAR9_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_36_oct1sar6_sar49_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_36_OCT1SAR6_SAR49_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_36_oct1sar6_sar49_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_36_oct1sar6_sar49_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_36_OCT1SAR6_SAR49_SHRG_INIT_VAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_36_oct1sar7_sar57_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_36_OCT1SAR7_SAR57_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_36_oct1sar7_sar57_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_36_oct1sar7_sar57_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_36_OCT1SAR7_SAR57_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_37_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_37_oct2sar2_sar18_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_37_OCT2SAR2_SAR18_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_37_oct2sar2_sar18_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_37_oct2sar2_sar18_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_37_OCT2SAR2_SAR18_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_37_oct2sar3_sar26_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_37_OCT2SAR3_SAR26_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_37_oct2sar3_sar26_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_37_oct2sar3_sar26_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_37_OCT2SAR3_SAR26_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_37_oct2sar4_sar34_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_37_OCT2SAR4_SAR34_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_37_oct2sar4_sar34_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_37_oct2sar4_sar34_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_37_OCT2SAR4_SAR34_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_37_oct2sar5_sar42_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_37_OCT2SAR5_SAR42_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_37_oct2sar5_sar42_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_37_oct2sar5_sar42_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_37_OCT2SAR5_SAR42_SHRG_INIT_VAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_38_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_38_oct2sar0_sar2_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_38_OCT2SAR0_SAR2_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_38_oct2sar0_sar2_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_38_oct2sar0_sar2_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_38_OCT2SAR0_SAR2_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_38_oct2sar1_sar10_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_38_OCT2SAR1_SAR10_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_38_oct2sar1_sar10_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_38_oct2sar1_sar10_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_38_OCT2SAR1_SAR10_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_38_oct2sar6_sar50_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_38_OCT2SAR6_SAR50_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_38_oct2sar6_sar50_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_38_oct2sar6_sar50_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_38_OCT2SAR6_SAR50_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_38_oct2sar7_sar58_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_38_OCT2SAR7_SAR58_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_38_oct2sar7_sar58_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_38_oct2sar7_sar58_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_38_OCT2SAR7_SAR58_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_39_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_39_oct3sar2_sar19_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_39_OCT3SAR2_SAR19_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_39_oct3sar2_sar19_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_39_oct3sar2_sar19_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_39_OCT3SAR2_SAR19_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_39_oct3sar3_sar27_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_39_OCT3SAR3_SAR27_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_39_oct3sar3_sar27_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_39_oct3sar3_sar27_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_39_OCT3SAR3_SAR27_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_39_oct3sar4_sar35_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_39_OCT3SAR4_SAR35_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_39_oct3sar4_sar35_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_39_oct3sar4_sar35_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_39_OCT3SAR4_SAR35_SHRG_INIT_VAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_39_oct3sar5_sar43_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_39_OCT3SAR5_SAR43_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_39_oct3sar5_sar43_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_39_oct3sar5_sar43_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_39_OCT3SAR5_SAR43_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_3_oct0sar4_sar32_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_3_oct0sar4_sar32_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_3_oct0sar5_sar40_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_3_oct0sar5_sar40_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_40_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_40_oct3sar0_sar3_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_40_OCT3SAR0_SAR3_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_40_oct3sar0_sar3_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_40_oct3sar0_sar3_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_40_OCT3SAR0_SAR3_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_40_oct3sar1_sar11_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_40_OCT3SAR1_SAR11_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_40_oct3sar1_sar11_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_40_oct3sar1_sar11_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_40_OCT3SAR1_SAR11_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_40_oct3sar6_sar51_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_40_OCT3SAR6_SAR51_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_40_oct3sar6_sar51_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_40_oct3sar6_sar51_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_40_OCT3SAR6_SAR51_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_40_oct3sar7_sar59_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_40_OCT3SAR7_SAR59_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_40_oct3sar7_sar59_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_40_oct3sar7_sar59_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_40_OCT3SAR7_SAR59_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_41_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_41_oct4sar2_sar20_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_41_OCT4SAR2_SAR20_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_41_oct4sar2_sar20_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_41_oct4sar2_sar20_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_41_OCT4SAR2_SAR20_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_41_oct4sar3_sar28_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_41_OCT4SAR3_SAR28_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_41_oct4sar3_sar28_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_41_oct4sar3_sar28_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_41_OCT4SAR3_SAR28_SHRG_INIT_VAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_41_oct4sar4_sar36_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_41_OCT4SAR4_SAR36_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_41_oct4sar4_sar36_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_41_oct4sar4_sar36_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_41_OCT4SAR4_SAR36_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_41_oct4sar5_sar44_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_41_OCT4SAR5_SAR44_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_41_oct4sar5_sar44_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_41_oct4sar5_sar44_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_41_OCT4SAR5_SAR44_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_42_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_42_oct4sar0_sar4_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_42_OCT4SAR0_SAR4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_42_oct4sar0_sar4_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_42_oct4sar0_sar4_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_42_OCT4SAR0_SAR4_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_42_oct4sar1_sar12_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_42_OCT4SAR1_SAR12_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_42_oct4sar1_sar12_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_42_oct4sar1_sar12_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_42_OCT4SAR1_SAR12_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_42_oct4sar6_sar52_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_42_OCT4SAR6_SAR52_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_42_oct4sar6_sar52_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_42_oct4sar6_sar52_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_42_OCT4SAR6_SAR52_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_42_oct4sar7_sar60_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_42_OCT4SAR7_SAR60_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_42_oct4sar7_sar60_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_42_oct4sar7_sar60_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_42_OCT4SAR7_SAR60_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_43_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_43_oct5sar2_sar21_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_43_OCT5SAR2_SAR21_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_43_oct5sar2_sar21_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_43_oct5sar2_sar21_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_43_OCT5SAR2_SAR21_SHRG_INIT_VAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_43_oct5sar3_sar29_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_43_OCT5SAR3_SAR29_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_43_oct5sar3_sar29_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_43_oct5sar3_sar29_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_43_OCT5SAR3_SAR29_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_43_oct5sar4_sar37_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_43_OCT5SAR4_SAR37_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_43_oct5sar4_sar37_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_43_oct5sar4_sar37_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_43_OCT5SAR4_SAR37_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_43_oct5sar5_sar45_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_43_OCT5SAR5_SAR45_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_43_oct5sar5_sar45_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_43_oct5sar5_sar45_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_43_OCT5SAR5_SAR45_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_44_glb_div10_en_fw_attr == SERDES_LANE_ANA_ADC_LANE3_REG_44_GLB_DIV10_EN_FW_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_44_glb_div33_frac0p25_fw_attr == SERDES_LANE_ANA_ADC_LANE3_REG_44_GLB_DIV33_FRAC0P25_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_44_glb_div33_frac0p5_fw_attr == SERDES_LANE_ANA_ADC_LANE3_REG_44_GLB_DIV33_FRAC0P5_FW_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_44_glb_div33_ratio_fw_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_44_oct5sar0_sar5_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_44_OCT5SAR0_SAR5_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_44_oct5sar0_sar5_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_44_oct5sar0_sar5_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_44_OCT5SAR0_SAR5_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_44_oct5sar1_sar13_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_44_OCT5SAR1_SAR13_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_44_oct5sar1_sar13_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_44_oct5sar1_sar13_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_44_OCT5SAR1_SAR13_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_44_oct5sar6_sar53_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_44_OCT5SAR6_SAR53_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_44_oct5sar6_sar53_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_44_oct5sar6_sar53_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_44_OCT5SAR6_SAR53_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_44_oct5sar7_sar61_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_44_OCT5SAR7_SAR61_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_44_oct5sar7_sar61_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_44_oct5sar7_sar61_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_44_OCT5SAR7_SAR61_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_45_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_45_oct6sar2_sar22_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_45_OCT6SAR2_SAR22_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_45_oct6sar2_sar22_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_45_oct6sar2_sar22_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_45_OCT6SAR2_SAR22_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_45_oct6sar3_sar30_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_45_OCT6SAR3_SAR30_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_45_oct6sar3_sar30_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_45_oct6sar3_sar30_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_45_OCT6SAR3_SAR30_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_45_oct6sar4_sar38_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_45_OCT6SAR4_SAR38_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_45_oct6sar4_sar38_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_45_oct6sar4_sar38_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_45_OCT6SAR4_SAR38_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_45_oct6sar5_sar46_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_45_OCT6SAR5_SAR46_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_45_oct6sar5_sar46_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_45_oct6sar5_sar46_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_45_OCT6SAR5_SAR46_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_46_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_46_oct6sar0_sar6_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_46_OCT6SAR0_SAR6_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_46_oct6sar0_sar6_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_46_oct6sar0_sar6_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_46_OCT6SAR0_SAR6_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_46_oct6sar1_sar14_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_46_OCT6SAR1_SAR14_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_46_oct6sar1_sar14_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_46_oct6sar1_sar14_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_46_OCT6SAR1_SAR14_SHRG_INIT_VAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_46_oct6sar6_sar54_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_46_OCT6SAR6_SAR54_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_46_oct6sar6_sar54_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_46_oct6sar6_sar54_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_46_OCT6SAR6_SAR54_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_46_oct6sar7_sar62_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_46_OCT6SAR7_SAR62_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_46_oct6sar7_sar62_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_46_oct6sar7_sar62_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_46_OCT6SAR7_SAR62_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_47_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_47_oct7sar2_sar23_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_47_OCT7SAR2_SAR23_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_47_oct7sar2_sar23_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_47_oct7sar2_sar23_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_47_OCT7SAR2_SAR23_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_47_oct7sar3_sar31_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_47_OCT7SAR3_SAR31_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_47_oct7sar3_sar31_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_47_oct7sar3_sar31_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_47_OCT7SAR3_SAR31_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_47_oct7sar4_sar39_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_47_OCT7SAR4_SAR39_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_47_oct7sar4_sar39_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_47_oct7sar4_sar39_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_47_OCT7SAR4_SAR39_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_47_oct7sar5_sar47_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_47_OCT7SAR5_SAR47_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_47_oct7sar5_sar47_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_47_oct7sar5_sar47_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_47_OCT7SAR5_SAR47_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_48_bonus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_48_oct7sar0_sar7_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_48_OCT7SAR0_SAR7_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_48_oct7sar0_sar7_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_48_oct7sar0_sar7_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_48_OCT7SAR0_SAR7_SHRG_INIT_VAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_48_oct7sar1_sar15_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_48_OCT7SAR1_SAR15_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_48_oct7sar1_sar15_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_48_oct7sar1_sar15_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_48_OCT7SAR1_SAR15_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_48_oct7sar6_sar55_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_48_OCT7SAR6_SAR55_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_48_oct7sar6_sar55_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_48_oct7sar6_sar55_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_48_OCT7SAR6_SAR55_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_48_oct7sar7_sar63_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_48_OCT7SAR7_SAR63_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_48_oct7sar7_sar63_gain_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_48_oct7sar7_sar63_shrg_init_val_attr == SERDES_LANE_ANA_ADC_LANE3_REG_48_OCT7SAR7_SAR63_SHRG_INIT_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_49_dac_clear_dis_attr == SERDES_LANE_ANA_ADC_LANE3_REG_49_DAC_CLEAR_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_49_dac_clear_force_dfx_attr == SERDES_LANE_ANA_ADC_LANE3_REG_49_DAC_CLEAR_FORCE_DFX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_49_dac_reset_force_dfx_attr == SERDES_LANE_ANA_ADC_LANE3_REG_49_DAC_RESET_FORCE_DFX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_49_i_sar_finish_disable_fw_attr == SERDES_LANE_ANA_ADC_LANE3_REG_49_I_SAR_FINISH_DISABLE_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_49_nob_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_49_osc_speed_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_49_refgen_cm_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_49_refgen_dfx_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_49_rstb_attr == SERDES_LANE_ANA_ADC_LANE3_REG_49_RSTB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_49_sar_array_spare_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_49_th2_bypass_attr == SERDES_LANE_ANA_ADC_LANE3_REG_49_TH2_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_49_th_boost_select_attr == SERDES_LANE_ANA_ADC_LANE3_REG_49_TH_BOOST_SELECT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_4_oct0sar6_sar48_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_4_oct0sar6_sar48_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_4_oct0sar7_sar56_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_4_oct0sar7_sar56_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_50_shrg_align_clk2cdrrst_val_attr == 8'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_50_shrg_align_clk2lgcrst_val_attr == 8'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_50_shrg_align_clkrst_val_attr == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_51_current_control_15pc_ctl1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_51_current_control_15pc_ctl2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_51_current_control_3_ctl2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_51_current_control_7_ctl1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_51_o_25pc_ctl_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_51_o_current_base_dis_attr == SERDES_LANE_ANA_ADC_LANE3_REG_51_O_CURRENT_BASE_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_51_o_dcmon_vbpn_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_51_O_DCMON_VBPN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_51_o_dcmon_vref0_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_51_O_DCMON_VREF0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_51_o_dcmon_vref_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_51_O_DCMON_VREF_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_51_o_dcmonp_vref_inp_attr == SERDES_LANE_ANA_ADC_LANE3_REG_51_O_DCMONP_VREF_INP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_51_o_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_51_O_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_51_res_ref_ladder_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_52_current_control_15pc_ctl1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_52_current_control_15pc_ctl2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_52_current_control_3_ctl2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_52_current_control_7_ctl1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_52_o_25pc_ctl_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_52_o_current_base_dis_attr == SERDES_LANE_ANA_ADC_LANE3_REG_52_O_CURRENT_BASE_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_52_o_dcmon_vbpn_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_52_O_DCMON_VBPN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_52_o_dcmon_vref0_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_52_O_DCMON_VREF0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_52_o_dcmon_vref_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_52_O_DCMON_VREF_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_52_o_dcmonp_vref_inp_attr == SERDES_LANE_ANA_ADC_LANE3_REG_52_O_DCMONP_VREF_INP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_52_o_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_52_O_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_52_res_ref_ladder_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_53_current_control_15pc_ctl1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_53_current_control_15pc_ctl2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_53_current_control_3_ctl2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_53_current_control_7_ctl1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_53_o_25pc_ctl_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_53_o_current_base_dis_attr == SERDES_LANE_ANA_ADC_LANE3_REG_53_O_CURRENT_BASE_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_53_o_dcmon_vbpn_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_53_O_DCMON_VBPN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_53_o_dcmon_vref0_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_53_O_DCMON_VREF0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_53_o_dcmon_vref_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_53_O_DCMON_VREF_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_53_o_dcmonp_vref_inp_attr == SERDES_LANE_ANA_ADC_LANE3_REG_53_O_DCMONP_VREF_INP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_53_o_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_53_O_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_53_res_ref_ladder_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_54_current_control_15pc_ctl1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_54_current_control_15pc_ctl2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_54_current_control_3_ctl2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_54_current_control_7_ctl1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_54_o_25pc_ctl_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_54_o_current_base_dis_attr == SERDES_LANE_ANA_ADC_LANE3_REG_54_O_CURRENT_BASE_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_54_o_dcmon_vbpn_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_54_O_DCMON_VBPN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_54_o_dcmon_vref0_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_54_O_DCMON_VREF0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_54_o_dcmon_vref_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_54_O_DCMON_VREF_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_54_o_dcmonp_vref_inp_attr == SERDES_LANE_ANA_ADC_LANE3_REG_54_O_DCMONP_VREF_INP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_54_o_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_54_O_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_54_res_ref_ladder_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_55_current_control_15pc_ctl1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_55_current_control_15pc_ctl2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_55_current_control_3_ctl2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_55_current_control_7_ctl1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_55_o_25pc_ctl_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_55_o_current_base_dis_attr == SERDES_LANE_ANA_ADC_LANE3_REG_55_O_CURRENT_BASE_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_55_o_dcmon_vbpn_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_55_O_DCMON_VBPN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_55_o_dcmon_vref0_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_55_O_DCMON_VREF0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_55_o_dcmon_vref_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_55_O_DCMON_VREF_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_55_o_dcmonp_vref_inp_attr == SERDES_LANE_ANA_ADC_LANE3_REG_55_O_DCMONP_VREF_INP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_55_o_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_55_O_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_55_res_ref_ladder_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_56_current_control_15pc_ctl1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_56_current_control_15pc_ctl2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_56_current_control_3_ctl2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_56_current_control_7_ctl1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_56_o_25pc_ctl_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_56_o_current_base_dis_attr == SERDES_LANE_ANA_ADC_LANE3_REG_56_O_CURRENT_BASE_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_56_o_dcmon_vbpn_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_56_O_DCMON_VBPN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_56_o_dcmon_vref0_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_56_O_DCMON_VREF0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_56_o_dcmon_vref_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_56_O_DCMON_VREF_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_56_o_dcmonp_vref_inp_attr == SERDES_LANE_ANA_ADC_LANE3_REG_56_O_DCMONP_VREF_INP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_56_o_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_56_O_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_56_res_ref_ladder_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_57_current_control_15pc_ctl1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_57_current_control_15pc_ctl2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_57_current_control_3_ctl2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_57_current_control_7_ctl1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_57_o_25pc_ctl_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_57_o_current_base_dis_attr == SERDES_LANE_ANA_ADC_LANE3_REG_57_O_CURRENT_BASE_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_57_o_dcmon_vbpn_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_57_O_DCMON_VBPN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_57_o_dcmon_vref0_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_57_O_DCMON_VREF0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_57_o_dcmon_vref_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_57_O_DCMON_VREF_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_57_o_dcmonp_vref_inp_attr == SERDES_LANE_ANA_ADC_LANE3_REG_57_O_DCMONP_VREF_INP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_57_o_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_57_O_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_57_res_ref_ladder_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_58_current_control_15pc_ctl1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_58_current_control_15pc_ctl2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_58_current_control_3_ctl2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_58_current_control_7_ctl1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_58_o_25pc_ctl_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_58_o_current_base_dis_attr == SERDES_LANE_ANA_ADC_LANE3_REG_58_O_CURRENT_BASE_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_58_o_dcmon_vbpn_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_58_O_DCMON_VBPN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_58_o_dcmon_vref0_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_58_O_DCMON_VREF0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_58_o_dcmon_vref_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_58_O_DCMON_VREF_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_58_o_dcmonp_vref_inp_attr == SERDES_LANE_ANA_ADC_LANE3_REG_58_O_DCMONP_VREF_INP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_58_o_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_58_O_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_58_res_ref_ladder_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_59_i_psf_cur_trim_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_59_i_psf_cur_trim_spare_attr == SERDES_LANE_ANA_ADC_LANE3_REG_59_I_PSF_CUR_TRIM_SPARE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_59_psf_bias_current_mon_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_59_PSF_BIAS_CURRENT_MON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_59_psf_cm_ctrl_reserved_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_59_psf_dcmon_spare1_attr == SERDES_LANE_ANA_ADC_LANE3_REG_59_PSF_DCMON_SPARE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_59_psf_dcmon_spare2_attr == SERDES_LANE_ANA_ADC_LANE3_REG_59_PSF_DCMON_SPARE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_59_psf_dcmon_spare3_attr == SERDES_LANE_ANA_ADC_LANE3_REG_59_PSF_DCMON_SPARE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_59_psf_dfx_int_out_mon_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_59_PSF_DFX_INT_OUT_MON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_59_psf_integrator_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_59_PSF_INTEGRATOR_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_59_psf_pbias_cas_mon_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_59_PSF_PBIAS_CAS_MON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_59_psf_vref_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_59_PSF_VREF_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_59_th0_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_59_TH0_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_59_th1_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_59_TH1_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_59_th2_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_59_TH2_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_59_th3_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_59_TH3_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_59_th4_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_59_TH4_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_59_th5_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_59_TH5_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_59_th6_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_59_TH6_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_59_th7_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_59_TH7_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_59_th_sw_bypass_attr == SERDES_LANE_ANA_ADC_LANE3_REG_59_TH_SW_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_5_oct1sar0_sar1_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_5_oct1sar0_sar1_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_5_oct1sar1_sar9_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_5_oct1sar1_sar9_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_60_th0_cur_trim_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_60_th1_cur_trim_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_60_th2_cur_trim_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_60_th3_cur_trim_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_60_th4_cur_trim_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_60_th5_cur_trim_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_60_th6_cur_trim_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_60_th7_cur_trim_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_61_th0_psf_ofc_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_61_th1_psf_ofc_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_61_th2_psf_ofc_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_61_th3_psf_ofc_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_61_th4_psf_ofc_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_61_th5_psf_ofc_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_61_th6_psf_ofc_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_61_th7_psf_ofc_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_62_bonus_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_62_dfx_en_mon_attr == SERDES_LANE_ANA_ADC_LANE3_REG_62_DFX_EN_MON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_62_dfx_en_slc_attr == SERDES_LANE_ANA_ADC_LANE3_REG_62_DFX_EN_SLC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_62_th0_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_62_TH0_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_62_th1_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_62_TH1_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_62_th2_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_62_TH2_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_62_th3_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_62_TH3_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_62_th4_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_62_TH4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_62_th5_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_62_TH5_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_62_th6_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_62_TH6_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_62_th7_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_62_TH7_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_62_th_bias_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_62_TH_BIAS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_63_bonus_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_63_sar_dfx_en_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_64_ch4_pi_code_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_64_ch5_pi_code_attr == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_64_ch6_pi_code_attr == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_64_ch7_pi_code_attr == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_65_ch0_pi_code_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_65_ch1_pi_code_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_65_ch2_pi_code_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_65_ch3_pi_code_attr == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_66_c2c_en_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_66_ch0_pi_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_66_CH0_PI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_66_ch0_pi_transp_in_attr == SERDES_LANE_ANA_ADC_LANE3_REG_66_CH0_PI_TRANSP_IN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_66_ch1_pi_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_66_CH1_PI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_66_ch1_pi_transp_in_attr == SERDES_LANE_ANA_ADC_LANE3_REG_66_CH1_PI_TRANSP_IN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_66_ch2_pi_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_66_CH2_PI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_66_ch2_pi_transp_in_attr == SERDES_LANE_ANA_ADC_LANE3_REG_66_CH2_PI_TRANSP_IN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_66_ch3_pi_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_66_CH3_PI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_66_ch3_pi_transp_in_attr == SERDES_LANE_ANA_ADC_LANE3_REG_66_CH3_PI_TRANSP_IN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_66_ch4_pi_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_66_CH4_PI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_66_ch4_pi_transp_in_attr == SERDES_LANE_ANA_ADC_LANE3_REG_66_CH4_PI_TRANSP_IN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_66_ch5_pi_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_66_CH5_PI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_66_ch5_pi_transp_in_attr == SERDES_LANE_ANA_ADC_LANE3_REG_66_CH5_PI_TRANSP_IN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_66_ch6_pi_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_66_CH6_PI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_66_ch6_pi_transp_in_attr == SERDES_LANE_ANA_ADC_LANE3_REG_66_CH6_PI_TRANSP_IN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_66_ch7_pi_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_66_CH7_PI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_66_ch7_pi_transp_in_attr == SERDES_LANE_ANA_ADC_LANE3_REG_66_CH7_PI_TRANSP_IN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_67_dispolarity_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_67_i_clkmux_ungate_req_reg_attr == SERDES_LANE_ANA_ADC_LANE3_REG_67_I_CLKMUX_UNGATE_REQ_REG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_67_i_clkmux_ungate_rst_reg_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_67_spare_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_67_td_degen_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_68_clk2td_ch_sel_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_68_pdo_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_68_PDO_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_68_spare_attr == SERDES_LANE_ANA_ADC_LANE3_REG_68_SPARE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_68_td_en_pd_attr == SERDES_LANE_ANA_ADC_LANE3_REG_68_TD_EN_PD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_68_td_i_ctrl_2ui_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_68_td_i_ctrl_4ui_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_68_td_i_sel_count_stop_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_68_td_rstb_attr == SERDES_LANE_ANA_ADC_LANE3_REG_68_TD_RSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_69_dcmon_cmp_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_69_dcmon_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_69_input_cs_trimming_attr == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_69_nc_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_69_nsf_enable_attr == SERDES_LANE_ANA_ADC_LANE3_REG_69_NSF_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_69_nsf_even_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_69_NSF_EVEN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_69_nsf_odd_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_69_NSF_ODD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_6_oct1sar2_sar17_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_6_oct1sar2_sar17_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_6_oct1sar3_sar25_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_6_oct1sar3_sar25_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_70_i_clkmux_hsmonsel_local_reg_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_70_i_clkmux_hsmonsel_next_reg_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_70_i_clkmux_hsmonseln_reg_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_70_i_clkmux_hsmonselp_reg_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_70_ph_out_seln_attr == SERDES_LANE_ANA_ADC_LANE3_REG_70_PH_OUT_SELN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_71_clk_gen_dcmon_n_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_71_CLK_GEN_DCMON_N_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_71_clk_gen_dcmon_p_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_71_CLK_GEN_DCMON_P_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_71_clkgen_and_sar_l_comp_n_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_71_CLKGEN_AND_SAR_L_COMP_N_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_71_clkgen_and_sar_l_comp_p_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_71_CLKGEN_AND_SAR_L_COMP_P_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_71_clkgen_and_sar_l_dcmon_n_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_71_CLKGEN_AND_SAR_L_DCMON_N_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_71_clkgen_and_sar_l_dcmon_p_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_71_CLKGEN_AND_SAR_L_DCMON_P_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_71_i_sararray_vref_n_attr == SERDES_LANE_ANA_ADC_LANE3_REG_71_I_SARARRAY_VREF_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_71_i_sararray_vref_p_attr == SERDES_LANE_ANA_ADC_LANE3_REG_71_I_SARARRAY_VREF_P_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_71_nsf_th_clkmux_comp_n_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_71_NSF_TH_CLKMUX_COMP_N_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_71_nsf_th_clkmux_comp_p_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_71_NSF_TH_CLKMUX_COMP_P_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_71_nsf_th_clkmux_dcmon_n_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_71_NSF_TH_CLKMUX_DCMON_N_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_71_nsf_th_clkmux_dcmon_p_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_71_NSF_TH_CLKMUX_DCMON_P_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_71_o_sar_dft_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_71_oct3_dfx_en_l_attr == SERDES_LANE_ANA_ADC_LANE3_REG_71_OCT3_DFX_EN_L_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_71_oct3_dfx_en_r_attr == SERDES_LANE_ANA_ADC_LANE3_REG_71_OCT3_DFX_EN_R_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_71_oct7_dfx_en_l_attr == SERDES_LANE_ANA_ADC_LANE3_REG_71_OCT7_DFX_EN_L_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_71_oct7_dfx_en_r_attr == SERDES_LANE_ANA_ADC_LANE3_REG_71_OCT7_DFX_EN_R_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_71_spare_dfx_left_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_72_dcmon2slc_attr == SERDES_LANE_ANA_ADC_LANE3_REG_72_DCMON2SLC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_72_dcmon_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_72_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_72_dcmon_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_72_ph_out_selp_attr == SERDES_LANE_ANA_ADC_LANE3_REG_72_PH_OUT_SELP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_72_spare_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_73_clkgen_comp_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_73_CLKGEN_COMP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_73_o_sar_dft_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_73_oct0_dfx_en_l_attr == SERDES_LANE_ANA_ADC_LANE3_REG_73_OCT0_DFX_EN_L_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_73_oct0_dfx_en_r_attr == SERDES_LANE_ANA_ADC_LANE3_REG_73_OCT0_DFX_EN_R_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_73_oct2_dfx_en_l_attr == SERDES_LANE_ANA_ADC_LANE3_REG_73_OCT2_DFX_EN_L_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_73_oct2_dfx_en_r_attr == SERDES_LANE_ANA_ADC_LANE3_REG_73_OCT2_DFX_EN_R_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_73_oct4_dfx_en_l_attr == SERDES_LANE_ANA_ADC_LANE3_REG_73_OCT4_DFX_EN_L_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_73_oct4_dfx_en_r_attr == SERDES_LANE_ANA_ADC_LANE3_REG_73_OCT4_DFX_EN_R_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_73_oct6_dfx_en_l_attr == SERDES_LANE_ANA_ADC_LANE3_REG_73_OCT6_DFX_EN_L_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_73_sar_r_comp_n_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_73_SAR_R_COMP_N_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_73_sar_r_comp_p_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_73_SAR_R_COMP_P_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_73_sar_r_dcmon_n_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_73_SAR_R_DCMON_N_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_73_sar_r_dcmon_p_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_73_SAR_R_DCMON_P_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_73_spare_dfx_right_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_74_fall_sel3_attr == 7'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_74_fall_sel5_attr == 7'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_74_fall_sel7_attr == 7'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_74_spare1_reg13_attr == SERDES_LANE_ANA_ADC_LANE3_REG_74_SPARE1_REG13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_74_spare2_reg13_attr == SERDES_LANE_ANA_ADC_LANE3_REG_74_SPARE2_REG13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_74_spare3_reg13_attr == SERDES_LANE_ANA_ADC_LANE3_REG_74_SPARE3_REG13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_75_rise_sel0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_75_rise_sel1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_75_rise_sel2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_75_rise_sel3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_76_spare_reg1_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_77_dfx_seln_attr == 17'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_77_spare1_reg2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_77_spare2_reg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_78_dfx_selp_attr == 17'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_78_spare_reg03_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_79_rise_sel4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_79_rise_sel5_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_79_rise_sel6_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_79_rise_sel7_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_7_oct1sar4_sar33_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_7_oct1sar4_sar33_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_7_oct1sar5_sar41_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_7_oct1sar5_sar41_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_80_c2c_en_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_80_clk_sel_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_80_counter_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_80_COUNTER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_80_dcd_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_80_DCD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_80_dcd_sel_attr == SERDES_LANE_ANA_ADC_LANE3_REG_80_DCD_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_80_dfx_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_80_DFX_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_80_en_dfx_attr == SERDES_LANE_ANA_ADC_LANE3_REG_80_EN_DFX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_80_spare5_reg5_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_81_buffer_bias0_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_81_buffer_bias_dfx_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_81_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_81_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_81_sel_c2c_cascode_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_81_sel_c2c_dc_coarse_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_81_sel_c2c_global_i_attr == 7'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_81_spare_reg6_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_82_bw_sel0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_82_i_a2f_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_82_I_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_82_i_dfx_a2f_boost_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_82_I_DFX_A2F_BOOST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_82_idfx_sel_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_82_sel_cgm_en_attr == SERDES_LANE_ANA_ADC_LANE3_REG_82_SEL_CGM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_82_spare_reg07_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_83_bw_sel1_attr == 15'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_83_res_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_83_spare_reg08_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_84_bw_sel2_attr == 15'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_84_clk_2ui_sel_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_84_spare_reg09_attr == SERDES_LANE_ANA_ADC_LANE3_REG_84_SPARE_REG09_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_85_bw_sel3_attr == 15'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_85_spare_reg10_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_86_fall_sel0_attr == 7'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_86_fall_sel1_attr == 7'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_86_spare1_reg11_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_86_spare2_reg11_attr == SERDES_LANE_ANA_ADC_LANE3_REG_86_SPARE2_REG11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_87_fall_sel2_attr == 7'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_87_fall_sel4_attr == 7'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_87_fall_sel6_attr == 7'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_87_spare1_reg12_attr == SERDES_LANE_ANA_ADC_LANE3_REG_87_SPARE1_REG12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_87_spare2_reg12_attr == SERDES_LANE_ANA_ADC_LANE3_REG_87_SPARE2_REG12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_87_spare3_reg12_attr == SERDES_LANE_ANA_ADC_LANE3_REG_87_SPARE3_REG12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_8_oct1sar6_sar49_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_8_oct1sar6_sar49_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_8_oct1sar7_sar57_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_8_oct1sar7_sar57_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_9_oct2sar0_sar2_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_9_oct2sar0_sar2_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_9_oct2sar1_sar10_slc1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_adc_lane3_reg_9_oct2sar1_sar10_slc2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_10_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_11_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_12_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_13_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_13_cfg_plllock_state_sel_attr == SERDES_LANE_ANA_PLL_LANE0_REG_13_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_13_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_18_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_18_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_18_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_18_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_18_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_18_cfg_dcocoarse_ovrden_attr == SERDES_LANE_ANA_PLL_LANE0_REG_18_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_18_cfg_full_range_afc_sel_attr == SERDES_LANE_ANA_PLL_LANE0_REG_18_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_19_cfg_boost_dtr_const_zeta_attr == SERDES_LANE_ANA_PLL_LANE0_REG_19_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_19_cfg_boost_fine_const_zeta_attr == SERDES_LANE_ANA_PLL_LANE0_REG_19_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_19_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_19_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_19_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_19_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_19_cfg_filter_boostfade_dtr_en_attr == SERDES_LANE_ANA_PLL_LANE0_REG_19_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_19_cfg_filter_boostfade_fine_en_attr == SERDES_LANE_ANA_PLL_LANE0_REG_19_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_19_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_19_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_1_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_1_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_1_o_fracnen_h_attr == SERDES_LANE_ANA_PLL_LANE0_REG_1_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_20_cfg_dtr_earlylock_sel_attr == SERDES_LANE_ANA_PLL_LANE0_REG_20_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_20_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_20_cfg_dtr_final_code_sel_attr == SERDES_LANE_ANA_PLL_LANE0_REG_20_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_20_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_20_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_20_cfg_fine_int_coeff_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_20_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_20_cfg_fine_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_20_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_21_cfg_dcosettle_mode_attr == SERDES_LANE_ANA_PLL_LANE0_REG_21_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_21_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_21_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_21_cfg_dtr_ovrden_attr == SERDES_LANE_ANA_PLL_LANE0_REG_21_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_21_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_21_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_21_cfg_skip_second_afc_calib_attr == SERDES_LANE_ANA_PLL_LANE0_REG_21_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_21_cfg_stay_fll_attr == SERDES_LANE_ANA_PLL_LANE0_REG_21_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_21_cfg_stay_pll_attr == SERDES_LANE_ANA_PLL_LANE0_REG_21_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_21_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_21_cfg_tdcbbpd_en_attr == SERDES_LANE_ANA_PLL_LANE0_REG_21_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_22_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_22_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_22_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_22_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_22_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_22_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_22_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_22_cfg_ssc_track_en_attr == SERDES_LANE_ANA_PLL_LANE0_REG_22_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_22_cfg_temp_track_en_attr == SERDES_LANE_ANA_PLL_LANE0_REG_22_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_23_cfg_cb56_lane32div_en_attr == SERDES_LANE_ANA_PLL_LANE0_REG_23_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_23_cfg_clkouten_cb_attr == SERDES_LANE_ANA_PLL_LANE0_REG_23_CFG_CLKOUTEN_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_23_cfg_clkouten_lane_attr == SERDES_LANE_ANA_PLL_LANE0_REG_23_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_23_cfg_fbdiv_rat0p5_attr == SERDES_LANE_ANA_PLL_LANE0_REG_23_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_23_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_23_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_23_cfg_pcs3334_divsel_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_23_cfg_pcs3334div_en_attr == SERDES_LANE_ANA_PLL_LANE0_REG_23_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_23_cfg_pcs40div_en_attr == SERDES_LANE_ANA_PLL_LANE0_REG_23_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_23_cfg_pll_bypass_attr == SERDES_LANE_ANA_PLL_LANE0_REG_23_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_23_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_23_cfg_refclk100div_en_attr == SERDES_LANE_ANA_PLL_LANE0_REG_23_CFG_REFCLK100DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_23_cfg_refclk156div_en_attr == SERDES_LANE_ANA_PLL_LANE0_REG_23_CFG_REFCLK156DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_23_cfg_sddiv_en_attr == SERDES_LANE_ANA_PLL_LANE0_REG_23_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_23_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_23_cfg_sddtr_clk_sel_attr == SERDES_LANE_ANA_PLL_LANE0_REG_23_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_24_cfg_a2f_en_attr == SERDES_LANE_ANA_PLL_LANE0_REG_24_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_24_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_24_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_24_cfg_en_peak_sense_attr == SERDES_LANE_ANA_PLL_LANE0_REG_24_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_24_cfg_force_vreglpfbyp_attr == SERDES_LANE_ANA_PLL_LANE0_REG_24_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_24_cfg_obsmux0_del_attr == SERDES_LANE_ANA_PLL_LANE0_REG_24_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_24_cfg_obsmux1_del_attr == SERDES_LANE_ANA_PLL_LANE0_REG_24_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_24_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_24_cfg_ref156div_rat0p5_attr == SERDES_LANE_ANA_PLL_LANE0_REG_24_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_24_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_24_cfg_ss_comp_out_sel_attr == SERDES_LANE_ANA_PLL_LANE0_REG_24_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_24_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_25_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_LANE_ANA_PLL_LANE0_REG_25_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_25_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_LANE_ANA_PLL_LANE0_REG_25_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_25_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_LANE_ANA_PLL_LANE0_REG_25_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_25_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_LANE_ANA_PLL_LANE0_REG_25_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_25_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_25_cfg_dfx_ramp_dir_ovr_attr == SERDES_LANE_ANA_PLL_LANE0_REG_25_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_25_cfg_dfx_ramp_enable_ovr_attr == SERDES_LANE_ANA_PLL_LANE0_REG_25_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_25_cfg_dfx_ramp_toggle_en_attr == SERDES_LANE_ANA_PLL_LANE0_REG_25_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_25_cfg_dpso_bypass_mode_attr == SERDES_LANE_ANA_PLL_LANE0_REG_25_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_25_cfg_dtr_modulation_en_attr == SERDES_LANE_ANA_PLL_LANE0_REG_25_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_25_cfg_fine_modulation_en_attr == SERDES_LANE_ANA_PLL_LANE0_REG_25_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_25_cfg_fine_modulation_sel_attr == SERDES_LANE_ANA_PLL_LANE0_REG_25_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_25_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_25_cfg_tdcpe_modulation_en_attr == SERDES_LANE_ANA_PLL_LANE0_REG_25_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_25_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_25_cfg_vreg_dac_modulation_en_attr == SERDES_LANE_ANA_PLL_LANE0_REG_25_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_26_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_26_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_26_cfg_fbdiv_clkgate_attr == SERDES_LANE_ANA_PLL_LANE0_REG_26_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_26_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_27_cfg_calib_comp_out_sel_attr == SERDES_LANE_ANA_PLL_LANE0_REG_27_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_27_cfg_fw_force_vreg_cal_done_attr == SERDES_LANE_ANA_PLL_LANE0_REG_27_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_27_cfg_fw_vreg_accum_ovrd_attr == SERDES_LANE_ANA_PLL_LANE0_REG_27_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_27_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_27_cfg_inv_vpeak_comb_fb_attr == SERDES_LANE_ANA_PLL_LANE0_REG_27_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_27_cfg_inv_vreg_comb_fb_attr == SERDES_LANE_ANA_PLL_LANE0_REG_27_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_27_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_27_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_27_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_27_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_28_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_28_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_29_cfg_dft_freq_meas_enable_attr == SERDES_LANE_ANA_PLL_LANE0_REG_29_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_29_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_29_cfg_kvcc_inv_polarity_attr == SERDES_LANE_ANA_PLL_LANE0_REG_29_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_29_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_29_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_29_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_29_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_29_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_2_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_2_cfg_fracn_sd_step_en_attr == SERDES_LANE_ANA_PLL_LANE0_REG_2_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_2_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_30_cfg_force_kvcc_done_attr == SERDES_LANE_ANA_PLL_LANE0_REG_30_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_30_cfg_kvcc_calib_by_fw_attr == SERDES_LANE_ANA_PLL_LANE0_REG_30_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_30_cfg_kvcc_code_ovrd_attr == SERDES_LANE_ANA_PLL_LANE0_REG_30_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_30_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_30_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_LANE_ANA_PLL_LANE0_REG_30_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_30_cfg_kvcc_vreg_offset_en_val_attr == SERDES_LANE_ANA_PLL_LANE0_REG_30_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_31_cfg_spare_dig2ana_attr == 18'd10240
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_3_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_3_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_3_o_tdc_fine_res_attr == SERDES_LANE_ANA_PLL_LANE0_REG_3_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_3_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_4_cfg_sigma_delta2_sel_attr == SERDES_LANE_ANA_PLL_LANE0_REG_4_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_4_o_dcoditheren_h_attr == SERDES_LANE_ANA_PLL_LANE0_REG_4_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_4_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_4_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_4_o_fbdiv_strobe_h_attr == SERDES_LANE_ANA_PLL_LANE0_REG_4_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_4_o_feedfwrdcal_en_h_attr == SERDES_LANE_ANA_PLL_LANE0_REG_4_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_4_o_feedfwrdcal_pause_h_attr == SERDES_LANE_ANA_PLL_LANE0_REG_4_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_4_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_4_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_5_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_5_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_6_cfg_tdc_bb_input_sel_attr == SERDES_LANE_ANA_PLL_LANE0_REG_6_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_6_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_6_o_bbinlock_h_attr == SERDES_LANE_ANA_PLL_LANE0_REG_6_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_6_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_6_o_tdcdc_en_h_attr == SERDES_LANE_ANA_PLL_LANE0_REG_6_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_6_o_tdcovccorr_en_h_attr == SERDES_LANE_ANA_PLL_LANE0_REG_6_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_6_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_7_o_dfx_tdc_disable_attr == SERDES_LANE_ANA_PLL_LANE0_REG_7_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_7_o_pll_reg_resetb_attr == SERDES_LANE_ANA_PLL_LANE0_REG_7_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_7_o_pll_reg_resetb_mode_ctrl_attr == SERDES_LANE_ANA_PLL_LANE0_REG_7_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_7_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_7_o_plllc_regen_h_attr == SERDES_LANE_ANA_PLL_LANE0_REG_7_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_8_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_8_o_dcocoarse_ovrd_h_attr == SERDES_LANE_ANA_PLL_LANE0_REG_8_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_8_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_8_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_9_cfg_dft_cnt_restart_attr == SERDES_LANE_ANA_PLL_LANE0_REG_9_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_9_cfg_force_tdcdone_at_afcdone_attr == SERDES_LANE_ANA_PLL_LANE0_REG_9_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_9_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_9_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_9_o_tdccalexten_h_attr == SERDES_LANE_ANA_PLL_LANE0_REG_9_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_9_o_tdcroen_h_attr == SERDES_LANE_ANA_PLL_LANE0_REG_9_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane0_reg_9_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_10_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_11_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_12_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_13_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_13_cfg_plllock_state_sel_attr == SERDES_LANE_ANA_PLL_LANE1_REG_13_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_13_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_18_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_18_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_18_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_18_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_18_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_18_cfg_dcocoarse_ovrden_attr == SERDES_LANE_ANA_PLL_LANE1_REG_18_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_18_cfg_full_range_afc_sel_attr == SERDES_LANE_ANA_PLL_LANE1_REG_18_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_19_cfg_boost_dtr_const_zeta_attr == SERDES_LANE_ANA_PLL_LANE1_REG_19_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_19_cfg_boost_fine_const_zeta_attr == SERDES_LANE_ANA_PLL_LANE1_REG_19_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_19_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_19_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_19_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_19_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_19_cfg_filter_boostfade_dtr_en_attr == SERDES_LANE_ANA_PLL_LANE1_REG_19_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_19_cfg_filter_boostfade_fine_en_attr == SERDES_LANE_ANA_PLL_LANE1_REG_19_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_19_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_19_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_1_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_1_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_1_o_fracnen_h_attr == SERDES_LANE_ANA_PLL_LANE1_REG_1_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_20_cfg_dtr_earlylock_sel_attr == SERDES_LANE_ANA_PLL_LANE1_REG_20_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_20_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_20_cfg_dtr_final_code_sel_attr == SERDES_LANE_ANA_PLL_LANE1_REG_20_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_20_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_20_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_20_cfg_fine_int_coeff_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_20_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_20_cfg_fine_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_20_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_21_cfg_dcosettle_mode_attr == SERDES_LANE_ANA_PLL_LANE1_REG_21_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_21_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_21_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_21_cfg_dtr_ovrden_attr == SERDES_LANE_ANA_PLL_LANE1_REG_21_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_21_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_21_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_21_cfg_skip_second_afc_calib_attr == SERDES_LANE_ANA_PLL_LANE1_REG_21_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_21_cfg_stay_fll_attr == SERDES_LANE_ANA_PLL_LANE1_REG_21_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_21_cfg_stay_pll_attr == SERDES_LANE_ANA_PLL_LANE1_REG_21_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_21_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_21_cfg_tdcbbpd_en_attr == SERDES_LANE_ANA_PLL_LANE1_REG_21_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_22_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_22_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_22_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_22_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_22_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_22_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_22_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_22_cfg_ssc_track_en_attr == SERDES_LANE_ANA_PLL_LANE1_REG_22_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_22_cfg_temp_track_en_attr == SERDES_LANE_ANA_PLL_LANE1_REG_22_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_23_cfg_cb56_lane32div_en_attr == SERDES_LANE_ANA_PLL_LANE1_REG_23_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_23_cfg_clkouten_cb_attr == SERDES_LANE_ANA_PLL_LANE1_REG_23_CFG_CLKOUTEN_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_23_cfg_clkouten_lane_attr == SERDES_LANE_ANA_PLL_LANE1_REG_23_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_23_cfg_fbdiv_rat0p5_attr == SERDES_LANE_ANA_PLL_LANE1_REG_23_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_23_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_23_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_23_cfg_pcs3334_divsel_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_23_cfg_pcs3334div_en_attr == SERDES_LANE_ANA_PLL_LANE1_REG_23_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_23_cfg_pcs40div_en_attr == SERDES_LANE_ANA_PLL_LANE1_REG_23_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_23_cfg_pll_bypass_attr == SERDES_LANE_ANA_PLL_LANE1_REG_23_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_23_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_23_cfg_refclk100div_en_attr == SERDES_LANE_ANA_PLL_LANE1_REG_23_CFG_REFCLK100DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_23_cfg_refclk156div_en_attr == SERDES_LANE_ANA_PLL_LANE1_REG_23_CFG_REFCLK156DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_23_cfg_sddiv_en_attr == SERDES_LANE_ANA_PLL_LANE1_REG_23_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_23_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_23_cfg_sddtr_clk_sel_attr == SERDES_LANE_ANA_PLL_LANE1_REG_23_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_24_cfg_a2f_en_attr == SERDES_LANE_ANA_PLL_LANE1_REG_24_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_24_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_24_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_24_cfg_en_peak_sense_attr == SERDES_LANE_ANA_PLL_LANE1_REG_24_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_24_cfg_force_vreglpfbyp_attr == SERDES_LANE_ANA_PLL_LANE1_REG_24_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_24_cfg_obsmux0_del_attr == SERDES_LANE_ANA_PLL_LANE1_REG_24_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_24_cfg_obsmux1_del_attr == SERDES_LANE_ANA_PLL_LANE1_REG_24_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_24_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_24_cfg_ref156div_rat0p5_attr == SERDES_LANE_ANA_PLL_LANE1_REG_24_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_24_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_24_cfg_ss_comp_out_sel_attr == SERDES_LANE_ANA_PLL_LANE1_REG_24_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_24_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_25_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_LANE_ANA_PLL_LANE1_REG_25_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_25_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_LANE_ANA_PLL_LANE1_REG_25_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_25_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_LANE_ANA_PLL_LANE1_REG_25_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_25_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_LANE_ANA_PLL_LANE1_REG_25_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_25_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_25_cfg_dfx_ramp_dir_ovr_attr == SERDES_LANE_ANA_PLL_LANE1_REG_25_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_25_cfg_dfx_ramp_enable_ovr_attr == SERDES_LANE_ANA_PLL_LANE1_REG_25_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_25_cfg_dfx_ramp_toggle_en_attr == SERDES_LANE_ANA_PLL_LANE1_REG_25_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_25_cfg_dpso_bypass_mode_attr == SERDES_LANE_ANA_PLL_LANE1_REG_25_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_25_cfg_dtr_modulation_en_attr == SERDES_LANE_ANA_PLL_LANE1_REG_25_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_25_cfg_fine_modulation_en_attr == SERDES_LANE_ANA_PLL_LANE1_REG_25_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_25_cfg_fine_modulation_sel_attr == SERDES_LANE_ANA_PLL_LANE1_REG_25_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_25_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_25_cfg_tdcpe_modulation_en_attr == SERDES_LANE_ANA_PLL_LANE1_REG_25_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_25_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_25_cfg_vreg_dac_modulation_en_attr == SERDES_LANE_ANA_PLL_LANE1_REG_25_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_26_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_26_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_26_cfg_fbdiv_clkgate_attr == SERDES_LANE_ANA_PLL_LANE1_REG_26_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_26_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_27_cfg_calib_comp_out_sel_attr == SERDES_LANE_ANA_PLL_LANE1_REG_27_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_27_cfg_fw_force_vreg_cal_done_attr == SERDES_LANE_ANA_PLL_LANE1_REG_27_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_27_cfg_fw_vreg_accum_ovrd_attr == SERDES_LANE_ANA_PLL_LANE1_REG_27_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_27_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_27_cfg_inv_vpeak_comb_fb_attr == SERDES_LANE_ANA_PLL_LANE1_REG_27_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_27_cfg_inv_vreg_comb_fb_attr == SERDES_LANE_ANA_PLL_LANE1_REG_27_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_27_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_27_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_27_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_27_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_28_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_28_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_29_cfg_dft_freq_meas_enable_attr == SERDES_LANE_ANA_PLL_LANE1_REG_29_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_29_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_29_cfg_kvcc_inv_polarity_attr == SERDES_LANE_ANA_PLL_LANE1_REG_29_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_29_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_29_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_29_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_29_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_29_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_2_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_2_cfg_fracn_sd_step_en_attr == SERDES_LANE_ANA_PLL_LANE1_REG_2_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_2_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_30_cfg_force_kvcc_done_attr == SERDES_LANE_ANA_PLL_LANE1_REG_30_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_30_cfg_kvcc_calib_by_fw_attr == SERDES_LANE_ANA_PLL_LANE1_REG_30_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_30_cfg_kvcc_code_ovrd_attr == SERDES_LANE_ANA_PLL_LANE1_REG_30_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_30_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_30_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_LANE_ANA_PLL_LANE1_REG_30_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_30_cfg_kvcc_vreg_offset_en_val_attr == SERDES_LANE_ANA_PLL_LANE1_REG_30_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_31_cfg_spare_dig2ana_attr == 18'd10240
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_3_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_3_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_3_o_tdc_fine_res_attr == SERDES_LANE_ANA_PLL_LANE1_REG_3_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_3_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_4_cfg_sigma_delta2_sel_attr == SERDES_LANE_ANA_PLL_LANE1_REG_4_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_4_o_dcoditheren_h_attr == SERDES_LANE_ANA_PLL_LANE1_REG_4_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_4_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_4_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_4_o_fbdiv_strobe_h_attr == SERDES_LANE_ANA_PLL_LANE1_REG_4_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_4_o_feedfwrdcal_en_h_attr == SERDES_LANE_ANA_PLL_LANE1_REG_4_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_4_o_feedfwrdcal_pause_h_attr == SERDES_LANE_ANA_PLL_LANE1_REG_4_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_4_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_4_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_5_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_5_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_6_cfg_tdc_bb_input_sel_attr == SERDES_LANE_ANA_PLL_LANE1_REG_6_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_6_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_6_o_bbinlock_h_attr == SERDES_LANE_ANA_PLL_LANE1_REG_6_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_6_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_6_o_tdcdc_en_h_attr == SERDES_LANE_ANA_PLL_LANE1_REG_6_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_6_o_tdcovccorr_en_h_attr == SERDES_LANE_ANA_PLL_LANE1_REG_6_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_6_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_7_o_dfx_tdc_disable_attr == SERDES_LANE_ANA_PLL_LANE1_REG_7_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_7_o_pll_reg_resetb_attr == SERDES_LANE_ANA_PLL_LANE1_REG_7_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_7_o_pll_reg_resetb_mode_ctrl_attr == SERDES_LANE_ANA_PLL_LANE1_REG_7_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_7_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_7_o_plllc_regen_h_attr == SERDES_LANE_ANA_PLL_LANE1_REG_7_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_8_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_8_o_dcocoarse_ovrd_h_attr == SERDES_LANE_ANA_PLL_LANE1_REG_8_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_8_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_8_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_9_cfg_dft_cnt_restart_attr == SERDES_LANE_ANA_PLL_LANE1_REG_9_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_9_cfg_force_tdcdone_at_afcdone_attr == SERDES_LANE_ANA_PLL_LANE1_REG_9_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_9_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_9_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_9_o_tdccalexten_h_attr == SERDES_LANE_ANA_PLL_LANE1_REG_9_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_9_o_tdcroen_h_attr == SERDES_LANE_ANA_PLL_LANE1_REG_9_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane1_reg_9_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_10_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_11_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_12_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_13_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_13_cfg_plllock_state_sel_attr == SERDES_LANE_ANA_PLL_LANE2_REG_13_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_13_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_18_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_18_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_18_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_18_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_18_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_18_cfg_dcocoarse_ovrden_attr == SERDES_LANE_ANA_PLL_LANE2_REG_18_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_18_cfg_full_range_afc_sel_attr == SERDES_LANE_ANA_PLL_LANE2_REG_18_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_19_cfg_boost_dtr_const_zeta_attr == SERDES_LANE_ANA_PLL_LANE2_REG_19_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_19_cfg_boost_fine_const_zeta_attr == SERDES_LANE_ANA_PLL_LANE2_REG_19_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_19_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_19_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_19_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_19_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_19_cfg_filter_boostfade_dtr_en_attr == SERDES_LANE_ANA_PLL_LANE2_REG_19_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_19_cfg_filter_boostfade_fine_en_attr == SERDES_LANE_ANA_PLL_LANE2_REG_19_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_19_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_19_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_1_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_1_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_1_o_fracnen_h_attr == SERDES_LANE_ANA_PLL_LANE2_REG_1_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_20_cfg_dtr_earlylock_sel_attr == SERDES_LANE_ANA_PLL_LANE2_REG_20_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_20_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_20_cfg_dtr_final_code_sel_attr == SERDES_LANE_ANA_PLL_LANE2_REG_20_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_20_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_20_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_20_cfg_fine_int_coeff_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_20_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_20_cfg_fine_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_20_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_21_cfg_dcosettle_mode_attr == SERDES_LANE_ANA_PLL_LANE2_REG_21_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_21_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_21_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_21_cfg_dtr_ovrden_attr == SERDES_LANE_ANA_PLL_LANE2_REG_21_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_21_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_21_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_21_cfg_skip_second_afc_calib_attr == SERDES_LANE_ANA_PLL_LANE2_REG_21_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_21_cfg_stay_fll_attr == SERDES_LANE_ANA_PLL_LANE2_REG_21_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_21_cfg_stay_pll_attr == SERDES_LANE_ANA_PLL_LANE2_REG_21_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_21_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_21_cfg_tdcbbpd_en_attr == SERDES_LANE_ANA_PLL_LANE2_REG_21_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_22_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_22_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_22_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_22_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_22_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_22_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_22_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_22_cfg_ssc_track_en_attr == SERDES_LANE_ANA_PLL_LANE2_REG_22_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_22_cfg_temp_track_en_attr == SERDES_LANE_ANA_PLL_LANE2_REG_22_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_23_cfg_cb56_lane32div_en_attr == SERDES_LANE_ANA_PLL_LANE2_REG_23_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_23_cfg_clkouten_cb_attr == SERDES_LANE_ANA_PLL_LANE2_REG_23_CFG_CLKOUTEN_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_23_cfg_clkouten_lane_attr == SERDES_LANE_ANA_PLL_LANE2_REG_23_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_23_cfg_fbdiv_rat0p5_attr == SERDES_LANE_ANA_PLL_LANE2_REG_23_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_23_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_23_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_23_cfg_pcs3334_divsel_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_23_cfg_pcs3334div_en_attr == SERDES_LANE_ANA_PLL_LANE2_REG_23_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_23_cfg_pcs40div_en_attr == SERDES_LANE_ANA_PLL_LANE2_REG_23_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_23_cfg_pll_bypass_attr == SERDES_LANE_ANA_PLL_LANE2_REG_23_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_23_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_23_cfg_refclk100div_en_attr == SERDES_LANE_ANA_PLL_LANE2_REG_23_CFG_REFCLK100DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_23_cfg_refclk156div_en_attr == SERDES_LANE_ANA_PLL_LANE2_REG_23_CFG_REFCLK156DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_23_cfg_sddiv_en_attr == SERDES_LANE_ANA_PLL_LANE2_REG_23_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_23_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_23_cfg_sddtr_clk_sel_attr == SERDES_LANE_ANA_PLL_LANE2_REG_23_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_24_cfg_a2f_en_attr == SERDES_LANE_ANA_PLL_LANE2_REG_24_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_24_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_24_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_24_cfg_en_peak_sense_attr == SERDES_LANE_ANA_PLL_LANE2_REG_24_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_24_cfg_force_vreglpfbyp_attr == SERDES_LANE_ANA_PLL_LANE2_REG_24_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_24_cfg_obsmux0_del_attr == SERDES_LANE_ANA_PLL_LANE2_REG_24_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_24_cfg_obsmux1_del_attr == SERDES_LANE_ANA_PLL_LANE2_REG_24_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_24_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_24_cfg_ref156div_rat0p5_attr == SERDES_LANE_ANA_PLL_LANE2_REG_24_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_24_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_24_cfg_ss_comp_out_sel_attr == SERDES_LANE_ANA_PLL_LANE2_REG_24_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_24_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_25_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_LANE_ANA_PLL_LANE2_REG_25_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_25_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_LANE_ANA_PLL_LANE2_REG_25_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_25_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_LANE_ANA_PLL_LANE2_REG_25_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_25_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_LANE_ANA_PLL_LANE2_REG_25_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_25_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_25_cfg_dfx_ramp_dir_ovr_attr == SERDES_LANE_ANA_PLL_LANE2_REG_25_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_25_cfg_dfx_ramp_enable_ovr_attr == SERDES_LANE_ANA_PLL_LANE2_REG_25_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_25_cfg_dfx_ramp_toggle_en_attr == SERDES_LANE_ANA_PLL_LANE2_REG_25_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_25_cfg_dpso_bypass_mode_attr == SERDES_LANE_ANA_PLL_LANE2_REG_25_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_25_cfg_dtr_modulation_en_attr == SERDES_LANE_ANA_PLL_LANE2_REG_25_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_25_cfg_fine_modulation_en_attr == SERDES_LANE_ANA_PLL_LANE2_REG_25_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_25_cfg_fine_modulation_sel_attr == SERDES_LANE_ANA_PLL_LANE2_REG_25_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_25_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_25_cfg_tdcpe_modulation_en_attr == SERDES_LANE_ANA_PLL_LANE2_REG_25_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_25_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_25_cfg_vreg_dac_modulation_en_attr == SERDES_LANE_ANA_PLL_LANE2_REG_25_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_26_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_26_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_26_cfg_fbdiv_clkgate_attr == SERDES_LANE_ANA_PLL_LANE2_REG_26_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_26_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_27_cfg_calib_comp_out_sel_attr == SERDES_LANE_ANA_PLL_LANE2_REG_27_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_27_cfg_fw_force_vreg_cal_done_attr == SERDES_LANE_ANA_PLL_LANE2_REG_27_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_27_cfg_fw_vreg_accum_ovrd_attr == SERDES_LANE_ANA_PLL_LANE2_REG_27_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_27_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_27_cfg_inv_vpeak_comb_fb_attr == SERDES_LANE_ANA_PLL_LANE2_REG_27_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_27_cfg_inv_vreg_comb_fb_attr == SERDES_LANE_ANA_PLL_LANE2_REG_27_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_27_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_27_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_27_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_27_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_28_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_28_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_29_cfg_dft_freq_meas_enable_attr == SERDES_LANE_ANA_PLL_LANE2_REG_29_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_29_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_29_cfg_kvcc_inv_polarity_attr == SERDES_LANE_ANA_PLL_LANE2_REG_29_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_29_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_29_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_29_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_29_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_29_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_2_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_2_cfg_fracn_sd_step_en_attr == SERDES_LANE_ANA_PLL_LANE2_REG_2_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_2_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_30_cfg_force_kvcc_done_attr == SERDES_LANE_ANA_PLL_LANE2_REG_30_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_30_cfg_kvcc_calib_by_fw_attr == SERDES_LANE_ANA_PLL_LANE2_REG_30_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_30_cfg_kvcc_code_ovrd_attr == SERDES_LANE_ANA_PLL_LANE2_REG_30_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_30_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_30_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_LANE_ANA_PLL_LANE2_REG_30_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_30_cfg_kvcc_vreg_offset_en_val_attr == SERDES_LANE_ANA_PLL_LANE2_REG_30_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_31_cfg_spare_dig2ana_attr == 18'd10240
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_3_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_3_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_3_o_tdc_fine_res_attr == SERDES_LANE_ANA_PLL_LANE2_REG_3_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_3_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_4_cfg_sigma_delta2_sel_attr == SERDES_LANE_ANA_PLL_LANE2_REG_4_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_4_o_dcoditheren_h_attr == SERDES_LANE_ANA_PLL_LANE2_REG_4_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_4_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_4_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_4_o_fbdiv_strobe_h_attr == SERDES_LANE_ANA_PLL_LANE2_REG_4_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_4_o_feedfwrdcal_en_h_attr == SERDES_LANE_ANA_PLL_LANE2_REG_4_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_4_o_feedfwrdcal_pause_h_attr == SERDES_LANE_ANA_PLL_LANE2_REG_4_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_4_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_4_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_5_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_5_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_6_cfg_tdc_bb_input_sel_attr == SERDES_LANE_ANA_PLL_LANE2_REG_6_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_6_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_6_o_bbinlock_h_attr == SERDES_LANE_ANA_PLL_LANE2_REG_6_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_6_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_6_o_tdcdc_en_h_attr == SERDES_LANE_ANA_PLL_LANE2_REG_6_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_6_o_tdcovccorr_en_h_attr == SERDES_LANE_ANA_PLL_LANE2_REG_6_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_6_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_7_o_dfx_tdc_disable_attr == SERDES_LANE_ANA_PLL_LANE2_REG_7_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_7_o_pll_reg_resetb_attr == SERDES_LANE_ANA_PLL_LANE2_REG_7_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_7_o_pll_reg_resetb_mode_ctrl_attr == SERDES_LANE_ANA_PLL_LANE2_REG_7_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_7_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_7_o_plllc_regen_h_attr == SERDES_LANE_ANA_PLL_LANE2_REG_7_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_8_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_8_o_dcocoarse_ovrd_h_attr == SERDES_LANE_ANA_PLL_LANE2_REG_8_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_8_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_8_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_9_cfg_dft_cnt_restart_attr == SERDES_LANE_ANA_PLL_LANE2_REG_9_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_9_cfg_force_tdcdone_at_afcdone_attr == SERDES_LANE_ANA_PLL_LANE2_REG_9_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_9_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_9_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_9_o_tdccalexten_h_attr == SERDES_LANE_ANA_PLL_LANE2_REG_9_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_9_o_tdcroen_h_attr == SERDES_LANE_ANA_PLL_LANE2_REG_9_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane2_reg_9_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_10_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_11_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_12_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_13_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_13_cfg_plllock_state_sel_attr == SERDES_LANE_ANA_PLL_LANE3_REG_13_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_13_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_18_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_18_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_18_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_18_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_18_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_18_cfg_dcocoarse_ovrden_attr == SERDES_LANE_ANA_PLL_LANE3_REG_18_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_18_cfg_full_range_afc_sel_attr == SERDES_LANE_ANA_PLL_LANE3_REG_18_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_19_cfg_boost_dtr_const_zeta_attr == SERDES_LANE_ANA_PLL_LANE3_REG_19_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_19_cfg_boost_fine_const_zeta_attr == SERDES_LANE_ANA_PLL_LANE3_REG_19_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_19_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_19_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_19_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_19_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_19_cfg_filter_boostfade_dtr_en_attr == SERDES_LANE_ANA_PLL_LANE3_REG_19_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_19_cfg_filter_boostfade_fine_en_attr == SERDES_LANE_ANA_PLL_LANE3_REG_19_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_19_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_19_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_1_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_1_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_1_o_fracnen_h_attr == SERDES_LANE_ANA_PLL_LANE3_REG_1_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_20_cfg_dtr_earlylock_sel_attr == SERDES_LANE_ANA_PLL_LANE3_REG_20_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_20_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_20_cfg_dtr_final_code_sel_attr == SERDES_LANE_ANA_PLL_LANE3_REG_20_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_20_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_20_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_20_cfg_fine_int_coeff_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_20_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_20_cfg_fine_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_20_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_21_cfg_dcosettle_mode_attr == SERDES_LANE_ANA_PLL_LANE3_REG_21_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_21_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_21_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_21_cfg_dtr_ovrden_attr == SERDES_LANE_ANA_PLL_LANE3_REG_21_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_21_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_21_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_21_cfg_skip_second_afc_calib_attr == SERDES_LANE_ANA_PLL_LANE3_REG_21_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_21_cfg_stay_fll_attr == SERDES_LANE_ANA_PLL_LANE3_REG_21_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_21_cfg_stay_pll_attr == SERDES_LANE_ANA_PLL_LANE3_REG_21_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_21_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_21_cfg_tdcbbpd_en_attr == SERDES_LANE_ANA_PLL_LANE3_REG_21_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_22_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_22_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_22_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_22_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_22_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_22_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_22_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_22_cfg_ssc_track_en_attr == SERDES_LANE_ANA_PLL_LANE3_REG_22_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_22_cfg_temp_track_en_attr == SERDES_LANE_ANA_PLL_LANE3_REG_22_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_23_cfg_cb56_lane32div_en_attr == SERDES_LANE_ANA_PLL_LANE3_REG_23_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_23_cfg_clkouten_cb_attr == SERDES_LANE_ANA_PLL_LANE3_REG_23_CFG_CLKOUTEN_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_23_cfg_clkouten_lane_attr == SERDES_LANE_ANA_PLL_LANE3_REG_23_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_23_cfg_fbdiv_rat0p5_attr == SERDES_LANE_ANA_PLL_LANE3_REG_23_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_23_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_23_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_23_cfg_pcs3334_divsel_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_23_cfg_pcs3334div_en_attr == SERDES_LANE_ANA_PLL_LANE3_REG_23_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_23_cfg_pcs40div_en_attr == SERDES_LANE_ANA_PLL_LANE3_REG_23_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_23_cfg_pll_bypass_attr == SERDES_LANE_ANA_PLL_LANE3_REG_23_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_23_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_23_cfg_refclk100div_en_attr == SERDES_LANE_ANA_PLL_LANE3_REG_23_CFG_REFCLK100DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_23_cfg_refclk156div_en_attr == SERDES_LANE_ANA_PLL_LANE3_REG_23_CFG_REFCLK156DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_23_cfg_sddiv_en_attr == SERDES_LANE_ANA_PLL_LANE3_REG_23_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_23_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_23_cfg_sddtr_clk_sel_attr == SERDES_LANE_ANA_PLL_LANE3_REG_23_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_24_cfg_a2f_en_attr == SERDES_LANE_ANA_PLL_LANE3_REG_24_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_24_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_24_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_24_cfg_en_peak_sense_attr == SERDES_LANE_ANA_PLL_LANE3_REG_24_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_24_cfg_force_vreglpfbyp_attr == SERDES_LANE_ANA_PLL_LANE3_REG_24_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_24_cfg_obsmux0_del_attr == SERDES_LANE_ANA_PLL_LANE3_REG_24_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_24_cfg_obsmux1_del_attr == SERDES_LANE_ANA_PLL_LANE3_REG_24_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_24_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_24_cfg_ref156div_rat0p5_attr == SERDES_LANE_ANA_PLL_LANE3_REG_24_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_24_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_24_cfg_ss_comp_out_sel_attr == SERDES_LANE_ANA_PLL_LANE3_REG_24_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_24_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_25_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_LANE_ANA_PLL_LANE3_REG_25_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_25_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_LANE_ANA_PLL_LANE3_REG_25_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_25_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_LANE_ANA_PLL_LANE3_REG_25_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_25_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_LANE_ANA_PLL_LANE3_REG_25_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_25_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_25_cfg_dfx_ramp_dir_ovr_attr == SERDES_LANE_ANA_PLL_LANE3_REG_25_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_25_cfg_dfx_ramp_enable_ovr_attr == SERDES_LANE_ANA_PLL_LANE3_REG_25_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_25_cfg_dfx_ramp_toggle_en_attr == SERDES_LANE_ANA_PLL_LANE3_REG_25_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_25_cfg_dpso_bypass_mode_attr == SERDES_LANE_ANA_PLL_LANE3_REG_25_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_25_cfg_dtr_modulation_en_attr == SERDES_LANE_ANA_PLL_LANE3_REG_25_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_25_cfg_fine_modulation_en_attr == SERDES_LANE_ANA_PLL_LANE3_REG_25_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_25_cfg_fine_modulation_sel_attr == SERDES_LANE_ANA_PLL_LANE3_REG_25_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_25_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_25_cfg_tdcpe_modulation_en_attr == SERDES_LANE_ANA_PLL_LANE3_REG_25_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_25_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_25_cfg_vreg_dac_modulation_en_attr == SERDES_LANE_ANA_PLL_LANE3_REG_25_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_26_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_26_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_26_cfg_fbdiv_clkgate_attr == SERDES_LANE_ANA_PLL_LANE3_REG_26_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_26_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_27_cfg_calib_comp_out_sel_attr == SERDES_LANE_ANA_PLL_LANE3_REG_27_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_27_cfg_fw_force_vreg_cal_done_attr == SERDES_LANE_ANA_PLL_LANE3_REG_27_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_27_cfg_fw_vreg_accum_ovrd_attr == SERDES_LANE_ANA_PLL_LANE3_REG_27_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_27_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_27_cfg_inv_vpeak_comb_fb_attr == SERDES_LANE_ANA_PLL_LANE3_REG_27_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_27_cfg_inv_vreg_comb_fb_attr == SERDES_LANE_ANA_PLL_LANE3_REG_27_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_27_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_27_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_27_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_27_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_28_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_28_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_29_cfg_dft_freq_meas_enable_attr == SERDES_LANE_ANA_PLL_LANE3_REG_29_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_29_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_29_cfg_kvcc_inv_polarity_attr == SERDES_LANE_ANA_PLL_LANE3_REG_29_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_29_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_29_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_29_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_29_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_29_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_2_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_2_cfg_fracn_sd_step_en_attr == SERDES_LANE_ANA_PLL_LANE3_REG_2_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_2_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_30_cfg_force_kvcc_done_attr == SERDES_LANE_ANA_PLL_LANE3_REG_30_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_30_cfg_kvcc_calib_by_fw_attr == SERDES_LANE_ANA_PLL_LANE3_REG_30_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_30_cfg_kvcc_code_ovrd_attr == SERDES_LANE_ANA_PLL_LANE3_REG_30_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_30_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_30_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_LANE_ANA_PLL_LANE3_REG_30_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_30_cfg_kvcc_vreg_offset_en_val_attr == SERDES_LANE_ANA_PLL_LANE3_REG_30_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_31_cfg_spare_dig2ana_attr == 18'd10240
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_3_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_3_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_3_o_tdc_fine_res_attr == SERDES_LANE_ANA_PLL_LANE3_REG_3_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_3_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_4_cfg_sigma_delta2_sel_attr == SERDES_LANE_ANA_PLL_LANE3_REG_4_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_4_o_dcoditheren_h_attr == SERDES_LANE_ANA_PLL_LANE3_REG_4_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_4_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_4_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_4_o_fbdiv_strobe_h_attr == SERDES_LANE_ANA_PLL_LANE3_REG_4_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_4_o_feedfwrdcal_en_h_attr == SERDES_LANE_ANA_PLL_LANE3_REG_4_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_4_o_feedfwrdcal_pause_h_attr == SERDES_LANE_ANA_PLL_LANE3_REG_4_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_4_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_4_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_5_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_5_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_6_cfg_tdc_bb_input_sel_attr == SERDES_LANE_ANA_PLL_LANE3_REG_6_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_6_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_6_o_bbinlock_h_attr == SERDES_LANE_ANA_PLL_LANE3_REG_6_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_6_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_6_o_tdcdc_en_h_attr == SERDES_LANE_ANA_PLL_LANE3_REG_6_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_6_o_tdcovccorr_en_h_attr == SERDES_LANE_ANA_PLL_LANE3_REG_6_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_6_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_7_o_dfx_tdc_disable_attr == SERDES_LANE_ANA_PLL_LANE3_REG_7_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_7_o_pll_reg_resetb_attr == SERDES_LANE_ANA_PLL_LANE3_REG_7_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_7_o_pll_reg_resetb_mode_ctrl_attr == SERDES_LANE_ANA_PLL_LANE3_REG_7_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_7_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_7_o_plllc_regen_h_attr == SERDES_LANE_ANA_PLL_LANE3_REG_7_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_8_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_8_o_dcocoarse_ovrd_h_attr == SERDES_LANE_ANA_PLL_LANE3_REG_8_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_8_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_8_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_9_cfg_dft_cnt_restart_attr == SERDES_LANE_ANA_PLL_LANE3_REG_9_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_9_cfg_force_tdcdone_at_afcdone_attr == SERDES_LANE_ANA_PLL_LANE3_REG_9_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_9_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_9_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_9_o_tdccalexten_h_attr == SERDES_LANE_ANA_PLL_LANE3_REG_9_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_9_o_tdcroen_h_attr == SERDES_LANE_ANA_PLL_LANE3_REG_9_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_pll_lane3_reg_9_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_10_afe_spare_1_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_11_afe_spare_2_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_12_afe_st1_config_1_reg_spare_attr == SERDES_LANE_ANA_RX1_LANE0_REG_12_AFE_ST1_CONFIG_1_REG_SPARE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_12_st1_en_vcmbf_attr == SERDES_LANE_ANA_RX1_LANE0_REG_12_ST1_EN_VCMBF_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_12_st1_ggain_n_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_12_st1_ggain_p_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_12_st1_grload_attr == 6'd34
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_12_st1_vcmnshift_attr == SERDES_LANE_ANA_RX1_LANE0_REG_12_ST1_VCMNSHIFT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_12_st3_bpktrm_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_13_afe_st2_config_reg_sp_attr == SERDES_LANE_ANA_RX1_LANE0_REG_13_AFE_ST2_CONFIG_REG_SP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_13_st2_bctune_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_13_st2_en_vcmbf_attr == SERDES_LANE_ANA_RX1_LANE0_REG_13_ST2_EN_VCMBF_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_13_st2_ggain_n_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_13_st2_ggain_p_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_13_st2_grload_attr == 6'd34
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_13_st2_vcmshift_attr == SERDES_LANE_ANA_RX1_LANE0_REG_13_ST2_VCMSHIFT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_14_afe_st3_config_reg_spare_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_14_st3_brload_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_14_st3_en_vcmbf_attr == SERDES_LANE_ANA_RX1_LANE0_REG_14_ST3_EN_VCMBF_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_14_st3_ggain_n_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_14_st3_ggain_p_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_14_st3_vcmshift_attr == SERDES_LANE_ANA_RX1_LANE0_REG_14_ST3_VCMSHIFT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_15_ioutp_abs_100u_31_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_15_ioutp_abs_100u_32_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_15_ioutp_abs_100u_33_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_15_ioutp_abs_100u_34_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_15_ioutp_abs_100u_35_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_15_ioutp_abs_100u_36_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_16_ioutp_abs_100u_37_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_16_ioutp_abs_100u_38_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_16_ioutp_abs_100u_39_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_16_ioutp_abs_100u_40_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_16_ioutp_abs_100u_41_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_16_ioutp_abs_100u_42_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_17_ioutp_abs_100u_43_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_17_ioutp_abs_100u_44_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_17_ioutp_abs_100u_45_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_17_ioutp_abs_100u_46_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_17_ioutp_abs_100u_47_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_17_ioutp_abs_100u_48_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_18_dcmon1_en_attr == SERDES_LANE_ANA_RX1_LANE0_REG_18_DCMON1_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_18_dcmon1_minus_100ua_attr == SERDES_LANE_ANA_RX1_LANE0_REG_18_DCMON1_MINUS_100UA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_18_dcmon1_minus_50ua_attr == SERDES_LANE_ANA_RX1_LANE0_REG_18_DCMON1_MINUS_50UA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_18_dcmon1_minus_v_n_attr == SERDES_LANE_ANA_RX1_LANE0_REG_18_DCMON1_MINUS_V_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_18_dcmon1_minus_v_p_attr == SERDES_LANE_ANA_RX1_LANE0_REG_18_DCMON1_MINUS_V_P_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_18_dcmon2_en_attr == SERDES_LANE_ANA_RX1_LANE0_REG_18_DCMON2_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_18_dcmon2_minus_100ua_attr == SERDES_LANE_ANA_RX1_LANE0_REG_18_DCMON2_MINUS_100UA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_18_dcmon2_minus_50ua_attr == SERDES_LANE_ANA_RX1_LANE0_REG_18_DCMON2_MINUS_50UA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_18_ioutp_abs_100u_49_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_18_ioutp_abs_100u_50_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_18_spare_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_18_vref_n_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_18_vref_p_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_19_ioutn_abs_50u_0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_19_ioutn_abs_50u_1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_19_ioutn_abs_50u_2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_19_ioutn_abs_50u_3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_19_ioutn_abs_50u_4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_19_ioutn_abs_50u_d_n_master_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_1_afe_bias_reg_sp_attr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_1_bias_en400_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_20_ioutn_abs_50u_10_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_20_ioutn_abs_50u_5_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_20_ioutn_abs_50u_6_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_20_ioutn_abs_50u_7_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_20_ioutn_abs_50u_8_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_20_ioutn_abs_50u_9_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_21_ioutn_abs_50u_11_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_21_ioutn_abs_50u_12_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_21_ioutn_abs_50u_13_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_21_ioutn_abs_50u_14_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_21_ioutn_abs_50u_15_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_21_ioutn_abs_50u_16_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_22_ioutn_abs_100u_0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_22_ioutn_abs_100u_1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_22_ioutn_abs_100u_2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_22_ioutn_abs_100u_3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_22_ioutn_abs_50u_17_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_22_ioutn_abs_50u_18_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_23_ioutn_abs_100u_4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_23_ioutn_abs_100u_5_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_23_ioutn_abs_100u_6_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_23_ioutn_abs_100u_7_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_23_ioutn_abs_100u_8_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_23_ioutn_abs_100u_9_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_24_ioutn_abs_100u_10_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_24_ioutn_abs_100u_11_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_24_ioutn_abs_100u_12_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_24_ioutn_abs_100u_13_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_24_ioutn_abs_100u_14_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_24_ioutn_abs_100u_15_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_25_ioutn_abs_100u_16_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_25_ioutn_abs_100u_17_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_25_ioutn_abs_100u_18_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_25_ioutn_abs_100u_19_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_25_ioutn_abs_100u_20_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_25_ioutn_abs_100u_21_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_26_ioutn_abs_100u_22_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_26_ioutn_abs_100u_23_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_26_ioutn_abs_100u_24_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_26_ioutn_abs_100u_25_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_26_ioutn_abs_100u_pchref_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_26_ioutn_abs_100u_tx1to100_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_27_ioutn_abs_200u_0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_27_ioutn_abs_200u_1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_27_ioutn_abs_200u_2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_27_ioutn_abs_200u_3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_27_ioutn_abs_200u_4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_27_ioutp_abs_100u_0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_28_ioutp_abs_100u_1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_28_ioutp_abs_100u_2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_28_ioutp_abs_100u_3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_28_ioutp_abs_100u_4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_28_ioutp_abs_100u_5_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_28_ioutp_abs_100u_6_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_29_ioutp_abs_100u_10_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_29_ioutp_abs_100u_11_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_29_ioutp_abs_100u_12_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_29_ioutp_abs_100u_7_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_29_ioutp_abs_100u_8_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_29_ioutp_abs_100u_9_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_2_en_acmp_attr == SERDES_LANE_ANA_RX1_LANE0_REG_2_EN_ACMP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_2_en_amon_attr == SERDES_LANE_ANA_RX1_LANE0_REG_2_EN_AMON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_2_inp_monen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_2_rgen_monen_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_2_rtrm_monen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_2_st1_monen_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_2_st2_monen_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_2_st3_monen_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_30_ioutp_abs_100u_13_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_30_ioutp_abs_100u_14_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_30_ioutp_abs_100u_15_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_30_ioutp_abs_100u_16_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_30_ioutp_abs_100u_17_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_30_ioutp_abs_100u_18_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_31_ioutp_abs_100u_19_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_31_ioutp_abs_100u_20_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_31_ioutp_abs_100u_21_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_31_ioutp_abs_100u_22_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_31_ioutp_abs_100u_23_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_31_ioutp_abs_100u_24_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_32_ioutp_abs_100u_25_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_32_ioutp_abs_100u_26_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_32_ioutp_abs_100u_27_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_32_ioutp_abs_100u_28_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_32_ioutp_abs_100u_29_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_32_ioutp_abs_100u_30_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_3_afe_odac_0_reg_sp_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_3_odac1_gmsb_attr == 5'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_3_odac2_gmsb_attr == 5'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_3_odac3_gmsb_attr == 5'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_3_odac_en_attr == SERDES_LANE_ANA_RX1_LANE0_REG_3_ODAC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_3_odac_range_attr == SERDES_LANE_ANA_RX1_LANE0_REG_3_ODAC_RANGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_4_afe_odac_1_reg_sp_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_4_odac1_gdmc_attr == 5'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_4_odac1_glsb_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_4_odac2_gdmc_attr == 5'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_4_odac2_glsb_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_4_odac3_glsb_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_5_afe_refgen_0_reg_sp_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_5_rgen_bitrm0p5_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_5_rgen_bitrm1p0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_5_rgen_bvtrm0p5_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_5_rgen_bvtrm1p0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_6_afe_refgen_1_reg_sp_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_6_rgen_bsel1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_6_rgen_bsel2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_6_rgen_bsel3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_6_rgen_bseli_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_7_afe_bivcm_reg_sp_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_7_st1_bivcm_n_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_7_st1_bivcm_p_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_7_st2_bivcm_n_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_7_st2_bivcm_p_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_7_st3_bivcm_n_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_7_st3_bivcm_p_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_8_afe_inp_rtrm_reg_sp_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_8_afe_lpbk_en_attr == SERDES_LANE_ANA_RX1_LANE0_REG_8_AFE_LPBK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_8_afe_slicer_in_attr == SERDES_LANE_ANA_RX1_LANE0_REG_8_AFE_SLICER_IN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_8_in_bypass_attr == SERDES_LANE_ANA_RX1_LANE0_REG_8_IN_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_8_inp_trmc_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_8_inp_trmp0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_8_inp_trmp1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_8_inp_trmp2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_8_rtrm_btune_attr == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_8_rtrm_vcm_swt_attr == SERDES_LANE_ANA_RX1_LANE0_REG_8_RTRM_VCM_SWT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane0_reg_9_afe_spare_0_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_10_afe_spare_1_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_11_afe_spare_2_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_12_afe_st1_config_1_reg_spare_attr == SERDES_LANE_ANA_RX1_LANE1_REG_12_AFE_ST1_CONFIG_1_REG_SPARE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_12_st1_en_vcmbf_attr == SERDES_LANE_ANA_RX1_LANE1_REG_12_ST1_EN_VCMBF_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_12_st1_ggain_n_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_12_st1_ggain_p_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_12_st1_grload_attr == 6'd34
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_12_st1_vcmnshift_attr == SERDES_LANE_ANA_RX1_LANE1_REG_12_ST1_VCMNSHIFT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_12_st3_bpktrm_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_13_afe_st2_config_reg_sp_attr == SERDES_LANE_ANA_RX1_LANE1_REG_13_AFE_ST2_CONFIG_REG_SP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_13_st2_bctune_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_13_st2_en_vcmbf_attr == SERDES_LANE_ANA_RX1_LANE1_REG_13_ST2_EN_VCMBF_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_13_st2_ggain_n_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_13_st2_ggain_p_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_13_st2_grload_attr == 6'd34
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_13_st2_vcmshift_attr == SERDES_LANE_ANA_RX1_LANE1_REG_13_ST2_VCMSHIFT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_14_afe_st3_config_reg_spare_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_14_st3_brload_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_14_st3_en_vcmbf_attr == SERDES_LANE_ANA_RX1_LANE1_REG_14_ST3_EN_VCMBF_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_14_st3_ggain_n_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_14_st3_ggain_p_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_14_st3_vcmshift_attr == SERDES_LANE_ANA_RX1_LANE1_REG_14_ST3_VCMSHIFT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_15_ioutp_abs_100u_31_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_15_ioutp_abs_100u_32_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_15_ioutp_abs_100u_33_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_15_ioutp_abs_100u_34_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_15_ioutp_abs_100u_35_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_15_ioutp_abs_100u_36_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_16_ioutp_abs_100u_37_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_16_ioutp_abs_100u_38_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_16_ioutp_abs_100u_39_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_16_ioutp_abs_100u_40_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_16_ioutp_abs_100u_41_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_16_ioutp_abs_100u_42_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_17_ioutp_abs_100u_43_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_17_ioutp_abs_100u_44_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_17_ioutp_abs_100u_45_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_17_ioutp_abs_100u_46_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_17_ioutp_abs_100u_47_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_17_ioutp_abs_100u_48_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_18_dcmon1_en_attr == SERDES_LANE_ANA_RX1_LANE1_REG_18_DCMON1_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_18_dcmon1_minus_100ua_attr == SERDES_LANE_ANA_RX1_LANE1_REG_18_DCMON1_MINUS_100UA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_18_dcmon1_minus_50ua_attr == SERDES_LANE_ANA_RX1_LANE1_REG_18_DCMON1_MINUS_50UA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_18_dcmon1_minus_v_n_attr == SERDES_LANE_ANA_RX1_LANE1_REG_18_DCMON1_MINUS_V_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_18_dcmon1_minus_v_p_attr == SERDES_LANE_ANA_RX1_LANE1_REG_18_DCMON1_MINUS_V_P_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_18_dcmon2_en_attr == SERDES_LANE_ANA_RX1_LANE1_REG_18_DCMON2_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_18_dcmon2_minus_100ua_attr == SERDES_LANE_ANA_RX1_LANE1_REG_18_DCMON2_MINUS_100UA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_18_dcmon2_minus_50ua_attr == SERDES_LANE_ANA_RX1_LANE1_REG_18_DCMON2_MINUS_50UA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_18_ioutp_abs_100u_49_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_18_ioutp_abs_100u_50_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_18_spare_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_18_vref_n_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_18_vref_p_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_19_ioutn_abs_50u_0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_19_ioutn_abs_50u_1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_19_ioutn_abs_50u_2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_19_ioutn_abs_50u_3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_19_ioutn_abs_50u_4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_19_ioutn_abs_50u_d_n_master_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_1_afe_bias_reg_sp_attr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_1_bias_en400_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_20_ioutn_abs_50u_10_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_20_ioutn_abs_50u_5_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_20_ioutn_abs_50u_6_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_20_ioutn_abs_50u_7_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_20_ioutn_abs_50u_8_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_20_ioutn_abs_50u_9_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_21_ioutn_abs_50u_11_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_21_ioutn_abs_50u_12_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_21_ioutn_abs_50u_13_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_21_ioutn_abs_50u_14_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_21_ioutn_abs_50u_15_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_21_ioutn_abs_50u_16_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_22_ioutn_abs_100u_0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_22_ioutn_abs_100u_1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_22_ioutn_abs_100u_2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_22_ioutn_abs_100u_3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_22_ioutn_abs_50u_17_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_22_ioutn_abs_50u_18_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_23_ioutn_abs_100u_4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_23_ioutn_abs_100u_5_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_23_ioutn_abs_100u_6_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_23_ioutn_abs_100u_7_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_23_ioutn_abs_100u_8_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_23_ioutn_abs_100u_9_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_24_ioutn_abs_100u_10_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_24_ioutn_abs_100u_11_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_24_ioutn_abs_100u_12_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_24_ioutn_abs_100u_13_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_24_ioutn_abs_100u_14_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_24_ioutn_abs_100u_15_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_25_ioutn_abs_100u_16_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_25_ioutn_abs_100u_17_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_25_ioutn_abs_100u_18_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_25_ioutn_abs_100u_19_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_25_ioutn_abs_100u_20_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_25_ioutn_abs_100u_21_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_26_ioutn_abs_100u_22_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_26_ioutn_abs_100u_23_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_26_ioutn_abs_100u_24_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_26_ioutn_abs_100u_25_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_26_ioutn_abs_100u_pchref_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_26_ioutn_abs_100u_tx1to100_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_27_ioutn_abs_200u_0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_27_ioutn_abs_200u_1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_27_ioutn_abs_200u_2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_27_ioutn_abs_200u_3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_27_ioutn_abs_200u_4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_27_ioutp_abs_100u_0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_28_ioutp_abs_100u_1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_28_ioutp_abs_100u_2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_28_ioutp_abs_100u_3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_28_ioutp_abs_100u_4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_28_ioutp_abs_100u_5_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_28_ioutp_abs_100u_6_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_29_ioutp_abs_100u_10_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_29_ioutp_abs_100u_11_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_29_ioutp_abs_100u_12_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_29_ioutp_abs_100u_7_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_29_ioutp_abs_100u_8_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_29_ioutp_abs_100u_9_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_2_en_acmp_attr == SERDES_LANE_ANA_RX1_LANE1_REG_2_EN_ACMP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_2_en_amon_attr == SERDES_LANE_ANA_RX1_LANE1_REG_2_EN_AMON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_2_inp_monen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_2_rgen_monen_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_2_rtrm_monen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_2_st1_monen_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_2_st2_monen_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_2_st3_monen_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_30_ioutp_abs_100u_13_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_30_ioutp_abs_100u_14_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_30_ioutp_abs_100u_15_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_30_ioutp_abs_100u_16_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_30_ioutp_abs_100u_17_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_30_ioutp_abs_100u_18_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_31_ioutp_abs_100u_19_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_31_ioutp_abs_100u_20_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_31_ioutp_abs_100u_21_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_31_ioutp_abs_100u_22_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_31_ioutp_abs_100u_23_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_31_ioutp_abs_100u_24_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_32_ioutp_abs_100u_25_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_32_ioutp_abs_100u_26_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_32_ioutp_abs_100u_27_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_32_ioutp_abs_100u_28_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_32_ioutp_abs_100u_29_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_32_ioutp_abs_100u_30_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_3_afe_odac_0_reg_sp_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_3_odac1_gmsb_attr == 5'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_3_odac2_gmsb_attr == 5'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_3_odac3_gmsb_attr == 5'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_3_odac_en_attr == SERDES_LANE_ANA_RX1_LANE1_REG_3_ODAC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_3_odac_range_attr == SERDES_LANE_ANA_RX1_LANE1_REG_3_ODAC_RANGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_4_afe_odac_1_reg_sp_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_4_odac1_gdmc_attr == 5'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_4_odac1_glsb_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_4_odac2_gdmc_attr == 5'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_4_odac2_glsb_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_4_odac3_glsb_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_5_afe_refgen_0_reg_sp_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_5_rgen_bitrm0p5_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_5_rgen_bitrm1p0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_5_rgen_bvtrm0p5_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_5_rgen_bvtrm1p0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_6_afe_refgen_1_reg_sp_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_6_rgen_bsel1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_6_rgen_bsel2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_6_rgen_bsel3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_6_rgen_bseli_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_7_afe_bivcm_reg_sp_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_7_st1_bivcm_n_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_7_st1_bivcm_p_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_7_st2_bivcm_n_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_7_st2_bivcm_p_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_7_st3_bivcm_n_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_7_st3_bivcm_p_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_8_afe_inp_rtrm_reg_sp_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_8_afe_lpbk_en_attr == SERDES_LANE_ANA_RX1_LANE1_REG_8_AFE_LPBK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_8_afe_slicer_in_attr == SERDES_LANE_ANA_RX1_LANE1_REG_8_AFE_SLICER_IN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_8_in_bypass_attr == SERDES_LANE_ANA_RX1_LANE1_REG_8_IN_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_8_inp_trmc_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_8_inp_trmp0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_8_inp_trmp1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_8_inp_trmp2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_8_rtrm_btune_attr == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_8_rtrm_vcm_swt_attr == SERDES_LANE_ANA_RX1_LANE1_REG_8_RTRM_VCM_SWT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane1_reg_9_afe_spare_0_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_10_afe_spare_1_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_11_afe_spare_2_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_12_afe_st1_config_1_reg_spare_attr == SERDES_LANE_ANA_RX1_LANE2_REG_12_AFE_ST1_CONFIG_1_REG_SPARE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_12_st1_en_vcmbf_attr == SERDES_LANE_ANA_RX1_LANE2_REG_12_ST1_EN_VCMBF_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_12_st1_ggain_n_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_12_st1_ggain_p_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_12_st1_grload_attr == 6'd34
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_12_st1_vcmnshift_attr == SERDES_LANE_ANA_RX1_LANE2_REG_12_ST1_VCMNSHIFT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_12_st3_bpktrm_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_13_afe_st2_config_reg_sp_attr == SERDES_LANE_ANA_RX1_LANE2_REG_13_AFE_ST2_CONFIG_REG_SP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_13_st2_bctune_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_13_st2_en_vcmbf_attr == SERDES_LANE_ANA_RX1_LANE2_REG_13_ST2_EN_VCMBF_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_13_st2_ggain_n_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_13_st2_ggain_p_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_13_st2_grload_attr == 6'd34
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_13_st2_vcmshift_attr == SERDES_LANE_ANA_RX1_LANE2_REG_13_ST2_VCMSHIFT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_14_afe_st3_config_reg_spare_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_14_st3_brload_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_14_st3_en_vcmbf_attr == SERDES_LANE_ANA_RX1_LANE2_REG_14_ST3_EN_VCMBF_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_14_st3_ggain_n_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_14_st3_ggain_p_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_14_st3_vcmshift_attr == SERDES_LANE_ANA_RX1_LANE2_REG_14_ST3_VCMSHIFT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_15_ioutp_abs_100u_31_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_15_ioutp_abs_100u_32_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_15_ioutp_abs_100u_33_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_15_ioutp_abs_100u_34_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_15_ioutp_abs_100u_35_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_15_ioutp_abs_100u_36_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_16_ioutp_abs_100u_37_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_16_ioutp_abs_100u_38_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_16_ioutp_abs_100u_39_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_16_ioutp_abs_100u_40_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_16_ioutp_abs_100u_41_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_16_ioutp_abs_100u_42_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_17_ioutp_abs_100u_43_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_17_ioutp_abs_100u_44_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_17_ioutp_abs_100u_45_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_17_ioutp_abs_100u_46_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_17_ioutp_abs_100u_47_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_17_ioutp_abs_100u_48_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_18_dcmon1_en_attr == SERDES_LANE_ANA_RX1_LANE2_REG_18_DCMON1_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_18_dcmon1_minus_100ua_attr == SERDES_LANE_ANA_RX1_LANE2_REG_18_DCMON1_MINUS_100UA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_18_dcmon1_minus_50ua_attr == SERDES_LANE_ANA_RX1_LANE2_REG_18_DCMON1_MINUS_50UA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_18_dcmon1_minus_v_n_attr == SERDES_LANE_ANA_RX1_LANE2_REG_18_DCMON1_MINUS_V_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_18_dcmon1_minus_v_p_attr == SERDES_LANE_ANA_RX1_LANE2_REG_18_DCMON1_MINUS_V_P_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_18_dcmon2_en_attr == SERDES_LANE_ANA_RX1_LANE2_REG_18_DCMON2_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_18_dcmon2_minus_100ua_attr == SERDES_LANE_ANA_RX1_LANE2_REG_18_DCMON2_MINUS_100UA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_18_dcmon2_minus_50ua_attr == SERDES_LANE_ANA_RX1_LANE2_REG_18_DCMON2_MINUS_50UA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_18_ioutp_abs_100u_49_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_18_ioutp_abs_100u_50_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_18_spare_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_18_vref_n_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_18_vref_p_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_19_ioutn_abs_50u_0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_19_ioutn_abs_50u_1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_19_ioutn_abs_50u_2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_19_ioutn_abs_50u_3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_19_ioutn_abs_50u_4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_19_ioutn_abs_50u_d_n_master_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_1_afe_bias_reg_sp_attr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_1_bias_en400_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_20_ioutn_abs_50u_10_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_20_ioutn_abs_50u_5_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_20_ioutn_abs_50u_6_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_20_ioutn_abs_50u_7_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_20_ioutn_abs_50u_8_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_20_ioutn_abs_50u_9_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_21_ioutn_abs_50u_11_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_21_ioutn_abs_50u_12_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_21_ioutn_abs_50u_13_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_21_ioutn_abs_50u_14_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_21_ioutn_abs_50u_15_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_21_ioutn_abs_50u_16_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_22_ioutn_abs_100u_0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_22_ioutn_abs_100u_1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_22_ioutn_abs_100u_2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_22_ioutn_abs_100u_3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_22_ioutn_abs_50u_17_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_22_ioutn_abs_50u_18_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_23_ioutn_abs_100u_4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_23_ioutn_abs_100u_5_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_23_ioutn_abs_100u_6_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_23_ioutn_abs_100u_7_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_23_ioutn_abs_100u_8_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_23_ioutn_abs_100u_9_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_24_ioutn_abs_100u_10_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_24_ioutn_abs_100u_11_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_24_ioutn_abs_100u_12_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_24_ioutn_abs_100u_13_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_24_ioutn_abs_100u_14_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_24_ioutn_abs_100u_15_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_25_ioutn_abs_100u_16_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_25_ioutn_abs_100u_17_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_25_ioutn_abs_100u_18_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_25_ioutn_abs_100u_19_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_25_ioutn_abs_100u_20_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_25_ioutn_abs_100u_21_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_26_ioutn_abs_100u_22_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_26_ioutn_abs_100u_23_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_26_ioutn_abs_100u_24_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_26_ioutn_abs_100u_25_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_26_ioutn_abs_100u_pchref_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_26_ioutn_abs_100u_tx1to100_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_27_ioutn_abs_200u_0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_27_ioutn_abs_200u_1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_27_ioutn_abs_200u_2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_27_ioutn_abs_200u_3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_27_ioutn_abs_200u_4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_27_ioutp_abs_100u_0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_28_ioutp_abs_100u_1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_28_ioutp_abs_100u_2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_28_ioutp_abs_100u_3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_28_ioutp_abs_100u_4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_28_ioutp_abs_100u_5_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_28_ioutp_abs_100u_6_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_29_ioutp_abs_100u_10_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_29_ioutp_abs_100u_11_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_29_ioutp_abs_100u_12_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_29_ioutp_abs_100u_7_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_29_ioutp_abs_100u_8_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_29_ioutp_abs_100u_9_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_2_en_acmp_attr == SERDES_LANE_ANA_RX1_LANE2_REG_2_EN_ACMP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_2_en_amon_attr == SERDES_LANE_ANA_RX1_LANE2_REG_2_EN_AMON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_2_inp_monen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_2_rgen_monen_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_2_rtrm_monen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_2_st1_monen_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_2_st2_monen_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_2_st3_monen_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_30_ioutp_abs_100u_13_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_30_ioutp_abs_100u_14_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_30_ioutp_abs_100u_15_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_30_ioutp_abs_100u_16_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_30_ioutp_abs_100u_17_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_30_ioutp_abs_100u_18_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_31_ioutp_abs_100u_19_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_31_ioutp_abs_100u_20_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_31_ioutp_abs_100u_21_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_31_ioutp_abs_100u_22_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_31_ioutp_abs_100u_23_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_31_ioutp_abs_100u_24_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_32_ioutp_abs_100u_25_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_32_ioutp_abs_100u_26_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_32_ioutp_abs_100u_27_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_32_ioutp_abs_100u_28_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_32_ioutp_abs_100u_29_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_32_ioutp_abs_100u_30_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_3_afe_odac_0_reg_sp_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_3_odac1_gmsb_attr == 5'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_3_odac2_gmsb_attr == 5'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_3_odac3_gmsb_attr == 5'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_3_odac_en_attr == SERDES_LANE_ANA_RX1_LANE2_REG_3_ODAC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_3_odac_range_attr == SERDES_LANE_ANA_RX1_LANE2_REG_3_ODAC_RANGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_4_afe_odac_1_reg_sp_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_4_odac1_gdmc_attr == 5'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_4_odac1_glsb_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_4_odac2_gdmc_attr == 5'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_4_odac2_glsb_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_4_odac3_glsb_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_5_afe_refgen_0_reg_sp_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_5_rgen_bitrm0p5_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_5_rgen_bitrm1p0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_5_rgen_bvtrm0p5_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_5_rgen_bvtrm1p0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_6_afe_refgen_1_reg_sp_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_6_rgen_bsel1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_6_rgen_bsel2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_6_rgen_bsel3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_6_rgen_bseli_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_7_afe_bivcm_reg_sp_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_7_st1_bivcm_n_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_7_st1_bivcm_p_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_7_st2_bivcm_n_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_7_st2_bivcm_p_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_7_st3_bivcm_n_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_7_st3_bivcm_p_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_8_afe_inp_rtrm_reg_sp_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_8_afe_lpbk_en_attr == SERDES_LANE_ANA_RX1_LANE2_REG_8_AFE_LPBK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_8_afe_slicer_in_attr == SERDES_LANE_ANA_RX1_LANE2_REG_8_AFE_SLICER_IN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_8_in_bypass_attr == SERDES_LANE_ANA_RX1_LANE2_REG_8_IN_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_8_inp_trmc_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_8_inp_trmp0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_8_inp_trmp1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_8_inp_trmp2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_8_rtrm_btune_attr == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_8_rtrm_vcm_swt_attr == SERDES_LANE_ANA_RX1_LANE2_REG_8_RTRM_VCM_SWT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane2_reg_9_afe_spare_0_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_10_afe_spare_1_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_11_afe_spare_2_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_12_afe_st1_config_1_reg_spare_attr == SERDES_LANE_ANA_RX1_LANE3_REG_12_AFE_ST1_CONFIG_1_REG_SPARE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_12_st1_en_vcmbf_attr == SERDES_LANE_ANA_RX1_LANE3_REG_12_ST1_EN_VCMBF_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_12_st1_ggain_n_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_12_st1_ggain_p_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_12_st1_grload_attr == 6'd34
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_12_st1_vcmnshift_attr == SERDES_LANE_ANA_RX1_LANE3_REG_12_ST1_VCMNSHIFT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_12_st3_bpktrm_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_13_afe_st2_config_reg_sp_attr == SERDES_LANE_ANA_RX1_LANE3_REG_13_AFE_ST2_CONFIG_REG_SP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_13_st2_bctune_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_13_st2_en_vcmbf_attr == SERDES_LANE_ANA_RX1_LANE3_REG_13_ST2_EN_VCMBF_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_13_st2_ggain_n_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_13_st2_ggain_p_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_13_st2_grload_attr == 6'd34
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_13_st2_vcmshift_attr == SERDES_LANE_ANA_RX1_LANE3_REG_13_ST2_VCMSHIFT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_14_afe_st3_config_reg_spare_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_14_st3_brload_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_14_st3_en_vcmbf_attr == SERDES_LANE_ANA_RX1_LANE3_REG_14_ST3_EN_VCMBF_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_14_st3_ggain_n_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_14_st3_ggain_p_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_14_st3_vcmshift_attr == SERDES_LANE_ANA_RX1_LANE3_REG_14_ST3_VCMSHIFT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_15_ioutp_abs_100u_31_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_15_ioutp_abs_100u_32_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_15_ioutp_abs_100u_33_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_15_ioutp_abs_100u_34_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_15_ioutp_abs_100u_35_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_15_ioutp_abs_100u_36_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_16_ioutp_abs_100u_37_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_16_ioutp_abs_100u_38_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_16_ioutp_abs_100u_39_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_16_ioutp_abs_100u_40_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_16_ioutp_abs_100u_41_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_16_ioutp_abs_100u_42_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_17_ioutp_abs_100u_43_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_17_ioutp_abs_100u_44_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_17_ioutp_abs_100u_45_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_17_ioutp_abs_100u_46_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_17_ioutp_abs_100u_47_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_17_ioutp_abs_100u_48_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_18_dcmon1_en_attr == SERDES_LANE_ANA_RX1_LANE3_REG_18_DCMON1_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_18_dcmon1_minus_100ua_attr == SERDES_LANE_ANA_RX1_LANE3_REG_18_DCMON1_MINUS_100UA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_18_dcmon1_minus_50ua_attr == SERDES_LANE_ANA_RX1_LANE3_REG_18_DCMON1_MINUS_50UA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_18_dcmon1_minus_v_n_attr == SERDES_LANE_ANA_RX1_LANE3_REG_18_DCMON1_MINUS_V_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_18_dcmon1_minus_v_p_attr == SERDES_LANE_ANA_RX1_LANE3_REG_18_DCMON1_MINUS_V_P_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_18_dcmon2_en_attr == SERDES_LANE_ANA_RX1_LANE3_REG_18_DCMON2_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_18_dcmon2_minus_100ua_attr == SERDES_LANE_ANA_RX1_LANE3_REG_18_DCMON2_MINUS_100UA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_18_dcmon2_minus_50ua_attr == SERDES_LANE_ANA_RX1_LANE3_REG_18_DCMON2_MINUS_50UA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_18_ioutp_abs_100u_49_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_18_ioutp_abs_100u_50_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_18_spare_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_18_vref_n_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_18_vref_p_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_19_ioutn_abs_50u_0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_19_ioutn_abs_50u_1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_19_ioutn_abs_50u_2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_19_ioutn_abs_50u_3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_19_ioutn_abs_50u_4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_19_ioutn_abs_50u_d_n_master_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_1_afe_bias_reg_sp_attr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_1_bias_en400_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_20_ioutn_abs_50u_10_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_20_ioutn_abs_50u_5_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_20_ioutn_abs_50u_6_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_20_ioutn_abs_50u_7_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_20_ioutn_abs_50u_8_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_20_ioutn_abs_50u_9_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_21_ioutn_abs_50u_11_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_21_ioutn_abs_50u_12_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_21_ioutn_abs_50u_13_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_21_ioutn_abs_50u_14_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_21_ioutn_abs_50u_15_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_21_ioutn_abs_50u_16_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_22_ioutn_abs_100u_0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_22_ioutn_abs_100u_1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_22_ioutn_abs_100u_2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_22_ioutn_abs_100u_3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_22_ioutn_abs_50u_17_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_22_ioutn_abs_50u_18_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_23_ioutn_abs_100u_4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_23_ioutn_abs_100u_5_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_23_ioutn_abs_100u_6_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_23_ioutn_abs_100u_7_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_23_ioutn_abs_100u_8_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_23_ioutn_abs_100u_9_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_24_ioutn_abs_100u_10_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_24_ioutn_abs_100u_11_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_24_ioutn_abs_100u_12_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_24_ioutn_abs_100u_13_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_24_ioutn_abs_100u_14_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_24_ioutn_abs_100u_15_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_25_ioutn_abs_100u_16_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_25_ioutn_abs_100u_17_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_25_ioutn_abs_100u_18_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_25_ioutn_abs_100u_19_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_25_ioutn_abs_100u_20_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_25_ioutn_abs_100u_21_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_26_ioutn_abs_100u_22_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_26_ioutn_abs_100u_23_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_26_ioutn_abs_100u_24_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_26_ioutn_abs_100u_25_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_26_ioutn_abs_100u_pchref_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_26_ioutn_abs_100u_tx1to100_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_27_ioutn_abs_200u_0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_27_ioutn_abs_200u_1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_27_ioutn_abs_200u_2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_27_ioutn_abs_200u_3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_27_ioutn_abs_200u_4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_27_ioutp_abs_100u_0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_28_ioutp_abs_100u_1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_28_ioutp_abs_100u_2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_28_ioutp_abs_100u_3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_28_ioutp_abs_100u_4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_28_ioutp_abs_100u_5_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_28_ioutp_abs_100u_6_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_29_ioutp_abs_100u_10_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_29_ioutp_abs_100u_11_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_29_ioutp_abs_100u_12_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_29_ioutp_abs_100u_7_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_29_ioutp_abs_100u_8_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_29_ioutp_abs_100u_9_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_2_en_acmp_attr == SERDES_LANE_ANA_RX1_LANE3_REG_2_EN_ACMP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_2_en_amon_attr == SERDES_LANE_ANA_RX1_LANE3_REG_2_EN_AMON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_2_inp_monen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_2_rgen_monen_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_2_rtrm_monen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_2_st1_monen_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_2_st2_monen_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_2_st3_monen_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_30_ioutp_abs_100u_13_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_30_ioutp_abs_100u_14_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_30_ioutp_abs_100u_15_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_30_ioutp_abs_100u_16_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_30_ioutp_abs_100u_17_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_30_ioutp_abs_100u_18_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_31_ioutp_abs_100u_19_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_31_ioutp_abs_100u_20_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_31_ioutp_abs_100u_21_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_31_ioutp_abs_100u_22_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_31_ioutp_abs_100u_23_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_31_ioutp_abs_100u_24_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_32_ioutp_abs_100u_25_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_32_ioutp_abs_100u_26_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_32_ioutp_abs_100u_27_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_32_ioutp_abs_100u_28_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_32_ioutp_abs_100u_29_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_32_ioutp_abs_100u_30_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_3_afe_odac_0_reg_sp_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_3_odac1_gmsb_attr == 5'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_3_odac2_gmsb_attr == 5'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_3_odac3_gmsb_attr == 5'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_3_odac_en_attr == SERDES_LANE_ANA_RX1_LANE3_REG_3_ODAC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_3_odac_range_attr == SERDES_LANE_ANA_RX1_LANE3_REG_3_ODAC_RANGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_4_afe_odac_1_reg_sp_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_4_odac1_gdmc_attr == 5'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_4_odac1_glsb_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_4_odac2_gdmc_attr == 5'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_4_odac2_glsb_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_4_odac3_glsb_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_5_afe_refgen_0_reg_sp_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_5_rgen_bitrm0p5_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_5_rgen_bitrm1p0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_5_rgen_bvtrm0p5_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_5_rgen_bvtrm1p0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_6_afe_refgen_1_reg_sp_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_6_rgen_bsel1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_6_rgen_bsel2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_6_rgen_bsel3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_6_rgen_bseli_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_7_afe_bivcm_reg_sp_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_7_st1_bivcm_n_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_7_st1_bivcm_p_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_7_st2_bivcm_n_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_7_st2_bivcm_p_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_7_st3_bivcm_n_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_7_st3_bivcm_p_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_8_afe_inp_rtrm_reg_sp_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_8_afe_lpbk_en_attr == SERDES_LANE_ANA_RX1_LANE3_REG_8_AFE_LPBK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_8_afe_slicer_in_attr == SERDES_LANE_ANA_RX1_LANE3_REG_8_AFE_SLICER_IN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_8_in_bypass_attr == SERDES_LANE_ANA_RX1_LANE3_REG_8_IN_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_8_inp_trmc_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_8_inp_trmp0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_8_inp_trmp1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_8_inp_trmp2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_8_rtrm_btune_attr == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_8_rtrm_vcm_swt_attr == SERDES_LANE_ANA_RX1_LANE3_REG_8_RTRM_VCM_SWT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx1_lane3_reg_9_afe_spare_0_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane0_reg_1_vref_cmp_sel_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane0_reg_1_vref_dcmon_cmp_en_attr == SERDES_LANE_ANA_RX2_LANE0_REG_1_VREF_DCMON_CMP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane0_reg_1_vref_dcmon_ldo_0p8_en_attr == SERDES_LANE_ANA_RX2_LANE0_REG_1_VREF_DCMON_LDO_0P8_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane0_reg_1_vref_dcmon_ldo_0p9_en_attr == SERDES_LANE_ANA_RX2_LANE0_REG_1_VREF_DCMON_LDO_0P9_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane0_reg_1_vref_dcmon_sampler_en_attr == SERDES_LANE_ANA_RX2_LANE0_REG_1_VREF_DCMON_SAMPLER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane0_reg_1_vref_sampler_sel_attr == 10'd603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane0_reg_2_vref_ldo_0p8_sel_attr == 10'd902
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane0_reg_2_vref_ldo_0p9_sel_attr == 10'd972
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane0_reg_2_vref_ldo_spare_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane0_reg_3_comp_en_attr == SERDES_LANE_ANA_RX2_LANE0_REG_3_COMP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane0_reg_3_ofstn_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane0_reg_3_ofstn_sgn_attr == SERDES_LANE_ANA_RX2_LANE0_REG_3_OFSTN_SGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane0_reg_3_ofstp_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane0_reg_3_ofstp_sgn_attr == SERDES_LANE_ANA_RX2_LANE0_REG_3_OFSTP_SGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane0_reg_3_pre_cmp_seln_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane0_reg_3_pre_cmp_selp_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane0_reg_3_rx_comparator_spare_nc_attr == SERDES_LANE_ANA_RX2_LANE0_REG_3_RX_COMPARATOR_SPARE_NC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane0_reg_4_rx_comparator_spare_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane0_reg_5_dco_buf_vcm_trim_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane0_reg_5_dco_cal_sp_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane0_reg_5_dco_ctail_trim_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane0_reg_5_dco_ibuf_trim_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane0_reg_5_dco_vb2comp_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane0_reg_5_dco_vb_gate_trim_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane0_reg_6_dco_cs_rtrim_attr == 7'd38
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane0_reg_6_dco_cs_vbn2_trim_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane0_reg_6_dco_cs_vbp2_trim_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane0_reg_6_dco_vcpi_trim_attr == 8'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane0_reg_6_inabs400u_en_attr == SERDES_LANE_ANA_RX2_LANE0_REG_6_INABS400U_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane0_reg_7_dco_dcmon1_en_attr == SERDES_LANE_ANA_RX2_LANE0_REG_7_DCO_DCMON1_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane0_reg_7_dco_dcmon1_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane0_reg_7_dco_dcmon2_en_attr == SERDES_LANE_ANA_RX2_LANE0_REG_7_DCO_DCMON2_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane0_reg_7_dco_dcmon2_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane0_reg_7_dco_tst_sp_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane1_reg_1_vref_cmp_sel_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane1_reg_1_vref_dcmon_cmp_en_attr == SERDES_LANE_ANA_RX2_LANE1_REG_1_VREF_DCMON_CMP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane1_reg_1_vref_dcmon_ldo_0p8_en_attr == SERDES_LANE_ANA_RX2_LANE1_REG_1_VREF_DCMON_LDO_0P8_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane1_reg_1_vref_dcmon_ldo_0p9_en_attr == SERDES_LANE_ANA_RX2_LANE1_REG_1_VREF_DCMON_LDO_0P9_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane1_reg_1_vref_dcmon_sampler_en_attr == SERDES_LANE_ANA_RX2_LANE1_REG_1_VREF_DCMON_SAMPLER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane1_reg_1_vref_sampler_sel_attr == 10'd603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane1_reg_2_vref_ldo_0p8_sel_attr == 10'd902
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane1_reg_2_vref_ldo_0p9_sel_attr == 10'd972
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane1_reg_2_vref_ldo_spare_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane1_reg_3_comp_en_attr == SERDES_LANE_ANA_RX2_LANE1_REG_3_COMP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane1_reg_3_ofstn_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane1_reg_3_ofstn_sgn_attr == SERDES_LANE_ANA_RX2_LANE1_REG_3_OFSTN_SGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane1_reg_3_ofstp_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane1_reg_3_ofstp_sgn_attr == SERDES_LANE_ANA_RX2_LANE1_REG_3_OFSTP_SGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane1_reg_3_pre_cmp_seln_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane1_reg_3_pre_cmp_selp_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane1_reg_3_rx_comparator_spare_nc_attr == SERDES_LANE_ANA_RX2_LANE1_REG_3_RX_COMPARATOR_SPARE_NC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane1_reg_4_rx_comparator_spare_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane1_reg_5_dco_buf_vcm_trim_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane1_reg_5_dco_cal_sp_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane1_reg_5_dco_ctail_trim_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane1_reg_5_dco_ibuf_trim_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane1_reg_5_dco_vb2comp_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane1_reg_5_dco_vb_gate_trim_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane1_reg_6_dco_cs_rtrim_attr == 7'd38
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane1_reg_6_dco_cs_vbn2_trim_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane1_reg_6_dco_cs_vbp2_trim_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane1_reg_6_dco_vcpi_trim_attr == 8'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane1_reg_6_inabs400u_en_attr == SERDES_LANE_ANA_RX2_LANE1_REG_6_INABS400U_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane1_reg_7_dco_dcmon1_en_attr == SERDES_LANE_ANA_RX2_LANE1_REG_7_DCO_DCMON1_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane1_reg_7_dco_dcmon1_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane1_reg_7_dco_dcmon2_en_attr == SERDES_LANE_ANA_RX2_LANE1_REG_7_DCO_DCMON2_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane1_reg_7_dco_dcmon2_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane1_reg_7_dco_tst_sp_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane2_reg_1_vref_cmp_sel_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane2_reg_1_vref_dcmon_cmp_en_attr == SERDES_LANE_ANA_RX2_LANE2_REG_1_VREF_DCMON_CMP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane2_reg_1_vref_dcmon_ldo_0p8_en_attr == SERDES_LANE_ANA_RX2_LANE2_REG_1_VREF_DCMON_LDO_0P8_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane2_reg_1_vref_dcmon_ldo_0p9_en_attr == SERDES_LANE_ANA_RX2_LANE2_REG_1_VREF_DCMON_LDO_0P9_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane2_reg_1_vref_dcmon_sampler_en_attr == SERDES_LANE_ANA_RX2_LANE2_REG_1_VREF_DCMON_SAMPLER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane2_reg_1_vref_sampler_sel_attr == 10'd603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane2_reg_2_vref_ldo_0p8_sel_attr == 10'd902
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane2_reg_2_vref_ldo_0p9_sel_attr == 10'd972
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane2_reg_2_vref_ldo_spare_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane2_reg_3_comp_en_attr == SERDES_LANE_ANA_RX2_LANE2_REG_3_COMP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane2_reg_3_ofstn_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane2_reg_3_ofstn_sgn_attr == SERDES_LANE_ANA_RX2_LANE2_REG_3_OFSTN_SGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane2_reg_3_ofstp_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane2_reg_3_ofstp_sgn_attr == SERDES_LANE_ANA_RX2_LANE2_REG_3_OFSTP_SGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane2_reg_3_pre_cmp_seln_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane2_reg_3_pre_cmp_selp_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane2_reg_3_rx_comparator_spare_nc_attr == SERDES_LANE_ANA_RX2_LANE2_REG_3_RX_COMPARATOR_SPARE_NC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane2_reg_4_rx_comparator_spare_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane2_reg_5_dco_buf_vcm_trim_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane2_reg_5_dco_cal_sp_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane2_reg_5_dco_ctail_trim_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane2_reg_5_dco_ibuf_trim_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane2_reg_5_dco_vb2comp_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane2_reg_5_dco_vb_gate_trim_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane2_reg_6_dco_cs_rtrim_attr == 7'd38
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane2_reg_6_dco_cs_vbn2_trim_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane2_reg_6_dco_cs_vbp2_trim_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane2_reg_6_dco_vcpi_trim_attr == 8'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane2_reg_6_inabs400u_en_attr == SERDES_LANE_ANA_RX2_LANE2_REG_6_INABS400U_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane2_reg_7_dco_dcmon1_en_attr == SERDES_LANE_ANA_RX2_LANE2_REG_7_DCO_DCMON1_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane2_reg_7_dco_dcmon1_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane2_reg_7_dco_dcmon2_en_attr == SERDES_LANE_ANA_RX2_LANE2_REG_7_DCO_DCMON2_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane2_reg_7_dco_dcmon2_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane2_reg_7_dco_tst_sp_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane3_reg_1_vref_cmp_sel_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane3_reg_1_vref_dcmon_cmp_en_attr == SERDES_LANE_ANA_RX2_LANE3_REG_1_VREF_DCMON_CMP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane3_reg_1_vref_dcmon_ldo_0p8_en_attr == SERDES_LANE_ANA_RX2_LANE3_REG_1_VREF_DCMON_LDO_0P8_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane3_reg_1_vref_dcmon_ldo_0p9_en_attr == SERDES_LANE_ANA_RX2_LANE3_REG_1_VREF_DCMON_LDO_0P9_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane3_reg_1_vref_dcmon_sampler_en_attr == SERDES_LANE_ANA_RX2_LANE3_REG_1_VREF_DCMON_SAMPLER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane3_reg_1_vref_sampler_sel_attr == 10'd603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane3_reg_2_vref_ldo_0p8_sel_attr == 10'd902
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane3_reg_2_vref_ldo_0p9_sel_attr == 10'd972
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane3_reg_2_vref_ldo_spare_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane3_reg_3_comp_en_attr == SERDES_LANE_ANA_RX2_LANE3_REG_3_COMP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane3_reg_3_ofstn_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane3_reg_3_ofstn_sgn_attr == SERDES_LANE_ANA_RX2_LANE3_REG_3_OFSTN_SGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane3_reg_3_ofstp_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane3_reg_3_ofstp_sgn_attr == SERDES_LANE_ANA_RX2_LANE3_REG_3_OFSTP_SGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane3_reg_3_pre_cmp_seln_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane3_reg_3_pre_cmp_selp_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane3_reg_3_rx_comparator_spare_nc_attr == SERDES_LANE_ANA_RX2_LANE3_REG_3_RX_COMPARATOR_SPARE_NC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane3_reg_4_rx_comparator_spare_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane3_reg_5_dco_buf_vcm_trim_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane3_reg_5_dco_cal_sp_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane3_reg_5_dco_ctail_trim_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane3_reg_5_dco_ibuf_trim_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane3_reg_5_dco_vb2comp_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane3_reg_5_dco_vb_gate_trim_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane3_reg_6_dco_cs_rtrim_attr == 7'd38
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane3_reg_6_dco_cs_vbn2_trim_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane3_reg_6_dco_cs_vbp2_trim_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane3_reg_6_dco_vcpi_trim_attr == 8'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane3_reg_6_inabs400u_en_attr == SERDES_LANE_ANA_RX2_LANE3_REG_6_INABS400U_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane3_reg_7_dco_dcmon1_en_attr == SERDES_LANE_ANA_RX2_LANE3_REG_7_DCO_DCMON1_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane3_reg_7_dco_dcmon1_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane3_reg_7_dco_dcmon2_en_attr == SERDES_LANE_ANA_RX2_LANE3_REG_7_DCO_DCMON2_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane3_reg_7_dco_dcmon2_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_rx2_lane3_reg_7_dco_tst_sp_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_10_csr_txclk_amon_pulldown_en_attr == SERDES_LANE_ANA_TX_LANE0_REG_10_CSR_TXCLK_AMON_PULLDOWN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_10_csr_txclk_amoni_sel_attr == SERDES_LANE_ANA_TX_LANE0_REG_10_CSR_TXCLK_AMONI_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_10_csr_txclk_amonv_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_10_csr_txclk_clk_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_10_csr_txclk_clk_ph_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_10_csr_txclk_dcc_amon_en_i_attr == SERDES_LANE_ANA_TX_LANE0_REG_10_CSR_TXCLK_DCC_AMON_EN_I_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_10_csr_txclk_dcc_amon_en_q_attr == SERDES_LANE_ANA_TX_LANE0_REG_10_CSR_TXCLK_DCC_AMON_EN_Q_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_10_csr_txclk_dcc_crs_vrefn_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_10_csr_txclk_dcc_crs_vrefp_sel_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_10_csr_txclk_div_ratio_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_10_csr_txclk_ibias_ctrl_dcc_dacn_i_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_10_csr_txclk_ibias_ctrl_dcc_dacn_q_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_10_csr_txclk_ibias_ctrl_dcc_dacp_i_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_10_csr_txclk_ibias_ctrl_dcc_dacp_q_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_11_csr_qec_crs_dll_cntrl_clk270_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_11_csr_qec_crs_dll_cntrl_clk90_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_11_csr_qec_crs_dll_inv_cntrl_clk270_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_11_csr_qec_crs_dll_inv_cntrl_clk90_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_12_csr_qec_crs_cntrl_clk0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_12_csr_qec_crs_cntrl_clk180_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_12_csr_qec_crs_cntrl_clk270_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_12_csr_qec_crs_cntrl_clk90_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_12_csr_qec_crs_inv_cntrl_clk0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_12_csr_qec_crs_inv_cntrl_clk180_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_12_csr_qec_crs_inv_cntrl_clk270_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_12_csr_qec_crs_inv_cntrl_clk90_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_13_csr_qec_fine_cntrl_clk0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_13_csr_qec_fine_cntrl_clk180_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_13_csr_qec_fine_cntrl_clk270_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_13_csr_qec_fine_cntrl_clk90_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_14_csr_ldo_bypass_0p8_en_attr == SERDES_LANE_ANA_TX_LANE0_REG_14_CSR_LDO_BYPASS_0P8_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_14_csr_ldo_bypass_0p9_en_attr == SERDES_LANE_ANA_TX_LANE0_REG_14_CSR_LDO_BYPASS_0P9_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_14_csr_ldo_cmp_out_en_attr == SERDES_LANE_ANA_TX_LANE0_REG_14_CSR_LDO_CMP_OUT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_14_csr_ldo_cmp_out_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_14_csr_ldo_dcmon_en_attr == SERDES_LANE_ANA_TX_LANE0_REG_14_CSR_LDO_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_14_csr_ldo_dcmon_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_14_csr_ldo_enable_attr == SERDES_LANE_ANA_TX_LANE0_REG_14_CSR_LDO_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_14_csr_ldo_leaker_en_attr == SERDES_LANE_ANA_TX_LANE0_REG_14_CSR_LDO_LEAKER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_14_csr_ldo_leaker_tune_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_14_csr_ldo_pwrdn_en_attr == SERDES_LANE_ANA_TX_LANE0_REG_14_CSR_LDO_PWRDN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_15_csr_drv_pd_cs_nmos_attr == 18'd16383
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_15_csr_drv_rterm_enb_attr == SERDES_LANE_ANA_TX_LANE0_REG_15_CSR_DRV_RTERM_ENB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_15_csr_loadgen_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_15_csr_pisoclk_flip_attr == SERDES_LANE_ANA_TX_LANE0_REG_15_CSR_PISOCLK_FLIP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_15_csr_tx_rterm_ctl_attr == 7'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_16_csr_drv_cs_com_enb_attr == SERDES_LANE_ANA_TX_LANE0_REG_16_CSR_DRV_CS_COM_ENB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_16_csr_drv_tx_cmp_rd_select_attr == SERDES_LANE_ANA_TX_LANE0_REG_16_CSR_DRV_TX_CMP_RD_SELECT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_16_csr_drv_tx_mode64b0_32b1_attr == SERDES_LANE_ANA_TX_LANE0_REG_16_CSR_DRV_TX_MODE64B0_32B1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_17_reg2hwa_cfg_avg_eng_start_attr == SERDES_LANE_ANA_TX_LANE0_REG_17_REG2HWA_CFG_AVG_ENG_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_18_reg2hwa_cfg_avg_eng_limit_attr == 32'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_1_csr_lgc_reset_bar_attr == SERDES_LANE_ANA_TX_LANE0_REG_1_CSR_LGC_RESET_BAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_22_csr_lanedig_o_ldo_stable_attr == SERDES_LANE_ANA_TX_LANE0_REG_22_CSR_LANEDIG_O_LDO_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_22_csr_lanedig_o_tx_caldone_attr == SERDES_LANE_ANA_TX_LANE0_REG_22_CSR_LANEDIG_O_TX_CALDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_22_csr_lanedig_o_txclk_ready_attr == SERDES_LANE_ANA_TX_LANE0_REG_22_CSR_LANEDIG_O_TXCLK_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_22_csr_probe0_select_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_22_csr_probe0_txvisa_en_attr == SERDES_LANE_ANA_TX_LANE0_REG_22_CSR_PROBE0_TXVISA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_22_csr_probe1_select_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_22_csr_probe1_txvisa_en_attr == SERDES_LANE_ANA_TX_LANE0_REG_22_CSR_PROBE1_TXVISA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_23_cmp_mirror_reg_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_24_csr_dcc_crs_cntrl_clk0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_24_csr_dcc_crs_cntrl_clk180_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_24_csr_dcc_crs_incr_clk0_attr == SERDES_LANE_ANA_TX_LANE0_REG_24_CSR_DCC_CRS_INCR_CLK0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_24_csr_dcc_crs_incr_clk180_attr == SERDES_LANE_ANA_TX_LANE0_REG_24_CSR_DCC_CRS_INCR_CLK180_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_24_csr_dcc_crs_range_clk0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_24_csr_dcc_crs_range_clk180_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_25_csr_dcc_crs_cntrl_clk270_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_25_csr_dcc_crs_cntrl_clk90_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_25_csr_dcc_crs_incr_clk270_attr == SERDES_LANE_ANA_TX_LANE0_REG_25_CSR_DCC_CRS_INCR_CLK270_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_25_csr_dcc_crs_incr_clk90_attr == SERDES_LANE_ANA_TX_LANE0_REG_25_CSR_DCC_CRS_INCR_CLK90_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_25_csr_dcc_crs_range_clk270_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_25_csr_dcc_crs_range_clk90_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_26_csr_dcc_fine_cntrl_clk0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_26_csr_dcc_fine_cntrl_clk180_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_26_csr_dcc_fine_incr_clk0_attr == SERDES_LANE_ANA_TX_LANE0_REG_26_CSR_DCC_FINE_INCR_CLK0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_26_csr_dcc_fine_incr_clk180_attr == SERDES_LANE_ANA_TX_LANE0_REG_26_CSR_DCC_FINE_INCR_CLK180_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_26_csr_dcc_fine_range_clk0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_26_csr_dcc_fine_range_clk180_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_27_csr_dcc_fine_cntrl_clk270_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_27_csr_dcc_fine_cntrl_clk90_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_27_csr_dcc_fine_incr_clk270_attr == SERDES_LANE_ANA_TX_LANE0_REG_27_CSR_DCC_FINE_INCR_CLK270_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_27_csr_dcc_fine_incr_clk90_attr == SERDES_LANE_ANA_TX_LANE0_REG_27_CSR_DCC_FINE_INCR_CLK90_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_27_csr_dcc_fine_range_clk270_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_27_csr_dcc_fine_range_clk90_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_28_csr_drv_amon0_en_attr == SERDES_LANE_ANA_TX_LANE0_REG_28_CSR_DRV_AMON0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_28_csr_drv_amon0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_28_csr_drv_amon1_en_attr == SERDES_LANE_ANA_TX_LANE0_REG_28_CSR_DRV_AMON1_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_28_csr_drv_amon1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_28_csr_drv_pk_det_vref_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_28_csr_drv_vbn1_par_en_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_29_csr_drv_iq_amp_calib_en_attr == SERDES_LANE_ANA_TX_LANE0_REG_29_CSR_DRV_IQ_AMP_CALIB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_29_csr_drv_iq_amp_cm_cntrl_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_29_csr_drv_iq_amp_en_attr == SERDES_LANE_ANA_TX_LANE0_REG_29_CSR_DRV_IQ_AMP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_29_csr_drv_iq_amp_vref_sel_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_29_csr_drv_lpb_sel_attr == SERDES_LANE_ANA_TX_LANE0_REG_29_CSR_DRV_LPB_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_29_csr_drv_pd_cs_bias2_attr == SERDES_LANE_ANA_TX_LANE0_REG_29_CSR_DRV_PD_CS_BIAS2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_29_csr_drv_replica_dis_attr == SERDES_LANE_ANA_TX_LANE0_REG_29_CSR_DRV_REPLICA_DIS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_29_csr_drv_tx_cmp_clk_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_29_csr_tx_switch_en_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_2_o_spare_a_rw_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_3_o_spare_b_rw_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_5_cmp_addr_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_5_cmp_addr_mask_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_5_cmp_mirror_rd_select_attr == SERDES_LANE_ANA_TX_LANE0_REG_5_CMP_MIRROR_RD_SELECT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_6_csr_txclk_dfx1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_6_csr_txclk_dfx2_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_6_csr_txclk_dfx_dfx1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_6_csr_txclk_dfx_lm1_en_attr == SERDES_LANE_ANA_TX_LANE0_REG_6_CSR_TXCLK_DFX_LM1_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_6_csr_txclk_dfx_lm_lp_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_6_csr_txffe_pll_dpso_sel_attr == SERDES_LANE_ANA_TX_LANE0_REG_6_CSR_TXFFE_PLL_DPSO_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_7_csr_txffe_coeff_0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_7_csr_txffe_coeff_load_attr == SERDES_LANE_ANA_TX_LANE0_REG_7_CSR_TXFFE_COEFF_LOAD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_7_csr_txffe_coeff_m1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_7_csr_txffe_coeff_m2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_7_csr_txffe_coeff_p1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_7_csr_txffe_mode32ui_attr == SERDES_LANE_ANA_TX_LANE0_REG_7_CSR_TXFFE_MODE32UI_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_7_csr_txffe_output_swizzle_attr == SERDES_LANE_ANA_TX_LANE0_REG_7_CSR_TXFFE_OUTPUT_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_8_csr_txffe_coeff_p2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_8_csr_txffe_coeff_p3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_8_csr_txffe_coeff_p4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_8_csr_txffe_coeff_p5_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane0_reg_9_csr_txffe_cmod_attr == 9'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_10_csr_txclk_amon_pulldown_en_attr == SERDES_LANE_ANA_TX_LANE1_REG_10_CSR_TXCLK_AMON_PULLDOWN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_10_csr_txclk_amoni_sel_attr == SERDES_LANE_ANA_TX_LANE1_REG_10_CSR_TXCLK_AMONI_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_10_csr_txclk_amonv_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_10_csr_txclk_clk_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_10_csr_txclk_clk_ph_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_10_csr_txclk_dcc_amon_en_i_attr == SERDES_LANE_ANA_TX_LANE1_REG_10_CSR_TXCLK_DCC_AMON_EN_I_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_10_csr_txclk_dcc_amon_en_q_attr == SERDES_LANE_ANA_TX_LANE1_REG_10_CSR_TXCLK_DCC_AMON_EN_Q_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_10_csr_txclk_dcc_crs_vrefn_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_10_csr_txclk_dcc_crs_vrefp_sel_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_10_csr_txclk_div_ratio_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_10_csr_txclk_ibias_ctrl_dcc_dacn_i_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_10_csr_txclk_ibias_ctrl_dcc_dacn_q_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_10_csr_txclk_ibias_ctrl_dcc_dacp_i_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_10_csr_txclk_ibias_ctrl_dcc_dacp_q_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_11_csr_qec_crs_dll_cntrl_clk270_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_11_csr_qec_crs_dll_cntrl_clk90_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_11_csr_qec_crs_dll_inv_cntrl_clk270_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_11_csr_qec_crs_dll_inv_cntrl_clk90_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_12_csr_qec_crs_cntrl_clk0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_12_csr_qec_crs_cntrl_clk180_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_12_csr_qec_crs_cntrl_clk270_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_12_csr_qec_crs_cntrl_clk90_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_12_csr_qec_crs_inv_cntrl_clk0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_12_csr_qec_crs_inv_cntrl_clk180_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_12_csr_qec_crs_inv_cntrl_clk270_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_12_csr_qec_crs_inv_cntrl_clk90_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_13_csr_qec_fine_cntrl_clk0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_13_csr_qec_fine_cntrl_clk180_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_13_csr_qec_fine_cntrl_clk270_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_13_csr_qec_fine_cntrl_clk90_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_14_csr_ldo_bypass_0p8_en_attr == SERDES_LANE_ANA_TX_LANE1_REG_14_CSR_LDO_BYPASS_0P8_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_14_csr_ldo_bypass_0p9_en_attr == SERDES_LANE_ANA_TX_LANE1_REG_14_CSR_LDO_BYPASS_0P9_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_14_csr_ldo_cmp_out_en_attr == SERDES_LANE_ANA_TX_LANE1_REG_14_CSR_LDO_CMP_OUT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_14_csr_ldo_cmp_out_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_14_csr_ldo_dcmon_en_attr == SERDES_LANE_ANA_TX_LANE1_REG_14_CSR_LDO_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_14_csr_ldo_dcmon_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_14_csr_ldo_enable_attr == SERDES_LANE_ANA_TX_LANE1_REG_14_CSR_LDO_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_14_csr_ldo_leaker_en_attr == SERDES_LANE_ANA_TX_LANE1_REG_14_CSR_LDO_LEAKER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_14_csr_ldo_leaker_tune_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_14_csr_ldo_pwrdn_en_attr == SERDES_LANE_ANA_TX_LANE1_REG_14_CSR_LDO_PWRDN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_15_csr_drv_pd_cs_nmos_attr == 18'd16383
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_15_csr_drv_rterm_enb_attr == SERDES_LANE_ANA_TX_LANE1_REG_15_CSR_DRV_RTERM_ENB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_15_csr_loadgen_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_15_csr_pisoclk_flip_attr == SERDES_LANE_ANA_TX_LANE1_REG_15_CSR_PISOCLK_FLIP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_15_csr_tx_rterm_ctl_attr == 7'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_16_csr_drv_cs_com_enb_attr == SERDES_LANE_ANA_TX_LANE1_REG_16_CSR_DRV_CS_COM_ENB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_16_csr_drv_tx_cmp_rd_select_attr == SERDES_LANE_ANA_TX_LANE1_REG_16_CSR_DRV_TX_CMP_RD_SELECT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_16_csr_drv_tx_mode64b0_32b1_attr == SERDES_LANE_ANA_TX_LANE1_REG_16_CSR_DRV_TX_MODE64B0_32B1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_17_reg2hwa_cfg_avg_eng_start_attr == SERDES_LANE_ANA_TX_LANE1_REG_17_REG2HWA_CFG_AVG_ENG_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_18_reg2hwa_cfg_avg_eng_limit_attr == 32'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_1_csr_lgc_reset_bar_attr == SERDES_LANE_ANA_TX_LANE1_REG_1_CSR_LGC_RESET_BAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_22_csr_lanedig_o_ldo_stable_attr == SERDES_LANE_ANA_TX_LANE1_REG_22_CSR_LANEDIG_O_LDO_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_22_csr_lanedig_o_tx_caldone_attr == SERDES_LANE_ANA_TX_LANE1_REG_22_CSR_LANEDIG_O_TX_CALDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_22_csr_lanedig_o_txclk_ready_attr == SERDES_LANE_ANA_TX_LANE1_REG_22_CSR_LANEDIG_O_TXCLK_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_22_csr_probe0_select_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_22_csr_probe0_txvisa_en_attr == SERDES_LANE_ANA_TX_LANE1_REG_22_CSR_PROBE0_TXVISA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_22_csr_probe1_select_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_22_csr_probe1_txvisa_en_attr == SERDES_LANE_ANA_TX_LANE1_REG_22_CSR_PROBE1_TXVISA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_23_cmp_mirror_reg_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_24_csr_dcc_crs_cntrl_clk0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_24_csr_dcc_crs_cntrl_clk180_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_24_csr_dcc_crs_incr_clk0_attr == SERDES_LANE_ANA_TX_LANE1_REG_24_CSR_DCC_CRS_INCR_CLK0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_24_csr_dcc_crs_incr_clk180_attr == SERDES_LANE_ANA_TX_LANE1_REG_24_CSR_DCC_CRS_INCR_CLK180_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_24_csr_dcc_crs_range_clk0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_24_csr_dcc_crs_range_clk180_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_25_csr_dcc_crs_cntrl_clk270_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_25_csr_dcc_crs_cntrl_clk90_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_25_csr_dcc_crs_incr_clk270_attr == SERDES_LANE_ANA_TX_LANE1_REG_25_CSR_DCC_CRS_INCR_CLK270_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_25_csr_dcc_crs_incr_clk90_attr == SERDES_LANE_ANA_TX_LANE1_REG_25_CSR_DCC_CRS_INCR_CLK90_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_25_csr_dcc_crs_range_clk270_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_25_csr_dcc_crs_range_clk90_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_26_csr_dcc_fine_cntrl_clk0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_26_csr_dcc_fine_cntrl_clk180_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_26_csr_dcc_fine_incr_clk0_attr == SERDES_LANE_ANA_TX_LANE1_REG_26_CSR_DCC_FINE_INCR_CLK0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_26_csr_dcc_fine_incr_clk180_attr == SERDES_LANE_ANA_TX_LANE1_REG_26_CSR_DCC_FINE_INCR_CLK180_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_26_csr_dcc_fine_range_clk0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_26_csr_dcc_fine_range_clk180_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_27_csr_dcc_fine_cntrl_clk270_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_27_csr_dcc_fine_cntrl_clk90_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_27_csr_dcc_fine_incr_clk270_attr == SERDES_LANE_ANA_TX_LANE1_REG_27_CSR_DCC_FINE_INCR_CLK270_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_27_csr_dcc_fine_incr_clk90_attr == SERDES_LANE_ANA_TX_LANE1_REG_27_CSR_DCC_FINE_INCR_CLK90_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_27_csr_dcc_fine_range_clk270_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_27_csr_dcc_fine_range_clk90_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_28_csr_drv_amon0_en_attr == SERDES_LANE_ANA_TX_LANE1_REG_28_CSR_DRV_AMON0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_28_csr_drv_amon0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_28_csr_drv_amon1_en_attr == SERDES_LANE_ANA_TX_LANE1_REG_28_CSR_DRV_AMON1_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_28_csr_drv_amon1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_28_csr_drv_pk_det_vref_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_28_csr_drv_vbn1_par_en_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_29_csr_drv_iq_amp_calib_en_attr == SERDES_LANE_ANA_TX_LANE1_REG_29_CSR_DRV_IQ_AMP_CALIB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_29_csr_drv_iq_amp_cm_cntrl_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_29_csr_drv_iq_amp_en_attr == SERDES_LANE_ANA_TX_LANE1_REG_29_CSR_DRV_IQ_AMP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_29_csr_drv_iq_amp_vref_sel_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_29_csr_drv_lpb_sel_attr == SERDES_LANE_ANA_TX_LANE1_REG_29_CSR_DRV_LPB_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_29_csr_drv_pd_cs_bias2_attr == SERDES_LANE_ANA_TX_LANE1_REG_29_CSR_DRV_PD_CS_BIAS2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_29_csr_drv_replica_dis_attr == SERDES_LANE_ANA_TX_LANE1_REG_29_CSR_DRV_REPLICA_DIS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_29_csr_drv_tx_cmp_clk_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_29_csr_tx_switch_en_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_2_o_spare_a_rw_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_3_o_spare_b_rw_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_5_cmp_addr_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_5_cmp_addr_mask_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_5_cmp_mirror_rd_select_attr == SERDES_LANE_ANA_TX_LANE1_REG_5_CMP_MIRROR_RD_SELECT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_6_csr_txclk_dfx1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_6_csr_txclk_dfx2_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_6_csr_txclk_dfx_dfx1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_6_csr_txclk_dfx_lm1_en_attr == SERDES_LANE_ANA_TX_LANE1_REG_6_CSR_TXCLK_DFX_LM1_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_6_csr_txclk_dfx_lm_lp_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_6_csr_txffe_pll_dpso_sel_attr == SERDES_LANE_ANA_TX_LANE1_REG_6_CSR_TXFFE_PLL_DPSO_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_7_csr_txffe_coeff_0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_7_csr_txffe_coeff_load_attr == SERDES_LANE_ANA_TX_LANE1_REG_7_CSR_TXFFE_COEFF_LOAD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_7_csr_txffe_coeff_m1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_7_csr_txffe_coeff_m2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_7_csr_txffe_coeff_p1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_7_csr_txffe_mode32ui_attr == SERDES_LANE_ANA_TX_LANE1_REG_7_CSR_TXFFE_MODE32UI_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_7_csr_txffe_output_swizzle_attr == SERDES_LANE_ANA_TX_LANE1_REG_7_CSR_TXFFE_OUTPUT_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_8_csr_txffe_coeff_p2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_8_csr_txffe_coeff_p3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_8_csr_txffe_coeff_p4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_8_csr_txffe_coeff_p5_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane1_reg_9_csr_txffe_cmod_attr == 9'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_10_csr_txclk_amon_pulldown_en_attr == SERDES_LANE_ANA_TX_LANE2_REG_10_CSR_TXCLK_AMON_PULLDOWN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_10_csr_txclk_amoni_sel_attr == SERDES_LANE_ANA_TX_LANE2_REG_10_CSR_TXCLK_AMONI_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_10_csr_txclk_amonv_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_10_csr_txclk_clk_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_10_csr_txclk_clk_ph_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_10_csr_txclk_dcc_amon_en_i_attr == SERDES_LANE_ANA_TX_LANE2_REG_10_CSR_TXCLK_DCC_AMON_EN_I_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_10_csr_txclk_dcc_amon_en_q_attr == SERDES_LANE_ANA_TX_LANE2_REG_10_CSR_TXCLK_DCC_AMON_EN_Q_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_10_csr_txclk_dcc_crs_vrefn_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_10_csr_txclk_dcc_crs_vrefp_sel_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_10_csr_txclk_div_ratio_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_10_csr_txclk_ibias_ctrl_dcc_dacn_i_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_10_csr_txclk_ibias_ctrl_dcc_dacn_q_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_10_csr_txclk_ibias_ctrl_dcc_dacp_i_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_10_csr_txclk_ibias_ctrl_dcc_dacp_q_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_11_csr_qec_crs_dll_cntrl_clk270_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_11_csr_qec_crs_dll_cntrl_clk90_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_11_csr_qec_crs_dll_inv_cntrl_clk270_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_11_csr_qec_crs_dll_inv_cntrl_clk90_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_12_csr_qec_crs_cntrl_clk0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_12_csr_qec_crs_cntrl_clk180_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_12_csr_qec_crs_cntrl_clk270_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_12_csr_qec_crs_cntrl_clk90_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_12_csr_qec_crs_inv_cntrl_clk0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_12_csr_qec_crs_inv_cntrl_clk180_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_12_csr_qec_crs_inv_cntrl_clk270_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_12_csr_qec_crs_inv_cntrl_clk90_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_13_csr_qec_fine_cntrl_clk0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_13_csr_qec_fine_cntrl_clk180_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_13_csr_qec_fine_cntrl_clk270_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_13_csr_qec_fine_cntrl_clk90_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_14_csr_ldo_bypass_0p8_en_attr == SERDES_LANE_ANA_TX_LANE2_REG_14_CSR_LDO_BYPASS_0P8_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_14_csr_ldo_bypass_0p9_en_attr == SERDES_LANE_ANA_TX_LANE2_REG_14_CSR_LDO_BYPASS_0P9_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_14_csr_ldo_cmp_out_en_attr == SERDES_LANE_ANA_TX_LANE2_REG_14_CSR_LDO_CMP_OUT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_14_csr_ldo_cmp_out_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_14_csr_ldo_dcmon_en_attr == SERDES_LANE_ANA_TX_LANE2_REG_14_CSR_LDO_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_14_csr_ldo_dcmon_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_14_csr_ldo_enable_attr == SERDES_LANE_ANA_TX_LANE2_REG_14_CSR_LDO_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_14_csr_ldo_leaker_en_attr == SERDES_LANE_ANA_TX_LANE2_REG_14_CSR_LDO_LEAKER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_14_csr_ldo_leaker_tune_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_14_csr_ldo_pwrdn_en_attr == SERDES_LANE_ANA_TX_LANE2_REG_14_CSR_LDO_PWRDN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_15_csr_drv_pd_cs_nmos_attr == 18'd16383
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_15_csr_drv_rterm_enb_attr == SERDES_LANE_ANA_TX_LANE2_REG_15_CSR_DRV_RTERM_ENB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_15_csr_loadgen_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_15_csr_pisoclk_flip_attr == SERDES_LANE_ANA_TX_LANE2_REG_15_CSR_PISOCLK_FLIP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_15_csr_tx_rterm_ctl_attr == 7'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_16_csr_drv_cs_com_enb_attr == SERDES_LANE_ANA_TX_LANE2_REG_16_CSR_DRV_CS_COM_ENB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_16_csr_drv_tx_cmp_rd_select_attr == SERDES_LANE_ANA_TX_LANE2_REG_16_CSR_DRV_TX_CMP_RD_SELECT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_16_csr_drv_tx_mode64b0_32b1_attr == SERDES_LANE_ANA_TX_LANE2_REG_16_CSR_DRV_TX_MODE64B0_32B1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_17_reg2hwa_cfg_avg_eng_start_attr == SERDES_LANE_ANA_TX_LANE2_REG_17_REG2HWA_CFG_AVG_ENG_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_18_reg2hwa_cfg_avg_eng_limit_attr == 32'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_1_csr_lgc_reset_bar_attr == SERDES_LANE_ANA_TX_LANE2_REG_1_CSR_LGC_RESET_BAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_22_csr_lanedig_o_ldo_stable_attr == SERDES_LANE_ANA_TX_LANE2_REG_22_CSR_LANEDIG_O_LDO_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_22_csr_lanedig_o_tx_caldone_attr == SERDES_LANE_ANA_TX_LANE2_REG_22_CSR_LANEDIG_O_TX_CALDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_22_csr_lanedig_o_txclk_ready_attr == SERDES_LANE_ANA_TX_LANE2_REG_22_CSR_LANEDIG_O_TXCLK_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_22_csr_probe0_select_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_22_csr_probe0_txvisa_en_attr == SERDES_LANE_ANA_TX_LANE2_REG_22_CSR_PROBE0_TXVISA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_22_csr_probe1_select_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_22_csr_probe1_txvisa_en_attr == SERDES_LANE_ANA_TX_LANE2_REG_22_CSR_PROBE1_TXVISA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_23_cmp_mirror_reg_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_24_csr_dcc_crs_cntrl_clk0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_24_csr_dcc_crs_cntrl_clk180_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_24_csr_dcc_crs_incr_clk0_attr == SERDES_LANE_ANA_TX_LANE2_REG_24_CSR_DCC_CRS_INCR_CLK0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_24_csr_dcc_crs_incr_clk180_attr == SERDES_LANE_ANA_TX_LANE2_REG_24_CSR_DCC_CRS_INCR_CLK180_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_24_csr_dcc_crs_range_clk0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_24_csr_dcc_crs_range_clk180_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_25_csr_dcc_crs_cntrl_clk270_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_25_csr_dcc_crs_cntrl_clk90_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_25_csr_dcc_crs_incr_clk270_attr == SERDES_LANE_ANA_TX_LANE2_REG_25_CSR_DCC_CRS_INCR_CLK270_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_25_csr_dcc_crs_incr_clk90_attr == SERDES_LANE_ANA_TX_LANE2_REG_25_CSR_DCC_CRS_INCR_CLK90_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_25_csr_dcc_crs_range_clk270_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_25_csr_dcc_crs_range_clk90_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_26_csr_dcc_fine_cntrl_clk0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_26_csr_dcc_fine_cntrl_clk180_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_26_csr_dcc_fine_incr_clk0_attr == SERDES_LANE_ANA_TX_LANE2_REG_26_CSR_DCC_FINE_INCR_CLK0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_26_csr_dcc_fine_incr_clk180_attr == SERDES_LANE_ANA_TX_LANE2_REG_26_CSR_DCC_FINE_INCR_CLK180_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_26_csr_dcc_fine_range_clk0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_26_csr_dcc_fine_range_clk180_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_27_csr_dcc_fine_cntrl_clk270_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_27_csr_dcc_fine_cntrl_clk90_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_27_csr_dcc_fine_incr_clk270_attr == SERDES_LANE_ANA_TX_LANE2_REG_27_CSR_DCC_FINE_INCR_CLK270_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_27_csr_dcc_fine_incr_clk90_attr == SERDES_LANE_ANA_TX_LANE2_REG_27_CSR_DCC_FINE_INCR_CLK90_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_27_csr_dcc_fine_range_clk270_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_27_csr_dcc_fine_range_clk90_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_28_csr_drv_amon0_en_attr == SERDES_LANE_ANA_TX_LANE2_REG_28_CSR_DRV_AMON0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_28_csr_drv_amon0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_28_csr_drv_amon1_en_attr == SERDES_LANE_ANA_TX_LANE2_REG_28_CSR_DRV_AMON1_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_28_csr_drv_amon1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_28_csr_drv_pk_det_vref_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_28_csr_drv_vbn1_par_en_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_29_csr_drv_iq_amp_calib_en_attr == SERDES_LANE_ANA_TX_LANE2_REG_29_CSR_DRV_IQ_AMP_CALIB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_29_csr_drv_iq_amp_cm_cntrl_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_29_csr_drv_iq_amp_en_attr == SERDES_LANE_ANA_TX_LANE2_REG_29_CSR_DRV_IQ_AMP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_29_csr_drv_iq_amp_vref_sel_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_29_csr_drv_lpb_sel_attr == SERDES_LANE_ANA_TX_LANE2_REG_29_CSR_DRV_LPB_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_29_csr_drv_pd_cs_bias2_attr == SERDES_LANE_ANA_TX_LANE2_REG_29_CSR_DRV_PD_CS_BIAS2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_29_csr_drv_replica_dis_attr == SERDES_LANE_ANA_TX_LANE2_REG_29_CSR_DRV_REPLICA_DIS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_29_csr_drv_tx_cmp_clk_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_29_csr_tx_switch_en_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_2_o_spare_a_rw_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_3_o_spare_b_rw_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_5_cmp_addr_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_5_cmp_addr_mask_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_5_cmp_mirror_rd_select_attr == SERDES_LANE_ANA_TX_LANE2_REG_5_CMP_MIRROR_RD_SELECT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_6_csr_txclk_dfx1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_6_csr_txclk_dfx2_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_6_csr_txclk_dfx_dfx1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_6_csr_txclk_dfx_lm1_en_attr == SERDES_LANE_ANA_TX_LANE2_REG_6_CSR_TXCLK_DFX_LM1_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_6_csr_txclk_dfx_lm_lp_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_6_csr_txffe_pll_dpso_sel_attr == SERDES_LANE_ANA_TX_LANE2_REG_6_CSR_TXFFE_PLL_DPSO_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_7_csr_txffe_coeff_0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_7_csr_txffe_coeff_load_attr == SERDES_LANE_ANA_TX_LANE2_REG_7_CSR_TXFFE_COEFF_LOAD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_7_csr_txffe_coeff_m1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_7_csr_txffe_coeff_m2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_7_csr_txffe_coeff_p1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_7_csr_txffe_mode32ui_attr == SERDES_LANE_ANA_TX_LANE2_REG_7_CSR_TXFFE_MODE32UI_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_7_csr_txffe_output_swizzle_attr == SERDES_LANE_ANA_TX_LANE2_REG_7_CSR_TXFFE_OUTPUT_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_8_csr_txffe_coeff_p2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_8_csr_txffe_coeff_p3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_8_csr_txffe_coeff_p4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_8_csr_txffe_coeff_p5_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane2_reg_9_csr_txffe_cmod_attr == 9'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_10_csr_txclk_amon_pulldown_en_attr == SERDES_LANE_ANA_TX_LANE3_REG_10_CSR_TXCLK_AMON_PULLDOWN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_10_csr_txclk_amoni_sel_attr == SERDES_LANE_ANA_TX_LANE3_REG_10_CSR_TXCLK_AMONI_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_10_csr_txclk_amonv_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_10_csr_txclk_clk_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_10_csr_txclk_clk_ph_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_10_csr_txclk_dcc_amon_en_i_attr == SERDES_LANE_ANA_TX_LANE3_REG_10_CSR_TXCLK_DCC_AMON_EN_I_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_10_csr_txclk_dcc_amon_en_q_attr == SERDES_LANE_ANA_TX_LANE3_REG_10_CSR_TXCLK_DCC_AMON_EN_Q_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_10_csr_txclk_dcc_crs_vrefn_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_10_csr_txclk_dcc_crs_vrefp_sel_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_10_csr_txclk_div_ratio_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_10_csr_txclk_ibias_ctrl_dcc_dacn_i_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_10_csr_txclk_ibias_ctrl_dcc_dacn_q_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_10_csr_txclk_ibias_ctrl_dcc_dacp_i_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_10_csr_txclk_ibias_ctrl_dcc_dacp_q_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_11_csr_qec_crs_dll_cntrl_clk270_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_11_csr_qec_crs_dll_cntrl_clk90_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_11_csr_qec_crs_dll_inv_cntrl_clk270_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_11_csr_qec_crs_dll_inv_cntrl_clk90_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_12_csr_qec_crs_cntrl_clk0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_12_csr_qec_crs_cntrl_clk180_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_12_csr_qec_crs_cntrl_clk270_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_12_csr_qec_crs_cntrl_clk90_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_12_csr_qec_crs_inv_cntrl_clk0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_12_csr_qec_crs_inv_cntrl_clk180_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_12_csr_qec_crs_inv_cntrl_clk270_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_12_csr_qec_crs_inv_cntrl_clk90_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_13_csr_qec_fine_cntrl_clk0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_13_csr_qec_fine_cntrl_clk180_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_13_csr_qec_fine_cntrl_clk270_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_13_csr_qec_fine_cntrl_clk90_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_14_csr_ldo_bypass_0p8_en_attr == SERDES_LANE_ANA_TX_LANE3_REG_14_CSR_LDO_BYPASS_0P8_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_14_csr_ldo_bypass_0p9_en_attr == SERDES_LANE_ANA_TX_LANE3_REG_14_CSR_LDO_BYPASS_0P9_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_14_csr_ldo_cmp_out_en_attr == SERDES_LANE_ANA_TX_LANE3_REG_14_CSR_LDO_CMP_OUT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_14_csr_ldo_cmp_out_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_14_csr_ldo_dcmon_en_attr == SERDES_LANE_ANA_TX_LANE3_REG_14_CSR_LDO_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_14_csr_ldo_dcmon_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_14_csr_ldo_enable_attr == SERDES_LANE_ANA_TX_LANE3_REG_14_CSR_LDO_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_14_csr_ldo_leaker_en_attr == SERDES_LANE_ANA_TX_LANE3_REG_14_CSR_LDO_LEAKER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_14_csr_ldo_leaker_tune_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_14_csr_ldo_pwrdn_en_attr == SERDES_LANE_ANA_TX_LANE3_REG_14_CSR_LDO_PWRDN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_15_csr_drv_pd_cs_nmos_attr == 18'd16383
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_15_csr_drv_rterm_enb_attr == SERDES_LANE_ANA_TX_LANE3_REG_15_CSR_DRV_RTERM_ENB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_15_csr_loadgen_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_15_csr_pisoclk_flip_attr == SERDES_LANE_ANA_TX_LANE3_REG_15_CSR_PISOCLK_FLIP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_15_csr_tx_rterm_ctl_attr == 7'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_16_csr_drv_cs_com_enb_attr == SERDES_LANE_ANA_TX_LANE3_REG_16_CSR_DRV_CS_COM_ENB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_16_csr_drv_tx_cmp_rd_select_attr == SERDES_LANE_ANA_TX_LANE3_REG_16_CSR_DRV_TX_CMP_RD_SELECT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_16_csr_drv_tx_mode64b0_32b1_attr == SERDES_LANE_ANA_TX_LANE3_REG_16_CSR_DRV_TX_MODE64B0_32B1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_17_reg2hwa_cfg_avg_eng_start_attr == SERDES_LANE_ANA_TX_LANE3_REG_17_REG2HWA_CFG_AVG_ENG_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_18_reg2hwa_cfg_avg_eng_limit_attr == 32'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_1_csr_lgc_reset_bar_attr == SERDES_LANE_ANA_TX_LANE3_REG_1_CSR_LGC_RESET_BAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_22_csr_lanedig_o_ldo_stable_attr == SERDES_LANE_ANA_TX_LANE3_REG_22_CSR_LANEDIG_O_LDO_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_22_csr_lanedig_o_tx_caldone_attr == SERDES_LANE_ANA_TX_LANE3_REG_22_CSR_LANEDIG_O_TX_CALDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_22_csr_lanedig_o_txclk_ready_attr == SERDES_LANE_ANA_TX_LANE3_REG_22_CSR_LANEDIG_O_TXCLK_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_22_csr_probe0_select_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_22_csr_probe0_txvisa_en_attr == SERDES_LANE_ANA_TX_LANE3_REG_22_CSR_PROBE0_TXVISA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_22_csr_probe1_select_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_22_csr_probe1_txvisa_en_attr == SERDES_LANE_ANA_TX_LANE3_REG_22_CSR_PROBE1_TXVISA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_23_cmp_mirror_reg_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_24_csr_dcc_crs_cntrl_clk0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_24_csr_dcc_crs_cntrl_clk180_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_24_csr_dcc_crs_incr_clk0_attr == SERDES_LANE_ANA_TX_LANE3_REG_24_CSR_DCC_CRS_INCR_CLK0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_24_csr_dcc_crs_incr_clk180_attr == SERDES_LANE_ANA_TX_LANE3_REG_24_CSR_DCC_CRS_INCR_CLK180_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_24_csr_dcc_crs_range_clk0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_24_csr_dcc_crs_range_clk180_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_25_csr_dcc_crs_cntrl_clk270_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_25_csr_dcc_crs_cntrl_clk90_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_25_csr_dcc_crs_incr_clk270_attr == SERDES_LANE_ANA_TX_LANE3_REG_25_CSR_DCC_CRS_INCR_CLK270_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_25_csr_dcc_crs_incr_clk90_attr == SERDES_LANE_ANA_TX_LANE3_REG_25_CSR_DCC_CRS_INCR_CLK90_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_25_csr_dcc_crs_range_clk270_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_25_csr_dcc_crs_range_clk90_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_26_csr_dcc_fine_cntrl_clk0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_26_csr_dcc_fine_cntrl_clk180_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_26_csr_dcc_fine_incr_clk0_attr == SERDES_LANE_ANA_TX_LANE3_REG_26_CSR_DCC_FINE_INCR_CLK0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_26_csr_dcc_fine_incr_clk180_attr == SERDES_LANE_ANA_TX_LANE3_REG_26_CSR_DCC_FINE_INCR_CLK180_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_26_csr_dcc_fine_range_clk0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_26_csr_dcc_fine_range_clk180_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_27_csr_dcc_fine_cntrl_clk270_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_27_csr_dcc_fine_cntrl_clk90_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_27_csr_dcc_fine_incr_clk270_attr == SERDES_LANE_ANA_TX_LANE3_REG_27_CSR_DCC_FINE_INCR_CLK270_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_27_csr_dcc_fine_incr_clk90_attr == SERDES_LANE_ANA_TX_LANE3_REG_27_CSR_DCC_FINE_INCR_CLK90_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_27_csr_dcc_fine_range_clk270_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_27_csr_dcc_fine_range_clk90_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_28_csr_drv_amon0_en_attr == SERDES_LANE_ANA_TX_LANE3_REG_28_CSR_DRV_AMON0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_28_csr_drv_amon0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_28_csr_drv_amon1_en_attr == SERDES_LANE_ANA_TX_LANE3_REG_28_CSR_DRV_AMON1_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_28_csr_drv_amon1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_28_csr_drv_pk_det_vref_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_28_csr_drv_vbn1_par_en_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_29_csr_drv_iq_amp_calib_en_attr == SERDES_LANE_ANA_TX_LANE3_REG_29_CSR_DRV_IQ_AMP_CALIB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_29_csr_drv_iq_amp_cm_cntrl_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_29_csr_drv_iq_amp_en_attr == SERDES_LANE_ANA_TX_LANE3_REG_29_CSR_DRV_IQ_AMP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_29_csr_drv_iq_amp_vref_sel_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_29_csr_drv_lpb_sel_attr == SERDES_LANE_ANA_TX_LANE3_REG_29_CSR_DRV_LPB_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_29_csr_drv_pd_cs_bias2_attr == SERDES_LANE_ANA_TX_LANE3_REG_29_CSR_DRV_PD_CS_BIAS2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_29_csr_drv_replica_dis_attr == SERDES_LANE_ANA_TX_LANE3_REG_29_CSR_DRV_REPLICA_DIS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_29_csr_drv_tx_cmp_clk_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_29_csr_tx_switch_en_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_2_o_spare_a_rw_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_3_o_spare_b_rw_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_5_cmp_addr_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_5_cmp_addr_mask_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_5_cmp_mirror_rd_select_attr == SERDES_LANE_ANA_TX_LANE3_REG_5_CMP_MIRROR_RD_SELECT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_6_csr_txclk_dfx1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_6_csr_txclk_dfx2_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_6_csr_txclk_dfx_dfx1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_6_csr_txclk_dfx_lm1_en_attr == SERDES_LANE_ANA_TX_LANE3_REG_6_CSR_TXCLK_DFX_LM1_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_6_csr_txclk_dfx_lm_lp_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_6_csr_txffe_pll_dpso_sel_attr == SERDES_LANE_ANA_TX_LANE3_REG_6_CSR_TXFFE_PLL_DPSO_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_7_csr_txffe_coeff_0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_7_csr_txffe_coeff_load_attr == SERDES_LANE_ANA_TX_LANE3_REG_7_CSR_TXFFE_COEFF_LOAD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_7_csr_txffe_coeff_m1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_7_csr_txffe_coeff_m2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_7_csr_txffe_coeff_p1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_7_csr_txffe_mode32ui_attr == SERDES_LANE_ANA_TX_LANE3_REG_7_CSR_TXFFE_MODE32UI_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_7_csr_txffe_output_swizzle_attr == SERDES_LANE_ANA_TX_LANE3_REG_7_CSR_TXFFE_OUTPUT_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_8_csr_txffe_coeff_p2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_8_csr_txffe_coeff_p3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_8_csr_txffe_coeff_p4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_8_csr_txffe_coeff_p5_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_ana_tx_lane3_reg_9_csr_txffe_cmod_attr == 9'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_1_car_dft_rx_clken_attr == SERDES_LANE_CAR_LANE0_REG_1_CAR_DFT_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_1_car_dft_tx_clken_attr == SERDES_LANE_CAR_LANE0_REG_1_CAR_DFT_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_1_car_dsp_64ui_clken_attr == SERDES_LANE_CAR_LANE0_REG_1_CAR_DSP_64UI_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_1_car_dsp_64ui_dfe_byps_clken_attr == SERDES_LANE_CAR_LANE0_REG_1_CAR_DSP_64UI_DFE_BYPS_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_1_car_dsp_64ui_dfe_clken_attr == SERDES_LANE_CAR_LANE0_REG_1_CAR_DSP_64UI_DFE_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_1_car_dsp_64ui_ffe_clken_attr == SERDES_LANE_CAR_LANE0_REG_1_CAR_DSP_64UI_FFE_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_1_car_dsp_64ui_first_samp_clken_attr == SERDES_LANE_CAR_LANE0_REG_1_CAR_DSP_64UI_FIRST_SAMP_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_1_car_ppm_all_tech_clken_attr == SERDES_LANE_CAR_LANE0_REG_1_CAR_PPM_ALL_TECH_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_1_car_ref_ppm_clken_attr == SERDES_LANE_CAR_LANE0_REG_1_CAR_REF_PPM_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_1_clkmux_dig_clk_en_attr == SERDES_LANE_CAR_LANE0_REG_1_CLKMUX_DIG_CLK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_1_dsp_64ui_cdr_pfd_clken_attr == SERDES_LANE_CAR_LANE0_REG_1_DSP_64UI_CDR_PFD_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_1_dsp_cdr_64ui_clken_attr == SERDES_LANE_CAR_LANE0_REG_1_DSP_CDR_64UI_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_1_dsp_gain_per_sar_clken_attr == SERDES_LANE_CAR_LANE0_REG_1_DSP_GAIN_PER_SAR_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_1_dsp_lms_eng_clken_attr == SERDES_LANE_CAR_LANE0_REG_1_DSP_LMS_ENG_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_1_dsp_ops_gps_clken_attr == SERDES_LANE_CAR_LANE0_REG_1_DSP_OPS_GPS_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_1_dsp_sec_lms_eng_clken_attr == SERDES_LANE_CAR_LANE0_REG_1_DSP_SEC_LMS_ENG_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_1_dsp_snr_meter_clken_attr == SERDES_LANE_CAR_LANE0_REG_1_DSP_SNR_METER_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_1_dsp_vga_adapt_clken_attr == SERDES_LANE_CAR_LANE0_REG_1_DSP_VGA_ADAPT_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_1_pcs_srds_tx_clken_attr == SERDES_LANE_CAR_LANE0_REG_1_PCS_SRDS_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_1_rx_clk_fifo_clken_attr == SERDES_LANE_CAR_LANE0_REG_1_RX_CLK_FIFO_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_1_tx_64ui_cdr_pfd_clken_attr == SERDES_LANE_CAR_LANE0_REG_1_TX_64UI_CDR_PFD_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_2_car_ana_datapth_swrstb_attr == SERDES_LANE_CAR_LANE0_REG_2_CAR_ANA_DATAPTH_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_2_car_brk_lane_swrstb_attr == SERDES_LANE_CAR_LANE0_REG_2_CAR_BRK_LANE_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_2_car_dft_rx_swrstb_attr == SERDES_LANE_CAR_LANE0_REG_2_CAR_DFT_RX_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_2_car_dft_tx_swrstb_attr == SERDES_LANE_CAR_LANE0_REG_2_CAR_DFT_TX_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_2_car_dsp_64ui_cdr_pfd_swrstb_attr == SERDES_LANE_CAR_LANE0_REG_2_CAR_DSP_64UI_CDR_PFD_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_2_car_dsp_64ui_dfe_swrstb_attr == SERDES_LANE_CAR_LANE0_REG_2_CAR_DSP_64UI_DFE_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_2_car_dsp_64ui_ffe_swrstb_attr == SERDES_LANE_CAR_LANE0_REG_2_CAR_DSP_64UI_FFE_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_2_car_dsp_64ui_first_samp_swrstb_attr == SERDES_LANE_CAR_LANE0_REG_2_CAR_DSP_64UI_FIRST_SAMP_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_2_car_dsp_64ui_swrstb_attr == SERDES_LANE_CAR_LANE0_REG_2_CAR_DSP_64UI_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_2_car_ppm_all_tech_swrstb_attr == SERDES_LANE_CAR_LANE0_REG_2_CAR_PPM_ALL_TECH_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_2_car_ref_ppm_swrstb_attr == SERDES_LANE_CAR_LANE0_REG_2_CAR_REF_PPM_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_2_car_tx_64ui_cdr_pfd_swrstb_attr == SERDES_LANE_CAR_LANE0_REG_2_CAR_TX_64UI_CDR_PFD_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_2_car_tx_64ui_swrstb_attr == SERDES_LANE_CAR_LANE0_REG_2_CAR_TX_64UI_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_2_dsp_cdr_64ui_swrstb_attr == SERDES_LANE_CAR_LANE0_REG_2_DSP_CDR_64UI_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_2_lane_swrstb_attr == SERDES_LANE_CAR_LANE0_REG_2_LANE_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_2_orx_srds_swrstb_attr == SERDES_LANE_CAR_LANE0_REG_2_ORX_SRDS_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_2_otx_srds_swrstb_attr == SERDES_LANE_CAR_LANE0_REG_2_OTX_SRDS_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_2_pcs_srds_tx_swrstb_attr == SERDES_LANE_CAR_LANE0_REG_2_PCS_SRDS_TX_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_3_apb_dsp_clk_sel_attr == SERDES_LANE_CAR_LANE0_REG_3_APB_DSP_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_3_apb_rx_divn_en_attr == SERDES_LANE_CAR_LANE0_REG_3_APB_RX_DIVN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_3_apb_rx_divn_val_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_3_cdr_pfd_rx_divn_en_attr == SERDES_LANE_CAR_LANE0_REG_3_CDR_PFD_RX_DIVN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_3_cdr_pfd_rx_divn_val_attr == 8'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_3_cdr_pfd_tx_divn_en_attr == SERDES_LANE_CAR_LANE0_REG_3_CDR_PFD_TX_DIVN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_3_cdr_pfd_tx_divn_val_attr == 8'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_3_ppm_clk_sel_attr == SERDES_LANE_CAR_LANE0_REG_3_PPM_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_4_cdr_as_pll_ref_divn_en_attr == SERDES_LANE_CAR_LANE0_REG_4_CDR_AS_PLL_REF_DIVN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_4_cdr_as_pll_ref_divn_val_attr == 8'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_6_obrk_rx_direct_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_7_obrk_rxsrds_rdy_attr == SERDES_LANE_CAR_LANE0_REG_7_OBRK_RXSRDS_RDY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_8_car_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_8_car_sec_acc_ctrl_broadcast_mode_attr == SERDES_LANE_CAR_LANE0_REG_8_CAR_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_8_car_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_8_car_sec_acc_ctrl_field_mask_write_en_attr == SERDES_LANE_CAR_LANE0_REG_8_CAR_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_8_car_sec_acc_ctrl_load_preset_attr == SERDES_LANE_CAR_LANE0_REG_8_CAR_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_8_car_sec_acc_ctrl_man_clear_on_read_attr == SERDES_LANE_CAR_LANE0_REG_8_CAR_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_8_car_sec_acc_ctrl_man_self_clear_attr == SERDES_LANE_CAR_LANE0_REG_8_CAR_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_8_car_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_8_car_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_8_car_sec_acc_ctrl_soft_reset_n_attr == SERDES_LANE_CAR_LANE0_REG_8_CAR_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_8_car_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_9_car_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane0_reg_9_car_reg2probe_en_attr == SERDES_LANE_CAR_LANE0_REG_9_CAR_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_1_car_dft_rx_clken_attr == SERDES_LANE_CAR_LANE1_REG_1_CAR_DFT_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_1_car_dft_tx_clken_attr == SERDES_LANE_CAR_LANE1_REG_1_CAR_DFT_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_1_car_dsp_64ui_clken_attr == SERDES_LANE_CAR_LANE1_REG_1_CAR_DSP_64UI_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_1_car_dsp_64ui_dfe_byps_clken_attr == SERDES_LANE_CAR_LANE1_REG_1_CAR_DSP_64UI_DFE_BYPS_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_1_car_dsp_64ui_dfe_clken_attr == SERDES_LANE_CAR_LANE1_REG_1_CAR_DSP_64UI_DFE_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_1_car_dsp_64ui_ffe_clken_attr == SERDES_LANE_CAR_LANE1_REG_1_CAR_DSP_64UI_FFE_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_1_car_dsp_64ui_first_samp_clken_attr == SERDES_LANE_CAR_LANE1_REG_1_CAR_DSP_64UI_FIRST_SAMP_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_1_car_ppm_all_tech_clken_attr == SERDES_LANE_CAR_LANE1_REG_1_CAR_PPM_ALL_TECH_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_1_car_ref_ppm_clken_attr == SERDES_LANE_CAR_LANE1_REG_1_CAR_REF_PPM_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_1_clkmux_dig_clk_en_attr == SERDES_LANE_CAR_LANE1_REG_1_CLKMUX_DIG_CLK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_1_dsp_64ui_cdr_pfd_clken_attr == SERDES_LANE_CAR_LANE1_REG_1_DSP_64UI_CDR_PFD_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_1_dsp_cdr_64ui_clken_attr == SERDES_LANE_CAR_LANE1_REG_1_DSP_CDR_64UI_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_1_dsp_gain_per_sar_clken_attr == SERDES_LANE_CAR_LANE1_REG_1_DSP_GAIN_PER_SAR_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_1_dsp_lms_eng_clken_attr == SERDES_LANE_CAR_LANE1_REG_1_DSP_LMS_ENG_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_1_dsp_ops_gps_clken_attr == SERDES_LANE_CAR_LANE1_REG_1_DSP_OPS_GPS_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_1_dsp_sec_lms_eng_clken_attr == SERDES_LANE_CAR_LANE1_REG_1_DSP_SEC_LMS_ENG_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_1_dsp_snr_meter_clken_attr == SERDES_LANE_CAR_LANE1_REG_1_DSP_SNR_METER_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_1_dsp_vga_adapt_clken_attr == SERDES_LANE_CAR_LANE1_REG_1_DSP_VGA_ADAPT_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_1_pcs_srds_tx_clken_attr == SERDES_LANE_CAR_LANE1_REG_1_PCS_SRDS_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_1_rx_clk_fifo_clken_attr == SERDES_LANE_CAR_LANE1_REG_1_RX_CLK_FIFO_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_1_tx_64ui_cdr_pfd_clken_attr == SERDES_LANE_CAR_LANE1_REG_1_TX_64UI_CDR_PFD_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_2_car_ana_datapth_swrstb_attr == SERDES_LANE_CAR_LANE1_REG_2_CAR_ANA_DATAPTH_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_2_car_brk_lane_swrstb_attr == SERDES_LANE_CAR_LANE1_REG_2_CAR_BRK_LANE_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_2_car_dft_rx_swrstb_attr == SERDES_LANE_CAR_LANE1_REG_2_CAR_DFT_RX_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_2_car_dft_tx_swrstb_attr == SERDES_LANE_CAR_LANE1_REG_2_CAR_DFT_TX_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_2_car_dsp_64ui_cdr_pfd_swrstb_attr == SERDES_LANE_CAR_LANE1_REG_2_CAR_DSP_64UI_CDR_PFD_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_2_car_dsp_64ui_dfe_swrstb_attr == SERDES_LANE_CAR_LANE1_REG_2_CAR_DSP_64UI_DFE_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_2_car_dsp_64ui_ffe_swrstb_attr == SERDES_LANE_CAR_LANE1_REG_2_CAR_DSP_64UI_FFE_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_2_car_dsp_64ui_first_samp_swrstb_attr == SERDES_LANE_CAR_LANE1_REG_2_CAR_DSP_64UI_FIRST_SAMP_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_2_car_dsp_64ui_swrstb_attr == SERDES_LANE_CAR_LANE1_REG_2_CAR_DSP_64UI_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_2_car_ppm_all_tech_swrstb_attr == SERDES_LANE_CAR_LANE1_REG_2_CAR_PPM_ALL_TECH_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_2_car_ref_ppm_swrstb_attr == SERDES_LANE_CAR_LANE1_REG_2_CAR_REF_PPM_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_2_car_tx_64ui_cdr_pfd_swrstb_attr == SERDES_LANE_CAR_LANE1_REG_2_CAR_TX_64UI_CDR_PFD_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_2_car_tx_64ui_swrstb_attr == SERDES_LANE_CAR_LANE1_REG_2_CAR_TX_64UI_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_2_dsp_cdr_64ui_swrstb_attr == SERDES_LANE_CAR_LANE1_REG_2_DSP_CDR_64UI_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_2_lane_swrstb_attr == SERDES_LANE_CAR_LANE1_REG_2_LANE_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_2_orx_srds_swrstb_attr == SERDES_LANE_CAR_LANE1_REG_2_ORX_SRDS_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_2_otx_srds_swrstb_attr == SERDES_LANE_CAR_LANE1_REG_2_OTX_SRDS_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_2_pcs_srds_tx_swrstb_attr == SERDES_LANE_CAR_LANE1_REG_2_PCS_SRDS_TX_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_3_apb_dsp_clk_sel_attr == SERDES_LANE_CAR_LANE1_REG_3_APB_DSP_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_3_apb_rx_divn_en_attr == SERDES_LANE_CAR_LANE1_REG_3_APB_RX_DIVN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_3_apb_rx_divn_val_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_3_cdr_pfd_rx_divn_en_attr == SERDES_LANE_CAR_LANE1_REG_3_CDR_PFD_RX_DIVN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_3_cdr_pfd_rx_divn_val_attr == 8'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_3_cdr_pfd_tx_divn_en_attr == SERDES_LANE_CAR_LANE1_REG_3_CDR_PFD_TX_DIVN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_3_cdr_pfd_tx_divn_val_attr == 8'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_3_ppm_clk_sel_attr == SERDES_LANE_CAR_LANE1_REG_3_PPM_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_4_cdr_as_pll_ref_divn_en_attr == SERDES_LANE_CAR_LANE1_REG_4_CDR_AS_PLL_REF_DIVN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_4_cdr_as_pll_ref_divn_val_attr == 8'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_6_obrk_rx_direct_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_7_obrk_rxsrds_rdy_attr == SERDES_LANE_CAR_LANE1_REG_7_OBRK_RXSRDS_RDY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_8_car_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_8_car_sec_acc_ctrl_broadcast_mode_attr == SERDES_LANE_CAR_LANE1_REG_8_CAR_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_8_car_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_8_car_sec_acc_ctrl_field_mask_write_en_attr == SERDES_LANE_CAR_LANE1_REG_8_CAR_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_8_car_sec_acc_ctrl_load_preset_attr == SERDES_LANE_CAR_LANE1_REG_8_CAR_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_8_car_sec_acc_ctrl_man_clear_on_read_attr == SERDES_LANE_CAR_LANE1_REG_8_CAR_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_8_car_sec_acc_ctrl_man_self_clear_attr == SERDES_LANE_CAR_LANE1_REG_8_CAR_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_8_car_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_8_car_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_8_car_sec_acc_ctrl_soft_reset_n_attr == SERDES_LANE_CAR_LANE1_REG_8_CAR_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_8_car_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_9_car_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane1_reg_9_car_reg2probe_en_attr == SERDES_LANE_CAR_LANE1_REG_9_CAR_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_1_car_dft_rx_clken_attr == SERDES_LANE_CAR_LANE2_REG_1_CAR_DFT_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_1_car_dft_tx_clken_attr == SERDES_LANE_CAR_LANE2_REG_1_CAR_DFT_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_1_car_dsp_64ui_clken_attr == SERDES_LANE_CAR_LANE2_REG_1_CAR_DSP_64UI_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_1_car_dsp_64ui_dfe_byps_clken_attr == SERDES_LANE_CAR_LANE2_REG_1_CAR_DSP_64UI_DFE_BYPS_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_1_car_dsp_64ui_dfe_clken_attr == SERDES_LANE_CAR_LANE2_REG_1_CAR_DSP_64UI_DFE_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_1_car_dsp_64ui_ffe_clken_attr == SERDES_LANE_CAR_LANE2_REG_1_CAR_DSP_64UI_FFE_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_1_car_dsp_64ui_first_samp_clken_attr == SERDES_LANE_CAR_LANE2_REG_1_CAR_DSP_64UI_FIRST_SAMP_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_1_car_ppm_all_tech_clken_attr == SERDES_LANE_CAR_LANE2_REG_1_CAR_PPM_ALL_TECH_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_1_car_ref_ppm_clken_attr == SERDES_LANE_CAR_LANE2_REG_1_CAR_REF_PPM_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_1_clkmux_dig_clk_en_attr == SERDES_LANE_CAR_LANE2_REG_1_CLKMUX_DIG_CLK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_1_dsp_64ui_cdr_pfd_clken_attr == SERDES_LANE_CAR_LANE2_REG_1_DSP_64UI_CDR_PFD_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_1_dsp_cdr_64ui_clken_attr == SERDES_LANE_CAR_LANE2_REG_1_DSP_CDR_64UI_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_1_dsp_gain_per_sar_clken_attr == SERDES_LANE_CAR_LANE2_REG_1_DSP_GAIN_PER_SAR_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_1_dsp_lms_eng_clken_attr == SERDES_LANE_CAR_LANE2_REG_1_DSP_LMS_ENG_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_1_dsp_ops_gps_clken_attr == SERDES_LANE_CAR_LANE2_REG_1_DSP_OPS_GPS_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_1_dsp_sec_lms_eng_clken_attr == SERDES_LANE_CAR_LANE2_REG_1_DSP_SEC_LMS_ENG_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_1_dsp_snr_meter_clken_attr == SERDES_LANE_CAR_LANE2_REG_1_DSP_SNR_METER_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_1_dsp_vga_adapt_clken_attr == SERDES_LANE_CAR_LANE2_REG_1_DSP_VGA_ADAPT_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_1_pcs_srds_tx_clken_attr == SERDES_LANE_CAR_LANE2_REG_1_PCS_SRDS_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_1_rx_clk_fifo_clken_attr == SERDES_LANE_CAR_LANE2_REG_1_RX_CLK_FIFO_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_1_tx_64ui_cdr_pfd_clken_attr == SERDES_LANE_CAR_LANE2_REG_1_TX_64UI_CDR_PFD_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_2_car_ana_datapth_swrstb_attr == SERDES_LANE_CAR_LANE2_REG_2_CAR_ANA_DATAPTH_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_2_car_brk_lane_swrstb_attr == SERDES_LANE_CAR_LANE2_REG_2_CAR_BRK_LANE_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_2_car_dft_rx_swrstb_attr == SERDES_LANE_CAR_LANE2_REG_2_CAR_DFT_RX_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_2_car_dft_tx_swrstb_attr == SERDES_LANE_CAR_LANE2_REG_2_CAR_DFT_TX_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_2_car_dsp_64ui_cdr_pfd_swrstb_attr == SERDES_LANE_CAR_LANE2_REG_2_CAR_DSP_64UI_CDR_PFD_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_2_car_dsp_64ui_dfe_swrstb_attr == SERDES_LANE_CAR_LANE2_REG_2_CAR_DSP_64UI_DFE_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_2_car_dsp_64ui_ffe_swrstb_attr == SERDES_LANE_CAR_LANE2_REG_2_CAR_DSP_64UI_FFE_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_2_car_dsp_64ui_first_samp_swrstb_attr == SERDES_LANE_CAR_LANE2_REG_2_CAR_DSP_64UI_FIRST_SAMP_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_2_car_dsp_64ui_swrstb_attr == SERDES_LANE_CAR_LANE2_REG_2_CAR_DSP_64UI_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_2_car_ppm_all_tech_swrstb_attr == SERDES_LANE_CAR_LANE2_REG_2_CAR_PPM_ALL_TECH_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_2_car_ref_ppm_swrstb_attr == SERDES_LANE_CAR_LANE2_REG_2_CAR_REF_PPM_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_2_car_tx_64ui_cdr_pfd_swrstb_attr == SERDES_LANE_CAR_LANE2_REG_2_CAR_TX_64UI_CDR_PFD_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_2_car_tx_64ui_swrstb_attr == SERDES_LANE_CAR_LANE2_REG_2_CAR_TX_64UI_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_2_dsp_cdr_64ui_swrstb_attr == SERDES_LANE_CAR_LANE2_REG_2_DSP_CDR_64UI_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_2_lane_swrstb_attr == SERDES_LANE_CAR_LANE2_REG_2_LANE_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_2_orx_srds_swrstb_attr == SERDES_LANE_CAR_LANE2_REG_2_ORX_SRDS_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_2_otx_srds_swrstb_attr == SERDES_LANE_CAR_LANE2_REG_2_OTX_SRDS_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_2_pcs_srds_tx_swrstb_attr == SERDES_LANE_CAR_LANE2_REG_2_PCS_SRDS_TX_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_3_apb_dsp_clk_sel_attr == SERDES_LANE_CAR_LANE2_REG_3_APB_DSP_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_3_apb_rx_divn_en_attr == SERDES_LANE_CAR_LANE2_REG_3_APB_RX_DIVN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_3_apb_rx_divn_val_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_3_cdr_pfd_rx_divn_en_attr == SERDES_LANE_CAR_LANE2_REG_3_CDR_PFD_RX_DIVN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_3_cdr_pfd_rx_divn_val_attr == 8'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_3_cdr_pfd_tx_divn_en_attr == SERDES_LANE_CAR_LANE2_REG_3_CDR_PFD_TX_DIVN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_3_cdr_pfd_tx_divn_val_attr == 8'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_3_ppm_clk_sel_attr == SERDES_LANE_CAR_LANE2_REG_3_PPM_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_4_cdr_as_pll_ref_divn_en_attr == SERDES_LANE_CAR_LANE2_REG_4_CDR_AS_PLL_REF_DIVN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_4_cdr_as_pll_ref_divn_val_attr == 8'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_6_obrk_rx_direct_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_7_obrk_rxsrds_rdy_attr == SERDES_LANE_CAR_LANE2_REG_7_OBRK_RXSRDS_RDY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_8_car_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_8_car_sec_acc_ctrl_broadcast_mode_attr == SERDES_LANE_CAR_LANE2_REG_8_CAR_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_8_car_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_8_car_sec_acc_ctrl_field_mask_write_en_attr == SERDES_LANE_CAR_LANE2_REG_8_CAR_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_8_car_sec_acc_ctrl_load_preset_attr == SERDES_LANE_CAR_LANE2_REG_8_CAR_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_8_car_sec_acc_ctrl_man_clear_on_read_attr == SERDES_LANE_CAR_LANE2_REG_8_CAR_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_8_car_sec_acc_ctrl_man_self_clear_attr == SERDES_LANE_CAR_LANE2_REG_8_CAR_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_8_car_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_8_car_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_8_car_sec_acc_ctrl_soft_reset_n_attr == SERDES_LANE_CAR_LANE2_REG_8_CAR_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_8_car_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_9_car_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane2_reg_9_car_reg2probe_en_attr == SERDES_LANE_CAR_LANE2_REG_9_CAR_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_1_car_dft_rx_clken_attr == SERDES_LANE_CAR_LANE3_REG_1_CAR_DFT_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_1_car_dft_tx_clken_attr == SERDES_LANE_CAR_LANE3_REG_1_CAR_DFT_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_1_car_dsp_64ui_clken_attr == SERDES_LANE_CAR_LANE3_REG_1_CAR_DSP_64UI_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_1_car_dsp_64ui_dfe_byps_clken_attr == SERDES_LANE_CAR_LANE3_REG_1_CAR_DSP_64UI_DFE_BYPS_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_1_car_dsp_64ui_dfe_clken_attr == SERDES_LANE_CAR_LANE3_REG_1_CAR_DSP_64UI_DFE_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_1_car_dsp_64ui_ffe_clken_attr == SERDES_LANE_CAR_LANE3_REG_1_CAR_DSP_64UI_FFE_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_1_car_dsp_64ui_first_samp_clken_attr == SERDES_LANE_CAR_LANE3_REG_1_CAR_DSP_64UI_FIRST_SAMP_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_1_car_ppm_all_tech_clken_attr == SERDES_LANE_CAR_LANE3_REG_1_CAR_PPM_ALL_TECH_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_1_car_ref_ppm_clken_attr == SERDES_LANE_CAR_LANE3_REG_1_CAR_REF_PPM_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_1_clkmux_dig_clk_en_attr == SERDES_LANE_CAR_LANE3_REG_1_CLKMUX_DIG_CLK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_1_dsp_64ui_cdr_pfd_clken_attr == SERDES_LANE_CAR_LANE3_REG_1_DSP_64UI_CDR_PFD_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_1_dsp_cdr_64ui_clken_attr == SERDES_LANE_CAR_LANE3_REG_1_DSP_CDR_64UI_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_1_dsp_gain_per_sar_clken_attr == SERDES_LANE_CAR_LANE3_REG_1_DSP_GAIN_PER_SAR_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_1_dsp_lms_eng_clken_attr == SERDES_LANE_CAR_LANE3_REG_1_DSP_LMS_ENG_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_1_dsp_ops_gps_clken_attr == SERDES_LANE_CAR_LANE3_REG_1_DSP_OPS_GPS_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_1_dsp_sec_lms_eng_clken_attr == SERDES_LANE_CAR_LANE3_REG_1_DSP_SEC_LMS_ENG_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_1_dsp_snr_meter_clken_attr == SERDES_LANE_CAR_LANE3_REG_1_DSP_SNR_METER_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_1_dsp_vga_adapt_clken_attr == SERDES_LANE_CAR_LANE3_REG_1_DSP_VGA_ADAPT_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_1_pcs_srds_tx_clken_attr == SERDES_LANE_CAR_LANE3_REG_1_PCS_SRDS_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_1_rx_clk_fifo_clken_attr == SERDES_LANE_CAR_LANE3_REG_1_RX_CLK_FIFO_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_1_tx_64ui_cdr_pfd_clken_attr == SERDES_LANE_CAR_LANE3_REG_1_TX_64UI_CDR_PFD_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_2_car_ana_datapth_swrstb_attr == SERDES_LANE_CAR_LANE3_REG_2_CAR_ANA_DATAPTH_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_2_car_brk_lane_swrstb_attr == SERDES_LANE_CAR_LANE3_REG_2_CAR_BRK_LANE_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_2_car_dft_rx_swrstb_attr == SERDES_LANE_CAR_LANE3_REG_2_CAR_DFT_RX_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_2_car_dft_tx_swrstb_attr == SERDES_LANE_CAR_LANE3_REG_2_CAR_DFT_TX_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_2_car_dsp_64ui_cdr_pfd_swrstb_attr == SERDES_LANE_CAR_LANE3_REG_2_CAR_DSP_64UI_CDR_PFD_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_2_car_dsp_64ui_dfe_swrstb_attr == SERDES_LANE_CAR_LANE3_REG_2_CAR_DSP_64UI_DFE_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_2_car_dsp_64ui_ffe_swrstb_attr == SERDES_LANE_CAR_LANE3_REG_2_CAR_DSP_64UI_FFE_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_2_car_dsp_64ui_first_samp_swrstb_attr == SERDES_LANE_CAR_LANE3_REG_2_CAR_DSP_64UI_FIRST_SAMP_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_2_car_dsp_64ui_swrstb_attr == SERDES_LANE_CAR_LANE3_REG_2_CAR_DSP_64UI_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_2_car_ppm_all_tech_swrstb_attr == SERDES_LANE_CAR_LANE3_REG_2_CAR_PPM_ALL_TECH_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_2_car_ref_ppm_swrstb_attr == SERDES_LANE_CAR_LANE3_REG_2_CAR_REF_PPM_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_2_car_tx_64ui_cdr_pfd_swrstb_attr == SERDES_LANE_CAR_LANE3_REG_2_CAR_TX_64UI_CDR_PFD_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_2_car_tx_64ui_swrstb_attr == SERDES_LANE_CAR_LANE3_REG_2_CAR_TX_64UI_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_2_dsp_cdr_64ui_swrstb_attr == SERDES_LANE_CAR_LANE3_REG_2_DSP_CDR_64UI_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_2_lane_swrstb_attr == SERDES_LANE_CAR_LANE3_REG_2_LANE_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_2_orx_srds_swrstb_attr == SERDES_LANE_CAR_LANE3_REG_2_ORX_SRDS_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_2_otx_srds_swrstb_attr == SERDES_LANE_CAR_LANE3_REG_2_OTX_SRDS_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_2_pcs_srds_tx_swrstb_attr == SERDES_LANE_CAR_LANE3_REG_2_PCS_SRDS_TX_SWRSTB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_3_apb_dsp_clk_sel_attr == SERDES_LANE_CAR_LANE3_REG_3_APB_DSP_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_3_apb_rx_divn_en_attr == SERDES_LANE_CAR_LANE3_REG_3_APB_RX_DIVN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_3_apb_rx_divn_val_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_3_cdr_pfd_rx_divn_en_attr == SERDES_LANE_CAR_LANE3_REG_3_CDR_PFD_RX_DIVN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_3_cdr_pfd_rx_divn_val_attr == 8'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_3_cdr_pfd_tx_divn_en_attr == SERDES_LANE_CAR_LANE3_REG_3_CDR_PFD_TX_DIVN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_3_cdr_pfd_tx_divn_val_attr == 8'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_3_ppm_clk_sel_attr == SERDES_LANE_CAR_LANE3_REG_3_PPM_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_4_cdr_as_pll_ref_divn_en_attr == SERDES_LANE_CAR_LANE3_REG_4_CDR_AS_PLL_REF_DIVN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_4_cdr_as_pll_ref_divn_val_attr == 8'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_6_obrk_rx_direct_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_7_obrk_rxsrds_rdy_attr == SERDES_LANE_CAR_LANE3_REG_7_OBRK_RXSRDS_RDY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_8_car_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_8_car_sec_acc_ctrl_broadcast_mode_attr == SERDES_LANE_CAR_LANE3_REG_8_CAR_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_8_car_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_8_car_sec_acc_ctrl_field_mask_write_en_attr == SERDES_LANE_CAR_LANE3_REG_8_CAR_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_8_car_sec_acc_ctrl_load_preset_attr == SERDES_LANE_CAR_LANE3_REG_8_CAR_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_8_car_sec_acc_ctrl_man_clear_on_read_attr == SERDES_LANE_CAR_LANE3_REG_8_CAR_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_8_car_sec_acc_ctrl_man_self_clear_attr == SERDES_LANE_CAR_LANE3_REG_8_CAR_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_8_car_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_8_car_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_8_car_sec_acc_ctrl_soft_reset_n_attr == SERDES_LANE_CAR_LANE3_REG_8_CAR_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_8_car_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_9_car_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_car_lane3_reg_9_car_reg2probe_en_attr == SERDES_LANE_CAR_LANE3_REG_9_CAR_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_10_cdr_prop_thr_load_attr == SERDES_LANE_CDR_NEW_LANE0_REG_10_CDR_PROP_THR_LOAD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_10_cdr_sar_inv_dp_cb_attr == SERDES_LANE_CDR_NEW_LANE0_REG_10_CDR_SAR_INV_DP_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_10_csr_ki_force_en_attr == SERDES_LANE_CDR_NEW_LANE0_REG_10_CSR_KI_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_10_csr_ki_force_val_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_10_ki_data_mode_val_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_10_ki_fine_cal_val_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_11_cdr_inv_accum_integ_attr == SERDES_LANE_CDR_NEW_LANE0_REG_11_CDR_INV_ACCUM_INTEG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_11_cfg_cdr_accum_init_attr == 21'd349525
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_11_cfg_cdr_accum_init_en_attr == SERDES_LANE_CDR_NEW_LANE0_REG_11_CFG_CDR_ACCUM_INIT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_12_dco_integ_force_en_attr == SERDES_LANE_CDR_NEW_LANE0_REG_12_DCO_INTEG_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_12_dco_integ_force_val_attr == 10'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_12_dco_prop_force_en_attr == SERDES_LANE_CDR_NEW_LANE0_REG_12_DCO_PROP_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_12_dco_prop_force_val_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_13_cfg_pde_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_14_cfg_pde_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_15_c2_c1_lms_init_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_15_c3_c0_lms_init_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_16_cfg_cdr_coeff_cm1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_16_cfg_cdr_coeff_cm2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_16_cfg_cdr_coeff_cp1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_16_cfg_cdr_coeff_cp2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_16_cfg_cdr_coeff_update_sc_attr == SERDES_LANE_CDR_NEW_LANE0_REG_16_CFG_CDR_COEFF_UPDATE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_17_coeff_lms_up1_dn0_inv_attr == SERDES_LANE_CDR_NEW_LANE0_REG_17_COEFF_LMS_UP1_DN0_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_17_lms_stable_clr_attr == SERDES_LANE_CDR_NEW_LANE0_REG_17_LMS_STABLE_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_17_lms_stable_dist_th_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_17_lms_stable_nochange_thr_attr == 16'd1023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_17_lms_stable_ref_th_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_18_cfg_cvar_trim_dcosettle_attr == 14'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_18_slow_trim_dac_sel_max_th_attr == 8'd240
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_18_slow_trim_dac_sel_min_th_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_19_cdr_sel_slow_trim_max_th_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_19_cdr_sel_slow_trim_min_th_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_19_cfg_slow_trim_dcosettle_attr == 14'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_19_cfg_slow_trim_dcoupdate_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_19_cfg_slow_trim_state_ovrd_en_attr == SERDES_LANE_CDR_NEW_LANE0_REG_19_CFG_SLOW_TRIM_STATE_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_19_cfg_slow_trim_state_ovrd_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_19_slow_trim_coarse_direction_inv_attr == SERDES_LANE_CDR_NEW_LANE0_REG_19_SLOW_TRIM_COARSE_DIRECTION_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_19_slow_trim_dac_sel_direction_inv_attr == SERDES_LANE_CDR_NEW_LANE0_REG_19_SLOW_TRIM_DAC_SEL_DIRECTION_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_1_agc_lms_up1_dn0_inv_attr == SERDES_LANE_CDR_NEW_LANE0_REG_1_AGC_LMS_UP1_DN0_INV_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_1_cdr_agc_en_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_1_cdr_agc_speed_th_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_1_cdr_idig_dco_dis_force_en_attr == SERDES_LANE_CDR_NEW_LANE0_REG_1_CDR_IDIG_DCO_DIS_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_1_cdr_idig_dco_dis_force_val_attr == SERDES_LANE_CDR_NEW_LANE0_REG_1_CDR_IDIG_DCO_DIS_FORCE_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_1_cdr_lms_en_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_1_cdr_lms_speed_th_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_1_cdr_pam2_en_from_constellation_attr == SERDES_LANE_CDR_NEW_LANE0_REG_1_CDR_PAM2_EN_FROM_CONSTELLATION_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_1_cdr_pam2_enable_from_reg_attr == SERDES_LANE_CDR_NEW_LANE0_REG_1_CDR_PAM2_ENABLE_FROM_REG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_1_cdr_pd_ext_lvl_dis_attr == SERDES_LANE_CDR_NEW_LANE0_REG_1_CDR_PD_EXT_LVL_DIS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_1_cdren_int_attr == SERDES_LANE_CDR_NEW_LANE0_REG_1_CDREN_INT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_1_cfg_cdr_lock2ref_attr == SERDES_LANE_CDR_NEW_LANE0_REG_1_CFG_CDR_LOCK2REF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_1_cfg_lms_symmetric_en_attr == SERDES_LANE_CDR_NEW_LANE0_REG_1_CFG_LMS_SYMMETRIC_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_1_csr_cdr_snap_data_attr == SERDES_LANE_CDR_NEW_LANE0_REG_1_CSR_CDR_SNAP_DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_1_lms_init_strobe_sc_attr == SERDES_LANE_CDR_NEW_LANE0_REG_1_LMS_INIT_STROBE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_1_oversample_mode_force_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_1_oversample_mode_force_en_attr == SERDES_LANE_CDR_NEW_LANE0_REG_1_OVERSAMPLE_MODE_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_1_ppm_test_en_by_fsm_attr == SERDES_LANE_CDR_NEW_LANE0_REG_1_PPM_TEST_EN_BY_FSM_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_1_ppm_test_en_from_reg_attr == SERDES_LANE_CDR_NEW_LANE0_REG_1_PPM_TEST_EN_FROM_REG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_1_slow_trim_en_attr == SERDES_LANE_CDR_NEW_LANE0_REG_1_SLOW_TRIM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_20_cdr_ber_ph_fifo_en_attr == SERDES_LANE_CDR_NEW_LANE0_REG_20_CDR_BER_PH_FIFO_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_20_cdr_dft_clk_enable_attr == SERDES_LANE_CDR_NEW_LANE0_REG_20_CDR_DFT_CLK_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_20_cdr_dft_clk_rst_n_attr == SERDES_LANE_CDR_NEW_LANE0_REG_20_CDR_DFT_CLK_RST_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_20_csr_cdr_vote_fifo_en_attr == SERDES_LANE_CDR_NEW_LANE0_REG_20_CSR_CDR_VOTE_FIFO_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_20_dft_toggle_vcpi_integ_en_attr == SERDES_LANE_CDR_NEW_LANE0_REG_20_DFT_TOGGLE_VCPI_INTEG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_20_integ_sd_bit_en_attr == SERDES_LANE_CDR_NEW_LANE0_REG_20_INTEG_SD_BIT_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_20_slow_trim_force_mode_attr == SERDES_LANE_CDR_NEW_LANE0_REG_20_SLOW_TRIM_FORCE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_20_slow_trim_strobe_force_val_attr == SERDES_LANE_CDR_NEW_LANE0_REG_20_SLOW_TRIM_STROBE_FORCE_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_20_slow_trim_up1_dn0_force_val_attr == SERDES_LANE_CDR_NEW_LANE0_REG_20_SLOW_TRIM_UP1_DN0_FORCE_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_21_cfg_cdr_jit_force_en_attr == SERDES_LANE_CDR_NEW_LANE0_REG_21_CFG_CDR_JIT_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_21_cfg_cdr_jit_force_mode_attr == SERDES_LANE_CDR_NEW_LANE0_REG_21_CFG_CDR_JIT_FORCE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_21_cfg_dft_jtr_gain_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_21_cfg_dft_jtr_inj_en_attr == SERDES_LANE_CDR_NEW_LANE0_REG_21_CFG_DFT_JTR_INJ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_21_csr_jtr_dis_cnt_th_attr == 12'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_21_csr_jtr_en_cnt_th_attr == 12'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_22_clkgen_skew_strobe_force_en_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_22_clkgen_skew_strobe_force_val_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_22_clkgen_skew_updn_force_en_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_22_clkgen_skew_updn_force_val_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_23_s1_set0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_23_s2_set0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_23_s3_set0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_24_s1_set1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_24_s2_set1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_24_s3_set1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_25_s1_set2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_25_s2_set2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_25_s3_set2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_26_s1_set3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_26_s2_set3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_26_s3_set3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_27_s1_set4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_27_s2_set4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_27_s3_set4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_28_s1_set5_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_28_s2_set5_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_28_s3_set5_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_29_s1_set6_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_29_s2_set6_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_29_s3_set6_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_2_cfg_dcodivcnt_target_attr == 17'd2000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_2_dco_coarse_init_attr == 7'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_2_dco_coarse_max_val_attr == 7'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_30_s1_set7_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_30_s2_set7_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_30_s3_set7_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_31_slicer_broadcast_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_32_constellation_p_braodcast_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_33_constellation_n_braodcast_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_34_c2_set0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_34_c3_set0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_35_c0_set0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_35_c1_set0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_36_c2_set1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_36_c3_set1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_37_c0_set1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_37_c1_set1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_38_c2_set2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_38_c3_set2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_39_c0_set2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_39_c1_set2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_3_cfg_time2dcocnt_attr == 19'd2000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_3_cfg_time2dcosettle_attr == 11'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_40_c2_set3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_40_c3_set3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_41_c0_set3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_41_c1_set3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_42_c2_set4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_42_c3_set4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_43_c0_set4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_43_c1_set4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_44_c2_set5_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_44_c3_set5_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_45_c0_set5_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_45_c1_set5_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_46_c2_set6_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_46_c3_set6_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_47_c0_set6_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_47_c1_set6_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_48_c2_set7_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_48_c3_set7_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_49_c0_set7_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_49_c1_set7_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_4_cfg_calib_reset_bit_attr == SERDES_LANE_CDR_NEW_LANE0_REG_4_CFG_CALIB_RESET_BIT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_4_cfg_coarse_step_final_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_4_cfg_coarse_step_init_attr == 7'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_4_dsp_dco_itail_trim_final_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_4_dsp_dco_itail_trim_init_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_4_icfg_calib_switch_up_down_attr == SERDES_LANE_CDR_NEW_LANE0_REG_4_ICFG_CALIB_SWITCH_UP_DOWN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_4_icfg_coarse_out_inv_attr == SERDES_LANE_CDR_NEW_LANE0_REG_4_ICFG_COARSE_OUT_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_50_cntln_slicer_reg_strobe_sc_attr == SERDES_LANE_CDR_NEW_LANE0_REG_50_CNTLN_SLICER_REG_STROBE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_51_cdr_clock_reset_force_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_51_cfg_cdr_div_te_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_51_cfg_cdr_pfd_clk_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_52_cdr_new_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_52_cdr_new_sec_acc_ctrl_broadcast_mode_attr == SERDES_LANE_CDR_NEW_LANE0_REG_52_CDR_NEW_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_52_cdr_new_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_52_cdr_new_sec_acc_ctrl_field_mask_write_en_attr == SERDES_LANE_CDR_NEW_LANE0_REG_52_CDR_NEW_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_52_cdr_new_sec_acc_ctrl_load_preset_attr == SERDES_LANE_CDR_NEW_LANE0_REG_52_CDR_NEW_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_52_cdr_new_sec_acc_ctrl_man_clear_on_read_attr == SERDES_LANE_CDR_NEW_LANE0_REG_52_CDR_NEW_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_52_cdr_new_sec_acc_ctrl_man_self_clear_attr == SERDES_LANE_CDR_NEW_LANE0_REG_52_CDR_NEW_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_52_cdr_new_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_52_cdr_new_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_52_cdr_new_sec_acc_ctrl_soft_reset_n_attr == SERDES_LANE_CDR_NEW_LANE0_REG_52_CDR_NEW_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_52_cdr_new_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_53_cdr_new_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_53_cdr_new_reg2probe_en_attr == SERDES_LANE_CDR_NEW_LANE0_REG_53_CDR_NEW_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_5_cfg_cdr_state_ovrd_en_attr == SERDES_LANE_CDR_NEW_LANE0_REG_5_CFG_CDR_STATE_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_5_cfg_cdr_state_ovrd_val_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_5_cfg_dcocoarse_ovrd_attr == SERDES_LANE_CDR_NEW_LANE0_REG_5_CFG_DCOCOARSE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_5_cfg_dcocoarse_val_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_5_coarse_ppm_lock_th_attr == 12'd250
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_5_skip_coarse_calib_attr == SERDES_LANE_CDR_NEW_LANE0_REG_5_SKIP_COARSE_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_5_skip_fine_calib_attr == SERDES_LANE_CDR_NEW_LANE0_REG_5_SKIP_FINE_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_6_bb_pfd_sample_negedge_attr == SERDES_LANE_CDR_NEW_LANE0_REG_6_BB_PFD_SAMPLE_NEGEDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_6_cdr_pfd_en_force_en_attr == SERDES_LANE_CDR_NEW_LANE0_REG_6_CDR_PFD_EN_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_6_cdr_pfd_en_force_val_attr == SERDES_LANE_CDR_NEW_LANE0_REG_6_CDR_PFD_EN_FORCE_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_6_cfg_cdr_bb_pfd_step_attr == 9'd207
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_6_cfg_time2tune_fine_cal_attr == 16'd400
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_7_cfg_analog_dco_cvar_strb_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_7_cfg_cvar_trim_dcoupdate_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_7_cfg_cvar_trim_state_ovrd_en_attr == SERDES_LANE_CDR_NEW_LANE0_REG_7_CFG_CVAR_TRIM_STATE_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_7_cfg_cvar_trim_state_ovrd_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_7_dco_cvar_force_mode_ctrl_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_8_cdr_coarse_dac_sel_init_en_attr == SERDES_LANE_CDR_NEW_LANE0_REG_8_CDR_COARSE_DAC_SEL_INIT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_8_csr_coarse_dac_sel_init_attr == 8'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane0_reg_9_cdr_prop_thrs_attr == 28'd63409921
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_10_cdr_prop_thr_load_attr == SERDES_LANE_CDR_NEW_LANE1_REG_10_CDR_PROP_THR_LOAD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_10_cdr_sar_inv_dp_cb_attr == SERDES_LANE_CDR_NEW_LANE1_REG_10_CDR_SAR_INV_DP_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_10_csr_ki_force_en_attr == SERDES_LANE_CDR_NEW_LANE1_REG_10_CSR_KI_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_10_csr_ki_force_val_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_10_ki_data_mode_val_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_10_ki_fine_cal_val_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_11_cdr_inv_accum_integ_attr == SERDES_LANE_CDR_NEW_LANE1_REG_11_CDR_INV_ACCUM_INTEG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_11_cfg_cdr_accum_init_attr == 21'd349525
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_11_cfg_cdr_accum_init_en_attr == SERDES_LANE_CDR_NEW_LANE1_REG_11_CFG_CDR_ACCUM_INIT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_12_dco_integ_force_en_attr == SERDES_LANE_CDR_NEW_LANE1_REG_12_DCO_INTEG_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_12_dco_integ_force_val_attr == 10'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_12_dco_prop_force_en_attr == SERDES_LANE_CDR_NEW_LANE1_REG_12_DCO_PROP_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_12_dco_prop_force_val_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_13_cfg_pde_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_14_cfg_pde_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_15_c2_c1_lms_init_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_15_c3_c0_lms_init_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_16_cfg_cdr_coeff_cm1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_16_cfg_cdr_coeff_cm2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_16_cfg_cdr_coeff_cp1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_16_cfg_cdr_coeff_cp2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_16_cfg_cdr_coeff_update_sc_attr == SERDES_LANE_CDR_NEW_LANE1_REG_16_CFG_CDR_COEFF_UPDATE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_17_coeff_lms_up1_dn0_inv_attr == SERDES_LANE_CDR_NEW_LANE1_REG_17_COEFF_LMS_UP1_DN0_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_17_lms_stable_clr_attr == SERDES_LANE_CDR_NEW_LANE1_REG_17_LMS_STABLE_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_17_lms_stable_dist_th_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_17_lms_stable_nochange_thr_attr == 16'd1023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_17_lms_stable_ref_th_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_18_cfg_cvar_trim_dcosettle_attr == 14'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_18_slow_trim_dac_sel_max_th_attr == 8'd240
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_18_slow_trim_dac_sel_min_th_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_19_cdr_sel_slow_trim_max_th_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_19_cdr_sel_slow_trim_min_th_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_19_cfg_slow_trim_dcosettle_attr == 14'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_19_cfg_slow_trim_dcoupdate_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_19_cfg_slow_trim_state_ovrd_en_attr == SERDES_LANE_CDR_NEW_LANE1_REG_19_CFG_SLOW_TRIM_STATE_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_19_cfg_slow_trim_state_ovrd_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_19_slow_trim_coarse_direction_inv_attr == SERDES_LANE_CDR_NEW_LANE1_REG_19_SLOW_TRIM_COARSE_DIRECTION_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_19_slow_trim_dac_sel_direction_inv_attr == SERDES_LANE_CDR_NEW_LANE1_REG_19_SLOW_TRIM_DAC_SEL_DIRECTION_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_1_agc_lms_up1_dn0_inv_attr == SERDES_LANE_CDR_NEW_LANE1_REG_1_AGC_LMS_UP1_DN0_INV_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_1_cdr_agc_en_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_1_cdr_agc_speed_th_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_1_cdr_idig_dco_dis_force_en_attr == SERDES_LANE_CDR_NEW_LANE1_REG_1_CDR_IDIG_DCO_DIS_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_1_cdr_idig_dco_dis_force_val_attr == SERDES_LANE_CDR_NEW_LANE1_REG_1_CDR_IDIG_DCO_DIS_FORCE_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_1_cdr_lms_en_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_1_cdr_lms_speed_th_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_1_cdr_pam2_en_from_constellation_attr == SERDES_LANE_CDR_NEW_LANE1_REG_1_CDR_PAM2_EN_FROM_CONSTELLATION_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_1_cdr_pam2_enable_from_reg_attr == SERDES_LANE_CDR_NEW_LANE1_REG_1_CDR_PAM2_ENABLE_FROM_REG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_1_cdr_pd_ext_lvl_dis_attr == SERDES_LANE_CDR_NEW_LANE1_REG_1_CDR_PD_EXT_LVL_DIS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_1_cdren_int_attr == SERDES_LANE_CDR_NEW_LANE1_REG_1_CDREN_INT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_1_cfg_cdr_lock2ref_attr == SERDES_LANE_CDR_NEW_LANE1_REG_1_CFG_CDR_LOCK2REF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_1_cfg_lms_symmetric_en_attr == SERDES_LANE_CDR_NEW_LANE1_REG_1_CFG_LMS_SYMMETRIC_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_1_csr_cdr_snap_data_attr == SERDES_LANE_CDR_NEW_LANE1_REG_1_CSR_CDR_SNAP_DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_1_lms_init_strobe_sc_attr == SERDES_LANE_CDR_NEW_LANE1_REG_1_LMS_INIT_STROBE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_1_oversample_mode_force_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_1_oversample_mode_force_en_attr == SERDES_LANE_CDR_NEW_LANE1_REG_1_OVERSAMPLE_MODE_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_1_ppm_test_en_by_fsm_attr == SERDES_LANE_CDR_NEW_LANE1_REG_1_PPM_TEST_EN_BY_FSM_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_1_ppm_test_en_from_reg_attr == SERDES_LANE_CDR_NEW_LANE1_REG_1_PPM_TEST_EN_FROM_REG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_1_slow_trim_en_attr == SERDES_LANE_CDR_NEW_LANE1_REG_1_SLOW_TRIM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_20_cdr_ber_ph_fifo_en_attr == SERDES_LANE_CDR_NEW_LANE1_REG_20_CDR_BER_PH_FIFO_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_20_cdr_dft_clk_enable_attr == SERDES_LANE_CDR_NEW_LANE1_REG_20_CDR_DFT_CLK_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_20_cdr_dft_clk_rst_n_attr == SERDES_LANE_CDR_NEW_LANE1_REG_20_CDR_DFT_CLK_RST_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_20_csr_cdr_vote_fifo_en_attr == SERDES_LANE_CDR_NEW_LANE1_REG_20_CSR_CDR_VOTE_FIFO_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_20_dft_toggle_vcpi_integ_en_attr == SERDES_LANE_CDR_NEW_LANE1_REG_20_DFT_TOGGLE_VCPI_INTEG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_20_integ_sd_bit_en_attr == SERDES_LANE_CDR_NEW_LANE1_REG_20_INTEG_SD_BIT_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_20_slow_trim_force_mode_attr == SERDES_LANE_CDR_NEW_LANE1_REG_20_SLOW_TRIM_FORCE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_20_slow_trim_strobe_force_val_attr == SERDES_LANE_CDR_NEW_LANE1_REG_20_SLOW_TRIM_STROBE_FORCE_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_20_slow_trim_up1_dn0_force_val_attr == SERDES_LANE_CDR_NEW_LANE1_REG_20_SLOW_TRIM_UP1_DN0_FORCE_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_21_cfg_cdr_jit_force_en_attr == SERDES_LANE_CDR_NEW_LANE1_REG_21_CFG_CDR_JIT_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_21_cfg_cdr_jit_force_mode_attr == SERDES_LANE_CDR_NEW_LANE1_REG_21_CFG_CDR_JIT_FORCE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_21_cfg_dft_jtr_gain_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_21_cfg_dft_jtr_inj_en_attr == SERDES_LANE_CDR_NEW_LANE1_REG_21_CFG_DFT_JTR_INJ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_21_csr_jtr_dis_cnt_th_attr == 12'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_21_csr_jtr_en_cnt_th_attr == 12'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_22_clkgen_skew_strobe_force_en_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_22_clkgen_skew_strobe_force_val_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_22_clkgen_skew_updn_force_en_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_22_clkgen_skew_updn_force_val_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_23_s1_set0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_23_s2_set0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_23_s3_set0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_24_s1_set1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_24_s2_set1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_24_s3_set1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_25_s1_set2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_25_s2_set2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_25_s3_set2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_26_s1_set3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_26_s2_set3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_26_s3_set3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_27_s1_set4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_27_s2_set4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_27_s3_set4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_28_s1_set5_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_28_s2_set5_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_28_s3_set5_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_29_s1_set6_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_29_s2_set6_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_29_s3_set6_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_2_cfg_dcodivcnt_target_attr == 17'd2000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_2_dco_coarse_init_attr == 7'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_2_dco_coarse_max_val_attr == 7'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_30_s1_set7_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_30_s2_set7_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_30_s3_set7_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_31_slicer_broadcast_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_32_constellation_p_braodcast_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_33_constellation_n_braodcast_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_34_c2_set0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_34_c3_set0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_35_c0_set0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_35_c1_set0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_36_c2_set1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_36_c3_set1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_37_c0_set1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_37_c1_set1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_38_c2_set2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_38_c3_set2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_39_c0_set2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_39_c1_set2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_3_cfg_time2dcocnt_attr == 19'd2000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_3_cfg_time2dcosettle_attr == 11'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_40_c2_set3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_40_c3_set3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_41_c0_set3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_41_c1_set3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_42_c2_set4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_42_c3_set4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_43_c0_set4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_43_c1_set4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_44_c2_set5_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_44_c3_set5_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_45_c0_set5_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_45_c1_set5_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_46_c2_set6_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_46_c3_set6_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_47_c0_set6_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_47_c1_set6_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_48_c2_set7_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_48_c3_set7_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_49_c0_set7_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_49_c1_set7_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_4_cfg_calib_reset_bit_attr == SERDES_LANE_CDR_NEW_LANE1_REG_4_CFG_CALIB_RESET_BIT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_4_cfg_coarse_step_final_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_4_cfg_coarse_step_init_attr == 7'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_4_dsp_dco_itail_trim_final_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_4_dsp_dco_itail_trim_init_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_4_icfg_calib_switch_up_down_attr == SERDES_LANE_CDR_NEW_LANE1_REG_4_ICFG_CALIB_SWITCH_UP_DOWN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_4_icfg_coarse_out_inv_attr == SERDES_LANE_CDR_NEW_LANE1_REG_4_ICFG_COARSE_OUT_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_50_cntln_slicer_reg_strobe_sc_attr == SERDES_LANE_CDR_NEW_LANE1_REG_50_CNTLN_SLICER_REG_STROBE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_51_cdr_clock_reset_force_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_51_cfg_cdr_div_te_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_51_cfg_cdr_pfd_clk_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_52_cdr_new_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_52_cdr_new_sec_acc_ctrl_broadcast_mode_attr == SERDES_LANE_CDR_NEW_LANE1_REG_52_CDR_NEW_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_52_cdr_new_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_52_cdr_new_sec_acc_ctrl_field_mask_write_en_attr == SERDES_LANE_CDR_NEW_LANE1_REG_52_CDR_NEW_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_52_cdr_new_sec_acc_ctrl_load_preset_attr == SERDES_LANE_CDR_NEW_LANE1_REG_52_CDR_NEW_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_52_cdr_new_sec_acc_ctrl_man_clear_on_read_attr == SERDES_LANE_CDR_NEW_LANE1_REG_52_CDR_NEW_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_52_cdr_new_sec_acc_ctrl_man_self_clear_attr == SERDES_LANE_CDR_NEW_LANE1_REG_52_CDR_NEW_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_52_cdr_new_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_52_cdr_new_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_52_cdr_new_sec_acc_ctrl_soft_reset_n_attr == SERDES_LANE_CDR_NEW_LANE1_REG_52_CDR_NEW_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_52_cdr_new_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_53_cdr_new_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_53_cdr_new_reg2probe_en_attr == SERDES_LANE_CDR_NEW_LANE1_REG_53_CDR_NEW_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_5_cfg_cdr_state_ovrd_en_attr == SERDES_LANE_CDR_NEW_LANE1_REG_5_CFG_CDR_STATE_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_5_cfg_cdr_state_ovrd_val_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_5_cfg_dcocoarse_ovrd_attr == SERDES_LANE_CDR_NEW_LANE1_REG_5_CFG_DCOCOARSE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_5_cfg_dcocoarse_val_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_5_coarse_ppm_lock_th_attr == 12'd250
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_5_skip_coarse_calib_attr == SERDES_LANE_CDR_NEW_LANE1_REG_5_SKIP_COARSE_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_5_skip_fine_calib_attr == SERDES_LANE_CDR_NEW_LANE1_REG_5_SKIP_FINE_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_6_bb_pfd_sample_negedge_attr == SERDES_LANE_CDR_NEW_LANE1_REG_6_BB_PFD_SAMPLE_NEGEDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_6_cdr_pfd_en_force_en_attr == SERDES_LANE_CDR_NEW_LANE1_REG_6_CDR_PFD_EN_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_6_cdr_pfd_en_force_val_attr == SERDES_LANE_CDR_NEW_LANE1_REG_6_CDR_PFD_EN_FORCE_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_6_cfg_cdr_bb_pfd_step_attr == 9'd207
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_6_cfg_time2tune_fine_cal_attr == 16'd400
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_7_cfg_analog_dco_cvar_strb_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_7_cfg_cvar_trim_dcoupdate_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_7_cfg_cvar_trim_state_ovrd_en_attr == SERDES_LANE_CDR_NEW_LANE1_REG_7_CFG_CVAR_TRIM_STATE_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_7_cfg_cvar_trim_state_ovrd_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_7_dco_cvar_force_mode_ctrl_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_8_cdr_coarse_dac_sel_init_en_attr == SERDES_LANE_CDR_NEW_LANE1_REG_8_CDR_COARSE_DAC_SEL_INIT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_8_csr_coarse_dac_sel_init_attr == 8'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane1_reg_9_cdr_prop_thrs_attr == 28'd63409921
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_10_cdr_prop_thr_load_attr == SERDES_LANE_CDR_NEW_LANE2_REG_10_CDR_PROP_THR_LOAD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_10_cdr_sar_inv_dp_cb_attr == SERDES_LANE_CDR_NEW_LANE2_REG_10_CDR_SAR_INV_DP_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_10_csr_ki_force_en_attr == SERDES_LANE_CDR_NEW_LANE2_REG_10_CSR_KI_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_10_csr_ki_force_val_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_10_ki_data_mode_val_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_10_ki_fine_cal_val_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_11_cdr_inv_accum_integ_attr == SERDES_LANE_CDR_NEW_LANE2_REG_11_CDR_INV_ACCUM_INTEG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_11_cfg_cdr_accum_init_attr == 21'd349525
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_11_cfg_cdr_accum_init_en_attr == SERDES_LANE_CDR_NEW_LANE2_REG_11_CFG_CDR_ACCUM_INIT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_12_dco_integ_force_en_attr == SERDES_LANE_CDR_NEW_LANE2_REG_12_DCO_INTEG_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_12_dco_integ_force_val_attr == 10'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_12_dco_prop_force_en_attr == SERDES_LANE_CDR_NEW_LANE2_REG_12_DCO_PROP_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_12_dco_prop_force_val_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_13_cfg_pde_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_14_cfg_pde_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_15_c2_c1_lms_init_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_15_c3_c0_lms_init_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_16_cfg_cdr_coeff_cm1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_16_cfg_cdr_coeff_cm2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_16_cfg_cdr_coeff_cp1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_16_cfg_cdr_coeff_cp2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_16_cfg_cdr_coeff_update_sc_attr == SERDES_LANE_CDR_NEW_LANE2_REG_16_CFG_CDR_COEFF_UPDATE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_17_coeff_lms_up1_dn0_inv_attr == SERDES_LANE_CDR_NEW_LANE2_REG_17_COEFF_LMS_UP1_DN0_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_17_lms_stable_clr_attr == SERDES_LANE_CDR_NEW_LANE2_REG_17_LMS_STABLE_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_17_lms_stable_dist_th_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_17_lms_stable_nochange_thr_attr == 16'd1023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_17_lms_stable_ref_th_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_18_cfg_cvar_trim_dcosettle_attr == 14'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_18_slow_trim_dac_sel_max_th_attr == 8'd240
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_18_slow_trim_dac_sel_min_th_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_19_cdr_sel_slow_trim_max_th_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_19_cdr_sel_slow_trim_min_th_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_19_cfg_slow_trim_dcosettle_attr == 14'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_19_cfg_slow_trim_dcoupdate_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_19_cfg_slow_trim_state_ovrd_en_attr == SERDES_LANE_CDR_NEW_LANE2_REG_19_CFG_SLOW_TRIM_STATE_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_19_cfg_slow_trim_state_ovrd_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_19_slow_trim_coarse_direction_inv_attr == SERDES_LANE_CDR_NEW_LANE2_REG_19_SLOW_TRIM_COARSE_DIRECTION_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_19_slow_trim_dac_sel_direction_inv_attr == SERDES_LANE_CDR_NEW_LANE2_REG_19_SLOW_TRIM_DAC_SEL_DIRECTION_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_1_agc_lms_up1_dn0_inv_attr == SERDES_LANE_CDR_NEW_LANE2_REG_1_AGC_LMS_UP1_DN0_INV_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_1_cdr_agc_en_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_1_cdr_agc_speed_th_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_1_cdr_idig_dco_dis_force_en_attr == SERDES_LANE_CDR_NEW_LANE2_REG_1_CDR_IDIG_DCO_DIS_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_1_cdr_idig_dco_dis_force_val_attr == SERDES_LANE_CDR_NEW_LANE2_REG_1_CDR_IDIG_DCO_DIS_FORCE_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_1_cdr_lms_en_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_1_cdr_lms_speed_th_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_1_cdr_pam2_en_from_constellation_attr == SERDES_LANE_CDR_NEW_LANE2_REG_1_CDR_PAM2_EN_FROM_CONSTELLATION_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_1_cdr_pam2_enable_from_reg_attr == SERDES_LANE_CDR_NEW_LANE2_REG_1_CDR_PAM2_ENABLE_FROM_REG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_1_cdr_pd_ext_lvl_dis_attr == SERDES_LANE_CDR_NEW_LANE2_REG_1_CDR_PD_EXT_LVL_DIS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_1_cdren_int_attr == SERDES_LANE_CDR_NEW_LANE2_REG_1_CDREN_INT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_1_cfg_cdr_lock2ref_attr == SERDES_LANE_CDR_NEW_LANE2_REG_1_CFG_CDR_LOCK2REF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_1_cfg_lms_symmetric_en_attr == SERDES_LANE_CDR_NEW_LANE2_REG_1_CFG_LMS_SYMMETRIC_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_1_csr_cdr_snap_data_attr == SERDES_LANE_CDR_NEW_LANE2_REG_1_CSR_CDR_SNAP_DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_1_lms_init_strobe_sc_attr == SERDES_LANE_CDR_NEW_LANE2_REG_1_LMS_INIT_STROBE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_1_oversample_mode_force_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_1_oversample_mode_force_en_attr == SERDES_LANE_CDR_NEW_LANE2_REG_1_OVERSAMPLE_MODE_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_1_ppm_test_en_by_fsm_attr == SERDES_LANE_CDR_NEW_LANE2_REG_1_PPM_TEST_EN_BY_FSM_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_1_ppm_test_en_from_reg_attr == SERDES_LANE_CDR_NEW_LANE2_REG_1_PPM_TEST_EN_FROM_REG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_1_slow_trim_en_attr == SERDES_LANE_CDR_NEW_LANE2_REG_1_SLOW_TRIM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_20_cdr_ber_ph_fifo_en_attr == SERDES_LANE_CDR_NEW_LANE2_REG_20_CDR_BER_PH_FIFO_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_20_cdr_dft_clk_enable_attr == SERDES_LANE_CDR_NEW_LANE2_REG_20_CDR_DFT_CLK_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_20_cdr_dft_clk_rst_n_attr == SERDES_LANE_CDR_NEW_LANE2_REG_20_CDR_DFT_CLK_RST_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_20_csr_cdr_vote_fifo_en_attr == SERDES_LANE_CDR_NEW_LANE2_REG_20_CSR_CDR_VOTE_FIFO_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_20_dft_toggle_vcpi_integ_en_attr == SERDES_LANE_CDR_NEW_LANE2_REG_20_DFT_TOGGLE_VCPI_INTEG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_20_integ_sd_bit_en_attr == SERDES_LANE_CDR_NEW_LANE2_REG_20_INTEG_SD_BIT_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_20_slow_trim_force_mode_attr == SERDES_LANE_CDR_NEW_LANE2_REG_20_SLOW_TRIM_FORCE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_20_slow_trim_strobe_force_val_attr == SERDES_LANE_CDR_NEW_LANE2_REG_20_SLOW_TRIM_STROBE_FORCE_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_20_slow_trim_up1_dn0_force_val_attr == SERDES_LANE_CDR_NEW_LANE2_REG_20_SLOW_TRIM_UP1_DN0_FORCE_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_21_cfg_cdr_jit_force_en_attr == SERDES_LANE_CDR_NEW_LANE2_REG_21_CFG_CDR_JIT_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_21_cfg_cdr_jit_force_mode_attr == SERDES_LANE_CDR_NEW_LANE2_REG_21_CFG_CDR_JIT_FORCE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_21_cfg_dft_jtr_gain_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_21_cfg_dft_jtr_inj_en_attr == SERDES_LANE_CDR_NEW_LANE2_REG_21_CFG_DFT_JTR_INJ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_21_csr_jtr_dis_cnt_th_attr == 12'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_21_csr_jtr_en_cnt_th_attr == 12'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_22_clkgen_skew_strobe_force_en_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_22_clkgen_skew_strobe_force_val_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_22_clkgen_skew_updn_force_en_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_22_clkgen_skew_updn_force_val_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_23_s1_set0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_23_s2_set0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_23_s3_set0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_24_s1_set1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_24_s2_set1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_24_s3_set1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_25_s1_set2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_25_s2_set2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_25_s3_set2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_26_s1_set3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_26_s2_set3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_26_s3_set3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_27_s1_set4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_27_s2_set4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_27_s3_set4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_28_s1_set5_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_28_s2_set5_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_28_s3_set5_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_29_s1_set6_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_29_s2_set6_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_29_s3_set6_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_2_cfg_dcodivcnt_target_attr == 17'd2000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_2_dco_coarse_init_attr == 7'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_2_dco_coarse_max_val_attr == 7'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_30_s1_set7_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_30_s2_set7_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_30_s3_set7_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_31_slicer_broadcast_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_32_constellation_p_braodcast_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_33_constellation_n_braodcast_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_34_c2_set0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_34_c3_set0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_35_c0_set0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_35_c1_set0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_36_c2_set1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_36_c3_set1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_37_c0_set1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_37_c1_set1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_38_c2_set2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_38_c3_set2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_39_c0_set2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_39_c1_set2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_3_cfg_time2dcocnt_attr == 19'd2000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_3_cfg_time2dcosettle_attr == 11'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_40_c2_set3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_40_c3_set3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_41_c0_set3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_41_c1_set3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_42_c2_set4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_42_c3_set4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_43_c0_set4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_43_c1_set4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_44_c2_set5_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_44_c3_set5_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_45_c0_set5_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_45_c1_set5_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_46_c2_set6_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_46_c3_set6_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_47_c0_set6_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_47_c1_set6_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_48_c2_set7_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_48_c3_set7_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_49_c0_set7_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_49_c1_set7_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_4_cfg_calib_reset_bit_attr == SERDES_LANE_CDR_NEW_LANE2_REG_4_CFG_CALIB_RESET_BIT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_4_cfg_coarse_step_final_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_4_cfg_coarse_step_init_attr == 7'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_4_dsp_dco_itail_trim_final_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_4_dsp_dco_itail_trim_init_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_4_icfg_calib_switch_up_down_attr == SERDES_LANE_CDR_NEW_LANE2_REG_4_ICFG_CALIB_SWITCH_UP_DOWN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_4_icfg_coarse_out_inv_attr == SERDES_LANE_CDR_NEW_LANE2_REG_4_ICFG_COARSE_OUT_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_50_cntln_slicer_reg_strobe_sc_attr == SERDES_LANE_CDR_NEW_LANE2_REG_50_CNTLN_SLICER_REG_STROBE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_51_cdr_clock_reset_force_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_51_cfg_cdr_div_te_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_51_cfg_cdr_pfd_clk_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_52_cdr_new_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_52_cdr_new_sec_acc_ctrl_broadcast_mode_attr == SERDES_LANE_CDR_NEW_LANE2_REG_52_CDR_NEW_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_52_cdr_new_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_52_cdr_new_sec_acc_ctrl_field_mask_write_en_attr == SERDES_LANE_CDR_NEW_LANE2_REG_52_CDR_NEW_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_52_cdr_new_sec_acc_ctrl_load_preset_attr == SERDES_LANE_CDR_NEW_LANE2_REG_52_CDR_NEW_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_52_cdr_new_sec_acc_ctrl_man_clear_on_read_attr == SERDES_LANE_CDR_NEW_LANE2_REG_52_CDR_NEW_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_52_cdr_new_sec_acc_ctrl_man_self_clear_attr == SERDES_LANE_CDR_NEW_LANE2_REG_52_CDR_NEW_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_52_cdr_new_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_52_cdr_new_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_52_cdr_new_sec_acc_ctrl_soft_reset_n_attr == SERDES_LANE_CDR_NEW_LANE2_REG_52_CDR_NEW_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_52_cdr_new_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_53_cdr_new_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_53_cdr_new_reg2probe_en_attr == SERDES_LANE_CDR_NEW_LANE2_REG_53_CDR_NEW_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_5_cfg_cdr_state_ovrd_en_attr == SERDES_LANE_CDR_NEW_LANE2_REG_5_CFG_CDR_STATE_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_5_cfg_cdr_state_ovrd_val_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_5_cfg_dcocoarse_ovrd_attr == SERDES_LANE_CDR_NEW_LANE2_REG_5_CFG_DCOCOARSE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_5_cfg_dcocoarse_val_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_5_coarse_ppm_lock_th_attr == 12'd250
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_5_skip_coarse_calib_attr == SERDES_LANE_CDR_NEW_LANE2_REG_5_SKIP_COARSE_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_5_skip_fine_calib_attr == SERDES_LANE_CDR_NEW_LANE2_REG_5_SKIP_FINE_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_6_bb_pfd_sample_negedge_attr == SERDES_LANE_CDR_NEW_LANE2_REG_6_BB_PFD_SAMPLE_NEGEDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_6_cdr_pfd_en_force_en_attr == SERDES_LANE_CDR_NEW_LANE2_REG_6_CDR_PFD_EN_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_6_cdr_pfd_en_force_val_attr == SERDES_LANE_CDR_NEW_LANE2_REG_6_CDR_PFD_EN_FORCE_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_6_cfg_cdr_bb_pfd_step_attr == 9'd207
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_6_cfg_time2tune_fine_cal_attr == 16'd400
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_7_cfg_analog_dco_cvar_strb_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_7_cfg_cvar_trim_dcoupdate_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_7_cfg_cvar_trim_state_ovrd_en_attr == SERDES_LANE_CDR_NEW_LANE2_REG_7_CFG_CVAR_TRIM_STATE_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_7_cfg_cvar_trim_state_ovrd_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_7_dco_cvar_force_mode_ctrl_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_8_cdr_coarse_dac_sel_init_en_attr == SERDES_LANE_CDR_NEW_LANE2_REG_8_CDR_COARSE_DAC_SEL_INIT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_8_csr_coarse_dac_sel_init_attr == 8'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane2_reg_9_cdr_prop_thrs_attr == 28'd63409921
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_10_cdr_prop_thr_load_attr == SERDES_LANE_CDR_NEW_LANE3_REG_10_CDR_PROP_THR_LOAD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_10_cdr_sar_inv_dp_cb_attr == SERDES_LANE_CDR_NEW_LANE3_REG_10_CDR_SAR_INV_DP_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_10_csr_ki_force_en_attr == SERDES_LANE_CDR_NEW_LANE3_REG_10_CSR_KI_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_10_csr_ki_force_val_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_10_ki_data_mode_val_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_10_ki_fine_cal_val_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_11_cdr_inv_accum_integ_attr == SERDES_LANE_CDR_NEW_LANE3_REG_11_CDR_INV_ACCUM_INTEG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_11_cfg_cdr_accum_init_attr == 21'd349525
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_11_cfg_cdr_accum_init_en_attr == SERDES_LANE_CDR_NEW_LANE3_REG_11_CFG_CDR_ACCUM_INIT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_12_dco_integ_force_en_attr == SERDES_LANE_CDR_NEW_LANE3_REG_12_DCO_INTEG_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_12_dco_integ_force_val_attr == 10'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_12_dco_prop_force_en_attr == SERDES_LANE_CDR_NEW_LANE3_REG_12_DCO_PROP_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_12_dco_prop_force_val_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_13_cfg_pde_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_14_cfg_pde_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_15_c2_c1_lms_init_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_15_c3_c0_lms_init_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_16_cfg_cdr_coeff_cm1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_16_cfg_cdr_coeff_cm2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_16_cfg_cdr_coeff_cp1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_16_cfg_cdr_coeff_cp2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_16_cfg_cdr_coeff_update_sc_attr == SERDES_LANE_CDR_NEW_LANE3_REG_16_CFG_CDR_COEFF_UPDATE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_17_coeff_lms_up1_dn0_inv_attr == SERDES_LANE_CDR_NEW_LANE3_REG_17_COEFF_LMS_UP1_DN0_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_17_lms_stable_clr_attr == SERDES_LANE_CDR_NEW_LANE3_REG_17_LMS_STABLE_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_17_lms_stable_dist_th_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_17_lms_stable_nochange_thr_attr == 16'd1023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_17_lms_stable_ref_th_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_18_cfg_cvar_trim_dcosettle_attr == 14'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_18_slow_trim_dac_sel_max_th_attr == 8'd240
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_18_slow_trim_dac_sel_min_th_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_19_cdr_sel_slow_trim_max_th_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_19_cdr_sel_slow_trim_min_th_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_19_cfg_slow_trim_dcosettle_attr == 14'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_19_cfg_slow_trim_dcoupdate_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_19_cfg_slow_trim_state_ovrd_en_attr == SERDES_LANE_CDR_NEW_LANE3_REG_19_CFG_SLOW_TRIM_STATE_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_19_cfg_slow_trim_state_ovrd_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_19_slow_trim_coarse_direction_inv_attr == SERDES_LANE_CDR_NEW_LANE3_REG_19_SLOW_TRIM_COARSE_DIRECTION_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_19_slow_trim_dac_sel_direction_inv_attr == SERDES_LANE_CDR_NEW_LANE3_REG_19_SLOW_TRIM_DAC_SEL_DIRECTION_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_1_agc_lms_up1_dn0_inv_attr == SERDES_LANE_CDR_NEW_LANE3_REG_1_AGC_LMS_UP1_DN0_INV_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_1_cdr_agc_en_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_1_cdr_agc_speed_th_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_1_cdr_idig_dco_dis_force_en_attr == SERDES_LANE_CDR_NEW_LANE3_REG_1_CDR_IDIG_DCO_DIS_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_1_cdr_idig_dco_dis_force_val_attr == SERDES_LANE_CDR_NEW_LANE3_REG_1_CDR_IDIG_DCO_DIS_FORCE_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_1_cdr_lms_en_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_1_cdr_lms_speed_th_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_1_cdr_pam2_en_from_constellation_attr == SERDES_LANE_CDR_NEW_LANE3_REG_1_CDR_PAM2_EN_FROM_CONSTELLATION_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_1_cdr_pam2_enable_from_reg_attr == SERDES_LANE_CDR_NEW_LANE3_REG_1_CDR_PAM2_ENABLE_FROM_REG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_1_cdr_pd_ext_lvl_dis_attr == SERDES_LANE_CDR_NEW_LANE3_REG_1_CDR_PD_EXT_LVL_DIS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_1_cdren_int_attr == SERDES_LANE_CDR_NEW_LANE3_REG_1_CDREN_INT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_1_cfg_cdr_lock2ref_attr == SERDES_LANE_CDR_NEW_LANE3_REG_1_CFG_CDR_LOCK2REF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_1_cfg_lms_symmetric_en_attr == SERDES_LANE_CDR_NEW_LANE3_REG_1_CFG_LMS_SYMMETRIC_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_1_csr_cdr_snap_data_attr == SERDES_LANE_CDR_NEW_LANE3_REG_1_CSR_CDR_SNAP_DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_1_lms_init_strobe_sc_attr == SERDES_LANE_CDR_NEW_LANE3_REG_1_LMS_INIT_STROBE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_1_oversample_mode_force_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_1_oversample_mode_force_en_attr == SERDES_LANE_CDR_NEW_LANE3_REG_1_OVERSAMPLE_MODE_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_1_ppm_test_en_by_fsm_attr == SERDES_LANE_CDR_NEW_LANE3_REG_1_PPM_TEST_EN_BY_FSM_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_1_ppm_test_en_from_reg_attr == SERDES_LANE_CDR_NEW_LANE3_REG_1_PPM_TEST_EN_FROM_REG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_1_slow_trim_en_attr == SERDES_LANE_CDR_NEW_LANE3_REG_1_SLOW_TRIM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_20_cdr_ber_ph_fifo_en_attr == SERDES_LANE_CDR_NEW_LANE3_REG_20_CDR_BER_PH_FIFO_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_20_cdr_dft_clk_enable_attr == SERDES_LANE_CDR_NEW_LANE3_REG_20_CDR_DFT_CLK_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_20_cdr_dft_clk_rst_n_attr == SERDES_LANE_CDR_NEW_LANE3_REG_20_CDR_DFT_CLK_RST_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_20_csr_cdr_vote_fifo_en_attr == SERDES_LANE_CDR_NEW_LANE3_REG_20_CSR_CDR_VOTE_FIFO_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_20_dft_toggle_vcpi_integ_en_attr == SERDES_LANE_CDR_NEW_LANE3_REG_20_DFT_TOGGLE_VCPI_INTEG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_20_integ_sd_bit_en_attr == SERDES_LANE_CDR_NEW_LANE3_REG_20_INTEG_SD_BIT_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_20_slow_trim_force_mode_attr == SERDES_LANE_CDR_NEW_LANE3_REG_20_SLOW_TRIM_FORCE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_20_slow_trim_strobe_force_val_attr == SERDES_LANE_CDR_NEW_LANE3_REG_20_SLOW_TRIM_STROBE_FORCE_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_20_slow_trim_up1_dn0_force_val_attr == SERDES_LANE_CDR_NEW_LANE3_REG_20_SLOW_TRIM_UP1_DN0_FORCE_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_21_cfg_cdr_jit_force_en_attr == SERDES_LANE_CDR_NEW_LANE3_REG_21_CFG_CDR_JIT_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_21_cfg_cdr_jit_force_mode_attr == SERDES_LANE_CDR_NEW_LANE3_REG_21_CFG_CDR_JIT_FORCE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_21_cfg_dft_jtr_gain_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_21_cfg_dft_jtr_inj_en_attr == SERDES_LANE_CDR_NEW_LANE3_REG_21_CFG_DFT_JTR_INJ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_21_csr_jtr_dis_cnt_th_attr == 12'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_21_csr_jtr_en_cnt_th_attr == 12'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_22_clkgen_skew_strobe_force_en_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_22_clkgen_skew_strobe_force_val_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_22_clkgen_skew_updn_force_en_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_22_clkgen_skew_updn_force_val_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_23_s1_set0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_23_s2_set0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_23_s3_set0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_24_s1_set1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_24_s2_set1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_24_s3_set1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_25_s1_set2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_25_s2_set2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_25_s3_set2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_26_s1_set3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_26_s2_set3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_26_s3_set3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_27_s1_set4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_27_s2_set4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_27_s3_set4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_28_s1_set5_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_28_s2_set5_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_28_s3_set5_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_29_s1_set6_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_29_s2_set6_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_29_s3_set6_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_2_cfg_dcodivcnt_target_attr == 17'd2000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_2_dco_coarse_init_attr == 7'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_2_dco_coarse_max_val_attr == 7'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_30_s1_set7_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_30_s2_set7_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_30_s3_set7_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_31_slicer_broadcast_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_32_constellation_p_braodcast_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_33_constellation_n_braodcast_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_34_c2_set0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_34_c3_set0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_35_c0_set0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_35_c1_set0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_36_c2_set1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_36_c3_set1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_37_c0_set1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_37_c1_set1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_38_c2_set2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_38_c3_set2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_39_c0_set2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_39_c1_set2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_3_cfg_time2dcocnt_attr == 19'd2000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_3_cfg_time2dcosettle_attr == 11'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_40_c2_set3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_40_c3_set3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_41_c0_set3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_41_c1_set3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_42_c2_set4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_42_c3_set4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_43_c0_set4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_43_c1_set4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_44_c2_set5_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_44_c3_set5_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_45_c0_set5_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_45_c1_set5_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_46_c2_set6_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_46_c3_set6_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_47_c0_set6_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_47_c1_set6_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_48_c2_set7_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_48_c3_set7_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_49_c0_set7_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_49_c1_set7_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_4_cfg_calib_reset_bit_attr == SERDES_LANE_CDR_NEW_LANE3_REG_4_CFG_CALIB_RESET_BIT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_4_cfg_coarse_step_final_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_4_cfg_coarse_step_init_attr == 7'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_4_dsp_dco_itail_trim_final_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_4_dsp_dco_itail_trim_init_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_4_icfg_calib_switch_up_down_attr == SERDES_LANE_CDR_NEW_LANE3_REG_4_ICFG_CALIB_SWITCH_UP_DOWN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_4_icfg_coarse_out_inv_attr == SERDES_LANE_CDR_NEW_LANE3_REG_4_ICFG_COARSE_OUT_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_50_cntln_slicer_reg_strobe_sc_attr == SERDES_LANE_CDR_NEW_LANE3_REG_50_CNTLN_SLICER_REG_STROBE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_51_cdr_clock_reset_force_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_51_cfg_cdr_div_te_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_51_cfg_cdr_pfd_clk_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_52_cdr_new_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_52_cdr_new_sec_acc_ctrl_broadcast_mode_attr == SERDES_LANE_CDR_NEW_LANE3_REG_52_CDR_NEW_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_52_cdr_new_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_52_cdr_new_sec_acc_ctrl_field_mask_write_en_attr == SERDES_LANE_CDR_NEW_LANE3_REG_52_CDR_NEW_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_52_cdr_new_sec_acc_ctrl_load_preset_attr == SERDES_LANE_CDR_NEW_LANE3_REG_52_CDR_NEW_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_52_cdr_new_sec_acc_ctrl_man_clear_on_read_attr == SERDES_LANE_CDR_NEW_LANE3_REG_52_CDR_NEW_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_52_cdr_new_sec_acc_ctrl_man_self_clear_attr == SERDES_LANE_CDR_NEW_LANE3_REG_52_CDR_NEW_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_52_cdr_new_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_52_cdr_new_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_52_cdr_new_sec_acc_ctrl_soft_reset_n_attr == SERDES_LANE_CDR_NEW_LANE3_REG_52_CDR_NEW_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_52_cdr_new_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_53_cdr_new_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_53_cdr_new_reg2probe_en_attr == SERDES_LANE_CDR_NEW_LANE3_REG_53_CDR_NEW_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_5_cfg_cdr_state_ovrd_en_attr == SERDES_LANE_CDR_NEW_LANE3_REG_5_CFG_CDR_STATE_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_5_cfg_cdr_state_ovrd_val_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_5_cfg_dcocoarse_ovrd_attr == SERDES_LANE_CDR_NEW_LANE3_REG_5_CFG_DCOCOARSE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_5_cfg_dcocoarse_val_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_5_coarse_ppm_lock_th_attr == 12'd250
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_5_skip_coarse_calib_attr == SERDES_LANE_CDR_NEW_LANE3_REG_5_SKIP_COARSE_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_5_skip_fine_calib_attr == SERDES_LANE_CDR_NEW_LANE3_REG_5_SKIP_FINE_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_6_bb_pfd_sample_negedge_attr == SERDES_LANE_CDR_NEW_LANE3_REG_6_BB_PFD_SAMPLE_NEGEDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_6_cdr_pfd_en_force_en_attr == SERDES_LANE_CDR_NEW_LANE3_REG_6_CDR_PFD_EN_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_6_cdr_pfd_en_force_val_attr == SERDES_LANE_CDR_NEW_LANE3_REG_6_CDR_PFD_EN_FORCE_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_6_cfg_cdr_bb_pfd_step_attr == 9'd207
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_6_cfg_time2tune_fine_cal_attr == 16'd400
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_7_cfg_analog_dco_cvar_strb_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_7_cfg_cvar_trim_dcoupdate_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_7_cfg_cvar_trim_state_ovrd_en_attr == SERDES_LANE_CDR_NEW_LANE3_REG_7_CFG_CVAR_TRIM_STATE_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_7_cfg_cvar_trim_state_ovrd_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_7_dco_cvar_force_mode_ctrl_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_8_cdr_coarse_dac_sel_init_en_attr == SERDES_LANE_CDR_NEW_LANE3_REG_8_CDR_COARSE_DAC_SEL_INIT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_8_csr_coarse_dac_sel_init_attr == 8'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_cdr_new_lane3_reg_9_cdr_prop_thrs_attr == 28'd63409921
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state10_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state11_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state12_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state13_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state14_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state15_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state6_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state8_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state9_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_101_cfg_lane_tx_prbs_ssprq_seed_state0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_101_cfg_lane_tx_prbs_ssprq_seed_state10_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_101_cfg_lane_tx_prbs_ssprq_seed_state11_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_101_cfg_lane_tx_prbs_ssprq_seed_state12_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_101_cfg_lane_tx_prbs_ssprq_seed_state13_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_101_cfg_lane_tx_prbs_ssprq_seed_state14_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_101_cfg_lane_tx_prbs_ssprq_seed_state15_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_101_cfg_lane_tx_prbs_ssprq_seed_state1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_101_cfg_lane_tx_prbs_ssprq_seed_state2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_101_cfg_lane_tx_prbs_ssprq_seed_state3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_101_cfg_lane_tx_prbs_ssprq_seed_state4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_101_cfg_lane_tx_prbs_ssprq_seed_state5_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_101_cfg_lane_tx_prbs_ssprq_seed_state6_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_101_cfg_lane_tx_prbs_ssprq_seed_state7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_101_cfg_lane_tx_prbs_ssprq_seed_state8_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_101_cfg_lane_tx_prbs_ssprq_seed_state9_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state0_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state10_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state11_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state1_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state2_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state3_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state4_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state5_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state6_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state7_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state8_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE8_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state9_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_102_cfg_lane_tx_prbs_ssprq_inv_state0_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_102_cfg_lane_tx_prbs_ssprq_inv_state10_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE10_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_102_cfg_lane_tx_prbs_ssprq_inv_state11_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE11_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_102_cfg_lane_tx_prbs_ssprq_inv_state12_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_102_cfg_lane_tx_prbs_ssprq_inv_state13_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_102_cfg_lane_tx_prbs_ssprq_inv_state14_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_102_cfg_lane_tx_prbs_ssprq_inv_state15_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_102_cfg_lane_tx_prbs_ssprq_inv_state1_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_102_cfg_lane_tx_prbs_ssprq_inv_state2_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_102_cfg_lane_tx_prbs_ssprq_inv_state3_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_102_cfg_lane_tx_prbs_ssprq_inv_state4_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_102_cfg_lane_tx_prbs_ssprq_inv_state5_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE5_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_102_cfg_lane_tx_prbs_ssprq_inv_state6_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_102_cfg_lane_tx_prbs_ssprq_inv_state7_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_102_cfg_lane_tx_prbs_ssprq_inv_state8_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_102_cfg_lane_tx_prbs_ssprq_inv_state9_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE9_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_102_cfg_lane_tx_prbs_ssprq_max_state_attr == 4'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_103_cfg_lane_tx_prbs_ssprq_inv_last_state12_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_103_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_103_cfg_lane_tx_prbs_ssprq_inv_last_state13_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_103_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_103_cfg_lane_tx_prbs_ssprq_inv_last_state14_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_103_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_103_cfg_lane_tx_prbs_ssprq_inv_last_state15_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_103_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_105_dft_ctrl_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_105_dft_ctrl_sec_acc_ctrl_broadcast_mode_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_105_DFT_CTRL_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_105_dft_ctrl_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_105_dft_ctrl_sec_acc_ctrl_field_mask_write_en_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_105_DFT_CTRL_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_105_dft_ctrl_sec_acc_ctrl_load_preset_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_105_DFT_CTRL_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_105_dft_ctrl_sec_acc_ctrl_man_clear_on_read_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_105_DFT_CTRL_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_105_dft_ctrl_sec_acc_ctrl_man_self_clear_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_105_DFT_CTRL_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_105_dft_ctrl_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_105_dft_ctrl_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_105_dft_ctrl_sec_acc_ctrl_soft_reset_n_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_105_DFT_CTRL_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_105_dft_ctrl_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_106_dft_ctrl_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_106_dft_ctrl_reg2probe_en_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_106_DFT_CTRL_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_107_cfg_cond_hist_en_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_107_CFG_COND_HIST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_107_cfg_cond_hist_ui_delay_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_107_cfg_hist_delayed_dfe_data_cond_ignore_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_107_CFG_HIST_DELAYED_DFE_DATA_COND_IGNORE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_107_cfg_hist_delayed_dfe_data_cond_val_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_107_cfg_hist_selected_dfe_data_cond_ignore_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_107_CFG_HIST_SELECTED_DFE_DATA_COND_IGNORE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_107_cfg_hist_selected_dfe_data_cond_val_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_107_cfg_hist_selected_ui_data_sel_force_en_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_107_CFG_HIST_SELECTED_UI_DATA_SEL_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_107_cfg_hist_selected_ui_data_sel_force_val_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_107_cfg_hist_selected_ui_level_sample_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_107_cfg_ui_sel_offset_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_108_cfg_hist_tigger_voltage_lvl_high_limit_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_108_cfg_hist_tigger_voltage_lvl_low_limit_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_10_cfg_hist_ui_sel_cnt_end_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_10_cfg_hist_ui_sel_cnt_start_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_10_cfg_hist_ui_sel_cnt_step_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_11_cfg_128ui_rolling_cnt_limit_attr == 32'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_12_cfg_idx_cntr_force_en_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_12_CFG_IDX_CNTR_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_12_cfg_idx_cntr_force_val_attr == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_13_cfg_128ui_next_idx_force_en_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_13_CFG_128UI_NEXT_IDX_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_13_cfg_128ui_next_idx_force_val_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_13_CFG_128UI_NEXT_IDX_FORCE_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_13_cfg_128ui_rolling_cnt_en_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_13_CFG_128UI_ROLLING_CNT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_13_cfg_128ui_samp_idx_step_attr == 8'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_13_cfg_128ui_samp_now_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_13_CFG_128UI_SAMP_NOW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_13_cfg_128ui_to_fifo_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_13_cfg_128ui_to_fifo_stage_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_173_cfg_hist_event_cnt_lim_lsb_attr == 32'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_174_cfg_hist_event_cnt_lim_msb_attr == 32'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_1_cfg_dft_sar_valid_low_stick_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_1_CFG_DFT_SAR_VALID_LOW_STICK_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_1_cfg_dft_sar_valid_sticky_clr_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_1_CFG_DFT_SAR_VALID_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_1_cfg_sar_sat_full_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_1_cfg_sar_sat_th_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_1_cfg_sar_val_window_sar_sel_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_1_cfg_val_window_attr == 11'd2047
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_43_cfg_pat_detect_align_dly_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_43_cfg_pat_detect_unalign_dly_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_44_cfg_pat_detect_align_done_sticky_en_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_44_CFG_PAT_DETECT_ALIGN_DONE_STICKY_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_44_cfg_pat_detect_compare_on_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_44_CFG_PAT_DETECT_COMPARE_ON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_44_cfg_pat_detect_cyc_for_align_search_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_44_cfg_pat_detect_en_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_44_CFG_PAT_DETECT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_44_cfg_pat_detect_pat_comp_place_in_period_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_44_cfg_pat_detect_pat_period_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_45_cfg_pat_detect_start_detect_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_45_CFG_PAT_DETECT_START_DETECT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_46_cfg_pat_detect_exp_pat0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_47_cfg_pat_detect_exp_pat1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_48_cfg_pat_detect_exp_pat2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_49_cfg_pat_detect_exp_pat3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_51_cfg_pat_detect_comp_mask_lsb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_52_cfg_pat_detect_comp_mask_msb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_53_cfg_pat_detect_probe_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_54_cfg_ber_count_force_cnt_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_54_CFG_BER_COUNT_FORCE_CNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_54_cfg_ber_hist_error_counter_clr_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_54_CFG_BER_HIST_ERROR_COUNTER_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_54_cfg_ber_hist_error_counter_en_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_54_CFG_BER_HIST_ERROR_COUNTER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_54_cfg_dft_ber_count_en_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_54_CFG_DFT_BER_COUNT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_54_cfg_dft_ber_count_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_54_cfg_dft_rx_force_lock_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_54_CFG_DFT_RX_FORCE_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_54_cfg_dft_rx_lock_dly_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_54_cfg_dft_rx_lock_sticky_en_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_54_CFG_DFT_RX_LOCK_STICKY_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_54_cfg_dft_rx_unlock_dly_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_55_cfg_dft_ber_clear_c_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_55_CFG_DFT_BER_CLEAR_C_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_55_cfg_dft_ber_start_c_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_55_CFG_DFT_BER_START_C_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_55_cfg_dft_ber_stop_c_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_55_CFG_DFT_BER_STOP_C_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_56_cfg_dft_ber_error_mask_0_31_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_57_cfg_dft_ber_error_mask_32_63_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_58_cfg_ber_symb_cnt_limit_lsb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_59_cfg_ber_symb_cnt_limit_msb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_75_cfg_dft_rx_prbs_common_en_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_75_CFG_DFT_RX_PRBS_COMMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_75_cfg_dft_rx_prbs_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_75_cfg_rx_dft_data_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_76_cfg_lane_tx_prbs_en_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_76_CFG_LANE_TX_PRBS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_76_cfg_lane_tx_prbs_mode_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_76_cfg_lane_tx_prbs_seed_high_attr == 26'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_76_cfg_lane_tx_prbs_ssprq_en_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_76_CFG_LANE_TX_PRBS_SSPRQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_77_cfg_lane_tx_prbs_seed_low_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_78_cfg_lane_tx_prbs_init_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_78_CFG_LANE_TX_PRBS_INIT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_79_cfg_prbs_mask_lsb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_80_cfg_prbs_mask_msb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_81_cfg_tx_pat_en_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_81_CFG_TX_PAT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_81_cfg_tx_pat_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_81_cfg_tx_pat_sp_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_82_cfg_tx_pat_load_line_data_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_83_cfg_tx_pat_load_pulse_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_83_CFG_TX_PAT_LOAD_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_84_cfg_clear_ppm_counters_sc_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_84_CFG_CLEAR_PPM_COUNTERS_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_84_cfg_ppm_raw_conter_restart_sc_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_84_CFG_PPM_RAW_CONTER_RESTART_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_84_cfg_stop_ppm_meters_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_84_CFG_STOP_PPM_METERS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_85_cfg_ppm_counter_th_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_89_cfg_dft_ber_error_mask_64_95_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_90_cfg_dft_ber_error_mask_96_127_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_91_cfg_bi_chk_en_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_91_CFG_BI_CHK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_91_cfg_bi_symbol_count_stop_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_91_CFG_BI_SYMBOL_COUNT_STOP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_91_cfg_bi_toggle_limit_attr == 28'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_94_cfg_lane_tx_prbs_ssprq_seed0_attr == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_95_cfg_lane_tx_prbs_ssprq_seed1_attr == 32'd872497143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_96_cfg_lane_tx_prbs_ssprq_seed2_attr == 32'd214748364
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_97_cfg_lane_tx_prbs_ssprq_seed3_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_98_cfg_lane_tx_prbs_ssprq_cnt0_attr == 16'd10924
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_98_cfg_lane_tx_prbs_ssprq_cnt1_attr == 16'd10922
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_99_cfg_lane_tx_prbs_ssprq_cnt2_attr == 16'd10923
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_99_cfg_lane_tx_prbs_ssprq_cnt3_attr == 16'd10921
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_9_cfg_hist_adc_consider_valid_bit_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_9_CFG_HIST_ADC_CONSIDER_VALID_BIT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_9_cfg_hist_enable_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_9_CFG_HIST_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_9_cfg_hist_free_running_event_cnt_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_9_CFG_HIST_FREE_RUNNING_EVENT_CNT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_9_cfg_hist_prbs_seed_attr == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_9_cfg_hist_reset_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_9_CFG_HIST_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_9_cfg_hist_source_mux_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_9_cfg_hist_start_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_9_cfg_hist_stop_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_9_cfg_hist_stop_event_cnt_at_bin_max_attr == SERDES_LANE_DFT_CTRL_LANE0_REG_9_CFG_HIST_STOP_EVENT_CNT_AT_BIN_MAX_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_9_cfg_hist_ui_sel_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane0_reg_9_cfg_hist_ui_sel_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state10_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state11_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state12_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state13_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state14_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state15_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state6_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state8_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state9_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_101_cfg_lane_tx_prbs_ssprq_seed_state0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_101_cfg_lane_tx_prbs_ssprq_seed_state10_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_101_cfg_lane_tx_prbs_ssprq_seed_state11_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_101_cfg_lane_tx_prbs_ssprq_seed_state12_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_101_cfg_lane_tx_prbs_ssprq_seed_state13_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_101_cfg_lane_tx_prbs_ssprq_seed_state14_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_101_cfg_lane_tx_prbs_ssprq_seed_state15_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_101_cfg_lane_tx_prbs_ssprq_seed_state1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_101_cfg_lane_tx_prbs_ssprq_seed_state2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_101_cfg_lane_tx_prbs_ssprq_seed_state3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_101_cfg_lane_tx_prbs_ssprq_seed_state4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_101_cfg_lane_tx_prbs_ssprq_seed_state5_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_101_cfg_lane_tx_prbs_ssprq_seed_state6_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_101_cfg_lane_tx_prbs_ssprq_seed_state7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_101_cfg_lane_tx_prbs_ssprq_seed_state8_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_101_cfg_lane_tx_prbs_ssprq_seed_state9_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state0_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state10_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state11_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state1_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state2_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state3_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state4_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state5_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state6_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state7_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state8_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE8_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state9_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_102_cfg_lane_tx_prbs_ssprq_inv_state0_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_102_cfg_lane_tx_prbs_ssprq_inv_state10_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE10_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_102_cfg_lane_tx_prbs_ssprq_inv_state11_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE11_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_102_cfg_lane_tx_prbs_ssprq_inv_state12_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_102_cfg_lane_tx_prbs_ssprq_inv_state13_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_102_cfg_lane_tx_prbs_ssprq_inv_state14_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_102_cfg_lane_tx_prbs_ssprq_inv_state15_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_102_cfg_lane_tx_prbs_ssprq_inv_state1_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_102_cfg_lane_tx_prbs_ssprq_inv_state2_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_102_cfg_lane_tx_prbs_ssprq_inv_state3_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_102_cfg_lane_tx_prbs_ssprq_inv_state4_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_102_cfg_lane_tx_prbs_ssprq_inv_state5_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE5_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_102_cfg_lane_tx_prbs_ssprq_inv_state6_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_102_cfg_lane_tx_prbs_ssprq_inv_state7_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_102_cfg_lane_tx_prbs_ssprq_inv_state8_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_102_cfg_lane_tx_prbs_ssprq_inv_state9_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE9_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_102_cfg_lane_tx_prbs_ssprq_max_state_attr == 4'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_103_cfg_lane_tx_prbs_ssprq_inv_last_state12_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_103_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_103_cfg_lane_tx_prbs_ssprq_inv_last_state13_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_103_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_103_cfg_lane_tx_prbs_ssprq_inv_last_state14_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_103_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_103_cfg_lane_tx_prbs_ssprq_inv_last_state15_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_103_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_105_dft_ctrl_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_105_dft_ctrl_sec_acc_ctrl_broadcast_mode_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_105_DFT_CTRL_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_105_dft_ctrl_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_105_dft_ctrl_sec_acc_ctrl_field_mask_write_en_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_105_DFT_CTRL_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_105_dft_ctrl_sec_acc_ctrl_load_preset_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_105_DFT_CTRL_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_105_dft_ctrl_sec_acc_ctrl_man_clear_on_read_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_105_DFT_CTRL_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_105_dft_ctrl_sec_acc_ctrl_man_self_clear_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_105_DFT_CTRL_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_105_dft_ctrl_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_105_dft_ctrl_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_105_dft_ctrl_sec_acc_ctrl_soft_reset_n_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_105_DFT_CTRL_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_105_dft_ctrl_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_106_dft_ctrl_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_106_dft_ctrl_reg2probe_en_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_106_DFT_CTRL_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_107_cfg_cond_hist_en_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_107_CFG_COND_HIST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_107_cfg_cond_hist_ui_delay_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_107_cfg_hist_delayed_dfe_data_cond_ignore_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_107_CFG_HIST_DELAYED_DFE_DATA_COND_IGNORE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_107_cfg_hist_delayed_dfe_data_cond_val_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_107_cfg_hist_selected_dfe_data_cond_ignore_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_107_CFG_HIST_SELECTED_DFE_DATA_COND_IGNORE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_107_cfg_hist_selected_dfe_data_cond_val_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_107_cfg_hist_selected_ui_data_sel_force_en_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_107_CFG_HIST_SELECTED_UI_DATA_SEL_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_107_cfg_hist_selected_ui_data_sel_force_val_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_107_cfg_hist_selected_ui_level_sample_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_107_cfg_ui_sel_offset_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_108_cfg_hist_tigger_voltage_lvl_high_limit_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_108_cfg_hist_tigger_voltage_lvl_low_limit_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_10_cfg_hist_ui_sel_cnt_end_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_10_cfg_hist_ui_sel_cnt_start_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_10_cfg_hist_ui_sel_cnt_step_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_11_cfg_128ui_rolling_cnt_limit_attr == 32'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_12_cfg_idx_cntr_force_en_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_12_CFG_IDX_CNTR_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_12_cfg_idx_cntr_force_val_attr == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_13_cfg_128ui_next_idx_force_en_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_13_CFG_128UI_NEXT_IDX_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_13_cfg_128ui_next_idx_force_val_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_13_CFG_128UI_NEXT_IDX_FORCE_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_13_cfg_128ui_rolling_cnt_en_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_13_CFG_128UI_ROLLING_CNT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_13_cfg_128ui_samp_idx_step_attr == 8'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_13_cfg_128ui_samp_now_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_13_CFG_128UI_SAMP_NOW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_13_cfg_128ui_to_fifo_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_13_cfg_128ui_to_fifo_stage_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_173_cfg_hist_event_cnt_lim_lsb_attr == 32'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_174_cfg_hist_event_cnt_lim_msb_attr == 32'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_1_cfg_dft_sar_valid_low_stick_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_1_CFG_DFT_SAR_VALID_LOW_STICK_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_1_cfg_dft_sar_valid_sticky_clr_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_1_CFG_DFT_SAR_VALID_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_1_cfg_sar_sat_full_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_1_cfg_sar_sat_th_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_1_cfg_sar_val_window_sar_sel_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_1_cfg_val_window_attr == 11'd2047
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_43_cfg_pat_detect_align_dly_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_43_cfg_pat_detect_unalign_dly_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_44_cfg_pat_detect_align_done_sticky_en_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_44_CFG_PAT_DETECT_ALIGN_DONE_STICKY_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_44_cfg_pat_detect_compare_on_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_44_CFG_PAT_DETECT_COMPARE_ON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_44_cfg_pat_detect_cyc_for_align_search_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_44_cfg_pat_detect_en_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_44_CFG_PAT_DETECT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_44_cfg_pat_detect_pat_comp_place_in_period_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_44_cfg_pat_detect_pat_period_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_45_cfg_pat_detect_start_detect_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_45_CFG_PAT_DETECT_START_DETECT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_46_cfg_pat_detect_exp_pat0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_47_cfg_pat_detect_exp_pat1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_48_cfg_pat_detect_exp_pat2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_49_cfg_pat_detect_exp_pat3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_51_cfg_pat_detect_comp_mask_lsb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_52_cfg_pat_detect_comp_mask_msb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_53_cfg_pat_detect_probe_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_54_cfg_ber_count_force_cnt_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_54_CFG_BER_COUNT_FORCE_CNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_54_cfg_ber_hist_error_counter_clr_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_54_CFG_BER_HIST_ERROR_COUNTER_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_54_cfg_ber_hist_error_counter_en_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_54_CFG_BER_HIST_ERROR_COUNTER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_54_cfg_dft_ber_count_en_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_54_CFG_DFT_BER_COUNT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_54_cfg_dft_ber_count_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_54_cfg_dft_rx_force_lock_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_54_CFG_DFT_RX_FORCE_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_54_cfg_dft_rx_lock_dly_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_54_cfg_dft_rx_lock_sticky_en_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_54_CFG_DFT_RX_LOCK_STICKY_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_54_cfg_dft_rx_unlock_dly_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_55_cfg_dft_ber_clear_c_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_55_CFG_DFT_BER_CLEAR_C_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_55_cfg_dft_ber_start_c_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_55_CFG_DFT_BER_START_C_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_55_cfg_dft_ber_stop_c_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_55_CFG_DFT_BER_STOP_C_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_56_cfg_dft_ber_error_mask_0_31_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_57_cfg_dft_ber_error_mask_32_63_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_58_cfg_ber_symb_cnt_limit_lsb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_59_cfg_ber_symb_cnt_limit_msb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_75_cfg_dft_rx_prbs_common_en_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_75_CFG_DFT_RX_PRBS_COMMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_75_cfg_dft_rx_prbs_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_75_cfg_rx_dft_data_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_76_cfg_lane_tx_prbs_en_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_76_CFG_LANE_TX_PRBS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_76_cfg_lane_tx_prbs_mode_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_76_cfg_lane_tx_prbs_seed_high_attr == 26'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_76_cfg_lane_tx_prbs_ssprq_en_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_76_CFG_LANE_TX_PRBS_SSPRQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_77_cfg_lane_tx_prbs_seed_low_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_78_cfg_lane_tx_prbs_init_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_78_CFG_LANE_TX_PRBS_INIT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_79_cfg_prbs_mask_lsb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_80_cfg_prbs_mask_msb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_81_cfg_tx_pat_en_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_81_CFG_TX_PAT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_81_cfg_tx_pat_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_81_cfg_tx_pat_sp_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_82_cfg_tx_pat_load_line_data_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_83_cfg_tx_pat_load_pulse_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_83_CFG_TX_PAT_LOAD_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_84_cfg_clear_ppm_counters_sc_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_84_CFG_CLEAR_PPM_COUNTERS_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_84_cfg_ppm_raw_conter_restart_sc_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_84_CFG_PPM_RAW_CONTER_RESTART_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_84_cfg_stop_ppm_meters_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_84_CFG_STOP_PPM_METERS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_85_cfg_ppm_counter_th_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_89_cfg_dft_ber_error_mask_64_95_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_90_cfg_dft_ber_error_mask_96_127_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_91_cfg_bi_chk_en_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_91_CFG_BI_CHK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_91_cfg_bi_symbol_count_stop_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_91_CFG_BI_SYMBOL_COUNT_STOP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_91_cfg_bi_toggle_limit_attr == 28'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_94_cfg_lane_tx_prbs_ssprq_seed0_attr == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_95_cfg_lane_tx_prbs_ssprq_seed1_attr == 32'd872497143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_96_cfg_lane_tx_prbs_ssprq_seed2_attr == 32'd214748364
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_97_cfg_lane_tx_prbs_ssprq_seed3_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_98_cfg_lane_tx_prbs_ssprq_cnt0_attr == 16'd10924
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_98_cfg_lane_tx_prbs_ssprq_cnt1_attr == 16'd10922
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_99_cfg_lane_tx_prbs_ssprq_cnt2_attr == 16'd10923
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_99_cfg_lane_tx_prbs_ssprq_cnt3_attr == 16'd10921
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_9_cfg_hist_adc_consider_valid_bit_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_9_CFG_HIST_ADC_CONSIDER_VALID_BIT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_9_cfg_hist_enable_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_9_CFG_HIST_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_9_cfg_hist_free_running_event_cnt_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_9_CFG_HIST_FREE_RUNNING_EVENT_CNT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_9_cfg_hist_prbs_seed_attr == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_9_cfg_hist_reset_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_9_CFG_HIST_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_9_cfg_hist_source_mux_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_9_cfg_hist_start_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_9_cfg_hist_stop_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_9_cfg_hist_stop_event_cnt_at_bin_max_attr == SERDES_LANE_DFT_CTRL_LANE1_REG_9_CFG_HIST_STOP_EVENT_CNT_AT_BIN_MAX_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_9_cfg_hist_ui_sel_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane1_reg_9_cfg_hist_ui_sel_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state10_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state11_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state12_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state13_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state14_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state15_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state6_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state8_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state9_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_101_cfg_lane_tx_prbs_ssprq_seed_state0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_101_cfg_lane_tx_prbs_ssprq_seed_state10_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_101_cfg_lane_tx_prbs_ssprq_seed_state11_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_101_cfg_lane_tx_prbs_ssprq_seed_state12_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_101_cfg_lane_tx_prbs_ssprq_seed_state13_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_101_cfg_lane_tx_prbs_ssprq_seed_state14_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_101_cfg_lane_tx_prbs_ssprq_seed_state15_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_101_cfg_lane_tx_prbs_ssprq_seed_state1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_101_cfg_lane_tx_prbs_ssprq_seed_state2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_101_cfg_lane_tx_prbs_ssprq_seed_state3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_101_cfg_lane_tx_prbs_ssprq_seed_state4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_101_cfg_lane_tx_prbs_ssprq_seed_state5_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_101_cfg_lane_tx_prbs_ssprq_seed_state6_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_101_cfg_lane_tx_prbs_ssprq_seed_state7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_101_cfg_lane_tx_prbs_ssprq_seed_state8_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_101_cfg_lane_tx_prbs_ssprq_seed_state9_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state0_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state10_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state11_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state1_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state2_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state3_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state4_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state5_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state6_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state7_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state8_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE8_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state9_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_102_cfg_lane_tx_prbs_ssprq_inv_state0_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_102_cfg_lane_tx_prbs_ssprq_inv_state10_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE10_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_102_cfg_lane_tx_prbs_ssprq_inv_state11_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE11_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_102_cfg_lane_tx_prbs_ssprq_inv_state12_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_102_cfg_lane_tx_prbs_ssprq_inv_state13_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_102_cfg_lane_tx_prbs_ssprq_inv_state14_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_102_cfg_lane_tx_prbs_ssprq_inv_state15_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_102_cfg_lane_tx_prbs_ssprq_inv_state1_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_102_cfg_lane_tx_prbs_ssprq_inv_state2_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_102_cfg_lane_tx_prbs_ssprq_inv_state3_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_102_cfg_lane_tx_prbs_ssprq_inv_state4_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_102_cfg_lane_tx_prbs_ssprq_inv_state5_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE5_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_102_cfg_lane_tx_prbs_ssprq_inv_state6_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_102_cfg_lane_tx_prbs_ssprq_inv_state7_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_102_cfg_lane_tx_prbs_ssprq_inv_state8_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_102_cfg_lane_tx_prbs_ssprq_inv_state9_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE9_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_102_cfg_lane_tx_prbs_ssprq_max_state_attr == 4'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_103_cfg_lane_tx_prbs_ssprq_inv_last_state12_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_103_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_103_cfg_lane_tx_prbs_ssprq_inv_last_state13_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_103_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_103_cfg_lane_tx_prbs_ssprq_inv_last_state14_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_103_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_103_cfg_lane_tx_prbs_ssprq_inv_last_state15_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_103_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_105_dft_ctrl_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_105_dft_ctrl_sec_acc_ctrl_broadcast_mode_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_105_DFT_CTRL_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_105_dft_ctrl_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_105_dft_ctrl_sec_acc_ctrl_field_mask_write_en_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_105_DFT_CTRL_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_105_dft_ctrl_sec_acc_ctrl_load_preset_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_105_DFT_CTRL_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_105_dft_ctrl_sec_acc_ctrl_man_clear_on_read_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_105_DFT_CTRL_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_105_dft_ctrl_sec_acc_ctrl_man_self_clear_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_105_DFT_CTRL_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_105_dft_ctrl_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_105_dft_ctrl_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_105_dft_ctrl_sec_acc_ctrl_soft_reset_n_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_105_DFT_CTRL_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_105_dft_ctrl_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_106_dft_ctrl_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_106_dft_ctrl_reg2probe_en_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_106_DFT_CTRL_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_107_cfg_cond_hist_en_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_107_CFG_COND_HIST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_107_cfg_cond_hist_ui_delay_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_107_cfg_hist_delayed_dfe_data_cond_ignore_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_107_CFG_HIST_DELAYED_DFE_DATA_COND_IGNORE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_107_cfg_hist_delayed_dfe_data_cond_val_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_107_cfg_hist_selected_dfe_data_cond_ignore_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_107_CFG_HIST_SELECTED_DFE_DATA_COND_IGNORE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_107_cfg_hist_selected_dfe_data_cond_val_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_107_cfg_hist_selected_ui_data_sel_force_en_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_107_CFG_HIST_SELECTED_UI_DATA_SEL_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_107_cfg_hist_selected_ui_data_sel_force_val_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_107_cfg_hist_selected_ui_level_sample_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_107_cfg_ui_sel_offset_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_108_cfg_hist_tigger_voltage_lvl_high_limit_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_108_cfg_hist_tigger_voltage_lvl_low_limit_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_10_cfg_hist_ui_sel_cnt_end_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_10_cfg_hist_ui_sel_cnt_start_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_10_cfg_hist_ui_sel_cnt_step_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_11_cfg_128ui_rolling_cnt_limit_attr == 32'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_12_cfg_idx_cntr_force_en_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_12_CFG_IDX_CNTR_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_12_cfg_idx_cntr_force_val_attr == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_13_cfg_128ui_next_idx_force_en_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_13_CFG_128UI_NEXT_IDX_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_13_cfg_128ui_next_idx_force_val_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_13_CFG_128UI_NEXT_IDX_FORCE_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_13_cfg_128ui_rolling_cnt_en_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_13_CFG_128UI_ROLLING_CNT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_13_cfg_128ui_samp_idx_step_attr == 8'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_13_cfg_128ui_samp_now_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_13_CFG_128UI_SAMP_NOW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_13_cfg_128ui_to_fifo_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_13_cfg_128ui_to_fifo_stage_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_173_cfg_hist_event_cnt_lim_lsb_attr == 32'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_174_cfg_hist_event_cnt_lim_msb_attr == 32'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_1_cfg_dft_sar_valid_low_stick_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_1_CFG_DFT_SAR_VALID_LOW_STICK_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_1_cfg_dft_sar_valid_sticky_clr_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_1_CFG_DFT_SAR_VALID_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_1_cfg_sar_sat_full_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_1_cfg_sar_sat_th_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_1_cfg_sar_val_window_sar_sel_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_1_cfg_val_window_attr == 11'd2047
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_43_cfg_pat_detect_align_dly_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_43_cfg_pat_detect_unalign_dly_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_44_cfg_pat_detect_align_done_sticky_en_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_44_CFG_PAT_DETECT_ALIGN_DONE_STICKY_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_44_cfg_pat_detect_compare_on_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_44_CFG_PAT_DETECT_COMPARE_ON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_44_cfg_pat_detect_cyc_for_align_search_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_44_cfg_pat_detect_en_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_44_CFG_PAT_DETECT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_44_cfg_pat_detect_pat_comp_place_in_period_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_44_cfg_pat_detect_pat_period_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_45_cfg_pat_detect_start_detect_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_45_CFG_PAT_DETECT_START_DETECT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_46_cfg_pat_detect_exp_pat0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_47_cfg_pat_detect_exp_pat1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_48_cfg_pat_detect_exp_pat2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_49_cfg_pat_detect_exp_pat3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_51_cfg_pat_detect_comp_mask_lsb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_52_cfg_pat_detect_comp_mask_msb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_53_cfg_pat_detect_probe_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_54_cfg_ber_count_force_cnt_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_54_CFG_BER_COUNT_FORCE_CNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_54_cfg_ber_hist_error_counter_clr_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_54_CFG_BER_HIST_ERROR_COUNTER_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_54_cfg_ber_hist_error_counter_en_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_54_CFG_BER_HIST_ERROR_COUNTER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_54_cfg_dft_ber_count_en_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_54_CFG_DFT_BER_COUNT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_54_cfg_dft_ber_count_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_54_cfg_dft_rx_force_lock_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_54_CFG_DFT_RX_FORCE_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_54_cfg_dft_rx_lock_dly_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_54_cfg_dft_rx_lock_sticky_en_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_54_CFG_DFT_RX_LOCK_STICKY_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_54_cfg_dft_rx_unlock_dly_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_55_cfg_dft_ber_clear_c_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_55_CFG_DFT_BER_CLEAR_C_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_55_cfg_dft_ber_start_c_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_55_CFG_DFT_BER_START_C_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_55_cfg_dft_ber_stop_c_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_55_CFG_DFT_BER_STOP_C_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_56_cfg_dft_ber_error_mask_0_31_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_57_cfg_dft_ber_error_mask_32_63_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_58_cfg_ber_symb_cnt_limit_lsb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_59_cfg_ber_symb_cnt_limit_msb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_75_cfg_dft_rx_prbs_common_en_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_75_CFG_DFT_RX_PRBS_COMMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_75_cfg_dft_rx_prbs_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_75_cfg_rx_dft_data_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_76_cfg_lane_tx_prbs_en_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_76_CFG_LANE_TX_PRBS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_76_cfg_lane_tx_prbs_mode_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_76_cfg_lane_tx_prbs_seed_high_attr == 26'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_76_cfg_lane_tx_prbs_ssprq_en_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_76_CFG_LANE_TX_PRBS_SSPRQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_77_cfg_lane_tx_prbs_seed_low_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_78_cfg_lane_tx_prbs_init_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_78_CFG_LANE_TX_PRBS_INIT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_79_cfg_prbs_mask_lsb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_80_cfg_prbs_mask_msb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_81_cfg_tx_pat_en_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_81_CFG_TX_PAT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_81_cfg_tx_pat_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_81_cfg_tx_pat_sp_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_82_cfg_tx_pat_load_line_data_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_83_cfg_tx_pat_load_pulse_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_83_CFG_TX_PAT_LOAD_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_84_cfg_clear_ppm_counters_sc_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_84_CFG_CLEAR_PPM_COUNTERS_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_84_cfg_ppm_raw_conter_restart_sc_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_84_CFG_PPM_RAW_CONTER_RESTART_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_84_cfg_stop_ppm_meters_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_84_CFG_STOP_PPM_METERS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_85_cfg_ppm_counter_th_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_89_cfg_dft_ber_error_mask_64_95_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_90_cfg_dft_ber_error_mask_96_127_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_91_cfg_bi_chk_en_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_91_CFG_BI_CHK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_91_cfg_bi_symbol_count_stop_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_91_CFG_BI_SYMBOL_COUNT_STOP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_91_cfg_bi_toggle_limit_attr == 28'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_94_cfg_lane_tx_prbs_ssprq_seed0_attr == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_95_cfg_lane_tx_prbs_ssprq_seed1_attr == 32'd872497143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_96_cfg_lane_tx_prbs_ssprq_seed2_attr == 32'd214748364
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_97_cfg_lane_tx_prbs_ssprq_seed3_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_98_cfg_lane_tx_prbs_ssprq_cnt0_attr == 16'd10924
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_98_cfg_lane_tx_prbs_ssprq_cnt1_attr == 16'd10922
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_99_cfg_lane_tx_prbs_ssprq_cnt2_attr == 16'd10923
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_99_cfg_lane_tx_prbs_ssprq_cnt3_attr == 16'd10921
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_9_cfg_hist_adc_consider_valid_bit_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_9_CFG_HIST_ADC_CONSIDER_VALID_BIT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_9_cfg_hist_enable_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_9_CFG_HIST_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_9_cfg_hist_free_running_event_cnt_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_9_CFG_HIST_FREE_RUNNING_EVENT_CNT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_9_cfg_hist_prbs_seed_attr == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_9_cfg_hist_reset_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_9_CFG_HIST_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_9_cfg_hist_source_mux_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_9_cfg_hist_start_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_9_cfg_hist_stop_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_9_cfg_hist_stop_event_cnt_at_bin_max_attr == SERDES_LANE_DFT_CTRL_LANE2_REG_9_CFG_HIST_STOP_EVENT_CNT_AT_BIN_MAX_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_9_cfg_hist_ui_sel_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane2_reg_9_cfg_hist_ui_sel_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state10_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state11_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state12_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state13_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state14_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state15_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state6_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state8_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_100_cfg_lane_tx_prbs_ssprq_cnt_state9_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_101_cfg_lane_tx_prbs_ssprq_seed_state0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_101_cfg_lane_tx_prbs_ssprq_seed_state10_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_101_cfg_lane_tx_prbs_ssprq_seed_state11_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_101_cfg_lane_tx_prbs_ssprq_seed_state12_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_101_cfg_lane_tx_prbs_ssprq_seed_state13_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_101_cfg_lane_tx_prbs_ssprq_seed_state14_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_101_cfg_lane_tx_prbs_ssprq_seed_state15_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_101_cfg_lane_tx_prbs_ssprq_seed_state1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_101_cfg_lane_tx_prbs_ssprq_seed_state2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_101_cfg_lane_tx_prbs_ssprq_seed_state3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_101_cfg_lane_tx_prbs_ssprq_seed_state4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_101_cfg_lane_tx_prbs_ssprq_seed_state5_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_101_cfg_lane_tx_prbs_ssprq_seed_state6_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_101_cfg_lane_tx_prbs_ssprq_seed_state7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_101_cfg_lane_tx_prbs_ssprq_seed_state8_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_101_cfg_lane_tx_prbs_ssprq_seed_state9_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state0_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state10_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state11_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state1_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state2_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state3_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state4_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state5_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state6_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state7_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state8_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE8_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_102_cfg_lane_tx_prbs_ssprq_inv_last_state9_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_102_cfg_lane_tx_prbs_ssprq_inv_state0_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_102_cfg_lane_tx_prbs_ssprq_inv_state10_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE10_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_102_cfg_lane_tx_prbs_ssprq_inv_state11_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE11_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_102_cfg_lane_tx_prbs_ssprq_inv_state12_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_102_cfg_lane_tx_prbs_ssprq_inv_state13_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_102_cfg_lane_tx_prbs_ssprq_inv_state14_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_102_cfg_lane_tx_prbs_ssprq_inv_state15_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_102_cfg_lane_tx_prbs_ssprq_inv_state1_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_102_cfg_lane_tx_prbs_ssprq_inv_state2_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_102_cfg_lane_tx_prbs_ssprq_inv_state3_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_102_cfg_lane_tx_prbs_ssprq_inv_state4_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_102_cfg_lane_tx_prbs_ssprq_inv_state5_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE5_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_102_cfg_lane_tx_prbs_ssprq_inv_state6_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_102_cfg_lane_tx_prbs_ssprq_inv_state7_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_102_cfg_lane_tx_prbs_ssprq_inv_state8_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_102_cfg_lane_tx_prbs_ssprq_inv_state9_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_102_CFG_LANE_TX_PRBS_SSPRQ_INV_STATE9_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_102_cfg_lane_tx_prbs_ssprq_max_state_attr == 4'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_103_cfg_lane_tx_prbs_ssprq_inv_last_state12_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_103_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_103_cfg_lane_tx_prbs_ssprq_inv_last_state13_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_103_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_103_cfg_lane_tx_prbs_ssprq_inv_last_state14_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_103_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_103_cfg_lane_tx_prbs_ssprq_inv_last_state15_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_103_CFG_LANE_TX_PRBS_SSPRQ_INV_LAST_STATE15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_105_dft_ctrl_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_105_dft_ctrl_sec_acc_ctrl_broadcast_mode_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_105_DFT_CTRL_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_105_dft_ctrl_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_105_dft_ctrl_sec_acc_ctrl_field_mask_write_en_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_105_DFT_CTRL_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_105_dft_ctrl_sec_acc_ctrl_load_preset_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_105_DFT_CTRL_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_105_dft_ctrl_sec_acc_ctrl_man_clear_on_read_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_105_DFT_CTRL_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_105_dft_ctrl_sec_acc_ctrl_man_self_clear_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_105_DFT_CTRL_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_105_dft_ctrl_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_105_dft_ctrl_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_105_dft_ctrl_sec_acc_ctrl_soft_reset_n_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_105_DFT_CTRL_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_105_dft_ctrl_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_106_dft_ctrl_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_106_dft_ctrl_reg2probe_en_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_106_DFT_CTRL_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_107_cfg_cond_hist_en_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_107_CFG_COND_HIST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_107_cfg_cond_hist_ui_delay_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_107_cfg_hist_delayed_dfe_data_cond_ignore_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_107_CFG_HIST_DELAYED_DFE_DATA_COND_IGNORE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_107_cfg_hist_delayed_dfe_data_cond_val_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_107_cfg_hist_selected_dfe_data_cond_ignore_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_107_CFG_HIST_SELECTED_DFE_DATA_COND_IGNORE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_107_cfg_hist_selected_dfe_data_cond_val_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_107_cfg_hist_selected_ui_data_sel_force_en_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_107_CFG_HIST_SELECTED_UI_DATA_SEL_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_107_cfg_hist_selected_ui_data_sel_force_val_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_107_cfg_hist_selected_ui_level_sample_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_107_cfg_ui_sel_offset_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_108_cfg_hist_tigger_voltage_lvl_high_limit_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_108_cfg_hist_tigger_voltage_lvl_low_limit_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_10_cfg_hist_ui_sel_cnt_end_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_10_cfg_hist_ui_sel_cnt_start_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_10_cfg_hist_ui_sel_cnt_step_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_11_cfg_128ui_rolling_cnt_limit_attr == 32'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_12_cfg_idx_cntr_force_en_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_12_CFG_IDX_CNTR_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_12_cfg_idx_cntr_force_val_attr == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_13_cfg_128ui_next_idx_force_en_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_13_CFG_128UI_NEXT_IDX_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_13_cfg_128ui_next_idx_force_val_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_13_CFG_128UI_NEXT_IDX_FORCE_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_13_cfg_128ui_rolling_cnt_en_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_13_CFG_128UI_ROLLING_CNT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_13_cfg_128ui_samp_idx_step_attr == 8'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_13_cfg_128ui_samp_now_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_13_CFG_128UI_SAMP_NOW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_13_cfg_128ui_to_fifo_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_13_cfg_128ui_to_fifo_stage_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_173_cfg_hist_event_cnt_lim_lsb_attr == 32'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_174_cfg_hist_event_cnt_lim_msb_attr == 32'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_1_cfg_dft_sar_valid_low_stick_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_1_CFG_DFT_SAR_VALID_LOW_STICK_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_1_cfg_dft_sar_valid_sticky_clr_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_1_CFG_DFT_SAR_VALID_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_1_cfg_sar_sat_full_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_1_cfg_sar_sat_th_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_1_cfg_sar_val_window_sar_sel_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_1_cfg_val_window_attr == 11'd2047
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_43_cfg_pat_detect_align_dly_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_43_cfg_pat_detect_unalign_dly_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_44_cfg_pat_detect_align_done_sticky_en_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_44_CFG_PAT_DETECT_ALIGN_DONE_STICKY_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_44_cfg_pat_detect_compare_on_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_44_CFG_PAT_DETECT_COMPARE_ON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_44_cfg_pat_detect_cyc_for_align_search_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_44_cfg_pat_detect_en_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_44_CFG_PAT_DETECT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_44_cfg_pat_detect_pat_comp_place_in_period_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_44_cfg_pat_detect_pat_period_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_45_cfg_pat_detect_start_detect_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_45_CFG_PAT_DETECT_START_DETECT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_46_cfg_pat_detect_exp_pat0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_47_cfg_pat_detect_exp_pat1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_48_cfg_pat_detect_exp_pat2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_49_cfg_pat_detect_exp_pat3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_51_cfg_pat_detect_comp_mask_lsb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_52_cfg_pat_detect_comp_mask_msb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_53_cfg_pat_detect_probe_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_54_cfg_ber_count_force_cnt_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_54_CFG_BER_COUNT_FORCE_CNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_54_cfg_ber_hist_error_counter_clr_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_54_CFG_BER_HIST_ERROR_COUNTER_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_54_cfg_ber_hist_error_counter_en_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_54_CFG_BER_HIST_ERROR_COUNTER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_54_cfg_dft_ber_count_en_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_54_CFG_DFT_BER_COUNT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_54_cfg_dft_ber_count_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_54_cfg_dft_rx_force_lock_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_54_CFG_DFT_RX_FORCE_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_54_cfg_dft_rx_lock_dly_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_54_cfg_dft_rx_lock_sticky_en_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_54_CFG_DFT_RX_LOCK_STICKY_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_54_cfg_dft_rx_unlock_dly_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_55_cfg_dft_ber_clear_c_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_55_CFG_DFT_BER_CLEAR_C_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_55_cfg_dft_ber_start_c_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_55_CFG_DFT_BER_START_C_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_55_cfg_dft_ber_stop_c_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_55_CFG_DFT_BER_STOP_C_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_56_cfg_dft_ber_error_mask_0_31_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_57_cfg_dft_ber_error_mask_32_63_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_58_cfg_ber_symb_cnt_limit_lsb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_59_cfg_ber_symb_cnt_limit_msb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_75_cfg_dft_rx_prbs_common_en_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_75_CFG_DFT_RX_PRBS_COMMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_75_cfg_dft_rx_prbs_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_75_cfg_rx_dft_data_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_76_cfg_lane_tx_prbs_en_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_76_CFG_LANE_TX_PRBS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_76_cfg_lane_tx_prbs_mode_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_76_cfg_lane_tx_prbs_seed_high_attr == 26'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_76_cfg_lane_tx_prbs_ssprq_en_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_76_CFG_LANE_TX_PRBS_SSPRQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_77_cfg_lane_tx_prbs_seed_low_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_78_cfg_lane_tx_prbs_init_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_78_CFG_LANE_TX_PRBS_INIT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_79_cfg_prbs_mask_lsb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_80_cfg_prbs_mask_msb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_81_cfg_tx_pat_en_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_81_CFG_TX_PAT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_81_cfg_tx_pat_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_81_cfg_tx_pat_sp_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_82_cfg_tx_pat_load_line_data_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_83_cfg_tx_pat_load_pulse_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_83_CFG_TX_PAT_LOAD_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_84_cfg_clear_ppm_counters_sc_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_84_CFG_CLEAR_PPM_COUNTERS_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_84_cfg_ppm_raw_conter_restart_sc_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_84_CFG_PPM_RAW_CONTER_RESTART_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_84_cfg_stop_ppm_meters_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_84_CFG_STOP_PPM_METERS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_85_cfg_ppm_counter_th_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_89_cfg_dft_ber_error_mask_64_95_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_90_cfg_dft_ber_error_mask_96_127_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_91_cfg_bi_chk_en_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_91_CFG_BI_CHK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_91_cfg_bi_symbol_count_stop_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_91_CFG_BI_SYMBOL_COUNT_STOP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_91_cfg_bi_toggle_limit_attr == 28'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_94_cfg_lane_tx_prbs_ssprq_seed0_attr == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_95_cfg_lane_tx_prbs_ssprq_seed1_attr == 32'd872497143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_96_cfg_lane_tx_prbs_ssprq_seed2_attr == 32'd214748364
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_97_cfg_lane_tx_prbs_ssprq_seed3_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_98_cfg_lane_tx_prbs_ssprq_cnt0_attr == 16'd10924
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_98_cfg_lane_tx_prbs_ssprq_cnt1_attr == 16'd10922
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_99_cfg_lane_tx_prbs_ssprq_cnt2_attr == 16'd10923
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_99_cfg_lane_tx_prbs_ssprq_cnt3_attr == 16'd10921
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_9_cfg_hist_adc_consider_valid_bit_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_9_CFG_HIST_ADC_CONSIDER_VALID_BIT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_9_cfg_hist_enable_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_9_CFG_HIST_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_9_cfg_hist_free_running_event_cnt_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_9_CFG_HIST_FREE_RUNNING_EVENT_CNT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_9_cfg_hist_prbs_seed_attr == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_9_cfg_hist_reset_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_9_CFG_HIST_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_9_cfg_hist_source_mux_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_9_cfg_hist_start_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_9_cfg_hist_stop_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_9_cfg_hist_stop_event_cnt_at_bin_max_attr == SERDES_LANE_DFT_CTRL_LANE3_REG_9_CFG_HIST_STOP_EVENT_CNT_AT_BIN_MAX_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_9_cfg_hist_ui_sel_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dft_ctrl_lane3_reg_9_cfg_hist_ui_sel_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_10_dfe2_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_11_dfe3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_12_dfe4_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_13_dfe5_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_15_dfe_adapt_all_taps_en_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_15_DFE_ADAPT_ALL_TAPS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_17_dfe6_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_18_dfe7_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_19_dfe8_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_20_dsp_bit_swz_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_20_DSP_BIT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_20_dsp_d_swz_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_20_DSP_D_SWZ_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_20_dsp_en_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_20_DSP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_20_dsp_inner_d_swz_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_20_DSP_INNER_D_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_20_dsp_inner_m_swz_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_20_DSP_INNER_M_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_20_dsp_latch_dis_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_20_DSP_LATCH_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_20_dsp_m_swz_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_20_DSP_M_SWZ_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_20_ehm_tap_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_20_fine_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_20_FINE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_20_io_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_20_ofc_sar_lsb_inv_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_20_OFC_SAR_LSB_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_20_ofc_sar_lsb_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_20_pam_4_en_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_20_PAM_4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_20_vref_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_21_ehm_event_sign_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_21_EHM_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_21_ehm_sym1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_21_ehm_sym_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_21_ehm_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_22_dfe_tap11_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_22_dfe_tap12_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_22_dfe_tap13_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_22_dfe_tap14_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_22_dfe_tap15_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_23_agc_en_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_23_AGC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_23_dfe_adapt_en_0_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_23_DFE_ADAPT_EN_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_23_dfe_adapt_en_10_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_23_DFE_ADAPT_EN_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_23_dfe_adapt_en_11_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_23_DFE_ADAPT_EN_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_23_dfe_adapt_en_12_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_23_DFE_ADAPT_EN_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_23_dfe_adapt_en_13_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_23_DFE_ADAPT_EN_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_23_dfe_adapt_en_14_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_23_DFE_ADAPT_EN_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_23_dfe_adapt_en_15_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_23_DFE_ADAPT_EN_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_23_dfe_adapt_en_1_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_23_DFE_ADAPT_EN_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_23_dfe_adapt_en_2_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_23_DFE_ADAPT_EN_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_23_dfe_adapt_en_3_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_23_DFE_ADAPT_EN_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_23_dfe_adapt_en_4_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_23_DFE_ADAPT_EN_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_23_dfe_adapt_en_5_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_23_DFE_ADAPT_EN_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_23_dfe_adapt_en_6_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_23_DFE_ADAPT_EN_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_23_dfe_adapt_en_7_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_23_DFE_ADAPT_EN_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_23_dfe_adapt_en_8_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_23_DFE_ADAPT_EN_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_23_dfe_adapt_en_9_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_23_DFE_ADAPT_EN_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_23_gain_sar_en_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_23_GAIN_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_23_ofc_en_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_23_OFC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_23_ofc_lsb_sar_en_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_23_OFC_LSB_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_23_ofc_sar_en_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_23_power_save_en_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_23_POWER_SAVE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_23_res_isi_mes_en_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_23_RES_ISI_MES_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_23_vga_en_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_23_VGA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_23_x3_en_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_23_X3_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_24_dfe9_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_25_dfe10_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_26_dfe11_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_27_dfe12_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_28_dfe13_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_29_dfe14_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_2_agc_coarse_det_en_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_2_AGC_COARSE_DET_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_2_agc_d_sign_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_2_AGC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_30_dfe15_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_31_dfe16_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_32_d_dly_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_32_e_dly_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_32_phase_mask0_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_32_phase_mask1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_32_phase_mask2_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_32_phase_mask3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_32_phase_num_mask_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_32_swap_bot_en_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_32_SWAP_BOT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_32_swap_top_en_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_32_SWAP_TOP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_33_coarse_det_pol_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_33_COARSE_DET_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_33_joint_dfe_en_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_33_JOINT_DFE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_33_phase_cnt_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_34_gain_sar_sticky_clr1_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_34_GAIN_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_34_gain_sar_sticky_clr2_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_34_GAIN_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_34_gain_sar_sticky_clr3_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_34_GAIN_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_34_gain_sar_sticky_clr4_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_34_GAIN_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_34_gain_sar_sticky_clr5_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_34_GAIN_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_34_gain_sar_sticky_clr6_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_34_GAIN_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_34_gain_sar_sticky_clr7_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_34_GAIN_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_34_gain_sar_sticky_clr8_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_34_GAIN_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_34_sticky_clr_0_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_34_STICKY_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_34_sticky_clr_10_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_34_STICKY_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_34_sticky_clr_11_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_34_STICKY_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_34_sticky_clr_12_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_34_STICKY_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_34_sticky_clr_13_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_34_STICKY_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_34_sticky_clr_14_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_34_STICKY_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_34_sticky_clr_15_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_34_STICKY_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_34_sticky_clr_16_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_34_STICKY_CLR_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_34_sticky_clr_17_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_34_STICKY_CLR_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_34_sticky_clr_18_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_34_STICKY_CLR_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_34_sticky_clr_1_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_34_STICKY_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_34_sticky_clr_2_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_34_STICKY_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_34_sticky_clr_3_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_34_STICKY_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_34_sticky_clr_4_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_34_STICKY_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_34_sticky_clr_5_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_34_STICKY_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_34_sticky_clr_6_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_34_STICKY_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_34_sticky_clr_7_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_34_STICKY_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_34_sticky_clr_8_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_34_STICKY_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_34_sticky_clr_9_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_34_STICKY_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_34_vga_sticky_clr_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_34_VGA_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_34_x3_sticky_clr_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_34_X3_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_35_agc_acc_clr_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_35_AGC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_35_dfe_acc_clr_0_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_35_DFE_ACC_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_35_dfe_acc_clr_10_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_35_DFE_ACC_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_35_dfe_acc_clr_11_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_35_DFE_ACC_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_35_dfe_acc_clr_12_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_35_DFE_ACC_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_35_dfe_acc_clr_13_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_35_DFE_ACC_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_35_dfe_acc_clr_14_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_35_DFE_ACC_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_35_dfe_acc_clr_15_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_35_DFE_ACC_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_35_dfe_acc_clr_1_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_35_DFE_ACC_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_35_dfe_acc_clr_2_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_35_DFE_ACC_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_35_dfe_acc_clr_3_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_35_DFE_ACC_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_35_dfe_acc_clr_4_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_35_DFE_ACC_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_35_dfe_acc_clr_5_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_35_DFE_ACC_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_35_dfe_acc_clr_6_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_35_DFE_ACC_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_35_dfe_acc_clr_7_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_35_DFE_ACC_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_35_dfe_acc_clr_8_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_35_DFE_ACC_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_35_dfe_acc_clr_9_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_35_DFE_ACC_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_35_ehm_acc_clr_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_35_EHM_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_35_ofc_acc_clr_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_35_OFC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_35_vga_acc_clr_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_35_VGA_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_35_x3_acc_clr_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_35_X3_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_36_ofc_d_sign_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_36_OFC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_36_ofc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_36_ofc_event_sign_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_36_OFC_EVENT_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_37_ofc_th_attr == 20'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_38_agc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_38_agc_event_sign_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_38_AGC_EVENT_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_39_dfe1_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_39_dfe_event_sign_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_3_agc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_3_agc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_40_ehm_event_rate_lsb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_41_ehm_event_rate_msb_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_42_ofc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_42_ofc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_45_agc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_46_ofc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_47_dfe_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_48_err_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_49_err_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_4_agc_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_50_vga_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_51_vga_range_detect_comp_const_h_attr == 7'd126
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_51_vga_range_detect_comp_const_l_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_51_vga_range_detect_sub_const_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_51_vga_shift_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_51_vga_zero_pull_en_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_51_VGA_ZERO_PULL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_51_vga_zero_pull_factor_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_52_ofc_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_53_vga_stable_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_53_VGA_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_54_dfe_common_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_54_dfe_common_th_en_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_54_DFE_COMMON_TH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_55_ofc_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_55_ofc_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_55_ofc_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_55_ofc_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_55_ofc_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_56_ofc_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_56_ofc_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_56_ofc_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_57_ofc_lsb_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_58_ofc_lsb_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_58_ofc_lsb_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_58_ofc_lsb_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_58_ofc_lsb_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_58_ofc_lsb_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_59_ofc_lsb_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_59_ofc_lsb_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_59_ofc_lsb_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_5_dfe_d_sign_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_5_DFE_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_5_dfe_tap9_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_60_ofc_lsb_sar_acc_clr1_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_60_OFC_LSB_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_60_ofc_lsb_sar_acc_clr2_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_60_OFC_LSB_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_60_ofc_lsb_sar_acc_clr3_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_60_OFC_LSB_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_60_ofc_lsb_sar_acc_clr4_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_60_OFC_LSB_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_60_ofc_lsb_sar_acc_clr5_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_60_OFC_LSB_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_60_ofc_lsb_sar_acc_clr6_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_60_OFC_LSB_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_60_ofc_lsb_sar_acc_clr7_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_60_OFC_LSB_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_60_ofc_lsb_sar_acc_clr8_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_60_OFC_LSB_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_60_ofc_lsb_sar_sticky_clr1_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_60_OFC_LSB_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_60_ofc_lsb_sar_sticky_clr2_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_60_OFC_LSB_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_60_ofc_lsb_sar_sticky_clr3_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_60_OFC_LSB_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_60_ofc_lsb_sar_sticky_clr4_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_60_OFC_LSB_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_60_ofc_lsb_sar_sticky_clr5_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_60_OFC_LSB_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_60_ofc_lsb_sar_sticky_clr6_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_60_OFC_LSB_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_60_ofc_lsb_sar_sticky_clr7_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_60_OFC_LSB_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_60_ofc_lsb_sar_sticky_clr8_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_60_OFC_LSB_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_60_ofc_sar_acc_clr1_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_60_OFC_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_60_ofc_sar_acc_clr2_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_60_OFC_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_60_ofc_sar_acc_clr3_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_60_OFC_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_60_ofc_sar_acc_clr4_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_60_OFC_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_60_ofc_sar_acc_clr5_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_60_OFC_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_60_ofc_sar_acc_clr6_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_60_OFC_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_60_ofc_sar_acc_clr7_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_60_OFC_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_60_ofc_sar_acc_clr8_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_60_OFC_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_60_ofc_sar_sticky_clr1_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_60_OFC_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_60_ofc_sar_sticky_clr2_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_60_OFC_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_60_ofc_sar_sticky_clr3_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_60_OFC_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_60_ofc_sar_sticky_clr4_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_60_OFC_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_60_ofc_sar_sticky_clr5_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_60_OFC_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_60_ofc_sar_sticky_clr6_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_60_OFC_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_60_ofc_sar_sticky_clr7_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_60_OFC_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_60_ofc_sar_sticky_clr8_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_60_OFC_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_61_gain_sar_acc_clr1_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_61_GAIN_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_61_gain_sar_acc_clr2_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_61_GAIN_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_61_gain_sar_acc_clr3_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_61_GAIN_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_61_gain_sar_acc_clr4_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_61_GAIN_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_61_gain_sar_acc_clr5_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_61_GAIN_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_61_gain_sar_acc_clr6_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_61_GAIN_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_61_gain_sar_acc_clr7_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_61_GAIN_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_61_gain_sar_acc_clr8_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_61_GAIN_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_61_gain_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_61_gps_tap32_sel_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_61_GPS_TAP32_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_61_gps_tap64_sel_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_61_GPS_TAP64_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_62_gain_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_62_gain_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_62_gain_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_62_gain_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_62_gain_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_63_gain_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_63_gain_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_63_gain_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_64_acc_clr_en_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_64_ACC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_64_acc_clr_rst_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_64_ACC_CLR_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_64_agc_clr_en_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_64_AGC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_64_agc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_64_dfe1_clr_en_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_64_DFE1_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_64_dfe1_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_64_dfe2_16_clr_en_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_64_DFE2_16_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_64_dfe2_16_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_64_ofc_clr_en_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_64_OFC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_64_ofc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_64_vga_clr_en_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_64_VGA_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_64_vga_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_65_snr_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_66_snr_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_67_snr_div_facror_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_67_snr_meter_en_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_67_SNR_METER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_67_snr_smooth_bw_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_69_x3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_6_dfe_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_6_dfe_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_70_dsp_adapt_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_70_dsp_adapt_sec_acc_ctrl_broadcast_mode_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_70_DSP_ADAPT_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_70_dsp_adapt_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_70_dsp_adapt_sec_acc_ctrl_field_mask_write_en_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_70_DSP_ADAPT_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_70_dsp_adapt_sec_acc_ctrl_load_preset_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_70_DSP_ADAPT_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_70_dsp_adapt_sec_acc_ctrl_man_clear_on_read_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_70_DSP_ADAPT_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_70_dsp_adapt_sec_acc_ctrl_man_self_clear_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_70_DSP_ADAPT_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_70_dsp_adapt_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_70_dsp_adapt_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_70_dsp_adapt_sec_acc_ctrl_soft_reset_n_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_70_DSP_ADAPT_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_70_dsp_adapt_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_71_dsp_adapt_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_71_dsp_adapt_reg2probe_en_attr == SERDES_LANE_DSP_ADAPT_LANE0_REG_71_DSP_ADAPT_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_74_sec_lms0_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_75_sec_lms1_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_76_sec_lms2_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_77_sec_lms3_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_78_sec_lms0_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_79_sec_lms1_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_7_dfe_tap1_sel_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_7_err_slice_snr_level_m1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_7_err_slice_snr_level_m3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_80_sec_lms2_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_81_sec_lms3_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_82_sec_lms_clr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_82_sec_lms_en_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_82_sec_lms_ofc_mode_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_83_sec_lms0_delay_attr == 8'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_83_sec_lms1_delay_attr == 8'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_83_sec_lms2_delay_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_83_sec_lms3_delay_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_84_sec_lms_acc_in_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_84_sec_lms_acc_set_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_8_dfe_tap10_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_8_err_slice_snr_level_p1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_8_err_slice_snr_level_p3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_9_dfe1_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane0_reg_9_dfe_tap16_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_10_dfe2_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_11_dfe3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_12_dfe4_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_13_dfe5_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_15_dfe_adapt_all_taps_en_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_15_DFE_ADAPT_ALL_TAPS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_17_dfe6_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_18_dfe7_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_19_dfe8_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_20_dsp_bit_swz_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_20_DSP_BIT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_20_dsp_d_swz_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_20_DSP_D_SWZ_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_20_dsp_en_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_20_DSP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_20_dsp_inner_d_swz_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_20_DSP_INNER_D_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_20_dsp_inner_m_swz_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_20_DSP_INNER_M_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_20_dsp_latch_dis_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_20_DSP_LATCH_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_20_dsp_m_swz_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_20_DSP_M_SWZ_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_20_ehm_tap_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_20_fine_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_20_FINE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_20_io_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_20_ofc_sar_lsb_inv_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_20_OFC_SAR_LSB_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_20_ofc_sar_lsb_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_20_pam_4_en_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_20_PAM_4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_20_vref_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_21_ehm_event_sign_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_21_EHM_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_21_ehm_sym1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_21_ehm_sym_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_21_ehm_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_22_dfe_tap11_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_22_dfe_tap12_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_22_dfe_tap13_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_22_dfe_tap14_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_22_dfe_tap15_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_23_agc_en_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_23_AGC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_23_dfe_adapt_en_0_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_23_DFE_ADAPT_EN_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_23_dfe_adapt_en_10_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_23_DFE_ADAPT_EN_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_23_dfe_adapt_en_11_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_23_DFE_ADAPT_EN_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_23_dfe_adapt_en_12_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_23_DFE_ADAPT_EN_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_23_dfe_adapt_en_13_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_23_DFE_ADAPT_EN_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_23_dfe_adapt_en_14_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_23_DFE_ADAPT_EN_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_23_dfe_adapt_en_15_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_23_DFE_ADAPT_EN_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_23_dfe_adapt_en_1_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_23_DFE_ADAPT_EN_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_23_dfe_adapt_en_2_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_23_DFE_ADAPT_EN_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_23_dfe_adapt_en_3_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_23_DFE_ADAPT_EN_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_23_dfe_adapt_en_4_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_23_DFE_ADAPT_EN_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_23_dfe_adapt_en_5_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_23_DFE_ADAPT_EN_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_23_dfe_adapt_en_6_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_23_DFE_ADAPT_EN_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_23_dfe_adapt_en_7_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_23_DFE_ADAPT_EN_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_23_dfe_adapt_en_8_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_23_DFE_ADAPT_EN_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_23_dfe_adapt_en_9_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_23_DFE_ADAPT_EN_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_23_gain_sar_en_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_23_GAIN_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_23_ofc_en_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_23_OFC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_23_ofc_lsb_sar_en_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_23_OFC_LSB_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_23_ofc_sar_en_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_23_power_save_en_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_23_POWER_SAVE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_23_res_isi_mes_en_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_23_RES_ISI_MES_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_23_vga_en_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_23_VGA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_23_x3_en_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_23_X3_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_24_dfe9_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_25_dfe10_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_26_dfe11_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_27_dfe12_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_28_dfe13_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_29_dfe14_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_2_agc_coarse_det_en_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_2_AGC_COARSE_DET_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_2_agc_d_sign_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_2_AGC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_30_dfe15_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_31_dfe16_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_32_d_dly_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_32_e_dly_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_32_phase_mask0_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_32_phase_mask1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_32_phase_mask2_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_32_phase_mask3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_32_phase_num_mask_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_32_swap_bot_en_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_32_SWAP_BOT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_32_swap_top_en_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_32_SWAP_TOP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_33_coarse_det_pol_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_33_COARSE_DET_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_33_joint_dfe_en_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_33_JOINT_DFE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_33_phase_cnt_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_34_gain_sar_sticky_clr1_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_34_GAIN_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_34_gain_sar_sticky_clr2_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_34_GAIN_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_34_gain_sar_sticky_clr3_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_34_GAIN_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_34_gain_sar_sticky_clr4_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_34_GAIN_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_34_gain_sar_sticky_clr5_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_34_GAIN_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_34_gain_sar_sticky_clr6_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_34_GAIN_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_34_gain_sar_sticky_clr7_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_34_GAIN_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_34_gain_sar_sticky_clr8_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_34_GAIN_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_34_sticky_clr_0_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_34_STICKY_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_34_sticky_clr_10_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_34_STICKY_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_34_sticky_clr_11_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_34_STICKY_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_34_sticky_clr_12_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_34_STICKY_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_34_sticky_clr_13_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_34_STICKY_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_34_sticky_clr_14_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_34_STICKY_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_34_sticky_clr_15_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_34_STICKY_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_34_sticky_clr_16_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_34_STICKY_CLR_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_34_sticky_clr_17_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_34_STICKY_CLR_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_34_sticky_clr_18_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_34_STICKY_CLR_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_34_sticky_clr_1_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_34_STICKY_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_34_sticky_clr_2_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_34_STICKY_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_34_sticky_clr_3_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_34_STICKY_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_34_sticky_clr_4_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_34_STICKY_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_34_sticky_clr_5_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_34_STICKY_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_34_sticky_clr_6_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_34_STICKY_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_34_sticky_clr_7_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_34_STICKY_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_34_sticky_clr_8_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_34_STICKY_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_34_sticky_clr_9_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_34_STICKY_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_34_vga_sticky_clr_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_34_VGA_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_34_x3_sticky_clr_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_34_X3_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_35_agc_acc_clr_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_35_AGC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_35_dfe_acc_clr_0_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_35_DFE_ACC_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_35_dfe_acc_clr_10_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_35_DFE_ACC_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_35_dfe_acc_clr_11_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_35_DFE_ACC_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_35_dfe_acc_clr_12_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_35_DFE_ACC_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_35_dfe_acc_clr_13_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_35_DFE_ACC_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_35_dfe_acc_clr_14_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_35_DFE_ACC_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_35_dfe_acc_clr_15_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_35_DFE_ACC_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_35_dfe_acc_clr_1_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_35_DFE_ACC_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_35_dfe_acc_clr_2_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_35_DFE_ACC_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_35_dfe_acc_clr_3_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_35_DFE_ACC_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_35_dfe_acc_clr_4_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_35_DFE_ACC_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_35_dfe_acc_clr_5_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_35_DFE_ACC_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_35_dfe_acc_clr_6_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_35_DFE_ACC_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_35_dfe_acc_clr_7_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_35_DFE_ACC_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_35_dfe_acc_clr_8_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_35_DFE_ACC_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_35_dfe_acc_clr_9_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_35_DFE_ACC_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_35_ehm_acc_clr_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_35_EHM_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_35_ofc_acc_clr_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_35_OFC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_35_vga_acc_clr_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_35_VGA_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_35_x3_acc_clr_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_35_X3_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_36_ofc_d_sign_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_36_OFC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_36_ofc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_36_ofc_event_sign_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_36_OFC_EVENT_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_37_ofc_th_attr == 20'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_38_agc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_38_agc_event_sign_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_38_AGC_EVENT_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_39_dfe1_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_39_dfe_event_sign_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_3_agc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_3_agc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_40_ehm_event_rate_lsb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_41_ehm_event_rate_msb_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_42_ofc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_42_ofc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_45_agc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_46_ofc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_47_dfe_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_48_err_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_49_err_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_4_agc_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_50_vga_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_51_vga_range_detect_comp_const_h_attr == 7'd126
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_51_vga_range_detect_comp_const_l_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_51_vga_range_detect_sub_const_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_51_vga_shift_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_51_vga_zero_pull_en_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_51_VGA_ZERO_PULL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_51_vga_zero_pull_factor_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_52_ofc_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_53_vga_stable_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_53_VGA_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_54_dfe_common_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_54_dfe_common_th_en_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_54_DFE_COMMON_TH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_55_ofc_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_55_ofc_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_55_ofc_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_55_ofc_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_55_ofc_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_56_ofc_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_56_ofc_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_56_ofc_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_57_ofc_lsb_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_58_ofc_lsb_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_58_ofc_lsb_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_58_ofc_lsb_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_58_ofc_lsb_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_58_ofc_lsb_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_59_ofc_lsb_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_59_ofc_lsb_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_59_ofc_lsb_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_5_dfe_d_sign_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_5_DFE_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_5_dfe_tap9_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_60_ofc_lsb_sar_acc_clr1_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_60_OFC_LSB_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_60_ofc_lsb_sar_acc_clr2_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_60_OFC_LSB_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_60_ofc_lsb_sar_acc_clr3_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_60_OFC_LSB_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_60_ofc_lsb_sar_acc_clr4_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_60_OFC_LSB_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_60_ofc_lsb_sar_acc_clr5_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_60_OFC_LSB_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_60_ofc_lsb_sar_acc_clr6_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_60_OFC_LSB_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_60_ofc_lsb_sar_acc_clr7_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_60_OFC_LSB_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_60_ofc_lsb_sar_acc_clr8_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_60_OFC_LSB_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_60_ofc_lsb_sar_sticky_clr1_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_60_OFC_LSB_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_60_ofc_lsb_sar_sticky_clr2_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_60_OFC_LSB_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_60_ofc_lsb_sar_sticky_clr3_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_60_OFC_LSB_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_60_ofc_lsb_sar_sticky_clr4_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_60_OFC_LSB_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_60_ofc_lsb_sar_sticky_clr5_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_60_OFC_LSB_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_60_ofc_lsb_sar_sticky_clr6_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_60_OFC_LSB_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_60_ofc_lsb_sar_sticky_clr7_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_60_OFC_LSB_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_60_ofc_lsb_sar_sticky_clr8_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_60_OFC_LSB_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_60_ofc_sar_acc_clr1_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_60_OFC_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_60_ofc_sar_acc_clr2_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_60_OFC_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_60_ofc_sar_acc_clr3_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_60_OFC_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_60_ofc_sar_acc_clr4_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_60_OFC_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_60_ofc_sar_acc_clr5_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_60_OFC_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_60_ofc_sar_acc_clr6_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_60_OFC_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_60_ofc_sar_acc_clr7_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_60_OFC_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_60_ofc_sar_acc_clr8_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_60_OFC_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_60_ofc_sar_sticky_clr1_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_60_OFC_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_60_ofc_sar_sticky_clr2_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_60_OFC_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_60_ofc_sar_sticky_clr3_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_60_OFC_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_60_ofc_sar_sticky_clr4_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_60_OFC_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_60_ofc_sar_sticky_clr5_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_60_OFC_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_60_ofc_sar_sticky_clr6_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_60_OFC_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_60_ofc_sar_sticky_clr7_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_60_OFC_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_60_ofc_sar_sticky_clr8_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_60_OFC_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_61_gain_sar_acc_clr1_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_61_GAIN_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_61_gain_sar_acc_clr2_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_61_GAIN_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_61_gain_sar_acc_clr3_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_61_GAIN_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_61_gain_sar_acc_clr4_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_61_GAIN_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_61_gain_sar_acc_clr5_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_61_GAIN_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_61_gain_sar_acc_clr6_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_61_GAIN_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_61_gain_sar_acc_clr7_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_61_GAIN_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_61_gain_sar_acc_clr8_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_61_GAIN_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_61_gain_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_61_gps_tap32_sel_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_61_GPS_TAP32_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_61_gps_tap64_sel_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_61_GPS_TAP64_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_62_gain_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_62_gain_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_62_gain_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_62_gain_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_62_gain_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_63_gain_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_63_gain_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_63_gain_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_64_acc_clr_en_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_64_ACC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_64_acc_clr_rst_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_64_ACC_CLR_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_64_agc_clr_en_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_64_AGC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_64_agc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_64_dfe1_clr_en_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_64_DFE1_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_64_dfe1_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_64_dfe2_16_clr_en_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_64_DFE2_16_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_64_dfe2_16_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_64_ofc_clr_en_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_64_OFC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_64_ofc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_64_vga_clr_en_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_64_VGA_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_64_vga_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_65_snr_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_66_snr_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_67_snr_div_facror_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_67_snr_meter_en_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_67_SNR_METER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_67_snr_smooth_bw_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_69_x3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_6_dfe_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_6_dfe_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_70_dsp_adapt_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_70_dsp_adapt_sec_acc_ctrl_broadcast_mode_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_70_DSP_ADAPT_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_70_dsp_adapt_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_70_dsp_adapt_sec_acc_ctrl_field_mask_write_en_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_70_DSP_ADAPT_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_70_dsp_adapt_sec_acc_ctrl_load_preset_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_70_DSP_ADAPT_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_70_dsp_adapt_sec_acc_ctrl_man_clear_on_read_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_70_DSP_ADAPT_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_70_dsp_adapt_sec_acc_ctrl_man_self_clear_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_70_DSP_ADAPT_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_70_dsp_adapt_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_70_dsp_adapt_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_70_dsp_adapt_sec_acc_ctrl_soft_reset_n_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_70_DSP_ADAPT_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_70_dsp_adapt_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_71_dsp_adapt_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_71_dsp_adapt_reg2probe_en_attr == SERDES_LANE_DSP_ADAPT_LANE1_REG_71_DSP_ADAPT_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_74_sec_lms0_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_75_sec_lms1_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_76_sec_lms2_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_77_sec_lms3_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_78_sec_lms0_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_79_sec_lms1_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_7_dfe_tap1_sel_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_7_err_slice_snr_level_m1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_7_err_slice_snr_level_m3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_80_sec_lms2_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_81_sec_lms3_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_82_sec_lms_clr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_82_sec_lms_en_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_82_sec_lms_ofc_mode_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_83_sec_lms0_delay_attr == 8'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_83_sec_lms1_delay_attr == 8'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_83_sec_lms2_delay_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_83_sec_lms3_delay_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_84_sec_lms_acc_in_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_84_sec_lms_acc_set_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_8_dfe_tap10_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_8_err_slice_snr_level_p1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_8_err_slice_snr_level_p3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_9_dfe1_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane1_reg_9_dfe_tap16_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_10_dfe2_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_11_dfe3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_12_dfe4_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_13_dfe5_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_15_dfe_adapt_all_taps_en_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_15_DFE_ADAPT_ALL_TAPS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_17_dfe6_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_18_dfe7_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_19_dfe8_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_20_dsp_bit_swz_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_20_DSP_BIT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_20_dsp_d_swz_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_20_DSP_D_SWZ_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_20_dsp_en_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_20_DSP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_20_dsp_inner_d_swz_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_20_DSP_INNER_D_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_20_dsp_inner_m_swz_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_20_DSP_INNER_M_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_20_dsp_latch_dis_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_20_DSP_LATCH_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_20_dsp_m_swz_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_20_DSP_M_SWZ_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_20_ehm_tap_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_20_fine_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_20_FINE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_20_io_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_20_ofc_sar_lsb_inv_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_20_OFC_SAR_LSB_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_20_ofc_sar_lsb_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_20_pam_4_en_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_20_PAM_4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_20_vref_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_21_ehm_event_sign_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_21_EHM_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_21_ehm_sym1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_21_ehm_sym_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_21_ehm_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_22_dfe_tap11_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_22_dfe_tap12_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_22_dfe_tap13_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_22_dfe_tap14_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_22_dfe_tap15_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_23_agc_en_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_23_AGC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_23_dfe_adapt_en_0_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_23_DFE_ADAPT_EN_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_23_dfe_adapt_en_10_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_23_DFE_ADAPT_EN_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_23_dfe_adapt_en_11_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_23_DFE_ADAPT_EN_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_23_dfe_adapt_en_12_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_23_DFE_ADAPT_EN_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_23_dfe_adapt_en_13_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_23_DFE_ADAPT_EN_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_23_dfe_adapt_en_14_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_23_DFE_ADAPT_EN_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_23_dfe_adapt_en_15_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_23_DFE_ADAPT_EN_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_23_dfe_adapt_en_1_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_23_DFE_ADAPT_EN_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_23_dfe_adapt_en_2_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_23_DFE_ADAPT_EN_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_23_dfe_adapt_en_3_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_23_DFE_ADAPT_EN_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_23_dfe_adapt_en_4_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_23_DFE_ADAPT_EN_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_23_dfe_adapt_en_5_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_23_DFE_ADAPT_EN_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_23_dfe_adapt_en_6_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_23_DFE_ADAPT_EN_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_23_dfe_adapt_en_7_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_23_DFE_ADAPT_EN_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_23_dfe_adapt_en_8_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_23_DFE_ADAPT_EN_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_23_dfe_adapt_en_9_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_23_DFE_ADAPT_EN_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_23_gain_sar_en_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_23_GAIN_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_23_ofc_en_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_23_OFC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_23_ofc_lsb_sar_en_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_23_OFC_LSB_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_23_ofc_sar_en_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_23_power_save_en_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_23_POWER_SAVE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_23_res_isi_mes_en_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_23_RES_ISI_MES_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_23_vga_en_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_23_VGA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_23_x3_en_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_23_X3_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_24_dfe9_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_25_dfe10_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_26_dfe11_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_27_dfe12_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_28_dfe13_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_29_dfe14_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_2_agc_coarse_det_en_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_2_AGC_COARSE_DET_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_2_agc_d_sign_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_2_AGC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_30_dfe15_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_31_dfe16_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_32_d_dly_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_32_e_dly_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_32_phase_mask0_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_32_phase_mask1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_32_phase_mask2_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_32_phase_mask3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_32_phase_num_mask_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_32_swap_bot_en_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_32_SWAP_BOT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_32_swap_top_en_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_32_SWAP_TOP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_33_coarse_det_pol_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_33_COARSE_DET_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_33_joint_dfe_en_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_33_JOINT_DFE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_33_phase_cnt_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_34_gain_sar_sticky_clr1_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_34_GAIN_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_34_gain_sar_sticky_clr2_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_34_GAIN_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_34_gain_sar_sticky_clr3_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_34_GAIN_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_34_gain_sar_sticky_clr4_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_34_GAIN_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_34_gain_sar_sticky_clr5_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_34_GAIN_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_34_gain_sar_sticky_clr6_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_34_GAIN_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_34_gain_sar_sticky_clr7_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_34_GAIN_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_34_gain_sar_sticky_clr8_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_34_GAIN_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_34_sticky_clr_0_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_34_STICKY_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_34_sticky_clr_10_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_34_STICKY_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_34_sticky_clr_11_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_34_STICKY_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_34_sticky_clr_12_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_34_STICKY_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_34_sticky_clr_13_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_34_STICKY_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_34_sticky_clr_14_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_34_STICKY_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_34_sticky_clr_15_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_34_STICKY_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_34_sticky_clr_16_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_34_STICKY_CLR_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_34_sticky_clr_17_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_34_STICKY_CLR_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_34_sticky_clr_18_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_34_STICKY_CLR_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_34_sticky_clr_1_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_34_STICKY_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_34_sticky_clr_2_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_34_STICKY_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_34_sticky_clr_3_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_34_STICKY_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_34_sticky_clr_4_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_34_STICKY_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_34_sticky_clr_5_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_34_STICKY_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_34_sticky_clr_6_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_34_STICKY_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_34_sticky_clr_7_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_34_STICKY_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_34_sticky_clr_8_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_34_STICKY_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_34_sticky_clr_9_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_34_STICKY_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_34_vga_sticky_clr_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_34_VGA_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_34_x3_sticky_clr_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_34_X3_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_35_agc_acc_clr_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_35_AGC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_35_dfe_acc_clr_0_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_35_DFE_ACC_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_35_dfe_acc_clr_10_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_35_DFE_ACC_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_35_dfe_acc_clr_11_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_35_DFE_ACC_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_35_dfe_acc_clr_12_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_35_DFE_ACC_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_35_dfe_acc_clr_13_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_35_DFE_ACC_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_35_dfe_acc_clr_14_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_35_DFE_ACC_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_35_dfe_acc_clr_15_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_35_DFE_ACC_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_35_dfe_acc_clr_1_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_35_DFE_ACC_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_35_dfe_acc_clr_2_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_35_DFE_ACC_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_35_dfe_acc_clr_3_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_35_DFE_ACC_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_35_dfe_acc_clr_4_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_35_DFE_ACC_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_35_dfe_acc_clr_5_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_35_DFE_ACC_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_35_dfe_acc_clr_6_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_35_DFE_ACC_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_35_dfe_acc_clr_7_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_35_DFE_ACC_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_35_dfe_acc_clr_8_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_35_DFE_ACC_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_35_dfe_acc_clr_9_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_35_DFE_ACC_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_35_ehm_acc_clr_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_35_EHM_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_35_ofc_acc_clr_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_35_OFC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_35_vga_acc_clr_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_35_VGA_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_35_x3_acc_clr_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_35_X3_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_36_ofc_d_sign_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_36_OFC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_36_ofc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_36_ofc_event_sign_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_36_OFC_EVENT_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_37_ofc_th_attr == 20'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_38_agc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_38_agc_event_sign_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_38_AGC_EVENT_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_39_dfe1_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_39_dfe_event_sign_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_3_agc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_3_agc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_40_ehm_event_rate_lsb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_41_ehm_event_rate_msb_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_42_ofc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_42_ofc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_45_agc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_46_ofc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_47_dfe_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_48_err_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_49_err_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_4_agc_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_50_vga_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_51_vga_range_detect_comp_const_h_attr == 7'd126
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_51_vga_range_detect_comp_const_l_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_51_vga_range_detect_sub_const_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_51_vga_shift_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_51_vga_zero_pull_en_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_51_VGA_ZERO_PULL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_51_vga_zero_pull_factor_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_52_ofc_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_53_vga_stable_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_53_VGA_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_54_dfe_common_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_54_dfe_common_th_en_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_54_DFE_COMMON_TH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_55_ofc_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_55_ofc_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_55_ofc_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_55_ofc_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_55_ofc_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_56_ofc_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_56_ofc_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_56_ofc_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_57_ofc_lsb_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_58_ofc_lsb_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_58_ofc_lsb_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_58_ofc_lsb_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_58_ofc_lsb_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_58_ofc_lsb_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_59_ofc_lsb_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_59_ofc_lsb_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_59_ofc_lsb_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_5_dfe_d_sign_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_5_DFE_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_5_dfe_tap9_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_60_ofc_lsb_sar_acc_clr1_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_60_OFC_LSB_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_60_ofc_lsb_sar_acc_clr2_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_60_OFC_LSB_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_60_ofc_lsb_sar_acc_clr3_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_60_OFC_LSB_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_60_ofc_lsb_sar_acc_clr4_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_60_OFC_LSB_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_60_ofc_lsb_sar_acc_clr5_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_60_OFC_LSB_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_60_ofc_lsb_sar_acc_clr6_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_60_OFC_LSB_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_60_ofc_lsb_sar_acc_clr7_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_60_OFC_LSB_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_60_ofc_lsb_sar_acc_clr8_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_60_OFC_LSB_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_60_ofc_lsb_sar_sticky_clr1_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_60_OFC_LSB_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_60_ofc_lsb_sar_sticky_clr2_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_60_OFC_LSB_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_60_ofc_lsb_sar_sticky_clr3_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_60_OFC_LSB_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_60_ofc_lsb_sar_sticky_clr4_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_60_OFC_LSB_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_60_ofc_lsb_sar_sticky_clr5_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_60_OFC_LSB_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_60_ofc_lsb_sar_sticky_clr6_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_60_OFC_LSB_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_60_ofc_lsb_sar_sticky_clr7_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_60_OFC_LSB_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_60_ofc_lsb_sar_sticky_clr8_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_60_OFC_LSB_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_60_ofc_sar_acc_clr1_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_60_OFC_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_60_ofc_sar_acc_clr2_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_60_OFC_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_60_ofc_sar_acc_clr3_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_60_OFC_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_60_ofc_sar_acc_clr4_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_60_OFC_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_60_ofc_sar_acc_clr5_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_60_OFC_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_60_ofc_sar_acc_clr6_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_60_OFC_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_60_ofc_sar_acc_clr7_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_60_OFC_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_60_ofc_sar_acc_clr8_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_60_OFC_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_60_ofc_sar_sticky_clr1_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_60_OFC_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_60_ofc_sar_sticky_clr2_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_60_OFC_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_60_ofc_sar_sticky_clr3_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_60_OFC_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_60_ofc_sar_sticky_clr4_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_60_OFC_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_60_ofc_sar_sticky_clr5_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_60_OFC_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_60_ofc_sar_sticky_clr6_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_60_OFC_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_60_ofc_sar_sticky_clr7_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_60_OFC_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_60_ofc_sar_sticky_clr8_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_60_OFC_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_61_gain_sar_acc_clr1_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_61_GAIN_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_61_gain_sar_acc_clr2_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_61_GAIN_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_61_gain_sar_acc_clr3_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_61_GAIN_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_61_gain_sar_acc_clr4_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_61_GAIN_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_61_gain_sar_acc_clr5_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_61_GAIN_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_61_gain_sar_acc_clr6_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_61_GAIN_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_61_gain_sar_acc_clr7_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_61_GAIN_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_61_gain_sar_acc_clr8_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_61_GAIN_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_61_gain_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_61_gps_tap32_sel_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_61_GPS_TAP32_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_61_gps_tap64_sel_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_61_GPS_TAP64_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_62_gain_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_62_gain_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_62_gain_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_62_gain_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_62_gain_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_63_gain_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_63_gain_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_63_gain_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_64_acc_clr_en_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_64_ACC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_64_acc_clr_rst_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_64_ACC_CLR_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_64_agc_clr_en_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_64_AGC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_64_agc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_64_dfe1_clr_en_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_64_DFE1_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_64_dfe1_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_64_dfe2_16_clr_en_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_64_DFE2_16_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_64_dfe2_16_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_64_ofc_clr_en_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_64_OFC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_64_ofc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_64_vga_clr_en_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_64_VGA_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_64_vga_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_65_snr_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_66_snr_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_67_snr_div_facror_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_67_snr_meter_en_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_67_SNR_METER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_67_snr_smooth_bw_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_69_x3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_6_dfe_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_6_dfe_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_70_dsp_adapt_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_70_dsp_adapt_sec_acc_ctrl_broadcast_mode_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_70_DSP_ADAPT_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_70_dsp_adapt_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_70_dsp_adapt_sec_acc_ctrl_field_mask_write_en_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_70_DSP_ADAPT_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_70_dsp_adapt_sec_acc_ctrl_load_preset_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_70_DSP_ADAPT_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_70_dsp_adapt_sec_acc_ctrl_man_clear_on_read_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_70_DSP_ADAPT_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_70_dsp_adapt_sec_acc_ctrl_man_self_clear_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_70_DSP_ADAPT_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_70_dsp_adapt_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_70_dsp_adapt_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_70_dsp_adapt_sec_acc_ctrl_soft_reset_n_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_70_DSP_ADAPT_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_70_dsp_adapt_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_71_dsp_adapt_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_71_dsp_adapt_reg2probe_en_attr == SERDES_LANE_DSP_ADAPT_LANE2_REG_71_DSP_ADAPT_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_74_sec_lms0_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_75_sec_lms1_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_76_sec_lms2_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_77_sec_lms3_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_78_sec_lms0_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_79_sec_lms1_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_7_dfe_tap1_sel_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_7_err_slice_snr_level_m1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_7_err_slice_snr_level_m3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_80_sec_lms2_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_81_sec_lms3_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_82_sec_lms_clr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_82_sec_lms_en_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_82_sec_lms_ofc_mode_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_83_sec_lms0_delay_attr == 8'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_83_sec_lms1_delay_attr == 8'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_83_sec_lms2_delay_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_83_sec_lms3_delay_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_84_sec_lms_acc_in_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_84_sec_lms_acc_set_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_8_dfe_tap10_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_8_err_slice_snr_level_p1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_8_err_slice_snr_level_p3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_9_dfe1_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane2_reg_9_dfe_tap16_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_10_dfe2_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_11_dfe3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_12_dfe4_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_13_dfe5_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_15_dfe_adapt_all_taps_en_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_15_DFE_ADAPT_ALL_TAPS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_17_dfe6_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_18_dfe7_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_19_dfe8_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_20_dsp_bit_swz_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_20_DSP_BIT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_20_dsp_d_swz_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_20_DSP_D_SWZ_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_20_dsp_en_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_20_DSP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_20_dsp_inner_d_swz_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_20_DSP_INNER_D_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_20_dsp_inner_m_swz_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_20_DSP_INNER_M_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_20_dsp_latch_dis_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_20_DSP_LATCH_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_20_dsp_m_swz_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_20_DSP_M_SWZ_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_20_ehm_tap_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_20_fine_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_20_FINE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_20_io_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_20_ofc_sar_lsb_inv_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_20_OFC_SAR_LSB_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_20_ofc_sar_lsb_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_20_pam_4_en_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_20_PAM_4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_20_vref_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_21_ehm_event_sign_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_21_EHM_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_21_ehm_sym1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_21_ehm_sym_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_21_ehm_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_22_dfe_tap11_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_22_dfe_tap12_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_22_dfe_tap13_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_22_dfe_tap14_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_22_dfe_tap15_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_23_agc_en_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_23_AGC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_23_dfe_adapt_en_0_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_23_DFE_ADAPT_EN_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_23_dfe_adapt_en_10_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_23_DFE_ADAPT_EN_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_23_dfe_adapt_en_11_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_23_DFE_ADAPT_EN_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_23_dfe_adapt_en_12_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_23_DFE_ADAPT_EN_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_23_dfe_adapt_en_13_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_23_DFE_ADAPT_EN_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_23_dfe_adapt_en_14_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_23_DFE_ADAPT_EN_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_23_dfe_adapt_en_15_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_23_DFE_ADAPT_EN_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_23_dfe_adapt_en_1_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_23_DFE_ADAPT_EN_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_23_dfe_adapt_en_2_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_23_DFE_ADAPT_EN_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_23_dfe_adapt_en_3_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_23_DFE_ADAPT_EN_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_23_dfe_adapt_en_4_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_23_DFE_ADAPT_EN_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_23_dfe_adapt_en_5_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_23_DFE_ADAPT_EN_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_23_dfe_adapt_en_6_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_23_DFE_ADAPT_EN_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_23_dfe_adapt_en_7_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_23_DFE_ADAPT_EN_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_23_dfe_adapt_en_8_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_23_DFE_ADAPT_EN_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_23_dfe_adapt_en_9_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_23_DFE_ADAPT_EN_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_23_gain_sar_en_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_23_GAIN_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_23_ofc_en_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_23_OFC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_23_ofc_lsb_sar_en_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_23_OFC_LSB_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_23_ofc_sar_en_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_23_power_save_en_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_23_POWER_SAVE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_23_res_isi_mes_en_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_23_RES_ISI_MES_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_23_vga_en_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_23_VGA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_23_x3_en_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_23_X3_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_24_dfe9_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_25_dfe10_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_26_dfe11_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_27_dfe12_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_28_dfe13_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_29_dfe14_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_2_agc_coarse_det_en_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_2_AGC_COARSE_DET_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_2_agc_d_sign_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_2_AGC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_30_dfe15_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_31_dfe16_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_32_d_dly_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_32_e_dly_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_32_phase_mask0_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_32_phase_mask1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_32_phase_mask2_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_32_phase_mask3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_32_phase_num_mask_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_32_swap_bot_en_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_32_SWAP_BOT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_32_swap_top_en_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_32_SWAP_TOP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_33_coarse_det_pol_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_33_COARSE_DET_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_33_joint_dfe_en_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_33_JOINT_DFE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_33_phase_cnt_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_34_gain_sar_sticky_clr1_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_34_GAIN_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_34_gain_sar_sticky_clr2_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_34_GAIN_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_34_gain_sar_sticky_clr3_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_34_GAIN_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_34_gain_sar_sticky_clr4_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_34_GAIN_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_34_gain_sar_sticky_clr5_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_34_GAIN_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_34_gain_sar_sticky_clr6_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_34_GAIN_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_34_gain_sar_sticky_clr7_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_34_GAIN_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_34_gain_sar_sticky_clr8_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_34_GAIN_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_34_sticky_clr_0_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_34_STICKY_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_34_sticky_clr_10_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_34_STICKY_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_34_sticky_clr_11_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_34_STICKY_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_34_sticky_clr_12_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_34_STICKY_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_34_sticky_clr_13_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_34_STICKY_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_34_sticky_clr_14_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_34_STICKY_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_34_sticky_clr_15_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_34_STICKY_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_34_sticky_clr_16_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_34_STICKY_CLR_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_34_sticky_clr_17_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_34_STICKY_CLR_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_34_sticky_clr_18_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_34_STICKY_CLR_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_34_sticky_clr_1_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_34_STICKY_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_34_sticky_clr_2_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_34_STICKY_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_34_sticky_clr_3_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_34_STICKY_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_34_sticky_clr_4_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_34_STICKY_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_34_sticky_clr_5_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_34_STICKY_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_34_sticky_clr_6_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_34_STICKY_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_34_sticky_clr_7_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_34_STICKY_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_34_sticky_clr_8_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_34_STICKY_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_34_sticky_clr_9_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_34_STICKY_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_34_vga_sticky_clr_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_34_VGA_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_34_x3_sticky_clr_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_34_X3_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_35_agc_acc_clr_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_35_AGC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_35_dfe_acc_clr_0_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_35_DFE_ACC_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_35_dfe_acc_clr_10_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_35_DFE_ACC_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_35_dfe_acc_clr_11_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_35_DFE_ACC_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_35_dfe_acc_clr_12_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_35_DFE_ACC_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_35_dfe_acc_clr_13_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_35_DFE_ACC_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_35_dfe_acc_clr_14_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_35_DFE_ACC_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_35_dfe_acc_clr_15_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_35_DFE_ACC_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_35_dfe_acc_clr_1_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_35_DFE_ACC_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_35_dfe_acc_clr_2_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_35_DFE_ACC_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_35_dfe_acc_clr_3_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_35_DFE_ACC_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_35_dfe_acc_clr_4_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_35_DFE_ACC_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_35_dfe_acc_clr_5_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_35_DFE_ACC_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_35_dfe_acc_clr_6_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_35_DFE_ACC_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_35_dfe_acc_clr_7_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_35_DFE_ACC_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_35_dfe_acc_clr_8_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_35_DFE_ACC_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_35_dfe_acc_clr_9_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_35_DFE_ACC_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_35_ehm_acc_clr_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_35_EHM_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_35_ofc_acc_clr_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_35_OFC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_35_vga_acc_clr_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_35_VGA_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_35_x3_acc_clr_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_35_X3_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_36_ofc_d_sign_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_36_OFC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_36_ofc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_36_ofc_event_sign_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_36_OFC_EVENT_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_37_ofc_th_attr == 20'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_38_agc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_38_agc_event_sign_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_38_AGC_EVENT_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_39_dfe1_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_39_dfe_event_sign_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_3_agc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_3_agc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_40_ehm_event_rate_lsb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_41_ehm_event_rate_msb_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_42_ofc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_42_ofc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_45_agc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_46_ofc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_47_dfe_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_48_err_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_49_err_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_4_agc_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_50_vga_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_51_vga_range_detect_comp_const_h_attr == 7'd126
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_51_vga_range_detect_comp_const_l_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_51_vga_range_detect_sub_const_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_51_vga_shift_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_51_vga_zero_pull_en_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_51_VGA_ZERO_PULL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_51_vga_zero_pull_factor_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_52_ofc_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_53_vga_stable_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_53_VGA_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_54_dfe_common_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_54_dfe_common_th_en_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_54_DFE_COMMON_TH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_55_ofc_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_55_ofc_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_55_ofc_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_55_ofc_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_55_ofc_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_56_ofc_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_56_ofc_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_56_ofc_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_57_ofc_lsb_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_58_ofc_lsb_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_58_ofc_lsb_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_58_ofc_lsb_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_58_ofc_lsb_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_58_ofc_lsb_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_59_ofc_lsb_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_59_ofc_lsb_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_59_ofc_lsb_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_5_dfe_d_sign_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_5_DFE_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_5_dfe_tap9_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_60_ofc_lsb_sar_acc_clr1_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_60_OFC_LSB_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_60_ofc_lsb_sar_acc_clr2_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_60_OFC_LSB_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_60_ofc_lsb_sar_acc_clr3_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_60_OFC_LSB_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_60_ofc_lsb_sar_acc_clr4_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_60_OFC_LSB_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_60_ofc_lsb_sar_acc_clr5_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_60_OFC_LSB_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_60_ofc_lsb_sar_acc_clr6_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_60_OFC_LSB_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_60_ofc_lsb_sar_acc_clr7_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_60_OFC_LSB_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_60_ofc_lsb_sar_acc_clr8_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_60_OFC_LSB_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_60_ofc_lsb_sar_sticky_clr1_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_60_OFC_LSB_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_60_ofc_lsb_sar_sticky_clr2_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_60_OFC_LSB_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_60_ofc_lsb_sar_sticky_clr3_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_60_OFC_LSB_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_60_ofc_lsb_sar_sticky_clr4_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_60_OFC_LSB_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_60_ofc_lsb_sar_sticky_clr5_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_60_OFC_LSB_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_60_ofc_lsb_sar_sticky_clr6_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_60_OFC_LSB_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_60_ofc_lsb_sar_sticky_clr7_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_60_OFC_LSB_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_60_ofc_lsb_sar_sticky_clr8_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_60_OFC_LSB_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_60_ofc_sar_acc_clr1_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_60_OFC_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_60_ofc_sar_acc_clr2_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_60_OFC_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_60_ofc_sar_acc_clr3_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_60_OFC_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_60_ofc_sar_acc_clr4_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_60_OFC_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_60_ofc_sar_acc_clr5_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_60_OFC_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_60_ofc_sar_acc_clr6_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_60_OFC_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_60_ofc_sar_acc_clr7_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_60_OFC_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_60_ofc_sar_acc_clr8_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_60_OFC_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_60_ofc_sar_sticky_clr1_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_60_OFC_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_60_ofc_sar_sticky_clr2_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_60_OFC_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_60_ofc_sar_sticky_clr3_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_60_OFC_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_60_ofc_sar_sticky_clr4_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_60_OFC_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_60_ofc_sar_sticky_clr5_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_60_OFC_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_60_ofc_sar_sticky_clr6_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_60_OFC_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_60_ofc_sar_sticky_clr7_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_60_OFC_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_60_ofc_sar_sticky_clr8_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_60_OFC_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_61_gain_sar_acc_clr1_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_61_GAIN_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_61_gain_sar_acc_clr2_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_61_GAIN_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_61_gain_sar_acc_clr3_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_61_GAIN_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_61_gain_sar_acc_clr4_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_61_GAIN_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_61_gain_sar_acc_clr5_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_61_GAIN_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_61_gain_sar_acc_clr6_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_61_GAIN_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_61_gain_sar_acc_clr7_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_61_GAIN_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_61_gain_sar_acc_clr8_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_61_GAIN_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_61_gain_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_61_gps_tap32_sel_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_61_GPS_TAP32_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_61_gps_tap64_sel_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_61_GPS_TAP64_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_62_gain_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_62_gain_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_62_gain_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_62_gain_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_62_gain_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_63_gain_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_63_gain_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_63_gain_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_64_acc_clr_en_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_64_ACC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_64_acc_clr_rst_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_64_ACC_CLR_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_64_agc_clr_en_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_64_AGC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_64_agc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_64_dfe1_clr_en_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_64_DFE1_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_64_dfe1_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_64_dfe2_16_clr_en_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_64_DFE2_16_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_64_dfe2_16_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_64_ofc_clr_en_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_64_OFC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_64_ofc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_64_vga_clr_en_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_64_VGA_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_64_vga_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_65_snr_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_66_snr_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_67_snr_div_facror_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_67_snr_meter_en_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_67_SNR_METER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_67_snr_smooth_bw_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_69_x3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_6_dfe_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_6_dfe_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_70_dsp_adapt_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_70_dsp_adapt_sec_acc_ctrl_broadcast_mode_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_70_DSP_ADAPT_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_70_dsp_adapt_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_70_dsp_adapt_sec_acc_ctrl_field_mask_write_en_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_70_DSP_ADAPT_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_70_dsp_adapt_sec_acc_ctrl_load_preset_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_70_DSP_ADAPT_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_70_dsp_adapt_sec_acc_ctrl_man_clear_on_read_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_70_DSP_ADAPT_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_70_dsp_adapt_sec_acc_ctrl_man_self_clear_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_70_DSP_ADAPT_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_70_dsp_adapt_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_70_dsp_adapt_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_70_dsp_adapt_sec_acc_ctrl_soft_reset_n_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_70_DSP_ADAPT_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_70_dsp_adapt_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_71_dsp_adapt_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_71_dsp_adapt_reg2probe_en_attr == SERDES_LANE_DSP_ADAPT_LANE3_REG_71_DSP_ADAPT_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_74_sec_lms0_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_75_sec_lms1_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_76_sec_lms2_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_77_sec_lms3_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_78_sec_lms0_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_79_sec_lms1_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_7_dfe_tap1_sel_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_7_err_slice_snr_level_m1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_7_err_slice_snr_level_m3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_80_sec_lms2_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_81_sec_lms3_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_82_sec_lms_clr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_82_sec_lms_en_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_82_sec_lms_ofc_mode_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_83_sec_lms0_delay_attr == 8'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_83_sec_lms1_delay_attr == 8'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_83_sec_lms2_delay_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_83_sec_lms3_delay_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_84_sec_lms_acc_in_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_84_sec_lms_acc_set_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_8_dfe_tap10_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_8_err_slice_snr_level_p1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_8_err_slice_snr_level_p3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_9_dfe1_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_adapt_lane3_reg_9_dfe_tap16_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_10_dfe_err_slicer_p_broadcast_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_11_dfe_err_slicer_n_broadcast_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_12_dfe_err_slice_level_p1_set0_attr == 9'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_12_dfe_err_slice_level_p3_set0_attr == 9'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_13_dfe_err_slice_level_m1_set0_attr == 9'd480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_13_dfe_err_slice_level_m3_set0_attr == 9'd416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_14_dfe_err_slice_level_p1_set1_attr == 9'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_14_dfe_err_slice_level_p3_set1_attr == 9'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_15_dfe_err_slice_level_m1_set1_attr == 9'd480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_15_dfe_err_slice_level_m3_set1_attr == 9'd416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_16_dfe_err_slice_level_p1_set2_attr == 9'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_16_dfe_err_slice_level_p3_set2_attr == 9'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_17_dfe_err_slice_level_m1_set2_attr == 9'd480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_17_dfe_err_slice_level_m3_set2_attr == 9'd416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_18_dfe_err_slice_level_p1_set3_attr == 9'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_18_dfe_err_slice_level_p3_set3_attr == 9'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_19_dfe_err_slice_level_m1_set3_attr == 9'd480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_19_dfe_err_slice_level_m3_set3_attr == 9'd416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_1_dfe_slicer_broadcast_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_20_dfe_err_slice_level_p1_set4_attr == 9'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_20_dfe_err_slice_level_p3_set4_attr == 9'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_21_dfe_err_slice_level_m1_set4_attr == 9'd480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_21_dfe_err_slice_level_m3_set4_attr == 9'd416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_22_dfe_err_slice_level_p1_set5_attr == 9'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_22_dfe_err_slice_level_p3_set5_attr == 9'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_23_dfe_err_slice_level_m1_set5_attr == 9'd480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_23_dfe_err_slice_level_m3_set5_attr == 9'd416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_24_dfe_err_slice_level_p1_set6_attr == 9'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_24_dfe_err_slice_level_p3_set6_attr == 9'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_25_dfe_err_slice_level_m1_set6_attr == 9'd480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_25_dfe_err_slice_level_m3_set6_attr == 9'd416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_26_dfe_err_slice_level_p1_set7_attr == 9'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_26_dfe_err_slice_level_p3_set7_attr == 9'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_27_dfe_err_slice_level_m1_set7_attr == 9'd480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_27_dfe_err_slice_level_m3_set7_attr == 9'd416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_28_brk_dfe_cb_not_sat_in_dfe_attr == SERDES_LANE_DSP_DFE1_LANE0_REG_28_BRK_DFE_CB_NOT_SAT_IN_DFE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_28_cfg_cb_inv_n_err_attr == SERDES_LANE_DSP_DFE1_LANE0_REG_28_CFG_CB_INV_N_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_28_cfg_cb_inv_p_err_attr == SERDES_LANE_DSP_DFE1_LANE0_REG_28_CFG_CB_INV_P_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_28_cfg_dfe_bypass_en_attr == SERDES_LANE_DSP_DFE1_LANE0_REG_28_CFG_DFE_BYPASS_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_28_cfg_en_ffe_out_to_snr_attr == SERDES_LANE_DSP_DFE1_LANE0_REG_28_CFG_EN_FFE_OUT_TO_SNR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_28_cfg_pre_slice_en_attr == SERDES_LANE_DSP_DFE1_LANE0_REG_28_CFG_PRE_SLICE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_29_dfe_coeff_post1_set0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_2_dfe_slice_level_0_set0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_2_dfe_slice_level_m1_set0_attr == 9'd342
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_2_dfe_slice_level_p1_set0_attr == 9'd170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_30_dfe_coeff_post1_set1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_31_dfe_coeff_post1_set2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_32_dfe_coeff_post1_set3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_33_dfe_coeff_post1_set4_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_34_dfe_coeff_post1_set5_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_35_dfe_coeff_post1_set6_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_36_dfe_coeff_post1_set7_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_37_dfe_coeff_broadcast_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_38_dsp_dfe1_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_38_dsp_dfe1_sec_acc_ctrl_broadcast_mode_attr == SERDES_LANE_DSP_DFE1_LANE0_REG_38_DSP_DFE1_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_38_dsp_dfe1_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_38_dsp_dfe1_sec_acc_ctrl_field_mask_write_en_attr == SERDES_LANE_DSP_DFE1_LANE0_REG_38_DSP_DFE1_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_38_dsp_dfe1_sec_acc_ctrl_load_preset_attr == SERDES_LANE_DSP_DFE1_LANE0_REG_38_DSP_DFE1_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_38_dsp_dfe1_sec_acc_ctrl_man_clear_on_read_attr == SERDES_LANE_DSP_DFE1_LANE0_REG_38_DSP_DFE1_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_38_dsp_dfe1_sec_acc_ctrl_man_self_clear_attr == SERDES_LANE_DSP_DFE1_LANE0_REG_38_DSP_DFE1_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_38_dsp_dfe1_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_38_dsp_dfe1_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_38_dsp_dfe1_sec_acc_ctrl_soft_reset_n_attr == SERDES_LANE_DSP_DFE1_LANE0_REG_38_DSP_DFE1_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_38_dsp_dfe1_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_39_dsp_dfe1_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_39_dsp_dfe1_reg2probe_en_attr == SERDES_LANE_DSP_DFE1_LANE0_REG_39_DSP_DFE1_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_3_dfe_slice_level_0_set1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_3_dfe_slice_level_m1_set1_attr == 9'd342
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_3_dfe_slice_level_p1_set1_attr == 9'd170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_4_dfe_slice_level_0_set2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_4_dfe_slice_level_m1_set2_attr == 9'd342
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_4_dfe_slice_level_p1_set2_attr == 9'd170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_5_dfe_slice_level_0_set3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_5_dfe_slice_level_m1_set3_attr == 9'd342
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_5_dfe_slice_level_p1_set3_attr == 9'd170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_6_dfe_slice_level_0_set4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_6_dfe_slice_level_m1_set4_attr == 9'd342
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_6_dfe_slice_level_p1_set4_attr == 9'd170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_7_dfe_slice_level_0_set5_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_7_dfe_slice_level_m1_set5_attr == 9'd342
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_7_dfe_slice_level_p1_set5_attr == 9'd170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_8_dfe_slice_level_0_set6_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_8_dfe_slice_level_m1_set6_attr == 9'd342
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_8_dfe_slice_level_p1_set6_attr == 9'd170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_9_dfe_slice_level_0_set7_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_9_dfe_slice_level_m1_set7_attr == 9'd342
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane0_reg_9_dfe_slice_level_p1_set7_attr == 9'd170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_10_dfe_err_slicer_p_broadcast_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_11_dfe_err_slicer_n_broadcast_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_12_dfe_err_slice_level_p1_set0_attr == 9'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_12_dfe_err_slice_level_p3_set0_attr == 9'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_13_dfe_err_slice_level_m1_set0_attr == 9'd480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_13_dfe_err_slice_level_m3_set0_attr == 9'd416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_14_dfe_err_slice_level_p1_set1_attr == 9'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_14_dfe_err_slice_level_p3_set1_attr == 9'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_15_dfe_err_slice_level_m1_set1_attr == 9'd480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_15_dfe_err_slice_level_m3_set1_attr == 9'd416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_16_dfe_err_slice_level_p1_set2_attr == 9'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_16_dfe_err_slice_level_p3_set2_attr == 9'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_17_dfe_err_slice_level_m1_set2_attr == 9'd480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_17_dfe_err_slice_level_m3_set2_attr == 9'd416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_18_dfe_err_slice_level_p1_set3_attr == 9'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_18_dfe_err_slice_level_p3_set3_attr == 9'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_19_dfe_err_slice_level_m1_set3_attr == 9'd480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_19_dfe_err_slice_level_m3_set3_attr == 9'd416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_1_dfe_slicer_broadcast_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_20_dfe_err_slice_level_p1_set4_attr == 9'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_20_dfe_err_slice_level_p3_set4_attr == 9'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_21_dfe_err_slice_level_m1_set4_attr == 9'd480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_21_dfe_err_slice_level_m3_set4_attr == 9'd416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_22_dfe_err_slice_level_p1_set5_attr == 9'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_22_dfe_err_slice_level_p3_set5_attr == 9'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_23_dfe_err_slice_level_m1_set5_attr == 9'd480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_23_dfe_err_slice_level_m3_set5_attr == 9'd416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_24_dfe_err_slice_level_p1_set6_attr == 9'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_24_dfe_err_slice_level_p3_set6_attr == 9'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_25_dfe_err_slice_level_m1_set6_attr == 9'd480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_25_dfe_err_slice_level_m3_set6_attr == 9'd416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_26_dfe_err_slice_level_p1_set7_attr == 9'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_26_dfe_err_slice_level_p3_set7_attr == 9'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_27_dfe_err_slice_level_m1_set7_attr == 9'd480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_27_dfe_err_slice_level_m3_set7_attr == 9'd416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_28_brk_dfe_cb_not_sat_in_dfe_attr == SERDES_LANE_DSP_DFE1_LANE1_REG_28_BRK_DFE_CB_NOT_SAT_IN_DFE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_28_cfg_cb_inv_n_err_attr == SERDES_LANE_DSP_DFE1_LANE1_REG_28_CFG_CB_INV_N_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_28_cfg_cb_inv_p_err_attr == SERDES_LANE_DSP_DFE1_LANE1_REG_28_CFG_CB_INV_P_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_28_cfg_dfe_bypass_en_attr == SERDES_LANE_DSP_DFE1_LANE1_REG_28_CFG_DFE_BYPASS_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_28_cfg_en_ffe_out_to_snr_attr == SERDES_LANE_DSP_DFE1_LANE1_REG_28_CFG_EN_FFE_OUT_TO_SNR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_28_cfg_pre_slice_en_attr == SERDES_LANE_DSP_DFE1_LANE1_REG_28_CFG_PRE_SLICE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_29_dfe_coeff_post1_set0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_2_dfe_slice_level_0_set0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_2_dfe_slice_level_m1_set0_attr == 9'd342
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_2_dfe_slice_level_p1_set0_attr == 9'd170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_30_dfe_coeff_post1_set1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_31_dfe_coeff_post1_set2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_32_dfe_coeff_post1_set3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_33_dfe_coeff_post1_set4_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_34_dfe_coeff_post1_set5_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_35_dfe_coeff_post1_set6_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_36_dfe_coeff_post1_set7_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_37_dfe_coeff_broadcast_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_38_dsp_dfe1_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_38_dsp_dfe1_sec_acc_ctrl_broadcast_mode_attr == SERDES_LANE_DSP_DFE1_LANE1_REG_38_DSP_DFE1_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_38_dsp_dfe1_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_38_dsp_dfe1_sec_acc_ctrl_field_mask_write_en_attr == SERDES_LANE_DSP_DFE1_LANE1_REG_38_DSP_DFE1_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_38_dsp_dfe1_sec_acc_ctrl_load_preset_attr == SERDES_LANE_DSP_DFE1_LANE1_REG_38_DSP_DFE1_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_38_dsp_dfe1_sec_acc_ctrl_man_clear_on_read_attr == SERDES_LANE_DSP_DFE1_LANE1_REG_38_DSP_DFE1_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_38_dsp_dfe1_sec_acc_ctrl_man_self_clear_attr == SERDES_LANE_DSP_DFE1_LANE1_REG_38_DSP_DFE1_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_38_dsp_dfe1_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_38_dsp_dfe1_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_38_dsp_dfe1_sec_acc_ctrl_soft_reset_n_attr == SERDES_LANE_DSP_DFE1_LANE1_REG_38_DSP_DFE1_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_38_dsp_dfe1_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_39_dsp_dfe1_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_39_dsp_dfe1_reg2probe_en_attr == SERDES_LANE_DSP_DFE1_LANE1_REG_39_DSP_DFE1_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_3_dfe_slice_level_0_set1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_3_dfe_slice_level_m1_set1_attr == 9'd342
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_3_dfe_slice_level_p1_set1_attr == 9'd170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_4_dfe_slice_level_0_set2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_4_dfe_slice_level_m1_set2_attr == 9'd342
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_4_dfe_slice_level_p1_set2_attr == 9'd170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_5_dfe_slice_level_0_set3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_5_dfe_slice_level_m1_set3_attr == 9'd342
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_5_dfe_slice_level_p1_set3_attr == 9'd170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_6_dfe_slice_level_0_set4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_6_dfe_slice_level_m1_set4_attr == 9'd342
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_6_dfe_slice_level_p1_set4_attr == 9'd170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_7_dfe_slice_level_0_set5_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_7_dfe_slice_level_m1_set5_attr == 9'd342
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_7_dfe_slice_level_p1_set5_attr == 9'd170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_8_dfe_slice_level_0_set6_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_8_dfe_slice_level_m1_set6_attr == 9'd342
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_8_dfe_slice_level_p1_set6_attr == 9'd170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_9_dfe_slice_level_0_set7_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_9_dfe_slice_level_m1_set7_attr == 9'd342
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane1_reg_9_dfe_slice_level_p1_set7_attr == 9'd170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_10_dfe_err_slicer_p_broadcast_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_11_dfe_err_slicer_n_broadcast_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_12_dfe_err_slice_level_p1_set0_attr == 9'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_12_dfe_err_slice_level_p3_set0_attr == 9'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_13_dfe_err_slice_level_m1_set0_attr == 9'd480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_13_dfe_err_slice_level_m3_set0_attr == 9'd416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_14_dfe_err_slice_level_p1_set1_attr == 9'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_14_dfe_err_slice_level_p3_set1_attr == 9'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_15_dfe_err_slice_level_m1_set1_attr == 9'd480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_15_dfe_err_slice_level_m3_set1_attr == 9'd416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_16_dfe_err_slice_level_p1_set2_attr == 9'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_16_dfe_err_slice_level_p3_set2_attr == 9'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_17_dfe_err_slice_level_m1_set2_attr == 9'd480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_17_dfe_err_slice_level_m3_set2_attr == 9'd416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_18_dfe_err_slice_level_p1_set3_attr == 9'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_18_dfe_err_slice_level_p3_set3_attr == 9'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_19_dfe_err_slice_level_m1_set3_attr == 9'd480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_19_dfe_err_slice_level_m3_set3_attr == 9'd416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_1_dfe_slicer_broadcast_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_20_dfe_err_slice_level_p1_set4_attr == 9'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_20_dfe_err_slice_level_p3_set4_attr == 9'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_21_dfe_err_slice_level_m1_set4_attr == 9'd480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_21_dfe_err_slice_level_m3_set4_attr == 9'd416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_22_dfe_err_slice_level_p1_set5_attr == 9'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_22_dfe_err_slice_level_p3_set5_attr == 9'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_23_dfe_err_slice_level_m1_set5_attr == 9'd480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_23_dfe_err_slice_level_m3_set5_attr == 9'd416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_24_dfe_err_slice_level_p1_set6_attr == 9'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_24_dfe_err_slice_level_p3_set6_attr == 9'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_25_dfe_err_slice_level_m1_set6_attr == 9'd480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_25_dfe_err_slice_level_m3_set6_attr == 9'd416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_26_dfe_err_slice_level_p1_set7_attr == 9'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_26_dfe_err_slice_level_p3_set7_attr == 9'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_27_dfe_err_slice_level_m1_set7_attr == 9'd480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_27_dfe_err_slice_level_m3_set7_attr == 9'd416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_28_brk_dfe_cb_not_sat_in_dfe_attr == SERDES_LANE_DSP_DFE1_LANE2_REG_28_BRK_DFE_CB_NOT_SAT_IN_DFE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_28_cfg_cb_inv_n_err_attr == SERDES_LANE_DSP_DFE1_LANE2_REG_28_CFG_CB_INV_N_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_28_cfg_cb_inv_p_err_attr == SERDES_LANE_DSP_DFE1_LANE2_REG_28_CFG_CB_INV_P_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_28_cfg_dfe_bypass_en_attr == SERDES_LANE_DSP_DFE1_LANE2_REG_28_CFG_DFE_BYPASS_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_28_cfg_en_ffe_out_to_snr_attr == SERDES_LANE_DSP_DFE1_LANE2_REG_28_CFG_EN_FFE_OUT_TO_SNR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_28_cfg_pre_slice_en_attr == SERDES_LANE_DSP_DFE1_LANE2_REG_28_CFG_PRE_SLICE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_29_dfe_coeff_post1_set0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_2_dfe_slice_level_0_set0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_2_dfe_slice_level_m1_set0_attr == 9'd342
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_2_dfe_slice_level_p1_set0_attr == 9'd170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_30_dfe_coeff_post1_set1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_31_dfe_coeff_post1_set2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_32_dfe_coeff_post1_set3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_33_dfe_coeff_post1_set4_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_34_dfe_coeff_post1_set5_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_35_dfe_coeff_post1_set6_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_36_dfe_coeff_post1_set7_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_37_dfe_coeff_broadcast_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_38_dsp_dfe1_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_38_dsp_dfe1_sec_acc_ctrl_broadcast_mode_attr == SERDES_LANE_DSP_DFE1_LANE2_REG_38_DSP_DFE1_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_38_dsp_dfe1_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_38_dsp_dfe1_sec_acc_ctrl_field_mask_write_en_attr == SERDES_LANE_DSP_DFE1_LANE2_REG_38_DSP_DFE1_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_38_dsp_dfe1_sec_acc_ctrl_load_preset_attr == SERDES_LANE_DSP_DFE1_LANE2_REG_38_DSP_DFE1_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_38_dsp_dfe1_sec_acc_ctrl_man_clear_on_read_attr == SERDES_LANE_DSP_DFE1_LANE2_REG_38_DSP_DFE1_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_38_dsp_dfe1_sec_acc_ctrl_man_self_clear_attr == SERDES_LANE_DSP_DFE1_LANE2_REG_38_DSP_DFE1_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_38_dsp_dfe1_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_38_dsp_dfe1_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_38_dsp_dfe1_sec_acc_ctrl_soft_reset_n_attr == SERDES_LANE_DSP_DFE1_LANE2_REG_38_DSP_DFE1_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_38_dsp_dfe1_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_39_dsp_dfe1_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_39_dsp_dfe1_reg2probe_en_attr == SERDES_LANE_DSP_DFE1_LANE2_REG_39_DSP_DFE1_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_3_dfe_slice_level_0_set1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_3_dfe_slice_level_m1_set1_attr == 9'd342
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_3_dfe_slice_level_p1_set1_attr == 9'd170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_4_dfe_slice_level_0_set2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_4_dfe_slice_level_m1_set2_attr == 9'd342
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_4_dfe_slice_level_p1_set2_attr == 9'd170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_5_dfe_slice_level_0_set3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_5_dfe_slice_level_m1_set3_attr == 9'd342
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_5_dfe_slice_level_p1_set3_attr == 9'd170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_6_dfe_slice_level_0_set4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_6_dfe_slice_level_m1_set4_attr == 9'd342
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_6_dfe_slice_level_p1_set4_attr == 9'd170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_7_dfe_slice_level_0_set5_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_7_dfe_slice_level_m1_set5_attr == 9'd342
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_7_dfe_slice_level_p1_set5_attr == 9'd170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_8_dfe_slice_level_0_set6_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_8_dfe_slice_level_m1_set6_attr == 9'd342
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_8_dfe_slice_level_p1_set6_attr == 9'd170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_9_dfe_slice_level_0_set7_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_9_dfe_slice_level_m1_set7_attr == 9'd342
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane2_reg_9_dfe_slice_level_p1_set7_attr == 9'd170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_10_dfe_err_slicer_p_broadcast_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_11_dfe_err_slicer_n_broadcast_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_12_dfe_err_slice_level_p1_set0_attr == 9'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_12_dfe_err_slice_level_p3_set0_attr == 9'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_13_dfe_err_slice_level_m1_set0_attr == 9'd480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_13_dfe_err_slice_level_m3_set0_attr == 9'd416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_14_dfe_err_slice_level_p1_set1_attr == 9'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_14_dfe_err_slice_level_p3_set1_attr == 9'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_15_dfe_err_slice_level_m1_set1_attr == 9'd480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_15_dfe_err_slice_level_m3_set1_attr == 9'd416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_16_dfe_err_slice_level_p1_set2_attr == 9'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_16_dfe_err_slice_level_p3_set2_attr == 9'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_17_dfe_err_slice_level_m1_set2_attr == 9'd480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_17_dfe_err_slice_level_m3_set2_attr == 9'd416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_18_dfe_err_slice_level_p1_set3_attr == 9'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_18_dfe_err_slice_level_p3_set3_attr == 9'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_19_dfe_err_slice_level_m1_set3_attr == 9'd480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_19_dfe_err_slice_level_m3_set3_attr == 9'd416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_1_dfe_slicer_broadcast_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_20_dfe_err_slice_level_p1_set4_attr == 9'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_20_dfe_err_slice_level_p3_set4_attr == 9'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_21_dfe_err_slice_level_m1_set4_attr == 9'd480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_21_dfe_err_slice_level_m3_set4_attr == 9'd416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_22_dfe_err_slice_level_p1_set5_attr == 9'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_22_dfe_err_slice_level_p3_set5_attr == 9'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_23_dfe_err_slice_level_m1_set5_attr == 9'd480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_23_dfe_err_slice_level_m3_set5_attr == 9'd416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_24_dfe_err_slice_level_p1_set6_attr == 9'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_24_dfe_err_slice_level_p3_set6_attr == 9'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_25_dfe_err_slice_level_m1_set6_attr == 9'd480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_25_dfe_err_slice_level_m3_set6_attr == 9'd416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_26_dfe_err_slice_level_p1_set7_attr == 9'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_26_dfe_err_slice_level_p3_set7_attr == 9'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_27_dfe_err_slice_level_m1_set7_attr == 9'd480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_27_dfe_err_slice_level_m3_set7_attr == 9'd416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_28_brk_dfe_cb_not_sat_in_dfe_attr == SERDES_LANE_DSP_DFE1_LANE3_REG_28_BRK_DFE_CB_NOT_SAT_IN_DFE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_28_cfg_cb_inv_n_err_attr == SERDES_LANE_DSP_DFE1_LANE3_REG_28_CFG_CB_INV_N_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_28_cfg_cb_inv_p_err_attr == SERDES_LANE_DSP_DFE1_LANE3_REG_28_CFG_CB_INV_P_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_28_cfg_dfe_bypass_en_attr == SERDES_LANE_DSP_DFE1_LANE3_REG_28_CFG_DFE_BYPASS_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_28_cfg_en_ffe_out_to_snr_attr == SERDES_LANE_DSP_DFE1_LANE3_REG_28_CFG_EN_FFE_OUT_TO_SNR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_28_cfg_pre_slice_en_attr == SERDES_LANE_DSP_DFE1_LANE3_REG_28_CFG_PRE_SLICE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_29_dfe_coeff_post1_set0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_2_dfe_slice_level_0_set0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_2_dfe_slice_level_m1_set0_attr == 9'd342
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_2_dfe_slice_level_p1_set0_attr == 9'd170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_30_dfe_coeff_post1_set1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_31_dfe_coeff_post1_set2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_32_dfe_coeff_post1_set3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_33_dfe_coeff_post1_set4_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_34_dfe_coeff_post1_set5_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_35_dfe_coeff_post1_set6_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_36_dfe_coeff_post1_set7_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_37_dfe_coeff_broadcast_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_38_dsp_dfe1_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_38_dsp_dfe1_sec_acc_ctrl_broadcast_mode_attr == SERDES_LANE_DSP_DFE1_LANE3_REG_38_DSP_DFE1_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_38_dsp_dfe1_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_38_dsp_dfe1_sec_acc_ctrl_field_mask_write_en_attr == SERDES_LANE_DSP_DFE1_LANE3_REG_38_DSP_DFE1_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_38_dsp_dfe1_sec_acc_ctrl_load_preset_attr == SERDES_LANE_DSP_DFE1_LANE3_REG_38_DSP_DFE1_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_38_dsp_dfe1_sec_acc_ctrl_man_clear_on_read_attr == SERDES_LANE_DSP_DFE1_LANE3_REG_38_DSP_DFE1_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_38_dsp_dfe1_sec_acc_ctrl_man_self_clear_attr == SERDES_LANE_DSP_DFE1_LANE3_REG_38_DSP_DFE1_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_38_dsp_dfe1_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_38_dsp_dfe1_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_38_dsp_dfe1_sec_acc_ctrl_soft_reset_n_attr == SERDES_LANE_DSP_DFE1_LANE3_REG_38_DSP_DFE1_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_38_dsp_dfe1_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_39_dsp_dfe1_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_39_dsp_dfe1_reg2probe_en_attr == SERDES_LANE_DSP_DFE1_LANE3_REG_39_DSP_DFE1_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_3_dfe_slice_level_0_set1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_3_dfe_slice_level_m1_set1_attr == 9'd342
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_3_dfe_slice_level_p1_set1_attr == 9'd170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_4_dfe_slice_level_0_set2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_4_dfe_slice_level_m1_set2_attr == 9'd342
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_4_dfe_slice_level_p1_set2_attr == 9'd170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_5_dfe_slice_level_0_set3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_5_dfe_slice_level_m1_set3_attr == 9'd342
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_5_dfe_slice_level_p1_set3_attr == 9'd170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_6_dfe_slice_level_0_set4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_6_dfe_slice_level_m1_set4_attr == 9'd342
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_6_dfe_slice_level_p1_set4_attr == 9'd170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_7_dfe_slice_level_0_set5_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_7_dfe_slice_level_m1_set5_attr == 9'd342
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_7_dfe_slice_level_p1_set5_attr == 9'd170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_8_dfe_slice_level_0_set6_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_8_dfe_slice_level_m1_set6_attr == 9'd342
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_8_dfe_slice_level_p1_set6_attr == 9'd170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_9_dfe_slice_level_0_set7_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_9_dfe_slice_level_m1_set7_attr == 9'd342
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_dfe1_lane3_reg_9_dfe_slice_level_p1_set7_attr == 9'd170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_10_ffe_coeff_set1_coeff_post1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_10_ffe_coeff_set1_coeff_post2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_10_ffe_coeff_set1_coeff_post3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_10_ffe_coeff_set1_coeff_post4_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_11_ffe_coeff_set1_coeff_post5_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_11_ffe_coeff_set1_coeff_post6_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_11_ffe_coeff_set1_coeff_post7_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_11_ffe_coeff_set1_coeff_post8_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_12_ffe_coeff_set1_coeff_post10_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_12_ffe_coeff_set1_coeff_post11_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_12_ffe_coeff_set1_coeff_post12_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_12_ffe_coeff_set1_coeff_post9_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_13_ffe_coeff_set1_coeff_post13_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_13_ffe_coeff_set1_coeff_pre1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_13_ffe_coeff_set1_coeff_pre2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_13_ffe_coeff_set1_coeff_pre3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_14_ffe_coeff_set2_coeff_post1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_14_ffe_coeff_set2_coeff_post2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_14_ffe_coeff_set2_coeff_post3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_14_ffe_coeff_set2_coeff_post4_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_15_ffe_coeff_set2_coeff_post5_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_15_ffe_coeff_set2_coeff_post6_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_15_ffe_coeff_set2_coeff_post7_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_15_ffe_coeff_set2_coeff_post8_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_16_ffe_coeff_set2_coeff_post10_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_16_ffe_coeff_set2_coeff_post11_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_16_ffe_coeff_set2_coeff_post12_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_16_ffe_coeff_set2_coeff_post9_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_17_ffe_coeff_set2_coeff_post13_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_17_ffe_coeff_set2_coeff_pre1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_17_ffe_coeff_set2_coeff_pre2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_17_ffe_coeff_set2_coeff_pre3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_18_ffe_coeff_set3_coeff_post1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_18_ffe_coeff_set3_coeff_post2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_18_ffe_coeff_set3_coeff_post3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_18_ffe_coeff_set3_coeff_post4_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_19_ffe_coeff_set3_coeff_post5_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_19_ffe_coeff_set3_coeff_post6_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_19_ffe_coeff_set3_coeff_post7_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_19_ffe_coeff_set3_coeff_post8_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_1_cfg_brk_ffe_no_sat_in_ffe_2nd_attr == SERDES_LANE_DSP_FFE_1_LANE0_REG_1_CFG_BRK_FFE_NO_SAT_IN_FFE_2ND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_1_cfg_en_dft_lut_data_out_attr == SERDES_LANE_DSP_FFE_1_LANE0_REG_1_CFG_EN_DFT_LUT_DATA_OUT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_1_float_tap_position_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_20_ffe_coeff_set3_coeff_post10_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_20_ffe_coeff_set3_coeff_post11_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_20_ffe_coeff_set3_coeff_post12_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_20_ffe_coeff_set3_coeff_post9_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_21_ffe_coeff_set3_coeff_post13_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_21_ffe_coeff_set3_coeff_pre1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_21_ffe_coeff_set3_coeff_pre2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_21_ffe_coeff_set3_coeff_pre3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_22_ffe_coeff_set4_coeff_post1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_22_ffe_coeff_set4_coeff_post2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_22_ffe_coeff_set4_coeff_post3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_22_ffe_coeff_set4_coeff_post4_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_23_ffe_coeff_set4_coeff_post5_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_23_ffe_coeff_set4_coeff_post6_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_23_ffe_coeff_set4_coeff_post7_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_23_ffe_coeff_set4_coeff_post8_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_24_ffe_coeff_set4_coeff_post10_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_24_ffe_coeff_set4_coeff_post11_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_24_ffe_coeff_set4_coeff_post12_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_24_ffe_coeff_set4_coeff_post9_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_25_ffe_coeff_set4_coeff_post13_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_25_ffe_coeff_set4_coeff_pre1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_25_ffe_coeff_set4_coeff_pre2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_25_ffe_coeff_set4_coeff_pre3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_26_ffe_coeff_set5_coeff_post1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_26_ffe_coeff_set5_coeff_post2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_26_ffe_coeff_set5_coeff_post3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_26_ffe_coeff_set5_coeff_post4_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_27_ffe_coeff_set5_coeff_post5_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_27_ffe_coeff_set5_coeff_post6_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_27_ffe_coeff_set5_coeff_post7_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_27_ffe_coeff_set5_coeff_post8_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_28_ffe_coeff_set5_coeff_post10_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_28_ffe_coeff_set5_coeff_post11_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_28_ffe_coeff_set5_coeff_post12_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_28_ffe_coeff_set5_coeff_post9_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_29_ffe_coeff_set5_coeff_post13_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_29_ffe_coeff_set5_coeff_pre1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_29_ffe_coeff_set5_coeff_pre2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_29_ffe_coeff_set5_coeff_pre3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_2_ffe_coeff_broadcast_group_1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_30_ffe_coeff_set6_coeff_post1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_30_ffe_coeff_set6_coeff_post2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_30_ffe_coeff_set6_coeff_post3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_30_ffe_coeff_set6_coeff_post4_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_31_ffe_coeff_set6_coeff_post5_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_31_ffe_coeff_set6_coeff_post6_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_31_ffe_coeff_set6_coeff_post7_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_31_ffe_coeff_set6_coeff_post8_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_32_ffe_coeff_set6_coeff_post10_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_32_ffe_coeff_set6_coeff_post11_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_32_ffe_coeff_set6_coeff_post12_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_32_ffe_coeff_set6_coeff_post9_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_33_ffe_coeff_set6_coeff_post13_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_33_ffe_coeff_set6_coeff_pre1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_33_ffe_coeff_set6_coeff_pre2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_33_ffe_coeff_set6_coeff_pre3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_34_ffe_coeff_set7_coeff_post1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_34_ffe_coeff_set7_coeff_post2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_34_ffe_coeff_set7_coeff_post3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_34_ffe_coeff_set7_coeff_post4_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_35_ffe_coeff_set7_coeff_post5_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_35_ffe_coeff_set7_coeff_post6_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_35_ffe_coeff_set7_coeff_post7_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_35_ffe_coeff_set7_coeff_post8_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_36_ffe_coeff_set7_coeff_post10_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_36_ffe_coeff_set7_coeff_post11_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_36_ffe_coeff_set7_coeff_post12_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_36_ffe_coeff_set7_coeff_post9_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_37_ffe_coeff_set7_coeff_post13_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_37_ffe_coeff_set7_coeff_pre1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_37_ffe_coeff_set7_coeff_pre2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_37_ffe_coeff_set7_coeff_pre3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_38_dsp_ffe_1_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_38_dsp_ffe_1_sec_acc_ctrl_broadcast_mode_attr == SERDES_LANE_DSP_FFE_1_LANE0_REG_38_DSP_FFE_1_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_38_dsp_ffe_1_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_38_dsp_ffe_1_sec_acc_ctrl_field_mask_write_en_attr == SERDES_LANE_DSP_FFE_1_LANE0_REG_38_DSP_FFE_1_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_38_dsp_ffe_1_sec_acc_ctrl_load_preset_attr == SERDES_LANE_DSP_FFE_1_LANE0_REG_38_DSP_FFE_1_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_38_dsp_ffe_1_sec_acc_ctrl_man_clear_on_read_attr == SERDES_LANE_DSP_FFE_1_LANE0_REG_38_DSP_FFE_1_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_38_dsp_ffe_1_sec_acc_ctrl_man_self_clear_attr == SERDES_LANE_DSP_FFE_1_LANE0_REG_38_DSP_FFE_1_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_38_dsp_ffe_1_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_38_dsp_ffe_1_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_38_dsp_ffe_1_sec_acc_ctrl_soft_reset_n_attr == SERDES_LANE_DSP_FFE_1_LANE0_REG_38_DSP_FFE_1_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_38_dsp_ffe_1_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_39_dsp_ffe_1_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_39_dsp_ffe_1_reg2probe_en_attr == SERDES_LANE_DSP_FFE_1_LANE0_REG_39_DSP_FFE_1_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_3_ffe_coeff_broadcast_group_2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_40_float_ffe_coeff_broadcast_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_41_float_ffe_set0_coeff_0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_41_float_ffe_set0_coeff_1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_41_float_ffe_set0_coeff_2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_41_float_ffe_set0_coeff_3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_42_float_ffe_set1_coeff_0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_42_float_ffe_set1_coeff_1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_42_float_ffe_set1_coeff_2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_42_float_ffe_set1_coeff_3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_43_float_ffe_set2_coeff_0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_43_float_ffe_set2_coeff_1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_43_float_ffe_set2_coeff_2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_43_float_ffe_set2_coeff_3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_44_float_ffe_set3_coeff_0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_44_float_ffe_set3_coeff_1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_44_float_ffe_set3_coeff_2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_44_float_ffe_set3_coeff_3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_45_float_ffe_set4_coeff_0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_45_float_ffe_set4_coeff_1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_45_float_ffe_set4_coeff_2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_45_float_ffe_set4_coeff_3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_46_float_ffe_set5_coeff_0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_46_float_ffe_set5_coeff_1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_46_float_ffe_set5_coeff_2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_46_float_ffe_set5_coeff_3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_47_float_ffe_set6_coeff_0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_47_float_ffe_set6_coeff_1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_47_float_ffe_set6_coeff_2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_47_float_ffe_set6_coeff_3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_48_float_ffe_set7_coeff_0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_48_float_ffe_set7_coeff_1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_48_float_ffe_set7_coeff_2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_48_float_ffe_set7_coeff_3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_4_ffe_coeff_broadcast_group_3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_5_ffe_coeff_broadcast_group_4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_6_ffe_coeff_set0_coeff_post1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_6_ffe_coeff_set0_coeff_post2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_6_ffe_coeff_set0_coeff_post3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_6_ffe_coeff_set0_coeff_post4_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_7_ffe_coeff_set0_coeff_post5_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_7_ffe_coeff_set0_coeff_post6_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_7_ffe_coeff_set0_coeff_post7_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_7_ffe_coeff_set0_coeff_post8_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_8_ffe_coeff_set0_coeff_post10_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_8_ffe_coeff_set0_coeff_post11_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_8_ffe_coeff_set0_coeff_post12_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_8_ffe_coeff_set0_coeff_post9_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_9_ffe_coeff_set0_coeff_post13_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_9_ffe_coeff_set0_coeff_pre1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_9_ffe_coeff_set0_coeff_pre2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane0_reg_9_ffe_coeff_set0_coeff_pre3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_10_ffe_coeff_set1_coeff_post1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_10_ffe_coeff_set1_coeff_post2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_10_ffe_coeff_set1_coeff_post3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_10_ffe_coeff_set1_coeff_post4_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_11_ffe_coeff_set1_coeff_post5_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_11_ffe_coeff_set1_coeff_post6_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_11_ffe_coeff_set1_coeff_post7_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_11_ffe_coeff_set1_coeff_post8_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_12_ffe_coeff_set1_coeff_post10_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_12_ffe_coeff_set1_coeff_post11_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_12_ffe_coeff_set1_coeff_post12_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_12_ffe_coeff_set1_coeff_post9_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_13_ffe_coeff_set1_coeff_post13_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_13_ffe_coeff_set1_coeff_pre1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_13_ffe_coeff_set1_coeff_pre2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_13_ffe_coeff_set1_coeff_pre3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_14_ffe_coeff_set2_coeff_post1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_14_ffe_coeff_set2_coeff_post2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_14_ffe_coeff_set2_coeff_post3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_14_ffe_coeff_set2_coeff_post4_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_15_ffe_coeff_set2_coeff_post5_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_15_ffe_coeff_set2_coeff_post6_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_15_ffe_coeff_set2_coeff_post7_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_15_ffe_coeff_set2_coeff_post8_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_16_ffe_coeff_set2_coeff_post10_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_16_ffe_coeff_set2_coeff_post11_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_16_ffe_coeff_set2_coeff_post12_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_16_ffe_coeff_set2_coeff_post9_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_17_ffe_coeff_set2_coeff_post13_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_17_ffe_coeff_set2_coeff_pre1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_17_ffe_coeff_set2_coeff_pre2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_17_ffe_coeff_set2_coeff_pre3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_18_ffe_coeff_set3_coeff_post1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_18_ffe_coeff_set3_coeff_post2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_18_ffe_coeff_set3_coeff_post3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_18_ffe_coeff_set3_coeff_post4_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_19_ffe_coeff_set3_coeff_post5_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_19_ffe_coeff_set3_coeff_post6_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_19_ffe_coeff_set3_coeff_post7_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_19_ffe_coeff_set3_coeff_post8_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_1_cfg_brk_ffe_no_sat_in_ffe_2nd_attr == SERDES_LANE_DSP_FFE_1_LANE1_REG_1_CFG_BRK_FFE_NO_SAT_IN_FFE_2ND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_1_cfg_en_dft_lut_data_out_attr == SERDES_LANE_DSP_FFE_1_LANE1_REG_1_CFG_EN_DFT_LUT_DATA_OUT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_1_float_tap_position_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_20_ffe_coeff_set3_coeff_post10_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_20_ffe_coeff_set3_coeff_post11_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_20_ffe_coeff_set3_coeff_post12_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_20_ffe_coeff_set3_coeff_post9_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_21_ffe_coeff_set3_coeff_post13_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_21_ffe_coeff_set3_coeff_pre1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_21_ffe_coeff_set3_coeff_pre2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_21_ffe_coeff_set3_coeff_pre3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_22_ffe_coeff_set4_coeff_post1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_22_ffe_coeff_set4_coeff_post2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_22_ffe_coeff_set4_coeff_post3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_22_ffe_coeff_set4_coeff_post4_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_23_ffe_coeff_set4_coeff_post5_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_23_ffe_coeff_set4_coeff_post6_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_23_ffe_coeff_set4_coeff_post7_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_23_ffe_coeff_set4_coeff_post8_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_24_ffe_coeff_set4_coeff_post10_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_24_ffe_coeff_set4_coeff_post11_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_24_ffe_coeff_set4_coeff_post12_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_24_ffe_coeff_set4_coeff_post9_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_25_ffe_coeff_set4_coeff_post13_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_25_ffe_coeff_set4_coeff_pre1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_25_ffe_coeff_set4_coeff_pre2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_25_ffe_coeff_set4_coeff_pre3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_26_ffe_coeff_set5_coeff_post1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_26_ffe_coeff_set5_coeff_post2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_26_ffe_coeff_set5_coeff_post3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_26_ffe_coeff_set5_coeff_post4_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_27_ffe_coeff_set5_coeff_post5_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_27_ffe_coeff_set5_coeff_post6_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_27_ffe_coeff_set5_coeff_post7_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_27_ffe_coeff_set5_coeff_post8_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_28_ffe_coeff_set5_coeff_post10_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_28_ffe_coeff_set5_coeff_post11_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_28_ffe_coeff_set5_coeff_post12_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_28_ffe_coeff_set5_coeff_post9_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_29_ffe_coeff_set5_coeff_post13_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_29_ffe_coeff_set5_coeff_pre1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_29_ffe_coeff_set5_coeff_pre2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_29_ffe_coeff_set5_coeff_pre3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_2_ffe_coeff_broadcast_group_1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_30_ffe_coeff_set6_coeff_post1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_30_ffe_coeff_set6_coeff_post2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_30_ffe_coeff_set6_coeff_post3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_30_ffe_coeff_set6_coeff_post4_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_31_ffe_coeff_set6_coeff_post5_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_31_ffe_coeff_set6_coeff_post6_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_31_ffe_coeff_set6_coeff_post7_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_31_ffe_coeff_set6_coeff_post8_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_32_ffe_coeff_set6_coeff_post10_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_32_ffe_coeff_set6_coeff_post11_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_32_ffe_coeff_set6_coeff_post12_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_32_ffe_coeff_set6_coeff_post9_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_33_ffe_coeff_set6_coeff_post13_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_33_ffe_coeff_set6_coeff_pre1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_33_ffe_coeff_set6_coeff_pre2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_33_ffe_coeff_set6_coeff_pre3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_34_ffe_coeff_set7_coeff_post1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_34_ffe_coeff_set7_coeff_post2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_34_ffe_coeff_set7_coeff_post3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_34_ffe_coeff_set7_coeff_post4_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_35_ffe_coeff_set7_coeff_post5_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_35_ffe_coeff_set7_coeff_post6_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_35_ffe_coeff_set7_coeff_post7_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_35_ffe_coeff_set7_coeff_post8_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_36_ffe_coeff_set7_coeff_post10_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_36_ffe_coeff_set7_coeff_post11_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_36_ffe_coeff_set7_coeff_post12_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_36_ffe_coeff_set7_coeff_post9_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_37_ffe_coeff_set7_coeff_post13_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_37_ffe_coeff_set7_coeff_pre1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_37_ffe_coeff_set7_coeff_pre2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_37_ffe_coeff_set7_coeff_pre3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_38_dsp_ffe_1_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_38_dsp_ffe_1_sec_acc_ctrl_broadcast_mode_attr == SERDES_LANE_DSP_FFE_1_LANE1_REG_38_DSP_FFE_1_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_38_dsp_ffe_1_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_38_dsp_ffe_1_sec_acc_ctrl_field_mask_write_en_attr == SERDES_LANE_DSP_FFE_1_LANE1_REG_38_DSP_FFE_1_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_38_dsp_ffe_1_sec_acc_ctrl_load_preset_attr == SERDES_LANE_DSP_FFE_1_LANE1_REG_38_DSP_FFE_1_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_38_dsp_ffe_1_sec_acc_ctrl_man_clear_on_read_attr == SERDES_LANE_DSP_FFE_1_LANE1_REG_38_DSP_FFE_1_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_38_dsp_ffe_1_sec_acc_ctrl_man_self_clear_attr == SERDES_LANE_DSP_FFE_1_LANE1_REG_38_DSP_FFE_1_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_38_dsp_ffe_1_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_38_dsp_ffe_1_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_38_dsp_ffe_1_sec_acc_ctrl_soft_reset_n_attr == SERDES_LANE_DSP_FFE_1_LANE1_REG_38_DSP_FFE_1_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_38_dsp_ffe_1_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_39_dsp_ffe_1_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_39_dsp_ffe_1_reg2probe_en_attr == SERDES_LANE_DSP_FFE_1_LANE1_REG_39_DSP_FFE_1_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_3_ffe_coeff_broadcast_group_2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_40_float_ffe_coeff_broadcast_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_41_float_ffe_set0_coeff_0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_41_float_ffe_set0_coeff_1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_41_float_ffe_set0_coeff_2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_41_float_ffe_set0_coeff_3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_42_float_ffe_set1_coeff_0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_42_float_ffe_set1_coeff_1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_42_float_ffe_set1_coeff_2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_42_float_ffe_set1_coeff_3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_43_float_ffe_set2_coeff_0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_43_float_ffe_set2_coeff_1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_43_float_ffe_set2_coeff_2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_43_float_ffe_set2_coeff_3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_44_float_ffe_set3_coeff_0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_44_float_ffe_set3_coeff_1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_44_float_ffe_set3_coeff_2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_44_float_ffe_set3_coeff_3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_45_float_ffe_set4_coeff_0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_45_float_ffe_set4_coeff_1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_45_float_ffe_set4_coeff_2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_45_float_ffe_set4_coeff_3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_46_float_ffe_set5_coeff_0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_46_float_ffe_set5_coeff_1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_46_float_ffe_set5_coeff_2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_46_float_ffe_set5_coeff_3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_47_float_ffe_set6_coeff_0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_47_float_ffe_set6_coeff_1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_47_float_ffe_set6_coeff_2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_47_float_ffe_set6_coeff_3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_48_float_ffe_set7_coeff_0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_48_float_ffe_set7_coeff_1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_48_float_ffe_set7_coeff_2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_48_float_ffe_set7_coeff_3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_4_ffe_coeff_broadcast_group_3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_5_ffe_coeff_broadcast_group_4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_6_ffe_coeff_set0_coeff_post1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_6_ffe_coeff_set0_coeff_post2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_6_ffe_coeff_set0_coeff_post3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_6_ffe_coeff_set0_coeff_post4_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_7_ffe_coeff_set0_coeff_post5_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_7_ffe_coeff_set0_coeff_post6_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_7_ffe_coeff_set0_coeff_post7_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_7_ffe_coeff_set0_coeff_post8_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_8_ffe_coeff_set0_coeff_post10_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_8_ffe_coeff_set0_coeff_post11_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_8_ffe_coeff_set0_coeff_post12_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_8_ffe_coeff_set0_coeff_post9_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_9_ffe_coeff_set0_coeff_post13_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_9_ffe_coeff_set0_coeff_pre1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_9_ffe_coeff_set0_coeff_pre2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane1_reg_9_ffe_coeff_set0_coeff_pre3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_10_ffe_coeff_set1_coeff_post1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_10_ffe_coeff_set1_coeff_post2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_10_ffe_coeff_set1_coeff_post3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_10_ffe_coeff_set1_coeff_post4_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_11_ffe_coeff_set1_coeff_post5_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_11_ffe_coeff_set1_coeff_post6_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_11_ffe_coeff_set1_coeff_post7_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_11_ffe_coeff_set1_coeff_post8_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_12_ffe_coeff_set1_coeff_post10_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_12_ffe_coeff_set1_coeff_post11_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_12_ffe_coeff_set1_coeff_post12_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_12_ffe_coeff_set1_coeff_post9_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_13_ffe_coeff_set1_coeff_post13_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_13_ffe_coeff_set1_coeff_pre1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_13_ffe_coeff_set1_coeff_pre2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_13_ffe_coeff_set1_coeff_pre3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_14_ffe_coeff_set2_coeff_post1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_14_ffe_coeff_set2_coeff_post2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_14_ffe_coeff_set2_coeff_post3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_14_ffe_coeff_set2_coeff_post4_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_15_ffe_coeff_set2_coeff_post5_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_15_ffe_coeff_set2_coeff_post6_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_15_ffe_coeff_set2_coeff_post7_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_15_ffe_coeff_set2_coeff_post8_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_16_ffe_coeff_set2_coeff_post10_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_16_ffe_coeff_set2_coeff_post11_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_16_ffe_coeff_set2_coeff_post12_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_16_ffe_coeff_set2_coeff_post9_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_17_ffe_coeff_set2_coeff_post13_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_17_ffe_coeff_set2_coeff_pre1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_17_ffe_coeff_set2_coeff_pre2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_17_ffe_coeff_set2_coeff_pre3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_18_ffe_coeff_set3_coeff_post1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_18_ffe_coeff_set3_coeff_post2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_18_ffe_coeff_set3_coeff_post3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_18_ffe_coeff_set3_coeff_post4_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_19_ffe_coeff_set3_coeff_post5_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_19_ffe_coeff_set3_coeff_post6_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_19_ffe_coeff_set3_coeff_post7_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_19_ffe_coeff_set3_coeff_post8_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_1_cfg_brk_ffe_no_sat_in_ffe_2nd_attr == SERDES_LANE_DSP_FFE_1_LANE2_REG_1_CFG_BRK_FFE_NO_SAT_IN_FFE_2ND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_1_cfg_en_dft_lut_data_out_attr == SERDES_LANE_DSP_FFE_1_LANE2_REG_1_CFG_EN_DFT_LUT_DATA_OUT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_1_float_tap_position_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_20_ffe_coeff_set3_coeff_post10_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_20_ffe_coeff_set3_coeff_post11_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_20_ffe_coeff_set3_coeff_post12_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_20_ffe_coeff_set3_coeff_post9_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_21_ffe_coeff_set3_coeff_post13_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_21_ffe_coeff_set3_coeff_pre1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_21_ffe_coeff_set3_coeff_pre2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_21_ffe_coeff_set3_coeff_pre3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_22_ffe_coeff_set4_coeff_post1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_22_ffe_coeff_set4_coeff_post2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_22_ffe_coeff_set4_coeff_post3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_22_ffe_coeff_set4_coeff_post4_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_23_ffe_coeff_set4_coeff_post5_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_23_ffe_coeff_set4_coeff_post6_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_23_ffe_coeff_set4_coeff_post7_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_23_ffe_coeff_set4_coeff_post8_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_24_ffe_coeff_set4_coeff_post10_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_24_ffe_coeff_set4_coeff_post11_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_24_ffe_coeff_set4_coeff_post12_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_24_ffe_coeff_set4_coeff_post9_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_25_ffe_coeff_set4_coeff_post13_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_25_ffe_coeff_set4_coeff_pre1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_25_ffe_coeff_set4_coeff_pre2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_25_ffe_coeff_set4_coeff_pre3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_26_ffe_coeff_set5_coeff_post1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_26_ffe_coeff_set5_coeff_post2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_26_ffe_coeff_set5_coeff_post3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_26_ffe_coeff_set5_coeff_post4_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_27_ffe_coeff_set5_coeff_post5_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_27_ffe_coeff_set5_coeff_post6_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_27_ffe_coeff_set5_coeff_post7_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_27_ffe_coeff_set5_coeff_post8_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_28_ffe_coeff_set5_coeff_post10_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_28_ffe_coeff_set5_coeff_post11_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_28_ffe_coeff_set5_coeff_post12_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_28_ffe_coeff_set5_coeff_post9_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_29_ffe_coeff_set5_coeff_post13_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_29_ffe_coeff_set5_coeff_pre1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_29_ffe_coeff_set5_coeff_pre2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_29_ffe_coeff_set5_coeff_pre3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_2_ffe_coeff_broadcast_group_1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_30_ffe_coeff_set6_coeff_post1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_30_ffe_coeff_set6_coeff_post2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_30_ffe_coeff_set6_coeff_post3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_30_ffe_coeff_set6_coeff_post4_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_31_ffe_coeff_set6_coeff_post5_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_31_ffe_coeff_set6_coeff_post6_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_31_ffe_coeff_set6_coeff_post7_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_31_ffe_coeff_set6_coeff_post8_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_32_ffe_coeff_set6_coeff_post10_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_32_ffe_coeff_set6_coeff_post11_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_32_ffe_coeff_set6_coeff_post12_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_32_ffe_coeff_set6_coeff_post9_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_33_ffe_coeff_set6_coeff_post13_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_33_ffe_coeff_set6_coeff_pre1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_33_ffe_coeff_set6_coeff_pre2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_33_ffe_coeff_set6_coeff_pre3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_34_ffe_coeff_set7_coeff_post1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_34_ffe_coeff_set7_coeff_post2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_34_ffe_coeff_set7_coeff_post3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_34_ffe_coeff_set7_coeff_post4_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_35_ffe_coeff_set7_coeff_post5_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_35_ffe_coeff_set7_coeff_post6_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_35_ffe_coeff_set7_coeff_post7_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_35_ffe_coeff_set7_coeff_post8_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_36_ffe_coeff_set7_coeff_post10_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_36_ffe_coeff_set7_coeff_post11_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_36_ffe_coeff_set7_coeff_post12_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_36_ffe_coeff_set7_coeff_post9_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_37_ffe_coeff_set7_coeff_post13_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_37_ffe_coeff_set7_coeff_pre1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_37_ffe_coeff_set7_coeff_pre2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_37_ffe_coeff_set7_coeff_pre3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_38_dsp_ffe_1_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_38_dsp_ffe_1_sec_acc_ctrl_broadcast_mode_attr == SERDES_LANE_DSP_FFE_1_LANE2_REG_38_DSP_FFE_1_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_38_dsp_ffe_1_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_38_dsp_ffe_1_sec_acc_ctrl_field_mask_write_en_attr == SERDES_LANE_DSP_FFE_1_LANE2_REG_38_DSP_FFE_1_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_38_dsp_ffe_1_sec_acc_ctrl_load_preset_attr == SERDES_LANE_DSP_FFE_1_LANE2_REG_38_DSP_FFE_1_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_38_dsp_ffe_1_sec_acc_ctrl_man_clear_on_read_attr == SERDES_LANE_DSP_FFE_1_LANE2_REG_38_DSP_FFE_1_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_38_dsp_ffe_1_sec_acc_ctrl_man_self_clear_attr == SERDES_LANE_DSP_FFE_1_LANE2_REG_38_DSP_FFE_1_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_38_dsp_ffe_1_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_38_dsp_ffe_1_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_38_dsp_ffe_1_sec_acc_ctrl_soft_reset_n_attr == SERDES_LANE_DSP_FFE_1_LANE2_REG_38_DSP_FFE_1_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_38_dsp_ffe_1_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_39_dsp_ffe_1_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_39_dsp_ffe_1_reg2probe_en_attr == SERDES_LANE_DSP_FFE_1_LANE2_REG_39_DSP_FFE_1_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_3_ffe_coeff_broadcast_group_2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_40_float_ffe_coeff_broadcast_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_41_float_ffe_set0_coeff_0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_41_float_ffe_set0_coeff_1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_41_float_ffe_set0_coeff_2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_41_float_ffe_set0_coeff_3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_42_float_ffe_set1_coeff_0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_42_float_ffe_set1_coeff_1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_42_float_ffe_set1_coeff_2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_42_float_ffe_set1_coeff_3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_43_float_ffe_set2_coeff_0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_43_float_ffe_set2_coeff_1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_43_float_ffe_set2_coeff_2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_43_float_ffe_set2_coeff_3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_44_float_ffe_set3_coeff_0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_44_float_ffe_set3_coeff_1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_44_float_ffe_set3_coeff_2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_44_float_ffe_set3_coeff_3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_45_float_ffe_set4_coeff_0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_45_float_ffe_set4_coeff_1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_45_float_ffe_set4_coeff_2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_45_float_ffe_set4_coeff_3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_46_float_ffe_set5_coeff_0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_46_float_ffe_set5_coeff_1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_46_float_ffe_set5_coeff_2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_46_float_ffe_set5_coeff_3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_47_float_ffe_set6_coeff_0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_47_float_ffe_set6_coeff_1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_47_float_ffe_set6_coeff_2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_47_float_ffe_set6_coeff_3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_48_float_ffe_set7_coeff_0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_48_float_ffe_set7_coeff_1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_48_float_ffe_set7_coeff_2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_48_float_ffe_set7_coeff_3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_4_ffe_coeff_broadcast_group_3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_5_ffe_coeff_broadcast_group_4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_6_ffe_coeff_set0_coeff_post1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_6_ffe_coeff_set0_coeff_post2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_6_ffe_coeff_set0_coeff_post3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_6_ffe_coeff_set0_coeff_post4_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_7_ffe_coeff_set0_coeff_post5_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_7_ffe_coeff_set0_coeff_post6_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_7_ffe_coeff_set0_coeff_post7_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_7_ffe_coeff_set0_coeff_post8_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_8_ffe_coeff_set0_coeff_post10_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_8_ffe_coeff_set0_coeff_post11_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_8_ffe_coeff_set0_coeff_post12_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_8_ffe_coeff_set0_coeff_post9_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_9_ffe_coeff_set0_coeff_post13_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_9_ffe_coeff_set0_coeff_pre1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_9_ffe_coeff_set0_coeff_pre2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane2_reg_9_ffe_coeff_set0_coeff_pre3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_10_ffe_coeff_set1_coeff_post1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_10_ffe_coeff_set1_coeff_post2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_10_ffe_coeff_set1_coeff_post3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_10_ffe_coeff_set1_coeff_post4_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_11_ffe_coeff_set1_coeff_post5_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_11_ffe_coeff_set1_coeff_post6_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_11_ffe_coeff_set1_coeff_post7_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_11_ffe_coeff_set1_coeff_post8_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_12_ffe_coeff_set1_coeff_post10_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_12_ffe_coeff_set1_coeff_post11_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_12_ffe_coeff_set1_coeff_post12_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_12_ffe_coeff_set1_coeff_post9_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_13_ffe_coeff_set1_coeff_post13_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_13_ffe_coeff_set1_coeff_pre1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_13_ffe_coeff_set1_coeff_pre2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_13_ffe_coeff_set1_coeff_pre3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_14_ffe_coeff_set2_coeff_post1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_14_ffe_coeff_set2_coeff_post2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_14_ffe_coeff_set2_coeff_post3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_14_ffe_coeff_set2_coeff_post4_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_15_ffe_coeff_set2_coeff_post5_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_15_ffe_coeff_set2_coeff_post6_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_15_ffe_coeff_set2_coeff_post7_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_15_ffe_coeff_set2_coeff_post8_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_16_ffe_coeff_set2_coeff_post10_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_16_ffe_coeff_set2_coeff_post11_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_16_ffe_coeff_set2_coeff_post12_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_16_ffe_coeff_set2_coeff_post9_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_17_ffe_coeff_set2_coeff_post13_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_17_ffe_coeff_set2_coeff_pre1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_17_ffe_coeff_set2_coeff_pre2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_17_ffe_coeff_set2_coeff_pre3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_18_ffe_coeff_set3_coeff_post1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_18_ffe_coeff_set3_coeff_post2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_18_ffe_coeff_set3_coeff_post3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_18_ffe_coeff_set3_coeff_post4_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_19_ffe_coeff_set3_coeff_post5_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_19_ffe_coeff_set3_coeff_post6_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_19_ffe_coeff_set3_coeff_post7_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_19_ffe_coeff_set3_coeff_post8_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_1_cfg_brk_ffe_no_sat_in_ffe_2nd_attr == SERDES_LANE_DSP_FFE_1_LANE3_REG_1_CFG_BRK_FFE_NO_SAT_IN_FFE_2ND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_1_cfg_en_dft_lut_data_out_attr == SERDES_LANE_DSP_FFE_1_LANE3_REG_1_CFG_EN_DFT_LUT_DATA_OUT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_1_float_tap_position_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_20_ffe_coeff_set3_coeff_post10_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_20_ffe_coeff_set3_coeff_post11_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_20_ffe_coeff_set3_coeff_post12_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_20_ffe_coeff_set3_coeff_post9_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_21_ffe_coeff_set3_coeff_post13_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_21_ffe_coeff_set3_coeff_pre1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_21_ffe_coeff_set3_coeff_pre2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_21_ffe_coeff_set3_coeff_pre3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_22_ffe_coeff_set4_coeff_post1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_22_ffe_coeff_set4_coeff_post2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_22_ffe_coeff_set4_coeff_post3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_22_ffe_coeff_set4_coeff_post4_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_23_ffe_coeff_set4_coeff_post5_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_23_ffe_coeff_set4_coeff_post6_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_23_ffe_coeff_set4_coeff_post7_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_23_ffe_coeff_set4_coeff_post8_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_24_ffe_coeff_set4_coeff_post10_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_24_ffe_coeff_set4_coeff_post11_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_24_ffe_coeff_set4_coeff_post12_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_24_ffe_coeff_set4_coeff_post9_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_25_ffe_coeff_set4_coeff_post13_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_25_ffe_coeff_set4_coeff_pre1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_25_ffe_coeff_set4_coeff_pre2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_25_ffe_coeff_set4_coeff_pre3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_26_ffe_coeff_set5_coeff_post1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_26_ffe_coeff_set5_coeff_post2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_26_ffe_coeff_set5_coeff_post3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_26_ffe_coeff_set5_coeff_post4_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_27_ffe_coeff_set5_coeff_post5_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_27_ffe_coeff_set5_coeff_post6_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_27_ffe_coeff_set5_coeff_post7_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_27_ffe_coeff_set5_coeff_post8_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_28_ffe_coeff_set5_coeff_post10_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_28_ffe_coeff_set5_coeff_post11_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_28_ffe_coeff_set5_coeff_post12_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_28_ffe_coeff_set5_coeff_post9_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_29_ffe_coeff_set5_coeff_post13_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_29_ffe_coeff_set5_coeff_pre1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_29_ffe_coeff_set5_coeff_pre2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_29_ffe_coeff_set5_coeff_pre3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_2_ffe_coeff_broadcast_group_1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_30_ffe_coeff_set6_coeff_post1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_30_ffe_coeff_set6_coeff_post2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_30_ffe_coeff_set6_coeff_post3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_30_ffe_coeff_set6_coeff_post4_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_31_ffe_coeff_set6_coeff_post5_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_31_ffe_coeff_set6_coeff_post6_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_31_ffe_coeff_set6_coeff_post7_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_31_ffe_coeff_set6_coeff_post8_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_32_ffe_coeff_set6_coeff_post10_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_32_ffe_coeff_set6_coeff_post11_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_32_ffe_coeff_set6_coeff_post12_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_32_ffe_coeff_set6_coeff_post9_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_33_ffe_coeff_set6_coeff_post13_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_33_ffe_coeff_set6_coeff_pre1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_33_ffe_coeff_set6_coeff_pre2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_33_ffe_coeff_set6_coeff_pre3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_34_ffe_coeff_set7_coeff_post1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_34_ffe_coeff_set7_coeff_post2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_34_ffe_coeff_set7_coeff_post3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_34_ffe_coeff_set7_coeff_post4_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_35_ffe_coeff_set7_coeff_post5_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_35_ffe_coeff_set7_coeff_post6_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_35_ffe_coeff_set7_coeff_post7_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_35_ffe_coeff_set7_coeff_post8_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_36_ffe_coeff_set7_coeff_post10_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_36_ffe_coeff_set7_coeff_post11_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_36_ffe_coeff_set7_coeff_post12_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_36_ffe_coeff_set7_coeff_post9_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_37_ffe_coeff_set7_coeff_post13_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_37_ffe_coeff_set7_coeff_pre1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_37_ffe_coeff_set7_coeff_pre2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_37_ffe_coeff_set7_coeff_pre3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_38_dsp_ffe_1_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_38_dsp_ffe_1_sec_acc_ctrl_broadcast_mode_attr == SERDES_LANE_DSP_FFE_1_LANE3_REG_38_DSP_FFE_1_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_38_dsp_ffe_1_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_38_dsp_ffe_1_sec_acc_ctrl_field_mask_write_en_attr == SERDES_LANE_DSP_FFE_1_LANE3_REG_38_DSP_FFE_1_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_38_dsp_ffe_1_sec_acc_ctrl_load_preset_attr == SERDES_LANE_DSP_FFE_1_LANE3_REG_38_DSP_FFE_1_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_38_dsp_ffe_1_sec_acc_ctrl_man_clear_on_read_attr == SERDES_LANE_DSP_FFE_1_LANE3_REG_38_DSP_FFE_1_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_38_dsp_ffe_1_sec_acc_ctrl_man_self_clear_attr == SERDES_LANE_DSP_FFE_1_LANE3_REG_38_DSP_FFE_1_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_38_dsp_ffe_1_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_38_dsp_ffe_1_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_38_dsp_ffe_1_sec_acc_ctrl_soft_reset_n_attr == SERDES_LANE_DSP_FFE_1_LANE3_REG_38_DSP_FFE_1_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_38_dsp_ffe_1_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_39_dsp_ffe_1_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_39_dsp_ffe_1_reg2probe_en_attr == SERDES_LANE_DSP_FFE_1_LANE3_REG_39_DSP_FFE_1_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_3_ffe_coeff_broadcast_group_2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_40_float_ffe_coeff_broadcast_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_41_float_ffe_set0_coeff_0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_41_float_ffe_set0_coeff_1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_41_float_ffe_set0_coeff_2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_41_float_ffe_set0_coeff_3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_42_float_ffe_set1_coeff_0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_42_float_ffe_set1_coeff_1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_42_float_ffe_set1_coeff_2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_42_float_ffe_set1_coeff_3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_43_float_ffe_set2_coeff_0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_43_float_ffe_set2_coeff_1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_43_float_ffe_set2_coeff_2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_43_float_ffe_set2_coeff_3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_44_float_ffe_set3_coeff_0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_44_float_ffe_set3_coeff_1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_44_float_ffe_set3_coeff_2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_44_float_ffe_set3_coeff_3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_45_float_ffe_set4_coeff_0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_45_float_ffe_set4_coeff_1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_45_float_ffe_set4_coeff_2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_45_float_ffe_set4_coeff_3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_46_float_ffe_set5_coeff_0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_46_float_ffe_set5_coeff_1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_46_float_ffe_set5_coeff_2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_46_float_ffe_set5_coeff_3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_47_float_ffe_set6_coeff_0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_47_float_ffe_set6_coeff_1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_47_float_ffe_set6_coeff_2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_47_float_ffe_set6_coeff_3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_48_float_ffe_set7_coeff_0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_48_float_ffe_set7_coeff_1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_48_float_ffe_set7_coeff_2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_48_float_ffe_set7_coeff_3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_4_ffe_coeff_broadcast_group_3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_5_ffe_coeff_broadcast_group_4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_6_ffe_coeff_set0_coeff_post1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_6_ffe_coeff_set0_coeff_post2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_6_ffe_coeff_set0_coeff_post3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_6_ffe_coeff_set0_coeff_post4_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_7_ffe_coeff_set0_coeff_post5_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_7_ffe_coeff_set0_coeff_post6_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_7_ffe_coeff_set0_coeff_post7_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_7_ffe_coeff_set0_coeff_post8_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_8_ffe_coeff_set0_coeff_post10_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_8_ffe_coeff_set0_coeff_post11_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_8_ffe_coeff_set0_coeff_post12_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_8_ffe_coeff_set0_coeff_post9_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_9_ffe_coeff_set0_coeff_post13_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_9_ffe_coeff_set0_coeff_pre1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_9_ffe_coeff_set0_coeff_pre2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_dsp_ffe_1_lane3_reg_9_ffe_coeff_set0_coeff_pre3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_10_idig_pll_spare_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_12_idig_pll_en_h_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_12_IDIG_PLL_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_12_idig_pll_resetb_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_12_IDIG_PLL_RESETB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_14_cfg_avg_eng_bit_in_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_14_cfg_avg_eng_count_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_14_cfg_avg_eng_probe_bit_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_14_cfg_avg_eng_start_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_14_CFG_AVG_ENG_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_15_cfg_avg_eng_limit_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_18_cfg_force_apb2strb_bridge_state_en_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_18_CFG_FORCE_APB2STRB_BRIDGE_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_18_cfg_force_apb2strb_bridge_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_19_cfg_cdr_apb2apb_bridge_timeout_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_19_cfg_force_cdr_apb2apb_bridge_src_state_en_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_19_CFG_FORCE_CDR_APB2APB_BRIDGE_SRC_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_19_cfg_force_cdr_apb2apb_bridge_src_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_19_cfg_force_cdr_apb2apb_bridge_trgt_state_en_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_19_CFG_FORCE_CDR_APB2APB_BRIDGE_TRGT_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_19_cfg_force_cdr_apb2apb_bridge_trgt_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_1_cfg_lane_dig_tx2rx_loopback_en_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_1_CFG_LANE_DIG_TX2RX_LOOPBACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_1_cfg_rx_grey_sym_lut_attr == 8'd228
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_1_cfg_rx_inv_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_1_CFG_RX_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_1_cfg_rx_precode_enable_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_1_CFG_RX_PRECODE_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_1_cfg_rx_probe_bus_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_1_cfg_rx_swizzle_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_1_cfg_rx_unused_sar_inv_data_path_cb_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_1_CFG_RX_UNUSED_SAR_INV_DATA_PATH_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_1_cfg_rx_unused_sar_inv_vga_adapt_cb_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_1_CFG_RX_UNUSED_SAR_INV_VGA_ADAPT_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_1_cfg_use_cdr_data_as_data_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_1_CFG_USE_CDR_DATA_AS_DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_20_cfg_dfe_apb2apb_bridge_timeout_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_20_cfg_force_dfe_apb2apb_bridge_src_state_en_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_20_CFG_FORCE_DFE_APB2APB_BRIDGE_SRC_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_20_cfg_force_dfe_apb2apb_bridge_src_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_20_cfg_force_dfe_apb2apb_bridge_trgt_state_en_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_20_CFG_FORCE_DFE_APB2APB_BRIDGE_TRGT_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_20_cfg_force_dfe_apb2apb_bridge_trgt_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_21_cfg_ffe_apb2apb_bridge_timeout_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_21_cfg_force_ffe_apb2apb_bridge_src_state_en_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_21_CFG_FORCE_FFE_APB2APB_BRIDGE_SRC_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_21_cfg_force_ffe_apb2apb_bridge_src_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_21_cfg_force_ffe_apb2apb_bridge_trgt_state_en_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_21_CFG_FORCE_FFE_APB2APB_BRIDGE_TRGT_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_21_cfg_force_ffe_apb2apb_bridge_trgt_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_22_cfg_adapt_apb2apb_bridge_timeout_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_22_cfg_force_adapt_apb2apb_bridge_src_state_en_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_22_CFG_FORCE_ADAPT_APB2APB_BRIDGE_SRC_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_22_cfg_force_adapt_apb2apb_bridge_src_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_22_cfg_force_adapt_apb2apb_bridge_trgt_state_en_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_22_CFG_FORCE_ADAPT_APB2APB_BRIDGE_TRGT_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_22_cfg_force_adapt_apb2apb_bridge_trgt_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_23_cfg_acc_ctrl_field_mask_write_en_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_23_CFG_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_23_cfg_stbl_time_aftr_strb_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_23_cfg_stbl_time_bfr_strb_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_23_cfg_strb_pulse_width_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_24_adc_nob_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_24_cfg_lane_mode_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_24_fake_training_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_24_FAKE_TRAINING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_24_rx_reconverge_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_24_RX_RECONVERGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_24_tfl_enable_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_24_TFL_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_25_dp_rx_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_25_dp_tx_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_25_rx_adc_active_sar_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_25_rx_pam_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_25_tx_pam_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_26_idig_adc_spare_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_26_idig_clkmux_spare_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_26_idig_lane_spare_attr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_28_lane_ctrl_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_28_lane_ctrl_sec_acc_ctrl_broadcast_mode_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_28_LANE_CTRL_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_28_lane_ctrl_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_28_lane_ctrl_sec_acc_ctrl_field_mask_write_en_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_28_LANE_CTRL_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_28_lane_ctrl_sec_acc_ctrl_load_preset_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_28_LANE_CTRL_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_28_lane_ctrl_sec_acc_ctrl_man_clear_on_read_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_28_LANE_CTRL_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_28_lane_ctrl_sec_acc_ctrl_man_self_clear_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_28_LANE_CTRL_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_28_lane_ctrl_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_28_lane_ctrl_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_28_lane_ctrl_sec_acc_ctrl_soft_reset_n_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_28_LANE_CTRL_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_28_lane_ctrl_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_29_lane_ctrl_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_29_lane_ctrl_reg2probe_en_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_29_LANE_CTRL_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_2_cfg_lane_dig_rx2tx_loopback_en_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_2_CFG_LANE_DIG_RX2TX_LOOPBACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_2_cfg_tx_bus_take_dft_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_2_CFG_TX_BUS_TAKE_DFT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_2_cfg_tx_grey_sym_lut_attr == 8'd228
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_2_cfg_tx_inv_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_2_CFG_TX_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_2_cfg_tx_lane_enable_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_2_CFG_TX_LANE_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_2_cfg_tx_precode_enable_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_2_CFG_TX_PRECODE_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_2_cfg_tx_probe_bus_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_2_cfg_tx_swizzle_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_30_metrics_1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_31_metrics_2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_32_fw_calib_fsm_state_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_32_fw_dsp_fsm_state_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_32_fw_tfl_fsm_state_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_33_fw_fsm_state1_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_33_fw_fsm_state2_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_33_fw_fsm_state3_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_34_lane_cal_error_code_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_34_lane_cal_state_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_3_cfg_tx_err_inj_en_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_3_CFG_TX_ERR_INJ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_3_cfg_tx_err_inj_mask_cfg_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_3_cfg_tx_err_inj_mask_rotate_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_3_CFG_TX_ERR_INJ_MASK_ROTATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_3_cfg_tx_err_inj_rate_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_4_cfg_tx_err_inj_trig_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_4_CFG_TX_ERR_INJ_TRIG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_5_cfg_tx_err_inj_mask_load_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_5_CFG_TX_ERR_INJ_MASK_LOAD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_6_idig_tx_dig_spare_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_6_tx_piso_reset_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_6_TX_PISO_RESET_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_7_idig_lclbias_pd_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_7_IDIG_LCLBIAS_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_7_idig_pll_dfx_bi_en_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_7_IDIG_PLL_DFX_BI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_7_idig_txpath_first_mux_control_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_7_IDIG_TXPATH_FIRST_MUX_CONTROL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_7_idig_txpath_second_mux_control_attr == SERDES_LANE_LANE_CTRL_LANE0_REG_7_IDIG_TXPATH_SECOND_MUX_CONTROL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane0_reg_7_link_up_cntr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_10_idig_pll_spare_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_12_idig_pll_en_h_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_12_IDIG_PLL_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_12_idig_pll_resetb_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_12_IDIG_PLL_RESETB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_14_cfg_avg_eng_bit_in_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_14_cfg_avg_eng_count_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_14_cfg_avg_eng_probe_bit_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_14_cfg_avg_eng_start_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_14_CFG_AVG_ENG_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_15_cfg_avg_eng_limit_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_18_cfg_force_apb2strb_bridge_state_en_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_18_CFG_FORCE_APB2STRB_BRIDGE_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_18_cfg_force_apb2strb_bridge_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_19_cfg_cdr_apb2apb_bridge_timeout_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_19_cfg_force_cdr_apb2apb_bridge_src_state_en_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_19_CFG_FORCE_CDR_APB2APB_BRIDGE_SRC_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_19_cfg_force_cdr_apb2apb_bridge_src_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_19_cfg_force_cdr_apb2apb_bridge_trgt_state_en_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_19_CFG_FORCE_CDR_APB2APB_BRIDGE_TRGT_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_19_cfg_force_cdr_apb2apb_bridge_trgt_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_1_cfg_lane_dig_tx2rx_loopback_en_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_1_CFG_LANE_DIG_TX2RX_LOOPBACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_1_cfg_rx_grey_sym_lut_attr == 8'd228
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_1_cfg_rx_inv_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_1_CFG_RX_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_1_cfg_rx_precode_enable_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_1_CFG_RX_PRECODE_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_1_cfg_rx_probe_bus_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_1_cfg_rx_swizzle_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_1_cfg_rx_unused_sar_inv_data_path_cb_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_1_CFG_RX_UNUSED_SAR_INV_DATA_PATH_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_1_cfg_rx_unused_sar_inv_vga_adapt_cb_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_1_CFG_RX_UNUSED_SAR_INV_VGA_ADAPT_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_1_cfg_use_cdr_data_as_data_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_1_CFG_USE_CDR_DATA_AS_DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_20_cfg_dfe_apb2apb_bridge_timeout_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_20_cfg_force_dfe_apb2apb_bridge_src_state_en_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_20_CFG_FORCE_DFE_APB2APB_BRIDGE_SRC_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_20_cfg_force_dfe_apb2apb_bridge_src_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_20_cfg_force_dfe_apb2apb_bridge_trgt_state_en_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_20_CFG_FORCE_DFE_APB2APB_BRIDGE_TRGT_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_20_cfg_force_dfe_apb2apb_bridge_trgt_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_21_cfg_ffe_apb2apb_bridge_timeout_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_21_cfg_force_ffe_apb2apb_bridge_src_state_en_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_21_CFG_FORCE_FFE_APB2APB_BRIDGE_SRC_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_21_cfg_force_ffe_apb2apb_bridge_src_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_21_cfg_force_ffe_apb2apb_bridge_trgt_state_en_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_21_CFG_FORCE_FFE_APB2APB_BRIDGE_TRGT_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_21_cfg_force_ffe_apb2apb_bridge_trgt_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_22_cfg_adapt_apb2apb_bridge_timeout_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_22_cfg_force_adapt_apb2apb_bridge_src_state_en_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_22_CFG_FORCE_ADAPT_APB2APB_BRIDGE_SRC_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_22_cfg_force_adapt_apb2apb_bridge_src_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_22_cfg_force_adapt_apb2apb_bridge_trgt_state_en_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_22_CFG_FORCE_ADAPT_APB2APB_BRIDGE_TRGT_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_22_cfg_force_adapt_apb2apb_bridge_trgt_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_23_cfg_acc_ctrl_field_mask_write_en_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_23_CFG_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_23_cfg_stbl_time_aftr_strb_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_23_cfg_stbl_time_bfr_strb_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_23_cfg_strb_pulse_width_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_24_adc_nob_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_24_cfg_lane_mode_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_24_fake_training_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_24_FAKE_TRAINING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_24_rx_reconverge_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_24_RX_RECONVERGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_24_tfl_enable_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_24_TFL_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_25_dp_rx_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_25_dp_tx_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_25_rx_adc_active_sar_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_25_rx_pam_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_25_tx_pam_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_26_idig_adc_spare_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_26_idig_clkmux_spare_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_26_idig_lane_spare_attr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_28_lane_ctrl_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_28_lane_ctrl_sec_acc_ctrl_broadcast_mode_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_28_LANE_CTRL_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_28_lane_ctrl_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_28_lane_ctrl_sec_acc_ctrl_field_mask_write_en_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_28_LANE_CTRL_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_28_lane_ctrl_sec_acc_ctrl_load_preset_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_28_LANE_CTRL_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_28_lane_ctrl_sec_acc_ctrl_man_clear_on_read_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_28_LANE_CTRL_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_28_lane_ctrl_sec_acc_ctrl_man_self_clear_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_28_LANE_CTRL_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_28_lane_ctrl_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_28_lane_ctrl_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_28_lane_ctrl_sec_acc_ctrl_soft_reset_n_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_28_LANE_CTRL_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_28_lane_ctrl_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_29_lane_ctrl_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_29_lane_ctrl_reg2probe_en_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_29_LANE_CTRL_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_2_cfg_lane_dig_rx2tx_loopback_en_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_2_CFG_LANE_DIG_RX2TX_LOOPBACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_2_cfg_tx_bus_take_dft_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_2_CFG_TX_BUS_TAKE_DFT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_2_cfg_tx_grey_sym_lut_attr == 8'd228
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_2_cfg_tx_inv_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_2_CFG_TX_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_2_cfg_tx_lane_enable_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_2_CFG_TX_LANE_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_2_cfg_tx_precode_enable_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_2_CFG_TX_PRECODE_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_2_cfg_tx_probe_bus_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_2_cfg_tx_swizzle_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_30_metrics_1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_31_metrics_2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_32_fw_calib_fsm_state_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_32_fw_dsp_fsm_state_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_32_fw_tfl_fsm_state_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_33_fw_fsm_state1_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_33_fw_fsm_state2_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_33_fw_fsm_state3_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_34_lane_cal_error_code_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_34_lane_cal_state_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_3_cfg_tx_err_inj_en_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_3_CFG_TX_ERR_INJ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_3_cfg_tx_err_inj_mask_cfg_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_3_cfg_tx_err_inj_mask_rotate_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_3_CFG_TX_ERR_INJ_MASK_ROTATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_3_cfg_tx_err_inj_rate_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_4_cfg_tx_err_inj_trig_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_4_CFG_TX_ERR_INJ_TRIG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_5_cfg_tx_err_inj_mask_load_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_5_CFG_TX_ERR_INJ_MASK_LOAD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_6_idig_tx_dig_spare_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_6_tx_piso_reset_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_6_TX_PISO_RESET_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_7_idig_lclbias_pd_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_7_IDIG_LCLBIAS_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_7_idig_pll_dfx_bi_en_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_7_IDIG_PLL_DFX_BI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_7_idig_txpath_first_mux_control_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_7_IDIG_TXPATH_FIRST_MUX_CONTROL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_7_idig_txpath_second_mux_control_attr == SERDES_LANE_LANE_CTRL_LANE1_REG_7_IDIG_TXPATH_SECOND_MUX_CONTROL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane1_reg_7_link_up_cntr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_10_idig_pll_spare_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_12_idig_pll_en_h_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_12_IDIG_PLL_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_12_idig_pll_resetb_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_12_IDIG_PLL_RESETB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_14_cfg_avg_eng_bit_in_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_14_cfg_avg_eng_count_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_14_cfg_avg_eng_probe_bit_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_14_cfg_avg_eng_start_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_14_CFG_AVG_ENG_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_15_cfg_avg_eng_limit_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_18_cfg_force_apb2strb_bridge_state_en_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_18_CFG_FORCE_APB2STRB_BRIDGE_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_18_cfg_force_apb2strb_bridge_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_19_cfg_cdr_apb2apb_bridge_timeout_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_19_cfg_force_cdr_apb2apb_bridge_src_state_en_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_19_CFG_FORCE_CDR_APB2APB_BRIDGE_SRC_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_19_cfg_force_cdr_apb2apb_bridge_src_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_19_cfg_force_cdr_apb2apb_bridge_trgt_state_en_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_19_CFG_FORCE_CDR_APB2APB_BRIDGE_TRGT_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_19_cfg_force_cdr_apb2apb_bridge_trgt_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_1_cfg_lane_dig_tx2rx_loopback_en_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_1_CFG_LANE_DIG_TX2RX_LOOPBACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_1_cfg_rx_grey_sym_lut_attr == 8'd228
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_1_cfg_rx_inv_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_1_CFG_RX_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_1_cfg_rx_precode_enable_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_1_CFG_RX_PRECODE_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_1_cfg_rx_probe_bus_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_1_cfg_rx_swizzle_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_1_cfg_rx_unused_sar_inv_data_path_cb_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_1_CFG_RX_UNUSED_SAR_INV_DATA_PATH_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_1_cfg_rx_unused_sar_inv_vga_adapt_cb_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_1_CFG_RX_UNUSED_SAR_INV_VGA_ADAPT_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_1_cfg_use_cdr_data_as_data_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_1_CFG_USE_CDR_DATA_AS_DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_20_cfg_dfe_apb2apb_bridge_timeout_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_20_cfg_force_dfe_apb2apb_bridge_src_state_en_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_20_CFG_FORCE_DFE_APB2APB_BRIDGE_SRC_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_20_cfg_force_dfe_apb2apb_bridge_src_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_20_cfg_force_dfe_apb2apb_bridge_trgt_state_en_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_20_CFG_FORCE_DFE_APB2APB_BRIDGE_TRGT_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_20_cfg_force_dfe_apb2apb_bridge_trgt_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_21_cfg_ffe_apb2apb_bridge_timeout_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_21_cfg_force_ffe_apb2apb_bridge_src_state_en_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_21_CFG_FORCE_FFE_APB2APB_BRIDGE_SRC_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_21_cfg_force_ffe_apb2apb_bridge_src_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_21_cfg_force_ffe_apb2apb_bridge_trgt_state_en_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_21_CFG_FORCE_FFE_APB2APB_BRIDGE_TRGT_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_21_cfg_force_ffe_apb2apb_bridge_trgt_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_22_cfg_adapt_apb2apb_bridge_timeout_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_22_cfg_force_adapt_apb2apb_bridge_src_state_en_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_22_CFG_FORCE_ADAPT_APB2APB_BRIDGE_SRC_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_22_cfg_force_adapt_apb2apb_bridge_src_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_22_cfg_force_adapt_apb2apb_bridge_trgt_state_en_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_22_CFG_FORCE_ADAPT_APB2APB_BRIDGE_TRGT_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_22_cfg_force_adapt_apb2apb_bridge_trgt_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_23_cfg_acc_ctrl_field_mask_write_en_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_23_CFG_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_23_cfg_stbl_time_aftr_strb_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_23_cfg_stbl_time_bfr_strb_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_23_cfg_strb_pulse_width_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_24_adc_nob_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_24_cfg_lane_mode_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_24_fake_training_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_24_FAKE_TRAINING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_24_rx_reconverge_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_24_RX_RECONVERGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_24_tfl_enable_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_24_TFL_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_25_dp_rx_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_25_dp_tx_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_25_rx_adc_active_sar_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_25_rx_pam_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_25_tx_pam_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_26_idig_adc_spare_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_26_idig_clkmux_spare_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_26_idig_lane_spare_attr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_28_lane_ctrl_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_28_lane_ctrl_sec_acc_ctrl_broadcast_mode_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_28_LANE_CTRL_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_28_lane_ctrl_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_28_lane_ctrl_sec_acc_ctrl_field_mask_write_en_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_28_LANE_CTRL_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_28_lane_ctrl_sec_acc_ctrl_load_preset_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_28_LANE_CTRL_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_28_lane_ctrl_sec_acc_ctrl_man_clear_on_read_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_28_LANE_CTRL_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_28_lane_ctrl_sec_acc_ctrl_man_self_clear_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_28_LANE_CTRL_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_28_lane_ctrl_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_28_lane_ctrl_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_28_lane_ctrl_sec_acc_ctrl_soft_reset_n_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_28_LANE_CTRL_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_28_lane_ctrl_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_29_lane_ctrl_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_29_lane_ctrl_reg2probe_en_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_29_LANE_CTRL_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_2_cfg_lane_dig_rx2tx_loopback_en_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_2_CFG_LANE_DIG_RX2TX_LOOPBACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_2_cfg_tx_bus_take_dft_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_2_CFG_TX_BUS_TAKE_DFT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_2_cfg_tx_grey_sym_lut_attr == 8'd228
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_2_cfg_tx_inv_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_2_CFG_TX_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_2_cfg_tx_lane_enable_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_2_CFG_TX_LANE_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_2_cfg_tx_precode_enable_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_2_CFG_TX_PRECODE_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_2_cfg_tx_probe_bus_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_2_cfg_tx_swizzle_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_30_metrics_1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_31_metrics_2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_32_fw_calib_fsm_state_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_32_fw_dsp_fsm_state_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_32_fw_tfl_fsm_state_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_33_fw_fsm_state1_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_33_fw_fsm_state2_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_33_fw_fsm_state3_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_34_lane_cal_error_code_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_34_lane_cal_state_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_3_cfg_tx_err_inj_en_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_3_CFG_TX_ERR_INJ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_3_cfg_tx_err_inj_mask_cfg_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_3_cfg_tx_err_inj_mask_rotate_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_3_CFG_TX_ERR_INJ_MASK_ROTATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_3_cfg_tx_err_inj_rate_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_4_cfg_tx_err_inj_trig_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_4_CFG_TX_ERR_INJ_TRIG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_5_cfg_tx_err_inj_mask_load_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_5_CFG_TX_ERR_INJ_MASK_LOAD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_6_idig_tx_dig_spare_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_6_tx_piso_reset_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_6_TX_PISO_RESET_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_7_idig_lclbias_pd_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_7_IDIG_LCLBIAS_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_7_idig_pll_dfx_bi_en_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_7_IDIG_PLL_DFX_BI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_7_idig_txpath_first_mux_control_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_7_IDIG_TXPATH_FIRST_MUX_CONTROL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_7_idig_txpath_second_mux_control_attr == SERDES_LANE_LANE_CTRL_LANE2_REG_7_IDIG_TXPATH_SECOND_MUX_CONTROL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane2_reg_7_link_up_cntr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_10_idig_pll_spare_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_12_idig_pll_en_h_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_12_IDIG_PLL_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_12_idig_pll_resetb_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_12_IDIG_PLL_RESETB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_14_cfg_avg_eng_bit_in_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_14_cfg_avg_eng_count_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_14_cfg_avg_eng_probe_bit_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_14_cfg_avg_eng_start_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_14_CFG_AVG_ENG_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_15_cfg_avg_eng_limit_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_18_cfg_force_apb2strb_bridge_state_en_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_18_CFG_FORCE_APB2STRB_BRIDGE_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_18_cfg_force_apb2strb_bridge_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_19_cfg_cdr_apb2apb_bridge_timeout_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_19_cfg_force_cdr_apb2apb_bridge_src_state_en_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_19_CFG_FORCE_CDR_APB2APB_BRIDGE_SRC_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_19_cfg_force_cdr_apb2apb_bridge_src_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_19_cfg_force_cdr_apb2apb_bridge_trgt_state_en_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_19_CFG_FORCE_CDR_APB2APB_BRIDGE_TRGT_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_19_cfg_force_cdr_apb2apb_bridge_trgt_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_1_cfg_lane_dig_tx2rx_loopback_en_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_1_CFG_LANE_DIG_TX2RX_LOOPBACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_1_cfg_rx_grey_sym_lut_attr == 8'd228
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_1_cfg_rx_inv_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_1_CFG_RX_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_1_cfg_rx_precode_enable_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_1_CFG_RX_PRECODE_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_1_cfg_rx_probe_bus_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_1_cfg_rx_swizzle_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_1_cfg_rx_unused_sar_inv_data_path_cb_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_1_CFG_RX_UNUSED_SAR_INV_DATA_PATH_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_1_cfg_rx_unused_sar_inv_vga_adapt_cb_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_1_CFG_RX_UNUSED_SAR_INV_VGA_ADAPT_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_1_cfg_use_cdr_data_as_data_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_1_CFG_USE_CDR_DATA_AS_DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_20_cfg_dfe_apb2apb_bridge_timeout_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_20_cfg_force_dfe_apb2apb_bridge_src_state_en_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_20_CFG_FORCE_DFE_APB2APB_BRIDGE_SRC_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_20_cfg_force_dfe_apb2apb_bridge_src_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_20_cfg_force_dfe_apb2apb_bridge_trgt_state_en_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_20_CFG_FORCE_DFE_APB2APB_BRIDGE_TRGT_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_20_cfg_force_dfe_apb2apb_bridge_trgt_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_21_cfg_ffe_apb2apb_bridge_timeout_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_21_cfg_force_ffe_apb2apb_bridge_src_state_en_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_21_CFG_FORCE_FFE_APB2APB_BRIDGE_SRC_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_21_cfg_force_ffe_apb2apb_bridge_src_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_21_cfg_force_ffe_apb2apb_bridge_trgt_state_en_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_21_CFG_FORCE_FFE_APB2APB_BRIDGE_TRGT_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_21_cfg_force_ffe_apb2apb_bridge_trgt_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_22_cfg_adapt_apb2apb_bridge_timeout_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_22_cfg_force_adapt_apb2apb_bridge_src_state_en_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_22_CFG_FORCE_ADAPT_APB2APB_BRIDGE_SRC_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_22_cfg_force_adapt_apb2apb_bridge_src_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_22_cfg_force_adapt_apb2apb_bridge_trgt_state_en_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_22_CFG_FORCE_ADAPT_APB2APB_BRIDGE_TRGT_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_22_cfg_force_adapt_apb2apb_bridge_trgt_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_23_cfg_acc_ctrl_field_mask_write_en_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_23_CFG_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_23_cfg_stbl_time_aftr_strb_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_23_cfg_stbl_time_bfr_strb_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_23_cfg_strb_pulse_width_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_24_adc_nob_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_24_cfg_lane_mode_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_24_fake_training_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_24_FAKE_TRAINING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_24_rx_reconverge_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_24_RX_RECONVERGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_24_tfl_enable_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_24_TFL_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_25_dp_rx_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_25_dp_tx_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_25_rx_adc_active_sar_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_25_rx_pam_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_25_tx_pam_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_26_idig_adc_spare_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_26_idig_clkmux_spare_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_26_idig_lane_spare_attr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_28_lane_ctrl_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_28_lane_ctrl_sec_acc_ctrl_broadcast_mode_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_28_LANE_CTRL_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_28_lane_ctrl_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_28_lane_ctrl_sec_acc_ctrl_field_mask_write_en_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_28_LANE_CTRL_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_28_lane_ctrl_sec_acc_ctrl_load_preset_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_28_LANE_CTRL_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_28_lane_ctrl_sec_acc_ctrl_man_clear_on_read_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_28_LANE_CTRL_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_28_lane_ctrl_sec_acc_ctrl_man_self_clear_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_28_LANE_CTRL_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_28_lane_ctrl_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_28_lane_ctrl_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_28_lane_ctrl_sec_acc_ctrl_soft_reset_n_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_28_LANE_CTRL_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_28_lane_ctrl_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_29_lane_ctrl_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_29_lane_ctrl_reg2probe_en_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_29_LANE_CTRL_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_2_cfg_lane_dig_rx2tx_loopback_en_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_2_CFG_LANE_DIG_RX2TX_LOOPBACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_2_cfg_tx_bus_take_dft_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_2_CFG_TX_BUS_TAKE_DFT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_2_cfg_tx_grey_sym_lut_attr == 8'd228
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_2_cfg_tx_inv_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_2_CFG_TX_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_2_cfg_tx_lane_enable_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_2_CFG_TX_LANE_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_2_cfg_tx_precode_enable_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_2_CFG_TX_PRECODE_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_2_cfg_tx_probe_bus_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_2_cfg_tx_swizzle_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_30_metrics_1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_31_metrics_2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_32_fw_calib_fsm_state_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_32_fw_dsp_fsm_state_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_32_fw_tfl_fsm_state_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_33_fw_fsm_state1_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_33_fw_fsm_state2_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_33_fw_fsm_state3_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_34_lane_cal_error_code_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_34_lane_cal_state_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_3_cfg_tx_err_inj_en_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_3_CFG_TX_ERR_INJ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_3_cfg_tx_err_inj_mask_cfg_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_3_cfg_tx_err_inj_mask_rotate_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_3_CFG_TX_ERR_INJ_MASK_ROTATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_3_cfg_tx_err_inj_rate_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_4_cfg_tx_err_inj_trig_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_4_CFG_TX_ERR_INJ_TRIG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_5_cfg_tx_err_inj_mask_load_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_5_CFG_TX_ERR_INJ_MASK_LOAD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_6_idig_tx_dig_spare_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_6_tx_piso_reset_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_6_TX_PISO_RESET_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_7_idig_lclbias_pd_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_7_IDIG_LCLBIAS_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_7_idig_pll_dfx_bi_en_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_7_IDIG_PLL_DFX_BI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_7_idig_txpath_first_mux_control_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_7_IDIG_TXPATH_FIRST_MUX_CONTROL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_7_idig_txpath_second_mux_control_attr == SERDES_LANE_LANE_CTRL_LANE3_REG_7_IDIG_TXPATH_SECOND_MUX_CONTROL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_lane_lane_ctrl_lane3_reg_7_link_up_cntr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_10_cfg_an_tx_lcw_high_attr == 27'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_11_cfg_an_rx_lcw_re_attr == SERDES_SHIM_AN_LANE0_REG_11_CFG_AN_RX_LCW_RE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_11_cfg_an_tx_lcw_low_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_11_cfg_an_tx_lcw_we_attr == SERDES_SHIM_AN_LANE0_REG_11_CFG_AN_TX_LCW_WE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_18_debug_fw_reg1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_19_debug_fw_reg2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_1_an_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_1_an_reg2probe_en_attr == SERDES_SHIM_AN_LANE0_REG_1_AN_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_20_debug_fw_reg3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_21_debug_fw_reg4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_22_debug_fw_reg5_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_23_debug_fw_reg6_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_24_debug_fw_reg7_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_25_debug_fw_reg8_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_26_debug_fw_reg9_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_27_direct_control_bus_attr == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_27_direct_control_bus_en_attr == SERDES_SHIM_AN_LANE0_REG_27_DIRECT_CONTROL_BUS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_2_an_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_2_an_sec_acc_ctrl_broadcast_mode_attr == SERDES_SHIM_AN_LANE0_REG_2_AN_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_2_an_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_2_an_sec_acc_ctrl_field_mask_write_en_attr == SERDES_SHIM_AN_LANE0_REG_2_AN_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_2_an_sec_acc_ctrl_load_preset_attr == SERDES_SHIM_AN_LANE0_REG_2_AN_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_2_an_sec_acc_ctrl_man_clear_on_read_attr == SERDES_SHIM_AN_LANE0_REG_2_AN_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_2_an_sec_acc_ctrl_man_self_clear_attr == SERDES_SHIM_AN_LANE0_REG_2_AN_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_2_an_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_2_an_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_2_an_sec_acc_ctrl_soft_reset_n_attr == SERDES_SHIM_AN_LANE0_REG_2_AN_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_2_an_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_3_cfg_an_idle_stiky_clear_attr == SERDES_SHIM_AN_LANE0_REG_3_CFG_AN_IDLE_STIKY_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_3_cfg_an_rx_enable_m_attr == SERDES_SHIM_AN_LANE0_REG_3_CFG_AN_RX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_3_cfg_an_tx_enable_m_attr == SERDES_SHIM_AN_LANE0_REG_3_CFG_AN_TX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_3_cfg_dig_cdr_disable_attr == SERDES_SHIM_AN_LANE0_REG_3_CFG_DIG_CDR_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_3_cfg_edge_too_long_disable_attr == SERDES_SHIM_AN_LANE0_REG_3_CFG_EDGE_TOO_LONG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_3_cfg_edge_too_short_disable_attr == SERDES_SHIM_AN_LANE0_REG_3_CFG_EDGE_TOO_SHORT_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_3_cfg_page_max_timer_disable_attr == SERDES_SHIM_AN_LANE0_REG_3_CFG_PAGE_MAX_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_3_cfg_page_min_timer_disable_attr == SERDES_SHIM_AN_LANE0_REG_3_CFG_PAGE_MIN_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_4_pcs_lock_attr == SERDES_SHIM_AN_LANE0_REG_4_PCS_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_5_pcs_rx_bypass_sample_attr == SERDES_SHIM_AN_LANE0_REG_5_PCS_RX_BYPASS_SAMPLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_5_pcs_tx_bypass_sample_attr == SERDES_SHIM_AN_LANE0_REG_5_PCS_TX_BYPASS_SAMPLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_5_rx_pma_en_attr == SERDES_SHIM_AN_LANE0_REG_5_RX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_5_sc_rx_80b_swz_attr == SERDES_SHIM_AN_LANE0_REG_5_SC_RX_80B_SWZ_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_5_sc_tx_80b_swz_attr == SERDES_SHIM_AN_LANE0_REG_5_SC_TX_80B_SWZ_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_5_transmit_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_5_tx_pma_en_attr == SERDES_SHIM_AN_LANE0_REG_5_TX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_6_serdes_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_7_serdes_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_8_serdes_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane0_reg_9_serdes_irq_bus_sel_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_10_cfg_an_tx_lcw_high_attr == 27'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_11_cfg_an_rx_lcw_re_attr == SERDES_SHIM_AN_LANE1_REG_11_CFG_AN_RX_LCW_RE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_11_cfg_an_tx_lcw_low_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_11_cfg_an_tx_lcw_we_attr == SERDES_SHIM_AN_LANE1_REG_11_CFG_AN_TX_LCW_WE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_18_debug_fw_reg1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_19_debug_fw_reg2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_1_an_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_1_an_reg2probe_en_attr == SERDES_SHIM_AN_LANE1_REG_1_AN_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_20_debug_fw_reg3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_21_debug_fw_reg4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_22_debug_fw_reg5_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_23_debug_fw_reg6_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_24_debug_fw_reg7_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_25_debug_fw_reg8_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_26_debug_fw_reg9_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_27_direct_control_bus_attr == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_27_direct_control_bus_en_attr == SERDES_SHIM_AN_LANE1_REG_27_DIRECT_CONTROL_BUS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_2_an_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_2_an_sec_acc_ctrl_broadcast_mode_attr == SERDES_SHIM_AN_LANE1_REG_2_AN_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_2_an_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_2_an_sec_acc_ctrl_field_mask_write_en_attr == SERDES_SHIM_AN_LANE1_REG_2_AN_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_2_an_sec_acc_ctrl_load_preset_attr == SERDES_SHIM_AN_LANE1_REG_2_AN_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_2_an_sec_acc_ctrl_man_clear_on_read_attr == SERDES_SHIM_AN_LANE1_REG_2_AN_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_2_an_sec_acc_ctrl_man_self_clear_attr == SERDES_SHIM_AN_LANE1_REG_2_AN_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_2_an_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_2_an_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_2_an_sec_acc_ctrl_soft_reset_n_attr == SERDES_SHIM_AN_LANE1_REG_2_AN_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_2_an_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_3_cfg_an_idle_stiky_clear_attr == SERDES_SHIM_AN_LANE1_REG_3_CFG_AN_IDLE_STIKY_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_3_cfg_an_rx_enable_m_attr == SERDES_SHIM_AN_LANE1_REG_3_CFG_AN_RX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_3_cfg_an_tx_enable_m_attr == SERDES_SHIM_AN_LANE1_REG_3_CFG_AN_TX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_3_cfg_dig_cdr_disable_attr == SERDES_SHIM_AN_LANE1_REG_3_CFG_DIG_CDR_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_3_cfg_edge_too_long_disable_attr == SERDES_SHIM_AN_LANE1_REG_3_CFG_EDGE_TOO_LONG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_3_cfg_edge_too_short_disable_attr == SERDES_SHIM_AN_LANE1_REG_3_CFG_EDGE_TOO_SHORT_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_3_cfg_page_max_timer_disable_attr == SERDES_SHIM_AN_LANE1_REG_3_CFG_PAGE_MAX_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_3_cfg_page_min_timer_disable_attr == SERDES_SHIM_AN_LANE1_REG_3_CFG_PAGE_MIN_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_4_pcs_lock_attr == SERDES_SHIM_AN_LANE1_REG_4_PCS_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_5_pcs_rx_bypass_sample_attr == SERDES_SHIM_AN_LANE1_REG_5_PCS_RX_BYPASS_SAMPLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_5_pcs_tx_bypass_sample_attr == SERDES_SHIM_AN_LANE1_REG_5_PCS_TX_BYPASS_SAMPLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_5_rx_pma_en_attr == SERDES_SHIM_AN_LANE1_REG_5_RX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_5_sc_rx_80b_swz_attr == SERDES_SHIM_AN_LANE1_REG_5_SC_RX_80B_SWZ_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_5_sc_tx_80b_swz_attr == SERDES_SHIM_AN_LANE1_REG_5_SC_TX_80B_SWZ_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_5_transmit_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_5_tx_pma_en_attr == SERDES_SHIM_AN_LANE1_REG_5_TX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_6_serdes_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_7_serdes_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_8_serdes_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane1_reg_9_serdes_irq_bus_sel_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_10_cfg_an_tx_lcw_high_attr == 27'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_11_cfg_an_rx_lcw_re_attr == SERDES_SHIM_AN_LANE2_REG_11_CFG_AN_RX_LCW_RE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_11_cfg_an_tx_lcw_low_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_11_cfg_an_tx_lcw_we_attr == SERDES_SHIM_AN_LANE2_REG_11_CFG_AN_TX_LCW_WE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_18_debug_fw_reg1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_19_debug_fw_reg2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_1_an_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_1_an_reg2probe_en_attr == SERDES_SHIM_AN_LANE2_REG_1_AN_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_20_debug_fw_reg3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_21_debug_fw_reg4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_22_debug_fw_reg5_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_23_debug_fw_reg6_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_24_debug_fw_reg7_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_25_debug_fw_reg8_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_26_debug_fw_reg9_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_27_direct_control_bus_attr == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_27_direct_control_bus_en_attr == SERDES_SHIM_AN_LANE2_REG_27_DIRECT_CONTROL_BUS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_2_an_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_2_an_sec_acc_ctrl_broadcast_mode_attr == SERDES_SHIM_AN_LANE2_REG_2_AN_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_2_an_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_2_an_sec_acc_ctrl_field_mask_write_en_attr == SERDES_SHIM_AN_LANE2_REG_2_AN_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_2_an_sec_acc_ctrl_load_preset_attr == SERDES_SHIM_AN_LANE2_REG_2_AN_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_2_an_sec_acc_ctrl_man_clear_on_read_attr == SERDES_SHIM_AN_LANE2_REG_2_AN_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_2_an_sec_acc_ctrl_man_self_clear_attr == SERDES_SHIM_AN_LANE2_REG_2_AN_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_2_an_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_2_an_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_2_an_sec_acc_ctrl_soft_reset_n_attr == SERDES_SHIM_AN_LANE2_REG_2_AN_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_2_an_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_3_cfg_an_idle_stiky_clear_attr == SERDES_SHIM_AN_LANE2_REG_3_CFG_AN_IDLE_STIKY_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_3_cfg_an_rx_enable_m_attr == SERDES_SHIM_AN_LANE2_REG_3_CFG_AN_RX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_3_cfg_an_tx_enable_m_attr == SERDES_SHIM_AN_LANE2_REG_3_CFG_AN_TX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_3_cfg_dig_cdr_disable_attr == SERDES_SHIM_AN_LANE2_REG_3_CFG_DIG_CDR_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_3_cfg_edge_too_long_disable_attr == SERDES_SHIM_AN_LANE2_REG_3_CFG_EDGE_TOO_LONG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_3_cfg_edge_too_short_disable_attr == SERDES_SHIM_AN_LANE2_REG_3_CFG_EDGE_TOO_SHORT_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_3_cfg_page_max_timer_disable_attr == SERDES_SHIM_AN_LANE2_REG_3_CFG_PAGE_MAX_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_3_cfg_page_min_timer_disable_attr == SERDES_SHIM_AN_LANE2_REG_3_CFG_PAGE_MIN_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_4_pcs_lock_attr == SERDES_SHIM_AN_LANE2_REG_4_PCS_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_5_pcs_rx_bypass_sample_attr == SERDES_SHIM_AN_LANE2_REG_5_PCS_RX_BYPASS_SAMPLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_5_pcs_tx_bypass_sample_attr == SERDES_SHIM_AN_LANE2_REG_5_PCS_TX_BYPASS_SAMPLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_5_rx_pma_en_attr == SERDES_SHIM_AN_LANE2_REG_5_RX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_5_sc_rx_80b_swz_attr == SERDES_SHIM_AN_LANE2_REG_5_SC_RX_80B_SWZ_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_5_sc_tx_80b_swz_attr == SERDES_SHIM_AN_LANE2_REG_5_SC_TX_80B_SWZ_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_5_transmit_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_5_tx_pma_en_attr == SERDES_SHIM_AN_LANE2_REG_5_TX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_6_serdes_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_7_serdes_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_8_serdes_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane2_reg_9_serdes_irq_bus_sel_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_10_cfg_an_tx_lcw_high_attr == 27'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_11_cfg_an_rx_lcw_re_attr == SERDES_SHIM_AN_LANE3_REG_11_CFG_AN_RX_LCW_RE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_11_cfg_an_tx_lcw_low_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_11_cfg_an_tx_lcw_we_attr == SERDES_SHIM_AN_LANE3_REG_11_CFG_AN_TX_LCW_WE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_18_debug_fw_reg1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_19_debug_fw_reg2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_1_an_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_1_an_reg2probe_en_attr == SERDES_SHIM_AN_LANE3_REG_1_AN_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_20_debug_fw_reg3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_21_debug_fw_reg4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_22_debug_fw_reg5_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_23_debug_fw_reg6_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_24_debug_fw_reg7_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_25_debug_fw_reg8_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_26_debug_fw_reg9_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_27_direct_control_bus_attr == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_27_direct_control_bus_en_attr == SERDES_SHIM_AN_LANE3_REG_27_DIRECT_CONTROL_BUS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_2_an_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_2_an_sec_acc_ctrl_broadcast_mode_attr == SERDES_SHIM_AN_LANE3_REG_2_AN_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_2_an_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_2_an_sec_acc_ctrl_field_mask_write_en_attr == SERDES_SHIM_AN_LANE3_REG_2_AN_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_2_an_sec_acc_ctrl_load_preset_attr == SERDES_SHIM_AN_LANE3_REG_2_AN_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_2_an_sec_acc_ctrl_man_clear_on_read_attr == SERDES_SHIM_AN_LANE3_REG_2_AN_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_2_an_sec_acc_ctrl_man_self_clear_attr == SERDES_SHIM_AN_LANE3_REG_2_AN_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_2_an_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_2_an_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_2_an_sec_acc_ctrl_soft_reset_n_attr == SERDES_SHIM_AN_LANE3_REG_2_AN_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_2_an_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_3_cfg_an_idle_stiky_clear_attr == SERDES_SHIM_AN_LANE3_REG_3_CFG_AN_IDLE_STIKY_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_3_cfg_an_rx_enable_m_attr == SERDES_SHIM_AN_LANE3_REG_3_CFG_AN_RX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_3_cfg_an_tx_enable_m_attr == SERDES_SHIM_AN_LANE3_REG_3_CFG_AN_TX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_3_cfg_dig_cdr_disable_attr == SERDES_SHIM_AN_LANE3_REG_3_CFG_DIG_CDR_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_3_cfg_edge_too_long_disable_attr == SERDES_SHIM_AN_LANE3_REG_3_CFG_EDGE_TOO_LONG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_3_cfg_edge_too_short_disable_attr == SERDES_SHIM_AN_LANE3_REG_3_CFG_EDGE_TOO_SHORT_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_3_cfg_page_max_timer_disable_attr == SERDES_SHIM_AN_LANE3_REG_3_CFG_PAGE_MAX_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_3_cfg_page_min_timer_disable_attr == SERDES_SHIM_AN_LANE3_REG_3_CFG_PAGE_MIN_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_4_pcs_lock_attr == SERDES_SHIM_AN_LANE3_REG_4_PCS_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_5_pcs_rx_bypass_sample_attr == SERDES_SHIM_AN_LANE3_REG_5_PCS_RX_BYPASS_SAMPLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_5_pcs_tx_bypass_sample_attr == SERDES_SHIM_AN_LANE3_REG_5_PCS_TX_BYPASS_SAMPLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_5_rx_pma_en_attr == SERDES_SHIM_AN_LANE3_REG_5_RX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_5_sc_rx_80b_swz_attr == SERDES_SHIM_AN_LANE3_REG_5_SC_RX_80B_SWZ_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_5_sc_tx_80b_swz_attr == SERDES_SHIM_AN_LANE3_REG_5_SC_TX_80B_SWZ_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_5_transmit_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_5_tx_pma_en_attr == SERDES_SHIM_AN_LANE3_REG_5_TX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_6_serdes_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_7_serdes_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_8_serdes_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_an_lane3_reg_9_serdes_irq_bus_sel_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_10_mb_lcb_enb_attr == SERDES_SHIM_ANA_COMMON_REG_10_MB_LCB_ENB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_10_mb_lcbamp_enb_attr == SERDES_SHIM_ANA_COMMON_REG_10_MB_LCBAMP_ENB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_10_mb_reg7_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_10_mb_rs_trim_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_10_mb_vacu600_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_10_mb_vreflocal_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_11_mb_compsel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_11_mb_reg8_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_11_mb_vref_dco_clb_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_11_mb_vref_rx_clb_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_11_mb_vref_tx_clb_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_11_mb_vrefen_attr == SERDES_SHIM_ANA_COMMON_REG_11_MB_VREFEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_12_mb_dcmonctr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_12_mb_reg9_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_12_mb_spare_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_13_cmn_dcmon_adcafe_l_en_attr == SERDES_SHIM_ANA_COMMON_REG_13_CMN_DCMON_ADCAFE_L_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_13_cmn_dcmon_adcafe_r_en_attr == SERDES_SHIM_ANA_COMMON_REG_13_CMN_DCMON_ADCAFE_R_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_13_cmn_dcmon_afe_l_en_attr == SERDES_SHIM_ANA_COMMON_REG_13_CMN_DCMON_AFE_L_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_13_cmn_dcmon_afe_r_en_attr == SERDES_SHIM_ANA_COMMON_REG_13_CMN_DCMON_AFE_R_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_13_cmn_ref_clks_sp_attr == 15'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_13_family_clk_tie_low_en_attr == SERDES_SHIM_ANA_COMMON_REG_13_FAMILY_CLK_TIE_LOW_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_13_refclk1_term_cm_en_attr == SERDES_SHIM_ANA_COMMON_REG_13_REFCLK1_TERM_CM_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_13_refclk1_term_en_attr == SERDES_SHIM_ANA_COMMON_REG_13_REFCLK1_TERM_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_13_refclk2_term_cm_en_attr == SERDES_SHIM_ANA_COMMON_REG_13_REFCLK2_TERM_CM_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_13_refclk2_term_en_attr == SERDES_SHIM_ANA_COMMON_REG_13_REFCLK2_TERM_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_1_cmn_dcmon_obs_sp_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_1_dcmon_adc_l_en_attr == SERDES_SHIM_ANA_COMMON_REG_1_DCMON_ADC_L_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_1_dcmon_adc_r_en_attr == SERDES_SHIM_ANA_COMMON_REG_1_DCMON_ADC_R_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_1_dcmon_en_attr == SERDES_SHIM_ANA_COMMON_REG_1_DCMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_1_dcmon_sel_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_1_delta_sigma_bgtrim_mode_attr == SERDES_SHIM_ANA_COMMON_REG_1_DELTA_SIGMA_BGTRIM_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_1_delta_sigma_chop_en_attr == SERDES_SHIM_ANA_COMMON_REG_1_DELTA_SIGMA_CHOP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_1_delta_sigma_clkdiv_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_1_delta_sigma_cont_mode_attr == SERDES_SHIM_ANA_COMMON_REG_1_DELTA_SIGMA_CONT_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_1_delta_sigma_en_attr == SERDES_SHIM_ANA_COMMON_REG_1_DELTA_SIGMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_1_delta_sigma_freeze_attr == SERDES_SHIM_ANA_COMMON_REG_1_DELTA_SIGMA_FREEZE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_1_delta_sigma_mux_en_attr == SERDES_SHIM_ANA_COMMON_REG_1_DELTA_SIGMA_MUX_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_1_delta_sigma_rst_b_attr == SERDES_SHIM_ANA_COMMON_REG_1_DELTA_SIGMA_RST_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_1_delta_sigma_sel_p_attr == SERDES_SHIM_ANA_COMMON_REG_1_DELTA_SIGMA_SEL_P_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_3_mb_cmp_en_attr == SERDES_SHIM_ANA_COMMON_REG_3_MB_CMP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_3_mb_cmp_ofc_n_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_3_mb_cmp_ofc_n_sign_attr == SERDES_SHIM_ANA_COMMON_REG_3_MB_CMP_OFC_N_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_3_mb_cmp_ofc_p_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_3_mb_cmp_ofc_p_sign_attr == SERDES_SHIM_ANA_COMMON_REG_3_MB_CMP_OFC_P_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_3_mb_reg0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_4_mb_dco_clbswen_attr == SERDES_SHIM_ANA_COMMON_REG_4_MB_DCO_CLBSWEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_4_mb_pre_cmp_n_sel_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_4_mb_pre_cmp_p_sel_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_4_mb_reg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_4_mb_rx_st3_clbswen_attr == SERDES_SHIM_ANA_COMMON_REG_4_MB_RX_ST3_CLBSWEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_4_mb_rx_term_clbswen_attr == SERDES_SHIM_ANA_COMMON_REG_4_MB_RX_TERM_CLBSWEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_4_mb_tx_term_clbswen_attr == SERDES_SHIM_ANA_COMMON_REG_4_MB_TX_TERM_CLBSWEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_5_mb_dco_bintrim_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_5_mb_reg2_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_5_txterm_trim_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_6_mb_reg3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_6_mb_rx_rterm_btrim_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_6_mb_rx_st3_trim_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_6_mb_vg750sel_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_7_mb_lcb_trim_plla_100u_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_7_mb_lcb_trim_pllb_100u_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_7_mb_lcb_trim_rclk1_100u_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_7_mb_lcb_trim_rclk2_100u_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_7_mb_lcb_trim_spare1_100u_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_7_mb_lcb_trim_spare2_100u_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_8_mb_lcb_trim_comp_50u_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_8_mb_lcb_trim_dcmon_50u_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_8_mb_lcb_trim_master_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_8_mb_lcb_trim_spare1_50u_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_8_mb_lcb_trim_spare2_50u_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_8_mb_reg5_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_9_mb_lcb_trim_spare3_100u_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_9_mb_lcb_trim_spare3_50u_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_9_mb_lcb_trim_spare4_100u_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_9_mb_lcb_trim_spare4_50u_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_common_reg_9_mb_reg6_attr == 8'd136
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_10_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_11_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_12_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_13_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_13_cfg_plllock_state_sel_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_13_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_13_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_18_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_18_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_18_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_18_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_18_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_18_cfg_dcocoarse_ovrden_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_18_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_18_cfg_full_range_afc_sel_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_18_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_19_cfg_boost_dtr_const_zeta_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_19_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_19_cfg_boost_fine_const_zeta_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_19_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_19_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_19_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_19_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_19_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_19_cfg_filter_boostfade_dtr_en_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_19_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_19_cfg_filter_boostfade_fine_en_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_19_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_19_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_19_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_1_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_1_o_fbdiv_intgr_attr == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_1_o_fracnen_h_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_1_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_20_cfg_dtr_earlylock_sel_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_20_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_20_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_20_cfg_dtr_final_code_sel_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_20_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_20_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_20_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_20_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_20_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_20_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_20_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_21_cfg_dcosettle_mode_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_21_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_21_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_21_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_21_cfg_dtr_ovrden_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_21_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_21_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_21_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_21_cfg_skip_second_afc_calib_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_21_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_21_cfg_stay_fll_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_21_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_21_cfg_stay_pll_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_21_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_21_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_21_cfg_tdcbbpd_en_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_21_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_22_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_22_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_22_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_22_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_22_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_22_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_22_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_22_cfg_ssc_track_en_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_22_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_22_cfg_temp_track_en_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_22_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_23_cfg_cb56_lane32div_en_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_23_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_23_cfg_clkouten_cb_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_23_CFG_CLKOUTEN_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_23_cfg_clkouten_lane_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_23_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_23_cfg_fbdiv_rat0p5_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_23_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_23_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_23_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_23_cfg_pcs3334_divsel_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_23_cfg_pcs3334div_en_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_23_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_23_cfg_pcs40div_en_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_23_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_23_cfg_pll_bypass_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_23_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_23_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_23_cfg_refclk100div_en_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_23_CFG_REFCLK100DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_23_cfg_refclk156div_en_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_23_CFG_REFCLK156DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_23_cfg_sddiv_en_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_23_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_23_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_23_cfg_sddtr_clk_sel_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_23_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_24_cfg_a2f_en_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_24_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_24_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_24_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_24_cfg_en_peak_sense_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_24_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_24_cfg_force_vreglpfbyp_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_24_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_24_cfg_obsmux0_del_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_24_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_24_cfg_obsmux1_del_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_24_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_24_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_24_cfg_ref156div_rat0p5_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_24_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_24_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_24_cfg_ss_comp_out_sel_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_24_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_24_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_25_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_25_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_25_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_25_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_25_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_25_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_25_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_25_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_25_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_25_cfg_dfx_ramp_dir_ovr_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_25_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_25_cfg_dfx_ramp_enable_ovr_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_25_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_25_cfg_dfx_ramp_toggle_en_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_25_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_25_cfg_dpso_bypass_mode_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_25_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_25_cfg_dtr_modulation_en_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_25_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_25_cfg_fine_modulation_en_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_25_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_25_cfg_fine_modulation_sel_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_25_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_25_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_25_cfg_tdcpe_modulation_en_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_25_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_25_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_25_cfg_vreg_dac_modulation_en_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_25_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_26_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_26_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_26_cfg_fbdiv_clkgate_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_26_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_26_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_27_cfg_calib_comp_out_sel_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_27_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_27_cfg_fw_force_vreg_cal_done_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_27_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_27_cfg_fw_vreg_accum_ovrd_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_27_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_27_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_27_cfg_inv_vpeak_comb_fb_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_27_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_27_cfg_inv_vreg_comb_fb_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_27_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_27_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_27_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_27_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_27_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_28_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_28_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_29_cfg_dft_freq_meas_enable_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_29_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_29_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_29_cfg_kvcc_inv_polarity_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_29_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_29_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_29_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_29_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_29_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_29_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_2_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_2_cfg_fracn_sd_step_en_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_2_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_2_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_30_cfg_force_kvcc_done_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_30_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_30_cfg_kvcc_calib_by_fw_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_30_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_30_cfg_kvcc_code_ovrd_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_30_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_30_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_30_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_30_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_30_cfg_kvcc_vreg_offset_en_val_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_30_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_31_cfg_spare_dig2ana_attr == 18'd10240
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_3_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_3_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_3_o_tdc_fine_res_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_3_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_3_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_4_cfg_sigma_delta2_sel_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_4_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_4_o_dcoditheren_h_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_4_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_4_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_4_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_4_o_fbdiv_strobe_h_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_4_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_4_o_feedfwrdcal_en_h_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_4_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_4_o_feedfwrdcal_pause_h_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_4_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_4_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_4_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_5_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_5_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_6_cfg_tdc_bb_input_sel_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_6_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_6_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_6_o_bbinlock_h_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_6_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_6_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_6_o_tdcdc_en_h_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_6_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_6_o_tdcovccorr_en_h_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_6_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_6_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_7_o_dfx_tdc_disable_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_7_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_7_o_pll_reg_resetb_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_7_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_7_o_pll_reg_resetb_mode_ctrl_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_7_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_7_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_7_o_plllc_regen_h_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_7_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_8_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_8_o_dcocoarse_ovrd_h_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_8_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_8_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_8_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_9_cfg_dft_cnt_restart_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_9_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_9_cfg_force_tdcdone_at_afcdone_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_9_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_9_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_9_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_9_o_tdccalexten_h_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_9_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_9_o_tdcroen_h_attr == SERDES_SHIM_ANA_PLL_PLL_A_REG_9_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_a_reg_9_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_10_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_11_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_12_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_13_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_13_cfg_plllock_state_sel_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_13_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_13_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_18_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_18_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_18_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_18_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_18_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_18_cfg_dcocoarse_ovrden_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_18_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_18_cfg_full_range_afc_sel_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_18_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_19_cfg_boost_dtr_const_zeta_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_19_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_19_cfg_boost_fine_const_zeta_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_19_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_19_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_19_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_19_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_19_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_19_cfg_filter_boostfade_dtr_en_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_19_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_19_cfg_filter_boostfade_fine_en_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_19_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_19_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_19_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_1_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_1_o_fbdiv_intgr_attr == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_1_o_fracnen_h_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_1_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_20_cfg_dtr_earlylock_sel_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_20_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_20_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_20_cfg_dtr_final_code_sel_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_20_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_20_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_20_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_20_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_20_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_20_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_20_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_21_cfg_dcosettle_mode_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_21_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_21_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_21_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_21_cfg_dtr_ovrden_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_21_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_21_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_21_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_21_cfg_skip_second_afc_calib_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_21_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_21_cfg_stay_fll_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_21_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_21_cfg_stay_pll_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_21_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_21_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_21_cfg_tdcbbpd_en_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_21_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_22_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_22_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_22_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_22_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_22_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_22_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_22_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_22_cfg_ssc_track_en_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_22_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_22_cfg_temp_track_en_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_22_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_23_cfg_cb56_lane32div_en_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_23_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_23_cfg_clkouten_cb_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_23_CFG_CLKOUTEN_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_23_cfg_clkouten_lane_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_23_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_23_cfg_fbdiv_rat0p5_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_23_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_23_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_23_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_23_cfg_pcs3334_divsel_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_23_cfg_pcs3334div_en_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_23_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_23_cfg_pcs40div_en_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_23_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_23_cfg_pll_bypass_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_23_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_23_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_23_cfg_refclk100div_en_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_23_CFG_REFCLK100DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_23_cfg_refclk156div_en_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_23_CFG_REFCLK156DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_23_cfg_sddiv_en_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_23_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_23_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_23_cfg_sddtr_clk_sel_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_23_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_24_cfg_a2f_en_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_24_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_24_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_24_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_24_cfg_en_peak_sense_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_24_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_24_cfg_force_vreglpfbyp_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_24_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_24_cfg_obsmux0_del_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_24_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_24_cfg_obsmux1_del_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_24_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_24_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_24_cfg_ref156div_rat0p5_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_24_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_24_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_24_cfg_ss_comp_out_sel_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_24_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_24_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_25_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_25_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_25_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_25_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_25_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_25_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_25_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_25_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_25_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_25_cfg_dfx_ramp_dir_ovr_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_25_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_25_cfg_dfx_ramp_enable_ovr_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_25_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_25_cfg_dfx_ramp_toggle_en_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_25_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_25_cfg_dpso_bypass_mode_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_25_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_25_cfg_dtr_modulation_en_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_25_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_25_cfg_fine_modulation_en_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_25_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_25_cfg_fine_modulation_sel_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_25_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_25_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_25_cfg_tdcpe_modulation_en_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_25_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_25_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_25_cfg_vreg_dac_modulation_en_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_25_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_26_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_26_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_26_cfg_fbdiv_clkgate_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_26_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_26_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_27_cfg_calib_comp_out_sel_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_27_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_27_cfg_fw_force_vreg_cal_done_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_27_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_27_cfg_fw_vreg_accum_ovrd_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_27_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_27_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_27_cfg_inv_vpeak_comb_fb_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_27_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_27_cfg_inv_vreg_comb_fb_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_27_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_27_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_27_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_27_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_27_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_28_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_28_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_29_cfg_dft_freq_meas_enable_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_29_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_29_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_29_cfg_kvcc_inv_polarity_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_29_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_29_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_29_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_29_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_29_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_29_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_2_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_2_cfg_fracn_sd_step_en_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_2_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_2_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_30_cfg_force_kvcc_done_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_30_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_30_cfg_kvcc_calib_by_fw_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_30_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_30_cfg_kvcc_code_ovrd_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_30_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_30_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_30_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_30_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_30_cfg_kvcc_vreg_offset_en_val_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_30_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_31_cfg_spare_dig2ana_attr == 18'd10240
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_3_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_3_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_3_o_tdc_fine_res_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_3_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_3_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_4_cfg_sigma_delta2_sel_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_4_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_4_o_dcoditheren_h_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_4_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_4_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_4_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_4_o_fbdiv_strobe_h_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_4_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_4_o_feedfwrdcal_en_h_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_4_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_4_o_feedfwrdcal_pause_h_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_4_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_4_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_4_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_5_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_5_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_6_cfg_tdc_bb_input_sel_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_6_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_6_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_6_o_bbinlock_h_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_6_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_6_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_6_o_tdcdc_en_h_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_6_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_6_o_tdcovccorr_en_h_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_6_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_6_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_7_o_dfx_tdc_disable_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_7_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_7_o_pll_reg_resetb_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_7_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_7_o_pll_reg_resetb_mode_ctrl_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_7_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_7_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_7_o_plllc_regen_h_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_7_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_8_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_8_o_dcocoarse_ovrd_h_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_8_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_8_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_8_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_9_cfg_dft_cnt_restart_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_9_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_9_cfg_force_tdcdone_at_afcdone_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_9_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_9_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_9_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_9_o_tdccalexten_h_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_9_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_9_o_tdcroen_h_attr == SERDES_SHIM_ANA_PLL_PLL_B_REG_9_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_ana_pll_pll_b_reg_9_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_10_common_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_10_common_reg2probe_en_attr == SERDES_SHIM_COMMON_REG_10_COMMON_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_11_cfg_cmn_plla_ref_clk_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_11_cfg_cmn_plla_ref_clk_sel_ovrd_attr == SERDES_SHIM_COMMON_REG_11_CFG_CMN_PLLA_REF_CLK_SEL_OVRD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_11_cfg_cmn_pllb_ref_clk_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_11_cfg_cmn_pllb_ref_clk_sel_ovrd_attr == SERDES_SHIM_COMMON_REG_11_CFG_CMN_PLLB_REF_CLK_SEL_OVRD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_13_icom_plla_dfx_bi_en_attr == SERDES_SHIM_COMMON_REG_13_ICOM_PLLA_DFX_BI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_13_icom_plla_en_attr == SERDES_SHIM_COMMON_REG_13_ICOM_PLLA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_13_icom_plla_resetb_attr == SERDES_SHIM_COMMON_REG_13_ICOM_PLLA_RESETB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_14_icom_pllb_dfx_bi_en_attr == SERDES_SHIM_COMMON_REG_14_ICOM_PLLB_DFX_BI_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_14_icom_pllb_en_attr == SERDES_SHIM_COMMON_REG_14_ICOM_PLLB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_14_icom_pllb_resetb_attr == SERDES_SHIM_COMMON_REG_14_ICOM_PLLB_RESETB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_15_cfg_acc_ctrl_field_mask_write_en_attr == SERDES_SHIM_COMMON_REG_15_CFG_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_15_cfg_force_apb2strb_bridge_state_en_attr == SERDES_SHIM_COMMON_REG_15_CFG_FORCE_APB2STRB_BRIDGE_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_15_cfg_force_apb2strb_bridge_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_15_cfg_stbl_time_aftr_strb_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_15_cfg_stbl_time_bfr_strb_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_15_cfg_strb_pulse_width_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_17_apb_bridge_wd_limit_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_17_fabric_wd_counter_max_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_1_icom_refclk1_en_attr == SERDES_SHIM_COMMON_REG_1_ICOM_REFCLK1_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_1_icom_refclk2_en_attr == SERDES_SHIM_COMMON_REG_1_ICOM_REFCLK2_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_2_common_avg_eng_bit_in_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_2_common_avg_eng_count_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_2_common_avg_eng_probe_bit_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_2_common_avg_eng_start_attr == SERDES_SHIM_COMMON_REG_2_COMMON_AVG_ENG_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_3_eth_probe_out_int_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_4_common_avg_eng_limit_attr == 32'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_7_icom_spare_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_9_common_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_9_common_sec_acc_ctrl_broadcast_mode_attr == SERDES_SHIM_COMMON_REG_9_COMMON_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_9_common_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_9_common_sec_acc_ctrl_field_mask_write_en_attr == SERDES_SHIM_COMMON_REG_9_COMMON_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_9_common_sec_acc_ctrl_load_preset_attr == SERDES_SHIM_COMMON_REG_9_COMMON_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_9_common_sec_acc_ctrl_man_clear_on_read_attr == SERDES_SHIM_COMMON_REG_9_COMMON_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_9_common_sec_acc_ctrl_man_self_clear_attr == SERDES_SHIM_COMMON_REG_9_COMMON_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_9_common_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_9_common_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_9_common_sec_acc_ctrl_soft_reset_n_attr == SERDES_SHIM_COMMON_REG_9_COMMON_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_common_reg_9_common_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_100_fuse_clkbyp_iram8_attr == SERDES_SHIM_CPU_PM_REG_100_FUSE_CLKBYP_IRAM8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_100_fuse_mce_iram8_attr == SERDES_SHIM_CPU_PM_REG_100_FUSE_MCE_IRAM8_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_100_fuse_ra_iram8_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_100_fuse_rmce_iram8_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_100_fuse_wa_iram8_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_100_fuse_wmce_iram8_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_100_fuse_wpulse_iram8_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_101_fuse_clkbyp_dram0_attr == SERDES_SHIM_CPU_PM_REG_101_FUSE_CLKBYP_DRAM0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_101_fuse_mce_dram0_attr == SERDES_SHIM_CPU_PM_REG_101_FUSE_MCE_DRAM0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_101_fuse_ra_dram0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_101_fuse_rmce_dram0_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_101_fuse_wa_dram0_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_101_fuse_wmce_dram0_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_101_fuse_wpulse_dram0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_102_fuse_clkbyp_dram1_attr == SERDES_SHIM_CPU_PM_REG_102_FUSE_CLKBYP_DRAM1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_102_fuse_mce_dram1_attr == SERDES_SHIM_CPU_PM_REG_102_FUSE_MCE_DRAM1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_102_fuse_ra_dram1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_102_fuse_rmce_dram1_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_102_fuse_wa_dram1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_102_fuse_wmce_dram1_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_102_fuse_wpulse_dram1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_103_fuse_clkbyp_dram2_attr == SERDES_SHIM_CPU_PM_REG_103_FUSE_CLKBYP_DRAM2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_103_fuse_mce_dram2_attr == SERDES_SHIM_CPU_PM_REG_103_FUSE_MCE_DRAM2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_103_fuse_ra_dram2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_103_fuse_rmce_dram2_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_103_fuse_wa_dram2_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_103_fuse_wmce_dram2_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_103_fuse_wpulse_dram2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_104_fuse_clkbyp_dram3_attr == SERDES_SHIM_CPU_PM_REG_104_FUSE_CLKBYP_DRAM3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_104_fuse_mce_dram3_attr == SERDES_SHIM_CPU_PM_REG_104_FUSE_MCE_DRAM3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_104_fuse_ra_dram3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_104_fuse_rmce_dram3_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_104_fuse_wa_dram3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_104_fuse_wmce_dram3_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_104_fuse_wpulse_dram3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_105_fuse_clkbyp_dram4_attr == SERDES_SHIM_CPU_PM_REG_105_FUSE_CLKBYP_DRAM4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_105_fuse_mce_dram4_attr == SERDES_SHIM_CPU_PM_REG_105_FUSE_MCE_DRAM4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_105_fuse_ra_dram4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_105_fuse_rmce_dram4_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_105_fuse_wa_dram4_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_105_fuse_wmce_dram4_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_105_fuse_wpulse_dram4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_106_fuse_clkbyp_trace_attr == SERDES_SHIM_CPU_PM_REG_106_FUSE_CLKBYP_TRACE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_106_fuse_mce_trace_attr == SERDES_SHIM_CPU_PM_REG_106_FUSE_MCE_TRACE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_106_fuse_ra_trace_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_106_fuse_rmce_trace_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_106_fuse_wa_trace_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_106_fuse_wmce_trace_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_106_fuse_wpulse_trace_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_107_fuse_clkbyp_fifo_attr == SERDES_SHIM_CPU_PM_REG_107_FUSE_CLKBYP_FIFO_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_107_fuse_mce_fifo_attr == SERDES_SHIM_CPU_PM_REG_107_FUSE_MCE_FIFO_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_107_fuse_rmce_fifo_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_107_fuse_wa_fifo_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_107_fuse_wmce_fifo_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_107_fuse_wpulse_fifo_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_109_sil_step_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_10_lane3_auto_halt_release_attr == SERDES_SHIM_CPU_PM_REG_10_LANE3_AUTO_HALT_RELEASE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_10_lane3_fsm_reset_attr == SERDES_SHIM_CPU_PM_REG_10_LANE3_FSM_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_10_lane3_halt_on_state_attr == 10'd1023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_10_lane3_jump_attr == SERDES_SHIM_CPU_PM_REG_10_LANE3_JUMP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_10_lane3_jump_from_halt_to_state_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_10_lane3_release_halt_attr == SERDES_SHIM_CPU_PM_REG_10_LANE3_RELEASE_HALT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_110_comm_cal_error_code_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_110_comm_cal_state_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_111_bitprog_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_112_bitprog_res_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_113_bitprog_status_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_114_bitlog_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_115_bitlog_res_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_116_fw_common_calib_fsm_state_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_116_fw_common_fsm_state1_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_116_fw_common_fsm_state2_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_11_extracted_model_attr == SERDES_SHIM_CPU_PM_REG_11_EXTRACTED_MODEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_11_rxtop_en_lane0_attr == SERDES_SHIM_CPU_PM_REG_11_RXTOP_EN_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_11_rxtop_en_lane1_attr == SERDES_SHIM_CPU_PM_REG_11_RXTOP_EN_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_11_rxtop_en_lane2_attr == SERDES_SHIM_CPU_PM_REG_11_RXTOP_EN_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_11_rxtop_en_lane3_attr == SERDES_SHIM_CPU_PM_REG_11_RXTOP_EN_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_11_speed_up_lane0_attr == SERDES_SHIM_CPU_PM_REG_11_SPEED_UP_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_11_speed_up_lane1_attr == SERDES_SHIM_CPU_PM_REG_11_SPEED_UP_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_11_speed_up_lane2_attr == SERDES_SHIM_CPU_PM_REG_11_SPEED_UP_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_11_speed_up_lane3_attr == SERDES_SHIM_CPU_PM_REG_11_SPEED_UP_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_11_txtop_en_lane0_attr == SERDES_SHIM_CPU_PM_REG_11_TXTOP_EN_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_11_txtop_en_lane1_attr == SERDES_SHIM_CPU_PM_REG_11_TXTOP_EN_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_11_txtop_en_lane2_attr == SERDES_SHIM_CPU_PM_REG_11_TXTOP_EN_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_11_txtop_en_lane3_attr == SERDES_SHIM_CPU_PM_REG_11_TXTOP_EN_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_16_fw_control_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_17_cpu_gen_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_18_cfg_xram_is_dram_attr == SERDES_SHIM_CPU_PM_REG_18_CFG_XRAM_IS_DRAM_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_18_cpu_ocdhaltonreset_attr == SERDES_SHIM_CPU_PM_REG_18_CPU_OCDHALTONRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_18_cpu_prid_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_18_cpu_ra_addr_by_fw_lane_cntxt_en_attr == SERDES_SHIM_CPU_PM_REG_18_CPU_RA_ADDR_BY_FW_LANE_CNTXT_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_18_cpu_statvectorsel_attr == SERDES_SHIM_CPU_PM_REG_18_CPU_STATVECTORSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_19_cpu_atresetn_attr == SERDES_SHIM_CPU_PM_REG_19_CPU_ATRESETN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_19_cpu_breakin_attr == SERDES_SHIM_CPU_PM_REG_19_CPU_BREAKIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_19_cpu_breakoutack_attr == SERDES_SHIM_CPU_PM_REG_19_CPU_BREAKOUTACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_19_cpu_crosstriggerin_attr == SERDES_SHIM_CPU_PM_REG_19_CPU_CROSSTRIGGERIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_19_cpu_crosstriggeroutack_attr == SERDES_SHIM_CPU_PM_REG_19_CPU_CROSSTRIGGEROUTACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_19_cpu_pdebugenable_attr == SERDES_SHIM_CPU_PM_REG_19_CPU_PDEBUGENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_19_cpu_tmodeclkgateoverride_reserved_attr == SERDES_SHIM_CPU_PM_REG_19_CPU_TMODECLKGATEOVERRIDE_RESERVED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_1_comm_dco_calib_en_attr == SERDES_SHIM_CPU_PM_REG_1_COMM_DCO_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_1_comm_rcomp_calib_en_attr == SERDES_SHIM_CPU_PM_REG_1_COMM_RCOMP_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_1_comm_stg3_calib_en_attr == SERDES_SHIM_CPU_PM_REG_1_COMM_STG3_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_1_comm_tcomp_calib_en_attr == SERDES_SHIM_CPU_PM_REG_1_COMM_TCOMP_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_1_lane0_en_attr == SERDES_SHIM_CPU_PM_REG_1_LANE0_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_1_lane1_en_attr == SERDES_SHIM_CPU_PM_REG_1_LANE1_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_1_lane2_en_attr == SERDES_SHIM_CPU_PM_REG_1_LANE2_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_1_lane3_en_attr == SERDES_SHIM_CPU_PM_REG_1_LANE3_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_1_main_manual_mode_en_attr == SERDES_SHIM_CPU_PM_REG_1_MAIN_MANUAL_MODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_1_main_periodic_state_en_attr == SERDES_SHIM_CPU_PM_REG_1_MAIN_PERIODIC_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_20_cpu_fifo_pattern_mask_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_20_cpu_fifo_pattern_match_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_21_lane_select_128ui_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_21_samples_to_read_128ui_attr == 8'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_21_write_enable_128ui_attr == SERDES_SHIM_CPU_PM_REG_21_WRITE_ENABLE_128UI_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_22_tb_reg0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_23_tb_reg1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_24_tb_reg2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_25_tb_reg3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_26_tb_reg4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_27_tb_reg5_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_28_tb_reg6_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_29_tb_reg7_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_2_lane0_adc_slc_ofc_calib_en_attr == SERDES_SHIM_CPU_PM_REG_2_LANE0_ADC_SLC_OFC_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_2_lane0_clkgen_duty_cycle_calib_en_attr == SERDES_SHIM_CPU_PM_REG_2_LANE0_CLKGEN_DUTY_CYCLE_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_2_lane0_clkgen_phase_coarse_calib_en_attr == SERDES_SHIM_CPU_PM_REG_2_LANE0_CLKGEN_PHASE_COARSE_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_2_lane0_clkgen_phase_fine_calib_en_attr == SERDES_SHIM_CPU_PM_REG_2_LANE0_CLKGEN_PHASE_FINE_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_2_lane0_clkmux_phase_calib_en_attr == SERDES_SHIM_CPU_PM_REG_2_LANE0_CLKMUX_PHASE_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_2_lane0_concon_adapt_dis_attr == SERDES_SHIM_CPU_PM_REG_2_LANE0_CONCON_ADAPT_DIS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_2_lane0_dco_pi_step_calib_en_attr == SERDES_SHIM_CPU_PM_REG_2_LANE0_DCO_PI_STEP_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_2_lane0_dco_vbuff_calib_en_attr == SERDES_SHIM_CPU_PM_REG_2_LANE0_DCO_VBUFF_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_2_lane0_dco_vgate_calib_en_attr == SERDES_SHIM_CPU_PM_REG_2_LANE0_DCO_VGATE_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_2_lane0_dsp_comm_dfe_n_ffe_en_attr == SERDES_SHIM_CPU_PM_REG_2_LANE0_DSP_COMM_DFE_N_FFE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_2_lane0_dsp_ehm_en_attr == SERDES_SHIM_CPU_PM_REG_2_LANE0_DSP_EHM_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_2_lane0_dsp_en_attr == SERDES_SHIM_CPU_PM_REG_2_LANE0_DSP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_2_lane0_dsp_g_per_sar_en_attr == SERDES_SHIM_CPU_PM_REG_2_LANE0_DSP_G_PER_SAR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_2_lane0_dsp_tap64_en_attr == SERDES_SHIM_CPU_PM_REG_2_LANE0_DSP_TAP64_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_2_lane0_dsp_vref_per_oct_en_attr == SERDES_SHIM_CPU_PM_REG_2_LANE0_DSP_VREF_PER_OCT_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_2_lane0_manual_mode_en_attr == SERDES_SHIM_CPU_PM_REG_2_LANE0_MANUAL_MODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_2_lane0_reduced_th_attr == SERDES_SHIM_CPU_PM_REG_2_LANE0_REDUCED_TH_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_2_lane0_rsrv_1_attr == SERDES_SHIM_CPU_PM_REG_2_LANE0_RSRV_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_2_lane0_rsrv_2_attr == SERDES_SHIM_CPU_PM_REG_2_LANE0_RSRV_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_2_lane0_st1_common_calib_en_attr == SERDES_SHIM_CPU_PM_REG_2_LANE0_ST1_COMMON_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_2_lane0_st1_ofc_calib_en_attr == SERDES_SHIM_CPU_PM_REG_2_LANE0_ST1_OFC_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_2_lane0_st2_common_calib_en_attr == SERDES_SHIM_CPU_PM_REG_2_LANE0_ST2_COMMON_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_2_lane0_st2_ofc_calib_en_attr == SERDES_SHIM_CPU_PM_REG_2_LANE0_ST2_OFC_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_2_lane0_st3_common_calib_en_attr == SERDES_SHIM_CPU_PM_REG_2_LANE0_ST3_COMMON_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_2_lane0_st3_ofc_calib_en_attr == SERDES_SHIM_CPU_PM_REG_2_LANE0_ST3_OFC_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_2_lane0_stand_alone_en_attr == SERDES_SHIM_CPU_PM_REG_2_LANE0_STAND_ALONE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_2_lane0_tx_dcc_calib_en_attr == SERDES_SHIM_CPU_PM_REG_2_LANE0_TX_DCC_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_2_lane0_tx_ldo_calib_en_attr == SERDES_SHIM_CPU_PM_REG_2_LANE0_TX_LDO_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_2_lane0_tx_qec_coarse_calib_en_attr == SERDES_SHIM_CPU_PM_REG_2_LANE0_TX_QEC_COARSE_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_2_lane0_tx_qec_fine_calib_en_attr == SERDES_SHIM_CPU_PM_REG_2_LANE0_TX_QEC_FINE_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_2_lane0_vga_adapt_dis_attr == SERDES_SHIM_CPU_PM_REG_2_LANE0_VGA_ADAPT_DIS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_2_lane0_vga_ofc_calib_en_attr == SERDES_SHIM_CPU_PM_REG_2_LANE0_VGA_OFC_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_30_tb_reg8_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_31_tb_reg9_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_32_fw_version_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_33_link_mng_cpi_cmd_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_33_link_mng_cpi_data_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_34_phy_cpi_cmd_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_34_phy_cpi_data_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_35_phy_owner_cpi_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_36_cpu_fifo_push_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_37_serdes_wrap_visactrl0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_38_serdes_wrap_visactrl1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_39_serdes_wrap_visactrl2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_3_lane1_adc_slc_ofc_calib_en_attr == SERDES_SHIM_CPU_PM_REG_3_LANE1_ADC_SLC_OFC_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_3_lane1_clkgen_duty_cycle_calib_en_attr == SERDES_SHIM_CPU_PM_REG_3_LANE1_CLKGEN_DUTY_CYCLE_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_3_lane1_clkgen_phase_coarse_calib_en_attr == SERDES_SHIM_CPU_PM_REG_3_LANE1_CLKGEN_PHASE_COARSE_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_3_lane1_clkgen_phase_fine_calib_en_attr == SERDES_SHIM_CPU_PM_REG_3_LANE1_CLKGEN_PHASE_FINE_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_3_lane1_clkmux_phase_calib_en_attr == SERDES_SHIM_CPU_PM_REG_3_LANE1_CLKMUX_PHASE_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_3_lane1_concon_adapt_dis_attr == SERDES_SHIM_CPU_PM_REG_3_LANE1_CONCON_ADAPT_DIS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_3_lane1_dco_pi_step_calib_en_attr == SERDES_SHIM_CPU_PM_REG_3_LANE1_DCO_PI_STEP_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_3_lane1_dco_vbuff_calib_en_attr == SERDES_SHIM_CPU_PM_REG_3_LANE1_DCO_VBUFF_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_3_lane1_dco_vgate_calib_en_attr == SERDES_SHIM_CPU_PM_REG_3_LANE1_DCO_VGATE_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_3_lane1_dsp_comm_dfe_n_ffe_en_attr == SERDES_SHIM_CPU_PM_REG_3_LANE1_DSP_COMM_DFE_N_FFE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_3_lane1_dsp_ehm_en_attr == SERDES_SHIM_CPU_PM_REG_3_LANE1_DSP_EHM_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_3_lane1_dsp_en_attr == SERDES_SHIM_CPU_PM_REG_3_LANE1_DSP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_3_lane1_dsp_g_per_sar_en_attr == SERDES_SHIM_CPU_PM_REG_3_LANE1_DSP_G_PER_SAR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_3_lane1_dsp_tap64_en_attr == SERDES_SHIM_CPU_PM_REG_3_LANE1_DSP_TAP64_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_3_lane1_dsp_vref_per_oct_en_attr == SERDES_SHIM_CPU_PM_REG_3_LANE1_DSP_VREF_PER_OCT_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_3_lane1_manual_mode_en_attr == SERDES_SHIM_CPU_PM_REG_3_LANE1_MANUAL_MODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_3_lane1_reduced_th_attr == SERDES_SHIM_CPU_PM_REG_3_LANE1_REDUCED_TH_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_3_lane1_rsrv_1_attr == SERDES_SHIM_CPU_PM_REG_3_LANE1_RSRV_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_3_lane1_rsrv_2_attr == SERDES_SHIM_CPU_PM_REG_3_LANE1_RSRV_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_3_lane1_st1_common_calib_en_attr == SERDES_SHIM_CPU_PM_REG_3_LANE1_ST1_COMMON_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_3_lane1_st1_ofc_calib_en_attr == SERDES_SHIM_CPU_PM_REG_3_LANE1_ST1_OFC_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_3_lane1_st2_common_calib_en_attr == SERDES_SHIM_CPU_PM_REG_3_LANE1_ST2_COMMON_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_3_lane1_st2_ofc_calib_en_attr == SERDES_SHIM_CPU_PM_REG_3_LANE1_ST2_OFC_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_3_lane1_st3_common_calib_en_attr == SERDES_SHIM_CPU_PM_REG_3_LANE1_ST3_COMMON_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_3_lane1_st3_ofc_calib_en_attr == SERDES_SHIM_CPU_PM_REG_3_LANE1_ST3_OFC_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_3_lane1_stand_alone_en_attr == SERDES_SHIM_CPU_PM_REG_3_LANE1_STAND_ALONE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_3_lane1_tx_dcc_calib_en_attr == SERDES_SHIM_CPU_PM_REG_3_LANE1_TX_DCC_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_3_lane1_tx_ldo_calib_en_attr == SERDES_SHIM_CPU_PM_REG_3_LANE1_TX_LDO_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_3_lane1_tx_qec_coarse_calib_en_attr == SERDES_SHIM_CPU_PM_REG_3_LANE1_TX_QEC_COARSE_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_3_lane1_tx_qec_fine_calib_en_attr == SERDES_SHIM_CPU_PM_REG_3_LANE1_TX_QEC_FINE_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_3_lane1_vga_adapt_dis_attr == SERDES_SHIM_CPU_PM_REG_3_LANE1_VGA_ADAPT_DIS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_3_lane1_vga_ofc_calib_en_attr == SERDES_SHIM_CPU_PM_REG_3_LANE1_VGA_OFC_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_40_serdes_wrap_visactrl3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_41_serdes_wrap_visactrl4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_42_serdes_wrap_visactrl5_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_43_serdes_wrap_visactrl6_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_44_serdes_wrap_visactrl7_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_45_serdes_wrap_visaenable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_46_lanes_m0_visactrl0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_47_lanes_m0_visactrl1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_48_lanes_m0_visaenable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_49_lanes_m1_visactrl0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_4_lane2_adc_slc_ofc_calib_en_attr == SERDES_SHIM_CPU_PM_REG_4_LANE2_ADC_SLC_OFC_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_4_lane2_clkgen_duty_cycle_calib_en_attr == SERDES_SHIM_CPU_PM_REG_4_LANE2_CLKGEN_DUTY_CYCLE_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_4_lane2_clkgen_phase_coarse_calib_en_attr == SERDES_SHIM_CPU_PM_REG_4_LANE2_CLKGEN_PHASE_COARSE_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_4_lane2_clkgen_phase_fine_calib_en_attr == SERDES_SHIM_CPU_PM_REG_4_LANE2_CLKGEN_PHASE_FINE_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_4_lane2_clkmux_phase_calib_en_attr == SERDES_SHIM_CPU_PM_REG_4_LANE2_CLKMUX_PHASE_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_4_lane2_concon_adapt_dis_attr == SERDES_SHIM_CPU_PM_REG_4_LANE2_CONCON_ADAPT_DIS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_4_lane2_dco_pi_step_calib_en_attr == SERDES_SHIM_CPU_PM_REG_4_LANE2_DCO_PI_STEP_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_4_lane2_dco_vbuff_calib_en_attr == SERDES_SHIM_CPU_PM_REG_4_LANE2_DCO_VBUFF_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_4_lane2_dco_vgate_calib_en_attr == SERDES_SHIM_CPU_PM_REG_4_LANE2_DCO_VGATE_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_4_lane2_dsp_comm_dfe_n_ffe_en_attr == SERDES_SHIM_CPU_PM_REG_4_LANE2_DSP_COMM_DFE_N_FFE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_4_lane2_dsp_ehm_en_attr == SERDES_SHIM_CPU_PM_REG_4_LANE2_DSP_EHM_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_4_lane2_dsp_en_attr == SERDES_SHIM_CPU_PM_REG_4_LANE2_DSP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_4_lane2_dsp_g_per_sar_en_attr == SERDES_SHIM_CPU_PM_REG_4_LANE2_DSP_G_PER_SAR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_4_lane2_dsp_tap64_en_attr == SERDES_SHIM_CPU_PM_REG_4_LANE2_DSP_TAP64_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_4_lane2_dsp_vref_per_oct_en_attr == SERDES_SHIM_CPU_PM_REG_4_LANE2_DSP_VREF_PER_OCT_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_4_lane2_manual_mode_en_attr == SERDES_SHIM_CPU_PM_REG_4_LANE2_MANUAL_MODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_4_lane2_reduced_th_attr == SERDES_SHIM_CPU_PM_REG_4_LANE2_REDUCED_TH_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_4_lane2_rsrv_1_attr == SERDES_SHIM_CPU_PM_REG_4_LANE2_RSRV_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_4_lane2_rsrv_2_attr == SERDES_SHIM_CPU_PM_REG_4_LANE2_RSRV_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_4_lane2_st1_common_calib_en_attr == SERDES_SHIM_CPU_PM_REG_4_LANE2_ST1_COMMON_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_4_lane2_st1_ofc_calib_en_attr == SERDES_SHIM_CPU_PM_REG_4_LANE2_ST1_OFC_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_4_lane2_st2_common_calib_en_attr == SERDES_SHIM_CPU_PM_REG_4_LANE2_ST2_COMMON_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_4_lane2_st2_ofc_calib_en_attr == SERDES_SHIM_CPU_PM_REG_4_LANE2_ST2_OFC_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_4_lane2_st3_common_calib_en_attr == SERDES_SHIM_CPU_PM_REG_4_LANE2_ST3_COMMON_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_4_lane2_st3_ofc_calib_en_attr == SERDES_SHIM_CPU_PM_REG_4_LANE2_ST3_OFC_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_4_lane2_stand_alone_en_attr == SERDES_SHIM_CPU_PM_REG_4_LANE2_STAND_ALONE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_4_lane2_tx_dcc_calib_en_attr == SERDES_SHIM_CPU_PM_REG_4_LANE2_TX_DCC_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_4_lane2_tx_ldo_calib_en_attr == SERDES_SHIM_CPU_PM_REG_4_LANE2_TX_LDO_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_4_lane2_tx_qec_coarse_calib_en_attr == SERDES_SHIM_CPU_PM_REG_4_LANE2_TX_QEC_COARSE_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_4_lane2_tx_qec_fine_calib_en_attr == SERDES_SHIM_CPU_PM_REG_4_LANE2_TX_QEC_FINE_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_4_lane2_vga_adapt_dis_attr == SERDES_SHIM_CPU_PM_REG_4_LANE2_VGA_ADAPT_DIS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_4_lane2_vga_ofc_calib_en_attr == SERDES_SHIM_CPU_PM_REG_4_LANE2_VGA_OFC_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_50_lanes_m1_visactrl1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_51_lanes_m1_visaenable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_52_lanes_m2_visactrl0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_53_lanes_m2_visactrl1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_54_lanes_m2_visaenable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_55_lanes_m3_visactrl0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_56_lanes_m3_visactrl1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_57_lanes_m3_visaenable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_5_lane3_adc_slc_ofc_calib_en_attr == SERDES_SHIM_CPU_PM_REG_5_LANE3_ADC_SLC_OFC_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_5_lane3_clkgen_duty_cycle_calib_en_attr == SERDES_SHIM_CPU_PM_REG_5_LANE3_CLKGEN_DUTY_CYCLE_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_5_lane3_clkgen_phase_coarse_calib_en_attr == SERDES_SHIM_CPU_PM_REG_5_LANE3_CLKGEN_PHASE_COARSE_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_5_lane3_clkgen_phase_fine_calib_en_attr == SERDES_SHIM_CPU_PM_REG_5_LANE3_CLKGEN_PHASE_FINE_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_5_lane3_clkmux_phase_calib_en_attr == SERDES_SHIM_CPU_PM_REG_5_LANE3_CLKMUX_PHASE_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_5_lane3_concon_adapt_dis_attr == SERDES_SHIM_CPU_PM_REG_5_LANE3_CONCON_ADAPT_DIS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_5_lane3_dco_pi_step_calib_en_attr == SERDES_SHIM_CPU_PM_REG_5_LANE3_DCO_PI_STEP_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_5_lane3_dco_vbuff_calib_en_attr == SERDES_SHIM_CPU_PM_REG_5_LANE3_DCO_VBUFF_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_5_lane3_dco_vgate_calib_en_attr == SERDES_SHIM_CPU_PM_REG_5_LANE3_DCO_VGATE_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_5_lane3_dsp_comm_dfe_n_ffe_en_attr == SERDES_SHIM_CPU_PM_REG_5_LANE3_DSP_COMM_DFE_N_FFE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_5_lane3_dsp_ehm_en_attr == SERDES_SHIM_CPU_PM_REG_5_LANE3_DSP_EHM_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_5_lane3_dsp_en_attr == SERDES_SHIM_CPU_PM_REG_5_LANE3_DSP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_5_lane3_dsp_g_per_sar_en_attr == SERDES_SHIM_CPU_PM_REG_5_LANE3_DSP_G_PER_SAR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_5_lane3_dsp_tap64_en_attr == SERDES_SHIM_CPU_PM_REG_5_LANE3_DSP_TAP64_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_5_lane3_dsp_vref_per_oct_en_attr == SERDES_SHIM_CPU_PM_REG_5_LANE3_DSP_VREF_PER_OCT_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_5_lane3_manual_mode_en_attr == SERDES_SHIM_CPU_PM_REG_5_LANE3_MANUAL_MODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_5_lane3_reduced_th_attr == SERDES_SHIM_CPU_PM_REG_5_LANE3_REDUCED_TH_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_5_lane3_rsrv_1_attr == SERDES_SHIM_CPU_PM_REG_5_LANE3_RSRV_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_5_lane3_rsrv_2_attr == SERDES_SHIM_CPU_PM_REG_5_LANE3_RSRV_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_5_lane3_st1_common_calib_en_attr == SERDES_SHIM_CPU_PM_REG_5_LANE3_ST1_COMMON_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_5_lane3_st1_ofc_calib_en_attr == SERDES_SHIM_CPU_PM_REG_5_LANE3_ST1_OFC_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_5_lane3_st2_common_calib_en_attr == SERDES_SHIM_CPU_PM_REG_5_LANE3_ST2_COMMON_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_5_lane3_st2_ofc_calib_en_attr == SERDES_SHIM_CPU_PM_REG_5_LANE3_ST2_OFC_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_5_lane3_st3_common_calib_en_attr == SERDES_SHIM_CPU_PM_REG_5_LANE3_ST3_COMMON_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_5_lane3_st3_ofc_calib_en_attr == SERDES_SHIM_CPU_PM_REG_5_LANE3_ST3_OFC_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_5_lane3_stand_alone_en_attr == SERDES_SHIM_CPU_PM_REG_5_LANE3_STAND_ALONE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_5_lane3_tx_dcc_calib_en_attr == SERDES_SHIM_CPU_PM_REG_5_LANE3_TX_DCC_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_5_lane3_tx_ldo_calib_en_attr == SERDES_SHIM_CPU_PM_REG_5_LANE3_TX_LDO_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_5_lane3_tx_qec_coarse_calib_en_attr == SERDES_SHIM_CPU_PM_REG_5_LANE3_TX_QEC_COARSE_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_5_lane3_tx_qec_fine_calib_en_attr == SERDES_SHIM_CPU_PM_REG_5_LANE3_TX_QEC_FINE_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_5_lane3_vga_adapt_dis_attr == SERDES_SHIM_CPU_PM_REG_5_LANE3_VGA_ADAPT_DIS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_5_lane3_vga_ofc_calib_en_attr == SERDES_SHIM_CPU_PM_REG_5_LANE3_VGA_OFC_CALIB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_64_cpu_pm_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_64_cpu_pm_sec_acc_ctrl_broadcast_mode_attr == SERDES_SHIM_CPU_PM_REG_64_CPU_PM_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_64_cpu_pm_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_64_cpu_pm_sec_acc_ctrl_field_mask_write_en_attr == SERDES_SHIM_CPU_PM_REG_64_CPU_PM_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_64_cpu_pm_sec_acc_ctrl_load_preset_attr == SERDES_SHIM_CPU_PM_REG_64_CPU_PM_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_64_cpu_pm_sec_acc_ctrl_man_clear_on_read_attr == SERDES_SHIM_CPU_PM_REG_64_CPU_PM_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_64_cpu_pm_sec_acc_ctrl_man_self_clear_attr == SERDES_SHIM_CPU_PM_REG_64_CPU_PM_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_64_cpu_pm_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_64_cpu_pm_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_64_cpu_pm_sec_acc_ctrl_soft_reset_n_attr == SERDES_SHIM_CPU_PM_REG_64_CPU_PM_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_64_cpu_pm_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_65_cpu_pm_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_65_cpu_pm_reg2probe_en_attr == SERDES_SHIM_CPU_PM_REG_65_CPU_PM_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_66_uc_timer_start_sc_common_attr == SERDES_SHIM_CPU_PM_REG_66_UC_TIMER_START_SC_COMMON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_66_uc_timer_start_sc_lane0_attr == SERDES_SHIM_CPU_PM_REG_66_UC_TIMER_START_SC_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_66_uc_timer_start_sc_lane1_attr == SERDES_SHIM_CPU_PM_REG_66_UC_TIMER_START_SC_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_66_uc_timer_start_sc_lane2_attr == SERDES_SHIM_CPU_PM_REG_66_UC_TIMER_START_SC_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_66_uc_timer_start_sc_lane3_attr == SERDES_SHIM_CPU_PM_REG_66_UC_TIMER_START_SC_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_67_uc_timer_limit_common_attr == 32'd2000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_68_uc_timer_limit_lane0_attr == 32'd2000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_69_uc_timer_limit_lane1_attr == 32'd2000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_6_main_auto_halt_release_attr == SERDES_SHIM_CPU_PM_REG_6_MAIN_AUTO_HALT_RELEASE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_6_main_fsm_reset_attr == SERDES_SHIM_CPU_PM_REG_6_MAIN_FSM_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_6_main_halt_on_state_attr == 10'd1023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_6_main_jump_attr == SERDES_SHIM_CPU_PM_REG_6_MAIN_JUMP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_6_main_jump_from_halt_to_state_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_6_main_release_halt_attr == SERDES_SHIM_CPU_PM_REG_6_MAIN_RELEASE_HALT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_70_uc_timer_limit_lane2_attr == 32'd2000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_71_uc_timer_limit_lane3_attr == 32'd2000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_72_uc_fsm_state_timer_en_attr == SERDES_SHIM_CPU_PM_REG_72_UC_FSM_STATE_TIMER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_72_uc_fsm_state_timer_th_attr == 31'd2000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_75_temerature_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_7_lane0_auto_halt_release_attr == SERDES_SHIM_CPU_PM_REG_7_LANE0_AUTO_HALT_RELEASE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_7_lane0_fsm_reset_attr == SERDES_SHIM_CPU_PM_REG_7_LANE0_FSM_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_7_lane0_halt_on_state_attr == 10'd1023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_7_lane0_jump_attr == SERDES_SHIM_CPU_PM_REG_7_LANE0_JUMP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_7_lane0_jump_from_halt_to_state_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_7_lane0_release_halt_attr == SERDES_SHIM_CPU_PM_REG_7_LANE0_RELEASE_HALT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_8_lane1_auto_halt_release_attr == SERDES_SHIM_CPU_PM_REG_8_LANE1_AUTO_HALT_RELEASE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_8_lane1_fsm_reset_attr == SERDES_SHIM_CPU_PM_REG_8_LANE1_FSM_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_8_lane1_halt_on_state_attr == 10'd1023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_8_lane1_jump_attr == SERDES_SHIM_CPU_PM_REG_8_LANE1_JUMP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_8_lane1_jump_from_halt_to_state_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_8_lane1_release_halt_attr == SERDES_SHIM_CPU_PM_REG_8_LANE1_RELEASE_HALT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_92_fuse_clkbyp_iram0_attr == SERDES_SHIM_CPU_PM_REG_92_FUSE_CLKBYP_IRAM0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_92_fuse_mce_iram0_attr == SERDES_SHIM_CPU_PM_REG_92_FUSE_MCE_IRAM0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_92_fuse_ra_iram0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_92_fuse_rmce_iram0_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_92_fuse_wa_iram0_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_92_fuse_wmce_iram0_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_92_fuse_wpulse_iram0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_93_fuse_clkbyp_iram1_attr == SERDES_SHIM_CPU_PM_REG_93_FUSE_CLKBYP_IRAM1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_93_fuse_mce_iram1_attr == SERDES_SHIM_CPU_PM_REG_93_FUSE_MCE_IRAM1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_93_fuse_ra_iram1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_93_fuse_rmce_iram1_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_93_fuse_wa_iram1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_93_fuse_wmce_iram1_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_93_fuse_wpulse_iram1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_94_fuse_clkbyp_iram2_attr == SERDES_SHIM_CPU_PM_REG_94_FUSE_CLKBYP_IRAM2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_94_fuse_mce_iram2_attr == SERDES_SHIM_CPU_PM_REG_94_FUSE_MCE_IRAM2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_94_fuse_ra_iram2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_94_fuse_rmce_iram2_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_94_fuse_wa_iram2_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_94_fuse_wmce_iram2_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_94_fuse_wpulse_iram2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_95_fuse_clkbyp_iram3_attr == SERDES_SHIM_CPU_PM_REG_95_FUSE_CLKBYP_IRAM3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_95_fuse_mce_iram3_attr == SERDES_SHIM_CPU_PM_REG_95_FUSE_MCE_IRAM3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_95_fuse_ra_iram3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_95_fuse_rmce_iram3_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_95_fuse_wa_iram3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_95_fuse_wmce_iram3_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_95_fuse_wpulse_iram3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_96_fuse_clkbyp_iram4_attr == SERDES_SHIM_CPU_PM_REG_96_FUSE_CLKBYP_IRAM4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_96_fuse_mce_iram4_attr == SERDES_SHIM_CPU_PM_REG_96_FUSE_MCE_IRAM4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_96_fuse_ra_iram4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_96_fuse_rmce_iram4_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_96_fuse_wa_iram4_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_96_fuse_wmce_iram4_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_96_fuse_wpulse_iram4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_97_fuse_clkbyp_iram5_attr == SERDES_SHIM_CPU_PM_REG_97_FUSE_CLKBYP_IRAM5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_97_fuse_mce_iram5_attr == SERDES_SHIM_CPU_PM_REG_97_FUSE_MCE_IRAM5_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_97_fuse_ra_iram5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_97_fuse_rmce_iram5_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_97_fuse_wa_iram5_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_97_fuse_wmce_iram5_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_97_fuse_wpulse_iram5_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_98_fuse_clkbyp_iram6_attr == SERDES_SHIM_CPU_PM_REG_98_FUSE_CLKBYP_IRAM6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_98_fuse_mce_iram6_attr == SERDES_SHIM_CPU_PM_REG_98_FUSE_MCE_IRAM6_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_98_fuse_ra_iram6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_98_fuse_rmce_iram6_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_98_fuse_wa_iram6_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_98_fuse_wmce_iram6_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_98_fuse_wpulse_iram6_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_99_fuse_clkbyp_iram7_attr == SERDES_SHIM_CPU_PM_REG_99_FUSE_CLKBYP_IRAM7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_99_fuse_mce_iram7_attr == SERDES_SHIM_CPU_PM_REG_99_FUSE_MCE_IRAM7_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_99_fuse_ra_iram7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_99_fuse_rmce_iram7_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_99_fuse_wa_iram7_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_99_fuse_wmce_iram7_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_99_fuse_wpulse_iram7_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_9_lane2_auto_halt_release_attr == SERDES_SHIM_CPU_PM_REG_9_LANE2_AUTO_HALT_RELEASE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_9_lane2_fsm_reset_attr == SERDES_SHIM_CPU_PM_REG_9_LANE2_FSM_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_9_lane2_halt_on_state_attr == 10'd1023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_9_lane2_jump_attr == SERDES_SHIM_CPU_PM_REG_9_LANE2_JUMP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_9_lane2_jump_from_halt_to_state_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_cpu_pm_reg_9_lane2_release_halt_attr == SERDES_SHIM_CPU_PM_REG_9_LANE2_RELEASE_HALT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_10_cfg_phymon_addr14_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_10_cfg_phymon_addr15_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_11_cfg_phymon_addr16_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_11_cfg_phymon_addr17_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_12_cfg_phymon_addr18_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_12_cfg_phymon_addr19_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_13_cfg_phymon_addr20_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_13_cfg_phymon_addr21_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_14_cfg_phymon_addr22_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_14_cfg_phymon_addr23_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_15_cfg_phymon_addr24_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_15_cfg_phymon_addr25_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_16_cfg_phymon_addr26_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_16_cfg_phymon_addr27_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_17_cfg_phymon_addr28_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_17_cfg_phymon_addr29_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_18_cfg_phymon_addr30_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_18_cfg_phymon_addr31_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_19_cfg_phymon_marker_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_1_cfg_blk_probe_samp_en_attr == SERDES_SHIM_LANE_WRAP_REG_1_CFG_BLK_PROBE_SAMP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_1_cfg_core_probe_samp_en_attr == SERDES_SHIM_LANE_WRAP_REG_1_CFG_CORE_PROBE_SAMP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_1_cfg_probe_addr_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_1_cfg_probe_id_out_sel_attr == SERDES_SHIM_LANE_WRAP_REG_1_CFG_PROBE_ID_OUT_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_1_cfg_top_clk_data_prb_sel_attr == SERDES_SHIM_LANE_WRAP_REG_1_CFG_TOP_CLK_DATA_PRB_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_20_cfg_phymon_last_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_20_cfg_phymon_marker_cyc_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_20_cfg_phymon_marker_dly_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_20_cfg_phymon_marker_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_20_cfg_phymon_marker_time_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_20_cfg_phymon_self_probe_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_21_lane_wrap_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_21_lane_wrap_sec_acc_ctrl_broadcast_mode_attr == SERDES_SHIM_LANE_WRAP_REG_21_LANE_WRAP_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_21_lane_wrap_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_21_lane_wrap_sec_acc_ctrl_field_mask_write_en_attr == SERDES_SHIM_LANE_WRAP_REG_21_LANE_WRAP_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_21_lane_wrap_sec_acc_ctrl_load_preset_attr == SERDES_SHIM_LANE_WRAP_REG_21_LANE_WRAP_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_21_lane_wrap_sec_acc_ctrl_man_clear_on_read_attr == SERDES_SHIM_LANE_WRAP_REG_21_LANE_WRAP_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_21_lane_wrap_sec_acc_ctrl_man_self_clear_attr == SERDES_SHIM_LANE_WRAP_REG_21_LANE_WRAP_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_21_lane_wrap_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_21_lane_wrap_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_21_lane_wrap_sec_acc_ctrl_soft_reset_n_attr == SERDES_SHIM_LANE_WRAP_REG_21_LANE_WRAP_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_21_lane_wrap_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_22_lane_wrap_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_22_lane_wrap_reg2probe_en_attr == SERDES_SHIM_LANE_WRAP_REG_22_LANE_WRAP_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_23_cfg_an_gb32to80_start_rd_ptr_force_en_lane0_attr == SERDES_SHIM_LANE_WRAP_REG_23_CFG_AN_GB32TO80_START_RD_PTR_FORCE_EN_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_23_cfg_an_gb32to80_start_rd_ptr_force_en_lane1_attr == SERDES_SHIM_LANE_WRAP_REG_23_CFG_AN_GB32TO80_START_RD_PTR_FORCE_EN_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_23_cfg_an_gb32to80_start_rd_ptr_force_en_lane2_attr == SERDES_SHIM_LANE_WRAP_REG_23_CFG_AN_GB32TO80_START_RD_PTR_FORCE_EN_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_23_cfg_an_gb32to80_start_rd_ptr_force_en_lane3_attr == SERDES_SHIM_LANE_WRAP_REG_23_CFG_AN_GB32TO80_START_RD_PTR_FORCE_EN_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_23_cfg_an_gb32to80_start_rd_ptr_force_lane0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_23_cfg_an_gb32to80_start_rd_ptr_force_lane1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_23_cfg_an_gb32to80_start_rd_ptr_force_lane2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_23_cfg_an_gb32to80_start_rd_ptr_force_lane3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_23_cfg_an_gb80to32_start_rd_ptr_force_en_lane0_attr == SERDES_SHIM_LANE_WRAP_REG_23_CFG_AN_GB80TO32_START_RD_PTR_FORCE_EN_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_23_cfg_an_gb80to32_start_rd_ptr_force_en_lane1_attr == SERDES_SHIM_LANE_WRAP_REG_23_CFG_AN_GB80TO32_START_RD_PTR_FORCE_EN_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_23_cfg_an_gb80to32_start_rd_ptr_force_en_lane2_attr == SERDES_SHIM_LANE_WRAP_REG_23_CFG_AN_GB80TO32_START_RD_PTR_FORCE_EN_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_23_cfg_an_gb80to32_start_rd_ptr_force_en_lane3_attr == SERDES_SHIM_LANE_WRAP_REG_23_CFG_AN_GB80TO32_START_RD_PTR_FORCE_EN_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_23_cfg_an_gb80to32_start_rd_ptr_force_lane0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_23_cfg_an_gb80to32_start_rd_ptr_force_lane1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_23_cfg_an_gb80to32_start_rd_ptr_force_lane2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_23_cfg_an_gb80to32_start_rd_ptr_force_lane3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_25_irq_en_attr == 24'd16709565
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_26_irq_clr_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_27_irq_inv_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_29_ecsr_ahb_bridge_clear_error_attr == SERDES_SHIM_LANE_WRAP_REG_29_ECSR_AHB_BRIDGE_CLEAR_ERROR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_29_ecsr_ahb_bridge_to_limit_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_2_cfg_phymon_burst_mode_attr == SERDES_SHIM_LANE_WRAP_REG_2_CFG_PHYMON_BURST_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_2_cfg_phymon_man_cnt_attr == SERDES_SHIM_LANE_WRAP_REG_2_CFG_PHYMON_MAN_CNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_2_cfg_phymon_man_mode_attr == SERDES_SHIM_LANE_WRAP_REG_2_CFG_PHYMON_MAN_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_2_cfg_phymon_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_2_cfg_phymon_samp_n_hold_attr == SERDES_SHIM_LANE_WRAP_REG_2_CFG_PHYMON_SAMP_N_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_2_cfg_phymon_start_attr == SERDES_SHIM_LANE_WRAP_REG_2_CFG_PHYMON_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_2_cfg_phymon_stop_attr == SERDES_SHIM_LANE_WRAP_REG_2_CFG_PHYMON_STOP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_2_cfg_phymon_timer_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_2_cfg_polar_en_attr == SERDES_SHIM_LANE_WRAP_REG_2_CFG_POLAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_2_cfg_polar_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_31_brk_int_out_by_reg_attr == SERDES_SHIM_LANE_WRAP_REG_31_BRK_INT_OUT_BY_REG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_3_cfg_phymon_addr0_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_3_cfg_phymon_addr1_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_4_cfg_phymon_addr2_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_4_cfg_phymon_addr3_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_5_cfg_phymon_addr4_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_5_cfg_phymon_addr5_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_6_cfg_phymon_addr6_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_6_cfg_phymon_addr7_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_7_cfg_phymon_addr8_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_7_cfg_phymon_addr9_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_8_cfg_phymon_addr10_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_8_cfg_phymon_addr11_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_9_cfg_phymon_addr12_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_lane_wrap_reg_9_cfg_phymon_addr13_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_10_cfg_tfl_rx_cl72_clear_one_marker_seen_attr == SERDES_SHIM_TFL_LANE0_REG_10_CFG_TFL_RX_CL72_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_10_cfg_tfl_rx_cl72_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_LANE0_REG_10_CFG_TFL_RX_CL72_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_10_cfg_tfl_rx_cl72_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_10_cfg_tfl_rx_cl72_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_10_cfg_tfl_rx_cl72_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_LANE0_REG_10_CFG_TFL_RX_CL72_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_10_cfg_tfl_rx_cl72_prbs_ber_en_attr == SERDES_SHIM_TFL_LANE0_REG_10_CFG_TFL_RX_CL72_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_10_cfg_tfl_rx_cl72_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_10_cfg_tfl_rx_cl72_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_10_cfg_tfl_rx_cl72_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_11_cfg_tfl_rx_cl72_ber_count_snap_lock_attr == SERDES_SHIM_TFL_LANE0_REG_11_CFG_TFL_RX_CL72_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_11_cfg_tfl_rx_cl72_ber_counter_clear_attr == SERDES_SHIM_TFL_LANE0_REG_11_CFG_TFL_RX_CL72_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_11_cfg_tfl_rx_cl72_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_LANE0_REG_11_CFG_TFL_RX_CL72_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_11_cfg_tfl_rx_cl72_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_11_cfg_tfl_rx_cl72_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_11_cfg_tfl_rx_cl72_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_11_cfg_tfl_rx_cl72_prbs_seed_force_en_attr == SERDES_SHIM_TFL_LANE0_REG_11_CFG_TFL_RX_CL72_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_11_cfg_tfl_rx_cl72_prbs_seed_force_val_attr == 13'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_12_cfg_tfl_cl136_ctrl_field_11_10_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_12_cfg_tfl_cl136_ctrl_field_13_12_init_cond_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_12_cfg_tfl_cl136_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_12_cfg_tfl_cl136_ctrl_field_1_0_coeff_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_12_cfg_tfl_cl136_ctrl_field_4_2_coeff_select_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_12_cfg_tfl_cl136_ctrl_field_7_5_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_12_cfg_tfl_cl136_ctrl_field_9_8_mod_precode_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_13_cfg_tfl_rx_cl136_clear_one_marker_seen_attr == SERDES_SHIM_TFL_LANE0_REG_13_CFG_TFL_RX_CL136_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_13_cfg_tfl_rx_cl136_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_13_cfg_tfl_rx_cl136_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_13_cfg_tfl_rx_cl136_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_LANE0_REG_13_CFG_TFL_RX_CL136_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_13_cfg_tfl_rx_cl136_pam4_modulation_select_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_13_cfg_tfl_rx_cl136_prbs_ber_en_attr == SERDES_SHIM_TFL_LANE0_REG_13_CFG_TFL_RX_CL136_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_13_cfg_tfl_rx_cl136_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_13_cfg_tfl_rx_cl136_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_13_cfg_tfl_rx_cl136_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_14_cfg_tfl_rx_cl136_ber_count_snap_lock_attr == SERDES_SHIM_TFL_LANE0_REG_14_CFG_TFL_RX_CL136_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_14_cfg_tfl_rx_cl136_ber_counter_clear_attr == SERDES_SHIM_TFL_LANE0_REG_14_CFG_TFL_RX_CL136_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_14_cfg_tfl_rx_cl136_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_LANE0_REG_14_CFG_TFL_RX_CL136_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_14_cfg_tfl_rx_cl136_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_LANE0_REG_14_CFG_TFL_RX_CL136_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_14_cfg_tfl_rx_cl136_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_14_cfg_tfl_rx_cl136_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_14_cfg_tfl_rx_cl136_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_14_cfg_tfl_rx_cl136_prbs_seed_force_en_attr == SERDES_SHIM_TFL_LANE0_REG_14_CFG_TFL_RX_CL136_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_14_cfg_tfl_rx_cl136_prbs_seed_force_val_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_17_cfg_tfl_cl136_stts_field_11_10_mod_precode_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_17_cfg_tfl_cl136_stts_field_14_12_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_17_cfg_tfl_cl136_stts_field_15_rx_ready_attr == SERDES_SHIM_TFL_LANE0_REG_17_CFG_TFL_CL136_STTS_FIELD_15_RX_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_17_cfg_tfl_cl136_stts_field_2_0_coeff_stts_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_17_cfg_tfl_cl136_stts_field_5_3_coeff_sel_echo_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_17_cfg_tfl_cl136_stts_field_6_rsvd_attr == SERDES_SHIM_TFL_LANE0_REG_17_CFG_TFL_CL136_STTS_FIELD_6_RSVD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_17_cfg_tfl_cl136_stts_field_7_parity_attr == SERDES_SHIM_TFL_LANE0_REG_17_CFG_TFL_CL136_STTS_FIELD_7_PARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_17_cfg_tfl_cl136_stts_field_8_init_cond_stts_attr == SERDES_SHIM_TFL_LANE0_REG_17_CFG_TFL_CL136_STTS_FIELD_8_INIT_COND_STTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_17_cfg_tfl_cl136_stts_field_9_rx_frame_lock_attr == SERDES_SHIM_TFL_LANE0_REG_17_CFG_TFL_CL136_STTS_FIELD_9_RX_FRAME_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_1_tfl_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_1_tfl_sec_acc_ctrl_broadcast_mode_attr == SERDES_SHIM_TFL_LANE0_REG_1_TFL_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_1_tfl_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_1_tfl_sec_acc_ctrl_field_mask_write_en_attr == SERDES_SHIM_TFL_LANE0_REG_1_TFL_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_1_tfl_sec_acc_ctrl_load_preset_attr == SERDES_SHIM_TFL_LANE0_REG_1_TFL_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_1_tfl_sec_acc_ctrl_man_clear_on_read_attr == SERDES_SHIM_TFL_LANE0_REG_1_TFL_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_1_tfl_sec_acc_ctrl_man_self_clear_attr == SERDES_SHIM_TFL_LANE0_REG_1_TFL_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_1_tfl_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_1_tfl_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_1_tfl_sec_acc_ctrl_soft_reset_n_attr == SERDES_SHIM_TFL_LANE0_REG_1_TFL_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_1_tfl_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_29_cfg_tfl_prbs13_seed_2_attr == 13'd7571
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_29_cfg_tfl_prbs13_seed_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_2_tfl_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_2_tfl_reg2probe_en_attr == SERDES_SHIM_TFL_LANE0_REG_2_TFL_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_36_cfg_tfl_gb_128_80_en_attr == SERDES_SHIM_TFL_LANE0_REG_36_CFG_TFL_GB_128_80_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_36_cfg_tfl_gb_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_3_cfg_tfl_frame_boundary_early_attr == SERDES_SHIM_TFL_LANE0_REG_3_CFG_TFL_FRAME_BOUNDARY_EARLY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_3_cfg_tfl_ignore_tfl_en_to_avoid_cut_frame_attr == SERDES_SHIM_TFL_LANE0_REG_3_CFG_TFL_IGNORE_TFL_EN_TO_AVOID_CUT_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_3_cfg_tfl_polynomial_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_3_cfg_tfl_pulse_sync_attr == SERDES_SHIM_TFL_LANE0_REG_3_CFG_TFL_PULSE_SYNC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_3_cfg_tfl_scrambler_force_init_at_each_frame_attr == SERDES_SHIM_TFL_LANE0_REG_3_CFG_TFL_SCRAMBLER_FORCE_INIT_AT_EACH_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_3_cfg_tfl_send_data_attr == SERDES_SHIM_TFL_LANE0_REG_3_CFG_TFL_SEND_DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_3_cfg_tfl_sync_ctrl_stts_word_pulse_attr == SERDES_SHIM_TFL_LANE0_REG_3_CFG_TFL_SYNC_CTRL_STTS_WORD_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_3_cfg_tfl_training_enable_tx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_3_cfg_tfl_tx_samp_cnt_max_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_3_cfg_tx_grey_sym_lut_attr == 8'd216
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_3_cfg_tx_swizzle_mode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_4_cfg_tfl_cl72_frame_cycle_to_lock_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_4_cfg_tfl_prbs11_en_attr == SERDES_SHIM_TFL_LANE0_REG_4_CFG_TFL_PRBS11_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_4_cfg_tfl_prbs11_seed_2_attr == 11'd977
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_4_cfg_tfl_prbs11_seed_attr == 11'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_5_cfg_tfl_cl136_frame_cycle_to_lock_attr == 10'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_5_cfg_tfl_cl136_prbs_encoder_select_even_attr == SERDES_SHIM_TFL_LANE0_REG_5_CFG_TFL_CL136_PRBS_ENCODER_SELECT_EVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_5_cfg_tfl_cl136_precoder_out_swz_attr == SERDES_SHIM_TFL_LANE0_REG_5_CFG_TFL_CL136_PRECODER_OUT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_5_cfg_tfl_cl136_precoder_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_5_cfg_tfl_prbs13_en_attr == SERDES_SHIM_TFL_LANE0_REG_5_CFG_TFL_PRBS13_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_6_cfg_tfl_cl72_ctrl_field_11_6_rsvd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_6_cfg_tfl_cl72_ctrl_field_12_initialize_attr == SERDES_SHIM_TFL_LANE0_REG_6_CFG_TFL_CL72_CTRL_FIELD_12_INITIALIZE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_6_cfg_tfl_cl72_ctrl_field_13_preset_attr == SERDES_SHIM_TFL_LANE0_REG_6_CFG_TFL_CL72_CTRL_FIELD_13_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_6_cfg_tfl_cl72_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_6_cfg_tfl_cl72_ctrl_field_1_0_coef_m1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_6_cfg_tfl_cl72_ctrl_field_3_2_coef_0_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_6_cfg_tfl_cl72_ctrl_field_5_4_coef_p1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_7_cfg_tfl_cl72_stts_field_14_6_rsvd_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_7_cfg_tfl_cl72_stts_field_15_rcv_ready_attr == SERDES_SHIM_TFL_LANE0_REG_7_CFG_TFL_CL72_STTS_FIELD_15_RCV_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_7_cfg_tfl_cl72_stts_field_1_0_coef_m1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_7_cfg_tfl_cl72_stts_field_3_2_coef_0_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_7_cfg_tfl_cl72_stts_field_5_4_coef_p1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_9_cfg_rx_grey_sym_lut_attr == 8'd216
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_9_cfg_rx_swizzle_mode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_9_cfg_tfl_rx_samp_cnt_max_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_9_cfg_tfl_rx_sync_pulse_attr == SERDES_SHIM_TFL_LANE0_REG_9_CFG_TFL_RX_SYNC_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane0_reg_9_cfg_tfl_training_enable_rx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_10_cfg_tfl_rx_cl72_clear_one_marker_seen_attr == SERDES_SHIM_TFL_LANE1_REG_10_CFG_TFL_RX_CL72_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_10_cfg_tfl_rx_cl72_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_LANE1_REG_10_CFG_TFL_RX_CL72_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_10_cfg_tfl_rx_cl72_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_10_cfg_tfl_rx_cl72_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_10_cfg_tfl_rx_cl72_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_LANE1_REG_10_CFG_TFL_RX_CL72_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_10_cfg_tfl_rx_cl72_prbs_ber_en_attr == SERDES_SHIM_TFL_LANE1_REG_10_CFG_TFL_RX_CL72_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_10_cfg_tfl_rx_cl72_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_10_cfg_tfl_rx_cl72_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_10_cfg_tfl_rx_cl72_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_11_cfg_tfl_rx_cl72_ber_count_snap_lock_attr == SERDES_SHIM_TFL_LANE1_REG_11_CFG_TFL_RX_CL72_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_11_cfg_tfl_rx_cl72_ber_counter_clear_attr == SERDES_SHIM_TFL_LANE1_REG_11_CFG_TFL_RX_CL72_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_11_cfg_tfl_rx_cl72_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_LANE1_REG_11_CFG_TFL_RX_CL72_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_11_cfg_tfl_rx_cl72_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_11_cfg_tfl_rx_cl72_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_11_cfg_tfl_rx_cl72_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_11_cfg_tfl_rx_cl72_prbs_seed_force_en_attr == SERDES_SHIM_TFL_LANE1_REG_11_CFG_TFL_RX_CL72_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_11_cfg_tfl_rx_cl72_prbs_seed_force_val_attr == 13'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_12_cfg_tfl_cl136_ctrl_field_11_10_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_12_cfg_tfl_cl136_ctrl_field_13_12_init_cond_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_12_cfg_tfl_cl136_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_12_cfg_tfl_cl136_ctrl_field_1_0_coeff_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_12_cfg_tfl_cl136_ctrl_field_4_2_coeff_select_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_12_cfg_tfl_cl136_ctrl_field_7_5_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_12_cfg_tfl_cl136_ctrl_field_9_8_mod_precode_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_13_cfg_tfl_rx_cl136_clear_one_marker_seen_attr == SERDES_SHIM_TFL_LANE1_REG_13_CFG_TFL_RX_CL136_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_13_cfg_tfl_rx_cl136_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_13_cfg_tfl_rx_cl136_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_13_cfg_tfl_rx_cl136_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_LANE1_REG_13_CFG_TFL_RX_CL136_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_13_cfg_tfl_rx_cl136_pam4_modulation_select_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_13_cfg_tfl_rx_cl136_prbs_ber_en_attr == SERDES_SHIM_TFL_LANE1_REG_13_CFG_TFL_RX_CL136_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_13_cfg_tfl_rx_cl136_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_13_cfg_tfl_rx_cl136_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_13_cfg_tfl_rx_cl136_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_14_cfg_tfl_rx_cl136_ber_count_snap_lock_attr == SERDES_SHIM_TFL_LANE1_REG_14_CFG_TFL_RX_CL136_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_14_cfg_tfl_rx_cl136_ber_counter_clear_attr == SERDES_SHIM_TFL_LANE1_REG_14_CFG_TFL_RX_CL136_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_14_cfg_tfl_rx_cl136_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_LANE1_REG_14_CFG_TFL_RX_CL136_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_14_cfg_tfl_rx_cl136_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_LANE1_REG_14_CFG_TFL_RX_CL136_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_14_cfg_tfl_rx_cl136_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_14_cfg_tfl_rx_cl136_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_14_cfg_tfl_rx_cl136_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_14_cfg_tfl_rx_cl136_prbs_seed_force_en_attr == SERDES_SHIM_TFL_LANE1_REG_14_CFG_TFL_RX_CL136_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_14_cfg_tfl_rx_cl136_prbs_seed_force_val_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_17_cfg_tfl_cl136_stts_field_11_10_mod_precode_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_17_cfg_tfl_cl136_stts_field_14_12_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_17_cfg_tfl_cl136_stts_field_15_rx_ready_attr == SERDES_SHIM_TFL_LANE1_REG_17_CFG_TFL_CL136_STTS_FIELD_15_RX_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_17_cfg_tfl_cl136_stts_field_2_0_coeff_stts_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_17_cfg_tfl_cl136_stts_field_5_3_coeff_sel_echo_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_17_cfg_tfl_cl136_stts_field_6_rsvd_attr == SERDES_SHIM_TFL_LANE1_REG_17_CFG_TFL_CL136_STTS_FIELD_6_RSVD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_17_cfg_tfl_cl136_stts_field_7_parity_attr == SERDES_SHIM_TFL_LANE1_REG_17_CFG_TFL_CL136_STTS_FIELD_7_PARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_17_cfg_tfl_cl136_stts_field_8_init_cond_stts_attr == SERDES_SHIM_TFL_LANE1_REG_17_CFG_TFL_CL136_STTS_FIELD_8_INIT_COND_STTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_17_cfg_tfl_cl136_stts_field_9_rx_frame_lock_attr == SERDES_SHIM_TFL_LANE1_REG_17_CFG_TFL_CL136_STTS_FIELD_9_RX_FRAME_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_1_tfl_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_1_tfl_sec_acc_ctrl_broadcast_mode_attr == SERDES_SHIM_TFL_LANE1_REG_1_TFL_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_1_tfl_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_1_tfl_sec_acc_ctrl_field_mask_write_en_attr == SERDES_SHIM_TFL_LANE1_REG_1_TFL_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_1_tfl_sec_acc_ctrl_load_preset_attr == SERDES_SHIM_TFL_LANE1_REG_1_TFL_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_1_tfl_sec_acc_ctrl_man_clear_on_read_attr == SERDES_SHIM_TFL_LANE1_REG_1_TFL_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_1_tfl_sec_acc_ctrl_man_self_clear_attr == SERDES_SHIM_TFL_LANE1_REG_1_TFL_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_1_tfl_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_1_tfl_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_1_tfl_sec_acc_ctrl_soft_reset_n_attr == SERDES_SHIM_TFL_LANE1_REG_1_TFL_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_1_tfl_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_29_cfg_tfl_prbs13_seed_2_attr == 13'd7571
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_29_cfg_tfl_prbs13_seed_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_2_tfl_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_2_tfl_reg2probe_en_attr == SERDES_SHIM_TFL_LANE1_REG_2_TFL_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_36_cfg_tfl_gb_128_80_en_attr == SERDES_SHIM_TFL_LANE1_REG_36_CFG_TFL_GB_128_80_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_36_cfg_tfl_gb_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_3_cfg_tfl_frame_boundary_early_attr == SERDES_SHIM_TFL_LANE1_REG_3_CFG_TFL_FRAME_BOUNDARY_EARLY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_3_cfg_tfl_ignore_tfl_en_to_avoid_cut_frame_attr == SERDES_SHIM_TFL_LANE1_REG_3_CFG_TFL_IGNORE_TFL_EN_TO_AVOID_CUT_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_3_cfg_tfl_polynomial_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_3_cfg_tfl_pulse_sync_attr == SERDES_SHIM_TFL_LANE1_REG_3_CFG_TFL_PULSE_SYNC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_3_cfg_tfl_scrambler_force_init_at_each_frame_attr == SERDES_SHIM_TFL_LANE1_REG_3_CFG_TFL_SCRAMBLER_FORCE_INIT_AT_EACH_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_3_cfg_tfl_send_data_attr == SERDES_SHIM_TFL_LANE1_REG_3_CFG_TFL_SEND_DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_3_cfg_tfl_sync_ctrl_stts_word_pulse_attr == SERDES_SHIM_TFL_LANE1_REG_3_CFG_TFL_SYNC_CTRL_STTS_WORD_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_3_cfg_tfl_training_enable_tx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_3_cfg_tfl_tx_samp_cnt_max_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_3_cfg_tx_grey_sym_lut_attr == 8'd216
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_3_cfg_tx_swizzle_mode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_4_cfg_tfl_cl72_frame_cycle_to_lock_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_4_cfg_tfl_prbs11_en_attr == SERDES_SHIM_TFL_LANE1_REG_4_CFG_TFL_PRBS11_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_4_cfg_tfl_prbs11_seed_2_attr == 11'd977
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_4_cfg_tfl_prbs11_seed_attr == 11'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_5_cfg_tfl_cl136_frame_cycle_to_lock_attr == 10'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_5_cfg_tfl_cl136_prbs_encoder_select_even_attr == SERDES_SHIM_TFL_LANE1_REG_5_CFG_TFL_CL136_PRBS_ENCODER_SELECT_EVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_5_cfg_tfl_cl136_precoder_out_swz_attr == SERDES_SHIM_TFL_LANE1_REG_5_CFG_TFL_CL136_PRECODER_OUT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_5_cfg_tfl_cl136_precoder_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_5_cfg_tfl_prbs13_en_attr == SERDES_SHIM_TFL_LANE1_REG_5_CFG_TFL_PRBS13_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_6_cfg_tfl_cl72_ctrl_field_11_6_rsvd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_6_cfg_tfl_cl72_ctrl_field_12_initialize_attr == SERDES_SHIM_TFL_LANE1_REG_6_CFG_TFL_CL72_CTRL_FIELD_12_INITIALIZE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_6_cfg_tfl_cl72_ctrl_field_13_preset_attr == SERDES_SHIM_TFL_LANE1_REG_6_CFG_TFL_CL72_CTRL_FIELD_13_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_6_cfg_tfl_cl72_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_6_cfg_tfl_cl72_ctrl_field_1_0_coef_m1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_6_cfg_tfl_cl72_ctrl_field_3_2_coef_0_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_6_cfg_tfl_cl72_ctrl_field_5_4_coef_p1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_7_cfg_tfl_cl72_stts_field_14_6_rsvd_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_7_cfg_tfl_cl72_stts_field_15_rcv_ready_attr == SERDES_SHIM_TFL_LANE1_REG_7_CFG_TFL_CL72_STTS_FIELD_15_RCV_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_7_cfg_tfl_cl72_stts_field_1_0_coef_m1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_7_cfg_tfl_cl72_stts_field_3_2_coef_0_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_7_cfg_tfl_cl72_stts_field_5_4_coef_p1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_9_cfg_rx_grey_sym_lut_attr == 8'd216
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_9_cfg_rx_swizzle_mode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_9_cfg_tfl_rx_samp_cnt_max_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_9_cfg_tfl_rx_sync_pulse_attr == SERDES_SHIM_TFL_LANE1_REG_9_CFG_TFL_RX_SYNC_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane1_reg_9_cfg_tfl_training_enable_rx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_10_cfg_tfl_rx_cl72_clear_one_marker_seen_attr == SERDES_SHIM_TFL_LANE2_REG_10_CFG_TFL_RX_CL72_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_10_cfg_tfl_rx_cl72_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_LANE2_REG_10_CFG_TFL_RX_CL72_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_10_cfg_tfl_rx_cl72_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_10_cfg_tfl_rx_cl72_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_10_cfg_tfl_rx_cl72_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_LANE2_REG_10_CFG_TFL_RX_CL72_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_10_cfg_tfl_rx_cl72_prbs_ber_en_attr == SERDES_SHIM_TFL_LANE2_REG_10_CFG_TFL_RX_CL72_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_10_cfg_tfl_rx_cl72_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_10_cfg_tfl_rx_cl72_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_10_cfg_tfl_rx_cl72_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_11_cfg_tfl_rx_cl72_ber_count_snap_lock_attr == SERDES_SHIM_TFL_LANE2_REG_11_CFG_TFL_RX_CL72_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_11_cfg_tfl_rx_cl72_ber_counter_clear_attr == SERDES_SHIM_TFL_LANE2_REG_11_CFG_TFL_RX_CL72_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_11_cfg_tfl_rx_cl72_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_LANE2_REG_11_CFG_TFL_RX_CL72_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_11_cfg_tfl_rx_cl72_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_11_cfg_tfl_rx_cl72_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_11_cfg_tfl_rx_cl72_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_11_cfg_tfl_rx_cl72_prbs_seed_force_en_attr == SERDES_SHIM_TFL_LANE2_REG_11_CFG_TFL_RX_CL72_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_11_cfg_tfl_rx_cl72_prbs_seed_force_val_attr == 13'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_12_cfg_tfl_cl136_ctrl_field_11_10_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_12_cfg_tfl_cl136_ctrl_field_13_12_init_cond_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_12_cfg_tfl_cl136_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_12_cfg_tfl_cl136_ctrl_field_1_0_coeff_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_12_cfg_tfl_cl136_ctrl_field_4_2_coeff_select_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_12_cfg_tfl_cl136_ctrl_field_7_5_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_12_cfg_tfl_cl136_ctrl_field_9_8_mod_precode_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_13_cfg_tfl_rx_cl136_clear_one_marker_seen_attr == SERDES_SHIM_TFL_LANE2_REG_13_CFG_TFL_RX_CL136_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_13_cfg_tfl_rx_cl136_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_13_cfg_tfl_rx_cl136_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_13_cfg_tfl_rx_cl136_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_LANE2_REG_13_CFG_TFL_RX_CL136_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_13_cfg_tfl_rx_cl136_pam4_modulation_select_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_13_cfg_tfl_rx_cl136_prbs_ber_en_attr == SERDES_SHIM_TFL_LANE2_REG_13_CFG_TFL_RX_CL136_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_13_cfg_tfl_rx_cl136_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_13_cfg_tfl_rx_cl136_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_13_cfg_tfl_rx_cl136_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_14_cfg_tfl_rx_cl136_ber_count_snap_lock_attr == SERDES_SHIM_TFL_LANE2_REG_14_CFG_TFL_RX_CL136_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_14_cfg_tfl_rx_cl136_ber_counter_clear_attr == SERDES_SHIM_TFL_LANE2_REG_14_CFG_TFL_RX_CL136_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_14_cfg_tfl_rx_cl136_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_LANE2_REG_14_CFG_TFL_RX_CL136_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_14_cfg_tfl_rx_cl136_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_LANE2_REG_14_CFG_TFL_RX_CL136_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_14_cfg_tfl_rx_cl136_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_14_cfg_tfl_rx_cl136_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_14_cfg_tfl_rx_cl136_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_14_cfg_tfl_rx_cl136_prbs_seed_force_en_attr == SERDES_SHIM_TFL_LANE2_REG_14_CFG_TFL_RX_CL136_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_14_cfg_tfl_rx_cl136_prbs_seed_force_val_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_17_cfg_tfl_cl136_stts_field_11_10_mod_precode_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_17_cfg_tfl_cl136_stts_field_14_12_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_17_cfg_tfl_cl136_stts_field_15_rx_ready_attr == SERDES_SHIM_TFL_LANE2_REG_17_CFG_TFL_CL136_STTS_FIELD_15_RX_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_17_cfg_tfl_cl136_stts_field_2_0_coeff_stts_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_17_cfg_tfl_cl136_stts_field_5_3_coeff_sel_echo_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_17_cfg_tfl_cl136_stts_field_6_rsvd_attr == SERDES_SHIM_TFL_LANE2_REG_17_CFG_TFL_CL136_STTS_FIELD_6_RSVD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_17_cfg_tfl_cl136_stts_field_7_parity_attr == SERDES_SHIM_TFL_LANE2_REG_17_CFG_TFL_CL136_STTS_FIELD_7_PARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_17_cfg_tfl_cl136_stts_field_8_init_cond_stts_attr == SERDES_SHIM_TFL_LANE2_REG_17_CFG_TFL_CL136_STTS_FIELD_8_INIT_COND_STTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_17_cfg_tfl_cl136_stts_field_9_rx_frame_lock_attr == SERDES_SHIM_TFL_LANE2_REG_17_CFG_TFL_CL136_STTS_FIELD_9_RX_FRAME_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_1_tfl_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_1_tfl_sec_acc_ctrl_broadcast_mode_attr == SERDES_SHIM_TFL_LANE2_REG_1_TFL_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_1_tfl_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_1_tfl_sec_acc_ctrl_field_mask_write_en_attr == SERDES_SHIM_TFL_LANE2_REG_1_TFL_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_1_tfl_sec_acc_ctrl_load_preset_attr == SERDES_SHIM_TFL_LANE2_REG_1_TFL_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_1_tfl_sec_acc_ctrl_man_clear_on_read_attr == SERDES_SHIM_TFL_LANE2_REG_1_TFL_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_1_tfl_sec_acc_ctrl_man_self_clear_attr == SERDES_SHIM_TFL_LANE2_REG_1_TFL_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_1_tfl_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_1_tfl_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_1_tfl_sec_acc_ctrl_soft_reset_n_attr == SERDES_SHIM_TFL_LANE2_REG_1_TFL_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_1_tfl_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_29_cfg_tfl_prbs13_seed_2_attr == 13'd7571
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_29_cfg_tfl_prbs13_seed_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_2_tfl_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_2_tfl_reg2probe_en_attr == SERDES_SHIM_TFL_LANE2_REG_2_TFL_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_36_cfg_tfl_gb_128_80_en_attr == SERDES_SHIM_TFL_LANE2_REG_36_CFG_TFL_GB_128_80_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_36_cfg_tfl_gb_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_3_cfg_tfl_frame_boundary_early_attr == SERDES_SHIM_TFL_LANE2_REG_3_CFG_TFL_FRAME_BOUNDARY_EARLY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_3_cfg_tfl_ignore_tfl_en_to_avoid_cut_frame_attr == SERDES_SHIM_TFL_LANE2_REG_3_CFG_TFL_IGNORE_TFL_EN_TO_AVOID_CUT_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_3_cfg_tfl_polynomial_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_3_cfg_tfl_pulse_sync_attr == SERDES_SHIM_TFL_LANE2_REG_3_CFG_TFL_PULSE_SYNC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_3_cfg_tfl_scrambler_force_init_at_each_frame_attr == SERDES_SHIM_TFL_LANE2_REG_3_CFG_TFL_SCRAMBLER_FORCE_INIT_AT_EACH_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_3_cfg_tfl_send_data_attr == SERDES_SHIM_TFL_LANE2_REG_3_CFG_TFL_SEND_DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_3_cfg_tfl_sync_ctrl_stts_word_pulse_attr == SERDES_SHIM_TFL_LANE2_REG_3_CFG_TFL_SYNC_CTRL_STTS_WORD_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_3_cfg_tfl_training_enable_tx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_3_cfg_tfl_tx_samp_cnt_max_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_3_cfg_tx_grey_sym_lut_attr == 8'd216
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_3_cfg_tx_swizzle_mode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_4_cfg_tfl_cl72_frame_cycle_to_lock_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_4_cfg_tfl_prbs11_en_attr == SERDES_SHIM_TFL_LANE2_REG_4_CFG_TFL_PRBS11_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_4_cfg_tfl_prbs11_seed_2_attr == 11'd977
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_4_cfg_tfl_prbs11_seed_attr == 11'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_5_cfg_tfl_cl136_frame_cycle_to_lock_attr == 10'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_5_cfg_tfl_cl136_prbs_encoder_select_even_attr == SERDES_SHIM_TFL_LANE2_REG_5_CFG_TFL_CL136_PRBS_ENCODER_SELECT_EVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_5_cfg_tfl_cl136_precoder_out_swz_attr == SERDES_SHIM_TFL_LANE2_REG_5_CFG_TFL_CL136_PRECODER_OUT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_5_cfg_tfl_cl136_precoder_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_5_cfg_tfl_prbs13_en_attr == SERDES_SHIM_TFL_LANE2_REG_5_CFG_TFL_PRBS13_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_6_cfg_tfl_cl72_ctrl_field_11_6_rsvd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_6_cfg_tfl_cl72_ctrl_field_12_initialize_attr == SERDES_SHIM_TFL_LANE2_REG_6_CFG_TFL_CL72_CTRL_FIELD_12_INITIALIZE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_6_cfg_tfl_cl72_ctrl_field_13_preset_attr == SERDES_SHIM_TFL_LANE2_REG_6_CFG_TFL_CL72_CTRL_FIELD_13_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_6_cfg_tfl_cl72_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_6_cfg_tfl_cl72_ctrl_field_1_0_coef_m1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_6_cfg_tfl_cl72_ctrl_field_3_2_coef_0_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_6_cfg_tfl_cl72_ctrl_field_5_4_coef_p1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_7_cfg_tfl_cl72_stts_field_14_6_rsvd_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_7_cfg_tfl_cl72_stts_field_15_rcv_ready_attr == SERDES_SHIM_TFL_LANE2_REG_7_CFG_TFL_CL72_STTS_FIELD_15_RCV_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_7_cfg_tfl_cl72_stts_field_1_0_coef_m1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_7_cfg_tfl_cl72_stts_field_3_2_coef_0_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_7_cfg_tfl_cl72_stts_field_5_4_coef_p1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_9_cfg_rx_grey_sym_lut_attr == 8'd216
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_9_cfg_rx_swizzle_mode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_9_cfg_tfl_rx_samp_cnt_max_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_9_cfg_tfl_rx_sync_pulse_attr == SERDES_SHIM_TFL_LANE2_REG_9_CFG_TFL_RX_SYNC_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane2_reg_9_cfg_tfl_training_enable_rx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_10_cfg_tfl_rx_cl72_clear_one_marker_seen_attr == SERDES_SHIM_TFL_LANE3_REG_10_CFG_TFL_RX_CL72_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_10_cfg_tfl_rx_cl72_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_LANE3_REG_10_CFG_TFL_RX_CL72_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_10_cfg_tfl_rx_cl72_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_10_cfg_tfl_rx_cl72_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_10_cfg_tfl_rx_cl72_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_LANE3_REG_10_CFG_TFL_RX_CL72_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_10_cfg_tfl_rx_cl72_prbs_ber_en_attr == SERDES_SHIM_TFL_LANE3_REG_10_CFG_TFL_RX_CL72_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_10_cfg_tfl_rx_cl72_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_10_cfg_tfl_rx_cl72_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_10_cfg_tfl_rx_cl72_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_11_cfg_tfl_rx_cl72_ber_count_snap_lock_attr == SERDES_SHIM_TFL_LANE3_REG_11_CFG_TFL_RX_CL72_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_11_cfg_tfl_rx_cl72_ber_counter_clear_attr == SERDES_SHIM_TFL_LANE3_REG_11_CFG_TFL_RX_CL72_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_11_cfg_tfl_rx_cl72_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_LANE3_REG_11_CFG_TFL_RX_CL72_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_11_cfg_tfl_rx_cl72_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_11_cfg_tfl_rx_cl72_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_11_cfg_tfl_rx_cl72_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_11_cfg_tfl_rx_cl72_prbs_seed_force_en_attr == SERDES_SHIM_TFL_LANE3_REG_11_CFG_TFL_RX_CL72_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_11_cfg_tfl_rx_cl72_prbs_seed_force_val_attr == 13'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_12_cfg_tfl_cl136_ctrl_field_11_10_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_12_cfg_tfl_cl136_ctrl_field_13_12_init_cond_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_12_cfg_tfl_cl136_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_12_cfg_tfl_cl136_ctrl_field_1_0_coeff_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_12_cfg_tfl_cl136_ctrl_field_4_2_coeff_select_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_12_cfg_tfl_cl136_ctrl_field_7_5_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_12_cfg_tfl_cl136_ctrl_field_9_8_mod_precode_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_13_cfg_tfl_rx_cl136_clear_one_marker_seen_attr == SERDES_SHIM_TFL_LANE3_REG_13_CFG_TFL_RX_CL136_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_13_cfg_tfl_rx_cl136_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_13_cfg_tfl_rx_cl136_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_13_cfg_tfl_rx_cl136_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_LANE3_REG_13_CFG_TFL_RX_CL136_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_13_cfg_tfl_rx_cl136_pam4_modulation_select_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_13_cfg_tfl_rx_cl136_prbs_ber_en_attr == SERDES_SHIM_TFL_LANE3_REG_13_CFG_TFL_RX_CL136_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_13_cfg_tfl_rx_cl136_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_13_cfg_tfl_rx_cl136_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_13_cfg_tfl_rx_cl136_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_14_cfg_tfl_rx_cl136_ber_count_snap_lock_attr == SERDES_SHIM_TFL_LANE3_REG_14_CFG_TFL_RX_CL136_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_14_cfg_tfl_rx_cl136_ber_counter_clear_attr == SERDES_SHIM_TFL_LANE3_REG_14_CFG_TFL_RX_CL136_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_14_cfg_tfl_rx_cl136_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_LANE3_REG_14_CFG_TFL_RX_CL136_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_14_cfg_tfl_rx_cl136_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_LANE3_REG_14_CFG_TFL_RX_CL136_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_14_cfg_tfl_rx_cl136_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_14_cfg_tfl_rx_cl136_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_14_cfg_tfl_rx_cl136_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_14_cfg_tfl_rx_cl136_prbs_seed_force_en_attr == SERDES_SHIM_TFL_LANE3_REG_14_CFG_TFL_RX_CL136_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_14_cfg_tfl_rx_cl136_prbs_seed_force_val_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_17_cfg_tfl_cl136_stts_field_11_10_mod_precode_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_17_cfg_tfl_cl136_stts_field_14_12_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_17_cfg_tfl_cl136_stts_field_15_rx_ready_attr == SERDES_SHIM_TFL_LANE3_REG_17_CFG_TFL_CL136_STTS_FIELD_15_RX_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_17_cfg_tfl_cl136_stts_field_2_0_coeff_stts_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_17_cfg_tfl_cl136_stts_field_5_3_coeff_sel_echo_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_17_cfg_tfl_cl136_stts_field_6_rsvd_attr == SERDES_SHIM_TFL_LANE3_REG_17_CFG_TFL_CL136_STTS_FIELD_6_RSVD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_17_cfg_tfl_cl136_stts_field_7_parity_attr == SERDES_SHIM_TFL_LANE3_REG_17_CFG_TFL_CL136_STTS_FIELD_7_PARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_17_cfg_tfl_cl136_stts_field_8_init_cond_stts_attr == SERDES_SHIM_TFL_LANE3_REG_17_CFG_TFL_CL136_STTS_FIELD_8_INIT_COND_STTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_17_cfg_tfl_cl136_stts_field_9_rx_frame_lock_attr == SERDES_SHIM_TFL_LANE3_REG_17_CFG_TFL_CL136_STTS_FIELD_9_RX_FRAME_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_1_tfl_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_1_tfl_sec_acc_ctrl_broadcast_mode_attr == SERDES_SHIM_TFL_LANE3_REG_1_TFL_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_1_tfl_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_1_tfl_sec_acc_ctrl_field_mask_write_en_attr == SERDES_SHIM_TFL_LANE3_REG_1_TFL_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_1_tfl_sec_acc_ctrl_load_preset_attr == SERDES_SHIM_TFL_LANE3_REG_1_TFL_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_1_tfl_sec_acc_ctrl_man_clear_on_read_attr == SERDES_SHIM_TFL_LANE3_REG_1_TFL_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_1_tfl_sec_acc_ctrl_man_self_clear_attr == SERDES_SHIM_TFL_LANE3_REG_1_TFL_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_1_tfl_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_1_tfl_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_1_tfl_sec_acc_ctrl_soft_reset_n_attr == SERDES_SHIM_TFL_LANE3_REG_1_TFL_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_1_tfl_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_29_cfg_tfl_prbs13_seed_2_attr == 13'd7571
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_29_cfg_tfl_prbs13_seed_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_2_tfl_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_2_tfl_reg2probe_en_attr == SERDES_SHIM_TFL_LANE3_REG_2_TFL_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_36_cfg_tfl_gb_128_80_en_attr == SERDES_SHIM_TFL_LANE3_REG_36_CFG_TFL_GB_128_80_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_36_cfg_tfl_gb_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_3_cfg_tfl_frame_boundary_early_attr == SERDES_SHIM_TFL_LANE3_REG_3_CFG_TFL_FRAME_BOUNDARY_EARLY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_3_cfg_tfl_ignore_tfl_en_to_avoid_cut_frame_attr == SERDES_SHIM_TFL_LANE3_REG_3_CFG_TFL_IGNORE_TFL_EN_TO_AVOID_CUT_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_3_cfg_tfl_polynomial_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_3_cfg_tfl_pulse_sync_attr == SERDES_SHIM_TFL_LANE3_REG_3_CFG_TFL_PULSE_SYNC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_3_cfg_tfl_scrambler_force_init_at_each_frame_attr == SERDES_SHIM_TFL_LANE3_REG_3_CFG_TFL_SCRAMBLER_FORCE_INIT_AT_EACH_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_3_cfg_tfl_send_data_attr == SERDES_SHIM_TFL_LANE3_REG_3_CFG_TFL_SEND_DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_3_cfg_tfl_sync_ctrl_stts_word_pulse_attr == SERDES_SHIM_TFL_LANE3_REG_3_CFG_TFL_SYNC_CTRL_STTS_WORD_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_3_cfg_tfl_training_enable_tx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_3_cfg_tfl_tx_samp_cnt_max_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_3_cfg_tx_grey_sym_lut_attr == 8'd216
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_3_cfg_tx_swizzle_mode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_4_cfg_tfl_cl72_frame_cycle_to_lock_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_4_cfg_tfl_prbs11_en_attr == SERDES_SHIM_TFL_LANE3_REG_4_CFG_TFL_PRBS11_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_4_cfg_tfl_prbs11_seed_2_attr == 11'd977
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_4_cfg_tfl_prbs11_seed_attr == 11'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_5_cfg_tfl_cl136_frame_cycle_to_lock_attr == 10'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_5_cfg_tfl_cl136_prbs_encoder_select_even_attr == SERDES_SHIM_TFL_LANE3_REG_5_CFG_TFL_CL136_PRBS_ENCODER_SELECT_EVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_5_cfg_tfl_cl136_precoder_out_swz_attr == SERDES_SHIM_TFL_LANE3_REG_5_CFG_TFL_CL136_PRECODER_OUT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_5_cfg_tfl_cl136_precoder_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_5_cfg_tfl_prbs13_en_attr == SERDES_SHIM_TFL_LANE3_REG_5_CFG_TFL_PRBS13_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_6_cfg_tfl_cl72_ctrl_field_11_6_rsvd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_6_cfg_tfl_cl72_ctrl_field_12_initialize_attr == SERDES_SHIM_TFL_LANE3_REG_6_CFG_TFL_CL72_CTRL_FIELD_12_INITIALIZE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_6_cfg_tfl_cl72_ctrl_field_13_preset_attr == SERDES_SHIM_TFL_LANE3_REG_6_CFG_TFL_CL72_CTRL_FIELD_13_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_6_cfg_tfl_cl72_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_6_cfg_tfl_cl72_ctrl_field_1_0_coef_m1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_6_cfg_tfl_cl72_ctrl_field_3_2_coef_0_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_6_cfg_tfl_cl72_ctrl_field_5_4_coef_p1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_7_cfg_tfl_cl72_stts_field_14_6_rsvd_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_7_cfg_tfl_cl72_stts_field_15_rcv_ready_attr == SERDES_SHIM_TFL_LANE3_REG_7_CFG_TFL_CL72_STTS_FIELD_15_RCV_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_7_cfg_tfl_cl72_stts_field_1_0_coef_m1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_7_cfg_tfl_cl72_stts_field_3_2_coef_0_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_7_cfg_tfl_cl72_stts_field_5_4_coef_p1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_9_cfg_rx_grey_sym_lut_attr == 8'd216
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_9_cfg_rx_swizzle_mode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_9_cfg_tfl_rx_samp_cnt_max_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_9_cfg_tfl_rx_sync_pulse_attr == SERDES_SHIM_TFL_LANE3_REG_9_CFG_TFL_RX_SYNC_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_tfl_lane3_reg_9_cfg_tfl_training_enable_rx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_10_wrap_car_reg2probe_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_10_wrap_car_reg2probe_en_attr == SERDES_SHIM_WRAP_CAR_REG_10_WRAP_CAR_REG2PROBE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_11_obrk_barak_ready_attr == SERDES_SHIM_WRAP_CAR_REG_11_OBRK_BARAK_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_12_cfg_run_stall_attr == SERDES_SHIM_WRAP_CAR_REG_12_CFG_RUN_STALL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_12_cfg_run_stall_force_en_attr == SERDES_SHIM_WRAP_CAR_REG_12_CFG_RUN_STALL_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_12_cfg_run_stall_force_val_attr == SERDES_SHIM_WRAP_CAR_REG_12_CFG_RUN_STALL_FORCE_VAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_1_apb_clk_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_1_car_tx_clk_src_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_1_cpu_clk_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_1_fast_clk_sel_attr == SERDES_SHIM_WRAP_CAR_REG_1_FAST_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_1_fifo_w_clk_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_1_ok_to_switch_fast_clk_attr == SERDES_SHIM_WRAP_CAR_REG_1_OK_TO_SWITCH_FAST_CLK_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_1_rx_fifo_clk_divn_value_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_2_apb_pclk_en_lane0_attr == SERDES_SHIM_WRAP_CAR_REG_2_APB_PCLK_EN_LANE0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_2_apb_pclk_en_lane1_attr == SERDES_SHIM_WRAP_CAR_REG_2_APB_PCLK_EN_LANE1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_2_apb_pclk_en_lane2_attr == SERDES_SHIM_WRAP_CAR_REG_2_APB_PCLK_EN_LANE2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_2_apb_pclk_en_lane3_attr == SERDES_SHIM_WRAP_CAR_REG_2_APB_PCLK_EN_LANE3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_2_ck_apb_pclken_attr == SERDES_SHIM_WRAP_CAR_REG_2_CK_APB_PCLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_2_fifo_w_clken_attr == SERDES_SHIM_WRAP_CAR_REG_2_FIFO_W_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_2_hw_assist_avg_eng_clken_attr == SERDES_SHIM_WRAP_CAR_REG_2_HW_ASSIST_AVG_ENG_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_2_probe_clk_en_attr == SERDES_SHIM_WRAP_CAR_REG_2_PROBE_CLK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_2_rx_8k_div2_clken_attr == SERDES_SHIM_WRAP_CAR_REG_2_RX_8K_DIV2_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_2_rx_fifo_clk_divn_en_attr == SERDES_SHIM_WRAP_CAR_REG_2_RX_FIFO_CLK_DIVN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_2_rx_pcs_clk_en_lane0_attr == SERDES_SHIM_WRAP_CAR_REG_2_RX_PCS_CLK_EN_LANE0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_2_rx_pcs_clk_en_lane1_attr == SERDES_SHIM_WRAP_CAR_REG_2_RX_PCS_CLK_EN_LANE1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_2_rx_pcs_clk_en_lane2_attr == SERDES_SHIM_WRAP_CAR_REG_2_RX_PCS_CLK_EN_LANE2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_2_rx_pcs_clk_en_lane3_attr == SERDES_SHIM_WRAP_CAR_REG_2_RX_PCS_CLK_EN_LANE3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_2_rx_pcs_reset_lane0_attr == SERDES_SHIM_WRAP_CAR_REG_2_RX_PCS_RESET_LANE0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_2_rx_pcs_reset_lane1_attr == SERDES_SHIM_WRAP_CAR_REG_2_RX_PCS_RESET_LANE1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_2_rx_pcs_reset_lane2_attr == SERDES_SHIM_WRAP_CAR_REG_2_RX_PCS_RESET_LANE2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_2_rx_pcs_reset_lane3_attr == SERDES_SHIM_WRAP_CAR_REG_2_RX_PCS_RESET_LANE3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_2_tx_pcs_clk_en_lane0_attr == SERDES_SHIM_WRAP_CAR_REG_2_TX_PCS_CLK_EN_LANE0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_2_tx_pcs_clk_en_lane1_attr == SERDES_SHIM_WRAP_CAR_REG_2_TX_PCS_CLK_EN_LANE1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_2_tx_pcs_clk_en_lane2_attr == SERDES_SHIM_WRAP_CAR_REG_2_TX_PCS_CLK_EN_LANE2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_2_tx_pcs_clk_en_lane3_attr == SERDES_SHIM_WRAP_CAR_REG_2_TX_PCS_CLK_EN_LANE3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_2_tx_pcs_reset_lane0_attr == SERDES_SHIM_WRAP_CAR_REG_2_TX_PCS_RESET_LANE0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_2_tx_pcs_reset_lane1_attr == SERDES_SHIM_WRAP_CAR_REG_2_TX_PCS_RESET_LANE1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_2_tx_pcs_reset_lane2_attr == SERDES_SHIM_WRAP_CAR_REG_2_TX_PCS_RESET_LANE2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_2_tx_pcs_reset_lane3_attr == SERDES_SHIM_WRAP_CAR_REG_2_TX_PCS_RESET_LANE3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_3_apb_presetn_swrst_attr == SERDES_SHIM_WRAP_CAR_REG_3_APB_PRESETN_SWRST_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_3_hw_assist_avg_eng_swrst_attr == SERDES_SHIM_WRAP_CAR_REG_3_HW_ASSIST_AVG_ENG_SWRST_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_3_rx_fifo_r_swrst_attr == SERDES_SHIM_WRAP_CAR_REG_3_RX_FIFO_R_SWRST_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_3_rx_fifo_w_swrst_attr == SERDES_SHIM_WRAP_CAR_REG_3_RX_FIFO_W_SWRST_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_4_cfg_car_div_te_attr == SERDES_SHIM_WRAP_CAR_REG_4_CFG_CAR_DIV_TE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_4_ecsr_period_clk_stabilizing_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_4_ecsr_restart_detection_attr == SERDES_SHIM_WRAP_CAR_REG_4_ECSR_RESTART_DETECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_4_non_posted_write_en_attr == SERDES_SHIM_WRAP_CAR_REG_4_NON_POSTED_WRITE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_7_wrap_car_sec_acc_ctrl_access_ind_extend_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_7_wrap_car_sec_acc_ctrl_broadcast_mode_attr == SERDES_SHIM_WRAP_CAR_REG_7_WRAP_CAR_SEC_ACC_CTRL_BROADCAST_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_7_wrap_car_sec_acc_ctrl_clear_on_read_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_7_wrap_car_sec_acc_ctrl_field_mask_write_en_attr == SERDES_SHIM_WRAP_CAR_REG_7_WRAP_CAR_SEC_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_7_wrap_car_sec_acc_ctrl_load_preset_attr == SERDES_SHIM_WRAP_CAR_REG_7_WRAP_CAR_SEC_ACC_CTRL_LOAD_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_7_wrap_car_sec_acc_ctrl_man_clear_on_read_attr == SERDES_SHIM_WRAP_CAR_REG_7_WRAP_CAR_SEC_ACC_CTRL_MAN_CLEAR_ON_READ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_7_wrap_car_sec_acc_ctrl_man_self_clear_attr == SERDES_SHIM_WRAP_CAR_REG_7_WRAP_CAR_SEC_ACC_CTRL_MAN_SELF_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_7_wrap_car_sec_acc_ctrl_read_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_7_wrap_car_sec_acc_ctrl_self_clear_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_7_wrap_car_sec_acc_ctrl_soft_reset_n_attr == SERDES_SHIM_WRAP_CAR_REG_7_WRAP_CAR_SEC_ACC_CTRL_SOFT_RESET_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_7_wrap_car_sec_acc_ctrl_write_delay_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_8_rx_tfl_clk_en_lane0_attr == SERDES_SHIM_WRAP_CAR_REG_8_RX_TFL_CLK_EN_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_8_rx_tfl_clk_en_lane1_attr == SERDES_SHIM_WRAP_CAR_REG_8_RX_TFL_CLK_EN_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_8_rx_tfl_clk_en_lane2_attr == SERDES_SHIM_WRAP_CAR_REG_8_RX_TFL_CLK_EN_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_8_rx_tfl_clk_en_lane3_attr == SERDES_SHIM_WRAP_CAR_REG_8_RX_TFL_CLK_EN_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_8_rx_tfl_clk_sel_lane0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_8_rx_tfl_clk_sel_lane1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_8_rx_tfl_clk_sel_lane2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_8_rx_tfl_clk_sel_lane3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_8_rx_tfl_reset_lane0_attr == SERDES_SHIM_WRAP_CAR_REG_8_RX_TFL_RESET_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_8_rx_tfl_reset_lane1_attr == SERDES_SHIM_WRAP_CAR_REG_8_RX_TFL_RESET_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_8_rx_tfl_reset_lane2_attr == SERDES_SHIM_WRAP_CAR_REG_8_RX_TFL_RESET_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_8_rx_tfl_reset_lane3_attr == SERDES_SHIM_WRAP_CAR_REG_8_RX_TFL_RESET_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_8_tx_tfl_clk_en_lane0_attr == SERDES_SHIM_WRAP_CAR_REG_8_TX_TFL_CLK_EN_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_8_tx_tfl_clk_en_lane1_attr == SERDES_SHIM_WRAP_CAR_REG_8_TX_TFL_CLK_EN_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_8_tx_tfl_clk_en_lane2_attr == SERDES_SHIM_WRAP_CAR_REG_8_TX_TFL_CLK_EN_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_8_tx_tfl_clk_en_lane3_attr == SERDES_SHIM_WRAP_CAR_REG_8_TX_TFL_CLK_EN_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_8_tx_tfl_clk_sel_lane0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_8_tx_tfl_clk_sel_lane1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_8_tx_tfl_clk_sel_lane2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_8_tx_tfl_clk_sel_lane3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_8_tx_tfl_reset_lane0_attr == SERDES_SHIM_WRAP_CAR_REG_8_TX_TFL_RESET_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_8_tx_tfl_reset_lane1_attr == SERDES_SHIM_WRAP_CAR_REG_8_TX_TFL_RESET_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_8_tx_tfl_reset_lane2_attr == SERDES_SHIM_WRAP_CAR_REG_8_TX_TFL_RESET_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_8_tx_tfl_reset_lane3_attr == SERDES_SHIM_WRAP_CAR_REG_8_TX_TFL_RESET_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_9_rx_an_clk_en_lane0_attr == SERDES_SHIM_WRAP_CAR_REG_9_RX_AN_CLK_EN_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_9_rx_an_clk_en_lane1_attr == SERDES_SHIM_WRAP_CAR_REG_9_RX_AN_CLK_EN_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_9_rx_an_clk_en_lane2_attr == SERDES_SHIM_WRAP_CAR_REG_9_RX_AN_CLK_EN_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_9_rx_an_clk_en_lane3_attr == SERDES_SHIM_WRAP_CAR_REG_9_RX_AN_CLK_EN_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_9_rx_an_reset_lane0_attr == SERDES_SHIM_WRAP_CAR_REG_9_RX_AN_RESET_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_9_rx_an_reset_lane1_attr == SERDES_SHIM_WRAP_CAR_REG_9_RX_AN_RESET_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_9_rx_an_reset_lane2_attr == SERDES_SHIM_WRAP_CAR_REG_9_RX_AN_RESET_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_9_rx_an_reset_lane3_attr == SERDES_SHIM_WRAP_CAR_REG_9_RX_AN_RESET_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_9_tx_an_clk_en_lane0_attr == SERDES_SHIM_WRAP_CAR_REG_9_TX_AN_CLK_EN_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_9_tx_an_clk_en_lane1_attr == SERDES_SHIM_WRAP_CAR_REG_9_TX_AN_CLK_EN_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_9_tx_an_clk_en_lane2_attr == SERDES_SHIM_WRAP_CAR_REG_9_TX_AN_CLK_EN_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_9_tx_an_clk_en_lane3_attr == SERDES_SHIM_WRAP_CAR_REG_9_TX_AN_CLK_EN_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_9_tx_an_reset_lane0_attr == SERDES_SHIM_WRAP_CAR_REG_9_TX_AN_RESET_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_9_tx_an_reset_lane1_attr == SERDES_SHIM_WRAP_CAR_REG_9_TX_AN_RESET_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_9_tx_an_reset_lane2_attr == SERDES_SHIM_WRAP_CAR_REG_9_TX_AN_RESET_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_barak_quad.u_ip758brktop.serdes_shim_wrap_car_reg_9_tx_an_reset_lane3_attr == SERDES_SHIM_WRAP_CAR_REG_9_TX_AN_RESET_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.avmm_clk_attr_hz == 36'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.barak_pri_ctrl_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.barak_sec_ctrl_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.cfgavmm_timeout_max_attr == 32'd6249975
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.cnoc_clk_attr_hz == 36'd250000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_bit0_ctrl_0_be0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_bit0_ctrl_0_be1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_bit0_ctrl_0_be2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_bit0_ctrl_0_be3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_bit0_ctrl_1_be0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_bit0_ctrl_1_be1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_bit0_ctrl_1_be2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_bit0_ctrl_1_be3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_bit0_ctrl_2_be0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_bit0_ctrl_2_be1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_bit0_ctrl_2_be2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_bit0_ctrl_2_be3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_bit0_ctrl_3_be0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_bit0_ctrl_3_be1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_bit0_ctrl_3_be2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_bit0_ctrl_3_be3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_bit1_ctrl_0_be0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_bit1_ctrl_0_be1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_bit1_ctrl_0_be2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_bit1_ctrl_0_be3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_bit1_ctrl_1_be0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_bit1_ctrl_1_be1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_bit1_ctrl_1_be2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_bit1_ctrl_1_be3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_bit1_ctrl_2_be0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_bit1_ctrl_2_be1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_bit1_ctrl_2_be2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_bit1_ctrl_2_be3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_bit1_ctrl_3_be0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_bit1_ctrl_3_be1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_bit1_ctrl_3_be2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_bit1_ctrl_3_be3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_data_mux_ctrl_0_ip_data_be0_attr == DFD_0_BE0_AIB_DAISYCHAIN_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_data_mux_ctrl_0_ip_data_be1_attr == DFD_0_BE1_AIB_DAISYCHAIN_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_data_mux_ctrl_0_ip_data_be2_attr == DFD_0_BE2_AIB_DAISYCHAIN_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_data_mux_ctrl_0_ip_data_be3_attr == DFD_0_BE3_AIB_DAISYCHAIN_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_data_mux_ctrl_1_ip_data_be0_attr == DFD_1_BE0_AIB_DAISYCHAIN_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_data_mux_ctrl_1_ip_data_be1_attr == DFD_1_BE1_AIB_DAISYCHAIN_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_data_mux_ctrl_1_ip_data_be2_attr == DFD_1_BE2_AIB_DAISYCHAIN_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_data_mux_ctrl_1_ip_data_be3_attr == DFD_1_BE3_AIB_DAISYCHAIN_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_data_mux_ctrl_2_ip_data_be0_attr == DFD_2_BE0_AIB_DAISYCHAIN_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_data_mux_ctrl_2_ip_data_be1_attr == DFD_2_BE1_AIB_DAISYCHAIN_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_data_mux_ctrl_2_ip_data_be2_attr == DFD_2_BE2_AIB_DAISYCHAIN_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_data_mux_ctrl_2_ip_data_be3_attr == DFD_2_BE3_AIB_DAISYCHAIN_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_data_mux_ctrl_3_ip_data_be0_attr == DFD_3_BE0_AIB_DAISYCHAIN_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_data_mux_ctrl_3_ip_data_be1_attr == DFD_3_BE1_AIB_DAISYCHAIN_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_data_mux_ctrl_3_ip_data_be2_attr == DFD_3_BE2_AIB_DAISYCHAIN_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_data_mux_ctrl_3_ip_data_be3_attr == DFD_3_BE3_AIB_DAISYCHAIN_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_mask0_ctrl_0_mv_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_mask0_ctrl_1_mv_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_mask0_ctrl_2_mv_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_mask0_ctrl_3_mv_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_mask1_ctrl_0_mv_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_mask1_ctrl_1_mv_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_mask1_ctrl_2_mv_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_mask1_ctrl_3_mv_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_memctrl_0_mem_addr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_memctrl_1_mem_addr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_memctrl_2_mem_addr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_memctrl_3_mem_addr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_0_capture_disabled_attr == DFD_PRIMARY_CTRL_0_CAPTURE_DISABLED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_0_extrig_sync_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_0_ipdata_sync_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_0_no_cprmemdata_attr == DFD_PRIMARY_CTRL_0_NO_CPRMEMDATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_0_no_trigger_attr == DFD_PRIMARY_CTRL_0_NO_TRIGGER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_0_odfd_flushmem_start_attr == DFD_PRIMARY_CTRL_0_ODFD_FLUSHMEM_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_0_perfmon_cnt_set_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_0_pretrigger_mode_attr == DFD_PRIMARY_CTRL_0_PRETRIGGER_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_0_primwr2_attr == DFD_PRIMARY_CTRL_0_PRIMWR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_0_read_trace_done_attr == DFD_PRIMARY_CTRL_0_READ_TRACE_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_0_rstc_attr == DFD_PRIMARY_CTRL_0_RSTC_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_0_start_capture_attr == DFD_PRIMARY_CTRL_0_START_CAPTURE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_0_swread_attr == DFD_PRIMARY_CTRL_0_SWREAD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_1_capture_disabled_attr == DFD_PRIMARY_CTRL_1_CAPTURE_DISABLED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_1_extrig_sync_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_1_ipdata_sync_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_1_no_cprmemdata_attr == DFD_PRIMARY_CTRL_1_NO_CPRMEMDATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_1_no_trigger_attr == DFD_PRIMARY_CTRL_1_NO_TRIGGER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_1_odfd_flushmem_start_attr == DFD_PRIMARY_CTRL_1_ODFD_FLUSHMEM_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_1_perfmon_cnt_set_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_1_pretrigger_mode_attr == DFD_PRIMARY_CTRL_1_PRETRIGGER_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_1_primwr2_attr == DFD_PRIMARY_CTRL_1_PRIMWR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_1_read_trace_done_attr == DFD_PRIMARY_CTRL_1_READ_TRACE_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_1_rstc_attr == DFD_PRIMARY_CTRL_1_RSTC_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_1_start_capture_attr == DFD_PRIMARY_CTRL_1_START_CAPTURE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_1_swread_attr == DFD_PRIMARY_CTRL_1_SWREAD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_2_capture_disabled_attr == DFD_PRIMARY_CTRL_2_CAPTURE_DISABLED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_2_extrig_sync_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_2_ipdata_sync_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_2_no_cprmemdata_attr == DFD_PRIMARY_CTRL_2_NO_CPRMEMDATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_2_no_trigger_attr == DFD_PRIMARY_CTRL_2_NO_TRIGGER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_2_odfd_flushmem_start_attr == DFD_PRIMARY_CTRL_2_ODFD_FLUSHMEM_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_2_perfmon_cnt_set_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_2_pretrigger_mode_attr == DFD_PRIMARY_CTRL_2_PRETRIGGER_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_2_primwr2_attr == DFD_PRIMARY_CTRL_2_PRIMWR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_2_read_trace_done_attr == DFD_PRIMARY_CTRL_2_READ_TRACE_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_2_rstc_attr == DFD_PRIMARY_CTRL_2_RSTC_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_2_start_capture_attr == DFD_PRIMARY_CTRL_2_START_CAPTURE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_2_swread_attr == DFD_PRIMARY_CTRL_2_SWREAD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_3_capture_disabled_attr == DFD_PRIMARY_CTRL_3_CAPTURE_DISABLED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_3_extrig_sync_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_3_ipdata_sync_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_3_no_cprmemdata_attr == DFD_PRIMARY_CTRL_3_NO_CPRMEMDATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_3_no_trigger_attr == DFD_PRIMARY_CTRL_3_NO_TRIGGER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_3_odfd_flushmem_start_attr == DFD_PRIMARY_CTRL_3_ODFD_FLUSHMEM_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_3_perfmon_cnt_set_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_3_pretrigger_mode_attr == DFD_PRIMARY_CTRL_3_PRETRIGGER_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_3_primwr2_attr == DFD_PRIMARY_CTRL_3_PRIMWR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_3_read_trace_done_attr == DFD_PRIMARY_CTRL_3_READ_TRACE_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_3_rstc_attr == DFD_PRIMARY_CTRL_3_RSTC_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_3_start_capture_attr == DFD_PRIMARY_CTRL_3_START_CAPTURE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_primary_ctrl_3_swread_attr == DFD_PRIMARY_CTRL_3_SWREAD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_secondary_ctrl_0_pre_trigger_window_attr == 15'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_secondary_ctrl_0_sm_trig_ena_attr == DFD_SECONDARY_CTRL_0_SM_TRIG_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_secondary_ctrl_1_pre_trigger_window_attr == 15'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_secondary_ctrl_1_sm_trig_ena_attr == DFD_SECONDARY_CTRL_1_SM_TRIG_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_secondary_ctrl_2_pre_trigger_window_attr == 15'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_secondary_ctrl_2_sm_trig_ena_attr == DFD_SECONDARY_CTRL_2_SM_TRIG_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_secondary_ctrl_3_pre_trigger_window_attr == 15'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_secondary_ctrl_3_sm_trig_ena_attr == DFD_SECONDARY_CTRL_3_SM_TRIG_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_sm_mask_ctrl_0_mv_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_sm_mask_ctrl_1_mv_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_sm_mask_ctrl_2_mv_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_sm_mask_ctrl_3_mv_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_0_andor_triggers_attr == DFD_TRIG_CTRL_0_ANDOR_TRIGGERS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_0_delay_capture_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_0_depth_capture_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_0_extrig0_edge_attr == DFD_TRIG_CTRL_0_EXTRIG0_EDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_0_extrig0_ena_attr == DFD_TRIG_CTRL_0_EXTRIG0_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_0_extrig1_edge_attr == DFD_TRIG_CTRL_0_EXTRIG1_EDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_0_extrig1_ena_attr == DFD_TRIG_CTRL_0_EXTRIG1_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_0_inv_triggers_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_0_mask0_edge_attr == DFD_TRIG_CTRL_0_MASK0_EDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_0_mask0_ena_attr == DFD_TRIG_CTRL_0_MASK0_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_0_mask0_trigger_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_0_mask1_edge_attr == DFD_TRIG_CTRL_0_MASK1_EDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_0_mask1_ena_attr == DFD_TRIG_CTRL_0_MASK1_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_0_mask1_trigger_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_0_odfd_flushmem_auto_attr == DFD_TRIG_CTRL_0_ODFD_FLUSHMEM_AUTO_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_0_odfd_flushmem_extrig_attr == DFD_TRIG_CTRL_0_ODFD_FLUSHMEM_EXTRIG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_0_use_windows_capture_attr == DFD_TRIG_CTRL_0_USE_WINDOWS_CAPTURE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_1_andor_triggers_attr == DFD_TRIG_CTRL_1_ANDOR_TRIGGERS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_1_delay_capture_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_1_depth_capture_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_1_extrig0_edge_attr == DFD_TRIG_CTRL_1_EXTRIG0_EDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_1_extrig0_ena_attr == DFD_TRIG_CTRL_1_EXTRIG0_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_1_extrig1_edge_attr == DFD_TRIG_CTRL_1_EXTRIG1_EDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_1_extrig1_ena_attr == DFD_TRIG_CTRL_1_EXTRIG1_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_1_inv_triggers_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_1_mask0_edge_attr == DFD_TRIG_CTRL_1_MASK0_EDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_1_mask0_ena_attr == DFD_TRIG_CTRL_1_MASK0_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_1_mask0_trigger_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_1_mask1_edge_attr == DFD_TRIG_CTRL_1_MASK1_EDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_1_mask1_ena_attr == DFD_TRIG_CTRL_1_MASK1_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_1_mask1_trigger_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_1_odfd_flushmem_auto_attr == DFD_TRIG_CTRL_1_ODFD_FLUSHMEM_AUTO_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_1_odfd_flushmem_extrig_attr == DFD_TRIG_CTRL_1_ODFD_FLUSHMEM_EXTRIG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_1_use_windows_capture_attr == DFD_TRIG_CTRL_1_USE_WINDOWS_CAPTURE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_2_andor_triggers_attr == DFD_TRIG_CTRL_2_ANDOR_TRIGGERS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_2_delay_capture_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_2_depth_capture_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_2_extrig0_edge_attr == DFD_TRIG_CTRL_2_EXTRIG0_EDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_2_extrig0_ena_attr == DFD_TRIG_CTRL_2_EXTRIG0_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_2_extrig1_edge_attr == DFD_TRIG_CTRL_2_EXTRIG1_EDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_2_extrig1_ena_attr == DFD_TRIG_CTRL_2_EXTRIG1_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_2_inv_triggers_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_2_mask0_edge_attr == DFD_TRIG_CTRL_2_MASK0_EDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_2_mask0_ena_attr == DFD_TRIG_CTRL_2_MASK0_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_2_mask0_trigger_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_2_mask1_edge_attr == DFD_TRIG_CTRL_2_MASK1_EDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_2_mask1_ena_attr == DFD_TRIG_CTRL_2_MASK1_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_2_mask1_trigger_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_2_odfd_flushmem_auto_attr == DFD_TRIG_CTRL_2_ODFD_FLUSHMEM_AUTO_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_2_odfd_flushmem_extrig_attr == DFD_TRIG_CTRL_2_ODFD_FLUSHMEM_EXTRIG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_2_use_windows_capture_attr == DFD_TRIG_CTRL_2_USE_WINDOWS_CAPTURE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_3_andor_triggers_attr == DFD_TRIG_CTRL_3_ANDOR_TRIGGERS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_3_delay_capture_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_3_depth_capture_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_3_extrig0_edge_attr == DFD_TRIG_CTRL_3_EXTRIG0_EDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_3_extrig0_ena_attr == DFD_TRIG_CTRL_3_EXTRIG0_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_3_extrig1_edge_attr == DFD_TRIG_CTRL_3_EXTRIG1_EDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_3_extrig1_ena_attr == DFD_TRIG_CTRL_3_EXTRIG1_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_3_inv_triggers_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_3_mask0_edge_attr == DFD_TRIG_CTRL_3_MASK0_EDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_3_mask0_ena_attr == DFD_TRIG_CTRL_3_MASK0_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_3_mask0_trigger_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_3_mask1_edge_attr == DFD_TRIG_CTRL_3_MASK1_EDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_3_mask1_ena_attr == DFD_TRIG_CTRL_3_MASK1_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_3_mask1_trigger_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_3_odfd_flushmem_auto_attr == DFD_TRIG_CTRL_3_ODFD_FLUSHMEM_AUTO_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_3_odfd_flushmem_extrig_attr == DFD_TRIG_CTRL_3_ODFD_FLUSHMEM_EXTRIG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_ctrl_3_use_windows_capture_attr == DFD_TRIG_CTRL_3_USE_WINDOWS_CAPTURE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_mux_ctrl_0_clk_sel_attr == DFD_0_CLK_AIB_DAISYCHAIN_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_mux_ctrl_0_extrig_sel0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_mux_ctrl_0_extrig_sel1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_mux_ctrl_0_odfd_mux_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_mux_ctrl_0_spare_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_mux_ctrl_1_clk_sel_attr == DFD_1_CLK_AIB_DAISYCHAIN_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_mux_ctrl_1_extrig_sel0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_mux_ctrl_1_extrig_sel1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_mux_ctrl_1_odfd_mux_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_mux_ctrl_1_spare_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_mux_ctrl_2_clk_sel_attr == DFD_2_CLK_AIB_DAISYCHAIN_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_mux_ctrl_2_extrig_sel0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_mux_ctrl_2_extrig_sel1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_mux_ctrl_2_odfd_mux_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_mux_ctrl_2_spare_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_mux_ctrl_3_clk_sel_attr == DFD_3_CLK_AIB_DAISYCHAIN_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_mux_ctrl_3_extrig_sel0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_mux_ctrl_3_extrig_sel1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_mux_ctrl_3_odfd_mux_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dfd_trig_mux_ctrl_3_spare_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_ctrl_ext_ctrl_attr == DTS_CTRL_EXT_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_ctrl_f_aclk_div_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_ctrl_f_alert_thresh_attr == 8'd155
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_ctrl_f_biasenable_attr == DTS_CTRL_F_BIASENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_ctrl_f_biasratiosel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_ctrl_f_burst_attr == DTS_CTRL_F_BURST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_ctrl_f_currratiosel_attr == DTS_CTRL_F_CURRRATIOSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_ctrl_f_dclk_div_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_ctrl_f_en_attr == DTS_CTRL_F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_ctrl_f_remotesensor_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_ctrl_f_remotesensor_valid_attr == DTS_CTRL_F_REMOTESENSOR_VALID_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_ctrl_f_rst_n_attr == DTS_CTRL_F_RST_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_ctrl_f_standalone_en_attr == DTS_CTRL_F_STANDALONE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_ctrl_f_trip_thresh_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_ld_calib_ext_ctrl_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_ld_calib_f_caloffset_attr == 13'd1906
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_ld_calib_f_calslope_attr == 13'd2244
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_rd_calib_1_ext_ctrl_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_rd_calib_1_f_caloffset_attr == 13'd1906
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_rd_calib_1_f_calslope_attr == 13'd2244
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_rd_calib_2_ext_ctrl_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_rd_calib_2_f_caloffset_attr == 13'd1906
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_rd_calib_2_f_calslope_attr == 13'd2244
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_rd_calib_3_ext_ctrl_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_rd_calib_3_f_caloffset_attr == 13'd1906
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_rd_calib_3_f_calslope_attr == 13'd2244
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_rd_calib_4_ext_ctrl_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_rd_calib_4_f_caloffset_attr == 13'd1906
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_rd_calib_4_f_calslope_attr == 13'd2244
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_rd_calib_5_ext_ctrl_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_rd_calib_5_f_caloffset_attr == 13'd1906
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_rd_calib_5_f_calslope_attr == 13'd2244
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_rd_calib_6_ext_ctrl_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_rd_calib_6_f_caloffset_attr == 13'd1906
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_rd_calib_6_f_calslope_attr == 13'd2244
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_status_f_calconfigsel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.dts_status_f_calgamma_attr == 6'd23
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.efuse_ctrl_ext_ctrl_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.efuse_ctrl_iaddr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.efuse_ctrl_ichipsel_attr == EFUSE_CTRL_ICHIPSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.efuse_ctrl_ifavor_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.efuse_ctrl_ipgmctl_attr == EFUSE_CTRL_IPGMCTL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.efuse_ctrl_ipgmen_attr == EFUSE_CTRL_IPGMEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.efuse_ctrl_isense_attr == EFUSE_CTRL_ISENSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.efuse_ctrl_isenselv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.efuse_wr_data_wr_data_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.gdr_ctrl_dfd_bsync_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.gdr_ctrl_dfd_datasel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.gdr_ctrl_dfd_dfd_clk_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.gdr_ctrl_dfd_dfd_rst_n_attr == GDR_CTRL_DFD_DFD_RST_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.gdr_ctrl_dfd_primary_attr == GDR_CTRL_DFD_PRIMARY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.gdr_ctrl_dfd_seondary_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.local_avmm_enable_attr == LOCAL_AVMM_DISABLE_ATTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.mailbox_out_outgoing_attr == 32'd119
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.memory_ctrl_f_addr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.memory_ctrl_f_pll_num == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.memory_ctrl_f_req == MEMREQ_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.memory_ctrl_f_wdata == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.memory_ctrl_f_wr == MEMWR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.mmem_ext_ctrl_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.mmem_m_1p_rmce_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.mmem_m_1p_wmce_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.mmem_m_1p_wpulse_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.mmem_m_2p_rmce_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.mmem_m_2p_wmce_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.mmem_m_2p_wpulse_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.mmem_mce_attr == MMEM_MCE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.mmem_ra_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.mmem_wa_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pcie_cvp_attr == PCIE_CVP_ATTR_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pcie_cvp_enable_attr == PCIE_CVP_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pcie_cvp_inprogress_attr == PCIE_CVP_INPROGRESS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pcie_cvp_request_attr == PCIE_CVP_REQUEST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pcie_ext_ctrl_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pcie_hrc_pin_perst_n_attr == PCIE_HRC_PIN_PERST_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pcie_hrc_pld_clrpll_n_attr == PCIE_HRC_PLD_CLRPLL_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pcie_hrc_pld_perst_n_attr == PCIE_HRC_PLD_PERST_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pcie_hw_decode_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pcie_perstn_debounced_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pcie_pll_lock_pldclk_attr == PCIE_PLL_LOCK_PLDCLK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pcie_ssm_perst_overide_attr == PCIE_SSM_PERST_OVERIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pcie_use_pin_perstn_attr == PCIE_DOES_NOT_USE_PINPERST_ATTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_c0_bypass_control == PLL_0_C0_BYPASS_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_c0_clkmute == PLL_0_C0_CLKMUTE_UNMUTE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_c0_counter == 11'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_c0_output_enable == PLL_0_C0_OUTPUT_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_c1_bypass_control == PLL_0_C1_BYPASS_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_c1_clkmute == PLL_0_C1_CLKMUTE_UNMUTE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_c1_counter == 11'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_c1_output_enable == PLL_0_C1_OUTPUT_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_c2_bypass_control == PLL_0_C2_BYPASS_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_c2_clkmute == PLL_0_C2_CLKMUTE_UNMUTE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_c2_counter == 11'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_c2_output_enable == PLL_0_C2_OUTPUT_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_c3_bypass_control == PLL_0_C3_BYPASS_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_c3_clkmute == PLL_0_C3_CLKMUTE_MUTE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_c3_counter == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_c3_output_enable == PLL_0_C3_OUTPUT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_calib_f_hscount == 10'd82
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_calib_f_mscount == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_ethernet_preset == PLL_0_ETHERNET_FREQ_OTHER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_f_max_pfd_hz == 36'd400000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_f_max_ref_hz == 36'd380000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_f_max_vco_hz == 36'd6650000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_f_min_pfd_hz == 36'd20000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_f_min_ref_hz == 36'd100000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_f_min_vco_hz == 36'd3500000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_f_out_c0_hz == 36'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_f_out_c1_hz == 36'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_f_out_c2_hz == 36'd250000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_f_out_c3_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_f_pfd_hz == 36'd31250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_f_ref0_hz == 36'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_f_ref1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_f_ref2_hz == 36'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_f_ref3_hz == 36'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_f_ref4_hz == 36'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_f_ref5_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_f_ref6_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_f_ref7_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_f_ref_gpio_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_f_ref_hz == 36'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_f_vco_hz == 36'd4500000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_fastref_enable == PLL_0_FASTREF_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_fractional_enable == PLL_0_FRACTIONAL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_k_counter == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_m_counter == 10'd144
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_mod_counter == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_n_counter == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_pcie_preset == PLL_0_PCIE_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_pll_sync == PLL_0_PLL_SYNC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_powerdown_mode == PLL_0_PWRDN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_primary_use == PLL_0_ETHERNET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_refclk_calibration_counter == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_refclk_mux_select == PLL_0_REF_CLK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_refclk_period_nsec == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_rst == PLL_0_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_spare_attribute_0 == PLL_0_VALUE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_spare_attribute_1 == PLL_0_VALUE4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_0_sup_mode == PLL_0_ADVANCED_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_c0_bypass_control == PLL_1_C0_BYPASS_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_c0_clkmute == PLL_1_C0_CLKMUTE_UNMUTE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_c0_counter == 11'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_c0_output_enable == PLL_1_C0_OUTPUT_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_c1_bypass_control == PLL_1_C1_BYPASS_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_c1_clkmute == PLL_1_C1_CLKMUTE_UNMUTE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_c1_counter == 11'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_c1_output_enable == PLL_1_C1_OUTPUT_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_c2_bypass_control == PLL_1_C2_BYPASS_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_c2_clkmute == PLL_1_C2_CLKMUTE_UNMUTE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_c2_counter == 11'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_c2_output_enable == PLL_1_C2_OUTPUT_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_c3_bypass_control == PLL_1_C3_BYPASS_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_c3_clkmute == PLL_1_C3_CLKMUTE_MUTE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_c3_counter == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_c3_output_enable == PLL_1_C3_OUTPUT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_calib_f_hscount == 10'd82
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_calib_f_mscount == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_ethernet_preset == PLL_1_ETHERNET_FREQ_OTHER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_f_max_pfd_hz == 36'd400000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_f_max_ref_hz == 36'd380000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_f_max_vco_hz == 36'd6650000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_f_min_pfd_hz == 36'd20000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_f_min_ref_hz == 36'd100000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_f_min_vco_hz == 36'd3500000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_f_out_c0_hz == 36'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_f_out_c1_hz == 36'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_f_out_c2_hz == 36'd250000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_f_out_c3_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_f_pfd_hz == 36'd31250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_f_ref0_hz == 36'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_f_ref1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_f_ref2_hz == 36'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_f_ref3_hz == 36'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_f_ref4_hz == 36'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_f_ref5_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_f_ref6_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_f_ref7_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_f_ref_gpio_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_f_ref_hz == 36'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_f_vco_hz == 36'd4500000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_fastref_enable == PLL_1_FASTREF_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_fractional_enable == PLL_1_FRACTIONAL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_k_counter == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_m_counter == 10'd144
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_mod_counter == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_n_counter == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_pcie_preset == PLL_1_PCIE_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_pll_sync == PLL_1_PLL_SYNC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_powerdown_mode == PLL_1_PWRDN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_primary_use == PLL_1_ETHERNET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_refclk_calibration_counter == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_refclk_mux_select == PLL_1_REF_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_refclk_period_nsec == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_rst == PLL_1_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_spare_attribute_0 == PLL_1_VALUE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_spare_attribute_1 == PLL_1_VALUE4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_1_sup_mode == PLL_1_ADVANCED_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_c0_bypass_control == PLL_2_C0_BYPASS_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_c0_clkmute == PLL_2_C0_CLKMUTE_MUTE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_c0_counter == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_c0_output_enable == PLL_2_C0_OUTPUT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_c1_bypass_control == PLL_2_C1_BYPASS_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_c1_clkmute == PLL_2_C1_CLKMUTE_MUTE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_c1_counter == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_c1_output_enable == PLL_2_C1_OUTPUT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_c2_bypass_control == PLL_2_C2_BYPASS_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_c2_clkmute == PLL_2_C2_CLKMUTE_MUTE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_c2_counter == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_c2_output_enable == PLL_2_C2_OUTPUT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_c3_bypass_control == PLL_2_C3_BYPASS_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_c3_clkmute == PLL_2_C3_CLKMUTE_MUTE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_c3_counter == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_c3_output_enable == PLL_2_C3_OUTPUT_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_calib_f_hscount == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_calib_f_mscount == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_ethernet_preset == PLL_2_ETHERNET_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_f_max_pfd_hz == 36'd400000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_f_max_ref_hz == 36'd380000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_f_max_vco_hz == 36'd6650000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_f_min_pfd_hz == 36'd20000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_f_min_ref_hz == 36'd100000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_f_min_vco_hz == 36'd3500000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_f_out_c0_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_f_out_c1_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_f_out_c2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_f_out_c3_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_f_pfd_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_f_ref0_hz == 36'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_f_ref1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_f_ref2_hz == 36'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_f_ref3_hz == 36'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_f_ref4_hz == 36'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_f_ref5_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_f_ref6_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_f_ref7_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_f_ref_gpio_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_f_ref_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_f_vco_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_fastref_enable == PLL_2_FASTREF_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_fractional_enable == PLL_2_FRACTIONAL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_k_counter == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_m_counter == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_mod_counter == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_n_counter == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_pcie_preset == PLL_2_PCIE_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_pll_sync == PLL_2_PLL_SYNC_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_powerdown_mode == PLL_2_PWRDN_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_primary_use == PLL_2_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_refclk_calibration_counter == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_refclk_mux_select == PLL_2_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_refclk_period_nsec == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_rst == PLL_2_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_spare_attribute_0 == PLL_2_VALUE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_spare_attribute_1 == PLL_2_VALUE4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_2_sup_mode == PLL_2_ADVANCED_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_calib_0_f_hscount_attr == 10'd82
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_calib_0_f_mscount_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_calib_1_f_hscount_attr == 10'd82
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_calib_1_f_mscount_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_calib_2_f_hscount_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_calib_2_f_mscount_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_0_f_aref_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_0_f_cal_clr_a_attr == PLL_CTRL_0_F_CAL_CLR_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_0_f_disconnect_a_attr == PLL_CTRL_0_F_DISCONNECT_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_0_f_disconnect_keepalive_attr == PLL_CTRL_0_F_DISCONNECT_KEEPALIVE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_0_f_dref_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_0_f_extended_attr == PLL_CTRL_0_F_EXTENDED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_0_f_fastrefen_attr == PLL_CTRL_0_F_FASTREFEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_0_f_freqgen_hop_dir_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_0_f_freqgen_hop_req_attr == PLL_CTRL_0_F_FREQGEN_HOP_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_0_f_freqgen_ssc_req_attr == PLL_CTRL_0_F_FREQGEN_SSC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_0_f_keepalive_attr == PLL_CTRL_0_F_KEEPALIVE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_0_f_mod_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_0_f_refclk_sel_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_0_f_rst_n_attr == PLL_CTRL_0_F_RST_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_0_f_spare_attr == PLL_CTRL_0_F_SPARE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_0_f_sync_attr == PLL_CTRL_0_F_SYNC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_1_f_aref_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_1_f_cal_clr_a_attr == PLL_CTRL_1_F_CAL_CLR_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_1_f_disconnect_a_attr == PLL_CTRL_1_F_DISCONNECT_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_1_f_disconnect_keepalive_attr == PLL_CTRL_1_F_DISCONNECT_KEEPALIVE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_1_f_dref_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_1_f_extended_attr == PLL_CTRL_1_F_EXTENDED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_1_f_fastrefen_attr == PLL_CTRL_1_F_FASTREFEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_1_f_freqgen_hop_dir_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_1_f_freqgen_hop_req_attr == PLL_CTRL_1_F_FREQGEN_HOP_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_1_f_freqgen_ssc_req_attr == PLL_CTRL_1_F_FREQGEN_SSC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_1_f_keepalive_attr == PLL_CTRL_1_F_KEEPALIVE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_1_f_mod_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_1_f_refclk_sel_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_1_f_rst_n_attr == PLL_CTRL_1_F_RST_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_1_f_spare_attr == PLL_CTRL_1_F_SPARE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_1_f_sync_attr == PLL_CTRL_1_F_SYNC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_2_f_aref_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_2_f_cal_clr_a_attr == PLL_CTRL_2_F_CAL_CLR_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_2_f_disconnect_a_attr == PLL_CTRL_2_F_DISCONNECT_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_2_f_disconnect_keepalive_attr == PLL_CTRL_2_F_DISCONNECT_KEEPALIVE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_2_f_dref_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_2_f_extended_attr == PLL_CTRL_2_F_EXTENDED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_2_f_fastrefen_attr == PLL_CTRL_2_F_FASTREFEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_2_f_freqgen_hop_dir_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_2_f_freqgen_hop_req_attr == PLL_CTRL_2_F_FREQGEN_HOP_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_2_f_freqgen_ssc_req_attr == PLL_CTRL_2_F_FREQGEN_SSC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_2_f_keepalive_attr == PLL_CTRL_2_F_KEEPALIVE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_2_f_mod_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_2_f_refclk_sel_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_2_f_rst_n_attr == PLL_CTRL_2_F_RST_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_2_f_spare_attr == PLL_CTRL_2_F_SPARE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ctrl_2_f_sync_attr == PLL_CTRL_2_F_SYNC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_f_ref0_hz == 36'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_f_ref1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_f_ref2_hz == 36'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_f_ref3_hz == 36'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_f_ref4_hz == 36'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_f_ref5_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_f_ref6_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_f_ref7_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_f_ref_gpio_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_fdiv_ctrl_0_f_ctrl_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_fdiv_ctrl_1_f_ctrl_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_fdiv_ctrl_2_f_ctrl_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_mdiv_ctrl_0_f_ctrl_attr == 10'd144
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_mdiv_ctrl_1_f_ctrl_attr == 10'd144
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_mdiv_ctrl_2_f_ctrl_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_mem_ctrl_f_addr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_mem_ctrl_f_pll_num_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_mem_ctrl_f_req_attr == PLL_MEM_CTRL_F_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_mem_ctrl_f_wdata_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_mem_ctrl_f_wr_attr == PLL_MEM_CTRL_F_WR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ref_clk_chk_0_f_cntr_end_value_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ref_clk_chk_0_f_ref_cntr_rstb_attr == PLL_REF_CLK_CHK_0_F_REF_CNTR_RSTB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ref_clk_chk_0_f_ref_cntr_start_attr == PLL_REF_CLK_CHK_0_F_REF_CNTR_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ref_clk_chk_1_f_cntr_end_value_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ref_clk_chk_1_f_ref_cntr_rstb_attr == PLL_REF_CLK_CHK_1_F_REF_CNTR_RSTB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ref_clk_chk_1_f_ref_cntr_start_attr == PLL_REF_CLK_CHK_1_F_REF_CNTR_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ref_clk_chk_2_f_cntr_end_value_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ref_clk_chk_2_f_ref_cntr_rstb_attr == PLL_REF_CLK_CHK_2_F_REF_CNTR_RSTB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_ref_clk_chk_2_f_ref_cntr_start_attr == PLL_REF_CLK_CHK_2_F_REF_CNTR_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice0_1_div_ctrl_0_f_ctrl_0_attr == 11'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice0_1_div_ctrl_0_f_ctrl_1_attr == 11'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice0_1_div_ctrl_0_f_slice_bypass_en_0_attr == PLL_SLICE0_1_DIV_CTRL_0_F_SLICE_BYPASS_EN_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice0_1_div_ctrl_0_f_slice_bypass_en_1_attr == PLL_SLICE0_1_DIV_CTRL_0_F_SLICE_BYPASS_EN_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice0_1_div_ctrl_0_f_slice_ckmute_en_0_attr == PLL_SLICE0_1_DIV_CTRL_0_F_SLICE_CKMUTE_EN_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice0_1_div_ctrl_0_f_slice_ckmute_en_1_attr == PLL_SLICE0_1_DIV_CTRL_0_F_SLICE_CKMUTE_EN_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice0_1_div_ctrl_0_f_slice_en_0_attr == PLL_SLICE0_1_DIV_CTRL_0_F_SLICE_EN_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice0_1_div_ctrl_0_f_slice_en_1_attr == PLL_SLICE0_1_DIV_CTRL_0_F_SLICE_EN_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice0_1_div_ctrl_1_f_ctrl_0_attr == 11'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice0_1_div_ctrl_1_f_ctrl_1_attr == 11'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice0_1_div_ctrl_1_f_slice_bypass_en_0_attr == PLL_SLICE0_1_DIV_CTRL_1_F_SLICE_BYPASS_EN_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice0_1_div_ctrl_1_f_slice_bypass_en_1_attr == PLL_SLICE0_1_DIV_CTRL_1_F_SLICE_BYPASS_EN_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice0_1_div_ctrl_1_f_slice_ckmute_en_0_attr == PLL_SLICE0_1_DIV_CTRL_1_F_SLICE_CKMUTE_EN_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice0_1_div_ctrl_1_f_slice_ckmute_en_1_attr == PLL_SLICE0_1_DIV_CTRL_1_F_SLICE_CKMUTE_EN_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice0_1_div_ctrl_1_f_slice_en_0_attr == PLL_SLICE0_1_DIV_CTRL_1_F_SLICE_EN_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice0_1_div_ctrl_1_f_slice_en_1_attr == PLL_SLICE0_1_DIV_CTRL_1_F_SLICE_EN_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice0_1_div_ctrl_2_f_ctrl_0_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice0_1_div_ctrl_2_f_ctrl_1_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice0_1_div_ctrl_2_f_slice_bypass_en_0_attr == PLL_SLICE0_1_DIV_CTRL_2_F_SLICE_BYPASS_EN_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice0_1_div_ctrl_2_f_slice_bypass_en_1_attr == PLL_SLICE0_1_DIV_CTRL_2_F_SLICE_BYPASS_EN_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice0_1_div_ctrl_2_f_slice_ckmute_en_0_attr == PLL_SLICE0_1_DIV_CTRL_2_F_SLICE_CKMUTE_EN_0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice0_1_div_ctrl_2_f_slice_ckmute_en_1_attr == PLL_SLICE0_1_DIV_CTRL_2_F_SLICE_CKMUTE_EN_1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice0_1_div_ctrl_2_f_slice_en_0_attr == PLL_SLICE0_1_DIV_CTRL_2_F_SLICE_EN_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice0_1_div_ctrl_2_f_slice_en_1_attr == PLL_SLICE0_1_DIV_CTRL_2_F_SLICE_EN_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice2_3_div_ctrl_0_f_ctrl_0_attr == 11'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice2_3_div_ctrl_0_f_ctrl_1_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice2_3_div_ctrl_0_f_slice_bypass_en_0_attr == PLL_SLICE2_3_DIV_CTRL_0_F_SLICE_BYPASS_EN_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice2_3_div_ctrl_0_f_slice_bypass_en_1_attr == PLL_SLICE2_3_DIV_CTRL_0_F_SLICE_BYPASS_EN_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice2_3_div_ctrl_0_f_slice_ckmute_en_0_attr == PLL_SLICE2_3_DIV_CTRL_0_F_SLICE_CKMUTE_EN_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice2_3_div_ctrl_0_f_slice_ckmute_en_1_attr == PLL_SLICE2_3_DIV_CTRL_0_F_SLICE_CKMUTE_EN_1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice2_3_div_ctrl_0_f_slice_en_0_attr == PLL_SLICE2_3_DIV_CTRL_0_F_SLICE_EN_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice2_3_div_ctrl_0_f_slice_en_1_attr == PLL_SLICE2_3_DIV_CTRL_0_F_SLICE_EN_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice2_3_div_ctrl_1_f_ctrl_0_attr == 11'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice2_3_div_ctrl_1_f_ctrl_1_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice2_3_div_ctrl_1_f_slice_bypass_en_0_attr == PLL_SLICE2_3_DIV_CTRL_1_F_SLICE_BYPASS_EN_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice2_3_div_ctrl_1_f_slice_bypass_en_1_attr == PLL_SLICE2_3_DIV_CTRL_1_F_SLICE_BYPASS_EN_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice2_3_div_ctrl_1_f_slice_ckmute_en_0_attr == PLL_SLICE2_3_DIV_CTRL_1_F_SLICE_CKMUTE_EN_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice2_3_div_ctrl_1_f_slice_ckmute_en_1_attr == PLL_SLICE2_3_DIV_CTRL_1_F_SLICE_CKMUTE_EN_1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice2_3_div_ctrl_1_f_slice_en_0_attr == PLL_SLICE2_3_DIV_CTRL_1_F_SLICE_EN_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice2_3_div_ctrl_1_f_slice_en_1_attr == PLL_SLICE2_3_DIV_CTRL_1_F_SLICE_EN_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice2_3_div_ctrl_2_f_ctrl_0_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice2_3_div_ctrl_2_f_ctrl_1_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice2_3_div_ctrl_2_f_slice_bypass_en_0_attr == PLL_SLICE2_3_DIV_CTRL_2_F_SLICE_BYPASS_EN_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice2_3_div_ctrl_2_f_slice_bypass_en_1_attr == PLL_SLICE2_3_DIV_CTRL_2_F_SLICE_BYPASS_EN_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice2_3_div_ctrl_2_f_slice_ckmute_en_0_attr == PLL_SLICE2_3_DIV_CTRL_2_F_SLICE_CKMUTE_EN_0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice2_3_div_ctrl_2_f_slice_ckmute_en_1_attr == PLL_SLICE2_3_DIV_CTRL_2_F_SLICE_CKMUTE_EN_1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice2_3_div_ctrl_2_f_slice_en_0_attr == PLL_SLICE2_3_DIV_CTRL_2_F_SLICE_EN_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.pll_slice2_3_div_ctrl_2_f_slice_en_1_attr == PLL_SLICE2_3_DIV_CTRL_2_F_SLICE_EN_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.powermode_ac_dfd == DFD_POWER_UP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.powermode_ac_misc == MISC_POWER_UP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.powermode_ac_pll0 == PLL0_POWER_UP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.powermode_ac_pll1 == PLL1_POWER_UP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.powermode_ac_pll2 == PLL2_POWER_DN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.powermode_freq_hz_avmm_clk_attr == 36'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.powermode_freq_hz_cnoc_clk_attr == 36'd250000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.powermode_freq_hz_pll_0_f_out_c0 == 36'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.powermode_freq_hz_pll_0_f_out_c1 == 36'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.powermode_freq_hz_pll_0_f_out_c2 == 36'd250000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.powermode_freq_hz_pll_0_f_ref == 36'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.powermode_freq_hz_pll_0_f_vco == 36'd4500000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.powermode_freq_hz_pll_1_f_out_c0 == 36'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.powermode_freq_hz_pll_1_f_out_c1 == 36'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.powermode_freq_hz_pll_1_f_out_c2 == 36'd250000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.powermode_freq_hz_pll_1_f_ref == 36'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.powermode_freq_hz_pll_1_f_vco == 36'd4500000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.powermode_freq_hz_pll_2_f_out_c0 == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.powermode_freq_hz_pll_2_f_out_c1 == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.powermode_freq_hz_pll_2_f_out_c2 == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.powermode_freq_hz_pll_2_f_ref == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.powermode_freq_hz_pll_2_f_vco == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.primary_arb_read_pipe_attr == PRIMARY_ARB_READ_PIPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.primary_arb_waitreq_pipe_attr == PRIMARY_ARB_WAITREQ_PIPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.primary_arb_write_pipe_attr == PRIMARY_ARB_WRITE_PIPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.primary_atb_ctrl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.primary_cfgavmm_to_ena_attr == PRIMARY_CFGAVMM_TO_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.primary_cfgavmm_to_rst_attr == PRIMARY_CFGAVMM_TO_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.primary_dfd_power_off_attr == PRIMARY_DFD_POWER_OFF_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.primary_ext_ctrl_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.primary_filt_avmm_orphean_dis_attr == PRIMARY_FILT_AVMM_ORPHEAN_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.primary_global_avmm_user_access_en_attr == PRIMARY_GLOBAL_AVMM_USER_ACCESS_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.primary_master_topologies_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.primary_reset_wcounter_attr == PRIMARY_RESET_WCOUNTER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.secondary_f_byte0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.secondary_f_byte1_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.secondary_f_byte2_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.secondary_f_byte3_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.ssm_mmem_ext_ctrl_attr == 14'd119
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.ssm_mmem_m_1p_rmce_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.ssm_mmem_m_1p_wmce_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.ssm_mmem_m_1p_wpulse_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.ssm_mmem_mce_attr == SMMEM_MCE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.ssm_mmem_ra_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.ssm_mmem_wa_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.sup_mode == ADVANCED_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.topology == UX16E400GPTP_XX_DISABLED_XX_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.ux0_ux1_ux0_ctrl_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.ux0_ux1_ux1_ctrl_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.ux2_ux3_ux2_ctrl_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.ux2_ux3_ux3_ctrl_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.aibaux_actreden == AIBAUX_ACTREDEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.aibaux_asyn_rxen == AIBAUX_ASYN_RXEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.aibaux_asyn_txen == AIBAUX_ASYN_TXEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.aibaux_cndn_cken == AIBAUX_CNDN_CKEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.aibaux_cndn_rxen == AIBAUX_CNDN_RXEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.aibaux_cnup_txen == AIBAUX_CNUP_TXEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.aibaux_dll_osc_cr_dftsel == AIBAUX_DLL_OSC_CR_DFTSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.aibaux_dly_ovrd_cnocdn == AIBAUX_DLY_OVRD_CNOCDN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.aibaux_dly_ovrd_cnocup == AIBAUX_DLY_OVRD_CNOCUP_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.aibaux_dly_ovrden_cnocdn == AIBAUX_DLY_OVRDEN_CNOCDN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.aibaux_dly_ovrden_cnocup == AIBAUX_DLY_OVRDEN_CNOCUP_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.aibaux_iocsr_sel == AIBAUX_IOCSRSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.aibaux_jtag_bypass == AIBAUX_JTAGBYP_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.aibaux_ndrv == AIBAUX_NDRV_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.aibaux_osc_atbmuxsel == AIBAUX_OSC_ATBMUXSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.aibaux_osc_bypclken == AIBAUX_OSC_BYPCLKEN_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.aibaux_osc_cr_dftcounter == AIBAUX_OSC_CR_DFTCOUNTER_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.aibaux_osc_cr_ld_cntr == AIBAUX_OSC_CR_LD_CNTR_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.aibaux_osc_cr_pdb == AIBAUX_OSC_CR_PDB_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.aibaux_osc_cr_spare == AIBAUX_OSC_CR_SPARE_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.aibaux_osc_cr_trim == 7'd45
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.aibaux_osc_cr_vccdreg_vsel == AIBAUX_OSC_CR_VCCDREG_VSEL_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.aibaux_osc_cr_vreg_rdy == AIBAUX_OSC_CR_VREG_RDY_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.aibaux_osc_monitoren == AIBAUX_OSC_MONITOREN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.aibaux_osc_reserved == AIBAUX_OSC_RESERVED_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.aibaux_osc_trim_overwrite == AIBAUX_OSC_OVRWRT_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.aibaux_pdrv == AIBAUX_PDRV_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.aibaux_pred_rxen == AIBAUX_PRED_RXEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.aibaux_pred_txen == AIBAUX_PRED_TXEN_SETTING1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.aibaux_spare0_bus0 == AIBAUX_SPARE0_BUS0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.aibaux_spare0_bus1 == AIBAUX_SPARE0_BUS1_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.aibaux_spare0_bus2 == AIBAUX_SPARE0_BUS2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.aibaux_spare1_bus0 == AIBAUX_SPARE1_BUS0_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.aibaux_spare1_bus2 == AIBAUX_SPARE1_BUS2_SETTING0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.dft_aux_en == DISABLE_DFT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.dft_dll_osc_dftsel == DISABLE_DLL_OSC_DFTSEL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.dft_osc_dftcounter == DISABLE_OSC_DFTCOUNTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.op_mode == AUX_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.powermode_ac == ENABLE_PWR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.redundancy_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ctrl.u_aibaux.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib1_tx_st0_adapt_rc_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib1_tx_st1_adapt_rc_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib1_tx_st2_adapt_rc_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib1_tx_st3_adapt_rc_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib1_tx_st4_adapt_rc_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib1_tx_st5_adapt_rc_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib1_tx_st6_adapt_rc_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib1_tx_st7_adapt_rc_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib2_rx_st0_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib2_rx_st1_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib2_rx_st2_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib2_rx_st3_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib2_rx_st4_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib2_rx_st5_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib2_rx_st6_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib2_rx_st7_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib2_tx_st0_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib2_tx_st1_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib2_tx_st2_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib2_tx_st3_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib2_tx_st4_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib2_tx_st5_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib2_tx_st6_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib2_tx_st7_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib3_rx_st0_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib3_rx_st1_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib3_rx_st2_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib3_rx_st3_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib3_rx_st4_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib3_rx_st5_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib3_rx_st6_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib3_rx_st7_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib3_tx_st0_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib3_tx_st1_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib3_tx_st2_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib3_tx_st3_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib3_tx_st4_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib3_tx_st5_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib3_tx_st6_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib3_tx_st7_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.aib_esys_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.block_enable == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_aib2_rx_st_clk_en == E200G_100G_0_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_aib2_tx_st_clk_en == E200G_100G_0_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_aib3_rx_st_clk_en == E200G_100G_0_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_aib3_tx_st_clk_en == E200G_100G_0_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_aibif_data_valid == E200G_100G_0_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_duplex_mode == E200G_100G_0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_fec_clk_src == E200G_100G_0_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_fec_error == E200G_100G_0_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_fec_mode == E200G_100G_0_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_fec_spec == E200G_100G_0_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_lpbk_mode == E200G_100G_0_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_mac_mode == E200G_100G_0_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_pcs_ber_mon_mode == E200G_100G_0_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_ptp_mode == E200G_100G_0_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_rx_aib_if_fifo_mode == E200G_100G_0_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_rx_excvr_gb_ratio_mode == E200G_100G_0_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_rx_excvr_if_fifo_mode == E200G_100G_0_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_rx_fec_enable == E200G_100G_0_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_rx_master_bond_chnl == E200G_100G_0_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_rx_pcs_mode == E200G_100G_0_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_rx_primary_use == E200G_100G_0_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_rx_xcvr_width == E200G_100G_0_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_speed_map == E200G_100G_0_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_sup_mode == E200G_100G_0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_sys_clk_src == E200G_100G_0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_tx_aib_if_fifo_mode == E200G_100G_0_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_tx_excvr_gb_ratio_mode == E200G_100G_0_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_tx_excvr_if_fifo_mode == E200G_100G_0_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_tx_fec_enable == E200G_100G_0_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_tx_master_bond_chnl == E200G_100G_0_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_tx_pcs_mode == E200G_100G_0_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_tx_primary_use == E200G_100G_0_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_tx_xcvr_width == E200G_100G_0_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_xcvr_mode == E200G_100G_0_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_0_xcvr_type == E200G_100G_0_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_aib2_rx_st_clk_en == E200G_100G_1_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_aib2_tx_st_clk_en == E200G_100G_1_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_aib3_rx_st_clk_en == E200G_100G_1_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_aib3_tx_st_clk_en == E200G_100G_1_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_aibif_data_valid == E200G_100G_1_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_duplex_mode == E200G_100G_1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_fec_clk_src == E200G_100G_1_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_fec_error == E200G_100G_1_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_fec_mode == E200G_100G_1_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_fec_spec == E200G_100G_1_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_lpbk_mode == E200G_100G_1_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_mac_mode == E200G_100G_1_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_pcs_ber_mon_mode == E200G_100G_1_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_ptp_mode == E200G_100G_1_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_rx_aib_if_fifo_mode == E200G_100G_1_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_rx_excvr_gb_ratio_mode == E200G_100G_1_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_rx_excvr_if_fifo_mode == E200G_100G_1_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_rx_fec_enable == E200G_100G_1_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_rx_master_bond_chnl == E200G_100G_1_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_rx_pcs_mode == E200G_100G_1_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_rx_primary_use == E200G_100G_1_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_rx_xcvr_width == E200G_100G_1_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_speed_map == E200G_100G_1_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_sup_mode == E200G_100G_1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_sys_clk_src == E200G_100G_1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_tx_aib_if_fifo_mode == E200G_100G_1_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_tx_excvr_gb_ratio_mode == E200G_100G_1_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_tx_excvr_if_fifo_mode == E200G_100G_1_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_tx_fec_enable == E200G_100G_1_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_tx_master_bond_chnl == E200G_100G_1_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_tx_pcs_mode == E200G_100G_1_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_tx_primary_use == E200G_100G_1_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_tx_xcvr_width == E200G_100G_1_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_xcvr_mode == E200G_100G_1_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_100g_1_xcvr_type == E200G_100G_1_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_aib2_rx_st_clk_en == E200G_150G_0_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_aib2_tx_st_clk_en == E200G_150G_0_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_aib3_rx_st_clk_en == E200G_150G_0_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_aib3_tx_st_clk_en == E200G_150G_0_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_aibif_data_valid == E200G_150G_0_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_duplex_mode == E200G_150G_0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_fec_mode == E200G_150G_0_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_fec_spec == E200G_150G_0_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_lpbk_mode == E200G_150G_0_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_mac_mode == E200G_150G_0_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_pcs_ber_mon_mode == E200G_150G_0_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_ptp_mode == E200G_150G_0_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_rx_aib_if_fifo_mode == E200G_150G_0_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_rx_excvr_gb_ratio_mode == E200G_150G_0_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_rx_excvr_if_fifo_mode == E200G_150G_0_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_rx_fec_enable == E200G_150G_0_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_rx_master_bond_chnl == E200G_150G_0_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_rx_pcs_mode == E200G_150G_0_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_rx_primary_use == E200G_150G_0_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_rx_xcvr_width == E200G_150G_0_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_speed_map == E200G_150G_0_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_sup_mode == E200G_150G_0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_sys_clk_src == E200G_150G_0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_tx_aib_if_fifo_mode == E200G_150G_0_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_tx_excvr_gb_ratio_mode == E200G_150G_0_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_tx_excvr_if_fifo_mode == E200G_150G_0_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_tx_fec_enable == E200G_150G_0_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_tx_master_bond_chnl == E200G_150G_0_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_tx_pcs_mode == E200G_150G_0_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_tx_primary_use == E200G_150G_0_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_tx_xcvr_width == E200G_150G_0_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_xcvr_mode == E200G_150G_0_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_0_xcvr_type == E200G_150G_0_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_aib2_rx_st_clk_en == E200G_150G_1_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_aib2_tx_st_clk_en == E200G_150G_1_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_aib3_rx_st_clk_en == E200G_150G_1_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_aib3_tx_st_clk_en == E200G_150G_1_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_aibif_data_valid == E200G_150G_1_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_duplex_mode == E200G_150G_1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_fec_mode == E200G_150G_1_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_fec_spec == E200G_150G_1_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_lpbk_mode == E200G_150G_1_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_mac_mode == E200G_150G_1_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_pcs_ber_mon_mode == E200G_150G_1_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_ptp_mode == E200G_150G_1_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_rx_aib_if_fifo_mode == E200G_150G_1_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_rx_excvr_gb_ratio_mode == E200G_150G_1_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_rx_excvr_if_fifo_mode == E200G_150G_1_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_rx_fec_enable == E200G_150G_1_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_rx_master_bond_chnl == E200G_150G_1_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_rx_pcs_mode == E200G_150G_1_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_rx_primary_use == E200G_150G_1_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_rx_xcvr_width == E200G_150G_1_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_speed_map == E200G_150G_1_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_sup_mode == E200G_150G_1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_sys_clk_src == E200G_150G_1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_tx_aib_if_fifo_mode == E200G_150G_1_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_tx_excvr_gb_ratio_mode == E200G_150G_1_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_tx_excvr_if_fifo_mode == E200G_150G_1_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_tx_fec_enable == E200G_150G_1_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_tx_master_bond_chnl == E200G_150G_1_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_tx_pcs_mode == E200G_150G_1_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_tx_primary_use == E200G_150G_1_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_tx_xcvr_width == E200G_150G_1_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_xcvr_mode == E200G_150G_1_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_150g_1_xcvr_type == E200G_150G_1_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_aib2_rx_st_clk_en == E200G_200G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_aib2_tx_st_clk_en == E200G_200G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_aib3_rx_st_clk_en == E200G_200G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_aib3_tx_st_clk_en == E200G_200G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_aibif_data_valid == E200G_200G_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_duplex_mode == E200G_200G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_fec_clk_src == E200G_200G_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_fec_error == E200G_200G_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_fec_mode == E200G_200G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_fec_spec == E200G_200G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_lpbk_mode == E200G_200G_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_mac_mode == E200G_200G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_pcs_ber_mon_mode == E200G_200G_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_ptp_mode == E200G_200G_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_rx_aib_if_fifo_mode == E200G_200G_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_rx_excvr_gb_ratio_mode == E200G_200G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_rx_excvr_if_fifo_mode == E200G_200G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_rx_fec_enable == E200G_200G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_rx_master_bond_chnl == E200G_200G_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_rx_pcs_mode == E200G_200G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_rx_primary_use == E200G_200G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_rx_xcvr_width == E200G_200G_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_speed_map == E200G_200G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_sup_mode == E200G_200G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_sys_clk_src == E200G_200G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_tx_aib_if_fifo_mode == E200G_200G_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_tx_excvr_gb_ratio_mode == E200G_200G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_tx_excvr_if_fifo_mode == E200G_200G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_tx_fec_enable == E200G_200G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_tx_master_bond_chnl == E200G_200G_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_tx_pcs_mode == E200G_200G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_tx_primary_use == E200G_200G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_tx_xcvr_width == E200G_200G_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_xcvr_mode == E200G_200G_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_200g_xcvr_type == E200G_200G_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_aib2_rx_st_clk_en == E200G_25G_0_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_aib2_tx_st_clk_en == E200G_25G_0_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_aib3_rx_st_clk_en == E200G_25G_0_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_aib3_tx_st_clk_en == E200G_25G_0_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_aibif_data_valid == E200G_25G_0_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_duplex_mode == E200G_25G_0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_fec_clk_src == E200G_25G_0_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_fec_error == E200G_25G_0_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_fec_mode == E200G_25G_0_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_fec_spec == E200G_25G_0_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_lpbk_mode == E200G_25G_0_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_mac_mode == E200G_25G_0_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_pcs_ber_mon_mode == E200G_25G_0_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_ptp_mode == E200G_25G_0_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_rx_aib_if_fifo_mode == E200G_25G_0_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_rx_excvr_gb_ratio_mode == E200G_25G_0_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_rx_excvr_if_fifo_mode == E200G_25G_0_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_rx_fec_enable == E200G_25G_0_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_rx_master_bond_chnl == E200G_25G_0_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_rx_pcs_mode == E200G_25G_0_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_rx_primary_use == E200G_25G_0_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_rx_xcvr_width == E200G_25G_0_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_speed_map == E200G_25G_0_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_sup_mode == E200G_25G_0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_sys_clk_src == E200G_25G_0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_tx_aib_if_fifo_mode == E200G_25G_0_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_tx_excvr_gb_ratio_mode == E200G_25G_0_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_tx_excvr_if_fifo_mode == E200G_25G_0_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_tx_fec_enable == E200G_25G_0_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_tx_master_bond_chnl == E200G_25G_0_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_tx_pcs_mode == E200G_25G_0_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_tx_primary_use == E200G_25G_0_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_tx_xcvr_width == E200G_25G_0_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_xcvr_mode == E200G_25G_0_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_0_xcvr_type == E200G_25G_0_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_aib2_rx_st_clk_en == E200G_25G_1_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_aib2_tx_st_clk_en == E200G_25G_1_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_aib3_rx_st_clk_en == E200G_25G_1_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_aib3_tx_st_clk_en == E200G_25G_1_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_aibif_data_valid == E200G_25G_1_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_duplex_mode == E200G_25G_1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_fec_clk_src == E200G_25G_1_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_fec_error == E200G_25G_1_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_fec_mode == E200G_25G_1_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_fec_spec == E200G_25G_1_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_lpbk_mode == E200G_25G_1_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_mac_mode == E200G_25G_1_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_pcs_ber_mon_mode == E200G_25G_1_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_ptp_mode == E200G_25G_1_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_rx_aib_if_fifo_mode == E200G_25G_1_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_rx_excvr_gb_ratio_mode == E200G_25G_1_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_rx_excvr_if_fifo_mode == E200G_25G_1_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_rx_fec_enable == E200G_25G_1_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_rx_master_bond_chnl == E200G_25G_1_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_rx_pcs_mode == E200G_25G_1_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_rx_primary_use == E200G_25G_1_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_rx_xcvr_width == E200G_25G_1_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_speed_map == E200G_25G_1_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_sup_mode == E200G_25G_1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_sys_clk_src == E200G_25G_1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_tx_aib_if_fifo_mode == E200G_25G_1_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_tx_excvr_gb_ratio_mode == E200G_25G_1_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_tx_excvr_if_fifo_mode == E200G_25G_1_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_tx_fec_enable == E200G_25G_1_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_tx_master_bond_chnl == E200G_25G_1_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_tx_pcs_mode == E200G_25G_1_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_tx_primary_use == E200G_25G_1_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_tx_xcvr_width == E200G_25G_1_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_xcvr_mode == E200G_25G_1_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_1_xcvr_type == E200G_25G_1_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_aib2_rx_st_clk_en == E200G_25G_2_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_aib2_tx_st_clk_en == E200G_25G_2_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_aib3_rx_st_clk_en == E200G_25G_2_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_aib3_tx_st_clk_en == E200G_25G_2_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_aibif_data_valid == E200G_25G_2_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_duplex_mode == E200G_25G_2_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_fec_clk_src == E200G_25G_2_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_fec_error == E200G_25G_2_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_fec_mode == E200G_25G_2_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_fec_spec == E200G_25G_2_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_lpbk_mode == E200G_25G_2_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_mac_mode == E200G_25G_2_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_pcs_ber_mon_mode == E200G_25G_2_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_ptp_mode == E200G_25G_2_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_rx_aib_if_fifo_mode == E200G_25G_2_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_rx_excvr_gb_ratio_mode == E200G_25G_2_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_rx_excvr_if_fifo_mode == E200G_25G_2_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_rx_fec_enable == E200G_25G_2_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_rx_master_bond_chnl == E200G_25G_2_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_rx_pcs_mode == E200G_25G_2_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_rx_primary_use == E200G_25G_2_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_rx_xcvr_width == E200G_25G_2_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_speed_map == E200G_25G_2_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_sup_mode == E200G_25G_2_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_sys_clk_src == E200G_25G_2_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_tx_aib_if_fifo_mode == E200G_25G_2_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_tx_excvr_gb_ratio_mode == E200G_25G_2_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_tx_excvr_if_fifo_mode == E200G_25G_2_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_tx_fec_enable == E200G_25G_2_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_tx_master_bond_chnl == E200G_25G_2_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_tx_pcs_mode == E200G_25G_2_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_tx_primary_use == E200G_25G_2_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_tx_xcvr_width == E200G_25G_2_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_xcvr_mode == E200G_25G_2_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_2_xcvr_type == E200G_25G_2_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_aib2_rx_st_clk_en == E200G_25G_3_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_aib2_tx_st_clk_en == E200G_25G_3_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_aib3_rx_st_clk_en == E200G_25G_3_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_aib3_tx_st_clk_en == E200G_25G_3_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_aibif_data_valid == E200G_25G_3_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_duplex_mode == E200G_25G_3_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_fec_clk_src == E200G_25G_3_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_fec_error == E200G_25G_3_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_fec_mode == E200G_25G_3_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_fec_spec == E200G_25G_3_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_lpbk_mode == E200G_25G_3_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_mac_mode == E200G_25G_3_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_pcs_ber_mon_mode == E200G_25G_3_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_ptp_mode == E200G_25G_3_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_rx_aib_if_fifo_mode == E200G_25G_3_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_rx_excvr_gb_ratio_mode == E200G_25G_3_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_rx_excvr_if_fifo_mode == E200G_25G_3_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_rx_fec_enable == E200G_25G_3_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_rx_master_bond_chnl == E200G_25G_3_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_rx_pcs_mode == E200G_25G_3_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_rx_primary_use == E200G_25G_3_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_rx_xcvr_width == E200G_25G_3_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_speed_map == E200G_25G_3_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_sup_mode == E200G_25G_3_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_sys_clk_src == E200G_25G_3_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_tx_aib_if_fifo_mode == E200G_25G_3_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_tx_excvr_gb_ratio_mode == E200G_25G_3_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_tx_excvr_if_fifo_mode == E200G_25G_3_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_tx_fec_enable == E200G_25G_3_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_tx_master_bond_chnl == E200G_25G_3_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_tx_pcs_mode == E200G_25G_3_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_tx_primary_use == E200G_25G_3_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_tx_xcvr_width == E200G_25G_3_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_xcvr_mode == E200G_25G_3_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_3_xcvr_type == E200G_25G_3_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_aib2_rx_st_clk_en == E200G_25G_4_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_aib2_tx_st_clk_en == E200G_25G_4_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_aib3_rx_st_clk_en == E200G_25G_4_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_aib3_tx_st_clk_en == E200G_25G_4_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_aibif_data_valid == E200G_25G_4_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_duplex_mode == E200G_25G_4_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_fec_clk_src == E200G_25G_4_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_fec_error == E200G_25G_4_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_fec_mode == E200G_25G_4_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_fec_spec == E200G_25G_4_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_lpbk_mode == E200G_25G_4_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_mac_mode == E200G_25G_4_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_pcs_ber_mon_mode == E200G_25G_4_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_ptp_mode == E200G_25G_4_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_rx_aib_if_fifo_mode == E200G_25G_4_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_rx_excvr_gb_ratio_mode == E200G_25G_4_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_rx_excvr_if_fifo_mode == E200G_25G_4_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_rx_fec_enable == E200G_25G_4_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_rx_master_bond_chnl == E200G_25G_4_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_rx_pcs_mode == E200G_25G_4_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_rx_primary_use == E200G_25G_4_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_rx_xcvr_width == E200G_25G_4_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_speed_map == E200G_25G_4_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_sup_mode == E200G_25G_4_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_sys_clk_src == E200G_25G_4_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_tx_aib_if_fifo_mode == E200G_25G_4_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_tx_excvr_gb_ratio_mode == E200G_25G_4_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_tx_excvr_if_fifo_mode == E200G_25G_4_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_tx_fec_enable == E200G_25G_4_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_tx_master_bond_chnl == E200G_25G_4_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_tx_pcs_mode == E200G_25G_4_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_tx_primary_use == E200G_25G_4_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_tx_xcvr_width == E200G_25G_4_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_xcvr_mode == E200G_25G_4_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_4_xcvr_type == E200G_25G_4_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_aib2_rx_st_clk_en == E200G_25G_5_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_aib2_tx_st_clk_en == E200G_25G_5_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_aib3_rx_st_clk_en == E200G_25G_5_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_aib3_tx_st_clk_en == E200G_25G_5_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_aibif_data_valid == E200G_25G_5_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_duplex_mode == E200G_25G_5_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_fec_clk_src == E200G_25G_5_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_fec_error == E200G_25G_5_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_fec_mode == E200G_25G_5_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_fec_spec == E200G_25G_5_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_lpbk_mode == E200G_25G_5_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_mac_mode == E200G_25G_5_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_pcs_ber_mon_mode == E200G_25G_5_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_ptp_mode == E200G_25G_5_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_rx_aib_if_fifo_mode == E200G_25G_5_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_rx_excvr_gb_ratio_mode == E200G_25G_5_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_rx_excvr_if_fifo_mode == E200G_25G_5_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_rx_fec_enable == E200G_25G_5_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_rx_master_bond_chnl == E200G_25G_5_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_rx_pcs_mode == E200G_25G_5_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_rx_primary_use == E200G_25G_5_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_rx_xcvr_width == E200G_25G_5_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_speed_map == E200G_25G_5_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_sup_mode == E200G_25G_5_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_sys_clk_src == E200G_25G_5_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_tx_aib_if_fifo_mode == E200G_25G_5_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_tx_excvr_gb_ratio_mode == E200G_25G_5_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_tx_excvr_if_fifo_mode == E200G_25G_5_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_tx_fec_enable == E200G_25G_5_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_tx_master_bond_chnl == E200G_25G_5_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_tx_pcs_mode == E200G_25G_5_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_tx_primary_use == E200G_25G_5_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_tx_xcvr_width == E200G_25G_5_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_xcvr_mode == E200G_25G_5_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_5_xcvr_type == E200G_25G_5_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_aib2_rx_st_clk_en == E200G_25G_6_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_aib2_tx_st_clk_en == E200G_25G_6_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_aib3_rx_st_clk_en == E200G_25G_6_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_aib3_tx_st_clk_en == E200G_25G_6_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_aibif_data_valid == E200G_25G_6_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_duplex_mode == E200G_25G_6_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_fec_clk_src == E200G_25G_6_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_fec_error == E200G_25G_6_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_fec_mode == E200G_25G_6_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_fec_spec == E200G_25G_6_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_lpbk_mode == E200G_25G_6_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_mac_mode == E200G_25G_6_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_pcs_ber_mon_mode == E200G_25G_6_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_ptp_mode == E200G_25G_6_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_rx_aib_if_fifo_mode == E200G_25G_6_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_rx_excvr_gb_ratio_mode == E200G_25G_6_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_rx_excvr_if_fifo_mode == E200G_25G_6_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_rx_fec_enable == E200G_25G_6_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_rx_master_bond_chnl == E200G_25G_6_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_rx_pcs_mode == E200G_25G_6_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_rx_primary_use == E200G_25G_6_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_rx_xcvr_width == E200G_25G_6_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_speed_map == E200G_25G_6_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_sup_mode == E200G_25G_6_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_sys_clk_src == E200G_25G_6_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_tx_aib_if_fifo_mode == E200G_25G_6_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_tx_excvr_gb_ratio_mode == E200G_25G_6_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_tx_excvr_if_fifo_mode == E200G_25G_6_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_tx_fec_enable == E200G_25G_6_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_tx_master_bond_chnl == E200G_25G_6_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_tx_pcs_mode == E200G_25G_6_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_tx_primary_use == E200G_25G_6_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_tx_xcvr_width == E200G_25G_6_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_xcvr_mode == E200G_25G_6_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_6_xcvr_type == E200G_25G_6_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_aib2_rx_st_clk_en == E200G_25G_7_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_aib2_tx_st_clk_en == E200G_25G_7_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_aib3_rx_st_clk_en == E200G_25G_7_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_aib3_tx_st_clk_en == E200G_25G_7_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_aibif_data_valid == E200G_25G_7_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_duplex_mode == E200G_25G_7_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_fec_clk_src == E200G_25G_7_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_fec_error == E200G_25G_7_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_fec_mode == E200G_25G_7_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_fec_spec == E200G_25G_7_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_lpbk_mode == E200G_25G_7_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_mac_mode == E200G_25G_7_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_pcs_ber_mon_mode == E200G_25G_7_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_ptp_mode == E200G_25G_7_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_rx_aib_if_fifo_mode == E200G_25G_7_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_rx_excvr_gb_ratio_mode == E200G_25G_7_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_rx_excvr_if_fifo_mode == E200G_25G_7_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_rx_fec_enable == E200G_25G_7_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_rx_master_bond_chnl == E200G_25G_7_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_rx_pcs_mode == E200G_25G_7_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_rx_primary_use == E200G_25G_7_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_rx_xcvr_width == E200G_25G_7_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_speed_map == E200G_25G_7_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_sup_mode == E200G_25G_7_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_sys_clk_src == E200G_25G_7_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_tx_aib_if_fifo_mode == E200G_25G_7_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_tx_excvr_gb_ratio_mode == E200G_25G_7_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_tx_excvr_if_fifo_mode == E200G_25G_7_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_tx_fec_enable == E200G_25G_7_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_tx_master_bond_chnl == E200G_25G_7_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_tx_pcs_mode == E200G_25G_7_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_tx_primary_use == E200G_25G_7_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_tx_xcvr_width == E200G_25G_7_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_xcvr_mode == E200G_25G_7_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_25g_7_xcvr_type == E200G_25G_7_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_aib2_rx_st_clk_en == E200G_50G_0_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_aib2_tx_st_clk_en == E200G_50G_0_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_aib3_rx_st_clk_en == E200G_50G_0_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_aib3_tx_st_clk_en == E200G_50G_0_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_aibif_data_valid == E200G_50G_0_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_duplex_mode == E200G_50G_0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_fec_clk_src == E200G_50G_0_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_fec_error == E200G_50G_0_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_fec_mode == E200G_50G_0_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_fec_spec == E200G_50G_0_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_lpbk_mode == E200G_50G_0_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_mac_mode == E200G_50G_0_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_pcs_ber_mon_mode == E200G_50G_0_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_ptp_mode == E200G_50G_0_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_rx_aib_if_fifo_mode == E200G_50G_0_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_rx_excvr_gb_ratio_mode == E200G_50G_0_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_rx_excvr_if_fifo_mode == E200G_50G_0_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_rx_fec_enable == E200G_50G_0_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_rx_master_bond_chnl == E200G_50G_0_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_rx_pcs_mode == E200G_50G_0_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_rx_primary_use == E200G_50G_0_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_rx_xcvr_width == E200G_50G_0_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_speed_map == E200G_50G_0_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_sup_mode == E200G_50G_0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_sys_clk_src == E200G_50G_0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_tx_aib_if_fifo_mode == E200G_50G_0_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_tx_excvr_gb_ratio_mode == E200G_50G_0_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_tx_excvr_if_fifo_mode == E200G_50G_0_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_tx_fec_enable == E200G_50G_0_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_tx_master_bond_chnl == E200G_50G_0_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_tx_pcs_mode == E200G_50G_0_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_tx_primary_use == E200G_50G_0_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_tx_xcvr_width == E200G_50G_0_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_xcvr_mode == E200G_50G_0_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_0_xcvr_type == E200G_50G_0_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_aib2_rx_st_clk_en == E200G_50G_1_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_aib2_tx_st_clk_en == E200G_50G_1_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_aib3_rx_st_clk_en == E200G_50G_1_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_aib3_tx_st_clk_en == E200G_50G_1_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_aibif_data_valid == E200G_50G_1_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_duplex_mode == E200G_50G_1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_fec_clk_src == E200G_50G_1_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_fec_error == E200G_50G_1_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_fec_mode == E200G_50G_1_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_fec_spec == E200G_50G_1_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_lpbk_mode == E200G_50G_1_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_mac_mode == E200G_50G_1_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_pcs_ber_mon_mode == E200G_50G_1_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_ptp_mode == E200G_50G_1_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_rx_aib_if_fifo_mode == E200G_50G_1_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_rx_excvr_gb_ratio_mode == E200G_50G_1_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_rx_excvr_if_fifo_mode == E200G_50G_1_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_rx_fec_enable == E200G_50G_1_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_rx_master_bond_chnl == E200G_50G_1_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_rx_pcs_mode == E200G_50G_1_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_rx_primary_use == E200G_50G_1_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_rx_xcvr_width == E200G_50G_1_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_speed_map == E200G_50G_1_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_sup_mode == E200G_50G_1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_sys_clk_src == E200G_50G_1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_tx_aib_if_fifo_mode == E200G_50G_1_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_tx_excvr_gb_ratio_mode == E200G_50G_1_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_tx_excvr_if_fifo_mode == E200G_50G_1_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_tx_fec_enable == E200G_50G_1_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_tx_master_bond_chnl == E200G_50G_1_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_tx_pcs_mode == E200G_50G_1_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_tx_primary_use == E200G_50G_1_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_tx_xcvr_width == E200G_50G_1_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_xcvr_mode == E200G_50G_1_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_1_xcvr_type == E200G_50G_1_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_aib2_rx_st_clk_en == E200G_50G_2_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_aib2_tx_st_clk_en == E200G_50G_2_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_aib3_rx_st_clk_en == E200G_50G_2_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_aib3_tx_st_clk_en == E200G_50G_2_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_aibif_data_valid == E200G_50G_2_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_duplex_mode == E200G_50G_2_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_fec_clk_src == E200G_50G_2_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_fec_error == E200G_50G_2_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_fec_mode == E200G_50G_2_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_fec_spec == E200G_50G_2_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_lpbk_mode == E200G_50G_2_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_mac_mode == E200G_50G_2_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_pcs_ber_mon_mode == E200G_50G_2_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_ptp_mode == E200G_50G_2_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_rx_aib_if_fifo_mode == E200G_50G_2_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_rx_excvr_gb_ratio_mode == E200G_50G_2_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_rx_excvr_if_fifo_mode == E200G_50G_2_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_rx_fec_enable == E200G_50G_2_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_rx_master_bond_chnl == E200G_50G_2_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_rx_pcs_mode == E200G_50G_2_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_rx_primary_use == E200G_50G_2_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_rx_xcvr_width == E200G_50G_2_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_speed_map == E200G_50G_2_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_sup_mode == E200G_50G_2_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_sys_clk_src == E200G_50G_2_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_tx_aib_if_fifo_mode == E200G_50G_2_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_tx_excvr_gb_ratio_mode == E200G_50G_2_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_tx_excvr_if_fifo_mode == E200G_50G_2_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_tx_fec_enable == E200G_50G_2_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_tx_master_bond_chnl == E200G_50G_2_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_tx_pcs_mode == E200G_50G_2_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_tx_primary_use == E200G_50G_2_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_tx_xcvr_width == E200G_50G_2_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_xcvr_mode == E200G_50G_2_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_2_xcvr_type == E200G_50G_2_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_aib2_rx_st_clk_en == E200G_50G_3_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_aib2_tx_st_clk_en == E200G_50G_3_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_aib3_rx_st_clk_en == E200G_50G_3_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_aib3_tx_st_clk_en == E200G_50G_3_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_aibif_data_valid == E200G_50G_3_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_duplex_mode == E200G_50G_3_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_fec_clk_src == E200G_50G_3_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_fec_error == E200G_50G_3_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_fec_mode == E200G_50G_3_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_fec_spec == E200G_50G_3_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_lpbk_mode == E200G_50G_3_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_mac_mode == E200G_50G_3_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_pcs_ber_mon_mode == E200G_50G_3_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_ptp_mode == E200G_50G_3_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_rx_aib_if_fifo_mode == E200G_50G_3_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_rx_excvr_gb_ratio_mode == E200G_50G_3_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_rx_excvr_if_fifo_mode == E200G_50G_3_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_rx_fec_enable == E200G_50G_3_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_rx_master_bond_chnl == E200G_50G_3_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_rx_pcs_mode == E200G_50G_3_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_rx_primary_use == E200G_50G_3_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_rx_xcvr_width == E200G_50G_3_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_speed_map == E200G_50G_3_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_sup_mode == E200G_50G_3_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_sys_clk_src == E200G_50G_3_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_tx_aib_if_fifo_mode == E200G_50G_3_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_tx_excvr_gb_ratio_mode == E200G_50G_3_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_tx_excvr_if_fifo_mode == E200G_50G_3_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_tx_fec_enable == E200G_50G_3_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_tx_master_bond_chnl == E200G_50G_3_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_tx_pcs_mode == E200G_50G_3_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_tx_primary_use == E200G_50G_3_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_tx_xcvr_width == E200G_50G_3_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_xcvr_mode == E200G_50G_3_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_50g_3_xcvr_type == E200G_50G_3_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream0_duplex_mode == E200G_STREAM0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream0_rx_aib_if_fifo_mode == E200G_STREAM0_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream0_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream0_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream0_rx_excvr_if_fifo_mode == E200G_STREAM0_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream0_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream0_rx_primary_use == E200G_STREAM0_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream0_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream0_rx_xcvr_width == E200G_STREAM0_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream0_sys_clk_src == E200G_STREAM0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream0_tx_aib_if_fifo_mode == E200G_STREAM0_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream0_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream0_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream0_tx_excvr_if_fifo_mode == E200G_STREAM0_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream0_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream0_tx_primary_use == E200G_STREAM0_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream0_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream0_tx_xcvr_width == E200G_STREAM0_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream1_duplex_mode == E200G_STREAM1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream1_rx_aib_if_fifo_mode == E200G_STREAM1_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream1_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream1_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream1_rx_excvr_if_fifo_mode == E200G_STREAM1_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream1_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream1_rx_primary_use == E200G_STREAM1_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream1_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream1_rx_xcvr_width == E200G_STREAM1_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream1_sys_clk_src == E200G_STREAM1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream1_tx_aib_if_fifo_mode == E200G_STREAM1_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream1_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream1_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream1_tx_excvr_if_fifo_mode == E200G_STREAM1_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream1_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream1_tx_primary_use == E200G_STREAM1_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream1_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream1_tx_xcvr_width == E200G_STREAM1_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream2_duplex_mode == E200G_STREAM2_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream2_rx_aib_if_fifo_mode == E200G_STREAM2_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream2_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream2_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream2_rx_excvr_if_fifo_mode == E200G_STREAM2_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream2_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream2_rx_primary_use == E200G_STREAM2_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream2_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream2_rx_xcvr_width == E200G_STREAM2_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream2_sys_clk_src == E200G_STREAM2_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream2_tx_aib_if_fifo_mode == E200G_STREAM2_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream2_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream2_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream2_tx_excvr_if_fifo_mode == E200G_STREAM2_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream2_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream2_tx_primary_use == E200G_STREAM2_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream2_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream2_tx_xcvr_width == E200G_STREAM2_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream3_duplex_mode == E200G_STREAM3_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream3_rx_aib_if_fifo_mode == E200G_STREAM3_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream3_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream3_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream3_rx_excvr_if_fifo_mode == E200G_STREAM3_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream3_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream3_rx_primary_use == E200G_STREAM3_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream3_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream3_rx_xcvr_width == E200G_STREAM3_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream3_sys_clk_src == E200G_STREAM3_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream3_tx_aib_if_fifo_mode == E200G_STREAM3_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream3_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream3_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream3_tx_excvr_if_fifo_mode == E200G_STREAM3_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream3_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream3_tx_primary_use == E200G_STREAM3_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream3_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream3_tx_xcvr_width == E200G_STREAM3_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream4_duplex_mode == E200G_STREAM4_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream4_rx_aib_if_fifo_mode == E200G_STREAM4_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream4_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream4_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream4_rx_excvr_if_fifo_mode == E200G_STREAM4_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream4_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream4_rx_primary_use == E200G_STREAM4_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream4_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream4_rx_xcvr_width == E200G_STREAM4_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream4_sys_clk_src == E200G_STREAM4_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream4_tx_aib_if_fifo_mode == E200G_STREAM4_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream4_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream4_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream4_tx_excvr_if_fifo_mode == E200G_STREAM4_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream4_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream4_tx_primary_use == E200G_STREAM4_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream4_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream4_tx_xcvr_width == E200G_STREAM4_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream5_duplex_mode == E200G_STREAM5_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream5_rx_aib_if_fifo_mode == E200G_STREAM5_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream5_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream5_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream5_rx_excvr_if_fifo_mode == E200G_STREAM5_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream5_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream5_rx_primary_use == E200G_STREAM5_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream5_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream5_rx_xcvr_width == E200G_STREAM5_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream5_sys_clk_src == E200G_STREAM5_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream5_tx_aib_if_fifo_mode == E200G_STREAM5_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream5_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream5_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream5_tx_excvr_if_fifo_mode == E200G_STREAM5_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream5_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream5_tx_primary_use == E200G_STREAM5_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream5_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream5_tx_xcvr_width == E200G_STREAM5_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream6_duplex_mode == E200G_STREAM6_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream6_rx_aib_if_fifo_mode == E200G_STREAM6_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream6_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream6_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream6_rx_excvr_if_fifo_mode == E200G_STREAM6_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream6_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream6_rx_primary_use == E200G_STREAM6_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream6_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream6_rx_xcvr_width == E200G_STREAM6_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream6_sys_clk_src == E200G_STREAM6_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream6_tx_aib_if_fifo_mode == E200G_STREAM6_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream6_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream6_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream6_tx_excvr_if_fifo_mode == E200G_STREAM6_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream6_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream6_tx_primary_use == E200G_STREAM6_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream6_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream6_tx_xcvr_width == E200G_STREAM6_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream7_duplex_mode == E200G_STREAM7_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream7_rx_aib_if_fifo_mode == E200G_STREAM7_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream7_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream7_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream7_rx_excvr_if_fifo_mode == E200G_STREAM7_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream7_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream7_rx_primary_use == E200G_STREAM7_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream7_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream7_rx_xcvr_width == E200G_STREAM7_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream7_sys_clk_src == E200G_STREAM7_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream7_tx_aib_if_fifo_mode == E200G_STREAM7_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream7_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream7_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream7_tx_excvr_if_fifo_mode == E200G_STREAM7_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream7_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream7_tx_primary_use == E200G_STREAM7_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream7_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_stream7_tx_xcvr_width == E200G_STREAM7_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux0_duplex_mode == E200G_UX0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux0_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux0_rx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux0_rx_master_bond_chnl == E200G_UX0_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux0_rx_protocol == E200G_UX0_RX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux0_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux0_rx_xcvr_width == E200G_UX0_RX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux0_speed_bucket == E200G_UX0_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux0_sys_clk_src == E200G_UX0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux0_tx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux0_tx_master_bond_chnl == E200G_UX0_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux0_tx_protocol == E200G_UX0_TX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux0_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux0_tx_xcvr_width == E200G_UX0_TX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux0_txrx_channel_operation == E200G_UX0_TXRX_CHANNEL_OPERATION_DUAL_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux0_txrx_line_encoding_type == E200G_UX0_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux0_xcvr_mode == E200G_UX0_XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux1_duplex_mode == E200G_UX1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux1_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux1_rx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux1_rx_master_bond_chnl == E200G_UX1_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux1_rx_protocol == E200G_UX1_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux1_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux1_rx_xcvr_width == E200G_UX1_RX_XCVR_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux1_speed_bucket == E200G_UX1_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux1_sys_clk_src == E200G_UX1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux1_tx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux1_tx_master_bond_chnl == E200G_UX1_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux1_tx_protocol == E200G_UX1_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux1_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux1_tx_xcvr_width == E200G_UX1_TX_XCVR_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux1_txrx_channel_operation == E200G_UX1_TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux1_txrx_line_encoding_type == E200G_UX1_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux1_xcvr_mode == E200G_UX1_XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux2_duplex_mode == E200G_UX2_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux2_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux2_rx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux2_rx_master_bond_chnl == E200G_UX2_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux2_rx_protocol == E200G_UX2_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux2_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux2_rx_xcvr_width == E200G_UX2_RX_XCVR_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux2_speed_bucket == E200G_UX2_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux2_sys_clk_src == E200G_UX2_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux2_tx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux2_tx_master_bond_chnl == E200G_UX2_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux2_tx_protocol == E200G_UX2_TX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux2_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux2_tx_xcvr_width == E200G_UX2_TX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux2_txrx_channel_operation == E200G_UX2_TXRX_CHANNEL_OPERATION_DUAL_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux2_txrx_line_encoding_type == E200G_UX2_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux2_xcvr_mode == E200G_UX2_XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux3_duplex_mode == E200G_UX3_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux3_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux3_rx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux3_rx_master_bond_chnl == E200G_UX3_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux3_rx_protocol == E200G_UX3_RX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux3_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux3_rx_xcvr_width == E200G_UX3_RX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux3_speed_bucket == E200G_UX3_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux3_sys_clk_src == E200G_UX3_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux3_tx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux3_tx_master_bond_chnl == E200G_UX3_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux3_tx_protocol == E200G_UX3_TX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux3_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux3_tx_xcvr_width == E200G_UX3_TX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux3_txrx_channel_operation == E200G_UX3_TXRX_CHANNEL_OPERATION_DUAL_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux3_txrx_line_encoding_type == E200G_UX3_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux3_xcvr_mode == E200G_UX3_XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux4_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux4_duplex_mode == E200G_UX4_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux4_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux4_rx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux4_rx_master_bond_chnl == E200G_UX4_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux4_rx_protocol == E200G_UX4_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux4_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux4_rx_xcvr_width == E200G_UX4_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux4_speed_bucket == E200G_UX4_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux4_sys_clk_src == E200G_UX4_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux4_tx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux4_tx_master_bond_chnl == E200G_UX4_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux4_tx_protocol == E200G_UX4_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux4_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux4_tx_xcvr_width == E200G_UX4_TX_XCVR_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux4_txrx_channel_operation == E200G_UX4_TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux4_txrx_line_encoding_type == E200G_UX4_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux4_xcvr_mode == E200G_UX4_XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux5_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux5_duplex_mode == E200G_UX5_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux5_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux5_rx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux5_rx_master_bond_chnl == E200G_UX5_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux5_rx_protocol == E200G_UX5_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux5_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux5_rx_xcvr_width == E200G_UX5_RX_XCVR_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux5_speed_bucket == E200G_UX5_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux5_sys_clk_src == E200G_UX5_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux5_tx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux5_tx_master_bond_chnl == E200G_UX5_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux5_tx_protocol == E200G_UX5_TX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux5_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux5_tx_xcvr_width == E200G_UX5_TX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux5_txrx_channel_operation == E200G_UX5_TXRX_CHANNEL_OPERATION_DUAL_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux5_txrx_line_encoding_type == E200G_UX5_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux5_xcvr_mode == E200G_UX5_XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux6_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux6_duplex_mode == E200G_UX6_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux6_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux6_rx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux6_rx_master_bond_chnl == E200G_UX6_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux6_rx_protocol == E200G_UX6_RX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux6_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux6_rx_xcvr_width == E200G_UX6_RX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux6_speed_bucket == E200G_UX6_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux6_sys_clk_src == E200G_UX6_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux6_tx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux6_tx_master_bond_chnl == E200G_UX6_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux6_tx_protocol == E200G_UX6_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux6_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux6_tx_xcvr_width == E200G_UX6_TX_XCVR_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux6_txrx_channel_operation == E200G_UX6_TXRX_CHANNEL_OPERATION_DUAL_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux6_txrx_line_encoding_type == E200G_UX6_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux6_xcvr_mode == E200G_UX6_XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux7_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux7_duplex_mode == E200G_UX7_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux7_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux7_rx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux7_rx_master_bond_chnl == E200G_UX7_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux7_rx_protocol == E200G_UX7_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux7_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux7_rx_xcvr_width == E200G_UX7_RX_XCVR_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux7_speed_bucket == E200G_UX7_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux7_sys_clk_src == E200G_UX7_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux7_tx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux7_tx_master_bond_chnl == E200G_UX7_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux7_tx_protocol == E200G_UX7_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux7_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux7_tx_xcvr_width == E200G_UX7_TX_XCVR_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux7_txrx_channel_operation == E200G_UX7_TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux7_txrx_line_encoding_type == E200G_UX7_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_ux7_xcvr_mode == E200G_UX7_XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x0_duplex_mode == E200G_XCVR_SPEED_MAP_25E2X0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x0_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x0_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x0_rx_master_bond_chnl == E200G_XCVR_SPEED_MAP_25E2X0_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x0_rx_protocol == E200G_XCVR_SPEED_MAP_25E2X0_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x0_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x0_rx_xcvr_width == E200G_XCVR_SPEED_MAP_25E2X0_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x0_speed_bucket == E200G_XCVR_SPEED_MAP_25E2X0_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x0_sys_clk_src == E200G_XCVR_SPEED_MAP_25E2X0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x0_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x0_tx_master_bond_chnl == E200G_XCVR_SPEED_MAP_25E2X0_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x0_tx_protocol == E200G_XCVR_SPEED_MAP_25E2X0_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x0_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x0_tx_xcvr_width == E200G_XCVR_SPEED_MAP_25E2X0_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x0_txrx_channel_operation == E200G_XCVR_SPEED_MAP_25E2X0_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x0_txrx_line_encoding_type == E200G_XCVR_SPEED_MAP_25E2X0_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x0_xcvr_mode == E200G_XCVR_SPEED_MAP_25E2X0_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x10_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x10_duplex_mode == E200G_XCVR_SPEED_MAP_25E2X10_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x10_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x10_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x10_rx_master_bond_chnl == E200G_XCVR_SPEED_MAP_25E2X10_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x10_rx_protocol == E200G_XCVR_SPEED_MAP_25E2X10_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x10_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x10_rx_xcvr_width == E200G_XCVR_SPEED_MAP_25E2X10_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x10_speed_bucket == E200G_XCVR_SPEED_MAP_25E2X10_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x10_sys_clk_src == E200G_XCVR_SPEED_MAP_25E2X10_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x10_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x10_tx_master_bond_chnl == E200G_XCVR_SPEED_MAP_25E2X10_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x10_tx_protocol == E200G_XCVR_SPEED_MAP_25E2X10_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x10_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x10_tx_xcvr_width == E200G_XCVR_SPEED_MAP_25E2X10_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x10_txrx_channel_operation == E200G_XCVR_SPEED_MAP_25E2X10_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x10_txrx_line_encoding_type == E200G_XCVR_SPEED_MAP_25E2X10_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x10_xcvr_mode == E200G_XCVR_SPEED_MAP_25E2X10_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x11_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x11_duplex_mode == E200G_XCVR_SPEED_MAP_25E2X11_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x11_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x11_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x11_rx_master_bond_chnl == E200G_XCVR_SPEED_MAP_25E2X11_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x11_rx_protocol == E200G_XCVR_SPEED_MAP_25E2X11_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x11_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x11_rx_xcvr_width == E200G_XCVR_SPEED_MAP_25E2X11_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x11_speed_bucket == E200G_XCVR_SPEED_MAP_25E2X11_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x11_sys_clk_src == E200G_XCVR_SPEED_MAP_25E2X11_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x11_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x11_tx_master_bond_chnl == E200G_XCVR_SPEED_MAP_25E2X11_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x11_tx_protocol == E200G_XCVR_SPEED_MAP_25E2X11_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x11_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x11_tx_xcvr_width == E200G_XCVR_SPEED_MAP_25E2X11_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x11_txrx_channel_operation == E200G_XCVR_SPEED_MAP_25E2X11_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x11_txrx_line_encoding_type == E200G_XCVR_SPEED_MAP_25E2X11_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x11_xcvr_mode == E200G_XCVR_SPEED_MAP_25E2X11_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x12_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x12_duplex_mode == E200G_XCVR_SPEED_MAP_25E2X12_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x12_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x12_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x12_rx_master_bond_chnl == E200G_XCVR_SPEED_MAP_25E2X12_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x12_rx_protocol == E200G_XCVR_SPEED_MAP_25E2X12_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x12_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x12_rx_xcvr_width == E200G_XCVR_SPEED_MAP_25E2X12_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x12_speed_bucket == E200G_XCVR_SPEED_MAP_25E2X12_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x12_sys_clk_src == E200G_XCVR_SPEED_MAP_25E2X12_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x12_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x12_tx_master_bond_chnl == E200G_XCVR_SPEED_MAP_25E2X12_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x12_tx_protocol == E200G_XCVR_SPEED_MAP_25E2X12_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x12_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x12_tx_xcvr_width == E200G_XCVR_SPEED_MAP_25E2X12_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x12_txrx_channel_operation == E200G_XCVR_SPEED_MAP_25E2X12_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x12_txrx_line_encoding_type == E200G_XCVR_SPEED_MAP_25E2X12_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x12_xcvr_mode == E200G_XCVR_SPEED_MAP_25E2X12_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x13_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x13_duplex_mode == E200G_XCVR_SPEED_MAP_25E2X13_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x13_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x13_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x13_rx_master_bond_chnl == E200G_XCVR_SPEED_MAP_25E2X13_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x13_rx_protocol == E200G_XCVR_SPEED_MAP_25E2X13_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x13_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x13_rx_xcvr_width == E200G_XCVR_SPEED_MAP_25E2X13_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x13_speed_bucket == E200G_XCVR_SPEED_MAP_25E2X13_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x13_sys_clk_src == E200G_XCVR_SPEED_MAP_25E2X13_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x13_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x13_tx_master_bond_chnl == E200G_XCVR_SPEED_MAP_25E2X13_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x13_tx_protocol == E200G_XCVR_SPEED_MAP_25E2X13_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x13_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x13_tx_xcvr_width == E200G_XCVR_SPEED_MAP_25E2X13_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x13_txrx_channel_operation == E200G_XCVR_SPEED_MAP_25E2X13_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x13_txrx_line_encoding_type == E200G_XCVR_SPEED_MAP_25E2X13_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x13_xcvr_mode == E200G_XCVR_SPEED_MAP_25E2X13_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x14_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x14_duplex_mode == E200G_XCVR_SPEED_MAP_25E2X14_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x14_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x14_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x14_rx_master_bond_chnl == E200G_XCVR_SPEED_MAP_25E2X14_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x14_rx_protocol == E200G_XCVR_SPEED_MAP_25E2X14_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x14_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x14_rx_xcvr_width == E200G_XCVR_SPEED_MAP_25E2X14_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x14_speed_bucket == E200G_XCVR_SPEED_MAP_25E2X14_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x14_sys_clk_src == E200G_XCVR_SPEED_MAP_25E2X14_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x14_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x14_tx_master_bond_chnl == E200G_XCVR_SPEED_MAP_25E2X14_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x14_tx_protocol == E200G_XCVR_SPEED_MAP_25E2X14_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x14_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x14_tx_xcvr_width == E200G_XCVR_SPEED_MAP_25E2X14_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x14_txrx_channel_operation == E200G_XCVR_SPEED_MAP_25E2X14_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x14_txrx_line_encoding_type == E200G_XCVR_SPEED_MAP_25E2X14_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x14_xcvr_mode == E200G_XCVR_SPEED_MAP_25E2X14_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x15_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x15_duplex_mode == E200G_XCVR_SPEED_MAP_25E2X15_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x15_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x15_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x15_rx_master_bond_chnl == E200G_XCVR_SPEED_MAP_25E2X15_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x15_rx_protocol == E200G_XCVR_SPEED_MAP_25E2X15_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x15_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x15_rx_xcvr_width == E200G_XCVR_SPEED_MAP_25E2X15_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x15_speed_bucket == E200G_XCVR_SPEED_MAP_25E2X15_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x15_sys_clk_src == E200G_XCVR_SPEED_MAP_25E2X15_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x15_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x15_tx_master_bond_chnl == E200G_XCVR_SPEED_MAP_25E2X15_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x15_tx_protocol == E200G_XCVR_SPEED_MAP_25E2X15_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x15_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x15_tx_xcvr_width == E200G_XCVR_SPEED_MAP_25E2X15_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x15_txrx_channel_operation == E200G_XCVR_SPEED_MAP_25E2X15_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x15_txrx_line_encoding_type == E200G_XCVR_SPEED_MAP_25E2X15_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x15_xcvr_mode == E200G_XCVR_SPEED_MAP_25E2X15_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x1_duplex_mode == E200G_XCVR_SPEED_MAP_25E2X1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x1_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x1_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x1_rx_master_bond_chnl == E200G_XCVR_SPEED_MAP_25E2X1_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x1_rx_protocol == E200G_XCVR_SPEED_MAP_25E2X1_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x1_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x1_rx_xcvr_width == E200G_XCVR_SPEED_MAP_25E2X1_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x1_speed_bucket == E200G_XCVR_SPEED_MAP_25E2X1_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x1_sys_clk_src == E200G_XCVR_SPEED_MAP_25E2X1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x1_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x1_tx_master_bond_chnl == E200G_XCVR_SPEED_MAP_25E2X1_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x1_tx_protocol == E200G_XCVR_SPEED_MAP_25E2X1_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x1_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x1_tx_xcvr_width == E200G_XCVR_SPEED_MAP_25E2X1_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x1_txrx_channel_operation == E200G_XCVR_SPEED_MAP_25E2X1_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x1_txrx_line_encoding_type == E200G_XCVR_SPEED_MAP_25E2X1_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x1_xcvr_mode == E200G_XCVR_SPEED_MAP_25E2X1_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x2_duplex_mode == E200G_XCVR_SPEED_MAP_25E2X2_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x2_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x2_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x2_rx_master_bond_chnl == E200G_XCVR_SPEED_MAP_25E2X2_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x2_rx_protocol == E200G_XCVR_SPEED_MAP_25E2X2_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x2_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x2_rx_xcvr_width == E200G_XCVR_SPEED_MAP_25E2X2_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x2_speed_bucket == E200G_XCVR_SPEED_MAP_25E2X2_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x2_sys_clk_src == E200G_XCVR_SPEED_MAP_25E2X2_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x2_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x2_tx_master_bond_chnl == E200G_XCVR_SPEED_MAP_25E2X2_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x2_tx_protocol == E200G_XCVR_SPEED_MAP_25E2X2_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x2_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x2_tx_xcvr_width == E200G_XCVR_SPEED_MAP_25E2X2_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x2_txrx_channel_operation == E200G_XCVR_SPEED_MAP_25E2X2_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x2_txrx_line_encoding_type == E200G_XCVR_SPEED_MAP_25E2X2_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x2_xcvr_mode == E200G_XCVR_SPEED_MAP_25E2X2_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x3_duplex_mode == E200G_XCVR_SPEED_MAP_25E2X3_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x3_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x3_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x3_rx_master_bond_chnl == E200G_XCVR_SPEED_MAP_25E2X3_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x3_rx_protocol == E200G_XCVR_SPEED_MAP_25E2X3_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x3_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x3_rx_xcvr_width == E200G_XCVR_SPEED_MAP_25E2X3_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x3_speed_bucket == E200G_XCVR_SPEED_MAP_25E2X3_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x3_sys_clk_src == E200G_XCVR_SPEED_MAP_25E2X3_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x3_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x3_tx_master_bond_chnl == E200G_XCVR_SPEED_MAP_25E2X3_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x3_tx_protocol == E200G_XCVR_SPEED_MAP_25E2X3_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x3_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x3_tx_xcvr_width == E200G_XCVR_SPEED_MAP_25E2X3_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x3_txrx_channel_operation == E200G_XCVR_SPEED_MAP_25E2X3_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x3_txrx_line_encoding_type == E200G_XCVR_SPEED_MAP_25E2X3_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x3_xcvr_mode == E200G_XCVR_SPEED_MAP_25E2X3_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x4_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x4_duplex_mode == E200G_XCVR_SPEED_MAP_25E2X4_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x4_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x4_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x4_rx_master_bond_chnl == E200G_XCVR_SPEED_MAP_25E2X4_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x4_rx_protocol == E200G_XCVR_SPEED_MAP_25E2X4_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x4_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x4_rx_xcvr_width == E200G_XCVR_SPEED_MAP_25E2X4_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x4_speed_bucket == E200G_XCVR_SPEED_MAP_25E2X4_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x4_sys_clk_src == E200G_XCVR_SPEED_MAP_25E2X4_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x4_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x4_tx_master_bond_chnl == E200G_XCVR_SPEED_MAP_25E2X4_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x4_tx_protocol == E200G_XCVR_SPEED_MAP_25E2X4_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x4_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x4_tx_xcvr_width == E200G_XCVR_SPEED_MAP_25E2X4_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x4_txrx_channel_operation == E200G_XCVR_SPEED_MAP_25E2X4_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x4_txrx_line_encoding_type == E200G_XCVR_SPEED_MAP_25E2X4_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x4_xcvr_mode == E200G_XCVR_SPEED_MAP_25E2X4_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x5_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x5_duplex_mode == E200G_XCVR_SPEED_MAP_25E2X5_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x5_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x5_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x5_rx_master_bond_chnl == E200G_XCVR_SPEED_MAP_25E2X5_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x5_rx_protocol == E200G_XCVR_SPEED_MAP_25E2X5_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x5_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x5_rx_xcvr_width == E200G_XCVR_SPEED_MAP_25E2X5_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x5_speed_bucket == E200G_XCVR_SPEED_MAP_25E2X5_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x5_sys_clk_src == E200G_XCVR_SPEED_MAP_25E2X5_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x5_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x5_tx_master_bond_chnl == E200G_XCVR_SPEED_MAP_25E2X5_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x5_tx_protocol == E200G_XCVR_SPEED_MAP_25E2X5_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x5_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x5_tx_xcvr_width == E200G_XCVR_SPEED_MAP_25E2X5_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x5_txrx_channel_operation == E200G_XCVR_SPEED_MAP_25E2X5_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x5_txrx_line_encoding_type == E200G_XCVR_SPEED_MAP_25E2X5_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x5_xcvr_mode == E200G_XCVR_SPEED_MAP_25E2X5_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x6_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x6_duplex_mode == E200G_XCVR_SPEED_MAP_25E2X6_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x6_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x6_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x6_rx_master_bond_chnl == E200G_XCVR_SPEED_MAP_25E2X6_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x6_rx_protocol == E200G_XCVR_SPEED_MAP_25E2X6_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x6_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x6_rx_xcvr_width == E200G_XCVR_SPEED_MAP_25E2X6_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x6_speed_bucket == E200G_XCVR_SPEED_MAP_25E2X6_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x6_sys_clk_src == E200G_XCVR_SPEED_MAP_25E2X6_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x6_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x6_tx_master_bond_chnl == E200G_XCVR_SPEED_MAP_25E2X6_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x6_tx_protocol == E200G_XCVR_SPEED_MAP_25E2X6_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x6_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x6_tx_xcvr_width == E200G_XCVR_SPEED_MAP_25E2X6_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x6_txrx_channel_operation == E200G_XCVR_SPEED_MAP_25E2X6_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x6_txrx_line_encoding_type == E200G_XCVR_SPEED_MAP_25E2X6_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x6_xcvr_mode == E200G_XCVR_SPEED_MAP_25E2X6_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x7_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x7_duplex_mode == E200G_XCVR_SPEED_MAP_25E2X7_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x7_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x7_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x7_rx_master_bond_chnl == E200G_XCVR_SPEED_MAP_25E2X7_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x7_rx_protocol == E200G_XCVR_SPEED_MAP_25E2X7_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x7_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x7_rx_xcvr_width == E200G_XCVR_SPEED_MAP_25E2X7_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x7_speed_bucket == E200G_XCVR_SPEED_MAP_25E2X7_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x7_sys_clk_src == E200G_XCVR_SPEED_MAP_25E2X7_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x7_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x7_tx_master_bond_chnl == E200G_XCVR_SPEED_MAP_25E2X7_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x7_tx_protocol == E200G_XCVR_SPEED_MAP_25E2X7_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x7_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x7_tx_xcvr_width == E200G_XCVR_SPEED_MAP_25E2X7_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x7_txrx_channel_operation == E200G_XCVR_SPEED_MAP_25E2X7_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x7_txrx_line_encoding_type == E200G_XCVR_SPEED_MAP_25E2X7_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x7_xcvr_mode == E200G_XCVR_SPEED_MAP_25E2X7_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x8_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x8_duplex_mode == E200G_XCVR_SPEED_MAP_25E2X8_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x8_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x8_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x8_rx_master_bond_chnl == E200G_XCVR_SPEED_MAP_25E2X8_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x8_rx_protocol == E200G_XCVR_SPEED_MAP_25E2X8_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x8_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x8_rx_xcvr_width == E200G_XCVR_SPEED_MAP_25E2X8_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x8_speed_bucket == E200G_XCVR_SPEED_MAP_25E2X8_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x8_sys_clk_src == E200G_XCVR_SPEED_MAP_25E2X8_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x8_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x8_tx_master_bond_chnl == E200G_XCVR_SPEED_MAP_25E2X8_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x8_tx_protocol == E200G_XCVR_SPEED_MAP_25E2X8_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x8_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x8_tx_xcvr_width == E200G_XCVR_SPEED_MAP_25E2X8_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x8_txrx_channel_operation == E200G_XCVR_SPEED_MAP_25E2X8_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x8_txrx_line_encoding_type == E200G_XCVR_SPEED_MAP_25E2X8_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x8_xcvr_mode == E200G_XCVR_SPEED_MAP_25E2X8_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x9_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x9_duplex_mode == E200G_XCVR_SPEED_MAP_25E2X9_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x9_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x9_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x9_rx_master_bond_chnl == E200G_XCVR_SPEED_MAP_25E2X9_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x9_rx_protocol == E200G_XCVR_SPEED_MAP_25E2X9_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x9_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x9_rx_xcvr_width == E200G_XCVR_SPEED_MAP_25E2X9_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x9_speed_bucket == E200G_XCVR_SPEED_MAP_25E2X9_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x9_sys_clk_src == E200G_XCVR_SPEED_MAP_25E2X9_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x9_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x9_tx_master_bond_chnl == E200G_XCVR_SPEED_MAP_25E2X9_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x9_tx_protocol == E200G_XCVR_SPEED_MAP_25E2X9_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x9_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x9_tx_xcvr_width == E200G_XCVR_SPEED_MAP_25E2X9_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x9_txrx_channel_operation == E200G_XCVR_SPEED_MAP_25E2X9_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x9_txrx_line_encoding_type == E200G_XCVR_SPEED_MAP_25E2X9_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_25e2x9_xcvr_mode == E200G_XCVR_SPEED_MAP_25E2X9_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x0_duplex_mode == E200G_XCVR_SPEED_MAP_56E2X0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x0_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x0_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x0_rx_master_bond_chnl == E200G_XCVR_SPEED_MAP_56E2X0_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x0_rx_protocol == E200G_XCVR_SPEED_MAP_56E2X0_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x0_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x0_rx_xcvr_width == E200G_XCVR_SPEED_MAP_56E2X0_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x0_speed_bucket == E200G_XCVR_SPEED_MAP_56E2X0_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x0_sys_clk_src == E200G_XCVR_SPEED_MAP_56E2X0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x0_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x0_tx_master_bond_chnl == E200G_XCVR_SPEED_MAP_56E2X0_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x0_tx_protocol == E200G_XCVR_SPEED_MAP_56E2X0_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x0_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x0_tx_xcvr_width == E200G_XCVR_SPEED_MAP_56E2X0_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x0_txrx_channel_operation == E200G_XCVR_SPEED_MAP_56E2X0_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x0_txrx_line_encoding_type == E200G_XCVR_SPEED_MAP_56E2X0_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x0_xcvr_mode == E200G_XCVR_SPEED_MAP_56E2X0_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x1_duplex_mode == E200G_XCVR_SPEED_MAP_56E2X1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x1_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x1_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x1_rx_master_bond_chnl == E200G_XCVR_SPEED_MAP_56E2X1_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x1_rx_protocol == E200G_XCVR_SPEED_MAP_56E2X1_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x1_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x1_rx_xcvr_width == E200G_XCVR_SPEED_MAP_56E2X1_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x1_speed_bucket == E200G_XCVR_SPEED_MAP_56E2X1_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x1_sys_clk_src == E200G_XCVR_SPEED_MAP_56E2X1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x1_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x1_tx_master_bond_chnl == E200G_XCVR_SPEED_MAP_56E2X1_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x1_tx_protocol == E200G_XCVR_SPEED_MAP_56E2X1_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x1_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x1_tx_xcvr_width == E200G_XCVR_SPEED_MAP_56E2X1_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x1_txrx_channel_operation == E200G_XCVR_SPEED_MAP_56E2X1_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x1_txrx_line_encoding_type == E200G_XCVR_SPEED_MAP_56E2X1_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x1_xcvr_mode == E200G_XCVR_SPEED_MAP_56E2X1_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x2_duplex_mode == E200G_XCVR_SPEED_MAP_56E2X2_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x2_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x2_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x2_rx_master_bond_chnl == E200G_XCVR_SPEED_MAP_56E2X2_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x2_rx_protocol == E200G_XCVR_SPEED_MAP_56E2X2_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x2_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x2_rx_xcvr_width == E200G_XCVR_SPEED_MAP_56E2X2_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x2_speed_bucket == E200G_XCVR_SPEED_MAP_56E2X2_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x2_sys_clk_src == E200G_XCVR_SPEED_MAP_56E2X2_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x2_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x2_tx_master_bond_chnl == E200G_XCVR_SPEED_MAP_56E2X2_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x2_tx_protocol == E200G_XCVR_SPEED_MAP_56E2X2_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x2_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x2_tx_xcvr_width == E200G_XCVR_SPEED_MAP_56E2X2_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x2_txrx_channel_operation == E200G_XCVR_SPEED_MAP_56E2X2_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x2_txrx_line_encoding_type == E200G_XCVR_SPEED_MAP_56E2X2_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x2_xcvr_mode == E200G_XCVR_SPEED_MAP_56E2X2_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x3_duplex_mode == E200G_XCVR_SPEED_MAP_56E2X3_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x3_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x3_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x3_rx_master_bond_chnl == E200G_XCVR_SPEED_MAP_56E2X3_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x3_rx_protocol == E200G_XCVR_SPEED_MAP_56E2X3_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x3_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x3_rx_xcvr_width == E200G_XCVR_SPEED_MAP_56E2X3_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x3_speed_bucket == E200G_XCVR_SPEED_MAP_56E2X3_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x3_sys_clk_src == E200G_XCVR_SPEED_MAP_56E2X3_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x3_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x3_tx_master_bond_chnl == E200G_XCVR_SPEED_MAP_56E2X3_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x3_tx_protocol == E200G_XCVR_SPEED_MAP_56E2X3_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x3_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x3_tx_xcvr_width == E200G_XCVR_SPEED_MAP_56E2X3_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x3_txrx_channel_operation == E200G_XCVR_SPEED_MAP_56E2X3_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x3_txrx_line_encoding_type == E200G_XCVR_SPEED_MAP_56E2X3_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x3_xcvr_mode == E200G_XCVR_SPEED_MAP_56E2X3_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x4_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x4_duplex_mode == E200G_XCVR_SPEED_MAP_56E2X4_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x4_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x4_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x4_rx_master_bond_chnl == E200G_XCVR_SPEED_MAP_56E2X4_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x4_rx_protocol == E200G_XCVR_SPEED_MAP_56E2X4_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x4_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x4_rx_xcvr_width == E200G_XCVR_SPEED_MAP_56E2X4_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x4_speed_bucket == E200G_XCVR_SPEED_MAP_56E2X4_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x4_sys_clk_src == E200G_XCVR_SPEED_MAP_56E2X4_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x4_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x4_tx_master_bond_chnl == E200G_XCVR_SPEED_MAP_56E2X4_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x4_tx_protocol == E200G_XCVR_SPEED_MAP_56E2X4_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x4_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x4_tx_xcvr_width == E200G_XCVR_SPEED_MAP_56E2X4_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x4_txrx_channel_operation == E200G_XCVR_SPEED_MAP_56E2X4_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x4_txrx_line_encoding_type == E200G_XCVR_SPEED_MAP_56E2X4_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x4_xcvr_mode == E200G_XCVR_SPEED_MAP_56E2X4_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x5_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x5_duplex_mode == E200G_XCVR_SPEED_MAP_56E2X5_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x5_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x5_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x5_rx_master_bond_chnl == E200G_XCVR_SPEED_MAP_56E2X5_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x5_rx_protocol == E200G_XCVR_SPEED_MAP_56E2X5_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x5_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x5_rx_xcvr_width == E200G_XCVR_SPEED_MAP_56E2X5_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x5_speed_bucket == E200G_XCVR_SPEED_MAP_56E2X5_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x5_sys_clk_src == E200G_XCVR_SPEED_MAP_56E2X5_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x5_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x5_tx_master_bond_chnl == E200G_XCVR_SPEED_MAP_56E2X5_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x5_tx_protocol == E200G_XCVR_SPEED_MAP_56E2X5_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x5_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x5_tx_xcvr_width == E200G_XCVR_SPEED_MAP_56E2X5_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x5_txrx_channel_operation == E200G_XCVR_SPEED_MAP_56E2X5_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x5_txrx_line_encoding_type == E200G_XCVR_SPEED_MAP_56E2X5_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x5_xcvr_mode == E200G_XCVR_SPEED_MAP_56E2X5_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x6_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x6_duplex_mode == E200G_XCVR_SPEED_MAP_56E2X6_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x6_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x6_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x6_rx_master_bond_chnl == E200G_XCVR_SPEED_MAP_56E2X6_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x6_rx_protocol == E200G_XCVR_SPEED_MAP_56E2X6_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x6_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x6_rx_xcvr_width == E200G_XCVR_SPEED_MAP_56E2X6_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x6_speed_bucket == E200G_XCVR_SPEED_MAP_56E2X6_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x6_sys_clk_src == E200G_XCVR_SPEED_MAP_56E2X6_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x6_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x6_tx_master_bond_chnl == E200G_XCVR_SPEED_MAP_56E2X6_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x6_tx_protocol == E200G_XCVR_SPEED_MAP_56E2X6_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x6_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x6_tx_xcvr_width == E200G_XCVR_SPEED_MAP_56E2X6_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x6_txrx_channel_operation == E200G_XCVR_SPEED_MAP_56E2X6_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x6_txrx_line_encoding_type == E200G_XCVR_SPEED_MAP_56E2X6_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x6_xcvr_mode == E200G_XCVR_SPEED_MAP_56E2X6_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x7_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x7_duplex_mode == E200G_XCVR_SPEED_MAP_56E2X7_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x7_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x7_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x7_rx_master_bond_chnl == E200G_XCVR_SPEED_MAP_56E2X7_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x7_rx_protocol == E200G_XCVR_SPEED_MAP_56E2X7_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x7_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x7_rx_xcvr_width == E200G_XCVR_SPEED_MAP_56E2X7_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x7_speed_bucket == E200G_XCVR_SPEED_MAP_56E2X7_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x7_sys_clk_src == E200G_XCVR_SPEED_MAP_56E2X7_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x7_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x7_tx_master_bond_chnl == E200G_XCVR_SPEED_MAP_56E2X7_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x7_tx_protocol == E200G_XCVR_SPEED_MAP_56E2X7_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x7_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x7_tx_xcvr_width == E200G_XCVR_SPEED_MAP_56E2X7_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x7_txrx_channel_operation == E200G_XCVR_SPEED_MAP_56E2X7_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x7_txrx_line_encoding_type == E200G_XCVR_SPEED_MAP_56E2X7_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.e200g_xcvr_speed_map_56e2x7_xcvr_mode == E200G_XCVR_SPEED_MAP_56E2X7_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.map_ux0 == MAP_UX0_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.map_ux1 == MAP_UX1_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.map_ux2 == MAP_UX2_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.map_ux3 == MAP_UX3_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.map_ux4 == MAP_UX4_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.map_ux5 == MAP_UX5_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.map_ux6 == MAP_UX6_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.map_ux7 == MAP_UX7_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.rx_transfer_clk0_adapt_rc_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.rx_transfer_clk1_adapt_rc_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.rx_transfer_clk2_adapt_rc_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.rx_transfer_clk3_adapt_rc_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.rx_transfer_clk4_adapt_rc_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.rx_transfer_clk5_adapt_rc_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.rx_transfer_clk6_adapt_rc_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.rx_transfer_clk7_adapt_rc_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.sys_pll0_div1_adapt_rc_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.sys_pll0_div2_adapt_rc_clk_hz == 37'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.sys_pll1_div1_adapt_rc_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.sys_pll1_div2_adapt_rc_clk_hz == 37'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.sys_pll2_div1_adapt_rc_clk_hz == 37'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.sys_pll2_div2_adapt_rc_clk_hz == 37'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.topo_supports_barak == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.topo_supports_pcie == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.topo_supports_ptp == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.topology == UX16E400GPTP_XX_DISABLED_XX_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.transfer_clk0_adapt_rc_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.transfer_clk1_adapt_rc_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.transfer_clk2_adapt_rc_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.transfer_clk3_adapt_rc_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.transfer_clk4_adapt_rc_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.transfer_clk5_adapt_rc_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.transfer_clk6_adapt_rc_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.transfer_clk7_adapt_rc_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux0_return_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux0_rx_user_xcvr_rc_clk_hz == 37'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux0_rxword_xcvr_rc_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux0_tx_user_xcvr_rc_clk1_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux0_tx_user_xcvr_rc_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux0_txword_xcvr_rc_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux1_return_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux1_rx_user_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux1_rxword_xcvr_rc_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux1_tx_user_xcvr_rc_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux1_tx_user_xcvr_rc_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux1_txword_xcvr_rc_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux2_return_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux2_rx_user_xcvr_rc_clk_hz == 37'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux2_rxword_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux2_tx_user_xcvr_rc_clk1_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux2_tx_user_xcvr_rc_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux2_txword_xcvr_rc_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux3_return_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux3_rx_user_xcvr_rc_clk_hz == 37'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux3_rxword_xcvr_rc_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux3_tx_user_xcvr_rc_clk1_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux3_tx_user_xcvr_rc_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux3_txword_xcvr_rc_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux4_return_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux4_rx_user_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux4_rxword_xcvr_rc_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux4_tx_user_xcvr_rc_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux4_tx_user_xcvr_rc_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux4_txword_xcvr_rc_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux5_return_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux5_rx_user_xcvr_rc_clk_hz == 37'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux5_rxword_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux5_tx_user_xcvr_rc_clk1_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux5_tx_user_xcvr_rc_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux5_txword_xcvr_rc_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux6_return_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux6_rx_user_xcvr_rc_clk_hz == 37'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux6_rxword_xcvr_rc_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux6_tx_user_xcvr_rc_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux6_tx_user_xcvr_rc_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux6_txword_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux7_return_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux7_rx_user_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux7_rxword_xcvr_rc_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux7_tx_user_xcvr_rc_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux7_tx_user_xcvr_rc_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.ux7_txword_xcvr_rc_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.xcvr_select_25e2x0 == XCVR_SELECT_25E2X0_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.xcvr_select_25e2x1 == XCVR_SELECT_25E2X1_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.xcvr_select_25e2x2 == XCVR_SELECT_25E2X2_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.xcvr_select_25e2x3 == XCVR_SELECT_25E2X3_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.xcvr_select_25e2x4 == XCVR_SELECT_25E2X4_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.xcvr_select_25e2x5 == XCVR_SELECT_25E2X5_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.xcvr_select_25e2x6 == XCVR_SELECT_25E2X6_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.xcvr_select_25e2x7 == XCVR_SELECT_25E2X7_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.xcvr_select_56e2x0 == XCVR_SELECT_56E2X0_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.xcvr_select_56e2x1 == XCVR_SELECT_56E2X1_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.xcvr_select_56e2x2 == XCVR_SELECT_56E2X2_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.xcvr_select_56e2x3 == XCVR_SELECT_56E2X3_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_0_aibif_data_valid == E200G_100G_0_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_0_duplex_mode == E200G_100G_0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_0_fec_mode == E200G_100G_0_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_0_lpbk_mode == E200G_100G_0_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_0_pcs_ber_mon_mode == E200G_100G_0_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_0_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_0_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_0_rx_fec_enable == E200G_100G_0_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_0_rx_pcs_mode == E200G_100G_0_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_0_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_0_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_0_rx_primary_use == E200G_100G_0_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_0_rx_system_bonding == E200G_100G_0_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_0_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_0_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_0_sup_mode == E200G_100G_0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_0_sys_clk_src == E200G_100G_0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_0_tx_aib_if_fifo_mode == E200G_100G_0_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_0_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_0_tx_fec_enable == E200G_100G_0_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_0_tx_pcs_mode == E200G_100G_0_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_0_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_0_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_0_tx_primary_use == E200G_100G_0_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_0_tx_system_bonding == E200G_100G_0_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_0_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_1_aibif_data_valid == E200G_100G_1_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_1_duplex_mode == E200G_100G_1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_1_fec_mode == E200G_100G_1_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_1_lpbk_mode == E200G_100G_1_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_1_pcs_ber_mon_mode == E200G_100G_1_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_1_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_1_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_1_rx_fec_enable == E200G_100G_1_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_1_rx_pcs_mode == E200G_100G_1_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_1_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_1_rx_primary_use == E200G_100G_1_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_1_rx_system_bonding == E200G_100G_1_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_1_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_1_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_1_sup_mode == E200G_100G_1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_1_sys_clk_src == E200G_100G_1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_1_tx_aib_if_fifo_mode == E200G_100G_1_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_1_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_1_tx_fec_enable == E200G_100G_1_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_1_tx_pcs_mode == E200G_100G_1_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_1_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_1_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_1_tx_primary_use == E200G_100G_1_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_1_tx_system_bonding == E200G_100G_1_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_100g_1_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_0_aibif_data_valid == E200G_150G_0_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_0_duplex_mode == E200G_150G_0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_0_fec_mode == E200G_150G_0_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_0_lpbk_mode == E200G_150G_0_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_0_pcs_ber_mon_mode == E200G_150G_0_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_0_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_0_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_0_rx_fec_enable == E200G_150G_0_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_0_rx_pcs_mode == E200G_150G_0_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_0_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_0_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_0_rx_primary_use == E200G_150G_0_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_0_rx_system_bonding == E200G_150G_0_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_0_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_0_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_0_sup_mode == E200G_150G_0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_0_sys_clk_src == E200G_150G_0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_0_tx_aib_if_fifo_mode == E200G_150G_0_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_0_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_0_tx_fec_enable == E200G_150G_0_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_0_tx_pcs_mode == E200G_150G_0_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_0_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_0_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_0_tx_primary_use == E200G_150G_0_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_0_tx_system_bonding == E200G_150G_0_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_0_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_1_aibif_data_valid == E200G_150G_1_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_1_duplex_mode == E200G_150G_1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_1_fec_mode == E200G_150G_1_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_1_lpbk_mode == E200G_150G_1_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_1_pcs_ber_mon_mode == E200G_150G_1_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_1_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_1_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_1_rx_fec_enable == E200G_150G_1_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_1_rx_pcs_mode == E200G_150G_1_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_1_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_1_rx_primary_use == E200G_150G_1_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_1_rx_system_bonding == E200G_150G_1_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_1_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_1_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_1_sup_mode == E200G_150G_1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_1_sys_clk_src == E200G_150G_1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_1_tx_aib_if_fifo_mode == E200G_150G_1_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_1_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_1_tx_fec_enable == E200G_150G_1_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_1_tx_pcs_mode == E200G_150G_1_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_1_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_1_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_1_tx_primary_use == E200G_150G_1_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_1_tx_system_bonding == E200G_150G_1_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_150g_1_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_200g_aibif_data_valid == E200G_200G_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_200g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_200g_duplex_mode == E200G_200G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_200g_fec_mode == E200G_200G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_200g_lpbk_mode == E200G_200G_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_200g_pcs_ber_mon_mode == E200G_200G_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_200g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_200g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_200g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_200g_rx_fec_enable == E200G_200G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_200g_rx_pcs_mode == E200G_200G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_200g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_200g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_200g_rx_primary_use == E200G_200G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_200g_rx_system_bonding == E200G_200G_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_200g_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_200g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_200g_sup_mode == E200G_200G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_200g_sys_clk_src == E200G_200G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_200g_tx_aib_if_fifo_mode == E200G_200G_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_200g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_200g_tx_fec_enable == E200G_200G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_200g_tx_pcs_mode == E200G_200G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_200g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_200g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_200g_tx_primary_use == E200G_200G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_200g_tx_system_bonding == E200G_200G_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_200g_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_0_aibif_data_valid == E200G_25G_0_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_0_duplex_mode == E200G_25G_0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_0_fec_mode == E200G_25G_0_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_0_fec_spec == E200G_25G_0_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_0_lpbk_mode == E200G_25G_0_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_0_pcs_ber_mon_mode == E200G_25G_0_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_0_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_0_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_0_rx_fec_enable == E200G_25G_0_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_0_rx_pcs_mode == E200G_25G_0_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_0_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_0_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_0_rx_primary_use == E200G_25G_0_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_0_rx_system_bonding == E200G_25G_0_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_0_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_0_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_0_sup_mode == E200G_25G_0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_0_sys_clk_src == E200G_25G_0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_0_tx_aib_if_fifo_mode == E200G_25G_0_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_0_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_0_tx_fec_enable == E200G_25G_0_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_0_tx_pcs_mode == E200G_25G_0_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_0_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_0_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_0_tx_primary_use == E200G_25G_0_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_0_tx_system_bonding == E200G_25G_0_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_0_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_1_aibif_data_valid == E200G_25G_1_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_1_duplex_mode == E200G_25G_1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_1_fec_mode == E200G_25G_1_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_1_fec_spec == E200G_25G_1_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_1_lpbk_mode == E200G_25G_1_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_1_pcs_ber_mon_mode == E200G_25G_1_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_1_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_1_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_1_rx_fec_enable == E200G_25G_1_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_1_rx_pcs_mode == E200G_25G_1_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_1_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_1_rx_primary_use == E200G_25G_1_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_1_rx_system_bonding == E200G_25G_1_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_1_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_1_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_1_sup_mode == E200G_25G_1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_1_sys_clk_src == E200G_25G_1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_1_tx_aib_if_fifo_mode == E200G_25G_1_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_1_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_1_tx_fec_enable == E200G_25G_1_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_1_tx_pcs_mode == E200G_25G_1_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_1_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_1_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_1_tx_primary_use == E200G_25G_1_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_1_tx_system_bonding == E200G_25G_1_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_1_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_2_aibif_data_valid == E200G_25G_2_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_2_duplex_mode == E200G_25G_2_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_2_fec_mode == E200G_25G_2_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_2_fec_spec == E200G_25G_2_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_2_lpbk_mode == E200G_25G_2_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_2_pcs_ber_mon_mode == E200G_25G_2_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_2_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_2_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_2_rx_fec_enable == E200G_25G_2_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_2_rx_pcs_mode == E200G_25G_2_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_2_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_2_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_2_rx_primary_use == E200G_25G_2_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_2_rx_system_bonding == E200G_25G_2_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_2_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_2_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_2_sup_mode == E200G_25G_2_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_2_sys_clk_src == E200G_25G_2_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_2_tx_aib_if_fifo_mode == E200G_25G_2_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_2_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_2_tx_fec_enable == E200G_25G_2_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_2_tx_pcs_mode == E200G_25G_2_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_2_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_2_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_2_tx_primary_use == E200G_25G_2_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_2_tx_system_bonding == E200G_25G_2_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_2_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_3_aibif_data_valid == E200G_25G_3_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_3_duplex_mode == E200G_25G_3_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_3_fec_mode == E200G_25G_3_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_3_fec_spec == E200G_25G_3_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_3_lpbk_mode == E200G_25G_3_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_3_pcs_ber_mon_mode == E200G_25G_3_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_3_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_3_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_3_rx_fec_enable == E200G_25G_3_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_3_rx_pcs_mode == E200G_25G_3_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_3_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_3_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_3_rx_primary_use == E200G_25G_3_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_3_rx_system_bonding == E200G_25G_3_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_3_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_3_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_3_sup_mode == E200G_25G_3_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_3_sys_clk_src == E200G_25G_3_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_3_tx_aib_if_fifo_mode == E200G_25G_3_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_3_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_3_tx_fec_enable == E200G_25G_3_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_3_tx_pcs_mode == E200G_25G_3_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_3_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_3_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_3_tx_primary_use == E200G_25G_3_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_3_tx_system_bonding == E200G_25G_3_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_3_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_4_aibif_data_valid == E200G_25G_4_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_4_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_4_duplex_mode == E200G_25G_4_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_4_fec_mode == E200G_25G_4_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_4_fec_spec == E200G_25G_4_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_4_lpbk_mode == E200G_25G_4_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_4_pcs_ber_mon_mode == E200G_25G_4_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_4_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_4_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_4_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_4_rx_fec_enable == E200G_25G_4_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_4_rx_pcs_mode == E200G_25G_4_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_4_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_4_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_4_rx_primary_use == E200G_25G_4_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_4_rx_system_bonding == E200G_25G_4_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_4_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_4_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_4_sup_mode == E200G_25G_4_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_4_sys_clk_src == E200G_25G_4_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_4_tx_aib_if_fifo_mode == E200G_25G_4_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_4_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_4_tx_fec_enable == E200G_25G_4_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_4_tx_pcs_mode == E200G_25G_4_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_4_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_4_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_4_tx_primary_use == E200G_25G_4_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_4_tx_system_bonding == E200G_25G_4_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_4_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_5_aibif_data_valid == E200G_25G_5_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_5_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_5_duplex_mode == E200G_25G_5_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_5_fec_mode == E200G_25G_5_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_5_fec_spec == E200G_25G_5_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_5_lpbk_mode == E200G_25G_5_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_5_pcs_ber_mon_mode == E200G_25G_5_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_5_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_5_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_5_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_5_rx_fec_enable == E200G_25G_5_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_5_rx_pcs_mode == E200G_25G_5_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_5_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_5_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_5_rx_primary_use == E200G_25G_5_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_5_rx_system_bonding == E200G_25G_5_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_5_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_5_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_5_sup_mode == E200G_25G_5_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_5_sys_clk_src == E200G_25G_5_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_5_tx_aib_if_fifo_mode == E200G_25G_5_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_5_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_5_tx_fec_enable == E200G_25G_5_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_5_tx_pcs_mode == E200G_25G_5_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_5_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_5_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_5_tx_primary_use == E200G_25G_5_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_5_tx_system_bonding == E200G_25G_5_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_5_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_6_aibif_data_valid == E200G_25G_6_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_6_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_6_duplex_mode == E200G_25G_6_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_6_fec_mode == E200G_25G_6_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_6_fec_spec == E200G_25G_6_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_6_lpbk_mode == E200G_25G_6_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_6_pcs_ber_mon_mode == E200G_25G_6_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_6_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_6_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_6_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_6_rx_fec_enable == E200G_25G_6_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_6_rx_pcs_mode == E200G_25G_6_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_6_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_6_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_6_rx_primary_use == E200G_25G_6_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_6_rx_system_bonding == E200G_25G_6_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_6_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_6_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_6_sup_mode == E200G_25G_6_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_6_sys_clk_src == E200G_25G_6_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_6_tx_aib_if_fifo_mode == E200G_25G_6_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_6_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_6_tx_fec_enable == E200G_25G_6_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_6_tx_pcs_mode == E200G_25G_6_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_6_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_6_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_6_tx_primary_use == E200G_25G_6_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_6_tx_system_bonding == E200G_25G_6_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_6_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_7_aibif_data_valid == E200G_25G_7_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_7_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_7_duplex_mode == E200G_25G_7_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_7_fec_mode == E200G_25G_7_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_7_fec_spec == E200G_25G_7_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_7_lpbk_mode == E200G_25G_7_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_7_pcs_ber_mon_mode == E200G_25G_7_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_7_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_7_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_7_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_7_rx_fec_enable == E200G_25G_7_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_7_rx_pcs_mode == E200G_25G_7_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_7_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_7_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_7_rx_primary_use == E200G_25G_7_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_7_rx_system_bonding == E200G_25G_7_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_7_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_7_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_7_sup_mode == E200G_25G_7_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_7_sys_clk_src == E200G_25G_7_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_7_tx_aib_if_fifo_mode == E200G_25G_7_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_7_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_7_tx_fec_enable == E200G_25G_7_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_7_tx_pcs_mode == E200G_25G_7_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_7_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_7_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_7_tx_primary_use == E200G_25G_7_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_7_tx_system_bonding == E200G_25G_7_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_25g_7_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_0_aibif_data_valid == E200G_50G_0_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_0_duplex_mode == E200G_50G_0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_0_fec_mode == E200G_50G_0_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_0_lpbk_mode == E200G_50G_0_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_0_pcs_ber_mon_mode == E200G_50G_0_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_0_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_0_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_0_rx_fec_enable == E200G_50G_0_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_0_rx_pcs_mode == E200G_50G_0_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_0_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_0_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_0_rx_primary_use == E200G_50G_0_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_0_rx_system_bonding == E200G_50G_0_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_0_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_0_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_0_sup_mode == E200G_50G_0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_0_sys_clk_src == E200G_50G_0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_0_tx_aib_if_fifo_mode == E200G_50G_0_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_0_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_0_tx_fec_enable == E200G_50G_0_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_0_tx_pcs_mode == E200G_50G_0_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_0_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_0_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_0_tx_primary_use == E200G_50G_0_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_0_tx_system_bonding == E200G_50G_0_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_0_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_1_aibif_data_valid == E200G_50G_1_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_1_duplex_mode == E200G_50G_1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_1_fec_mode == E200G_50G_1_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_1_lpbk_mode == E200G_50G_1_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_1_pcs_ber_mon_mode == E200G_50G_1_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_1_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_1_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_1_rx_fec_enable == E200G_50G_1_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_1_rx_pcs_mode == E200G_50G_1_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_1_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_1_rx_primary_use == E200G_50G_1_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_1_rx_system_bonding == E200G_50G_1_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_1_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_1_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_1_sup_mode == E200G_50G_1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_1_sys_clk_src == E200G_50G_1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_1_tx_aib_if_fifo_mode == E200G_50G_1_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_1_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_1_tx_fec_enable == E200G_50G_1_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_1_tx_pcs_mode == E200G_50G_1_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_1_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_1_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_1_tx_primary_use == E200G_50G_1_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_1_tx_system_bonding == E200G_50G_1_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_1_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_2_aibif_data_valid == E200G_50G_2_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_2_duplex_mode == E200G_50G_2_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_2_fec_mode == E200G_50G_2_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_2_lpbk_mode == E200G_50G_2_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_2_pcs_ber_mon_mode == E200G_50G_2_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_2_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_2_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_2_rx_fec_enable == E200G_50G_2_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_2_rx_pcs_mode == E200G_50G_2_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_2_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_2_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_2_rx_primary_use == E200G_50G_2_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_2_rx_system_bonding == E200G_50G_2_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_2_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_2_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_2_sup_mode == E200G_50G_2_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_2_sys_clk_src == E200G_50G_2_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_2_tx_aib_if_fifo_mode == E200G_50G_2_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_2_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_2_tx_fec_enable == E200G_50G_2_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_2_tx_pcs_mode == E200G_50G_2_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_2_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_2_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_2_tx_primary_use == E200G_50G_2_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_2_tx_system_bonding == E200G_50G_2_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_2_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_3_aibif_data_valid == E200G_50G_3_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_3_duplex_mode == E200G_50G_3_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_3_fec_mode == E200G_50G_3_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_3_lpbk_mode == E200G_50G_3_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_3_pcs_ber_mon_mode == E200G_50G_3_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_3_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_3_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_3_rx_fec_enable == E200G_50G_3_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_3_rx_pcs_mode == E200G_50G_3_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_3_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_3_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_3_rx_primary_use == E200G_50G_3_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_3_rx_system_bonding == E200G_50G_3_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_3_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_3_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_3_sup_mode == E200G_50G_3_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_3_sys_clk_src == E200G_50G_3_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_3_tx_aib_if_fifo_mode == E200G_50G_3_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_3_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_3_tx_fec_enable == E200G_50G_3_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_3_tx_pcs_mode == E200G_50G_3_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_3_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_3_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_3_tx_primary_use == E200G_50G_3_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_3_tx_system_bonding == E200G_50G_3_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_50g_3_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream0_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream0_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream0_rx_primary_use == E200G_STREAM0_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream0_tx_aib_if_fifo_mode == E200G_STREAM0_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream0_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream0_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream0_tx_primary_use == E200G_STREAM0_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream1_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream1_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream1_rx_primary_use == E200G_STREAM1_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream1_tx_aib_if_fifo_mode == E200G_STREAM1_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream1_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream1_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream1_tx_primary_use == E200G_STREAM1_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream2_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream2_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream2_rx_primary_use == E200G_STREAM2_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream2_tx_aib_if_fifo_mode == E200G_STREAM2_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream2_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream2_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream2_tx_primary_use == E200G_STREAM2_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream3_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream3_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream3_rx_primary_use == E200G_STREAM3_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream3_tx_aib_if_fifo_mode == E200G_STREAM3_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream3_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream3_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream3_tx_primary_use == E200G_STREAM3_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream4_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream4_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream4_rx_primary_use == E200G_STREAM4_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream4_tx_aib_if_fifo_mode == E200G_STREAM4_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream4_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream4_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream4_tx_primary_use == E200G_STREAM4_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream5_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream5_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream5_rx_primary_use == E200G_STREAM5_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream5_tx_aib_if_fifo_mode == E200G_STREAM5_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream5_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream5_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream5_tx_primary_use == E200G_STREAM5_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream6_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream6_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream6_rx_primary_use == E200G_STREAM6_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream6_tx_aib_if_fifo_mode == E200G_STREAM6_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream6_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream6_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream6_tx_primary_use == E200G_STREAM6_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream7_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream7_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream7_rx_primary_use == E200G_STREAM7_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream7_tx_aib_if_fifo_mode == E200G_STREAM7_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream7_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream7_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.e200g_stream7_tx_primary_use == E200G_STREAM7_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_100g_0_rx_aibif == E200G_100G_0_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_100g_0_rx_pcs == E200G_100G_0_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_100g_0_tx_aibif == E200G_100G_0_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_100g_0_tx_pcs == E200G_100G_0_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_100g_1_rx_aibif == E200G_100G_1_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_100g_1_rx_pcs == E200G_100G_1_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_100g_1_tx_aibif == E200G_100G_1_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_100g_1_tx_pcs == E200G_100G_1_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_200g_rx_aibif == E200G_200G_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_200g_rx_pcs == E200G_200G_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_200g_tx_aibif == E200G_200G_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_200g_tx_pcs == E200G_200G_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_25g_0_rx_aibif == E200G_25G_0_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_25g_0_rx_pcs == E200G_25G_0_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_25g_0_tx_aibif == E200G_25G_0_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_25g_0_tx_pcs == E200G_25G_0_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_25g_1_rx_aibif == E200G_25G_1_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_25g_1_rx_pcs == E200G_25G_1_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_25g_1_tx_aibif == E200G_25G_1_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_25g_1_tx_pcs == E200G_25G_1_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_25g_2_rx_aibif == E200G_25G_2_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_25g_2_rx_pcs == E200G_25G_2_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_25g_2_tx_aibif == E200G_25G_2_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_25g_2_tx_pcs == E200G_25G_2_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_25g_3_rx_aibif == E200G_25G_3_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_25g_3_rx_pcs == E200G_25G_3_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_25g_3_tx_aibif == E200G_25G_3_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_25g_3_tx_pcs == E200G_25G_3_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_25g_4_rx_aibif == E200G_25G_4_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_25g_4_rx_pcs == E200G_25G_4_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_25g_4_tx_aibif == E200G_25G_4_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_25g_4_tx_pcs == E200G_25G_4_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_25g_5_rx_aibif == E200G_25G_5_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_25g_5_rx_pcs == E200G_25G_5_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_25g_5_tx_aibif == E200G_25G_5_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_25g_5_tx_pcs == E200G_25G_5_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_25g_6_rx_aibif == E200G_25G_6_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_25g_6_rx_pcs == E200G_25G_6_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_25g_6_tx_aibif == E200G_25G_6_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_25g_6_tx_pcs == E200G_25G_6_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_25g_7_rx_aibif == E200G_25G_7_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_25g_7_rx_pcs == E200G_25G_7_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_25g_7_tx_aibif == E200G_25G_7_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_25g_7_tx_pcs == E200G_25G_7_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_50g_0_rx_aibif == E200G_50G_0_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_50g_0_rx_pcs == E200G_50G_0_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_50g_0_tx_aibif == E200G_50G_0_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_50g_0_tx_pcs == E200G_50G_0_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_50g_1_rx_aibif == E200G_50G_1_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_50g_1_rx_pcs == E200G_50G_1_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_50g_1_tx_aibif == E200G_50G_1_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_50g_1_tx_pcs == E200G_50G_1_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_50g_2_rx_aibif == E200G_50G_2_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_50g_2_rx_pcs == E200G_50G_2_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_50g_2_tx_aibif == E200G_50G_2_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_50g_2_tx_pcs == E200G_50G_2_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_50g_3_rx_aibif == E200G_50G_3_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_50g_3_rx_pcs == E200G_50G_3_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_50g_3_tx_aibif == E200G_50G_3_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_e200g_50g_3_tx_pcs == E200G_50G_3_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_ehip_cfg == EHIP_CFG_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_ac_ehip_misc == EHIP_MISC_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_dc == POWERUP_DC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_freq_hz_ehip_cfg_clk == 31'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_freq_hz_ehip_ch0_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_freq_hz_ehip_ch1_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_freq_hz_ehip_ch2_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_freq_hz_ehip_ch3_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_freq_hz_ehip_ch4_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_freq_hz_ehip_ch5_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_freq_hz_ehip_ch6_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.powermode_freq_hz_ehip_ch7_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.ehip_rate == RATE_100G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_100g.gdr_e2hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.ehip_rate == RATE_200G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_200g.gdr_e2hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.ehip_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_25g.gdr_e2hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.ehip_rate == RATE_50G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch0_50g.gdr_e2hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.ehip_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch1_25g.gdr_e2hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.ehip_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_25g.gdr_e2hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.ehip_rate == RATE_50G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch2_50g.gdr_e2hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.ehip_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch3_25g.gdr_e2hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.ehip_rate == RATE_100G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_100g.gdr_e2hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.ehip_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_25g.gdr_e2hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.ehip_rate == RATE_50G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch4_50g.gdr_e2hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.ehip_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch5_25g.gdr_e2hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.ehip_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_25g.gdr_e2hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.ehip_rate == RATE_50G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch6_50g.gdr_e2hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.ehip_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.gdr_e2hip_top.u_gdr_e2hip_config_ch7_25g.gdr_e2hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib1_tx_st0_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib1_tx_st1_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib1_tx_st2_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib1_tx_st3_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib1_tx_st4_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib1_tx_st5_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib1_tx_st6_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib1_tx_st7_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib2_rx_st0_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib2_rx_st1_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib2_rx_st2_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib2_rx_st3_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib2_rx_st4_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib2_rx_st5_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib2_rx_st6_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib2_rx_st7_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib2_tx_st0_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib2_tx_st1_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib2_tx_st2_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib2_tx_st3_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib2_tx_st4_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib2_tx_st5_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib2_tx_st6_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib2_tx_st7_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib3_rx_st0_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib3_rx_st1_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib3_rx_st2_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib3_rx_st3_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib3_rx_st4_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib3_rx_st5_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib3_rx_st6_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib3_rx_st7_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib3_tx_st0_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib3_tx_st1_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib3_tx_st2_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib3_tx_st3_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib3_tx_st4_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib3_tx_st5_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib3_tx_st6_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib3_tx_st7_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.aib_esys_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.block_enable == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.bond_rx0_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.bond_rx1_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.bond_rx2_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.bond_rx3_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.bond_rx4_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.bond_rx5_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.bond_rx6_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.bond_rx7_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.bond_tx0_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.bond_tx1_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.bond_tx2_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.bond_tx3_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.bond_tx4_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.bond_tx5_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.bond_tx6_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.bond_tx7_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_aib2_rx_st_clk_en == E200G_100G_0_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_aib2_tx_st_clk_en == E200G_100G_0_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_aib3_rx_st_clk_en == E200G_100G_0_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_aib3_tx_st_clk_en == E200G_100G_0_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_duplex_mode == E200G_100G_0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_fec_clk_src == E200G_100G_0_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_fec_error == E200G_100G_0_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_fec_mode == E200G_100G_0_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_fec_spec == E200G_100G_0_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_lpbk_mode == E200G_100G_0_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_mac_mode == E200G_100G_0_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_ptp_mode == E200G_100G_0_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_rx_datarate == 36'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_rx_excvr_gb_ratio_mode == E200G_100G_0_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_rx_excvr_if_fifo_mode == E200G_100G_0_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_rx_fec_enable == E200G_100G_0_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_rx_pcs_mode == E200G_100G_0_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_rx_primary_use == E200G_100G_0_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_rx_stream_bonding == E200G_100G_0_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_rx_xcvr_bonded == E200G_100G_0_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_rx_xcvr_width == E200G_100G_0_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_speed_map == E200G_100G_0_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_sup_mode == E200G_100G_0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_sys_clk_src == E200G_100G_0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_tx_datarate == 36'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_tx_excvr_gb_ratio_mode == E200G_100G_0_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_tx_excvr_if_fifo_mode == E200G_100G_0_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_tx_fec_enable == E200G_100G_0_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_tx_pcs_mode == E200G_100G_0_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_tx_primary_use == E200G_100G_0_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_tx_stream_bonding == E200G_100G_0_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_tx_xcvr_bonded == E200G_100G_0_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_tx_xcvr_width == E200G_100G_0_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_xcvr_type == E200G_100G_0_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_0_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_aib2_rx_st_clk_en == E200G_100G_1_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_aib2_tx_st_clk_en == E200G_100G_1_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_aib3_rx_st_clk_en == E200G_100G_1_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_aib3_tx_st_clk_en == E200G_100G_1_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_duplex_mode == E200G_100G_1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_fec_clk_src == E200G_100G_1_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_fec_error == E200G_100G_1_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_fec_mode == E200G_100G_1_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_fec_spec == E200G_100G_1_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_lpbk_mode == E200G_100G_1_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_mac_mode == E200G_100G_1_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_ptp_mode == E200G_100G_1_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_rx_datarate == 36'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_rx_excvr_gb_ratio_mode == E200G_100G_1_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_rx_excvr_if_fifo_mode == E200G_100G_1_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_rx_fec_enable == E200G_100G_1_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_rx_pcs_mode == E200G_100G_1_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_rx_primary_use == E200G_100G_1_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_rx_stream_bonding == E200G_100G_1_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_rx_xcvr_bonded == E200G_100G_1_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_rx_xcvr_width == E200G_100G_1_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_speed_map == E200G_100G_1_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_sup_mode == E200G_100G_1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_sys_clk_src == E200G_100G_1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_tx_datarate == 36'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_tx_excvr_gb_ratio_mode == E200G_100G_1_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_tx_excvr_if_fifo_mode == E200G_100G_1_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_tx_fec_enable == E200G_100G_1_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_tx_pcs_mode == E200G_100G_1_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_tx_primary_use == E200G_100G_1_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_tx_stream_bonding == E200G_100G_1_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_tx_xcvr_bonded == E200G_100G_1_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_tx_xcvr_width == E200G_100G_1_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_xcvr_type == E200G_100G_1_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_100g_1_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_aib2_rx_st_clk_en == E200G_150G_0_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_aib2_tx_st_clk_en == E200G_150G_0_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_aib3_rx_st_clk_en == E200G_150G_0_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_aib3_tx_st_clk_en == E200G_150G_0_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_duplex_mode == E200G_150G_0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_fec_mode == E200G_150G_0_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_fec_spec == E200G_150G_0_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_lpbk_mode == E200G_150G_0_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_mac_mode == E200G_150G_0_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_ptp_mode == E200G_150G_0_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_rx_datarate == 36'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_rx_excvr_gb_ratio_mode == E200G_150G_0_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_rx_excvr_if_fifo_mode == E200G_150G_0_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_rx_fec_enable == E200G_150G_0_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_rx_pcs_mode == E200G_150G_0_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_rx_primary_use == E200G_150G_0_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_rx_stream_bonding == E200G_150G_0_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_rx_xcvr_bonded == E200G_150G_0_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_rx_xcvr_width == E200G_150G_0_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_speed_map == E200G_150G_0_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_sup_mode == E200G_150G_0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_sys_clk_src == E200G_150G_0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_tx_datarate == 36'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_tx_excvr_gb_ratio_mode == E200G_150G_0_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_tx_excvr_if_fifo_mode == E200G_150G_0_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_tx_fec_enable == E200G_150G_0_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_tx_pcs_mode == E200G_150G_0_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_tx_primary_use == E200G_150G_0_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_tx_stream_bonding == E200G_150G_0_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_tx_xcvr_bonded == E200G_150G_0_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_tx_xcvr_width == E200G_150G_0_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_xcvr_type == E200G_150G_0_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_0_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_aib2_rx_st_clk_en == E200G_150G_1_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_aib2_tx_st_clk_en == E200G_150G_1_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_aib3_rx_st_clk_en == E200G_150G_1_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_aib3_tx_st_clk_en == E200G_150G_1_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_duplex_mode == E200G_150G_1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_fec_mode == E200G_150G_1_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_fec_spec == E200G_150G_1_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_lpbk_mode == E200G_150G_1_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_mac_mode == E200G_150G_1_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_ptp_mode == E200G_150G_1_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_rx_datarate == 36'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_rx_excvr_gb_ratio_mode == E200G_150G_1_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_rx_excvr_if_fifo_mode == E200G_150G_1_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_rx_fec_enable == E200G_150G_1_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_rx_pcs_mode == E200G_150G_1_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_rx_primary_use == E200G_150G_1_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_rx_stream_bonding == E200G_150G_1_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_rx_xcvr_bonded == E200G_150G_1_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_rx_xcvr_width == E200G_150G_1_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_speed_map == E200G_150G_1_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_sup_mode == E200G_150G_1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_sys_clk_src == E200G_150G_1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_tx_datarate == 36'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_tx_excvr_gb_ratio_mode == E200G_150G_1_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_tx_excvr_if_fifo_mode == E200G_150G_1_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_tx_fec_enable == E200G_150G_1_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_tx_pcs_mode == E200G_150G_1_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_tx_primary_use == E200G_150G_1_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_tx_stream_bonding == E200G_150G_1_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_tx_xcvr_bonded == E200G_150G_1_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_tx_xcvr_width == E200G_150G_1_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_xcvr_type == E200G_150G_1_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_150g_1_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_aib2_rx_st_clk_en == E200G_200G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_aib2_tx_st_clk_en == E200G_200G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_aib3_rx_st_clk_en == E200G_200G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_aib3_tx_st_clk_en == E200G_200G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_duplex_mode == E200G_200G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_fec_clk_src == E200G_200G_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_fec_error == E200G_200G_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_fec_mode == E200G_200G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_fec_spec == E200G_200G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_lpbk_mode == E200G_200G_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_mac_mode == E200G_200G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_ptp_mode == E200G_200G_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_rx_datarate == 36'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_rx_excvr_gb_ratio_mode == E200G_200G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_rx_excvr_if_fifo_mode == E200G_200G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_rx_fec_enable == E200G_200G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_rx_pcs_mode == E200G_200G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_rx_primary_use == E200G_200G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_rx_stream_bonding == E200G_200G_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_rx_xcvr_bonded == E200G_200G_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_rx_xcvr_width == E200G_200G_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_speed_map == E200G_200G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_sup_mode == E200G_200G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_sys_clk_src == E200G_200G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_tx_datarate == 36'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_tx_excvr_gb_ratio_mode == E200G_200G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_tx_excvr_if_fifo_mode == E200G_200G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_tx_fec_enable == E200G_200G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_tx_pcs_mode == E200G_200G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_tx_primary_use == E200G_200G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_tx_stream_bonding == E200G_200G_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_tx_xcvr_bonded == E200G_200G_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_tx_xcvr_width == E200G_200G_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_xcvr_type == E200G_200G_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_200g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_aib2_rx_st_clk_en == E200G_25G_0_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_aib2_tx_st_clk_en == E200G_25G_0_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_aib3_rx_st_clk_en == E200G_25G_0_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_aib3_tx_st_clk_en == E200G_25G_0_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_duplex_mode == E200G_25G_0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_fec_clk_src == E200G_25G_0_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_fec_error == E200G_25G_0_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_fec_mode == E200G_25G_0_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_fec_spec == E200G_25G_0_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_lpbk_mode == E200G_25G_0_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_mac_mode == E200G_25G_0_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_ptp_mode == E200G_25G_0_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_rx_datarate == 36'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_rx_excvr_gb_ratio_mode == E200G_25G_0_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_rx_excvr_if_fifo_mode == E200G_25G_0_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_rx_fec_enable == E200G_25G_0_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_rx_pcs_mode == E200G_25G_0_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_rx_primary_use == E200G_25G_0_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_rx_stream_bonding == E200G_25G_0_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_rx_xcvr_bonded == E200G_25G_0_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_rx_xcvr_width == E200G_25G_0_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_speed_map == E200G_25G_0_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_sup_mode == E200G_25G_0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_sys_clk_src == E200G_25G_0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_tx_datarate == 36'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_tx_excvr_gb_ratio_mode == E200G_25G_0_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_tx_excvr_if_fifo_mode == E200G_25G_0_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_tx_fec_enable == E200G_25G_0_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_tx_pcs_mode == E200G_25G_0_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_tx_primary_use == E200G_25G_0_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_tx_stream_bonding == E200G_25G_0_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_tx_xcvr_bonded == E200G_25G_0_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_tx_xcvr_width == E200G_25G_0_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_xcvr_type == E200G_25G_0_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_0_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_aib2_rx_st_clk_en == E200G_25G_1_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_aib2_tx_st_clk_en == E200G_25G_1_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_aib3_rx_st_clk_en == E200G_25G_1_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_aib3_tx_st_clk_en == E200G_25G_1_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_duplex_mode == E200G_25G_1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_fec_clk_src == E200G_25G_1_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_fec_error == E200G_25G_1_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_fec_mode == E200G_25G_1_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_fec_spec == E200G_25G_1_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_lpbk_mode == E200G_25G_1_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_mac_mode == E200G_25G_1_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_ptp_mode == E200G_25G_1_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_rx_datarate == 36'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_rx_excvr_gb_ratio_mode == E200G_25G_1_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_rx_excvr_if_fifo_mode == E200G_25G_1_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_rx_fec_enable == E200G_25G_1_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_rx_pcs_mode == E200G_25G_1_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_rx_primary_use == E200G_25G_1_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_rx_stream_bonding == E200G_25G_1_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_rx_xcvr_bonded == E200G_25G_1_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_rx_xcvr_width == E200G_25G_1_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_speed_map == E200G_25G_1_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_sup_mode == E200G_25G_1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_sys_clk_src == E200G_25G_1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_tx_datarate == 36'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_tx_excvr_gb_ratio_mode == E200G_25G_1_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_tx_excvr_if_fifo_mode == E200G_25G_1_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_tx_fec_enable == E200G_25G_1_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_tx_pcs_mode == E200G_25G_1_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_tx_primary_use == E200G_25G_1_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_tx_stream_bonding == E200G_25G_1_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_tx_xcvr_bonded == E200G_25G_1_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_tx_xcvr_width == E200G_25G_1_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_xcvr_type == E200G_25G_1_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_1_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_aib2_rx_st_clk_en == E200G_25G_2_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_aib2_tx_st_clk_en == E200G_25G_2_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_aib3_rx_st_clk_en == E200G_25G_2_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_aib3_tx_st_clk_en == E200G_25G_2_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_duplex_mode == E200G_25G_2_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_fec_clk_src == E200G_25G_2_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_fec_error == E200G_25G_2_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_fec_mode == E200G_25G_2_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_fec_spec == E200G_25G_2_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_lpbk_mode == E200G_25G_2_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_mac_mode == E200G_25G_2_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_ptp_mode == E200G_25G_2_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_rx_datarate == 36'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_rx_excvr_gb_ratio_mode == E200G_25G_2_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_rx_excvr_if_fifo_mode == E200G_25G_2_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_rx_fec_enable == E200G_25G_2_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_rx_pcs_mode == E200G_25G_2_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_rx_primary_use == E200G_25G_2_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_rx_stream_bonding == E200G_25G_2_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_rx_xcvr_bonded == E200G_25G_2_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_rx_xcvr_width == E200G_25G_2_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_speed_map == E200G_25G_2_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_sup_mode == E200G_25G_2_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_sys_clk_src == E200G_25G_2_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_tx_datarate == 36'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_tx_excvr_gb_ratio_mode == E200G_25G_2_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_tx_excvr_if_fifo_mode == E200G_25G_2_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_tx_fec_enable == E200G_25G_2_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_tx_pcs_mode == E200G_25G_2_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_tx_primary_use == E200G_25G_2_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_tx_stream_bonding == E200G_25G_2_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_tx_xcvr_bonded == E200G_25G_2_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_tx_xcvr_width == E200G_25G_2_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_xcvr_type == E200G_25G_2_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_2_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_aib2_rx_st_clk_en == E200G_25G_3_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_aib2_tx_st_clk_en == E200G_25G_3_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_aib3_rx_st_clk_en == E200G_25G_3_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_aib3_tx_st_clk_en == E200G_25G_3_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_duplex_mode == E200G_25G_3_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_fec_clk_src == E200G_25G_3_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_fec_error == E200G_25G_3_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_fec_mode == E200G_25G_3_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_fec_spec == E200G_25G_3_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_lpbk_mode == E200G_25G_3_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_mac_mode == E200G_25G_3_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_ptp_mode == E200G_25G_3_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_rx_datarate == 36'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_rx_excvr_gb_ratio_mode == E200G_25G_3_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_rx_excvr_if_fifo_mode == E200G_25G_3_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_rx_fec_enable == E200G_25G_3_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_rx_pcs_mode == E200G_25G_3_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_rx_primary_use == E200G_25G_3_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_rx_stream_bonding == E200G_25G_3_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_rx_xcvr_bonded == E200G_25G_3_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_rx_xcvr_width == E200G_25G_3_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_speed_map == E200G_25G_3_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_sup_mode == E200G_25G_3_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_sys_clk_src == E200G_25G_3_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_tx_datarate == 36'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_tx_excvr_gb_ratio_mode == E200G_25G_3_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_tx_excvr_if_fifo_mode == E200G_25G_3_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_tx_fec_enable == E200G_25G_3_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_tx_pcs_mode == E200G_25G_3_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_tx_primary_use == E200G_25G_3_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_tx_stream_bonding == E200G_25G_3_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_tx_xcvr_bonded == E200G_25G_3_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_tx_xcvr_width == E200G_25G_3_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_xcvr_type == E200G_25G_3_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_3_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_aib2_rx_st_clk_en == E200G_25G_4_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_aib2_tx_st_clk_en == E200G_25G_4_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_aib3_rx_st_clk_en == E200G_25G_4_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_aib3_tx_st_clk_en == E200G_25G_4_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_duplex_mode == E200G_25G_4_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_fec_clk_src == E200G_25G_4_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_fec_error == E200G_25G_4_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_fec_mode == E200G_25G_4_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_fec_spec == E200G_25G_4_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_lpbk_mode == E200G_25G_4_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_mac_mode == E200G_25G_4_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_ptp_mode == E200G_25G_4_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_rx_datarate == 36'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_rx_excvr_gb_ratio_mode == E200G_25G_4_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_rx_excvr_if_fifo_mode == E200G_25G_4_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_rx_fec_enable == E200G_25G_4_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_rx_pcs_mode == E200G_25G_4_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_rx_primary_use == E200G_25G_4_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_rx_stream_bonding == E200G_25G_4_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_rx_xcvr_bonded == E200G_25G_4_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_rx_xcvr_width == E200G_25G_4_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_speed_map == E200G_25G_4_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_sup_mode == E200G_25G_4_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_sys_clk_src == E200G_25G_4_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_tx_datarate == 36'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_tx_excvr_gb_ratio_mode == E200G_25G_4_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_tx_excvr_if_fifo_mode == E200G_25G_4_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_tx_fec_enable == E200G_25G_4_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_tx_pcs_mode == E200G_25G_4_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_tx_primary_use == E200G_25G_4_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_tx_stream_bonding == E200G_25G_4_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_tx_xcvr_bonded == E200G_25G_4_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_tx_xcvr_width == E200G_25G_4_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_xcvr_type == E200G_25G_4_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_4_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_aib2_rx_st_clk_en == E200G_25G_5_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_aib2_tx_st_clk_en == E200G_25G_5_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_aib3_rx_st_clk_en == E200G_25G_5_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_aib3_tx_st_clk_en == E200G_25G_5_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_duplex_mode == E200G_25G_5_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_fec_clk_src == E200G_25G_5_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_fec_error == E200G_25G_5_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_fec_mode == E200G_25G_5_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_fec_spec == E200G_25G_5_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_lpbk_mode == E200G_25G_5_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_mac_mode == E200G_25G_5_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_ptp_mode == E200G_25G_5_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_rx_datarate == 36'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_rx_excvr_gb_ratio_mode == E200G_25G_5_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_rx_excvr_if_fifo_mode == E200G_25G_5_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_rx_fec_enable == E200G_25G_5_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_rx_pcs_mode == E200G_25G_5_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_rx_primary_use == E200G_25G_5_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_rx_stream_bonding == E200G_25G_5_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_rx_xcvr_bonded == E200G_25G_5_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_rx_xcvr_width == E200G_25G_5_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_speed_map == E200G_25G_5_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_sup_mode == E200G_25G_5_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_sys_clk_src == E200G_25G_5_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_tx_datarate == 36'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_tx_excvr_gb_ratio_mode == E200G_25G_5_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_tx_excvr_if_fifo_mode == E200G_25G_5_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_tx_fec_enable == E200G_25G_5_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_tx_pcs_mode == E200G_25G_5_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_tx_primary_use == E200G_25G_5_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_tx_stream_bonding == E200G_25G_5_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_tx_xcvr_bonded == E200G_25G_5_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_tx_xcvr_width == E200G_25G_5_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_xcvr_type == E200G_25G_5_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_5_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_aib2_rx_st_clk_en == E200G_25G_6_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_aib2_tx_st_clk_en == E200G_25G_6_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_aib3_rx_st_clk_en == E200G_25G_6_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_aib3_tx_st_clk_en == E200G_25G_6_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_duplex_mode == E200G_25G_6_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_fec_clk_src == E200G_25G_6_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_fec_error == E200G_25G_6_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_fec_mode == E200G_25G_6_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_fec_spec == E200G_25G_6_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_lpbk_mode == E200G_25G_6_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_mac_mode == E200G_25G_6_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_ptp_mode == E200G_25G_6_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_rx_datarate == 36'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_rx_excvr_gb_ratio_mode == E200G_25G_6_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_rx_excvr_if_fifo_mode == E200G_25G_6_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_rx_fec_enable == E200G_25G_6_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_rx_pcs_mode == E200G_25G_6_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_rx_primary_use == E200G_25G_6_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_rx_stream_bonding == E200G_25G_6_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_rx_xcvr_bonded == E200G_25G_6_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_rx_xcvr_width == E200G_25G_6_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_speed_map == E200G_25G_6_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_sup_mode == E200G_25G_6_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_sys_clk_src == E200G_25G_6_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_tx_datarate == 36'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_tx_excvr_gb_ratio_mode == E200G_25G_6_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_tx_excvr_if_fifo_mode == E200G_25G_6_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_tx_fec_enable == E200G_25G_6_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_tx_pcs_mode == E200G_25G_6_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_tx_primary_use == E200G_25G_6_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_tx_stream_bonding == E200G_25G_6_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_tx_xcvr_bonded == E200G_25G_6_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_tx_xcvr_width == E200G_25G_6_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_xcvr_type == E200G_25G_6_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_6_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_aib2_rx_st_clk_en == E200G_25G_7_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_aib2_tx_st_clk_en == E200G_25G_7_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_aib3_rx_st_clk_en == E200G_25G_7_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_aib3_tx_st_clk_en == E200G_25G_7_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_duplex_mode == E200G_25G_7_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_fec_clk_src == E200G_25G_7_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_fec_error == E200G_25G_7_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_fec_mode == E200G_25G_7_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_fec_spec == E200G_25G_7_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_lpbk_mode == E200G_25G_7_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_mac_mode == E200G_25G_7_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_ptp_mode == E200G_25G_7_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_rx_datarate == 36'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_rx_excvr_gb_ratio_mode == E200G_25G_7_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_rx_excvr_if_fifo_mode == E200G_25G_7_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_rx_fec_enable == E200G_25G_7_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_rx_pcs_mode == E200G_25G_7_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_rx_primary_use == E200G_25G_7_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_rx_stream_bonding == E200G_25G_7_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_rx_xcvr_bonded == E200G_25G_7_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_rx_xcvr_width == E200G_25G_7_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_speed_map == E200G_25G_7_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_sup_mode == E200G_25G_7_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_sys_clk_src == E200G_25G_7_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_tx_datarate == 36'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_tx_excvr_gb_ratio_mode == E200G_25G_7_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_tx_excvr_if_fifo_mode == E200G_25G_7_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_tx_fec_enable == E200G_25G_7_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_tx_pcs_mode == E200G_25G_7_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_tx_primary_use == E200G_25G_7_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_tx_stream_bonding == E200G_25G_7_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_tx_xcvr_bonded == E200G_25G_7_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_tx_xcvr_width == E200G_25G_7_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_xcvr_type == E200G_25G_7_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_25g_7_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_aib2_rx_st_clk_en == E200G_50G_0_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_aib2_tx_st_clk_en == E200G_50G_0_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_aib3_rx_st_clk_en == E200G_50G_0_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_aib3_tx_st_clk_en == E200G_50G_0_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_duplex_mode == E200G_50G_0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_fec_clk_src == E200G_50G_0_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_fec_error == E200G_50G_0_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_fec_mode == E200G_50G_0_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_fec_spec == E200G_50G_0_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_lpbk_mode == E200G_50G_0_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_mac_mode == E200G_50G_0_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_ptp_mode == E200G_50G_0_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_rx_datarate == 36'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_rx_excvr_gb_ratio_mode == E200G_50G_0_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_rx_excvr_if_fifo_mode == E200G_50G_0_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_rx_fec_enable == E200G_50G_0_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_rx_pcs_mode == E200G_50G_0_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_rx_primary_use == E200G_50G_0_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_rx_stream_bonding == E200G_50G_0_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_rx_xcvr_bonded == E200G_50G_0_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_rx_xcvr_width == E200G_50G_0_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_speed_map == E200G_50G_0_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_sup_mode == E200G_50G_0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_sys_clk_src == E200G_50G_0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_tx_datarate == 36'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_tx_excvr_gb_ratio_mode == E200G_50G_0_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_tx_excvr_if_fifo_mode == E200G_50G_0_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_tx_fec_enable == E200G_50G_0_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_tx_pcs_mode == E200G_50G_0_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_tx_primary_use == E200G_50G_0_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_tx_stream_bonding == E200G_50G_0_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_tx_xcvr_bonded == E200G_50G_0_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_tx_xcvr_width == E200G_50G_0_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_xcvr_type == E200G_50G_0_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_0_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_aib2_rx_st_clk_en == E200G_50G_1_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_aib2_tx_st_clk_en == E200G_50G_1_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_aib3_rx_st_clk_en == E200G_50G_1_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_aib3_tx_st_clk_en == E200G_50G_1_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_duplex_mode == E200G_50G_1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_fec_clk_src == E200G_50G_1_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_fec_error == E200G_50G_1_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_fec_mode == E200G_50G_1_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_fec_spec == E200G_50G_1_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_lpbk_mode == E200G_50G_1_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_mac_mode == E200G_50G_1_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_ptp_mode == E200G_50G_1_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_rx_datarate == 36'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_rx_excvr_gb_ratio_mode == E200G_50G_1_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_rx_excvr_if_fifo_mode == E200G_50G_1_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_rx_fec_enable == E200G_50G_1_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_rx_pcs_mode == E200G_50G_1_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_rx_primary_use == E200G_50G_1_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_rx_stream_bonding == E200G_50G_1_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_rx_xcvr_bonded == E200G_50G_1_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_rx_xcvr_width == E200G_50G_1_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_speed_map == E200G_50G_1_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_sup_mode == E200G_50G_1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_sys_clk_src == E200G_50G_1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_tx_datarate == 36'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_tx_excvr_gb_ratio_mode == E200G_50G_1_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_tx_excvr_if_fifo_mode == E200G_50G_1_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_tx_fec_enable == E200G_50G_1_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_tx_pcs_mode == E200G_50G_1_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_tx_primary_use == E200G_50G_1_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_tx_stream_bonding == E200G_50G_1_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_tx_xcvr_bonded == E200G_50G_1_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_tx_xcvr_width == E200G_50G_1_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_xcvr_type == E200G_50G_1_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_1_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_aib2_rx_st_clk_en == E200G_50G_2_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_aib2_tx_st_clk_en == E200G_50G_2_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_aib3_rx_st_clk_en == E200G_50G_2_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_aib3_tx_st_clk_en == E200G_50G_2_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_duplex_mode == E200G_50G_2_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_fec_clk_src == E200G_50G_2_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_fec_error == E200G_50G_2_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_fec_mode == E200G_50G_2_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_fec_spec == E200G_50G_2_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_lpbk_mode == E200G_50G_2_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_mac_mode == E200G_50G_2_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_ptp_mode == E200G_50G_2_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_rx_datarate == 36'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_rx_excvr_gb_ratio_mode == E200G_50G_2_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_rx_excvr_if_fifo_mode == E200G_50G_2_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_rx_fec_enable == E200G_50G_2_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_rx_pcs_mode == E200G_50G_2_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_rx_primary_use == E200G_50G_2_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_rx_stream_bonding == E200G_50G_2_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_rx_xcvr_bonded == E200G_50G_2_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_rx_xcvr_width == E200G_50G_2_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_speed_map == E200G_50G_2_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_sup_mode == E200G_50G_2_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_sys_clk_src == E200G_50G_2_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_tx_datarate == 36'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_tx_excvr_gb_ratio_mode == E200G_50G_2_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_tx_excvr_if_fifo_mode == E200G_50G_2_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_tx_fec_enable == E200G_50G_2_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_tx_pcs_mode == E200G_50G_2_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_tx_primary_use == E200G_50G_2_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_tx_stream_bonding == E200G_50G_2_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_tx_xcvr_bonded == E200G_50G_2_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_tx_xcvr_width == E200G_50G_2_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_xcvr_type == E200G_50G_2_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_2_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_aib2_rx_st_clk_en == E200G_50G_3_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_aib2_tx_st_clk_en == E200G_50G_3_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_aib3_rx_st_clk_en == E200G_50G_3_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_aib3_tx_st_clk_en == E200G_50G_3_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_duplex_mode == E200G_50G_3_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_fec_clk_src == E200G_50G_3_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_fec_error == E200G_50G_3_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_fec_mode == E200G_50G_3_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_fec_spec == E200G_50G_3_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_lpbk_mode == E200G_50G_3_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_mac_mode == E200G_50G_3_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_ptp_mode == E200G_50G_3_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_rx_datarate == 36'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_rx_excvr_gb_ratio_mode == E200G_50G_3_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_rx_excvr_if_fifo_mode == E200G_50G_3_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_rx_fec_enable == E200G_50G_3_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_rx_pcs_mode == E200G_50G_3_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_rx_primary_use == E200G_50G_3_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_rx_stream_bonding == E200G_50G_3_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_rx_xcvr_bonded == E200G_50G_3_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_rx_xcvr_width == E200G_50G_3_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_speed_map == E200G_50G_3_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_sup_mode == E200G_50G_3_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_sys_clk_src == E200G_50G_3_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_tx_datarate == 36'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_tx_excvr_gb_ratio_mode == E200G_50G_3_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_tx_excvr_if_fifo_mode == E200G_50G_3_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_tx_fec_enable == E200G_50G_3_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_tx_pcs_mode == E200G_50G_3_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_tx_primary_use == E200G_50G_3_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_tx_stream_bonding == E200G_50G_3_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_tx_xcvr_bonded == E200G_50G_3_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_tx_xcvr_width == E200G_50G_3_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_xcvr_type == E200G_50G_3_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_50g_3_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_stream0_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_stream0_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_stream0_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_stream0_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_stream1_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_stream1_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_stream1_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_stream1_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_stream2_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_stream2_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_stream2_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_stream2_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_stream3_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_stream3_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_stream3_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_stream3_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_stream4_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_stream4_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_stream4_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_stream4_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_stream5_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_stream5_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_stream5_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_stream5_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_stream6_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_stream6_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_stream6_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_stream6_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_stream7_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_stream7_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_stream7_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.e200g_stream7_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.func_mode == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.map_25e2x0 == MAP_25E2X0_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.map_25e2x1 == MAP_25E2X1_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.map_25e2x2 == MAP_25E2X2_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.map_25e2x3 == MAP_25E2X3_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.map_25e2x4 == MAP_25E2X4_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.map_25e2x5 == MAP_25E2X5_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.map_25e2x6 == MAP_25E2X6_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.map_25e2x7 == MAP_25E2X7_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.map_56e2x0 == MAP_56E2X0_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.map_56e2x1 == MAP_56E2X1_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.map_56e2x2 == MAP_56E2X2_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.map_56e2x3 == MAP_56E2X3_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.map_ux0 == MAP_UX0_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.map_ux1 == MAP_UX1_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.map_ux2 == MAP_UX2_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.map_ux3 == MAP_UX3_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.map_ux4 == MAP_UX4_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.map_ux5 == MAP_UX5_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.map_ux6 == MAP_UX6_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.map_ux7 == MAP_UX7_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_ac_100g_0 == OFF_100G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_ac_100g_1 == OFF_100G_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_ac_150g_0 == OFF_150G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_ac_150g_1 == OFF_150G_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_ac_200g == OFF_200G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_ac_25g_0 == OFF_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_ac_25g_1 == OFF_25G_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_ac_25g_2 == OFF_25G_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_ac_25g_3 == OFF_25G_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_ac_25g_4 == OFF_25G_4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_ac_25g_5 == OFF_25G_5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_ac_25g_6 == OFF_25G_6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_ac_25g_7 == OFF_25G_7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_ac_50g_0 == OFF_50G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_ac_50g_1 == OFF_50G_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_ac_50g_2 == OFF_50G_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_ac_50g_3 == OFF_50G_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_ac_core0_clk == FEC_CORE0_CLK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_ac_core1_clk == FEC_CORE1_CLK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_ac_global_avmm == GLOBAL_AVMM_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_freq_hz_eth_rx_st0_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_freq_hz_eth_rx_st1_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_freq_hz_eth_rx_st2_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_freq_hz_eth_rx_st3_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_freq_hz_eth_rx_st4_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_freq_hz_eth_rx_st5_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_freq_hz_eth_rx_st6_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_freq_hz_eth_rx_st7_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_freq_hz_eth_tx_st0_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_freq_hz_eth_tx_st1_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_freq_hz_eth_tx_st2_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_freq_hz_eth_tx_st3_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_freq_hz_eth_tx_st4_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_freq_hz_eth_tx_st5_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_freq_hz_eth_tx_st6_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_freq_hz_eth_tx_st7_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.powermode_freq_hz_global_avmm_clk == 37'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.speed_grade == DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.sys_pll0_div1_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.sys_pll0_div2_clk_hz == 37'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.sys_pll1_div1_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.sys_pll1_div2_clk_hz == 37'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.sys_pll2_div1_clk_hz == 37'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.sys_pll2_div2_clk_hz == 37'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.transfer_clk0_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.transfer_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.transfer_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.transfer_clk3_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.transfer_clk4_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.transfer_clk5_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.transfer_clk6_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.transfer_clk7_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux0_return_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux0_rx_user_clk_hz == 37'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux0_rxword_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux0_tx_user_clk1_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux0_tx_user_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux0_txword_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux1_return_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux1_rx_user_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux1_rxword_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux1_tx_user_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux1_tx_user_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux1_txword_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux2_return_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux2_rx_user_clk_hz == 37'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux2_rxword_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux2_tx_user_clk1_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux2_tx_user_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux2_txword_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux3_return_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux3_rx_user_clk_hz == 37'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux3_rxword_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux3_tx_user_clk1_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux3_tx_user_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux3_txword_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux4_return_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux4_rx_user_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux4_rxword_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux4_tx_user_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux4_tx_user_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux4_txword_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux5_return_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux5_rx_user_clk_hz == 37'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux5_rxword_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux5_tx_user_clk1_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux5_tx_user_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux5_txword_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux6_return_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux6_rx_user_clk_hz == 37'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux6_rxword_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux6_tx_user_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux6_tx_user_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux6_txword_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux7_return_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux7_rx_user_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux7_rxword_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux7_tx_user_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux7_tx_user_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.ux7_txword_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_rx_st0_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_rx_st1_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_rx_st2_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_rx_st3_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_rx_st4_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_rx_st5_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_rx_st6_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_rx_st7_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_rx_user_st0_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_rx_user_st0_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_rx_user_st1_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_rx_user_st1_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_rx_user_st2_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_rx_user_st2_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_rx_user_st3_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_rx_user_st3_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_rx_user_st4_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_rx_user_st4_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_rx_user_st5_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_rx_user_st5_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_rx_user_st6_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_rx_user_st6_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_rx_user_st7_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_rx_user_st7_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_select_25e2x0 == XCVR_SELECT_25E2X0_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_select_25e2x1 == XCVR_SELECT_25E2X1_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_select_25e2x2 == XCVR_SELECT_25E2X2_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_select_25e2x3 == XCVR_SELECT_25E2X3_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_select_25e2x4 == XCVR_SELECT_25E2X4_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_select_25e2x5 == XCVR_SELECT_25E2X5_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_select_25e2x6 == XCVR_SELECT_25E2X6_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_select_25e2x7 == XCVR_SELECT_25E2X7_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_select_56e2x0 == XCVR_SELECT_56E2X0_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_select_56e2x1 == XCVR_SELECT_56E2X1_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_select_56e2x2 == XCVR_SELECT_56E2X2_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_select_56e2x3 == XCVR_SELECT_56E2X3_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_tx_st0_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_tx_st1_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_tx_st2_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_tx_st3_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_tx_st4_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_tx_st5_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_tx_st6_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_tx_st7_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_tx_user_st0_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_tx_user_st0_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_tx_user_st1_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_tx_user_st1_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_tx_user_st2_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_tx_user_st2_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_tx_user_st3_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_tx_user_st3_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_tx_user_st4_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_tx_user_st4_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_tx_user_st5_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_tx_user_st5_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_tx_user_st6_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_tx_user_st6_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_tx_user_st7_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.xcvr_tx_user_st7_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_aib2_rx_st_clk_en == E200G_100G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_aib2_tx_st_clk_en == E200G_100G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_aib3_rx_st_clk_en == E200G_100G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_aib3_tx_st_clk_en == E200G_100G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_duplex_mode == E200G_100G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_fec_mode == E200G_100G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_fec_spec == E200G_100G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_mac_mode == E200G_100G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_rx_excvr_gb_ratio_mode == E200G_100G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_rx_excvr_if_fifo_mode == E200G_100G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_rx_fec_enable == E200G_100G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_rx_pcs_mode == E200G_100G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_rx_primary_use == E200G_100G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_speed_map == E200G_100G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_sup_mode == E200G_100G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_sys_clk_src == E200G_100G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_tx_excvr_gb_ratio_mode == E200G_100G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_tx_excvr_if_fifo_mode == E200G_100G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_tx_fec_enable == E200G_100G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_tx_pcs_mode == E200G_100G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_tx_primary_use == E200G_100G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.e200g_100g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.unused_bk_return_clk_gate_attr == UNUSED_BK_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.unused_bk_tx_rtrn_clk_sel == BK3_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_sel3 == UNUSED_RX_CLK_SEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvr_sel == UX_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_sys_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.cfg_frac == FRAC_LN4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_sfrz_rx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_sfrz_tx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.unused_bk_return_clk_gate_attr == UNUSED_BK_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.unused_bk_tx_rtrn_clk_sel == BK3_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_sel3 == UNUSED_RX_CLK_SEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.ux_tx_rtrn_clk_sel == UX7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvr_sel == UX_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pempty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_sys_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.cfg_frac == FRAC_LN4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_sfrz_rx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_sfrz_tx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.unused_bk_return_clk_gate_attr == UNUSED_BK_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.unused_bk_tx_rtrn_clk_sel == BK3_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.unused_lphy_rx_clk_sel3 == UNUSED_RX_CLK_SEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.ux_tx_rtrn_clk_sel == UX7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvr_sel == UX_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_fifo_pempty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_sys_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.cfg_frac == FRAC_LN4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_sfrz_rx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_sfrz_tx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.unused_bk_return_clk_gate_attr == UNUSED_BK_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.unused_bk_tx_rtrn_clk_sel == BK3_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.unused_lphy_rx_clk_sel3 == UNUSED_RX_CLK_SEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.ux_tx_rtrn_clk_sel == UX7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvr_sel == UX_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_fifo_pempty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_sys_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_aib2_rx_st_clk_en == E200G_100G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_aib2_tx_st_clk_en == E200G_100G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_aib3_rx_st_clk_en == E200G_100G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_aib3_tx_st_clk_en == E200G_100G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_duplex_mode == E200G_100G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_fec_mode == E200G_100G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_fec_spec == E200G_100G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_mac_mode == E200G_100G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_rx_excvr_gb_ratio_mode == E200G_100G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_rx_excvr_if_fifo_mode == E200G_100G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_rx_fec_enable == E200G_100G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_rx_pcs_mode == E200G_100G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_rx_primary_use == E200G_100G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_speed_map == E200G_100G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_sup_mode == E200G_100G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_sys_clk_src == E200G_100G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_tx_excvr_gb_ratio_mode == E200G_100G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_tx_excvr_if_fifo_mode == E200G_100G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_tx_fec_enable == E200G_100G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_tx_pcs_mode == E200G_100G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_tx_primary_use == E200G_100G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.e200g_100g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.unused_bk_return_clk_gate_attr == UNUSED_BK_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.unused_bk_tx_rtrn_clk_sel == BK3_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_sel3 == UNUSED_RX_CLK_SEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvr_sel == UX_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_sys_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.cfg_frac == FRAC_LN4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_sfrz_rx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_sfrz_tx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.unused_bk_return_clk_gate_attr == UNUSED_BK_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.unused_bk_tx_rtrn_clk_sel == BK3_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_sel3 == UNUSED_RX_CLK_SEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.ux_tx_rtrn_clk_sel == UX7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvr_sel == UX_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pempty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_sys_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.cfg_frac == FRAC_LN4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.lphy_sfrz_rx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.lphy_sfrz_tx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.unused_bk_return_clk_gate_attr == UNUSED_BK_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.unused_bk_tx_rtrn_clk_sel == BK3_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.unused_lphy_rx_clk_sel3 == UNUSED_RX_CLK_SEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.ux_tx_rtrn_clk_sel == UX7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvr_sel == UX_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_fifo_pempty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_sys_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.cfg_frac == FRAC_LN4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.lphy_sfrz_rx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.lphy_sfrz_tx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.unused_bk_return_clk_gate_attr == UNUSED_BK_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.unused_bk_tx_rtrn_clk_sel == BK3_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.unused_lphy_rx_clk_sel3 == UNUSED_RX_CLK_SEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.ux_tx_rtrn_clk_sel == UX7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvr_sel == UX_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_fifo_pempty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_sys_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e100g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_aib2_rx_st_clk_en == E200G_200G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_aib2_tx_st_clk_en == E200G_200G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_aib3_rx_st_clk_en == E200G_200G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_aib3_tx_st_clk_en == E200G_200G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_duplex_mode == E200G_200G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_fec_mode == E200G_200G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_fec_spec == E200G_200G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_mac_mode == E200G_200G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_rx_excvr_gb_ratio_mode == E200G_200G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_rx_excvr_if_fifo_mode == E200G_200G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_rx_fec_enable == E200G_200G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_rx_pcs_mode == E200G_200G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_rx_primary_use == E200G_200G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_speed_map == E200G_200G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_sup_mode == E200G_200G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_sys_clk_src == E200G_200G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_tx_excvr_gb_ratio_mode == E200G_200G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_tx_excvr_if_fifo_mode == E200G_200G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_tx_fec_enable == E200G_200G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_tx_pcs_mode == E200G_200G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_tx_primary_use == E200G_200G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.e200g_200g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.unused_bk_return_clk_gate_attr == UNUSED_BK_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.unused_bk_tx_rtrn_clk_sel == BK3_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_sel3 == UNUSED_RX_CLK_SEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvr_sel == UX_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_sys_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.cfg_frac == FRAC_LN8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_sfrz_rx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_sfrz_tx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.unused_bk_return_clk_gate_attr == UNUSED_BK_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.unused_bk_tx_rtrn_clk_sel == BK3_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_sel3 == UNUSED_RX_CLK_SEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.ux_tx_rtrn_clk_sel == UX7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvr_sel == UX_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pempty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_sys_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.cfg_frac == FRAC_LN8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_sfrz_rx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_sfrz_tx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.unused_bk_return_clk_gate_attr == UNUSED_BK_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.unused_bk_tx_rtrn_clk_sel == BK3_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.unused_lphy_rx_clk_sel3 == UNUSED_RX_CLK_SEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.ux_tx_rtrn_clk_sel == UX7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvr_sel == UX_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_fifo_pempty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_sys_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s2.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.cfg_frac == FRAC_LN8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_sfrz_rx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_sfrz_tx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.unused_bk_return_clk_gate_attr == UNUSED_BK_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.unused_bk_tx_rtrn_clk_sel == BK3_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.unused_lphy_rx_clk_sel3 == UNUSED_RX_CLK_SEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.ux_tx_rtrn_clk_sel == UX7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvr_sel == UX_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_fifo_pempty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_sys_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s3.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.cfg_frac == FRAC_LN8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.lphy_sfrz_rx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.lphy_sfrz_tx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.unused_bk_return_clk_gate_attr == UNUSED_BK_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.unused_bk_tx_rtrn_clk_sel == BK3_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.unused_lphy_rx_clk_sel3 == UNUSED_RX_CLK_SEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.ux_tx_rtrn_clk_sel == UX7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvr_sel == UX_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_rx_fifo_pempty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_rx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_rx_sys_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_tx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s4.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.cfg_frac == FRAC_LN8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.lphy_sfrz_rx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.lphy_sfrz_tx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.unused_bk_return_clk_gate_attr == UNUSED_BK_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.unused_bk_tx_rtrn_clk_sel == BK3_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.unused_lphy_rx_clk_sel3 == UNUSED_RX_CLK_SEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.ux_tx_rtrn_clk_sel == UX7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvr_sel == UX_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_rx_fifo_pempty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_rx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_rx_sys_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_tx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s5.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.cfg_frac == FRAC_LN8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.lphy_sfrz_rx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.lphy_sfrz_tx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.unused_bk_return_clk_gate_attr == UNUSED_BK_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.unused_bk_tx_rtrn_clk_sel == BK3_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.unused_lphy_rx_clk_sel3 == UNUSED_RX_CLK_SEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.ux_tx_rtrn_clk_sel == UX7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvr_sel == UX_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_rx_fifo_pempty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_rx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_rx_sys_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_tx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s6.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.cfg_frac == FRAC_LN8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.lphy_sfrz_rx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.lphy_sfrz_tx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.unused_bk_return_clk_gate_attr == UNUSED_BK_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.unused_bk_tx_rtrn_clk_sel == BK3_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.unused_lphy_rx_clk_sel3 == UNUSED_RX_CLK_SEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.ux_tx_rtrn_clk_sel == UX7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvr_sel == UX_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_rx_fifo_pempty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_rx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_rx_sys_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_tx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e200g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s7.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_aib2_rx_st_clk_en == E200G_25G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_aib2_tx_st_clk_en == E200G_25G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_aib3_rx_st_clk_en == E200G_25G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_aib3_tx_st_clk_en == E200G_25G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_duplex_mode == E200G_25G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_fec_mode == E200G_25G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_fec_spec == E200G_25G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_mac_mode == E200G_25G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_rx_excvr_gb_ratio_mode == E200G_25G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_rx_excvr_if_fifo_mode == E200G_25G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_rx_fec_enable == E200G_25G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_rx_pcs_mode == E200G_25G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_rx_primary_use == E200G_25G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_speed_map == E200G_25G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_sup_mode == E200G_25G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_sys_clk_src == E200G_25G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_tx_excvr_gb_ratio_mode == E200G_25G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_tx_excvr_if_fifo_mode == E200G_25G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_tx_fec_enable == E200G_25G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_tx_pcs_mode == E200G_25G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_tx_primary_use == E200G_25G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.e200g_25g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN1111
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.unused_bk_return_clk_gate_attr == UNUSED_BK_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.unused_bk_tx_rtrn_clk_sel == BK3_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_sel3 == UNUSED_RX_CLK_SEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvr_sel == UX_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_sys_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_aib2_rx_st_clk_en == E200G_25G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_aib2_tx_st_clk_en == E200G_25G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_aib3_rx_st_clk_en == E200G_25G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_aib3_tx_st_clk_en == E200G_25G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_duplex_mode == E200G_25G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_fec_mode == E200G_25G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_fec_spec == E200G_25G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_mac_mode == E200G_25G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_rx_excvr_gb_ratio_mode == E200G_25G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_rx_excvr_if_fifo_mode == E200G_25G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_rx_fec_enable == E200G_25G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_rx_pcs_mode == E200G_25G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_rx_primary_use == E200G_25G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_speed_map == E200G_25G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_sup_mode == E200G_25G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_sys_clk_src == E200G_25G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_tx_excvr_gb_ratio_mode == E200G_25G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_tx_excvr_if_fifo_mode == E200G_25G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_tx_fec_enable == E200G_25G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_tx_pcs_mode == E200G_25G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_tx_primary_use == E200G_25G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.e200g_25g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN1111
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.unused_bk_return_clk_gate_attr == UNUSED_BK_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.unused_bk_tx_rtrn_clk_sel == BK3_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_sel3 == UNUSED_RX_CLK_SEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvr_sel == UX_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_sys_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch1.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_aib2_rx_st_clk_en == E200G_25G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_aib2_tx_st_clk_en == E200G_25G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_aib3_rx_st_clk_en == E200G_25G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_aib3_tx_st_clk_en == E200G_25G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_duplex_mode == E200G_25G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_fec_mode == E200G_25G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_fec_spec == E200G_25G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_mac_mode == E200G_25G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_rx_excvr_gb_ratio_mode == E200G_25G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_rx_excvr_if_fifo_mode == E200G_25G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_rx_fec_enable == E200G_25G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_rx_pcs_mode == E200G_25G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_rx_primary_use == E200G_25G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_speed_map == E200G_25G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_sup_mode == E200G_25G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_sys_clk_src == E200G_25G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_tx_excvr_gb_ratio_mode == E200G_25G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_tx_excvr_if_fifo_mode == E200G_25G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_tx_fec_enable == E200G_25G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_tx_pcs_mode == E200G_25G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_tx_primary_use == E200G_25G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.e200g_25g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN1111
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.unused_bk_return_clk_gate_attr == UNUSED_BK_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.unused_bk_tx_rtrn_clk_sel == BK3_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_sel3 == UNUSED_RX_CLK_SEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvr_sel == UX_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_sys_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_aib2_rx_st_clk_en == E200G_25G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_aib2_tx_st_clk_en == E200G_25G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_aib3_rx_st_clk_en == E200G_25G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_aib3_tx_st_clk_en == E200G_25G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_duplex_mode == E200G_25G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_fec_mode == E200G_25G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_fec_spec == E200G_25G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_mac_mode == E200G_25G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_rx_excvr_gb_ratio_mode == E200G_25G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_rx_excvr_if_fifo_mode == E200G_25G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_rx_fec_enable == E200G_25G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_rx_pcs_mode == E200G_25G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_rx_primary_use == E200G_25G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_speed_map == E200G_25G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_sup_mode == E200G_25G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_sys_clk_src == E200G_25G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_tx_excvr_gb_ratio_mode == E200G_25G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_tx_excvr_if_fifo_mode == E200G_25G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_tx_fec_enable == E200G_25G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_tx_pcs_mode == E200G_25G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_tx_primary_use == E200G_25G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.e200g_25g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN1111
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.unused_bk_return_clk_gate_attr == UNUSED_BK_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.unused_bk_tx_rtrn_clk_sel == BK3_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_sel3 == UNUSED_RX_CLK_SEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvr_sel == UX_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_sys_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch3.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_aib2_rx_st_clk_en == E200G_25G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_aib2_tx_st_clk_en == E200G_25G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_aib3_rx_st_clk_en == E200G_25G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_aib3_tx_st_clk_en == E200G_25G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_duplex_mode == E200G_25G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_fec_mode == E200G_25G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_fec_spec == E200G_25G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_mac_mode == E200G_25G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_rx_excvr_gb_ratio_mode == E200G_25G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_rx_excvr_if_fifo_mode == E200G_25G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_rx_fec_enable == E200G_25G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_rx_pcs_mode == E200G_25G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_rx_primary_use == E200G_25G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_speed_map == E200G_25G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_sup_mode == E200G_25G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_sys_clk_src == E200G_25G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_tx_excvr_gb_ratio_mode == E200G_25G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_tx_excvr_if_fifo_mode == E200G_25G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_tx_fec_enable == E200G_25G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_tx_pcs_mode == E200G_25G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_tx_primary_use == E200G_25G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.e200g_25g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN1111
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.unused_bk_return_clk_gate_attr == UNUSED_BK_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.unused_bk_tx_rtrn_clk_sel == BK3_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_sel3 == UNUSED_RX_CLK_SEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvr_sel == UX_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_sys_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_aib2_rx_st_clk_en == E200G_25G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_aib2_tx_st_clk_en == E200G_25G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_aib3_rx_st_clk_en == E200G_25G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_aib3_tx_st_clk_en == E200G_25G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_duplex_mode == E200G_25G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_fec_mode == E200G_25G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_fec_spec == E200G_25G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_mac_mode == E200G_25G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_rx_excvr_gb_ratio_mode == E200G_25G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_rx_excvr_if_fifo_mode == E200G_25G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_rx_fec_enable == E200G_25G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_rx_pcs_mode == E200G_25G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_rx_primary_use == E200G_25G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_speed_map == E200G_25G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_sup_mode == E200G_25G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_sys_clk_src == E200G_25G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_tx_excvr_gb_ratio_mode == E200G_25G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_tx_excvr_if_fifo_mode == E200G_25G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_tx_fec_enable == E200G_25G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_tx_pcs_mode == E200G_25G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_tx_primary_use == E200G_25G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.e200g_25g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN1111
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.unused_bk_return_clk_gate_attr == UNUSED_BK_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.unused_bk_tx_rtrn_clk_sel == BK3_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_sel3 == UNUSED_RX_CLK_SEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvr_sel == UX_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_sys_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch5.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_aib2_rx_st_clk_en == E200G_25G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_aib2_tx_st_clk_en == E200G_25G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_aib3_rx_st_clk_en == E200G_25G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_aib3_tx_st_clk_en == E200G_25G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_duplex_mode == E200G_25G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_fec_mode == E200G_25G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_fec_spec == E200G_25G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_mac_mode == E200G_25G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_rx_excvr_gb_ratio_mode == E200G_25G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_rx_excvr_if_fifo_mode == E200G_25G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_rx_fec_enable == E200G_25G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_rx_pcs_mode == E200G_25G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_rx_primary_use == E200G_25G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_speed_map == E200G_25G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_sup_mode == E200G_25G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_sys_clk_src == E200G_25G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_tx_excvr_gb_ratio_mode == E200G_25G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_tx_excvr_if_fifo_mode == E200G_25G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_tx_fec_enable == E200G_25G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_tx_pcs_mode == E200G_25G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_tx_primary_use == E200G_25G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.e200g_25g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN1111
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.unused_bk_return_clk_gate_attr == UNUSED_BK_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.unused_bk_tx_rtrn_clk_sel == BK3_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_sel3 == UNUSED_RX_CLK_SEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvr_sel == UX_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_sys_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_aib2_rx_st_clk_en == E200G_25G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_aib2_tx_st_clk_en == E200G_25G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_aib3_rx_st_clk_en == E200G_25G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_aib3_tx_st_clk_en == E200G_25G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_duplex_mode == E200G_25G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_fec_mode == E200G_25G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_fec_spec == E200G_25G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_mac_mode == E200G_25G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_rx_excvr_gb_ratio_mode == E200G_25G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_rx_excvr_if_fifo_mode == E200G_25G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_rx_fec_enable == E200G_25G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_rx_pcs_mode == E200G_25G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_rx_primary_use == E200G_25G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_speed_map == E200G_25G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_sup_mode == E200G_25G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_sys_clk_src == E200G_25G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_tx_excvr_gb_ratio_mode == E200G_25G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_tx_excvr_if_fifo_mode == E200G_25G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_tx_fec_enable == E200G_25G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_tx_pcs_mode == E200G_25G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_tx_primary_use == E200G_25G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.e200g_25g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN1111
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.unused_bk_return_clk_gate_attr == UNUSED_BK_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.unused_bk_tx_rtrn_clk_sel == BK3_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_sel3 == UNUSED_RX_CLK_SEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvr_sel == UX_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_sys_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e25g_reg_ch7.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_aib2_rx_st_clk_en == E200G_50G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_aib2_tx_st_clk_en == E200G_50G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_aib3_rx_st_clk_en == E200G_50G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_aib3_tx_st_clk_en == E200G_50G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_duplex_mode == E200G_50G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_fec_mode == E200G_50G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_fec_spec == E200G_50G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_mac_mode == E200G_50G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_rx_excvr_gb_ratio_mode == E200G_50G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_rx_excvr_if_fifo_mode == E200G_50G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_rx_fec_enable == E200G_50G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_rx_pcs_mode == E200G_50G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_rx_primary_use == E200G_50G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_speed_map == E200G_50G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_sup_mode == E200G_50G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_sys_clk_src == E200G_50G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_tx_excvr_gb_ratio_mode == E200G_50G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_tx_excvr_if_fifo_mode == E200G_50G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_tx_fec_enable == E200G_50G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_tx_pcs_mode == E200G_50G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_tx_primary_use == E200G_50G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.e200g_50g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.unused_bk_return_clk_gate_attr == UNUSED_BK_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.unused_bk_tx_rtrn_clk_sel == BK3_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_sel3 == UNUSED_RX_CLK_SEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvr_sel == UX_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_sys_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.cfg_frac == FRAC_LN112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_sfrz_rx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_sfrz_tx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.unused_bk_return_clk_gate_attr == UNUSED_BK_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.unused_bk_tx_rtrn_clk_sel == BK3_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_sel3 == UNUSED_RX_CLK_SEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.ux_tx_rtrn_clk_sel == UX7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvr_sel == UX_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pempty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_sys_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch0.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_aib2_rx_st_clk_en == E200G_50G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_aib2_tx_st_clk_en == E200G_50G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_aib3_rx_st_clk_en == E200G_50G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_aib3_tx_st_clk_en == E200G_50G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_duplex_mode == E200G_50G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_fec_mode == E200G_50G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_fec_spec == E200G_50G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_mac_mode == E200G_50G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_rx_excvr_gb_ratio_mode == E200G_50G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_rx_excvr_if_fifo_mode == E200G_50G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_rx_fec_enable == E200G_50G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_rx_pcs_mode == E200G_50G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_rx_primary_use == E200G_50G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_speed_map == E200G_50G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_sup_mode == E200G_50G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_sys_clk_src == E200G_50G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_tx_excvr_gb_ratio_mode == E200G_50G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_tx_excvr_if_fifo_mode == E200G_50G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_tx_fec_enable == E200G_50G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_tx_pcs_mode == E200G_50G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_tx_primary_use == E200G_50G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.e200g_50g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.unused_bk_return_clk_gate_attr == UNUSED_BK_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.unused_bk_tx_rtrn_clk_sel == BK3_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_sel3 == UNUSED_RX_CLK_SEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvr_sel == UX_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_sys_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.cfg_frac == FRAC_LN112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.lphy_sfrz_rx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.lphy_sfrz_tx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.unused_bk_return_clk_gate_attr == UNUSED_BK_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.unused_bk_tx_rtrn_clk_sel == BK3_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_sel3 == UNUSED_RX_CLK_SEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.ux_tx_rtrn_clk_sel == UX7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvr_sel == UX_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pempty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_sys_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch2.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_aib2_rx_st_clk_en == E200G_50G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_aib2_tx_st_clk_en == E200G_50G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_aib3_rx_st_clk_en == E200G_50G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_aib3_tx_st_clk_en == E200G_50G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_duplex_mode == E200G_50G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_fec_mode == E200G_50G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_fec_spec == E200G_50G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_mac_mode == E200G_50G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_rx_excvr_gb_ratio_mode == E200G_50G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_rx_excvr_if_fifo_mode == E200G_50G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_rx_fec_enable == E200G_50G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_rx_pcs_mode == E200G_50G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_rx_primary_use == E200G_50G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_speed_map == E200G_50G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_sup_mode == E200G_50G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_sys_clk_src == E200G_50G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_tx_excvr_gb_ratio_mode == E200G_50G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_tx_excvr_if_fifo_mode == E200G_50G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_tx_fec_enable == E200G_50G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_tx_pcs_mode == E200G_50G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_tx_primary_use == E200G_50G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.e200g_50g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.unused_bk_return_clk_gate_attr == UNUSED_BK_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.unused_bk_tx_rtrn_clk_sel == BK3_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_sel3 == UNUSED_RX_CLK_SEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvr_sel == UX_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_sys_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.cfg_frac == FRAC_LN112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_sfrz_rx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_sfrz_tx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.unused_bk_return_clk_gate_attr == UNUSED_BK_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.unused_bk_tx_rtrn_clk_sel == BK3_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_sel3 == UNUSED_RX_CLK_SEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.ux_tx_rtrn_clk_sel == UX7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvr_sel == UX_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pempty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_sys_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch4.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_aib2_rx_st_clk_en == E200G_50G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_aib2_tx_st_clk_en == E200G_50G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_aib3_rx_st_clk_en == E200G_50G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_aib3_tx_st_clk_en == E200G_50G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_duplex_mode == E200G_50G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_fec_mode == E200G_50G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_fec_spec == E200G_50G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_mac_mode == E200G_50G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_rx_excvr_gb_ratio_mode == E200G_50G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_rx_excvr_if_fifo_mode == E200G_50G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_rx_fec_enable == E200G_50G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_rx_pcs_mode == E200G_50G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_rx_primary_use == E200G_50G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_speed_map == E200G_50G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_sup_mode == E200G_50G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_sys_clk_src == E200G_50G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_tx_excvr_gb_ratio_mode == E200G_50G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_tx_excvr_if_fifo_mode == E200G_50G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_tx_fec_enable == E200G_50G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_tx_pcs_mode == E200G_50G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_tx_primary_use == E200G_50G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.e200g_50g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.unused_bk_return_clk_gate_attr == UNUSED_BK_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.unused_bk_tx_rtrn_clk_sel == BK3_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_sel3 == UNUSED_RX_CLK_SEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvr_sel == UX_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_sys_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.cfg_frac == FRAC_LN112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.lphy_sfrz_rx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.lphy_sfrz_tx_bond_sel == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.unused_bk_return_clk_gate_attr == UNUSED_BK_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.unused_bk_tx_rtrn_clk_sel == BK3_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_sel3 == UNUSED_RX_CLK_SEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.ux_tx_rtrn_clk_sel == UX7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvr_sel == UX_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pempty == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_sys_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pfull == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e200g_top.u_gdr_e200g_lphy.gdr_e200g_lphy_e50g_reg_ch6.gdr_e200g_lphy_e25g_reg_base_s1.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib1_tx_st0_adapt_rc_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib1_tx_st10_adapt_rc_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib1_tx_st11_adapt_rc_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib1_tx_st12_adapt_rc_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib1_tx_st13_adapt_rc_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib1_tx_st14_adapt_rc_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib1_tx_st15_adapt_rc_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib1_tx_st16_adapt_rc_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib1_tx_st17_adapt_rc_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib1_tx_st1_adapt_rc_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib1_tx_st2_adapt_rc_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib1_tx_st3_adapt_rc_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib1_tx_st4_adapt_rc_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib1_tx_st5_adapt_rc_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib1_tx_st6_adapt_rc_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib1_tx_st7_adapt_rc_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib1_tx_st8_adapt_rc_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib1_tx_st9_adapt_rc_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib2_rx_st0_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib2_rx_st10_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib2_rx_st11_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib2_rx_st12_adapt_rc_clk_hz == 37'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib2_rx_st13_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib2_rx_st14_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib2_rx_st15_adapt_rc_clk_hz == 37'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib2_rx_st16_adapt_rc_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib2_rx_st17_adapt_rc_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib2_rx_st1_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib2_rx_st2_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib2_rx_st3_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib2_rx_st4_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib2_rx_st5_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib2_rx_st6_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib2_rx_st7_adapt_rc_clk_hz == 37'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib2_rx_st8_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib2_rx_st9_adapt_rc_clk_hz == 37'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib2_tx_st0_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib2_tx_st10_adapt_rc_clk_hz == 37'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib2_tx_st11_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib2_tx_st12_adapt_rc_clk_hz == 37'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib2_tx_st13_adapt_rc_clk_hz == 37'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib2_tx_st14_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib2_tx_st15_adapt_rc_clk_hz == 37'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib2_tx_st16_adapt_rc_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib2_tx_st17_adapt_rc_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib2_tx_st1_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib2_tx_st2_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib2_tx_st3_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib2_tx_st4_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib2_tx_st5_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib2_tx_st6_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib2_tx_st7_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib2_tx_st8_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib2_tx_st9_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib3_rx_st0_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib3_rx_st10_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib3_rx_st11_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib3_rx_st12_adapt_rc_clk_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib3_rx_st13_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib3_rx_st14_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib3_rx_st15_adapt_rc_clk_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib3_rx_st1_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib3_rx_st2_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib3_rx_st3_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib3_rx_st4_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib3_rx_st5_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib3_rx_st6_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib3_rx_st7_adapt_rc_clk_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib3_rx_st8_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib3_rx_st9_adapt_rc_clk_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib3_tx_st0_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib3_tx_st10_adapt_rc_clk_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib3_tx_st11_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib3_tx_st12_adapt_rc_clk_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib3_tx_st13_adapt_rc_clk_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib3_tx_st14_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib3_tx_st15_adapt_rc_clk_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib3_tx_st1_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib3_tx_st2_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib3_tx_st3_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib3_tx_st4_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib3_tx_st5_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib3_tx_st6_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib3_tx_st7_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib3_tx_st8_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib3_tx_st9_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib_esys_adapt_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib_transfer_ptp0_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.aib_transfer_ptp1_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.bk0_return_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.bk0_rx_user_xcvr_rc_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.bk0_rx_user_xcvr_rc_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.bk0_rxword_xcvr_rc_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.bk0_tx_line_rate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.bk0_tx_user_xcvr_rc_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.bk0_tx_user_xcvr_rc_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.bk0_txword_xcvr_rc_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.bk1_return_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.bk1_rx_user_xcvr_rc_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.bk1_rx_user_xcvr_rc_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.bk1_rxword_xcvr_rc_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.bk1_tx_user_xcvr_rc_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.bk1_tx_user_xcvr_rc_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.bk1_txword_xcvr_rc_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.bk2_return_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.bk2_rx_user_xcvr_rc_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.bk2_rx_user_xcvr_rc_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.bk2_rxword_xcvr_rc_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.bk2_tx_user_xcvr_rc_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.bk2_tx_user_xcvr_rc_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.bk2_txword_xcvr_rc_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.bk3_return_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.bk3_rx_user_xcvr_rc_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.bk3_rx_user_xcvr_rc_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.bk3_rxword_xcvr_rc_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.bk3_tx_user_xcvr_rc_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.bk3_tx_user_xcvr_rc_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.bk3_txword_xcvr_rc_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.block_enable == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_aib2_rx_st_clk_en == E400G_100G_0_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_aib2_tx_st_clk_en == E400G_100G_0_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_aib3_rx_st_clk_en == E400G_100G_0_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_aib3_tx_st_clk_en == E400G_100G_0_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_aibif_data_valid == E400G_100G_0_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_duplex_mode == E400G_100G_0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_fec_clk_src == E400G_100G_0_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_fec_error == E400G_100G_0_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_fec_mode == E400G_100G_0_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_fec_spec == E400G_100G_0_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_lpbk_mode == E400G_100G_0_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_flow_control == E400G_100G_0_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_flow_control_holdoff_mode == E400G_100G_0_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_link_fault_mode == E400G_100G_0_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_mode == E400G_100G_0_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_rx_ptp_phy_lane_num == E400G_100G_0_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_tx_ipg_size == E400G_100G_0_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_tx_ptp_phy_lane_num == E400G_100G_0_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_pcs_ber_mon_mode == E400G_100G_0_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_pcs_pcs_ber_mon_mode == E400G_100G_0_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_ptp_mode == E400G_100G_0_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_rx_aib_if_fifo_mode == E400G_100G_0_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_rx_excvr_gb_ratio_mode == E400G_100G_0_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_rx_excvr_if_fifo_mode == E400G_100G_0_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_rx_fec_enable == E400G_100G_0_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_rx_master_bond_chnl == E400G_100G_0_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_rx_pcs_mode == E400G_100G_0_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_rx_primary_use == E400G_100G_0_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_rx_xcvr_width == E400G_100G_0_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_speed_map == E400G_100G_0_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_sup_mode == E400G_100G_0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_sys_clk_src == E400G_100G_0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_tx_aib_if_fifo_mode == E400G_100G_0_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_tx_excvr_gb_ratio_mode == E400G_100G_0_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_tx_excvr_if_fifo_mode == E400G_100G_0_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_tx_fec_enable == E400G_100G_0_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_tx_master_bond_chnl == E400G_100G_0_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_tx_pcs_mode == E400G_100G_0_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_tx_primary_use == E400G_100G_0_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_tx_xcvr_width == E400G_100G_0_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_xcvr_mode == E400G_100G_0_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_0_xcvr_type == E400G_100G_0_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_aib2_rx_st_clk_en == E400G_100G_1_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_aib2_tx_st_clk_en == E400G_100G_1_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_aib3_rx_st_clk_en == E400G_100G_1_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_aib3_tx_st_clk_en == E400G_100G_1_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_aibif_data_valid == E400G_100G_1_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_duplex_mode == E400G_100G_1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_fec_clk_src == E400G_100G_1_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_fec_error == E400G_100G_1_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_fec_mode == E400G_100G_1_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_fec_spec == E400G_100G_1_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_lpbk_mode == E400G_100G_1_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_flow_control == E400G_100G_1_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_flow_control_holdoff_mode == E400G_100G_1_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_link_fault_mode == E400G_100G_1_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_mode == E400G_100G_1_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_rx_ptp_phy_lane_num == E400G_100G_1_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_tx_ipg_size == E400G_100G_1_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_tx_ptp_phy_lane_num == E400G_100G_1_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_pcs_ber_mon_mode == E400G_100G_1_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_pcs_pcs_ber_mon_mode == E400G_100G_1_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_ptp_mode == E400G_100G_1_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_rx_aib_if_fifo_mode == E400G_100G_1_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_rx_excvr_gb_ratio_mode == E400G_100G_1_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_rx_excvr_if_fifo_mode == E400G_100G_1_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_rx_fec_enable == E400G_100G_1_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_rx_master_bond_chnl == E400G_100G_1_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_rx_pcs_mode == E400G_100G_1_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_rx_primary_use == E400G_100G_1_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_rx_xcvr_width == E400G_100G_1_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_speed_map == E400G_100G_1_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_sup_mode == E400G_100G_1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_sys_clk_src == E400G_100G_1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_tx_aib_if_fifo_mode == E400G_100G_1_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_tx_excvr_gb_ratio_mode == E400G_100G_1_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_tx_excvr_if_fifo_mode == E400G_100G_1_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_tx_fec_enable == E400G_100G_1_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_tx_master_bond_chnl == E400G_100G_1_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_tx_pcs_mode == E400G_100G_1_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_tx_primary_use == E400G_100G_1_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_tx_xcvr_width == E400G_100G_1_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_xcvr_mode == E400G_100G_1_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_1_xcvr_type == E400G_100G_1_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_aib2_rx_st_clk_en == E400G_100G_2_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_aib2_tx_st_clk_en == E400G_100G_2_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_aib3_rx_st_clk_en == E400G_100G_2_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_aib3_tx_st_clk_en == E400G_100G_2_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_aibif_data_valid == E400G_100G_2_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_duplex_mode == E400G_100G_2_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_fec_clk_src == E400G_100G_2_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_fec_error == E400G_100G_2_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_fec_mode == E400G_100G_2_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_fec_spec == E400G_100G_2_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_lpbk_mode == E400G_100G_2_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_flow_control == E400G_100G_2_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_flow_control_holdoff_mode == E400G_100G_2_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_link_fault_mode == E400G_100G_2_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_mode == E400G_100G_2_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_rx_ptp_phy_lane_num == E400G_100G_2_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_tx_ipg_size == E400G_100G_2_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_tx_ptp_phy_lane_num == E400G_100G_2_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_pcs_ber_mon_mode == E400G_100G_2_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_pcs_pcs_ber_mon_mode == E400G_100G_2_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_ptp_mode == E400G_100G_2_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_rx_aib_if_fifo_mode == E400G_100G_2_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_rx_excvr_gb_ratio_mode == E400G_100G_2_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_rx_excvr_if_fifo_mode == E400G_100G_2_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_rx_fec_enable == E400G_100G_2_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_rx_master_bond_chnl == E400G_100G_2_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_rx_pcs_mode == E400G_100G_2_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_rx_primary_use == E400G_100G_2_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_rx_xcvr_width == E400G_100G_2_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_speed_map == E400G_100G_2_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_sup_mode == E400G_100G_2_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_sys_clk_src == E400G_100G_2_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_tx_aib_if_fifo_mode == E400G_100G_2_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_tx_excvr_gb_ratio_mode == E400G_100G_2_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_tx_excvr_if_fifo_mode == E400G_100G_2_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_tx_fec_enable == E400G_100G_2_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_tx_master_bond_chnl == E400G_100G_2_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_tx_pcs_mode == E400G_100G_2_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_tx_primary_use == E400G_100G_2_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_tx_xcvr_width == E400G_100G_2_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_xcvr_mode == E400G_100G_2_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_2_xcvr_type == E400G_100G_2_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_aib2_rx_st_clk_en == E400G_100G_3_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_aib2_tx_st_clk_en == E400G_100G_3_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_aib3_rx_st_clk_en == E400G_100G_3_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_aib3_tx_st_clk_en == E400G_100G_3_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_aibif_data_valid == E400G_100G_3_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_duplex_mode == E400G_100G_3_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_fec_clk_src == E400G_100G_3_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_fec_error == E400G_100G_3_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_fec_mode == E400G_100G_3_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_fec_spec == E400G_100G_3_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_lpbk_mode == E400G_100G_3_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_flow_control == E400G_100G_3_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_flow_control_holdoff_mode == E400G_100G_3_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_link_fault_mode == E400G_100G_3_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_mode == E400G_100G_3_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_rx_ptp_phy_lane_num == E400G_100G_3_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_tx_ipg_size == E400G_100G_3_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_tx_ptp_phy_lane_num == E400G_100G_3_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_pcs_ber_mon_mode == E400G_100G_3_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_pcs_pcs_ber_mon_mode == E400G_100G_3_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_ptp_mode == E400G_100G_3_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_rx_aib_if_fifo_mode == E400G_100G_3_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_rx_excvr_gb_ratio_mode == E400G_100G_3_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_rx_excvr_if_fifo_mode == E400G_100G_3_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_rx_fec_enable == E400G_100G_3_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_rx_master_bond_chnl == E400G_100G_3_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_rx_pcs_mode == E400G_100G_3_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_rx_primary_use == E400G_100G_3_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_rx_xcvr_width == E400G_100G_3_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_speed_map == E400G_100G_3_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_sup_mode == E400G_100G_3_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_sys_clk_src == E400G_100G_3_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_tx_aib_if_fifo_mode == E400G_100G_3_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_tx_excvr_gb_ratio_mode == E400G_100G_3_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_tx_excvr_if_fifo_mode == E400G_100G_3_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_tx_fec_enable == E400G_100G_3_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_tx_master_bond_chnl == E400G_100G_3_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_tx_pcs_mode == E400G_100G_3_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_tx_primary_use == E400G_100G_3_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_tx_xcvr_width == E400G_100G_3_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_xcvr_mode == E400G_100G_3_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_100g_3_xcvr_type == E400G_100G_3_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_aib2_rx_st_clk_en == E400G_150G_0_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_aib2_tx_st_clk_en == E400G_150G_0_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_aib3_rx_st_clk_en == E400G_150G_0_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_aib3_tx_st_clk_en == E400G_150G_0_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_aibif_data_valid == E400G_150G_0_AIBIF_DATA_VALID_CUSTOM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_duplex_mode == E400G_150G_0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_fec_mode == E400G_150G_0_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_fec_spec == E400G_150G_0_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_lpbk_mode == E400G_150G_0_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_mac_mode == E400G_150G_0_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_pcs_ber_mon_mode == E400G_150G_0_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_ptp_mode == E400G_150G_0_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_rx_aib_if_fifo_mode == E400G_150G_0_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_rx_excvr_gb_ratio_mode == E400G_150G_0_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_rx_excvr_if_fifo_mode == E400G_150G_0_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_rx_fec_enable == E400G_150G_0_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_rx_master_bond_chnl == E400G_150G_0_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_rx_pcs_mode == E400G_150G_0_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_rx_primary_use == E400G_150G_0_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_rx_xcvr_width == E400G_150G_0_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_speed_map == E400G_150G_0_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_sup_mode == E400G_150G_0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_sys_clk_src == E400G_150G_0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_tx_aib_if_fifo_mode == E400G_150G_0_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_tx_excvr_gb_ratio_mode == E400G_150G_0_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_tx_excvr_if_fifo_mode == E400G_150G_0_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_tx_fec_enable == E400G_150G_0_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_tx_master_bond_chnl == E400G_150G_0_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_tx_pcs_mode == E400G_150G_0_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_tx_primary_use == E400G_150G_0_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_tx_xcvr_width == E400G_150G_0_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_xcvr_mode == E400G_150G_0_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_0_xcvr_type == E400G_150G_0_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_aib2_rx_st_clk_en == E400G_150G_1_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_aib2_tx_st_clk_en == E400G_150G_1_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_aib3_rx_st_clk_en == E400G_150G_1_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_aib3_tx_st_clk_en == E400G_150G_1_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_aibif_data_valid == E400G_150G_1_AIBIF_DATA_VALID_40G_CUSTOM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_duplex_mode == E400G_150G_1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_fec_mode == E400G_150G_1_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_fec_spec == E400G_150G_1_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_lpbk_mode == E400G_150G_1_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_mac_mode == E400G_150G_1_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_pcs_ber_mon_mode == E400G_150G_1_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_ptp_mode == E400G_150G_1_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_rx_aib_if_fifo_mode == E400G_150G_1_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_rx_excvr_gb_ratio_mode == E400G_150G_1_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_rx_excvr_if_fifo_mode == E400G_150G_1_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_rx_fec_enable == E400G_150G_1_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_rx_master_bond_chnl == E400G_150G_1_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_rx_pcs_mode == E400G_150G_1_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_rx_primary_use == E400G_150G_1_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_rx_xcvr_width == E400G_150G_1_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_speed_map == E400G_150G_1_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_sup_mode == E400G_150G_1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_sys_clk_src == E400G_150G_1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_tx_aib_if_fifo_mode == E400G_150G_1_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_tx_excvr_gb_ratio_mode == E400G_150G_1_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_tx_excvr_if_fifo_mode == E400G_150G_1_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_tx_fec_enable == E400G_150G_1_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_tx_master_bond_chnl == E400G_150G_1_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_tx_pcs_mode == E400G_150G_1_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_tx_primary_use == E400G_150G_1_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_tx_xcvr_width == E400G_150G_1_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_xcvr_mode == E400G_150G_1_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_1_xcvr_type == E400G_150G_1_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_aib2_rx_st_clk_en == E400G_150G_2_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_aib2_tx_st_clk_en == E400G_150G_2_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_aib3_rx_st_clk_en == E400G_150G_2_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_aib3_tx_st_clk_en == E400G_150G_2_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_aibif_data_valid == E400G_150G_2_AIBIF_DATA_VALID_CUSTOM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_duplex_mode == E400G_150G_2_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_fec_mode == E400G_150G_2_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_fec_spec == E400G_150G_2_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_lpbk_mode == E400G_150G_2_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_mac_mode == E400G_150G_2_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_pcs_ber_mon_mode == E400G_150G_2_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_ptp_mode == E400G_150G_2_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_rx_aib_if_fifo_mode == E400G_150G_2_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_rx_excvr_gb_ratio_mode == E400G_150G_2_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_rx_excvr_if_fifo_mode == E400G_150G_2_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_rx_fec_enable == E400G_150G_2_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_rx_master_bond_chnl == E400G_150G_2_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_rx_pcs_mode == E400G_150G_2_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_rx_primary_use == E400G_150G_2_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_rx_xcvr_width == E400G_150G_2_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_speed_map == E400G_150G_2_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_sup_mode == E400G_150G_2_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_sys_clk_src == E400G_150G_2_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_tx_aib_if_fifo_mode == E400G_150G_2_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_tx_excvr_gb_ratio_mode == E400G_150G_2_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_tx_excvr_if_fifo_mode == E400G_150G_2_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_tx_fec_enable == E400G_150G_2_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_tx_master_bond_chnl == E400G_150G_2_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_tx_pcs_mode == E400G_150G_2_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_tx_primary_use == E400G_150G_2_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_tx_xcvr_width == E400G_150G_2_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_xcvr_mode == E400G_150G_2_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_2_xcvr_type == E400G_150G_2_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_aib2_rx_st_clk_en == E400G_150G_3_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_aib2_tx_st_clk_en == E400G_150G_3_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_aib3_rx_st_clk_en == E400G_150G_3_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_aib3_tx_st_clk_en == E400G_150G_3_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_aibif_data_valid == E400G_150G_3_AIBIF_DATA_VALID_CUSTOM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_duplex_mode == E400G_150G_3_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_fec_mode == E400G_150G_3_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_fec_spec == E400G_150G_3_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_lpbk_mode == E400G_150G_3_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_mac_mode == E400G_150G_3_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_pcs_ber_mon_mode == E400G_150G_3_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_ptp_mode == E400G_150G_3_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_rx_aib_if_fifo_mode == E400G_150G_3_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_rx_excvr_gb_ratio_mode == E400G_150G_3_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_rx_excvr_if_fifo_mode == E400G_150G_3_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_rx_fec_enable == E400G_150G_3_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_rx_master_bond_chnl == E400G_150G_3_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_rx_pcs_mode == E400G_150G_3_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_rx_primary_use == E400G_150G_3_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_rx_xcvr_width == E400G_150G_3_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_speed_map == E400G_150G_3_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_sup_mode == E400G_150G_3_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_sys_clk_src == E400G_150G_3_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_tx_aib_if_fifo_mode == E400G_150G_3_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_tx_excvr_gb_ratio_mode == E400G_150G_3_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_tx_excvr_if_fifo_mode == E400G_150G_3_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_tx_fec_enable == E400G_150G_3_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_tx_master_bond_chnl == E400G_150G_3_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_tx_pcs_mode == E400G_150G_3_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_tx_primary_use == E400G_150G_3_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_tx_xcvr_width == E400G_150G_3_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_xcvr_mode == E400G_150G_3_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_150g_3_xcvr_type == E400G_150G_3_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_aib2_rx_st_clk_en == E400G_200G_0_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_aib2_tx_st_clk_en == E400G_200G_0_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_aib3_rx_st_clk_en == E400G_200G_0_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_aib3_tx_st_clk_en == E400G_200G_0_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_aibif_data_valid == E400G_200G_0_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_duplex_mode == E400G_200G_0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_fec_clk_src == E400G_200G_0_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_fec_error == E400G_200G_0_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_fec_mode == E400G_200G_0_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_fec_spec == E400G_200G_0_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_lpbk_mode == E400G_200G_0_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_flow_control == E400G_200G_0_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_flow_control_holdoff_mode == E400G_200G_0_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_link_fault_mode == E400G_200G_0_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_mode == E400G_200G_0_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_rx_ptp_phy_lane_num == E400G_200G_0_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_tx_ipg_size == E400G_200G_0_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_tx_ptp_phy_lane_num == E400G_200G_0_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_pcs_ber_mon_mode == E400G_200G_0_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_pcs_pcs_ber_mon_mode == E400G_200G_0_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_ptp_mode == E400G_200G_0_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_rx_aib_if_fifo_mode == E400G_200G_0_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_rx_excvr_gb_ratio_mode == E400G_200G_0_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_rx_excvr_if_fifo_mode == E400G_200G_0_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_rx_fec_enable == E400G_200G_0_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_rx_master_bond_chnl == E400G_200G_0_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_rx_pcs_mode == E400G_200G_0_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_rx_primary_use == E400G_200G_0_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_rx_xcvr_width == E400G_200G_0_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_speed_map == E400G_200G_0_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_sup_mode == E400G_200G_0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_sys_clk_src == E400G_200G_0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_tx_aib_if_fifo_mode == E400G_200G_0_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_tx_excvr_gb_ratio_mode == E400G_200G_0_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_tx_excvr_if_fifo_mode == E400G_200G_0_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_tx_fec_enable == E400G_200G_0_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_tx_master_bond_chnl == E400G_200G_0_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_tx_pcs_mode == E400G_200G_0_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_tx_primary_use == E400G_200G_0_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_tx_xcvr_width == E400G_200G_0_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_xcvr_mode == E400G_200G_0_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_0_xcvr_type == E400G_200G_0_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_aib2_rx_st_clk_en == E400G_200G_1_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_aib2_tx_st_clk_en == E400G_200G_1_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_aib3_rx_st_clk_en == E400G_200G_1_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_aib3_tx_st_clk_en == E400G_200G_1_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_aibif_data_valid == E400G_200G_1_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_duplex_mode == E400G_200G_1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_fec_clk_src == E400G_200G_1_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_fec_error == E400G_200G_1_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_fec_mode == E400G_200G_1_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_fec_spec == E400G_200G_1_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_lpbk_mode == E400G_200G_1_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_flow_control == E400G_200G_1_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_flow_control_holdoff_mode == E400G_200G_1_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_link_fault_mode == E400G_200G_1_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_mode == E400G_200G_1_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_rx_ptp_phy_lane_num == E400G_200G_1_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_tx_ipg_size == E400G_200G_1_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_tx_ptp_phy_lane_num == E400G_200G_1_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_pcs_ber_mon_mode == E400G_200G_1_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_pcs_pcs_ber_mon_mode == E400G_200G_1_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_ptp_mode == E400G_200G_1_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_rx_aib_if_fifo_mode == E400G_200G_1_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_rx_excvr_gb_ratio_mode == E400G_200G_1_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_rx_excvr_if_fifo_mode == E400G_200G_1_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_rx_fec_enable == E400G_200G_1_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_rx_master_bond_chnl == E400G_200G_1_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_rx_pcs_mode == E400G_200G_1_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_rx_primary_use == E400G_200G_1_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_rx_xcvr_width == E400G_200G_1_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_speed_map == E400G_200G_1_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_sup_mode == E400G_200G_1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_sys_clk_src == E400G_200G_1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_tx_aib_if_fifo_mode == E400G_200G_1_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_tx_excvr_gb_ratio_mode == E400G_200G_1_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_tx_excvr_if_fifo_mode == E400G_200G_1_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_tx_fec_enable == E400G_200G_1_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_tx_master_bond_chnl == E400G_200G_1_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_tx_pcs_mode == E400G_200G_1_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_tx_primary_use == E400G_200G_1_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_tx_xcvr_width == E400G_200G_1_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_xcvr_mode == E400G_200G_1_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_200g_1_xcvr_type == E400G_200G_1_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_aib2_rx_st_clk_en == E400G_25G_0_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_aib2_tx_st_clk_en == E400G_25G_0_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_aib3_rx_st_clk_en == E400G_25G_0_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_aib3_tx_st_clk_en == E400G_25G_0_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_aibif_data_valid == E400G_25G_0_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_duplex_mode == E400G_25G_0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_fec_clk_src == E400G_25G_0_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_fec_error == E400G_25G_0_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_fec_mode == E400G_25G_0_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_fec_spec == E400G_25G_0_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_lpbk_mode == E400G_25G_0_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_flow_control == E400G_25G_0_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_flow_control_holdoff_mode == E400G_25G_0_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_link_fault_mode == E400G_25G_0_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_mode == E400G_25G_0_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_rx_ptp_phy_lane_num == E400G_25G_0_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_tx_ipg_size == E400G_25G_0_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_tx_ptp_phy_lane_num == E400G_25G_0_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_pcs_ber_mon_mode == E400G_25G_0_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_pcs_pcs_ber_mon_mode == E400G_25G_0_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_ptp_mode == E400G_25G_0_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_rx_aib_if_fifo_mode == E400G_25G_0_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_rx_excvr_gb_ratio_mode == E400G_25G_0_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_rx_excvr_if_fifo_mode == E400G_25G_0_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_rx_fec_enable == E400G_25G_0_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_rx_master_bond_chnl == E400G_25G_0_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_rx_pcs_mode == E400G_25G_0_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_rx_primary_use == E400G_25G_0_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_rx_xcvr_width == E400G_25G_0_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_speed_map == E400G_25G_0_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_sup_mode == E400G_25G_0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_sys_clk_src == E400G_25G_0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_tx_aib_if_fifo_mode == E400G_25G_0_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_tx_excvr_gb_ratio_mode == E400G_25G_0_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_tx_excvr_if_fifo_mode == E400G_25G_0_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_tx_fec_enable == E400G_25G_0_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_tx_master_bond_chnl == E400G_25G_0_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_tx_pcs_mode == E400G_25G_0_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_tx_primary_use == E400G_25G_0_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_tx_xcvr_width == E400G_25G_0_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_xcvr_mode == E400G_25G_0_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_0_xcvr_type == E400G_25G_0_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_aib2_rx_st_clk_en == E400G_25G_10_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_aib2_tx_st_clk_en == E400G_25G_10_AIB2_TX_ST_CLK_EN_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_aib3_rx_st_clk_en == E400G_25G_10_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_aib3_tx_st_clk_en == E400G_25G_10_AIB3_TX_ST_CLK_EN_TX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_aibif_data_valid == E400G_25G_10_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_duplex_mode == E400G_25G_10_DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_fec_clk_src == E400G_25G_10_FEC_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_fec_error == E400G_25G_10_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_fec_mode == E400G_25G_10_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_fec_spec == E400G_25G_10_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_lpbk_mode == E400G_25G_10_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_flow_control == E400G_25G_10_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_flow_control_holdoff_mode == E400G_25G_10_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_link_fault_mode == E400G_25G_10_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_mode == E400G_25G_10_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_rx_ptp_phy_lane_num == E400G_25G_10_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_tx_ipg_size == E400G_25G_10_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_tx_ptp_phy_lane_num == E400G_25G_10_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_pcs_ber_mon_mode == E400G_25G_10_PCS_BER_MON_MODE_10G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_pcs_pcs_ber_mon_mode == E400G_25G_10_PCS_PCS_BER_MON_MODE_10G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_ptp_mode == E400G_25G_10_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_rx_aib_if_fifo_mode == E400G_25G_10_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_rx_excvr_gb_ratio_mode == E400G_25G_10_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_rx_excvr_if_fifo_mode == E400G_25G_10_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_rx_fec_enable == E400G_25G_10_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_rx_master_bond_chnl == E400G_25G_10_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_rx_pcs_mode == E400G_25G_10_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_rx_primary_use == E400G_25G_10_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_rx_xcvr_width == E400G_25G_10_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_speed_map == E400G_25G_10_SPEED_MAP_MAP_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_sup_mode == E400G_25G_10_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_sys_clk_src == E400G_25G_10_SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_tx_aib_if_fifo_mode == E400G_25G_10_TX_AIB_IF_FIFO_MODE_PHASECOMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_tx_datarate == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_tx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_tx_excvr_gb_ratio_mode == E400G_25G_10_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_tx_excvr_if_fifo_mode == E400G_25G_10_TX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_tx_fec_enable == E400G_25G_10_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_tx_master_bond_chnl == E400G_25G_10_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_tx_pcs_mode == E400G_25G_10_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_tx_primary_use == E400G_25G_10_TX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_tx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_tx_word_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_tx_xcvr_width == E400G_25G_10_TX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_xcvr_mode == E400G_25G_10_XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_10_xcvr_type == E400G_25G_10_XCVR_TYPE_UX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_aib2_rx_st_clk_en == E400G_25G_11_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_aib2_tx_st_clk_en == E400G_25G_11_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_aib3_rx_st_clk_en == E400G_25G_11_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_aib3_tx_st_clk_en == E400G_25G_11_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_aibif_data_valid == E400G_25G_11_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_duplex_mode == E400G_25G_11_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_fec_clk_src == E400G_25G_11_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_fec_error == E400G_25G_11_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_fec_mode == E400G_25G_11_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_fec_spec == E400G_25G_11_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_lpbk_mode == E400G_25G_11_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_flow_control == E400G_25G_11_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_flow_control_holdoff_mode == E400G_25G_11_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_link_fault_mode == E400G_25G_11_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_mode == E400G_25G_11_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_rx_ptp_phy_lane_num == E400G_25G_11_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_tx_ipg_size == E400G_25G_11_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_tx_ptp_phy_lane_num == E400G_25G_11_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_pcs_ber_mon_mode == E400G_25G_11_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_pcs_pcs_ber_mon_mode == E400G_25G_11_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_ptp_mode == E400G_25G_11_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_rx_aib_if_fifo_mode == E400G_25G_11_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_rx_excvr_gb_ratio_mode == E400G_25G_11_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_rx_excvr_if_fifo_mode == E400G_25G_11_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_rx_fec_enable == E400G_25G_11_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_rx_master_bond_chnl == E400G_25G_11_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_rx_pcs_mode == E400G_25G_11_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_rx_primary_use == E400G_25G_11_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_rx_xcvr_width == E400G_25G_11_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_speed_map == E400G_25G_11_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_sup_mode == E400G_25G_11_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_sys_clk_src == E400G_25G_11_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_tx_aib_if_fifo_mode == E400G_25G_11_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_tx_excvr_gb_ratio_mode == E400G_25G_11_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_tx_excvr_if_fifo_mode == E400G_25G_11_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_tx_fec_enable == E400G_25G_11_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_tx_master_bond_chnl == E400G_25G_11_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_tx_pcs_mode == E400G_25G_11_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_tx_primary_use == E400G_25G_11_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_tx_xcvr_width == E400G_25G_11_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_xcvr_mode == E400G_25G_11_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_11_xcvr_type == E400G_25G_11_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_aib2_rx_st_clk_en == E400G_25G_12_AIB2_RX_ST_CLK_EN_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_aib2_tx_st_clk_en == E400G_25G_12_AIB2_TX_ST_CLK_EN_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_aib3_rx_st_clk_en == E400G_25G_12_AIB3_RX_ST_CLK_EN_RX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_aib3_tx_st_clk_en == E400G_25G_12_AIB3_TX_ST_CLK_EN_TX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_aibif_data_valid == E400G_25G_12_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_duplex_mode == E400G_25G_12_DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_fec_clk_src == E400G_25G_12_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_fec_error == E400G_25G_12_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_fec_mode == E400G_25G_12_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_fec_spec == E400G_25G_12_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_lpbk_mode == E400G_25G_12_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_flow_control == E400G_25G_12_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_flow_control_holdoff_mode == E400G_25G_12_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_link_fault_mode == E400G_25G_12_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_mode == E400G_25G_12_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_rx_ptp_phy_lane_num == E400G_25G_12_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_tx_ipg_size == E400G_25G_12_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_tx_ptp_phy_lane_num == E400G_25G_12_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_pcs_ber_mon_mode == E400G_25G_12_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_pcs_pcs_ber_mon_mode == E400G_25G_12_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_ptp_mode == E400G_25G_12_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_rx_aib_if_fifo_mode == E400G_25G_12_RX_AIB_IF_FIFO_MODE_REGISTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_rx_datarate == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_rx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_rx_excvr_gb_ratio_mode == E400G_25G_12_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_rx_excvr_if_fifo_mode == E400G_25G_12_RX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_rx_fec_enable == E400G_25G_12_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_rx_master_bond_chnl == E400G_25G_12_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_rx_pcs_mode == E400G_25G_12_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_rx_primary_use == E400G_25G_12_RX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_rx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_rx_word_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_rx_xcvr_width == E400G_25G_12_RX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_speed_map == E400G_25G_12_SPEED_MAP_MAP_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_sup_mode == E400G_25G_12_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_sys_clk_src == E400G_25G_12_SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_tx_aib_if_fifo_mode == E400G_25G_12_TX_AIB_IF_FIFO_MODE_PHASECOMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_tx_datarate == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_tx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_tx_excvr_gb_ratio_mode == E400G_25G_12_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_tx_excvr_if_fifo_mode == E400G_25G_12_TX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_tx_fec_enable == E400G_25G_12_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_tx_master_bond_chnl == E400G_25G_12_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_tx_pcs_mode == E400G_25G_12_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_tx_primary_use == E400G_25G_12_TX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_tx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_tx_word_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_tx_xcvr_width == E400G_25G_12_TX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_xcvr_mode == E400G_25G_12_XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_12_xcvr_type == E400G_25G_12_XCVR_TYPE_UX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_aib2_rx_st_clk_en == E400G_25G_13_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_aib2_tx_st_clk_en == E400G_25G_13_AIB2_TX_ST_CLK_EN_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_aib3_rx_st_clk_en == E400G_25G_13_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_aib3_tx_st_clk_en == E400G_25G_13_AIB3_TX_ST_CLK_EN_TX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_aibif_data_valid == E400G_25G_13_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_duplex_mode == E400G_25G_13_DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_fec_clk_src == E400G_25G_13_FEC_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_fec_error == E400G_25G_13_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_fec_mode == E400G_25G_13_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_fec_spec == E400G_25G_13_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_lpbk_mode == E400G_25G_13_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_flow_control == E400G_25G_13_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_flow_control_holdoff_mode == E400G_25G_13_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_link_fault_mode == E400G_25G_13_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_mode == E400G_25G_13_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_rx_ptp_phy_lane_num == E400G_25G_13_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_tx_ipg_size == E400G_25G_13_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_tx_ptp_phy_lane_num == E400G_25G_13_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_pcs_ber_mon_mode == E400G_25G_13_PCS_BER_MON_MODE_10G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_pcs_pcs_ber_mon_mode == E400G_25G_13_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_ptp_mode == E400G_25G_13_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_rx_aib_if_fifo_mode == E400G_25G_13_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_rx_excvr_gb_ratio_mode == E400G_25G_13_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_rx_excvr_if_fifo_mode == E400G_25G_13_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_rx_fec_enable == E400G_25G_13_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_rx_master_bond_chnl == E400G_25G_13_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_rx_pcs_mode == E400G_25G_13_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_rx_primary_use == E400G_25G_13_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_rx_xcvr_width == E400G_25G_13_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_speed_map == E400G_25G_13_SPEED_MAP_MAP_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_sup_mode == E400G_25G_13_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_sys_clk_src == E400G_25G_13_SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_tx_aib_if_fifo_mode == E400G_25G_13_TX_AIB_IF_FIFO_MODE_PHASECOMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_tx_datarate == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_tx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_tx_excvr_gb_ratio_mode == E400G_25G_13_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_tx_excvr_if_fifo_mode == E400G_25G_13_TX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_tx_fec_enable == E400G_25G_13_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_tx_master_bond_chnl == E400G_25G_13_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_tx_pcs_mode == E400G_25G_13_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_tx_primary_use == E400G_25G_13_TX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_tx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_tx_word_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_tx_xcvr_width == E400G_25G_13_TX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_xcvr_mode == E400G_25G_13_XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_13_xcvr_type == E400G_25G_13_XCVR_TYPE_UX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_aib2_rx_st_clk_en == E400G_25G_14_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_aib2_tx_st_clk_en == E400G_25G_14_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_aib3_rx_st_clk_en == E400G_25G_14_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_aib3_tx_st_clk_en == E400G_25G_14_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_aibif_data_valid == E400G_25G_14_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_duplex_mode == E400G_25G_14_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_fec_clk_src == E400G_25G_14_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_fec_error == E400G_25G_14_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_fec_mode == E400G_25G_14_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_fec_spec == E400G_25G_14_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_lpbk_mode == E400G_25G_14_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_flow_control == E400G_25G_14_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_flow_control_holdoff_mode == E400G_25G_14_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_link_fault_mode == E400G_25G_14_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_mode == E400G_25G_14_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_rx_ptp_phy_lane_num == E400G_25G_14_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_tx_ipg_size == E400G_25G_14_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_tx_ptp_phy_lane_num == E400G_25G_14_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_pcs_ber_mon_mode == E400G_25G_14_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_pcs_pcs_ber_mon_mode == E400G_25G_14_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_ptp_mode == E400G_25G_14_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_rx_aib_if_fifo_mode == E400G_25G_14_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_rx_excvr_gb_ratio_mode == E400G_25G_14_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_rx_excvr_if_fifo_mode == E400G_25G_14_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_rx_fec_enable == E400G_25G_14_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_rx_master_bond_chnl == E400G_25G_14_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_rx_pcs_mode == E400G_25G_14_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_rx_primary_use == E400G_25G_14_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_rx_xcvr_width == E400G_25G_14_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_speed_map == E400G_25G_14_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_sup_mode == E400G_25G_14_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_sys_clk_src == E400G_25G_14_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_tx_aib_if_fifo_mode == E400G_25G_14_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_tx_excvr_gb_ratio_mode == E400G_25G_14_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_tx_excvr_if_fifo_mode == E400G_25G_14_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_tx_fec_enable == E400G_25G_14_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_tx_master_bond_chnl == E400G_25G_14_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_tx_pcs_mode == E400G_25G_14_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_tx_primary_use == E400G_25G_14_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_tx_xcvr_width == E400G_25G_14_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_xcvr_mode == E400G_25G_14_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_14_xcvr_type == E400G_25G_14_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_aib2_rx_st_clk_en == E400G_25G_15_AIB2_RX_ST_CLK_EN_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_aib2_tx_st_clk_en == E400G_25G_15_AIB2_TX_ST_CLK_EN_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_aib3_rx_st_clk_en == E400G_25G_15_AIB3_RX_ST_CLK_EN_RX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_aib3_tx_st_clk_en == E400G_25G_15_AIB3_TX_ST_CLK_EN_TX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_aibif_data_valid == E400G_25G_15_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_duplex_mode == E400G_25G_15_DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_fec_clk_src == E400G_25G_15_FEC_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_fec_error == E400G_25G_15_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_fec_mode == E400G_25G_15_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_fec_spec == E400G_25G_15_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_lpbk_mode == E400G_25G_15_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_flow_control == E400G_25G_15_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_flow_control_holdoff_mode == E400G_25G_15_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_link_fault_mode == E400G_25G_15_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_mode == E400G_25G_15_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_rx_ptp_phy_lane_num == E400G_25G_15_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_tx_ipg_size == E400G_25G_15_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_tx_ptp_phy_lane_num == E400G_25G_15_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_pcs_ber_mon_mode == E400G_25G_15_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_pcs_pcs_ber_mon_mode == E400G_25G_15_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_ptp_mode == E400G_25G_15_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_rx_aib_if_fifo_mode == E400G_25G_15_RX_AIB_IF_FIFO_MODE_REGISTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_rx_datarate == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_rx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_rx_excvr_gb_ratio_mode == E400G_25G_15_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_rx_excvr_if_fifo_mode == E400G_25G_15_RX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_rx_fec_enable == E400G_25G_15_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_rx_master_bond_chnl == E400G_25G_15_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_rx_pcs_mode == E400G_25G_15_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_rx_primary_use == E400G_25G_15_RX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_rx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_rx_word_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_rx_xcvr_width == E400G_25G_15_RX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_speed_map == E400G_25G_15_SPEED_MAP_MAP_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_sup_mode == E400G_25G_15_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_sys_clk_src == E400G_25G_15_SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_tx_aib_if_fifo_mode == E400G_25G_15_TX_AIB_IF_FIFO_MODE_PHASECOMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_tx_datarate == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_tx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_tx_excvr_gb_ratio_mode == E400G_25G_15_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_tx_excvr_if_fifo_mode == E400G_25G_15_TX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_tx_fec_enable == E400G_25G_15_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_tx_master_bond_chnl == E400G_25G_15_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_tx_pcs_mode == E400G_25G_15_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_tx_primary_use == E400G_25G_15_TX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_tx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_tx_word_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_tx_xcvr_width == E400G_25G_15_TX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_xcvr_mode == E400G_25G_15_XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_15_xcvr_type == E400G_25G_15_XCVR_TYPE_UX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_aib2_rx_st_clk_en == E400G_25G_1_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_aib2_tx_st_clk_en == E400G_25G_1_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_aib3_rx_st_clk_en == E400G_25G_1_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_aib3_tx_st_clk_en == E400G_25G_1_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_aibif_data_valid == E400G_25G_1_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_duplex_mode == E400G_25G_1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_fec_clk_src == E400G_25G_1_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_fec_error == E400G_25G_1_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_fec_mode == E400G_25G_1_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_fec_spec == E400G_25G_1_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_lpbk_mode == E400G_25G_1_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_flow_control == E400G_25G_1_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_flow_control_holdoff_mode == E400G_25G_1_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_link_fault_mode == E400G_25G_1_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_mode == E400G_25G_1_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_rx_ptp_phy_lane_num == E400G_25G_1_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_tx_ipg_size == E400G_25G_1_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_tx_ptp_phy_lane_num == E400G_25G_1_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_pcs_ber_mon_mode == E400G_25G_1_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_pcs_pcs_ber_mon_mode == E400G_25G_1_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_ptp_mode == E400G_25G_1_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_rx_aib_if_fifo_mode == E400G_25G_1_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_rx_excvr_gb_ratio_mode == E400G_25G_1_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_rx_excvr_if_fifo_mode == E400G_25G_1_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_rx_fec_enable == E400G_25G_1_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_rx_master_bond_chnl == E400G_25G_1_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_rx_pcs_mode == E400G_25G_1_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_rx_primary_use == E400G_25G_1_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_rx_xcvr_width == E400G_25G_1_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_speed_map == E400G_25G_1_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_sup_mode == E400G_25G_1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_sys_clk_src == E400G_25G_1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_tx_aib_if_fifo_mode == E400G_25G_1_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_tx_excvr_gb_ratio_mode == E400G_25G_1_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_tx_excvr_if_fifo_mode == E400G_25G_1_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_tx_fec_enable == E400G_25G_1_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_tx_master_bond_chnl == E400G_25G_1_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_tx_pcs_mode == E400G_25G_1_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_tx_primary_use == E400G_25G_1_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_tx_xcvr_width == E400G_25G_1_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_xcvr_mode == E400G_25G_1_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_1_xcvr_type == E400G_25G_1_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_aib2_rx_st_clk_en == E400G_25G_2_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_aib2_tx_st_clk_en == E400G_25G_2_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_aib3_rx_st_clk_en == E400G_25G_2_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_aib3_tx_st_clk_en == E400G_25G_2_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_aibif_data_valid == E400G_25G_2_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_duplex_mode == E400G_25G_2_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_fec_clk_src == E400G_25G_2_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_fec_error == E400G_25G_2_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_fec_mode == E400G_25G_2_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_fec_spec == E400G_25G_2_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_lpbk_mode == E400G_25G_2_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_flow_control == E400G_25G_2_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_flow_control_holdoff_mode == E400G_25G_2_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_link_fault_mode == E400G_25G_2_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_mode == E400G_25G_2_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_rx_ptp_phy_lane_num == E400G_25G_2_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_tx_ipg_size == E400G_25G_2_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_tx_ptp_phy_lane_num == E400G_25G_2_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_pcs_ber_mon_mode == E400G_25G_2_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_pcs_pcs_ber_mon_mode == E400G_25G_2_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_ptp_mode == E400G_25G_2_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_rx_aib_if_fifo_mode == E400G_25G_2_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_rx_excvr_gb_ratio_mode == E400G_25G_2_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_rx_excvr_if_fifo_mode == E400G_25G_2_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_rx_fec_enable == E400G_25G_2_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_rx_master_bond_chnl == E400G_25G_2_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_rx_pcs_mode == E400G_25G_2_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_rx_primary_use == E400G_25G_2_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_rx_xcvr_width == E400G_25G_2_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_speed_map == E400G_25G_2_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_sup_mode == E400G_25G_2_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_sys_clk_src == E400G_25G_2_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_tx_aib_if_fifo_mode == E400G_25G_2_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_tx_excvr_gb_ratio_mode == E400G_25G_2_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_tx_excvr_if_fifo_mode == E400G_25G_2_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_tx_fec_enable == E400G_25G_2_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_tx_master_bond_chnl == E400G_25G_2_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_tx_pcs_mode == E400G_25G_2_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_tx_primary_use == E400G_25G_2_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_tx_xcvr_width == E400G_25G_2_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_xcvr_mode == E400G_25G_2_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_2_xcvr_type == E400G_25G_2_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_aib2_rx_st_clk_en == E400G_25G_3_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_aib2_tx_st_clk_en == E400G_25G_3_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_aib3_rx_st_clk_en == E400G_25G_3_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_aib3_tx_st_clk_en == E400G_25G_3_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_aibif_data_valid == E400G_25G_3_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_duplex_mode == E400G_25G_3_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_fec_clk_src == E400G_25G_3_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_fec_error == E400G_25G_3_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_fec_mode == E400G_25G_3_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_fec_spec == E400G_25G_3_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_lpbk_mode == E400G_25G_3_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_flow_control == E400G_25G_3_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_flow_control_holdoff_mode == E400G_25G_3_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_link_fault_mode == E400G_25G_3_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_mode == E400G_25G_3_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_rx_ptp_phy_lane_num == E400G_25G_3_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_tx_ipg_size == E400G_25G_3_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_tx_ptp_phy_lane_num == E400G_25G_3_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_pcs_ber_mon_mode == E400G_25G_3_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_pcs_pcs_ber_mon_mode == E400G_25G_3_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_ptp_mode == E400G_25G_3_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_rx_aib_if_fifo_mode == E400G_25G_3_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_rx_excvr_gb_ratio_mode == E400G_25G_3_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_rx_excvr_if_fifo_mode == E400G_25G_3_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_rx_fec_enable == E400G_25G_3_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_rx_master_bond_chnl == E400G_25G_3_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_rx_pcs_mode == E400G_25G_3_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_rx_primary_use == E400G_25G_3_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_rx_xcvr_width == E400G_25G_3_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_speed_map == E400G_25G_3_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_sup_mode == E400G_25G_3_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_sys_clk_src == E400G_25G_3_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_tx_aib_if_fifo_mode == E400G_25G_3_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_tx_excvr_gb_ratio_mode == E400G_25G_3_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_tx_excvr_if_fifo_mode == E400G_25G_3_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_tx_fec_enable == E400G_25G_3_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_tx_master_bond_chnl == E400G_25G_3_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_tx_pcs_mode == E400G_25G_3_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_tx_primary_use == E400G_25G_3_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_tx_xcvr_width == E400G_25G_3_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_xcvr_mode == E400G_25G_3_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_3_xcvr_type == E400G_25G_3_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_aib2_rx_st_clk_en == E400G_25G_4_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_aib2_tx_st_clk_en == E400G_25G_4_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_aib3_rx_st_clk_en == E400G_25G_4_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_aib3_tx_st_clk_en == E400G_25G_4_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_aibif_data_valid == E400G_25G_4_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_duplex_mode == E400G_25G_4_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_fec_clk_src == E400G_25G_4_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_fec_error == E400G_25G_4_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_fec_mode == E400G_25G_4_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_fec_spec == E400G_25G_4_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_lpbk_mode == E400G_25G_4_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_flow_control == E400G_25G_4_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_flow_control_holdoff_mode == E400G_25G_4_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_link_fault_mode == E400G_25G_4_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_mode == E400G_25G_4_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_rx_ptp_phy_lane_num == E400G_25G_4_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_tx_ipg_size == E400G_25G_4_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_tx_ptp_phy_lane_num == E400G_25G_4_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_pcs_ber_mon_mode == E400G_25G_4_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_pcs_pcs_ber_mon_mode == E400G_25G_4_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_ptp_mode == E400G_25G_4_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_rx_aib_if_fifo_mode == E400G_25G_4_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_rx_excvr_gb_ratio_mode == E400G_25G_4_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_rx_excvr_if_fifo_mode == E400G_25G_4_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_rx_fec_enable == E400G_25G_4_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_rx_master_bond_chnl == E400G_25G_4_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_rx_pcs_mode == E400G_25G_4_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_rx_primary_use == E400G_25G_4_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_rx_xcvr_width == E400G_25G_4_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_speed_map == E400G_25G_4_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_sup_mode == E400G_25G_4_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_sys_clk_src == E400G_25G_4_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_tx_aib_if_fifo_mode == E400G_25G_4_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_tx_excvr_gb_ratio_mode == E400G_25G_4_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_tx_excvr_if_fifo_mode == E400G_25G_4_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_tx_fec_enable == E400G_25G_4_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_tx_master_bond_chnl == E400G_25G_4_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_tx_pcs_mode == E400G_25G_4_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_tx_primary_use == E400G_25G_4_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_tx_xcvr_width == E400G_25G_4_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_xcvr_mode == E400G_25G_4_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_4_xcvr_type == E400G_25G_4_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_aib2_rx_st_clk_en == E400G_25G_5_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_aib2_tx_st_clk_en == E400G_25G_5_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_aib3_rx_st_clk_en == E400G_25G_5_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_aib3_tx_st_clk_en == E400G_25G_5_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_aibif_data_valid == E400G_25G_5_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_duplex_mode == E400G_25G_5_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_fec_clk_src == E400G_25G_5_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_fec_error == E400G_25G_5_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_fec_mode == E400G_25G_5_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_fec_spec == E400G_25G_5_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_lpbk_mode == E400G_25G_5_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_flow_control == E400G_25G_5_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_flow_control_holdoff_mode == E400G_25G_5_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_link_fault_mode == E400G_25G_5_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_mode == E400G_25G_5_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_rx_ptp_phy_lane_num == E400G_25G_5_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_tx_ipg_size == E400G_25G_5_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_tx_ptp_phy_lane_num == E400G_25G_5_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_pcs_ber_mon_mode == E400G_25G_5_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_pcs_pcs_ber_mon_mode == E400G_25G_5_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_ptp_mode == E400G_25G_5_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_rx_aib_if_fifo_mode == E400G_25G_5_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_rx_excvr_gb_ratio_mode == E400G_25G_5_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_rx_excvr_if_fifo_mode == E400G_25G_5_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_rx_fec_enable == E400G_25G_5_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_rx_master_bond_chnl == E400G_25G_5_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_rx_pcs_mode == E400G_25G_5_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_rx_primary_use == E400G_25G_5_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_rx_xcvr_width == E400G_25G_5_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_speed_map == E400G_25G_5_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_sup_mode == E400G_25G_5_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_sys_clk_src == E400G_25G_5_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_tx_aib_if_fifo_mode == E400G_25G_5_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_tx_excvr_gb_ratio_mode == E400G_25G_5_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_tx_excvr_if_fifo_mode == E400G_25G_5_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_tx_fec_enable == E400G_25G_5_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_tx_master_bond_chnl == E400G_25G_5_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_tx_pcs_mode == E400G_25G_5_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_tx_primary_use == E400G_25G_5_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_tx_xcvr_width == E400G_25G_5_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_xcvr_mode == E400G_25G_5_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_5_xcvr_type == E400G_25G_5_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_aib2_rx_st_clk_en == E400G_25G_6_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_aib2_tx_st_clk_en == E400G_25G_6_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_aib3_rx_st_clk_en == E400G_25G_6_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_aib3_tx_st_clk_en == E400G_25G_6_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_aibif_data_valid == E400G_25G_6_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_duplex_mode == E400G_25G_6_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_fec_clk_src == E400G_25G_6_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_fec_error == E400G_25G_6_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_fec_mode == E400G_25G_6_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_fec_spec == E400G_25G_6_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_lpbk_mode == E400G_25G_6_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_flow_control == E400G_25G_6_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_flow_control_holdoff_mode == E400G_25G_6_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_link_fault_mode == E400G_25G_6_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_mode == E400G_25G_6_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_rx_ptp_phy_lane_num == E400G_25G_6_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_tx_ipg_size == E400G_25G_6_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_tx_ptp_phy_lane_num == E400G_25G_6_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_pcs_ber_mon_mode == E400G_25G_6_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_pcs_pcs_ber_mon_mode == E400G_25G_6_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_ptp_mode == E400G_25G_6_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_rx_aib_if_fifo_mode == E400G_25G_6_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_rx_excvr_gb_ratio_mode == E400G_25G_6_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_rx_excvr_if_fifo_mode == E400G_25G_6_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_rx_fec_enable == E400G_25G_6_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_rx_master_bond_chnl == E400G_25G_6_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_rx_pcs_mode == E400G_25G_6_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_rx_primary_use == E400G_25G_6_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_rx_xcvr_width == E400G_25G_6_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_speed_map == E400G_25G_6_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_sup_mode == E400G_25G_6_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_sys_clk_src == E400G_25G_6_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_tx_aib_if_fifo_mode == E400G_25G_6_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_tx_excvr_gb_ratio_mode == E400G_25G_6_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_tx_excvr_if_fifo_mode == E400G_25G_6_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_tx_fec_enable == E400G_25G_6_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_tx_master_bond_chnl == E400G_25G_6_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_tx_pcs_mode == E400G_25G_6_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_tx_primary_use == E400G_25G_6_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_tx_xcvr_width == E400G_25G_6_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_xcvr_mode == E400G_25G_6_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_6_xcvr_type == E400G_25G_6_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_aib2_rx_st_clk_en == E400G_25G_7_AIB2_RX_ST_CLK_EN_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_aib2_tx_st_clk_en == E400G_25G_7_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_aib3_rx_st_clk_en == E400G_25G_7_AIB3_RX_ST_CLK_EN_RX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_aib3_tx_st_clk_en == E400G_25G_7_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_aibif_data_valid == E400G_25G_7_AIBIF_DATA_VALID_40G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_duplex_mode == E400G_25G_7_DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_fec_clk_src == E400G_25G_7_FEC_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_fec_error == E400G_25G_7_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_fec_mode == E400G_25G_7_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_fec_spec == E400G_25G_7_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_lpbk_mode == E400G_25G_7_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_flow_control == E400G_25G_7_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_flow_control_holdoff_mode == E400G_25G_7_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_link_fault_mode == E400G_25G_7_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_mode == E400G_25G_7_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_rx_ptp_phy_lane_num == E400G_25G_7_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_tx_ipg_size == E400G_25G_7_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_tx_ptp_phy_lane_num == E400G_25G_7_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_pcs_ber_mon_mode == E400G_25G_7_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_pcs_pcs_ber_mon_mode == E400G_25G_7_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_ptp_mode == E400G_25G_7_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_rx_aib_if_fifo_mode == E400G_25G_7_RX_AIB_IF_FIFO_MODE_REGISTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_rx_datarate == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_rx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_rx_excvr_gb_ratio_mode == E400G_25G_7_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_rx_excvr_if_fifo_mode == E400G_25G_7_RX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_rx_fec_enable == E400G_25G_7_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_rx_master_bond_chnl == E400G_25G_7_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_rx_pcs_mode == E400G_25G_7_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_rx_primary_use == E400G_25G_7_RX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_rx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_rx_word_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_rx_xcvr_width == E400G_25G_7_RX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_speed_map == E400G_25G_7_SPEED_MAP_MAP_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_sup_mode == E400G_25G_7_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_sys_clk_src == E400G_25G_7_SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_tx_aib_if_fifo_mode == E400G_25G_7_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_tx_excvr_gb_ratio_mode == E400G_25G_7_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_tx_excvr_if_fifo_mode == E400G_25G_7_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_tx_fec_enable == E400G_25G_7_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_tx_master_bond_chnl == E400G_25G_7_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_tx_pcs_mode == E400G_25G_7_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_tx_primary_use == E400G_25G_7_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_tx_xcvr_width == E400G_25G_7_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_xcvr_mode == E400G_25G_7_XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_7_xcvr_type == E400G_25G_7_XCVR_TYPE_UX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_aib2_rx_st_clk_en == E400G_25G_8_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_aib2_tx_st_clk_en == E400G_25G_8_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_aib3_rx_st_clk_en == E400G_25G_8_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_aib3_tx_st_clk_en == E400G_25G_8_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_aibif_data_valid == E400G_25G_8_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_duplex_mode == E400G_25G_8_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_fec_clk_src == E400G_25G_8_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_fec_error == E400G_25G_8_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_fec_mode == E400G_25G_8_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_fec_spec == E400G_25G_8_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_lpbk_mode == E400G_25G_8_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_flow_control == E400G_25G_8_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_flow_control_holdoff_mode == E400G_25G_8_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_link_fault_mode == E400G_25G_8_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_mode == E400G_25G_8_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_rx_ptp_phy_lane_num == E400G_25G_8_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_tx_ipg_size == E400G_25G_8_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_tx_ptp_phy_lane_num == E400G_25G_8_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_pcs_ber_mon_mode == E400G_25G_8_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_pcs_pcs_ber_mon_mode == E400G_25G_8_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_ptp_mode == E400G_25G_8_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_rx_aib_if_fifo_mode == E400G_25G_8_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_rx_excvr_gb_ratio_mode == E400G_25G_8_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_rx_excvr_if_fifo_mode == E400G_25G_8_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_rx_fec_enable == E400G_25G_8_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_rx_master_bond_chnl == E400G_25G_8_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_rx_pcs_mode == E400G_25G_8_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_rx_primary_use == E400G_25G_8_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_rx_xcvr_width == E400G_25G_8_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_speed_map == E400G_25G_8_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_sup_mode == E400G_25G_8_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_sys_clk_src == E400G_25G_8_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_tx_aib_if_fifo_mode == E400G_25G_8_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_tx_excvr_gb_ratio_mode == E400G_25G_8_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_tx_excvr_if_fifo_mode == E400G_25G_8_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_tx_fec_enable == E400G_25G_8_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_tx_master_bond_chnl == E400G_25G_8_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_tx_pcs_mode == E400G_25G_8_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_tx_primary_use == E400G_25G_8_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_tx_xcvr_width == E400G_25G_8_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_xcvr_mode == E400G_25G_8_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_8_xcvr_type == E400G_25G_8_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_aib2_rx_st_clk_en == E400G_25G_9_AIB2_RX_ST_CLK_EN_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_aib2_tx_st_clk_en == E400G_25G_9_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_aib3_rx_st_clk_en == E400G_25G_9_AIB3_RX_ST_CLK_EN_RX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_aib3_tx_st_clk_en == E400G_25G_9_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_aibif_data_valid == E400G_25G_9_AIBIF_DATA_VALID_40G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_duplex_mode == E400G_25G_9_DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_fec_clk_src == E400G_25G_9_FEC_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_fec_error == E400G_25G_9_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_fec_mode == E400G_25G_9_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_fec_spec == E400G_25G_9_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_lpbk_mode == E400G_25G_9_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_flow_control == E400G_25G_9_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_flow_control_holdoff_mode == E400G_25G_9_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_link_fault_mode == E400G_25G_9_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_mode == E400G_25G_9_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_rx_ptp_phy_lane_num == E400G_25G_9_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_tx_ipg_size == E400G_25G_9_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_tx_ptp_phy_lane_num == E400G_25G_9_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_pcs_ber_mon_mode == E400G_25G_9_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_pcs_pcs_ber_mon_mode == E400G_25G_9_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_ptp_mode == E400G_25G_9_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_rx_aib_if_fifo_mode == E400G_25G_9_RX_AIB_IF_FIFO_MODE_REGISTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_rx_datarate == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_rx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_rx_excvr_gb_ratio_mode == E400G_25G_9_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_rx_excvr_if_fifo_mode == E400G_25G_9_RX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_rx_fec_enable == E400G_25G_9_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_rx_master_bond_chnl == E400G_25G_9_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_rx_pcs_mode == E400G_25G_9_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_rx_primary_use == E400G_25G_9_RX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_rx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_rx_word_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_rx_xcvr_width == E400G_25G_9_RX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_speed_map == E400G_25G_9_SPEED_MAP_MAP_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_sup_mode == E400G_25G_9_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_sys_clk_src == E400G_25G_9_SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_tx_aib_if_fifo_mode == E400G_25G_9_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_tx_excvr_gb_ratio_mode == E400G_25G_9_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_tx_excvr_if_fifo_mode == E400G_25G_9_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_tx_fec_enable == E400G_25G_9_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_tx_master_bond_chnl == E400G_25G_9_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_tx_pcs_mode == E400G_25G_9_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_tx_primary_use == E400G_25G_9_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_tx_xcvr_width == E400G_25G_9_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_xcvr_mode == E400G_25G_9_XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_25g_9_xcvr_type == E400G_25G_9_XCVR_TYPE_UX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_aib2_rx_st_clk_en == E400G_300G_0_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_aib2_tx_st_clk_en == E400G_300G_0_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_aib3_rx_st_clk_en == E400G_300G_0_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_aib3_tx_st_clk_en == E400G_300G_0_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_aibif_data_valid == E400G_300G_0_AIBIF_DATA_VALID_CUSTOM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_duplex_mode == E400G_300G_0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_fec_mode == E400G_300G_0_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_fec_spec == E400G_300G_0_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_lpbk_mode == E400G_300G_0_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_mac_mode == E400G_300G_0_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_pcs_ber_mon_mode == E400G_300G_0_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_ptp_mode == E400G_300G_0_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_rx_aib_if_fifo_mode == E400G_300G_0_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_rx_excvr_gb_ratio_mode == E400G_300G_0_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_rx_excvr_if_fifo_mode == E400G_300G_0_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_rx_fec_enable == E400G_300G_0_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_rx_master_bond_chnl == E400G_300G_0_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_rx_pcs_mode == E400G_300G_0_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_rx_primary_use == E400G_300G_0_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_rx_xcvr_width == E400G_300G_0_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_speed_map == E400G_300G_0_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_sup_mode == E400G_300G_0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_sys_clk_src == E400G_300G_0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_tx_aib_if_fifo_mode == E400G_300G_0_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_tx_excvr_gb_ratio_mode == E400G_300G_0_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_tx_excvr_if_fifo_mode == E400G_300G_0_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_tx_fec_enable == E400G_300G_0_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_tx_master_bond_chnl == E400G_300G_0_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_tx_pcs_mode == E400G_300G_0_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_tx_primary_use == E400G_300G_0_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_tx_xcvr_width == E400G_300G_0_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_xcvr_mode == E400G_300G_0_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_0_xcvr_type == E400G_300G_0_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_aib2_rx_st_clk_en == E400G_300G_1_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_aib2_tx_st_clk_en == E400G_300G_1_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_aib3_rx_st_clk_en == E400G_300G_1_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_aib3_tx_st_clk_en == E400G_300G_1_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_aibif_data_valid == E400G_300G_1_AIBIF_DATA_VALID_CUSTOM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_duplex_mode == E400G_300G_1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_fec_mode == E400G_300G_1_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_fec_spec == E400G_300G_1_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_lpbk_mode == E400G_300G_1_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_mac_mode == E400G_300G_1_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_pcs_ber_mon_mode == E400G_300G_1_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_ptp_mode == E400G_300G_1_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_rx_aib_if_fifo_mode == E400G_300G_1_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_rx_excvr_gb_ratio_mode == E400G_300G_1_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_rx_excvr_if_fifo_mode == E400G_300G_1_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_rx_fec_enable == E400G_300G_1_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_rx_master_bond_chnl == E400G_300G_1_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_rx_pcs_mode == E400G_300G_1_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_rx_primary_use == E400G_300G_1_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_rx_xcvr_width == E400G_300G_1_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_speed_map == E400G_300G_1_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_sup_mode == E400G_300G_1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_sys_clk_src == E400G_300G_1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_tx_aib_if_fifo_mode == E400G_300G_1_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_tx_excvr_gb_ratio_mode == E400G_300G_1_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_tx_excvr_if_fifo_mode == E400G_300G_1_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_tx_fec_enable == E400G_300G_1_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_tx_master_bond_chnl == E400G_300G_1_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_tx_pcs_mode == E400G_300G_1_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_tx_primary_use == E400G_300G_1_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_tx_xcvr_width == E400G_300G_1_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_xcvr_mode == E400G_300G_1_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_300g_1_xcvr_type == E400G_300G_1_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_aib2_rx_st_clk_en == E400G_400G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_aib2_tx_st_clk_en == E400G_400G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_aib3_rx_st_clk_en == E400G_400G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_aib3_tx_st_clk_en == E400G_400G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_aibif_data_valid == E400G_400G_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_duplex_mode == E400G_400G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_fec_clk_src == E400G_400G_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_fec_error == E400G_400G_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_fec_mode == E400G_400G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_fec_spec == E400G_400G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_lpbk_mode == E400G_400G_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_flow_control == E400G_400G_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_flow_control_holdoff_mode == E400G_400G_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_link_fault_mode == E400G_400G_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_mode == E400G_400G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_rx_ptp_phy_lane_num == E400G_400G_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_tx_ipg_size == E400G_400G_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_tx_ptp_phy_lane_num == E400G_400G_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_pcs_ber_mon_mode == E400G_400G_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_pcs_pcs_ber_mon_mode == E400G_400G_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_ptp_mode == E400G_400G_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_rx_aib_if_fifo_mode == E400G_400G_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_rx_excvr_gb_ratio_mode == E400G_400G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_rx_excvr_if_fifo_mode == E400G_400G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_rx_fec_enable == E400G_400G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_rx_master_bond_chnl == E400G_400G_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_rx_pcs_mode == E400G_400G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_rx_primary_use == E400G_400G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_rx_xcvr_width == E400G_400G_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_speed_map == E400G_400G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_sup_mode == E400G_400G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_sys_clk_src == E400G_400G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_tx_aib_if_fifo_mode == E400G_400G_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_tx_excvr_gb_ratio_mode == E400G_400G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_tx_excvr_if_fifo_mode == E400G_400G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_tx_fec_enable == E400G_400G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_tx_master_bond_chnl == E400G_400G_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_tx_pcs_mode == E400G_400G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_tx_primary_use == E400G_400G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_tx_xcvr_width == E400G_400G_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_xcvr_mode == E400G_400G_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_400g_xcvr_type == E400G_400G_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_aib2_rx_st_clk_en == E400G_50G_0_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_aib2_tx_st_clk_en == E400G_50G_0_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_aib3_rx_st_clk_en == E400G_50G_0_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_aib3_tx_st_clk_en == E400G_50G_0_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_aibif_data_valid == E400G_50G_0_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_duplex_mode == E400G_50G_0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_fec_clk_src == E400G_50G_0_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_fec_error == E400G_50G_0_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_fec_mode == E400G_50G_0_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_fec_spec == E400G_50G_0_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_lpbk_mode == E400G_50G_0_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_flow_control == E400G_50G_0_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_flow_control_holdoff_mode == E400G_50G_0_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_link_fault_mode == E400G_50G_0_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_mode == E400G_50G_0_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_rx_ptp_phy_lane_num == E400G_50G_0_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_tx_ipg_size == E400G_50G_0_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_tx_ptp_phy_lane_num == E400G_50G_0_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_pcs_ber_mon_mode == E400G_50G_0_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_pcs_pcs_ber_mon_mode == E400G_50G_0_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_ptp_mode == E400G_50G_0_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_rx_aib_if_fifo_mode == E400G_50G_0_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_rx_excvr_gb_ratio_mode == E400G_50G_0_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_rx_excvr_if_fifo_mode == E400G_50G_0_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_rx_fec_enable == E400G_50G_0_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_rx_master_bond_chnl == E400G_50G_0_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_rx_pcs_mode == E400G_50G_0_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_rx_primary_use == E400G_50G_0_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_rx_xcvr_width == E400G_50G_0_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_speed_map == E400G_50G_0_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_sup_mode == E400G_50G_0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_sys_clk_src == E400G_50G_0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_tx_aib_if_fifo_mode == E400G_50G_0_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_tx_excvr_gb_ratio_mode == E400G_50G_0_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_tx_excvr_if_fifo_mode == E400G_50G_0_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_tx_fec_enable == E400G_50G_0_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_tx_master_bond_chnl == E400G_50G_0_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_tx_pcs_mode == E400G_50G_0_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_tx_primary_use == E400G_50G_0_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_tx_xcvr_width == E400G_50G_0_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_xcvr_mode == E400G_50G_0_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_0_xcvr_type == E400G_50G_0_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_aib2_rx_st_clk_en == E400G_50G_1_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_aib2_tx_st_clk_en == E400G_50G_1_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_aib3_rx_st_clk_en == E400G_50G_1_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_aib3_tx_st_clk_en == E400G_50G_1_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_aibif_data_valid == E400G_50G_1_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_duplex_mode == E400G_50G_1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_fec_clk_src == E400G_50G_1_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_fec_error == E400G_50G_1_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_fec_mode == E400G_50G_1_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_fec_spec == E400G_50G_1_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_lpbk_mode == E400G_50G_1_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_flow_control == E400G_50G_1_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_flow_control_holdoff_mode == E400G_50G_1_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_link_fault_mode == E400G_50G_1_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_mode == E400G_50G_1_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_rx_ptp_phy_lane_num == E400G_50G_1_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_tx_ipg_size == E400G_50G_1_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_tx_ptp_phy_lane_num == E400G_50G_1_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_pcs_ber_mon_mode == E400G_50G_1_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_pcs_pcs_ber_mon_mode == E400G_50G_1_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_ptp_mode == E400G_50G_1_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_rx_aib_if_fifo_mode == E400G_50G_1_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_rx_excvr_gb_ratio_mode == E400G_50G_1_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_rx_excvr_if_fifo_mode == E400G_50G_1_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_rx_fec_enable == E400G_50G_1_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_rx_master_bond_chnl == E400G_50G_1_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_rx_pcs_mode == E400G_50G_1_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_rx_primary_use == E400G_50G_1_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_rx_xcvr_width == E400G_50G_1_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_speed_map == E400G_50G_1_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_sup_mode == E400G_50G_1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_sys_clk_src == E400G_50G_1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_tx_aib_if_fifo_mode == E400G_50G_1_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_tx_excvr_gb_ratio_mode == E400G_50G_1_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_tx_excvr_if_fifo_mode == E400G_50G_1_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_tx_fec_enable == E400G_50G_1_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_tx_master_bond_chnl == E400G_50G_1_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_tx_pcs_mode == E400G_50G_1_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_tx_primary_use == E400G_50G_1_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_tx_xcvr_width == E400G_50G_1_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_xcvr_mode == E400G_50G_1_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_1_xcvr_type == E400G_50G_1_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_aib2_rx_st_clk_en == E400G_50G_2_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_aib2_tx_st_clk_en == E400G_50G_2_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_aib3_rx_st_clk_en == E400G_50G_2_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_aib3_tx_st_clk_en == E400G_50G_2_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_aibif_data_valid == E400G_50G_2_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_duplex_mode == E400G_50G_2_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_fec_clk_src == E400G_50G_2_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_fec_error == E400G_50G_2_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_fec_mode == E400G_50G_2_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_fec_spec == E400G_50G_2_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_lpbk_mode == E400G_50G_2_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_flow_control == E400G_50G_2_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_flow_control_holdoff_mode == E400G_50G_2_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_link_fault_mode == E400G_50G_2_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_mode == E400G_50G_2_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_rx_ptp_phy_lane_num == E400G_50G_2_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_tx_ipg_size == E400G_50G_2_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_tx_ptp_phy_lane_num == E400G_50G_2_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_pcs_ber_mon_mode == E400G_50G_2_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_pcs_pcs_ber_mon_mode == E400G_50G_2_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_ptp_mode == E400G_50G_2_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_rx_aib_if_fifo_mode == E400G_50G_2_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_rx_excvr_gb_ratio_mode == E400G_50G_2_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_rx_excvr_if_fifo_mode == E400G_50G_2_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_rx_fec_enable == E400G_50G_2_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_rx_master_bond_chnl == E400G_50G_2_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_rx_pcs_mode == E400G_50G_2_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_rx_primary_use == E400G_50G_2_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_rx_xcvr_width == E400G_50G_2_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_speed_map == E400G_50G_2_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_sup_mode == E400G_50G_2_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_sys_clk_src == E400G_50G_2_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_tx_aib_if_fifo_mode == E400G_50G_2_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_tx_excvr_gb_ratio_mode == E400G_50G_2_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_tx_excvr_if_fifo_mode == E400G_50G_2_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_tx_fec_enable == E400G_50G_2_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_tx_master_bond_chnl == E400G_50G_2_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_tx_pcs_mode == E400G_50G_2_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_tx_primary_use == E400G_50G_2_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_tx_xcvr_width == E400G_50G_2_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_xcvr_mode == E400G_50G_2_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_2_xcvr_type == E400G_50G_2_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_aib2_rx_st_clk_en == E400G_50G_3_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_aib2_tx_st_clk_en == E400G_50G_3_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_aib3_rx_st_clk_en == E400G_50G_3_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_aib3_tx_st_clk_en == E400G_50G_3_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_aibif_data_valid == E400G_50G_3_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_duplex_mode == E400G_50G_3_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_fec_clk_src == E400G_50G_3_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_fec_error == E400G_50G_3_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_fec_mode == E400G_50G_3_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_fec_spec == E400G_50G_3_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_lpbk_mode == E400G_50G_3_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_flow_control == E400G_50G_3_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_flow_control_holdoff_mode == E400G_50G_3_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_link_fault_mode == E400G_50G_3_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_mode == E400G_50G_3_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_rx_ptp_phy_lane_num == E400G_50G_3_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_tx_ipg_size == E400G_50G_3_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_tx_ptp_phy_lane_num == E400G_50G_3_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_pcs_ber_mon_mode == E400G_50G_3_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_pcs_pcs_ber_mon_mode == E400G_50G_3_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_ptp_mode == E400G_50G_3_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_rx_aib_if_fifo_mode == E400G_50G_3_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_rx_excvr_gb_ratio_mode == E400G_50G_3_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_rx_excvr_if_fifo_mode == E400G_50G_3_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_rx_fec_enable == E400G_50G_3_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_rx_master_bond_chnl == E400G_50G_3_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_rx_pcs_mode == E400G_50G_3_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_rx_primary_use == E400G_50G_3_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_rx_xcvr_width == E400G_50G_3_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_speed_map == E400G_50G_3_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_sup_mode == E400G_50G_3_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_sys_clk_src == E400G_50G_3_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_tx_aib_if_fifo_mode == E400G_50G_3_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_tx_excvr_gb_ratio_mode == E400G_50G_3_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_tx_excvr_if_fifo_mode == E400G_50G_3_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_tx_fec_enable == E400G_50G_3_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_tx_master_bond_chnl == E400G_50G_3_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_tx_pcs_mode == E400G_50G_3_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_tx_primary_use == E400G_50G_3_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_tx_xcvr_width == E400G_50G_3_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_xcvr_mode == E400G_50G_3_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_3_xcvr_type == E400G_50G_3_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_aib2_rx_st_clk_en == E400G_50G_4_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_aib2_tx_st_clk_en == E400G_50G_4_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_aib3_rx_st_clk_en == E400G_50G_4_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_aib3_tx_st_clk_en == E400G_50G_4_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_aibif_data_valid == E400G_50G_4_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_duplex_mode == E400G_50G_4_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_fec_clk_src == E400G_50G_4_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_fec_error == E400G_50G_4_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_fec_mode == E400G_50G_4_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_fec_spec == E400G_50G_4_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_lpbk_mode == E400G_50G_4_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_flow_control == E400G_50G_4_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_flow_control_holdoff_mode == E400G_50G_4_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_link_fault_mode == E400G_50G_4_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_mode == E400G_50G_4_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_rx_ptp_phy_lane_num == E400G_50G_4_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_tx_ipg_size == E400G_50G_4_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_tx_ptp_phy_lane_num == E400G_50G_4_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_pcs_ber_mon_mode == E400G_50G_4_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_pcs_pcs_ber_mon_mode == E400G_50G_4_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_ptp_mode == E400G_50G_4_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_rx_aib_if_fifo_mode == E400G_50G_4_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_rx_excvr_gb_ratio_mode == E400G_50G_4_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_rx_excvr_if_fifo_mode == E400G_50G_4_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_rx_fec_enable == E400G_50G_4_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_rx_master_bond_chnl == E400G_50G_4_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_rx_pcs_mode == E400G_50G_4_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_rx_primary_use == E400G_50G_4_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_rx_xcvr_width == E400G_50G_4_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_speed_map == E400G_50G_4_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_sup_mode == E400G_50G_4_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_sys_clk_src == E400G_50G_4_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_tx_aib_if_fifo_mode == E400G_50G_4_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_tx_excvr_gb_ratio_mode == E400G_50G_4_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_tx_excvr_if_fifo_mode == E400G_50G_4_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_tx_fec_enable == E400G_50G_4_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_tx_master_bond_chnl == E400G_50G_4_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_tx_pcs_mode == E400G_50G_4_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_tx_primary_use == E400G_50G_4_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_tx_xcvr_width == E400G_50G_4_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_xcvr_mode == E400G_50G_4_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_4_xcvr_type == E400G_50G_4_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_aib2_rx_st_clk_en == E400G_50G_5_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_aib2_tx_st_clk_en == E400G_50G_5_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_aib3_rx_st_clk_en == E400G_50G_5_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_aib3_tx_st_clk_en == E400G_50G_5_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_aibif_data_valid == E400G_50G_5_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_duplex_mode == E400G_50G_5_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_fec_clk_src == E400G_50G_5_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_fec_error == E400G_50G_5_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_fec_mode == E400G_50G_5_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_fec_spec == E400G_50G_5_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_lpbk_mode == E400G_50G_5_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_flow_control == E400G_50G_5_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_flow_control_holdoff_mode == E400G_50G_5_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_link_fault_mode == E400G_50G_5_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_mode == E400G_50G_5_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_rx_ptp_phy_lane_num == E400G_50G_5_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_tx_ipg_size == E400G_50G_5_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_tx_ptp_phy_lane_num == E400G_50G_5_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_pcs_ber_mon_mode == E400G_50G_5_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_pcs_pcs_ber_mon_mode == E400G_50G_5_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_ptp_mode == E400G_50G_5_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_rx_aib_if_fifo_mode == E400G_50G_5_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_rx_excvr_gb_ratio_mode == E400G_50G_5_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_rx_excvr_if_fifo_mode == E400G_50G_5_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_rx_fec_enable == E400G_50G_5_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_rx_master_bond_chnl == E400G_50G_5_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_rx_pcs_mode == E400G_50G_5_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_rx_primary_use == E400G_50G_5_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_rx_xcvr_width == E400G_50G_5_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_speed_map == E400G_50G_5_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_sup_mode == E400G_50G_5_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_sys_clk_src == E400G_50G_5_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_tx_aib_if_fifo_mode == E400G_50G_5_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_tx_excvr_gb_ratio_mode == E400G_50G_5_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_tx_excvr_if_fifo_mode == E400G_50G_5_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_tx_fec_enable == E400G_50G_5_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_tx_master_bond_chnl == E400G_50G_5_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_tx_pcs_mode == E400G_50G_5_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_tx_primary_use == E400G_50G_5_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_tx_xcvr_width == E400G_50G_5_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_xcvr_mode == E400G_50G_5_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_5_xcvr_type == E400G_50G_5_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_aib2_rx_st_clk_en == E400G_50G_6_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_aib2_tx_st_clk_en == E400G_50G_6_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_aib3_rx_st_clk_en == E400G_50G_6_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_aib3_tx_st_clk_en == E400G_50G_6_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_aibif_data_valid == E400G_50G_6_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_duplex_mode == E400G_50G_6_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_fec_clk_src == E400G_50G_6_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_fec_error == E400G_50G_6_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_fec_mode == E400G_50G_6_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_fec_spec == E400G_50G_6_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_lpbk_mode == E400G_50G_6_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_flow_control == E400G_50G_6_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_flow_control_holdoff_mode == E400G_50G_6_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_link_fault_mode == E400G_50G_6_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_mode == E400G_50G_6_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_rx_ptp_phy_lane_num == E400G_50G_6_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_tx_ipg_size == E400G_50G_6_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_tx_ptp_phy_lane_num == E400G_50G_6_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_pcs_ber_mon_mode == E400G_50G_6_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_pcs_pcs_ber_mon_mode == E400G_50G_6_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_ptp_mode == E400G_50G_6_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_rx_aib_if_fifo_mode == E400G_50G_6_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_rx_excvr_gb_ratio_mode == E400G_50G_6_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_rx_excvr_if_fifo_mode == E400G_50G_6_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_rx_fec_enable == E400G_50G_6_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_rx_master_bond_chnl == E400G_50G_6_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_rx_pcs_mode == E400G_50G_6_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_rx_primary_use == E400G_50G_6_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_rx_xcvr_width == E400G_50G_6_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_speed_map == E400G_50G_6_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_sup_mode == E400G_50G_6_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_sys_clk_src == E400G_50G_6_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_tx_aib_if_fifo_mode == E400G_50G_6_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_tx_excvr_gb_ratio_mode == E400G_50G_6_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_tx_excvr_if_fifo_mode == E400G_50G_6_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_tx_fec_enable == E400G_50G_6_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_tx_master_bond_chnl == E400G_50G_6_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_tx_pcs_mode == E400G_50G_6_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_tx_primary_use == E400G_50G_6_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_tx_xcvr_width == E400G_50G_6_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_xcvr_mode == E400G_50G_6_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_6_xcvr_type == E400G_50G_6_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_aib2_rx_st_clk_en == E400G_50G_7_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_aib2_tx_st_clk_en == E400G_50G_7_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_aib3_rx_st_clk_en == E400G_50G_7_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_aib3_tx_st_clk_en == E400G_50G_7_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_aibif_data_valid == E400G_50G_7_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_duplex_mode == E400G_50G_7_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_fec_clk_src == E400G_50G_7_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_fec_error == E400G_50G_7_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_fec_mode == E400G_50G_7_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_fec_spec == E400G_50G_7_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_lpbk_mode == E400G_50G_7_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_flow_control == E400G_50G_7_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_flow_control_holdoff_mode == E400G_50G_7_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_link_fault_mode == E400G_50G_7_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_mode == E400G_50G_7_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_rx_ptp_phy_lane_num == E400G_50G_7_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_tx_ipg_size == E400G_50G_7_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_tx_ptp_phy_lane_num == E400G_50G_7_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_pcs_ber_mon_mode == E400G_50G_7_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_pcs_pcs_ber_mon_mode == E400G_50G_7_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_ptp_mode == E400G_50G_7_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_rx_aib_if_fifo_mode == E400G_50G_7_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_rx_excvr_gb_ratio_mode == E400G_50G_7_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_rx_excvr_if_fifo_mode == E400G_50G_7_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_rx_fec_enable == E400G_50G_7_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_rx_master_bond_chnl == E400G_50G_7_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_rx_pcs_mode == E400G_50G_7_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_rx_primary_use == E400G_50G_7_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_rx_xcvr_width == E400G_50G_7_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_speed_map == E400G_50G_7_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_sup_mode == E400G_50G_7_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_sys_clk_src == E400G_50G_7_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_tx_aib_if_fifo_mode == E400G_50G_7_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_tx_excvr_gb_ratio_mode == E400G_50G_7_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_tx_excvr_if_fifo_mode == E400G_50G_7_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_tx_fec_enable == E400G_50G_7_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_tx_master_bond_chnl == E400G_50G_7_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_tx_pcs_mode == E400G_50G_7_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_tx_primary_use == E400G_50G_7_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_tx_xcvr_width == E400G_50G_7_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_xcvr_mode == E400G_50G_7_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_50g_7_xcvr_type == E400G_50G_7_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk0_duplex_mode == E400G_BK0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk0_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk0_rx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk0_rx_master_bond_chnl == E400G_BK0_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk0_rx_protocol == E400G_BK0_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk0_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk0_rx_xcvr_width == E400G_BK0_RX_XCVR_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk0_speed_bucket == E400G_BK0_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk0_sys_clk_src == E400G_BK0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk0_tx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk0_tx_master_bond_chnl == E400G_BK0_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk0_tx_protocol == E400G_BK0_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk0_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk0_tx_xcvr_width == E400G_BK0_TX_XCVR_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk0_txrx_channel_operation == E400G_BK0_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk0_txrx_line_encoding_type == E400G_BK0_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk0_xcvr_mode == E400G_BK0_XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk1_duplex_mode == E400G_BK1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk1_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk1_rx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk1_rx_master_bond_chnl == E400G_BK1_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk1_rx_protocol == E400G_BK1_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk1_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk1_rx_xcvr_width == E400G_BK1_RX_XCVR_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk1_speed_bucket == E400G_BK1_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk1_sys_clk_src == E400G_BK1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk1_tx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk1_tx_master_bond_chnl == E400G_BK1_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk1_tx_protocol == E400G_BK1_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk1_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk1_tx_xcvr_width == E400G_BK1_TX_XCVR_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk1_txrx_channel_operation == E400G_BK1_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk1_txrx_line_encoding_type == E400G_BK1_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk1_xcvr_mode == E400G_BK1_XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk2_duplex_mode == E400G_BK2_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk2_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk2_rx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk2_rx_master_bond_chnl == E400G_BK2_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk2_rx_protocol == E400G_BK2_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk2_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk2_rx_xcvr_width == E400G_BK2_RX_XCVR_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk2_speed_bucket == E400G_BK2_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk2_sys_clk_src == E400G_BK2_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk2_tx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk2_tx_master_bond_chnl == E400G_BK2_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk2_tx_protocol == E400G_BK2_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk2_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk2_tx_xcvr_width == E400G_BK2_TX_XCVR_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk2_txrx_channel_operation == E400G_BK2_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk2_txrx_line_encoding_type == E400G_BK2_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk2_xcvr_mode == E400G_BK2_XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk3_duplex_mode == E400G_BK3_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk3_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk3_rx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk3_rx_master_bond_chnl == E400G_BK3_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk3_rx_protocol == E400G_BK3_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk3_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk3_rx_xcvr_width == E400G_BK3_RX_XCVR_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk3_speed_bucket == E400G_BK3_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk3_sys_clk_src == E400G_BK3_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk3_tx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk3_tx_master_bond_chnl == E400G_BK3_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk3_tx_protocol == E400G_BK3_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk3_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk3_tx_xcvr_width == E400G_BK3_TX_XCVR_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk3_txrx_channel_operation == E400G_BK3_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk3_txrx_line_encoding_type == E400G_BK3_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_bk3_xcvr_mode == E400G_BK3_XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ptp0_aib2_div2_clk == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ptp1_aib2_div2_clk == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream0_duplex_mode == E400G_STREAM0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream0_ptp_mode == E400G_STREAM0_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream0_rx_aib_if_fifo_mode == E400G_STREAM0_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream0_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream0_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream0_rx_excvr_if_fifo_mode == E400G_STREAM0_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream0_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream0_rx_primary_use == E400G_STREAM0_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream0_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream0_rx_xcvr_width == E400G_STREAM0_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream0_sys_clk_src == E400G_STREAM0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream0_tx_aib_if_fifo_mode == E400G_STREAM0_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream0_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream0_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream0_tx_excvr_if_fifo_mode == E400G_STREAM0_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream0_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream0_tx_primary_use == E400G_STREAM0_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream0_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream0_tx_xcvr_width == E400G_STREAM0_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream10_duplex_mode == E400G_STREAM10_DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream10_ptp_mode == E400G_STREAM10_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream10_rx_aib_if_fifo_mode == E400G_STREAM10_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream10_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream10_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream10_rx_excvr_if_fifo_mode == E400G_STREAM10_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream10_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream10_rx_primary_use == E400G_STREAM10_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream10_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream10_rx_xcvr_width == E400G_STREAM10_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream10_sys_clk_src == E400G_STREAM10_SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream10_tx_aib_if_fifo_mode == E400G_STREAM10_TX_AIB_IF_FIFO_MODE_PHASECOMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream10_tx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream10_tx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream10_tx_excvr_if_fifo_mode == E400G_STREAM10_TX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream10_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream10_tx_primary_use == E400G_STREAM10_TX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream10_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream10_tx_xcvr_width == E400G_STREAM10_TX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream11_duplex_mode == E400G_STREAM11_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream11_ptp_mode == E400G_STREAM11_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream11_rx_aib_if_fifo_mode == E400G_STREAM11_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream11_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream11_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream11_rx_excvr_if_fifo_mode == E400G_STREAM11_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream11_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream11_rx_primary_use == E400G_STREAM11_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream11_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream11_rx_xcvr_width == E400G_STREAM11_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream11_sys_clk_src == E400G_STREAM11_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream11_tx_aib_if_fifo_mode == E400G_STREAM11_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream11_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream11_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream11_tx_excvr_if_fifo_mode == E400G_STREAM11_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream11_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream11_tx_primary_use == E400G_STREAM11_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream11_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream11_tx_xcvr_width == E400G_STREAM11_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream12_duplex_mode == E400G_STREAM12_DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream12_ptp_mode == E400G_STREAM12_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream12_rx_aib_if_fifo_mode == E400G_STREAM12_RX_AIB_IF_FIFO_MODE_REGISTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream12_rx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream12_rx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream12_rx_excvr_if_fifo_mode == E400G_STREAM12_RX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream12_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream12_rx_primary_use == E400G_STREAM12_RX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream12_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream12_rx_xcvr_width == E400G_STREAM12_RX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream12_sys_clk_src == E400G_STREAM12_SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream12_tx_aib_if_fifo_mode == E400G_STREAM12_TX_AIB_IF_FIFO_MODE_PHASECOMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream12_tx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream12_tx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream12_tx_excvr_if_fifo_mode == E400G_STREAM12_TX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream12_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream12_tx_primary_use == E400G_STREAM12_TX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream12_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream12_tx_xcvr_width == E400G_STREAM12_TX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream13_duplex_mode == E400G_STREAM13_DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream13_ptp_mode == E400G_STREAM13_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream13_rx_aib_if_fifo_mode == E400G_STREAM13_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream13_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream13_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream13_rx_excvr_if_fifo_mode == E400G_STREAM13_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream13_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream13_rx_primary_use == E400G_STREAM13_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream13_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream13_rx_xcvr_width == E400G_STREAM13_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream13_sys_clk_src == E400G_STREAM13_SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream13_tx_aib_if_fifo_mode == E400G_STREAM13_TX_AIB_IF_FIFO_MODE_PHASECOMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream13_tx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream13_tx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream13_tx_excvr_if_fifo_mode == E400G_STREAM13_TX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream13_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream13_tx_primary_use == E400G_STREAM13_TX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream13_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream13_tx_xcvr_width == E400G_STREAM13_TX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream14_duplex_mode == E400G_STREAM14_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream14_ptp_mode == E400G_STREAM14_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream14_rx_aib_if_fifo_mode == E400G_STREAM14_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream14_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream14_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream14_rx_excvr_if_fifo_mode == E400G_STREAM14_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream14_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream14_rx_primary_use == E400G_STREAM14_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream14_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream14_rx_xcvr_width == E400G_STREAM14_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream14_sys_clk_src == E400G_STREAM14_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream14_tx_aib_if_fifo_mode == E400G_STREAM14_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream14_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream14_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream14_tx_excvr_if_fifo_mode == E400G_STREAM14_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream14_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream14_tx_primary_use == E400G_STREAM14_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream14_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream14_tx_xcvr_width == E400G_STREAM14_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream15_duplex_mode == E400G_STREAM15_DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream15_ptp_mode == E400G_STREAM15_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream15_rx_aib_if_fifo_mode == E400G_STREAM15_RX_AIB_IF_FIFO_MODE_REGISTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream15_rx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream15_rx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream15_rx_excvr_if_fifo_mode == E400G_STREAM15_RX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream15_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream15_rx_primary_use == E400G_STREAM15_RX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream15_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream15_rx_xcvr_width == E400G_STREAM15_RX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream15_sys_clk_src == E400G_STREAM15_SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream15_tx_aib_if_fifo_mode == E400G_STREAM15_TX_AIB_IF_FIFO_MODE_PHASECOMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream15_tx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream15_tx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream15_tx_excvr_if_fifo_mode == E400G_STREAM15_TX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream15_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream15_tx_primary_use == E400G_STREAM15_TX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream15_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream15_tx_xcvr_width == E400G_STREAM15_TX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream16_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream17_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream1_duplex_mode == E400G_STREAM1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream1_ptp_mode == E400G_STREAM1_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream1_rx_aib_if_fifo_mode == E400G_STREAM1_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream1_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream1_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream1_rx_excvr_if_fifo_mode == E400G_STREAM1_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream1_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream1_rx_primary_use == E400G_STREAM1_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream1_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream1_rx_xcvr_width == E400G_STREAM1_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream1_sys_clk_src == E400G_STREAM1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream1_tx_aib_if_fifo_mode == E400G_STREAM1_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream1_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream1_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream1_tx_excvr_if_fifo_mode == E400G_STREAM1_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream1_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream1_tx_primary_use == E400G_STREAM1_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream1_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream1_tx_xcvr_width == E400G_STREAM1_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream2_duplex_mode == E400G_STREAM2_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream2_ptp_mode == E400G_STREAM2_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream2_rx_aib_if_fifo_mode == E400G_STREAM2_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream2_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream2_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream2_rx_excvr_if_fifo_mode == E400G_STREAM2_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream2_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream2_rx_primary_use == E400G_STREAM2_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream2_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream2_rx_xcvr_width == E400G_STREAM2_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream2_sys_clk_src == E400G_STREAM2_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream2_tx_aib_if_fifo_mode == E400G_STREAM2_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream2_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream2_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream2_tx_excvr_if_fifo_mode == E400G_STREAM2_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream2_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream2_tx_primary_use == E400G_STREAM2_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream2_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream2_tx_xcvr_width == E400G_STREAM2_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream3_duplex_mode == E400G_STREAM3_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream3_ptp_mode == E400G_STREAM3_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream3_rx_aib_if_fifo_mode == E400G_STREAM3_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream3_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream3_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream3_rx_excvr_if_fifo_mode == E400G_STREAM3_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream3_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream3_rx_primary_use == E400G_STREAM3_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream3_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream3_rx_xcvr_width == E400G_STREAM3_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream3_sys_clk_src == E400G_STREAM3_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream3_tx_aib_if_fifo_mode == E400G_STREAM3_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream3_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream3_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream3_tx_excvr_if_fifo_mode == E400G_STREAM3_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream3_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream3_tx_primary_use == E400G_STREAM3_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream3_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream3_tx_xcvr_width == E400G_STREAM3_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream4_duplex_mode == E400G_STREAM4_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream4_ptp_mode == E400G_STREAM4_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream4_rx_aib_if_fifo_mode == E400G_STREAM4_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream4_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream4_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream4_rx_excvr_if_fifo_mode == E400G_STREAM4_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream4_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream4_rx_primary_use == E400G_STREAM4_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream4_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream4_rx_xcvr_width == E400G_STREAM4_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream4_sys_clk_src == E400G_STREAM4_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream4_tx_aib_if_fifo_mode == E400G_STREAM4_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream4_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream4_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream4_tx_excvr_if_fifo_mode == E400G_STREAM4_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream4_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream4_tx_primary_use == E400G_STREAM4_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream4_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream4_tx_xcvr_width == E400G_STREAM4_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream5_duplex_mode == E400G_STREAM5_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream5_ptp_mode == E400G_STREAM5_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream5_rx_aib_if_fifo_mode == E400G_STREAM5_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream5_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream5_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream5_rx_excvr_if_fifo_mode == E400G_STREAM5_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream5_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream5_rx_primary_use == E400G_STREAM5_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream5_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream5_rx_xcvr_width == E400G_STREAM5_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream5_sys_clk_src == E400G_STREAM5_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream5_tx_aib_if_fifo_mode == E400G_STREAM5_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream5_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream5_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream5_tx_excvr_if_fifo_mode == E400G_STREAM5_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream5_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream5_tx_primary_use == E400G_STREAM5_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream5_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream5_tx_xcvr_width == E400G_STREAM5_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream6_duplex_mode == E400G_STREAM6_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream6_ptp_mode == E400G_STREAM6_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream6_rx_aib_if_fifo_mode == E400G_STREAM6_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream6_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream6_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream6_rx_excvr_if_fifo_mode == E400G_STREAM6_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream6_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream6_rx_primary_use == E400G_STREAM6_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream6_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream6_rx_xcvr_width == E400G_STREAM6_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream6_sys_clk_src == E400G_STREAM6_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream6_tx_aib_if_fifo_mode == E400G_STREAM6_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream6_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream6_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream6_tx_excvr_if_fifo_mode == E400G_STREAM6_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream6_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream6_tx_primary_use == E400G_STREAM6_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream6_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream6_tx_xcvr_width == E400G_STREAM6_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream7_duplex_mode == E400G_STREAM7_DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream7_ptp_mode == E400G_STREAM7_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream7_rx_aib_if_fifo_mode == E400G_STREAM7_RX_AIB_IF_FIFO_MODE_REGISTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream7_rx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream7_rx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream7_rx_excvr_if_fifo_mode == E400G_STREAM7_RX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream7_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream7_rx_primary_use == E400G_STREAM7_RX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream7_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream7_rx_xcvr_width == E400G_STREAM7_RX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream7_sys_clk_src == E400G_STREAM7_SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream7_tx_aib_if_fifo_mode == E400G_STREAM7_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream7_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream7_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream7_tx_excvr_if_fifo_mode == E400G_STREAM7_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream7_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream7_tx_primary_use == E400G_STREAM7_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream7_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream7_tx_xcvr_width == E400G_STREAM7_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream8_duplex_mode == E400G_STREAM8_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream8_ptp_mode == E400G_STREAM8_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream8_rx_aib_if_fifo_mode == E400G_STREAM8_RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream8_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream8_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream8_rx_excvr_if_fifo_mode == E400G_STREAM8_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream8_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream8_rx_primary_use == E400G_STREAM8_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream8_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream8_rx_xcvr_width == E400G_STREAM8_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream8_sys_clk_src == E400G_STREAM8_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream8_tx_aib_if_fifo_mode == E400G_STREAM8_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream8_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream8_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream8_tx_excvr_if_fifo_mode == E400G_STREAM8_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream8_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream8_tx_primary_use == E400G_STREAM8_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream8_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream8_tx_xcvr_width == E400G_STREAM8_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream9_duplex_mode == E400G_STREAM9_DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream9_ptp_mode == E400G_STREAM9_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream9_rx_aib_if_fifo_mode == E400G_STREAM9_RX_AIB_IF_FIFO_MODE_REGISTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream9_rx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream9_rx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream9_rx_excvr_if_fifo_mode == E400G_STREAM9_RX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream9_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream9_rx_primary_use == E400G_STREAM9_RX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream9_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream9_rx_xcvr_width == E400G_STREAM9_RX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream9_sys_clk_src == E400G_STREAM9_SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream9_tx_aib_if_fifo_mode == E400G_STREAM9_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream9_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream9_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream9_tx_excvr_if_fifo_mode == E400G_STREAM9_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream9_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream9_tx_primary_use == E400G_STREAM9_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream9_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_stream9_tx_xcvr_width == E400G_STREAM9_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux0_duplex_mode == E400G_UX0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux0_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux0_rx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux0_rx_master_bond_chnl == E400G_UX0_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux0_rx_protocol == E400G_UX0_RX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux0_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux0_rx_xcvr_width == E400G_UX0_RX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux0_speed_bucket == E400G_UX0_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux0_sys_clk_src == E400G_UX0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux0_tx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux0_tx_master_bond_chnl == E400G_UX0_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux0_tx_protocol == E400G_UX0_TX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux0_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux0_tx_xcvr_width == E400G_UX0_TX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux0_txrx_channel_operation == E400G_UX0_TXRX_CHANNEL_OPERATION_DUAL_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux0_txrx_line_encoding_type == E400G_UX0_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux0_xcvr_mode == E400G_UX0_XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux10_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux10_duplex_mode == E400G_UX10_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux10_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux10_rx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux10_rx_master_bond_chnl == E400G_UX10_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux10_rx_protocol == E400G_UX10_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux10_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux10_rx_xcvr_width == E400G_UX10_RX_XCVR_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux10_speed_bucket == E400G_UX10_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux10_sys_clk_src == E400G_UX10_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux10_tx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux10_tx_master_bond_chnl == E400G_UX10_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux10_tx_protocol == E400G_UX10_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux10_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux10_tx_xcvr_width == E400G_UX10_TX_XCVR_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux10_txrx_channel_operation == E400G_UX10_TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux10_txrx_line_encoding_type == E400G_UX10_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux10_xcvr_mode == E400G_UX10_XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux11_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux11_duplex_mode == E400G_UX11_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux11_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux11_rx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux11_rx_master_bond_chnl == E400G_UX11_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux11_rx_protocol == E400G_UX11_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux11_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux11_rx_xcvr_width == E400G_UX11_RX_XCVR_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux11_speed_bucket == E400G_UX11_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux11_sys_clk_src == E400G_UX11_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux11_tx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux11_tx_master_bond_chnl == E400G_UX11_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux11_tx_protocol == E400G_UX11_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux11_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux11_tx_xcvr_width == E400G_UX11_TX_XCVR_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux11_txrx_channel_operation == E400G_UX11_TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux11_txrx_line_encoding_type == E400G_UX11_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux11_xcvr_mode == E400G_UX11_XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux12_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux12_duplex_mode == E400G_UX12_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux12_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux12_rx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux12_rx_master_bond_chnl == E400G_UX12_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux12_rx_protocol == E400G_UX12_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux12_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux12_rx_xcvr_width == E400G_UX12_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux12_speed_bucket == E400G_UX12_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux12_sys_clk_src == E400G_UX12_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux12_tx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux12_tx_master_bond_chnl == E400G_UX12_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux12_tx_protocol == E400G_UX12_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux12_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux12_tx_xcvr_width == E400G_UX12_TX_XCVR_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux12_txrx_channel_operation == E400G_UX12_TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux12_txrx_line_encoding_type == E400G_UX12_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux12_xcvr_mode == E400G_UX12_XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux13_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux13_duplex_mode == E400G_UX13_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux13_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux13_rx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux13_rx_master_bond_chnl == E400G_UX13_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux13_rx_protocol == E400G_UX13_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux13_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux13_rx_xcvr_width == E400G_UX13_RX_XCVR_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux13_speed_bucket == E400G_UX13_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux13_sys_clk_src == E400G_UX13_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux13_tx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux13_tx_master_bond_chnl == E400G_UX13_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux13_tx_protocol == E400G_UX13_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux13_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux13_tx_xcvr_width == E400G_UX13_TX_XCVR_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux13_txrx_channel_operation == E400G_UX13_TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux13_txrx_line_encoding_type == E400G_UX13_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux13_xcvr_mode == E400G_UX13_XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux14_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux14_duplex_mode == E400G_UX14_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux14_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux14_rx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux14_rx_master_bond_chnl == E400G_UX14_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux14_rx_protocol == E400G_UX14_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux14_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux14_rx_xcvr_width == E400G_UX14_RX_XCVR_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux14_speed_bucket == E400G_UX14_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux14_sys_clk_src == E400G_UX14_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux14_tx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux14_tx_master_bond_chnl == E400G_UX14_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux14_tx_protocol == E400G_UX14_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux14_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux14_tx_xcvr_width == E400G_UX14_TX_XCVR_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux14_txrx_channel_operation == E400G_UX14_TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux14_txrx_line_encoding_type == E400G_UX14_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux14_xcvr_mode == E400G_UX14_XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux15_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux15_duplex_mode == E400G_UX15_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux15_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux15_rx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux15_rx_master_bond_chnl == E400G_UX15_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux15_rx_protocol == E400G_UX15_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux15_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux15_rx_xcvr_width == E400G_UX15_RX_XCVR_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux15_speed_bucket == E400G_UX15_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux15_sys_clk_src == E400G_UX15_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux15_tx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux15_tx_master_bond_chnl == E400G_UX15_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux15_tx_protocol == E400G_UX15_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux15_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux15_tx_xcvr_width == E400G_UX15_TX_XCVR_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux15_txrx_channel_operation == E400G_UX15_TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux15_txrx_line_encoding_type == E400G_UX15_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux15_xcvr_mode == E400G_UX15_XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux1_duplex_mode == E400G_UX1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux1_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux1_rx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux1_rx_master_bond_chnl == E400G_UX1_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux1_rx_protocol == E400G_UX1_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux1_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux1_rx_xcvr_width == E400G_UX1_RX_XCVR_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux1_speed_bucket == E400G_UX1_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux1_sys_clk_src == E400G_UX1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux1_tx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux1_tx_master_bond_chnl == E400G_UX1_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux1_tx_protocol == E400G_UX1_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux1_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux1_tx_xcvr_width == E400G_UX1_TX_XCVR_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux1_txrx_channel_operation == E400G_UX1_TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux1_txrx_line_encoding_type == E400G_UX1_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux1_xcvr_mode == E400G_UX1_XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux2_duplex_mode == E400G_UX2_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux2_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux2_rx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux2_rx_master_bond_chnl == E400G_UX2_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux2_rx_protocol == E400G_UX2_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux2_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux2_rx_xcvr_width == E400G_UX2_RX_XCVR_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux2_speed_bucket == E400G_UX2_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux2_sys_clk_src == E400G_UX2_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux2_tx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux2_tx_master_bond_chnl == E400G_UX2_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux2_tx_protocol == E400G_UX2_TX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux2_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux2_tx_xcvr_width == E400G_UX2_TX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux2_txrx_channel_operation == E400G_UX2_TXRX_CHANNEL_OPERATION_DUAL_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux2_txrx_line_encoding_type == E400G_UX2_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux2_xcvr_mode == E400G_UX2_XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux3_duplex_mode == E400G_UX3_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux3_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux3_rx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux3_rx_master_bond_chnl == E400G_UX3_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux3_rx_protocol == E400G_UX3_RX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux3_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux3_rx_xcvr_width == E400G_UX3_RX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux3_speed_bucket == E400G_UX3_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux3_sys_clk_src == E400G_UX3_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux3_tx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux3_tx_master_bond_chnl == E400G_UX3_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux3_tx_protocol == E400G_UX3_TX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux3_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux3_tx_xcvr_width == E400G_UX3_TX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux3_txrx_channel_operation == E400G_UX3_TXRX_CHANNEL_OPERATION_DUAL_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux3_txrx_line_encoding_type == E400G_UX3_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux3_xcvr_mode == E400G_UX3_XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux4_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux4_duplex_mode == E400G_UX4_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux4_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux4_rx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux4_rx_master_bond_chnl == E400G_UX4_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux4_rx_protocol == E400G_UX4_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux4_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux4_rx_xcvr_width == E400G_UX4_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux4_speed_bucket == E400G_UX4_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux4_sys_clk_src == E400G_UX4_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux4_tx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux4_tx_master_bond_chnl == E400G_UX4_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux4_tx_protocol == E400G_UX4_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux4_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux4_tx_xcvr_width == E400G_UX4_TX_XCVR_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux4_txrx_channel_operation == E400G_UX4_TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux4_txrx_line_encoding_type == E400G_UX4_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux4_xcvr_mode == E400G_UX4_XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux5_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux5_duplex_mode == E400G_UX5_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux5_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux5_rx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux5_rx_master_bond_chnl == E400G_UX5_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux5_rx_protocol == E400G_UX5_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux5_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux5_rx_xcvr_width == E400G_UX5_RX_XCVR_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux5_speed_bucket == E400G_UX5_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux5_sys_clk_src == E400G_UX5_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux5_tx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux5_tx_master_bond_chnl == E400G_UX5_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux5_tx_protocol == E400G_UX5_TX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux5_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux5_tx_xcvr_width == E400G_UX5_TX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux5_txrx_channel_operation == E400G_UX5_TXRX_CHANNEL_OPERATION_DUAL_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux5_txrx_line_encoding_type == E400G_UX5_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux5_xcvr_mode == E400G_UX5_XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux6_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux6_duplex_mode == E400G_UX6_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux6_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux6_rx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux6_rx_master_bond_chnl == E400G_UX6_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux6_rx_protocol == E400G_UX6_RX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux6_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux6_rx_xcvr_width == E400G_UX6_RX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux6_speed_bucket == E400G_UX6_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux6_sys_clk_src == E400G_UX6_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux6_tx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux6_tx_master_bond_chnl == E400G_UX6_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux6_tx_protocol == E400G_UX6_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux6_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux6_tx_xcvr_width == E400G_UX6_TX_XCVR_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux6_txrx_channel_operation == E400G_UX6_TXRX_CHANNEL_OPERATION_DUAL_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux6_txrx_line_encoding_type == E400G_UX6_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux6_xcvr_mode == E400G_UX6_XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux7_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux7_duplex_mode == E400G_UX7_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux7_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux7_rx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux7_rx_master_bond_chnl == E400G_UX7_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux7_rx_protocol == E400G_UX7_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux7_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux7_rx_xcvr_width == E400G_UX7_RX_XCVR_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux7_speed_bucket == E400G_UX7_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux7_sys_clk_src == E400G_UX7_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux7_tx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux7_tx_master_bond_chnl == E400G_UX7_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux7_tx_protocol == E400G_UX7_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux7_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux7_tx_xcvr_width == E400G_UX7_TX_XCVR_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux7_txrx_channel_operation == E400G_UX7_TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux7_txrx_line_encoding_type == E400G_UX7_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux7_xcvr_mode == E400G_UX7_XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux8_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux8_duplex_mode == E400G_UX8_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux8_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux8_rx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux8_rx_master_bond_chnl == E400G_UX8_RX_MASTER_BOND_CHNL_CH15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux8_rx_protocol == E400G_UX8_RX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux8_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux8_rx_xcvr_width == E400G_UX8_RX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux8_speed_bucket == E400G_UX8_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux8_sys_clk_src == E400G_UX8_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux8_tx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux8_tx_master_bond_chnl == E400G_UX8_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux8_tx_protocol == E400G_UX8_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux8_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux8_tx_xcvr_width == E400G_UX8_TX_XCVR_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux8_txrx_channel_operation == E400G_UX8_TXRX_CHANNEL_OPERATION_DUAL_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux8_txrx_line_encoding_type == E400G_UX8_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux8_xcvr_mode == E400G_UX8_XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux9_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux9_duplex_mode == E400G_UX9_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux9_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux9_rx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux9_rx_master_bond_chnl == E400G_UX9_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux9_rx_protocol == E400G_UX9_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux9_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux9_rx_xcvr_width == E400G_UX9_RX_XCVR_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux9_speed_bucket == E400G_UX9_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux9_sys_clk_src == E400G_UX9_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux9_tx_bond_size == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux9_tx_master_bond_chnl == E400G_UX9_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux9_tx_protocol == E400G_UX9_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux9_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux9_tx_xcvr_width == E400G_UX9_TX_XCVR_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux9_txrx_channel_operation == E400G_UX9_TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux9_txrx_line_encoding_type == E400G_UX9_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_ux9_xcvr_mode == E400G_UX9_XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x0_duplex_mode == E400G_XCVR_SPEED_MAP_112E4X0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x0_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x0_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x0_rx_master_bond_chnl == E400G_XCVR_SPEED_MAP_112E4X0_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x0_rx_protocol == E400G_XCVR_SPEED_MAP_112E4X0_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x0_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x0_rx_xcvr_width == E400G_XCVR_SPEED_MAP_112E4X0_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x0_speed_bucket == E400G_XCVR_SPEED_MAP_112E4X0_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x0_sys_clk_src == E400G_XCVR_SPEED_MAP_112E4X0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x0_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x0_tx_master_bond_chnl == E400G_XCVR_SPEED_MAP_112E4X0_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x0_tx_protocol == E400G_XCVR_SPEED_MAP_112E4X0_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x0_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x0_tx_xcvr_width == E400G_XCVR_SPEED_MAP_112E4X0_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x0_txrx_channel_operation == E400G_XCVR_SPEED_MAP_112E4X0_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x0_txrx_line_encoding_type == E400G_XCVR_SPEED_MAP_112E4X0_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x0_xcvr_mode == E400G_XCVR_SPEED_MAP_112E4X0_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x1_duplex_mode == E400G_XCVR_SPEED_MAP_112E4X1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x1_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x1_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x1_rx_master_bond_chnl == E400G_XCVR_SPEED_MAP_112E4X1_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x1_rx_protocol == E400G_XCVR_SPEED_MAP_112E4X1_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x1_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x1_rx_xcvr_width == E400G_XCVR_SPEED_MAP_112E4X1_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x1_speed_bucket == E400G_XCVR_SPEED_MAP_112E4X1_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x1_sys_clk_src == E400G_XCVR_SPEED_MAP_112E4X1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x1_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x1_tx_master_bond_chnl == E400G_XCVR_SPEED_MAP_112E4X1_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x1_tx_protocol == E400G_XCVR_SPEED_MAP_112E4X1_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x1_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x1_tx_xcvr_width == E400G_XCVR_SPEED_MAP_112E4X1_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x1_txrx_channel_operation == E400G_XCVR_SPEED_MAP_112E4X1_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x1_txrx_line_encoding_type == E400G_XCVR_SPEED_MAP_112E4X1_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x1_xcvr_mode == E400G_XCVR_SPEED_MAP_112E4X1_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x2_duplex_mode == E400G_XCVR_SPEED_MAP_112E4X2_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x2_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x2_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x2_rx_master_bond_chnl == E400G_XCVR_SPEED_MAP_112E4X2_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x2_rx_protocol == E400G_XCVR_SPEED_MAP_112E4X2_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x2_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x2_rx_xcvr_width == E400G_XCVR_SPEED_MAP_112E4X2_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x2_speed_bucket == E400G_XCVR_SPEED_MAP_112E4X2_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x2_sys_clk_src == E400G_XCVR_SPEED_MAP_112E4X2_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x2_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x2_tx_master_bond_chnl == E400G_XCVR_SPEED_MAP_112E4X2_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x2_tx_protocol == E400G_XCVR_SPEED_MAP_112E4X2_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x2_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x2_tx_xcvr_width == E400G_XCVR_SPEED_MAP_112E4X2_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x2_txrx_channel_operation == E400G_XCVR_SPEED_MAP_112E4X2_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x2_txrx_line_encoding_type == E400G_XCVR_SPEED_MAP_112E4X2_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x2_xcvr_mode == E400G_XCVR_SPEED_MAP_112E4X2_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x3_duplex_mode == E400G_XCVR_SPEED_MAP_112E4X3_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x3_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x3_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x3_rx_master_bond_chnl == E400G_XCVR_SPEED_MAP_112E4X3_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x3_rx_protocol == E400G_XCVR_SPEED_MAP_112E4X3_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x3_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x3_rx_xcvr_width == E400G_XCVR_SPEED_MAP_112E4X3_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x3_speed_bucket == E400G_XCVR_SPEED_MAP_112E4X3_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x3_sys_clk_src == E400G_XCVR_SPEED_MAP_112E4X3_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x3_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x3_tx_master_bond_chnl == E400G_XCVR_SPEED_MAP_112E4X3_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x3_tx_protocol == E400G_XCVR_SPEED_MAP_112E4X3_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x3_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x3_tx_xcvr_width == E400G_XCVR_SPEED_MAP_112E4X3_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x3_txrx_channel_operation == E400G_XCVR_SPEED_MAP_112E4X3_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x3_txrx_line_encoding_type == E400G_XCVR_SPEED_MAP_112E4X3_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_112e4x3_xcvr_mode == E400G_XCVR_SPEED_MAP_112E4X3_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x0_duplex_mode == E400G_XCVR_SPEED_MAP_25E4X0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x0_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x0_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x0_rx_master_bond_chnl == E400G_XCVR_SPEED_MAP_25E4X0_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x0_rx_protocol == E400G_XCVR_SPEED_MAP_25E4X0_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x0_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x0_rx_xcvr_width == E400G_XCVR_SPEED_MAP_25E4X0_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x0_speed_bucket == E400G_XCVR_SPEED_MAP_25E4X0_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x0_sys_clk_src == E400G_XCVR_SPEED_MAP_25E4X0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x0_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x0_tx_master_bond_chnl == E400G_XCVR_SPEED_MAP_25E4X0_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x0_tx_protocol == E400G_XCVR_SPEED_MAP_25E4X0_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x0_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x0_tx_xcvr_width == E400G_XCVR_SPEED_MAP_25E4X0_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x0_txrx_channel_operation == E400G_XCVR_SPEED_MAP_25E4X0_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x0_txrx_line_encoding_type == E400G_XCVR_SPEED_MAP_25E4X0_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x0_xcvr_mode == E400G_XCVR_SPEED_MAP_25E4X0_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x10_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x10_duplex_mode == E400G_XCVR_SPEED_MAP_25E4X10_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x10_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x10_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x10_rx_master_bond_chnl == E400G_XCVR_SPEED_MAP_25E4X10_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x10_rx_protocol == E400G_XCVR_SPEED_MAP_25E4X10_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x10_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x10_rx_xcvr_width == E400G_XCVR_SPEED_MAP_25E4X10_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x10_speed_bucket == E400G_XCVR_SPEED_MAP_25E4X10_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x10_sys_clk_src == E400G_XCVR_SPEED_MAP_25E4X10_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x10_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x10_tx_master_bond_chnl == E400G_XCVR_SPEED_MAP_25E4X10_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x10_tx_protocol == E400G_XCVR_SPEED_MAP_25E4X10_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x10_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x10_tx_xcvr_width == E400G_XCVR_SPEED_MAP_25E4X10_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x10_txrx_channel_operation == E400G_XCVR_SPEED_MAP_25E4X10_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x10_txrx_line_encoding_type == E400G_XCVR_SPEED_MAP_25E4X10_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x10_xcvr_mode == E400G_XCVR_SPEED_MAP_25E4X10_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x11_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x11_duplex_mode == E400G_XCVR_SPEED_MAP_25E4X11_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x11_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x11_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x11_rx_master_bond_chnl == E400G_XCVR_SPEED_MAP_25E4X11_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x11_rx_protocol == E400G_XCVR_SPEED_MAP_25E4X11_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x11_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x11_rx_xcvr_width == E400G_XCVR_SPEED_MAP_25E4X11_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x11_speed_bucket == E400G_XCVR_SPEED_MAP_25E4X11_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x11_sys_clk_src == E400G_XCVR_SPEED_MAP_25E4X11_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x11_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x11_tx_master_bond_chnl == E400G_XCVR_SPEED_MAP_25E4X11_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x11_tx_protocol == E400G_XCVR_SPEED_MAP_25E4X11_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x11_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x11_tx_xcvr_width == E400G_XCVR_SPEED_MAP_25E4X11_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x11_txrx_channel_operation == E400G_XCVR_SPEED_MAP_25E4X11_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x11_txrx_line_encoding_type == E400G_XCVR_SPEED_MAP_25E4X11_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x11_xcvr_mode == E400G_XCVR_SPEED_MAP_25E4X11_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x12_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x12_duplex_mode == E400G_XCVR_SPEED_MAP_25E4X12_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x12_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x12_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x12_rx_master_bond_chnl == E400G_XCVR_SPEED_MAP_25E4X12_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x12_rx_protocol == E400G_XCVR_SPEED_MAP_25E4X12_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x12_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x12_rx_xcvr_width == E400G_XCVR_SPEED_MAP_25E4X12_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x12_speed_bucket == E400G_XCVR_SPEED_MAP_25E4X12_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x12_sys_clk_src == E400G_XCVR_SPEED_MAP_25E4X12_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x12_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x12_tx_master_bond_chnl == E400G_XCVR_SPEED_MAP_25E4X12_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x12_tx_protocol == E400G_XCVR_SPEED_MAP_25E4X12_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x12_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x12_tx_xcvr_width == E400G_XCVR_SPEED_MAP_25E4X12_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x12_txrx_channel_operation == E400G_XCVR_SPEED_MAP_25E4X12_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x12_txrx_line_encoding_type == E400G_XCVR_SPEED_MAP_25E4X12_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x12_xcvr_mode == E400G_XCVR_SPEED_MAP_25E4X12_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x13_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x13_duplex_mode == E400G_XCVR_SPEED_MAP_25E4X13_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x13_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x13_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x13_rx_master_bond_chnl == E400G_XCVR_SPEED_MAP_25E4X13_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x13_rx_protocol == E400G_XCVR_SPEED_MAP_25E4X13_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x13_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x13_rx_xcvr_width == E400G_XCVR_SPEED_MAP_25E4X13_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x13_speed_bucket == E400G_XCVR_SPEED_MAP_25E4X13_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x13_sys_clk_src == E400G_XCVR_SPEED_MAP_25E4X13_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x13_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x13_tx_master_bond_chnl == E400G_XCVR_SPEED_MAP_25E4X13_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x13_tx_protocol == E400G_XCVR_SPEED_MAP_25E4X13_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x13_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x13_tx_xcvr_width == E400G_XCVR_SPEED_MAP_25E4X13_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x13_txrx_channel_operation == E400G_XCVR_SPEED_MAP_25E4X13_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x13_txrx_line_encoding_type == E400G_XCVR_SPEED_MAP_25E4X13_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x13_xcvr_mode == E400G_XCVR_SPEED_MAP_25E4X13_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x14_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x14_duplex_mode == E400G_XCVR_SPEED_MAP_25E4X14_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x14_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x14_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x14_rx_master_bond_chnl == E400G_XCVR_SPEED_MAP_25E4X14_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x14_rx_protocol == E400G_XCVR_SPEED_MAP_25E4X14_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x14_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x14_rx_xcvr_width == E400G_XCVR_SPEED_MAP_25E4X14_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x14_speed_bucket == E400G_XCVR_SPEED_MAP_25E4X14_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x14_sys_clk_src == E400G_XCVR_SPEED_MAP_25E4X14_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x14_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x14_tx_master_bond_chnl == E400G_XCVR_SPEED_MAP_25E4X14_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x14_tx_protocol == E400G_XCVR_SPEED_MAP_25E4X14_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x14_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x14_tx_xcvr_width == E400G_XCVR_SPEED_MAP_25E4X14_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x14_txrx_channel_operation == E400G_XCVR_SPEED_MAP_25E4X14_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x14_txrx_line_encoding_type == E400G_XCVR_SPEED_MAP_25E4X14_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x14_xcvr_mode == E400G_XCVR_SPEED_MAP_25E4X14_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x15_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x15_duplex_mode == E400G_XCVR_SPEED_MAP_25E4X15_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x15_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x15_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x15_rx_master_bond_chnl == E400G_XCVR_SPEED_MAP_25E4X15_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x15_rx_protocol == E400G_XCVR_SPEED_MAP_25E4X15_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x15_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x15_rx_xcvr_width == E400G_XCVR_SPEED_MAP_25E4X15_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x15_speed_bucket == E400G_XCVR_SPEED_MAP_25E4X15_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x15_sys_clk_src == E400G_XCVR_SPEED_MAP_25E4X15_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x15_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x15_tx_master_bond_chnl == E400G_XCVR_SPEED_MAP_25E4X15_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x15_tx_protocol == E400G_XCVR_SPEED_MAP_25E4X15_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x15_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x15_tx_xcvr_width == E400G_XCVR_SPEED_MAP_25E4X15_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x15_txrx_channel_operation == E400G_XCVR_SPEED_MAP_25E4X15_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x15_txrx_line_encoding_type == E400G_XCVR_SPEED_MAP_25E4X15_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x15_xcvr_mode == E400G_XCVR_SPEED_MAP_25E4X15_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x1_duplex_mode == E400G_XCVR_SPEED_MAP_25E4X1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x1_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x1_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x1_rx_master_bond_chnl == E400G_XCVR_SPEED_MAP_25E4X1_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x1_rx_protocol == E400G_XCVR_SPEED_MAP_25E4X1_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x1_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x1_rx_xcvr_width == E400G_XCVR_SPEED_MAP_25E4X1_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x1_speed_bucket == E400G_XCVR_SPEED_MAP_25E4X1_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x1_sys_clk_src == E400G_XCVR_SPEED_MAP_25E4X1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x1_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x1_tx_master_bond_chnl == E400G_XCVR_SPEED_MAP_25E4X1_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x1_tx_protocol == E400G_XCVR_SPEED_MAP_25E4X1_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x1_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x1_tx_xcvr_width == E400G_XCVR_SPEED_MAP_25E4X1_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x1_txrx_channel_operation == E400G_XCVR_SPEED_MAP_25E4X1_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x1_txrx_line_encoding_type == E400G_XCVR_SPEED_MAP_25E4X1_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x1_xcvr_mode == E400G_XCVR_SPEED_MAP_25E4X1_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x2_duplex_mode == E400G_XCVR_SPEED_MAP_25E4X2_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x2_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x2_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x2_rx_master_bond_chnl == E400G_XCVR_SPEED_MAP_25E4X2_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x2_rx_protocol == E400G_XCVR_SPEED_MAP_25E4X2_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x2_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x2_rx_xcvr_width == E400G_XCVR_SPEED_MAP_25E4X2_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x2_speed_bucket == E400G_XCVR_SPEED_MAP_25E4X2_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x2_sys_clk_src == E400G_XCVR_SPEED_MAP_25E4X2_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x2_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x2_tx_master_bond_chnl == E400G_XCVR_SPEED_MAP_25E4X2_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x2_tx_protocol == E400G_XCVR_SPEED_MAP_25E4X2_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x2_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x2_tx_xcvr_width == E400G_XCVR_SPEED_MAP_25E4X2_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x2_txrx_channel_operation == E400G_XCVR_SPEED_MAP_25E4X2_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x2_txrx_line_encoding_type == E400G_XCVR_SPEED_MAP_25E4X2_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x2_xcvr_mode == E400G_XCVR_SPEED_MAP_25E4X2_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x3_duplex_mode == E400G_XCVR_SPEED_MAP_25E4X3_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x3_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x3_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x3_rx_master_bond_chnl == E400G_XCVR_SPEED_MAP_25E4X3_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x3_rx_protocol == E400G_XCVR_SPEED_MAP_25E4X3_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x3_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x3_rx_xcvr_width == E400G_XCVR_SPEED_MAP_25E4X3_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x3_speed_bucket == E400G_XCVR_SPEED_MAP_25E4X3_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x3_sys_clk_src == E400G_XCVR_SPEED_MAP_25E4X3_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x3_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x3_tx_master_bond_chnl == E400G_XCVR_SPEED_MAP_25E4X3_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x3_tx_protocol == E400G_XCVR_SPEED_MAP_25E4X3_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x3_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x3_tx_xcvr_width == E400G_XCVR_SPEED_MAP_25E4X3_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x3_txrx_channel_operation == E400G_XCVR_SPEED_MAP_25E4X3_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x3_txrx_line_encoding_type == E400G_XCVR_SPEED_MAP_25E4X3_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x3_xcvr_mode == E400G_XCVR_SPEED_MAP_25E4X3_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x4_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x4_duplex_mode == E400G_XCVR_SPEED_MAP_25E4X4_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x4_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x4_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x4_rx_master_bond_chnl == E400G_XCVR_SPEED_MAP_25E4X4_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x4_rx_protocol == E400G_XCVR_SPEED_MAP_25E4X4_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x4_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x4_rx_xcvr_width == E400G_XCVR_SPEED_MAP_25E4X4_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x4_speed_bucket == E400G_XCVR_SPEED_MAP_25E4X4_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x4_sys_clk_src == E400G_XCVR_SPEED_MAP_25E4X4_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x4_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x4_tx_master_bond_chnl == E400G_XCVR_SPEED_MAP_25E4X4_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x4_tx_protocol == E400G_XCVR_SPEED_MAP_25E4X4_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x4_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x4_tx_xcvr_width == E400G_XCVR_SPEED_MAP_25E4X4_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x4_txrx_channel_operation == E400G_XCVR_SPEED_MAP_25E4X4_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x4_txrx_line_encoding_type == E400G_XCVR_SPEED_MAP_25E4X4_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x4_xcvr_mode == E400G_XCVR_SPEED_MAP_25E4X4_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x5_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x5_duplex_mode == E400G_XCVR_SPEED_MAP_25E4X5_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x5_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x5_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x5_rx_master_bond_chnl == E400G_XCVR_SPEED_MAP_25E4X5_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x5_rx_protocol == E400G_XCVR_SPEED_MAP_25E4X5_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x5_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x5_rx_xcvr_width == E400G_XCVR_SPEED_MAP_25E4X5_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x5_speed_bucket == E400G_XCVR_SPEED_MAP_25E4X5_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x5_sys_clk_src == E400G_XCVR_SPEED_MAP_25E4X5_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x5_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x5_tx_master_bond_chnl == E400G_XCVR_SPEED_MAP_25E4X5_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x5_tx_protocol == E400G_XCVR_SPEED_MAP_25E4X5_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x5_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x5_tx_xcvr_width == E400G_XCVR_SPEED_MAP_25E4X5_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x5_txrx_channel_operation == E400G_XCVR_SPEED_MAP_25E4X5_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x5_txrx_line_encoding_type == E400G_XCVR_SPEED_MAP_25E4X5_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x5_xcvr_mode == E400G_XCVR_SPEED_MAP_25E4X5_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x6_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x6_duplex_mode == E400G_XCVR_SPEED_MAP_25E4X6_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x6_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x6_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x6_rx_master_bond_chnl == E400G_XCVR_SPEED_MAP_25E4X6_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x6_rx_protocol == E400G_XCVR_SPEED_MAP_25E4X6_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x6_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x6_rx_xcvr_width == E400G_XCVR_SPEED_MAP_25E4X6_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x6_speed_bucket == E400G_XCVR_SPEED_MAP_25E4X6_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x6_sys_clk_src == E400G_XCVR_SPEED_MAP_25E4X6_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x6_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x6_tx_master_bond_chnl == E400G_XCVR_SPEED_MAP_25E4X6_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x6_tx_protocol == E400G_XCVR_SPEED_MAP_25E4X6_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x6_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x6_tx_xcvr_width == E400G_XCVR_SPEED_MAP_25E4X6_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x6_txrx_channel_operation == E400G_XCVR_SPEED_MAP_25E4X6_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x6_txrx_line_encoding_type == E400G_XCVR_SPEED_MAP_25E4X6_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x6_xcvr_mode == E400G_XCVR_SPEED_MAP_25E4X6_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x7_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x7_duplex_mode == E400G_XCVR_SPEED_MAP_25E4X7_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x7_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x7_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x7_rx_master_bond_chnl == E400G_XCVR_SPEED_MAP_25E4X7_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x7_rx_protocol == E400G_XCVR_SPEED_MAP_25E4X7_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x7_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x7_rx_xcvr_width == E400G_XCVR_SPEED_MAP_25E4X7_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x7_speed_bucket == E400G_XCVR_SPEED_MAP_25E4X7_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x7_sys_clk_src == E400G_XCVR_SPEED_MAP_25E4X7_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x7_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x7_tx_master_bond_chnl == E400G_XCVR_SPEED_MAP_25E4X7_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x7_tx_protocol == E400G_XCVR_SPEED_MAP_25E4X7_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x7_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x7_tx_xcvr_width == E400G_XCVR_SPEED_MAP_25E4X7_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x7_txrx_channel_operation == E400G_XCVR_SPEED_MAP_25E4X7_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x7_txrx_line_encoding_type == E400G_XCVR_SPEED_MAP_25E4X7_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x7_xcvr_mode == E400G_XCVR_SPEED_MAP_25E4X7_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x8_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x8_duplex_mode == E400G_XCVR_SPEED_MAP_25E4X8_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x8_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x8_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x8_rx_master_bond_chnl == E400G_XCVR_SPEED_MAP_25E4X8_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x8_rx_protocol == E400G_XCVR_SPEED_MAP_25E4X8_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x8_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x8_rx_xcvr_width == E400G_XCVR_SPEED_MAP_25E4X8_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x8_speed_bucket == E400G_XCVR_SPEED_MAP_25E4X8_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x8_sys_clk_src == E400G_XCVR_SPEED_MAP_25E4X8_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x8_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x8_tx_master_bond_chnl == E400G_XCVR_SPEED_MAP_25E4X8_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x8_tx_protocol == E400G_XCVR_SPEED_MAP_25E4X8_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x8_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x8_tx_xcvr_width == E400G_XCVR_SPEED_MAP_25E4X8_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x8_txrx_channel_operation == E400G_XCVR_SPEED_MAP_25E4X8_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x8_txrx_line_encoding_type == E400G_XCVR_SPEED_MAP_25E4X8_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x8_xcvr_mode == E400G_XCVR_SPEED_MAP_25E4X8_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x9_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x9_duplex_mode == E400G_XCVR_SPEED_MAP_25E4X9_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x9_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x9_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x9_rx_master_bond_chnl == E400G_XCVR_SPEED_MAP_25E4X9_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x9_rx_protocol == E400G_XCVR_SPEED_MAP_25E4X9_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x9_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x9_rx_xcvr_width == E400G_XCVR_SPEED_MAP_25E4X9_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x9_speed_bucket == E400G_XCVR_SPEED_MAP_25E4X9_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x9_sys_clk_src == E400G_XCVR_SPEED_MAP_25E4X9_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x9_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x9_tx_master_bond_chnl == E400G_XCVR_SPEED_MAP_25E4X9_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x9_tx_protocol == E400G_XCVR_SPEED_MAP_25E4X9_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x9_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x9_tx_xcvr_width == E400G_XCVR_SPEED_MAP_25E4X9_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x9_txrx_channel_operation == E400G_XCVR_SPEED_MAP_25E4X9_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x9_txrx_line_encoding_type == E400G_XCVR_SPEED_MAP_25E4X9_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_25e4x9_xcvr_mode == E400G_XCVR_SPEED_MAP_25E4X9_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x0_duplex_mode == E400G_XCVR_SPEED_MAP_56E4X0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x0_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x0_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x0_rx_master_bond_chnl == E400G_XCVR_SPEED_MAP_56E4X0_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x0_rx_protocol == E400G_XCVR_SPEED_MAP_56E4X0_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x0_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x0_rx_xcvr_width == E400G_XCVR_SPEED_MAP_56E4X0_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x0_speed_bucket == E400G_XCVR_SPEED_MAP_56E4X0_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x0_sys_clk_src == E400G_XCVR_SPEED_MAP_56E4X0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x0_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x0_tx_master_bond_chnl == E400G_XCVR_SPEED_MAP_56E4X0_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x0_tx_protocol == E400G_XCVR_SPEED_MAP_56E4X0_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x0_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x0_tx_xcvr_width == E400G_XCVR_SPEED_MAP_56E4X0_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x0_txrx_channel_operation == E400G_XCVR_SPEED_MAP_56E4X0_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x0_txrx_line_encoding_type == E400G_XCVR_SPEED_MAP_56E4X0_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x0_xcvr_mode == E400G_XCVR_SPEED_MAP_56E4X0_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x1_duplex_mode == E400G_XCVR_SPEED_MAP_56E4X1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x1_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x1_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x1_rx_master_bond_chnl == E400G_XCVR_SPEED_MAP_56E4X1_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x1_rx_protocol == E400G_XCVR_SPEED_MAP_56E4X1_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x1_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x1_rx_xcvr_width == E400G_XCVR_SPEED_MAP_56E4X1_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x1_speed_bucket == E400G_XCVR_SPEED_MAP_56E4X1_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x1_sys_clk_src == E400G_XCVR_SPEED_MAP_56E4X1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x1_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x1_tx_master_bond_chnl == E400G_XCVR_SPEED_MAP_56E4X1_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x1_tx_protocol == E400G_XCVR_SPEED_MAP_56E4X1_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x1_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x1_tx_xcvr_width == E400G_XCVR_SPEED_MAP_56E4X1_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x1_txrx_channel_operation == E400G_XCVR_SPEED_MAP_56E4X1_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x1_txrx_line_encoding_type == E400G_XCVR_SPEED_MAP_56E4X1_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x1_xcvr_mode == E400G_XCVR_SPEED_MAP_56E4X1_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x2_duplex_mode == E400G_XCVR_SPEED_MAP_56E4X2_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x2_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x2_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x2_rx_master_bond_chnl == E400G_XCVR_SPEED_MAP_56E4X2_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x2_rx_protocol == E400G_XCVR_SPEED_MAP_56E4X2_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x2_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x2_rx_xcvr_width == E400G_XCVR_SPEED_MAP_56E4X2_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x2_speed_bucket == E400G_XCVR_SPEED_MAP_56E4X2_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x2_sys_clk_src == E400G_XCVR_SPEED_MAP_56E4X2_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x2_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x2_tx_master_bond_chnl == E400G_XCVR_SPEED_MAP_56E4X2_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x2_tx_protocol == E400G_XCVR_SPEED_MAP_56E4X2_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x2_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x2_tx_xcvr_width == E400G_XCVR_SPEED_MAP_56E4X2_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x2_txrx_channel_operation == E400G_XCVR_SPEED_MAP_56E4X2_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x2_txrx_line_encoding_type == E400G_XCVR_SPEED_MAP_56E4X2_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x2_xcvr_mode == E400G_XCVR_SPEED_MAP_56E4X2_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x3_duplex_mode == E400G_XCVR_SPEED_MAP_56E4X3_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x3_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x3_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x3_rx_master_bond_chnl == E400G_XCVR_SPEED_MAP_56E4X3_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x3_rx_protocol == E400G_XCVR_SPEED_MAP_56E4X3_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x3_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x3_rx_xcvr_width == E400G_XCVR_SPEED_MAP_56E4X3_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x3_speed_bucket == E400G_XCVR_SPEED_MAP_56E4X3_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x3_sys_clk_src == E400G_XCVR_SPEED_MAP_56E4X3_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x3_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x3_tx_master_bond_chnl == E400G_XCVR_SPEED_MAP_56E4X3_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x3_tx_protocol == E400G_XCVR_SPEED_MAP_56E4X3_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x3_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x3_tx_xcvr_width == E400G_XCVR_SPEED_MAP_56E4X3_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x3_txrx_channel_operation == E400G_XCVR_SPEED_MAP_56E4X3_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x3_txrx_line_encoding_type == E400G_XCVR_SPEED_MAP_56E4X3_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x3_xcvr_mode == E400G_XCVR_SPEED_MAP_56E4X3_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x4_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x4_duplex_mode == E400G_XCVR_SPEED_MAP_56E4X4_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x4_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x4_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x4_rx_master_bond_chnl == E400G_XCVR_SPEED_MAP_56E4X4_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x4_rx_protocol == E400G_XCVR_SPEED_MAP_56E4X4_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x4_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x4_rx_xcvr_width == E400G_XCVR_SPEED_MAP_56E4X4_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x4_speed_bucket == E400G_XCVR_SPEED_MAP_56E4X4_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x4_sys_clk_src == E400G_XCVR_SPEED_MAP_56E4X4_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x4_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x4_tx_master_bond_chnl == E400G_XCVR_SPEED_MAP_56E4X4_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x4_tx_protocol == E400G_XCVR_SPEED_MAP_56E4X4_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x4_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x4_tx_xcvr_width == E400G_XCVR_SPEED_MAP_56E4X4_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x4_txrx_channel_operation == E400G_XCVR_SPEED_MAP_56E4X4_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x4_txrx_line_encoding_type == E400G_XCVR_SPEED_MAP_56E4X4_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x4_xcvr_mode == E400G_XCVR_SPEED_MAP_56E4X4_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x5_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x5_duplex_mode == E400G_XCVR_SPEED_MAP_56E4X5_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x5_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x5_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x5_rx_master_bond_chnl == E400G_XCVR_SPEED_MAP_56E4X5_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x5_rx_protocol == E400G_XCVR_SPEED_MAP_56E4X5_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x5_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x5_rx_xcvr_width == E400G_XCVR_SPEED_MAP_56E4X5_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x5_speed_bucket == E400G_XCVR_SPEED_MAP_56E4X5_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x5_sys_clk_src == E400G_XCVR_SPEED_MAP_56E4X5_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x5_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x5_tx_master_bond_chnl == E400G_XCVR_SPEED_MAP_56E4X5_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x5_tx_protocol == E400G_XCVR_SPEED_MAP_56E4X5_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x5_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x5_tx_xcvr_width == E400G_XCVR_SPEED_MAP_56E4X5_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x5_txrx_channel_operation == E400G_XCVR_SPEED_MAP_56E4X5_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x5_txrx_line_encoding_type == E400G_XCVR_SPEED_MAP_56E4X5_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x5_xcvr_mode == E400G_XCVR_SPEED_MAP_56E4X5_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x6_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x6_duplex_mode == E400G_XCVR_SPEED_MAP_56E4X6_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x6_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x6_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x6_rx_master_bond_chnl == E400G_XCVR_SPEED_MAP_56E4X6_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x6_rx_protocol == E400G_XCVR_SPEED_MAP_56E4X6_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x6_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x6_rx_xcvr_width == E400G_XCVR_SPEED_MAP_56E4X6_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x6_speed_bucket == E400G_XCVR_SPEED_MAP_56E4X6_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x6_sys_clk_src == E400G_XCVR_SPEED_MAP_56E4X6_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x6_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x6_tx_master_bond_chnl == E400G_XCVR_SPEED_MAP_56E4X6_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x6_tx_protocol == E400G_XCVR_SPEED_MAP_56E4X6_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x6_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x6_tx_xcvr_width == E400G_XCVR_SPEED_MAP_56E4X6_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x6_txrx_channel_operation == E400G_XCVR_SPEED_MAP_56E4X6_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x6_txrx_line_encoding_type == E400G_XCVR_SPEED_MAP_56E4X6_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x6_xcvr_mode == E400G_XCVR_SPEED_MAP_56E4X6_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x7_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x7_duplex_mode == E400G_XCVR_SPEED_MAP_56E4X7_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x7_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x7_rx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x7_rx_master_bond_chnl == E400G_XCVR_SPEED_MAP_56E4X7_RX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x7_rx_protocol == E400G_XCVR_SPEED_MAP_56E4X7_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x7_rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x7_rx_xcvr_width == E400G_XCVR_SPEED_MAP_56E4X7_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x7_speed_bucket == E400G_XCVR_SPEED_MAP_56E4X7_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x7_sys_clk_src == E400G_XCVR_SPEED_MAP_56E4X7_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x7_tx_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x7_tx_master_bond_chnl == E400G_XCVR_SPEED_MAP_56E4X7_TX_MASTER_BOND_CHNL_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x7_tx_protocol == E400G_XCVR_SPEED_MAP_56E4X7_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x7_tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x7_tx_xcvr_width == E400G_XCVR_SPEED_MAP_56E4X7_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x7_txrx_channel_operation == E400G_XCVR_SPEED_MAP_56E4X7_TXRX_CHANNEL_OPERATION_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x7_txrx_line_encoding_type == E400G_XCVR_SPEED_MAP_56E4X7_TXRX_LINE_ENCODING_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.e400g_xcvr_speed_map_56e4x7_xcvr_mode == E400G_XCVR_SPEED_MAP_56E4X7_XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.map_bk0 == MAP_BK0_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.map_bk1 == MAP_BK1_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.map_bk2 == MAP_BK2_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.map_bk3 == MAP_BK3_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.map_ux0 == MAP_UX0_ENABLE_25E4X15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.map_ux1 == MAP_UX1_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.map_ux10 == MAP_UX10_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.map_ux11 == MAP_UX11_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.map_ux12 == MAP_UX12_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.map_ux13 == MAP_UX13_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.map_ux14 == MAP_UX14_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.map_ux15 == MAP_UX15_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.map_ux2 == MAP_UX2_ENABLE_25E4X13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.map_ux3 == MAP_UX3_ENABLE_25E4X12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.map_ux4 == MAP_UX4_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.map_ux5 == MAP_UX5_ENABLE_25E4X10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.map_ux6 == MAP_UX6_ENABLE_25E4X9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.map_ux7 == MAP_UX7_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.map_ux8 == MAP_UX8_ENABLE_25E4X7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.map_ux9 == MAP_UX9_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ptp0_clk_adapt_rc_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ptp1_clk_adapt_rc_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.rx_transfer_clk0_adapt_rc_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.rx_transfer_clk10_adapt_rc_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.rx_transfer_clk11_adapt_rc_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.rx_transfer_clk12_adapt_rc_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.rx_transfer_clk13_adapt_rc_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.rx_transfer_clk14_adapt_rc_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.rx_transfer_clk15_adapt_rc_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.rx_transfer_clk1_adapt_rc_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.rx_transfer_clk2_adapt_rc_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.rx_transfer_clk3_adapt_rc_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.rx_transfer_clk4_adapt_rc_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.rx_transfer_clk5_adapt_rc_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.rx_transfer_clk6_adapt_rc_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.rx_transfer_clk7_adapt_rc_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.rx_transfer_clk8_adapt_rc_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.rx_transfer_clk9_adapt_rc_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.sup_mode == INDIVIDUAL_31_CONTROL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.sys_pll0_div1_adapt_rc_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.sys_pll0_div2_adapt_rc_clk_hz == 37'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.sys_pll1_div1_adapt_rc_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.sys_pll1_div2_adapt_rc_clk_hz == 37'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.sys_pll2_div1_adapt_rc_clk_hz == 37'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.sys_pll2_div2_adapt_rc_clk_hz == 37'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.topo_supports_barak == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.topo_supports_pcie == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.topo_supports_ptp == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.topology == UX16E400GPTP_XX_DISABLED_XX_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.transfer_clk0_adapt_rc_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.transfer_clk10_adapt_rc_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.transfer_clk11_adapt_rc_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.transfer_clk12_adapt_rc_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.transfer_clk13_adapt_rc_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.transfer_clk14_adapt_rc_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.transfer_clk15_adapt_rc_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.transfer_clk1_adapt_rc_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.transfer_clk2_adapt_rc_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.transfer_clk3_adapt_rc_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.transfer_clk4_adapt_rc_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.transfer_clk5_adapt_rc_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.transfer_clk6_adapt_rc_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.transfer_clk7_adapt_rc_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.transfer_clk8_adapt_rc_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.transfer_clk9_adapt_rc_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux0_return_xcvr_rc_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux0_rx_user_xcvr_rc_clk_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux0_rxword_xcvr_rc_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux0_tx_line_rate == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux0_tx_user_xcvr_rc_clk1_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux0_tx_user_xcvr_rc_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux0_txword_xcvr_rc_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux10_return_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux10_rx_user_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux10_rxword_xcvr_rc_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux10_tx_user_xcvr_rc_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux10_tx_user_xcvr_rc_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux10_txword_xcvr_rc_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux11_return_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux11_rx_user_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux11_rxword_xcvr_rc_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux11_tx_user_xcvr_rc_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux11_tx_user_xcvr_rc_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux11_txword_xcvr_rc_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux12_return_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux12_rx_user_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux12_rxword_xcvr_rc_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux12_tx_user_xcvr_rc_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux12_tx_user_xcvr_rc_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux12_txword_xcvr_rc_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux13_return_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux13_rx_user_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux13_rxword_xcvr_rc_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux13_tx_user_xcvr_rc_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux13_tx_user_xcvr_rc_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux13_txword_xcvr_rc_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux14_return_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux14_rx_user_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux14_rxword_xcvr_rc_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux14_tx_user_xcvr_rc_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux14_tx_user_xcvr_rc_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux14_txword_xcvr_rc_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux15_return_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux15_rx_user_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux15_rxword_xcvr_rc_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux15_tx_user_xcvr_rc_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux15_tx_user_xcvr_rc_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux15_txword_xcvr_rc_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux1_return_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux1_rx_user_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux1_rxword_xcvr_rc_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux1_tx_user_xcvr_rc_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux1_tx_user_xcvr_rc_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux1_txword_xcvr_rc_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux2_return_xcvr_rc_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux2_rx_user_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux2_rxword_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux2_tx_user_xcvr_rc_clk1_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux2_tx_user_xcvr_rc_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux2_txword_xcvr_rc_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux3_return_xcvr_rc_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux3_rx_user_xcvr_rc_clk_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux3_rxword_xcvr_rc_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux3_tx_user_xcvr_rc_clk1_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux3_tx_user_xcvr_rc_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux3_txword_xcvr_rc_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux4_return_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux4_rx_user_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux4_rxword_xcvr_rc_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux4_tx_user_xcvr_rc_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux4_tx_user_xcvr_rc_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux4_txword_xcvr_rc_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux5_return_xcvr_rc_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux5_rx_user_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux5_rxword_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux5_tx_user_xcvr_rc_clk1_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux5_tx_user_xcvr_rc_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux5_txword_xcvr_rc_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux6_return_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux6_rx_user_xcvr_rc_clk_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux6_rxword_xcvr_rc_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux6_tx_user_xcvr_rc_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux6_tx_user_xcvr_rc_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux6_txword_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux7_return_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux7_rx_user_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux7_rxword_xcvr_rc_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux7_tx_user_xcvr_rc_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux7_tx_user_xcvr_rc_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux7_txword_xcvr_rc_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux8_return_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux8_rx_user_xcvr_rc_clk_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux8_rxword_xcvr_rc_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux8_tx_user_xcvr_rc_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux8_tx_user_xcvr_rc_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux8_txword_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux9_return_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux9_rx_user_xcvr_rc_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux9_rxword_xcvr_rc_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux9_tx_user_xcvr_rc_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux9_tx_user_xcvr_rc_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.ux9_txword_xcvr_rc_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.xcvr_select_112e4x0 == XCVR_SELECT_112E4X0_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.xcvr_select_112e4x1 == XCVR_SELECT_112E4X1_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.xcvr_select_112e4x2 == XCVR_SELECT_112E4X2_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.xcvr_select_112e4x3 == XCVR_SELECT_112E4X3_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.xcvr_select_25e4x0 == XCVR_SELECT_25E4X0_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.xcvr_select_25e4x1 == XCVR_SELECT_25E4X1_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.xcvr_select_25e4x10 == XCVR_SELECT_25E4X10_E4UX5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.xcvr_select_25e4x11 == XCVR_SELECT_25E4X11_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.xcvr_select_25e4x12 == XCVR_SELECT_25E4X12_E4UX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.xcvr_select_25e4x13 == XCVR_SELECT_25E4X13_E4UX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.xcvr_select_25e4x14 == XCVR_SELECT_25E4X14_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.xcvr_select_25e4x15 == XCVR_SELECT_25E4X15_E4UX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.xcvr_select_25e4x2 == XCVR_SELECT_25E4X2_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.xcvr_select_25e4x3 == XCVR_SELECT_25E4X3_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.xcvr_select_25e4x4 == XCVR_SELECT_25E4X4_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.xcvr_select_25e4x5 == XCVR_SELECT_25E4X5_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.xcvr_select_25e4x6 == XCVR_SELECT_25E4X6_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.xcvr_select_25e4x7 == XCVR_SELECT_25E4X7_E4UX8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.xcvr_select_25e4x8 == XCVR_SELECT_25E4X8_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.xcvr_select_25e4x9 == XCVR_SELECT_25E4X9_E4UX6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.xcvr_select_56e4x0 == XCVR_SELECT_56E4X0_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.xcvr_select_56e4x1 == XCVR_SELECT_56E4X1_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.xcvr_select_56e4x2 == XCVR_SELECT_56E4X2_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.xcvr_select_56e4x3 == XCVR_SELECT_56E4X3_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.xcvr_select_56e4x4 == XCVR_SELECT_56E4X4_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.xcvr_select_56e4x5 == XCVR_SELECT_56E4X5_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.xcvr_select_56e4x6 == XCVR_SELECT_56E4X6_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.xcvr_select_56e4x7 == XCVR_SELECT_56E4X7_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib1_ptp_st0_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib1_tx_st0_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib1_tx_st10_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib1_tx_st11_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib1_tx_st12_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib1_tx_st13_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib1_tx_st14_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib1_tx_st15_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib1_tx_st1_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib1_tx_st2_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib1_tx_st3_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib1_tx_st4_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib1_tx_st5_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib1_tx_st6_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib1_tx_st7_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib1_tx_st8_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib1_tx_st9_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib2_ptp_st0_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib2_rx_st0_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib2_rx_st10_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib2_rx_st11_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib2_rx_st12_clk_hz == 37'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib2_rx_st13_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib2_rx_st14_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib2_rx_st15_clk_hz == 37'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib2_rx_st1_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib2_rx_st2_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib2_rx_st3_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib2_rx_st4_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib2_rx_st5_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib2_rx_st6_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib2_rx_st7_clk_hz == 37'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib2_rx_st8_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib2_rx_st9_clk_hz == 37'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib2_tx_st0_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib2_tx_st10_clk_hz == 37'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib2_tx_st11_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib2_tx_st12_clk_hz == 37'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib2_tx_st13_clk_hz == 37'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib2_tx_st14_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib2_tx_st15_clk_hz == 37'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib2_tx_st1_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib2_tx_st2_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib2_tx_st3_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib2_tx_st4_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib2_tx_st5_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib2_tx_st6_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib2_tx_st7_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib2_tx_st8_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib2_tx_st9_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib3_rx_st0_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib3_rx_st10_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib3_rx_st11_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib3_rx_st12_clk_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib3_rx_st13_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib3_rx_st14_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib3_rx_st15_clk_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib3_rx_st1_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib3_rx_st2_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib3_rx_st3_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib3_rx_st4_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib3_rx_st5_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib3_rx_st6_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib3_rx_st7_clk_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib3_rx_st8_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib3_rx_st9_clk_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib3_tx_st0_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib3_tx_st10_clk_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib3_tx_st11_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib3_tx_st12_clk_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib3_tx_st13_clk_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib3_tx_st14_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib3_tx_st15_clk_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib3_tx_st1_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib3_tx_st2_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib3_tx_st3_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib3_tx_st4_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib3_tx_st5_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib3_tx_st6_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib3_tx_st7_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib3_tx_st8_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib3_tx_st9_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.aib_esys_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bk0_return_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bk0_rx_user_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bk0_rx_user_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bk0_rxword_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bk0_tx_user_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bk0_tx_user_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bk0_txword_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bk1_return_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bk1_rx_user_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bk1_rx_user_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bk1_rxword_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bk1_tx_user_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bk1_tx_user_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bk1_txword_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bk2_return_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bk2_rx_user_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bk2_rx_user_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bk2_rxword_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bk2_tx_user_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bk2_tx_user_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bk2_txword_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bk3_return_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bk3_rx_user_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bk3_rx_user_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bk3_rxword_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bk3_tx_user_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bk3_tx_user_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bk3_txword_clk_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.block_enable == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bond_rx0_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bond_rx10_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bond_rx11_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bond_rx12_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bond_rx13_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bond_rx14_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bond_rx15_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bond_rx1_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bond_rx2_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bond_rx3_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bond_rx4_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bond_rx5_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bond_rx6_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bond_rx7_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bond_rx8_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bond_rx9_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bond_tx0_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bond_tx10_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bond_tx11_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bond_tx12_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bond_tx13_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bond_tx14_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bond_tx15_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bond_tx1_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bond_tx2_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bond_tx3_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bond_tx4_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bond_tx5_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bond_tx6_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bond_tx7_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bond_tx8_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.bond_tx9_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_aib2_rx_st_clk_en == E400G_100G_0_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_aib2_tx_st_clk_en == E400G_100G_0_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_aib3_rx_st_clk_en == E400G_100G_0_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_aib3_tx_st_clk_en == E400G_100G_0_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_duplex_mode == E400G_100G_0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_fec_clk_src == E400G_100G_0_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_fec_error == E400G_100G_0_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_fec_mode == E400G_100G_0_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_fec_spec == E400G_100G_0_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_lpbk_mode == E400G_100G_0_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_mac_mode == E400G_100G_0_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_ptp_mode == E400G_100G_0_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_rx_excvr_gb_ratio_mode == E400G_100G_0_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_rx_excvr_if_fifo_mode == E400G_100G_0_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_rx_fec_enable == E400G_100G_0_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_rx_pcs_mode == E400G_100G_0_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_rx_primary_use == E400G_100G_0_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_rx_stream_bonding == E400G_100G_0_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_rx_xcvr_bonded == E400G_100G_0_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_rx_xcvr_width == E400G_100G_0_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_speed_map == E400G_100G_0_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_sup_mode == E400G_100G_0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_sys_clk_src == E400G_100G_0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_tx_excvr_gb_ratio_mode == E400G_100G_0_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_tx_excvr_if_fifo_mode == E400G_100G_0_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_tx_fec_enable == E400G_100G_0_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_tx_pcs_mode == E400G_100G_0_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_tx_primary_use == E400G_100G_0_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_tx_stream_bonding == E400G_100G_0_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_tx_xcvr_bonded == E400G_100G_0_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_tx_xcvr_width == E400G_100G_0_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_xcvr_type == E400G_100G_0_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_0_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_aib2_rx_st_clk_en == E400G_100G_1_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_aib2_tx_st_clk_en == E400G_100G_1_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_aib3_rx_st_clk_en == E400G_100G_1_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_aib3_tx_st_clk_en == E400G_100G_1_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_duplex_mode == E400G_100G_1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_fec_clk_src == E400G_100G_1_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_fec_error == E400G_100G_1_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_fec_mode == E400G_100G_1_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_fec_spec == E400G_100G_1_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_lpbk_mode == E400G_100G_1_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_mac_mode == E400G_100G_1_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_ptp_mode == E400G_100G_1_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_rx_excvr_gb_ratio_mode == E400G_100G_1_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_rx_excvr_if_fifo_mode == E400G_100G_1_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_rx_fec_enable == E400G_100G_1_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_rx_pcs_mode == E400G_100G_1_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_rx_primary_use == E400G_100G_1_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_rx_stream_bonding == E400G_100G_1_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_rx_xcvr_bonded == E400G_100G_1_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_rx_xcvr_width == E400G_100G_1_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_speed_map == E400G_100G_1_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_sup_mode == E400G_100G_1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_sys_clk_src == E400G_100G_1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_tx_excvr_gb_ratio_mode == E400G_100G_1_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_tx_excvr_if_fifo_mode == E400G_100G_1_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_tx_fec_enable == E400G_100G_1_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_tx_pcs_mode == E400G_100G_1_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_tx_primary_use == E400G_100G_1_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_tx_stream_bonding == E400G_100G_1_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_tx_xcvr_bonded == E400G_100G_1_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_tx_xcvr_width == E400G_100G_1_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_xcvr_type == E400G_100G_1_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_1_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_aib2_rx_st_clk_en == E400G_100G_2_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_aib2_tx_st_clk_en == E400G_100G_2_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_aib3_rx_st_clk_en == E400G_100G_2_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_aib3_tx_st_clk_en == E400G_100G_2_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_duplex_mode == E400G_100G_2_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_fec_clk_src == E400G_100G_2_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_fec_error == E400G_100G_2_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_fec_mode == E400G_100G_2_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_fec_spec == E400G_100G_2_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_lpbk_mode == E400G_100G_2_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_mac_mode == E400G_100G_2_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_ptp_mode == E400G_100G_2_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_rx_excvr_gb_ratio_mode == E400G_100G_2_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_rx_excvr_if_fifo_mode == E400G_100G_2_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_rx_fec_enable == E400G_100G_2_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_rx_pcs_mode == E400G_100G_2_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_rx_primary_use == E400G_100G_2_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_rx_stream_bonding == E400G_100G_2_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_rx_xcvr_bonded == E400G_100G_2_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_rx_xcvr_width == E400G_100G_2_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_speed_map == E400G_100G_2_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_sup_mode == E400G_100G_2_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_sys_clk_src == E400G_100G_2_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_tx_excvr_gb_ratio_mode == E400G_100G_2_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_tx_excvr_if_fifo_mode == E400G_100G_2_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_tx_fec_enable == E400G_100G_2_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_tx_pcs_mode == E400G_100G_2_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_tx_primary_use == E400G_100G_2_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_tx_stream_bonding == E400G_100G_2_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_tx_xcvr_bonded == E400G_100G_2_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_tx_xcvr_width == E400G_100G_2_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_xcvr_type == E400G_100G_2_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_2_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_aib2_rx_st_clk_en == E400G_100G_3_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_aib2_tx_st_clk_en == E400G_100G_3_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_aib3_rx_st_clk_en == E400G_100G_3_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_aib3_tx_st_clk_en == E400G_100G_3_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_duplex_mode == E400G_100G_3_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_fec_clk_src == E400G_100G_3_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_fec_error == E400G_100G_3_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_fec_mode == E400G_100G_3_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_fec_spec == E400G_100G_3_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_lpbk_mode == E400G_100G_3_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_mac_mode == E400G_100G_3_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_ptp_mode == E400G_100G_3_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_rx_excvr_gb_ratio_mode == E400G_100G_3_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_rx_excvr_if_fifo_mode == E400G_100G_3_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_rx_fec_enable == E400G_100G_3_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_rx_pcs_mode == E400G_100G_3_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_rx_primary_use == E400G_100G_3_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_rx_stream_bonding == E400G_100G_3_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_rx_xcvr_bonded == E400G_100G_3_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_rx_xcvr_width == E400G_100G_3_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_speed_map == E400G_100G_3_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_sup_mode == E400G_100G_3_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_sys_clk_src == E400G_100G_3_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_tx_excvr_gb_ratio_mode == E400G_100G_3_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_tx_excvr_if_fifo_mode == E400G_100G_3_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_tx_fec_enable == E400G_100G_3_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_tx_pcs_mode == E400G_100G_3_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_tx_primary_use == E400G_100G_3_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_tx_stream_bonding == E400G_100G_3_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_tx_xcvr_bonded == E400G_100G_3_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_tx_xcvr_width == E400G_100G_3_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_xcvr_type == E400G_100G_3_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_100g_3_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_aib2_rx_st_clk_en == E400G_150G_0_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_aib2_tx_st_clk_en == E400G_150G_0_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_aib3_rx_st_clk_en == E400G_150G_0_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_aib3_tx_st_clk_en == E400G_150G_0_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_duplex_mode == E400G_150G_0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_fec_mode == E400G_150G_0_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_fec_spec == E400G_150G_0_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_lpbk_mode == E400G_150G_0_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_mac_mode == E400G_150G_0_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_ptp_mode == E400G_150G_0_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_rx_excvr_gb_ratio_mode == E400G_150G_0_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_rx_excvr_if_fifo_mode == E400G_150G_0_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_rx_fec_enable == E400G_150G_0_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_rx_pcs_mode == E400G_150G_0_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_rx_primary_use == E400G_150G_0_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_rx_stream_bonding == E400G_150G_0_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_rx_xcvr_bonded == E400G_150G_0_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_rx_xcvr_width == E400G_150G_0_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_speed_map == E400G_150G_0_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_sup_mode == E400G_150G_0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_sys_clk_src == E400G_150G_0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_tx_excvr_gb_ratio_mode == E400G_150G_0_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_tx_excvr_if_fifo_mode == E400G_150G_0_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_tx_fec_enable == E400G_150G_0_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_tx_pcs_mode == E400G_150G_0_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_tx_primary_use == E400G_150G_0_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_tx_stream_bonding == E400G_150G_0_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_tx_xcvr_bonded == E400G_150G_0_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_tx_xcvr_width == E400G_150G_0_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_xcvr_type == E400G_150G_0_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_0_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_aib2_rx_st_clk_en == E400G_150G_1_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_aib2_tx_st_clk_en == E400G_150G_1_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_aib3_rx_st_clk_en == E400G_150G_1_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_aib3_tx_st_clk_en == E400G_150G_1_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_duplex_mode == E400G_150G_1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_fec_mode == E400G_150G_1_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_fec_spec == E400G_150G_1_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_lpbk_mode == E400G_150G_1_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_mac_mode == E400G_150G_1_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_ptp_mode == E400G_150G_1_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_rx_excvr_gb_ratio_mode == E400G_150G_1_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_rx_excvr_if_fifo_mode == E400G_150G_1_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_rx_fec_enable == E400G_150G_1_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_rx_pcs_mode == E400G_150G_1_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_rx_primary_use == E400G_150G_1_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_rx_stream_bonding == E400G_150G_1_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_rx_xcvr_bonded == E400G_150G_1_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_rx_xcvr_width == E400G_150G_1_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_speed_map == E400G_150G_1_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_sup_mode == E400G_150G_1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_sys_clk_src == E400G_150G_1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_tx_excvr_gb_ratio_mode == E400G_150G_1_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_tx_excvr_if_fifo_mode == E400G_150G_1_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_tx_fec_enable == E400G_150G_1_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_tx_pcs_mode == E400G_150G_1_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_tx_primary_use == E400G_150G_1_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_tx_stream_bonding == E400G_150G_1_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_tx_xcvr_bonded == E400G_150G_1_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_tx_xcvr_width == E400G_150G_1_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_xcvr_type == E400G_150G_1_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_1_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_aib2_rx_st_clk_en == E400G_150G_2_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_aib2_tx_st_clk_en == E400G_150G_2_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_aib3_rx_st_clk_en == E400G_150G_2_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_aib3_tx_st_clk_en == E400G_150G_2_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_duplex_mode == E400G_150G_2_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_fec_mode == E400G_150G_2_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_fec_spec == E400G_150G_2_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_lpbk_mode == E400G_150G_2_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_mac_mode == E400G_150G_2_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_ptp_mode == E400G_150G_2_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_rx_excvr_gb_ratio_mode == E400G_150G_2_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_rx_excvr_if_fifo_mode == E400G_150G_2_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_rx_fec_enable == E400G_150G_2_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_rx_pcs_mode == E400G_150G_2_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_rx_primary_use == E400G_150G_2_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_rx_stream_bonding == E400G_150G_2_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_rx_xcvr_bonded == E400G_150G_2_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_rx_xcvr_width == E400G_150G_2_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_speed_map == E400G_150G_2_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_sup_mode == E400G_150G_2_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_sys_clk_src == E400G_150G_2_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_tx_excvr_gb_ratio_mode == E400G_150G_2_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_tx_excvr_if_fifo_mode == E400G_150G_2_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_tx_fec_enable == E400G_150G_2_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_tx_pcs_mode == E400G_150G_2_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_tx_primary_use == E400G_150G_2_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_tx_stream_bonding == E400G_150G_2_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_tx_xcvr_bonded == E400G_150G_2_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_tx_xcvr_width == E400G_150G_2_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_xcvr_type == E400G_150G_2_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_2_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_aib2_rx_st_clk_en == E400G_150G_3_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_aib2_tx_st_clk_en == E400G_150G_3_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_aib3_rx_st_clk_en == E400G_150G_3_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_aib3_tx_st_clk_en == E400G_150G_3_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_duplex_mode == E400G_150G_3_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_fec_mode == E400G_150G_3_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_fec_spec == E400G_150G_3_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_lpbk_mode == E400G_150G_3_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_mac_mode == E400G_150G_3_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_ptp_mode == E400G_150G_3_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_rx_excvr_gb_ratio_mode == E400G_150G_3_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_rx_excvr_if_fifo_mode == E400G_150G_3_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_rx_fec_enable == E400G_150G_3_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_rx_pcs_mode == E400G_150G_3_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_rx_primary_use == E400G_150G_3_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_rx_stream_bonding == E400G_150G_3_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_rx_xcvr_bonded == E400G_150G_3_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_rx_xcvr_width == E400G_150G_3_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_speed_map == E400G_150G_3_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_sup_mode == E400G_150G_3_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_sys_clk_src == E400G_150G_3_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_tx_excvr_gb_ratio_mode == E400G_150G_3_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_tx_excvr_if_fifo_mode == E400G_150G_3_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_tx_fec_enable == E400G_150G_3_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_tx_pcs_mode == E400G_150G_3_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_tx_primary_use == E400G_150G_3_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_tx_stream_bonding == E400G_150G_3_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_tx_xcvr_bonded == E400G_150G_3_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_tx_xcvr_width == E400G_150G_3_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_xcvr_type == E400G_150G_3_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_150g_3_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_aib2_rx_st_clk_en == E400G_200G_0_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_aib2_tx_st_clk_en == E400G_200G_0_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_aib3_rx_st_clk_en == E400G_200G_0_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_aib3_tx_st_clk_en == E400G_200G_0_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_duplex_mode == E400G_200G_0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_fec_clk_src == E400G_200G_0_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_fec_error == E400G_200G_0_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_fec_mode == E400G_200G_0_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_fec_spec == E400G_200G_0_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_lpbk_mode == E400G_200G_0_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_mac_mode == E400G_200G_0_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_ptp_mode == E400G_200G_0_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_rx_excvr_gb_ratio_mode == E400G_200G_0_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_rx_excvr_if_fifo_mode == E400G_200G_0_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_rx_fec_enable == E400G_200G_0_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_rx_pcs_mode == E400G_200G_0_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_rx_primary_use == E400G_200G_0_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_rx_stream_bonding == E400G_200G_0_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_rx_xcvr_bonded == E400G_200G_0_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_rx_xcvr_width == E400G_200G_0_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_speed_map == E400G_200G_0_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_sup_mode == E400G_200G_0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_sys_clk_src == E400G_200G_0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_tx_excvr_gb_ratio_mode == E400G_200G_0_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_tx_excvr_if_fifo_mode == E400G_200G_0_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_tx_fec_enable == E400G_200G_0_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_tx_pcs_mode == E400G_200G_0_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_tx_primary_use == E400G_200G_0_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_tx_stream_bonding == E400G_200G_0_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_tx_xcvr_bonded == E400G_200G_0_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_tx_xcvr_width == E400G_200G_0_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_xcvr_type == E400G_200G_0_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_0_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_aib2_rx_st_clk_en == E400G_200G_1_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_aib2_tx_st_clk_en == E400G_200G_1_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_aib3_rx_st_clk_en == E400G_200G_1_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_aib3_tx_st_clk_en == E400G_200G_1_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_duplex_mode == E400G_200G_1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_fec_clk_src == E400G_200G_1_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_fec_error == E400G_200G_1_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_fec_mode == E400G_200G_1_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_fec_spec == E400G_200G_1_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_lpbk_mode == E400G_200G_1_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_mac_mode == E400G_200G_1_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_ptp_mode == E400G_200G_1_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_rx_excvr_gb_ratio_mode == E400G_200G_1_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_rx_excvr_if_fifo_mode == E400G_200G_1_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_rx_fec_enable == E400G_200G_1_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_rx_pcs_mode == E400G_200G_1_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_rx_primary_use == E400G_200G_1_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_rx_stream_bonding == E400G_200G_1_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_rx_xcvr_bonded == E400G_200G_1_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_rx_xcvr_width == E400G_200G_1_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_speed_map == E400G_200G_1_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_sup_mode == E400G_200G_1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_sys_clk_src == E400G_200G_1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_tx_excvr_gb_ratio_mode == E400G_200G_1_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_tx_excvr_if_fifo_mode == E400G_200G_1_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_tx_fec_enable == E400G_200G_1_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_tx_pcs_mode == E400G_200G_1_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_tx_primary_use == E400G_200G_1_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_tx_stream_bonding == E400G_200G_1_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_tx_xcvr_bonded == E400G_200G_1_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_tx_xcvr_width == E400G_200G_1_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_xcvr_type == E400G_200G_1_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_200g_1_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_aib2_rx_st_clk_en == E400G_25G_0_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_aib2_tx_st_clk_en == E400G_25G_0_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_aib3_rx_st_clk_en == E400G_25G_0_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_aib3_tx_st_clk_en == E400G_25G_0_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_duplex_mode == E400G_25G_0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_fec_clk_src == E400G_25G_0_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_fec_error == E400G_25G_0_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_fec_mode == E400G_25G_0_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_fec_spec == E400G_25G_0_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_lpbk_mode == E400G_25G_0_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_mac_mode == E400G_25G_0_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_ptp_mode == E400G_25G_0_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_rx_excvr_gb_ratio_mode == E400G_25G_0_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_rx_excvr_if_fifo_mode == E400G_25G_0_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_rx_fec_enable == E400G_25G_0_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_rx_pcs_mode == E400G_25G_0_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_rx_primary_use == E400G_25G_0_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_rx_stream_bonding == E400G_25G_0_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_rx_xcvr_bonded == E400G_25G_0_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_rx_xcvr_width == E400G_25G_0_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_speed_map == E400G_25G_0_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_sup_mode == E400G_25G_0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_sys_clk_src == E400G_25G_0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_tx_excvr_gb_ratio_mode == E400G_25G_0_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_tx_excvr_if_fifo_mode == E400G_25G_0_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_tx_fec_enable == E400G_25G_0_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_tx_pcs_mode == E400G_25G_0_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_tx_primary_use == E400G_25G_0_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_tx_stream_bonding == E400G_25G_0_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_tx_xcvr_bonded == E400G_25G_0_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_tx_xcvr_width == E400G_25G_0_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_xcvr_type == E400G_25G_0_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_0_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_aib2_rx_st_clk_en == E400G_25G_10_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_aib2_tx_st_clk_en == E400G_25G_10_AIB2_TX_ST_CLK_EN_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_aib3_rx_st_clk_en == E400G_25G_10_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_aib3_tx_st_clk_en == E400G_25G_10_AIB3_TX_ST_CLK_EN_TX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_duplex_mode == E400G_25G_10_DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_fec_clk_src == E400G_25G_10_FEC_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_fec_error == E400G_25G_10_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_fec_mode == E400G_25G_10_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_fec_spec == E400G_25G_10_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_lpbk_mode == E400G_25G_10_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_mac_mode == E400G_25G_10_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_ptp_mode == E400G_25G_10_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_rx_excvr_gb_ratio_mode == E400G_25G_10_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_rx_excvr_if_fifo_mode == E400G_25G_10_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_rx_fec_enable == E400G_25G_10_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_rx_pcs_mode == E400G_25G_10_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_rx_primary_use == E400G_25G_10_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_rx_stream_bonding == E400G_25G_10_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_rx_xcvr_bonded == E400G_25G_10_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_rx_xcvr_width == E400G_25G_10_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_speed_map == E400G_25G_10_SPEED_MAP_MAP_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_sup_mode == E400G_25G_10_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_sys_clk_src == E400G_25G_10_SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_tx_datarate == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_tx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_tx_excvr_gb_ratio_mode == E400G_25G_10_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_tx_excvr_if_fifo_mode == E400G_25G_10_TX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_tx_fec_enable == E400G_25G_10_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_tx_pcs_mode == E400G_25G_10_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_tx_primary_use == E400G_25G_10_TX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_tx_stream_bonding == E400G_25G_10_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_tx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_tx_xcvr_bonded == E400G_25G_10_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_tx_xcvr_width == E400G_25G_10_TX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_xcvr_type == E400G_25G_10_XCVR_TYPE_UX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_10_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_aib2_rx_st_clk_en == E400G_25G_11_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_aib2_tx_st_clk_en == E400G_25G_11_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_aib3_rx_st_clk_en == E400G_25G_11_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_aib3_tx_st_clk_en == E400G_25G_11_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_duplex_mode == E400G_25G_11_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_fec_clk_src == E400G_25G_11_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_fec_error == E400G_25G_11_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_fec_mode == E400G_25G_11_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_fec_spec == E400G_25G_11_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_lpbk_mode == E400G_25G_11_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_mac_mode == E400G_25G_11_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_ptp_mode == E400G_25G_11_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_rx_excvr_gb_ratio_mode == E400G_25G_11_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_rx_excvr_if_fifo_mode == E400G_25G_11_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_rx_fec_enable == E400G_25G_11_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_rx_pcs_mode == E400G_25G_11_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_rx_primary_use == E400G_25G_11_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_rx_stream_bonding == E400G_25G_11_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_rx_xcvr_bonded == E400G_25G_11_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_rx_xcvr_width == E400G_25G_11_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_speed_map == E400G_25G_11_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_sup_mode == E400G_25G_11_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_sys_clk_src == E400G_25G_11_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_tx_excvr_gb_ratio_mode == E400G_25G_11_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_tx_excvr_if_fifo_mode == E400G_25G_11_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_tx_fec_enable == E400G_25G_11_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_tx_pcs_mode == E400G_25G_11_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_tx_primary_use == E400G_25G_11_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_tx_stream_bonding == E400G_25G_11_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_tx_xcvr_bonded == E400G_25G_11_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_tx_xcvr_width == E400G_25G_11_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_xcvr_type == E400G_25G_11_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_11_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_aib2_rx_st_clk_en == E400G_25G_12_AIB2_RX_ST_CLK_EN_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_aib2_tx_st_clk_en == E400G_25G_12_AIB2_TX_ST_CLK_EN_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_aib3_rx_st_clk_en == E400G_25G_12_AIB3_RX_ST_CLK_EN_RX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_aib3_tx_st_clk_en == E400G_25G_12_AIB3_TX_ST_CLK_EN_TX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_duplex_mode == E400G_25G_12_DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_fec_clk_src == E400G_25G_12_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_fec_error == E400G_25G_12_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_fec_mode == E400G_25G_12_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_fec_spec == E400G_25G_12_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_lpbk_mode == E400G_25G_12_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_mac_mode == E400G_25G_12_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_ptp_mode == E400G_25G_12_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_rx_datarate == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_rx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_rx_excvr_gb_ratio_mode == E400G_25G_12_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_rx_excvr_if_fifo_mode == E400G_25G_12_RX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_rx_fec_enable == E400G_25G_12_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_rx_pcs_mode == E400G_25G_12_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_rx_primary_use == E400G_25G_12_RX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_rx_stream_bonding == E400G_25G_12_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_rx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_rx_xcvr_bonded == E400G_25G_12_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_rx_xcvr_width == E400G_25G_12_RX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_speed_map == E400G_25G_12_SPEED_MAP_MAP_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_sup_mode == E400G_25G_12_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_sys_clk_src == E400G_25G_12_SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_tx_datarate == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_tx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_tx_excvr_gb_ratio_mode == E400G_25G_12_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_tx_excvr_if_fifo_mode == E400G_25G_12_TX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_tx_fec_enable == E400G_25G_12_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_tx_pcs_mode == E400G_25G_12_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_tx_primary_use == E400G_25G_12_TX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_tx_stream_bonding == E400G_25G_12_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_tx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_tx_xcvr_bonded == E400G_25G_12_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_tx_xcvr_width == E400G_25G_12_TX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_xcvr_type == E400G_25G_12_XCVR_TYPE_UX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_12_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_aib2_rx_st_clk_en == E400G_25G_13_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_aib2_tx_st_clk_en == E400G_25G_13_AIB2_TX_ST_CLK_EN_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_aib3_rx_st_clk_en == E400G_25G_13_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_aib3_tx_st_clk_en == E400G_25G_13_AIB3_TX_ST_CLK_EN_TX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_duplex_mode == E400G_25G_13_DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_fec_clk_src == E400G_25G_13_FEC_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_fec_error == E400G_25G_13_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_fec_mode == E400G_25G_13_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_fec_spec == E400G_25G_13_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_lpbk_mode == E400G_25G_13_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_mac_mode == E400G_25G_13_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_ptp_mode == E400G_25G_13_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_rx_excvr_gb_ratio_mode == E400G_25G_13_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_rx_excvr_if_fifo_mode == E400G_25G_13_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_rx_fec_enable == E400G_25G_13_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_rx_pcs_mode == E400G_25G_13_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_rx_primary_use == E400G_25G_13_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_rx_stream_bonding == E400G_25G_13_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_rx_xcvr_bonded == E400G_25G_13_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_rx_xcvr_width == E400G_25G_13_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_speed_map == E400G_25G_13_SPEED_MAP_MAP_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_sup_mode == E400G_25G_13_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_sys_clk_src == E400G_25G_13_SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_tx_datarate == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_tx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_tx_excvr_gb_ratio_mode == E400G_25G_13_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_tx_excvr_if_fifo_mode == E400G_25G_13_TX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_tx_fec_enable == E400G_25G_13_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_tx_pcs_mode == E400G_25G_13_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_tx_primary_use == E400G_25G_13_TX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_tx_stream_bonding == E400G_25G_13_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_tx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_tx_xcvr_bonded == E400G_25G_13_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_tx_xcvr_width == E400G_25G_13_TX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_xcvr_type == E400G_25G_13_XCVR_TYPE_UX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_13_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_aib2_rx_st_clk_en == E400G_25G_14_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_aib2_tx_st_clk_en == E400G_25G_14_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_aib3_rx_st_clk_en == E400G_25G_14_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_aib3_tx_st_clk_en == E400G_25G_14_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_duplex_mode == E400G_25G_14_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_fec_clk_src == E400G_25G_14_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_fec_error == E400G_25G_14_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_fec_mode == E400G_25G_14_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_fec_spec == E400G_25G_14_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_lpbk_mode == E400G_25G_14_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_mac_mode == E400G_25G_14_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_ptp_mode == E400G_25G_14_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_rx_excvr_gb_ratio_mode == E400G_25G_14_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_rx_excvr_if_fifo_mode == E400G_25G_14_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_rx_fec_enable == E400G_25G_14_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_rx_pcs_mode == E400G_25G_14_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_rx_primary_use == E400G_25G_14_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_rx_stream_bonding == E400G_25G_14_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_rx_xcvr_bonded == E400G_25G_14_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_rx_xcvr_width == E400G_25G_14_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_speed_map == E400G_25G_14_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_sup_mode == E400G_25G_14_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_sys_clk_src == E400G_25G_14_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_tx_excvr_gb_ratio_mode == E400G_25G_14_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_tx_excvr_if_fifo_mode == E400G_25G_14_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_tx_fec_enable == E400G_25G_14_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_tx_pcs_mode == E400G_25G_14_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_tx_primary_use == E400G_25G_14_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_tx_stream_bonding == E400G_25G_14_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_tx_xcvr_bonded == E400G_25G_14_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_tx_xcvr_width == E400G_25G_14_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_xcvr_type == E400G_25G_14_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_14_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_aib2_rx_st_clk_en == E400G_25G_15_AIB2_RX_ST_CLK_EN_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_aib2_tx_st_clk_en == E400G_25G_15_AIB2_TX_ST_CLK_EN_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_aib3_rx_st_clk_en == E400G_25G_15_AIB3_RX_ST_CLK_EN_RX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_aib3_tx_st_clk_en == E400G_25G_15_AIB3_TX_ST_CLK_EN_TX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_duplex_mode == E400G_25G_15_DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_fec_clk_src == E400G_25G_15_FEC_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_fec_error == E400G_25G_15_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_fec_mode == E400G_25G_15_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_fec_spec == E400G_25G_15_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_lpbk_mode == E400G_25G_15_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_mac_mode == E400G_25G_15_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_ptp_mode == E400G_25G_15_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_rx_datarate == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_rx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_rx_excvr_gb_ratio_mode == E400G_25G_15_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_rx_excvr_if_fifo_mode == E400G_25G_15_RX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_rx_fec_enable == E400G_25G_15_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_rx_pcs_mode == E400G_25G_15_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_rx_primary_use == E400G_25G_15_RX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_rx_stream_bonding == E400G_25G_15_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_rx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_rx_xcvr_bonded == E400G_25G_15_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_rx_xcvr_width == E400G_25G_15_RX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_speed_map == E400G_25G_15_SPEED_MAP_MAP_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_sup_mode == E400G_25G_15_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_sys_clk_src == E400G_25G_15_SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_tx_datarate == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_tx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_tx_excvr_gb_ratio_mode == E400G_25G_15_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_tx_excvr_if_fifo_mode == E400G_25G_15_TX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_tx_fec_enable == E400G_25G_15_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_tx_pcs_mode == E400G_25G_15_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_tx_primary_use == E400G_25G_15_TX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_tx_stream_bonding == E400G_25G_15_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_tx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_tx_xcvr_bonded == E400G_25G_15_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_tx_xcvr_width == E400G_25G_15_TX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_xcvr_type == E400G_25G_15_XCVR_TYPE_UX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_15_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_aib2_rx_st_clk_en == E400G_25G_1_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_aib2_tx_st_clk_en == E400G_25G_1_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_aib3_rx_st_clk_en == E400G_25G_1_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_aib3_tx_st_clk_en == E400G_25G_1_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_duplex_mode == E400G_25G_1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_fec_clk_src == E400G_25G_1_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_fec_error == E400G_25G_1_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_fec_mode == E400G_25G_1_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_fec_spec == E400G_25G_1_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_lpbk_mode == E400G_25G_1_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_mac_mode == E400G_25G_1_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_ptp_mode == E400G_25G_1_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_rx_excvr_gb_ratio_mode == E400G_25G_1_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_rx_excvr_if_fifo_mode == E400G_25G_1_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_rx_fec_enable == E400G_25G_1_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_rx_pcs_mode == E400G_25G_1_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_rx_primary_use == E400G_25G_1_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_rx_stream_bonding == E400G_25G_1_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_rx_xcvr_bonded == E400G_25G_1_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_rx_xcvr_width == E400G_25G_1_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_speed_map == E400G_25G_1_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_sup_mode == E400G_25G_1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_sys_clk_src == E400G_25G_1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_tx_excvr_gb_ratio_mode == E400G_25G_1_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_tx_excvr_if_fifo_mode == E400G_25G_1_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_tx_fec_enable == E400G_25G_1_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_tx_pcs_mode == E400G_25G_1_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_tx_primary_use == E400G_25G_1_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_tx_stream_bonding == E400G_25G_1_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_tx_xcvr_bonded == E400G_25G_1_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_tx_xcvr_width == E400G_25G_1_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_xcvr_type == E400G_25G_1_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_1_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_aib2_rx_st_clk_en == E400G_25G_2_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_aib2_tx_st_clk_en == E400G_25G_2_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_aib3_rx_st_clk_en == E400G_25G_2_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_aib3_tx_st_clk_en == E400G_25G_2_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_duplex_mode == E400G_25G_2_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_fec_clk_src == E400G_25G_2_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_fec_error == E400G_25G_2_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_fec_mode == E400G_25G_2_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_fec_spec == E400G_25G_2_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_lpbk_mode == E400G_25G_2_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_mac_mode == E400G_25G_2_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_ptp_mode == E400G_25G_2_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_rx_excvr_gb_ratio_mode == E400G_25G_2_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_rx_excvr_if_fifo_mode == E400G_25G_2_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_rx_fec_enable == E400G_25G_2_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_rx_pcs_mode == E400G_25G_2_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_rx_primary_use == E400G_25G_2_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_rx_stream_bonding == E400G_25G_2_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_rx_xcvr_bonded == E400G_25G_2_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_rx_xcvr_width == E400G_25G_2_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_speed_map == E400G_25G_2_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_sup_mode == E400G_25G_2_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_sys_clk_src == E400G_25G_2_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_tx_excvr_gb_ratio_mode == E400G_25G_2_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_tx_excvr_if_fifo_mode == E400G_25G_2_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_tx_fec_enable == E400G_25G_2_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_tx_pcs_mode == E400G_25G_2_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_tx_primary_use == E400G_25G_2_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_tx_stream_bonding == E400G_25G_2_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_tx_xcvr_bonded == E400G_25G_2_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_tx_xcvr_width == E400G_25G_2_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_xcvr_type == E400G_25G_2_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_2_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_aib2_rx_st_clk_en == E400G_25G_3_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_aib2_tx_st_clk_en == E400G_25G_3_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_aib3_rx_st_clk_en == E400G_25G_3_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_aib3_tx_st_clk_en == E400G_25G_3_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_duplex_mode == E400G_25G_3_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_fec_clk_src == E400G_25G_3_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_fec_error == E400G_25G_3_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_fec_mode == E400G_25G_3_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_fec_spec == E400G_25G_3_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_lpbk_mode == E400G_25G_3_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_mac_mode == E400G_25G_3_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_ptp_mode == E400G_25G_3_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_rx_excvr_gb_ratio_mode == E400G_25G_3_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_rx_excvr_if_fifo_mode == E400G_25G_3_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_rx_fec_enable == E400G_25G_3_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_rx_pcs_mode == E400G_25G_3_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_rx_primary_use == E400G_25G_3_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_rx_stream_bonding == E400G_25G_3_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_rx_xcvr_bonded == E400G_25G_3_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_rx_xcvr_width == E400G_25G_3_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_speed_map == E400G_25G_3_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_sup_mode == E400G_25G_3_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_sys_clk_src == E400G_25G_3_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_tx_excvr_gb_ratio_mode == E400G_25G_3_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_tx_excvr_if_fifo_mode == E400G_25G_3_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_tx_fec_enable == E400G_25G_3_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_tx_pcs_mode == E400G_25G_3_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_tx_primary_use == E400G_25G_3_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_tx_stream_bonding == E400G_25G_3_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_tx_xcvr_bonded == E400G_25G_3_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_tx_xcvr_width == E400G_25G_3_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_xcvr_type == E400G_25G_3_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_3_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_aib2_rx_st_clk_en == E400G_25G_4_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_aib2_tx_st_clk_en == E400G_25G_4_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_aib3_rx_st_clk_en == E400G_25G_4_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_aib3_tx_st_clk_en == E400G_25G_4_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_duplex_mode == E400G_25G_4_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_fec_clk_src == E400G_25G_4_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_fec_error == E400G_25G_4_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_fec_mode == E400G_25G_4_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_fec_spec == E400G_25G_4_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_lpbk_mode == E400G_25G_4_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_mac_mode == E400G_25G_4_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_ptp_mode == E400G_25G_4_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_rx_excvr_gb_ratio_mode == E400G_25G_4_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_rx_excvr_if_fifo_mode == E400G_25G_4_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_rx_fec_enable == E400G_25G_4_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_rx_pcs_mode == E400G_25G_4_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_rx_primary_use == E400G_25G_4_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_rx_stream_bonding == E400G_25G_4_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_rx_xcvr_bonded == E400G_25G_4_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_rx_xcvr_width == E400G_25G_4_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_speed_map == E400G_25G_4_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_sup_mode == E400G_25G_4_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_sys_clk_src == E400G_25G_4_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_tx_excvr_gb_ratio_mode == E400G_25G_4_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_tx_excvr_if_fifo_mode == E400G_25G_4_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_tx_fec_enable == E400G_25G_4_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_tx_pcs_mode == E400G_25G_4_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_tx_primary_use == E400G_25G_4_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_tx_stream_bonding == E400G_25G_4_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_tx_xcvr_bonded == E400G_25G_4_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_tx_xcvr_width == E400G_25G_4_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_xcvr_type == E400G_25G_4_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_4_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_aib2_rx_st_clk_en == E400G_25G_5_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_aib2_tx_st_clk_en == E400G_25G_5_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_aib3_rx_st_clk_en == E400G_25G_5_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_aib3_tx_st_clk_en == E400G_25G_5_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_duplex_mode == E400G_25G_5_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_fec_clk_src == E400G_25G_5_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_fec_error == E400G_25G_5_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_fec_mode == E400G_25G_5_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_fec_spec == E400G_25G_5_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_lpbk_mode == E400G_25G_5_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_mac_mode == E400G_25G_5_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_ptp_mode == E400G_25G_5_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_rx_excvr_gb_ratio_mode == E400G_25G_5_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_rx_excvr_if_fifo_mode == E400G_25G_5_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_rx_fec_enable == E400G_25G_5_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_rx_pcs_mode == E400G_25G_5_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_rx_primary_use == E400G_25G_5_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_rx_stream_bonding == E400G_25G_5_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_rx_xcvr_bonded == E400G_25G_5_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_rx_xcvr_width == E400G_25G_5_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_speed_map == E400G_25G_5_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_sup_mode == E400G_25G_5_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_sys_clk_src == E400G_25G_5_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_tx_excvr_gb_ratio_mode == E400G_25G_5_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_tx_excvr_if_fifo_mode == E400G_25G_5_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_tx_fec_enable == E400G_25G_5_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_tx_pcs_mode == E400G_25G_5_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_tx_primary_use == E400G_25G_5_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_tx_stream_bonding == E400G_25G_5_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_tx_xcvr_bonded == E400G_25G_5_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_tx_xcvr_width == E400G_25G_5_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_xcvr_type == E400G_25G_5_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_5_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_aib2_rx_st_clk_en == E400G_25G_6_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_aib2_tx_st_clk_en == E400G_25G_6_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_aib3_rx_st_clk_en == E400G_25G_6_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_aib3_tx_st_clk_en == E400G_25G_6_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_duplex_mode == E400G_25G_6_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_fec_clk_src == E400G_25G_6_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_fec_error == E400G_25G_6_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_fec_mode == E400G_25G_6_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_fec_spec == E400G_25G_6_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_lpbk_mode == E400G_25G_6_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_mac_mode == E400G_25G_6_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_ptp_mode == E400G_25G_6_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_rx_excvr_gb_ratio_mode == E400G_25G_6_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_rx_excvr_if_fifo_mode == E400G_25G_6_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_rx_fec_enable == E400G_25G_6_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_rx_pcs_mode == E400G_25G_6_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_rx_primary_use == E400G_25G_6_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_rx_stream_bonding == E400G_25G_6_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_rx_xcvr_bonded == E400G_25G_6_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_rx_xcvr_width == E400G_25G_6_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_speed_map == E400G_25G_6_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_sup_mode == E400G_25G_6_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_sys_clk_src == E400G_25G_6_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_tx_excvr_gb_ratio_mode == E400G_25G_6_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_tx_excvr_if_fifo_mode == E400G_25G_6_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_tx_fec_enable == E400G_25G_6_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_tx_pcs_mode == E400G_25G_6_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_tx_primary_use == E400G_25G_6_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_tx_stream_bonding == E400G_25G_6_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_tx_xcvr_bonded == E400G_25G_6_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_tx_xcvr_width == E400G_25G_6_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_xcvr_type == E400G_25G_6_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_6_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_aib2_rx_st_clk_en == E400G_25G_7_AIB2_RX_ST_CLK_EN_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_aib2_tx_st_clk_en == E400G_25G_7_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_aib3_rx_st_clk_en == E400G_25G_7_AIB3_RX_ST_CLK_EN_RX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_aib3_tx_st_clk_en == E400G_25G_7_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_duplex_mode == E400G_25G_7_DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_fec_clk_src == E400G_25G_7_FEC_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_fec_error == E400G_25G_7_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_fec_mode == E400G_25G_7_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_fec_spec == E400G_25G_7_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_lpbk_mode == E400G_25G_7_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_mac_mode == E400G_25G_7_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_ptp_mode == E400G_25G_7_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_rx_datarate == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_rx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_rx_excvr_gb_ratio_mode == E400G_25G_7_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_rx_excvr_if_fifo_mode == E400G_25G_7_RX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_rx_fec_enable == E400G_25G_7_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_rx_pcs_mode == E400G_25G_7_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_rx_primary_use == E400G_25G_7_RX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_rx_stream_bonding == E400G_25G_7_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_rx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_rx_xcvr_bonded == E400G_25G_7_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_rx_xcvr_width == E400G_25G_7_RX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_speed_map == E400G_25G_7_SPEED_MAP_MAP_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_sup_mode == E400G_25G_7_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_sys_clk_src == E400G_25G_7_SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_tx_excvr_gb_ratio_mode == E400G_25G_7_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_tx_excvr_if_fifo_mode == E400G_25G_7_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_tx_fec_enable == E400G_25G_7_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_tx_pcs_mode == E400G_25G_7_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_tx_primary_use == E400G_25G_7_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_tx_stream_bonding == E400G_25G_7_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_tx_xcvr_bonded == E400G_25G_7_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_tx_xcvr_width == E400G_25G_7_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_xcvr_type == E400G_25G_7_XCVR_TYPE_UX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_7_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_aib2_rx_st_clk_en == E400G_25G_8_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_aib2_tx_st_clk_en == E400G_25G_8_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_aib3_rx_st_clk_en == E400G_25G_8_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_aib3_tx_st_clk_en == E400G_25G_8_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_duplex_mode == E400G_25G_8_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_fec_clk_src == E400G_25G_8_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_fec_error == E400G_25G_8_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_fec_mode == E400G_25G_8_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_fec_spec == E400G_25G_8_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_lpbk_mode == E400G_25G_8_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_mac_mode == E400G_25G_8_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_ptp_mode == E400G_25G_8_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_rx_excvr_gb_ratio_mode == E400G_25G_8_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_rx_excvr_if_fifo_mode == E400G_25G_8_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_rx_fec_enable == E400G_25G_8_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_rx_pcs_mode == E400G_25G_8_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_rx_primary_use == E400G_25G_8_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_rx_stream_bonding == E400G_25G_8_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_rx_xcvr_bonded == E400G_25G_8_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_rx_xcvr_width == E400G_25G_8_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_speed_map == E400G_25G_8_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_sup_mode == E400G_25G_8_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_sys_clk_src == E400G_25G_8_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_tx_excvr_gb_ratio_mode == E400G_25G_8_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_tx_excvr_if_fifo_mode == E400G_25G_8_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_tx_fec_enable == E400G_25G_8_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_tx_pcs_mode == E400G_25G_8_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_tx_primary_use == E400G_25G_8_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_tx_stream_bonding == E400G_25G_8_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_tx_xcvr_bonded == E400G_25G_8_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_tx_xcvr_width == E400G_25G_8_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_xcvr_type == E400G_25G_8_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_8_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_aib2_rx_st_clk_en == E400G_25G_9_AIB2_RX_ST_CLK_EN_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_aib2_tx_st_clk_en == E400G_25G_9_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_aib3_rx_st_clk_en == E400G_25G_9_AIB3_RX_ST_CLK_EN_RX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_aib3_tx_st_clk_en == E400G_25G_9_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_duplex_mode == E400G_25G_9_DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_fec_clk_src == E400G_25G_9_FEC_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_fec_error == E400G_25G_9_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_fec_mode == E400G_25G_9_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_fec_spec == E400G_25G_9_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_lpbk_mode == E400G_25G_9_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_mac_mode == E400G_25G_9_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_ptp_mode == E400G_25G_9_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_rx_datarate == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_rx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_rx_excvr_gb_ratio_mode == E400G_25G_9_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_rx_excvr_if_fifo_mode == E400G_25G_9_RX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_rx_fec_enable == E400G_25G_9_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_rx_pcs_mode == E400G_25G_9_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_rx_primary_use == E400G_25G_9_RX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_rx_stream_bonding == E400G_25G_9_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_rx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_rx_xcvr_bonded == E400G_25G_9_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_rx_xcvr_width == E400G_25G_9_RX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_speed_map == E400G_25G_9_SPEED_MAP_MAP_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_sup_mode == E400G_25G_9_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_sys_clk_src == E400G_25G_9_SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_tx_excvr_gb_ratio_mode == E400G_25G_9_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_tx_excvr_if_fifo_mode == E400G_25G_9_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_tx_fec_enable == E400G_25G_9_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_tx_pcs_mode == E400G_25G_9_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_tx_primary_use == E400G_25G_9_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_tx_stream_bonding == E400G_25G_9_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_tx_xcvr_bonded == E400G_25G_9_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_tx_xcvr_width == E400G_25G_9_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_xcvr_type == E400G_25G_9_XCVR_TYPE_UX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_25g_9_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_aib2_rx_st_clk_en == E400G_300G_0_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_aib2_tx_st_clk_en == E400G_300G_0_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_aib3_rx_st_clk_en == E400G_300G_0_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_aib3_tx_st_clk_en == E400G_300G_0_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_duplex_mode == E400G_300G_0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_fec_mode == E400G_300G_0_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_fec_spec == E400G_300G_0_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_lpbk_mode == E400G_300G_0_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_mac_mode == E400G_300G_0_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_ptp_mode == E400G_300G_0_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_rx_excvr_gb_ratio_mode == E400G_300G_0_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_rx_excvr_if_fifo_mode == E400G_300G_0_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_rx_fec_enable == E400G_300G_0_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_rx_pcs_mode == E400G_300G_0_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_rx_primary_use == E400G_300G_0_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_rx_stream_bonding == E400G_300G_0_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_rx_xcvr_bonded == E400G_300G_0_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_rx_xcvr_width == E400G_300G_0_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_speed_map == E400G_300G_0_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_sup_mode == E400G_300G_0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_sys_clk_src == E400G_300G_0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_tx_excvr_gb_ratio_mode == E400G_300G_0_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_tx_excvr_if_fifo_mode == E400G_300G_0_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_tx_fec_enable == E400G_300G_0_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_tx_pcs_mode == E400G_300G_0_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_tx_primary_use == E400G_300G_0_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_tx_stream_bonding == E400G_300G_0_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_tx_xcvr_bonded == E400G_300G_0_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_tx_xcvr_width == E400G_300G_0_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_xcvr_type == E400G_300G_0_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_0_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_aib2_rx_st_clk_en == E400G_300G_1_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_aib2_tx_st_clk_en == E400G_300G_1_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_aib3_rx_st_clk_en == E400G_300G_1_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_aib3_tx_st_clk_en == E400G_300G_1_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_duplex_mode == E400G_300G_1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_fec_mode == E400G_300G_1_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_fec_spec == E400G_300G_1_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_lpbk_mode == E400G_300G_1_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_mac_mode == E400G_300G_1_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_ptp_mode == E400G_300G_1_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_rx_excvr_gb_ratio_mode == E400G_300G_1_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_rx_excvr_if_fifo_mode == E400G_300G_1_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_rx_fec_enable == E400G_300G_1_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_rx_pcs_mode == E400G_300G_1_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_rx_primary_use == E400G_300G_1_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_rx_stream_bonding == E400G_300G_1_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_rx_xcvr_bonded == E400G_300G_1_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_rx_xcvr_width == E400G_300G_1_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_speed_map == E400G_300G_1_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_sup_mode == E400G_300G_1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_sys_clk_src == E400G_300G_1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_tx_excvr_gb_ratio_mode == E400G_300G_1_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_tx_excvr_if_fifo_mode == E400G_300G_1_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_tx_fec_enable == E400G_300G_1_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_tx_pcs_mode == E400G_300G_1_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_tx_primary_use == E400G_300G_1_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_tx_stream_bonding == E400G_300G_1_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_tx_xcvr_bonded == E400G_300G_1_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_tx_xcvr_width == E400G_300G_1_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_xcvr_type == E400G_300G_1_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_300g_1_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_aib2_rx_st_clk_en == E400G_400G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_aib2_tx_st_clk_en == E400G_400G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_aib3_rx_st_clk_en == E400G_400G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_aib3_tx_st_clk_en == E400G_400G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_duplex_mode == E400G_400G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_fec_clk_src == E400G_400G_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_fec_error == E400G_400G_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_fec_mode == E400G_400G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_fec_spec == E400G_400G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_lpbk_mode == E400G_400G_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_mac_mode == E400G_400G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_ptp_mode == E400G_400G_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_rx_excvr_gb_ratio_mode == E400G_400G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_rx_excvr_if_fifo_mode == E400G_400G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_rx_fec_enable == E400G_400G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_rx_pcs_mode == E400G_400G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_rx_primary_use == E400G_400G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_rx_stream_bonding == E400G_400G_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_rx_xcvr_bonded == E400G_400G_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_rx_xcvr_width == E400G_400G_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_speed_map == E400G_400G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_sup_mode == E400G_400G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_sys_clk_src == E400G_400G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_tx_excvr_gb_ratio_mode == E400G_400G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_tx_excvr_if_fifo_mode == E400G_400G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_tx_fec_enable == E400G_400G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_tx_pcs_mode == E400G_400G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_tx_primary_use == E400G_400G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_tx_stream_bonding == E400G_400G_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_tx_xcvr_bonded == E400G_400G_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_tx_xcvr_width == E400G_400G_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_xcvr_type == E400G_400G_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_400g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_aib2_rx_st_clk_en == E400G_50G_0_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_aib2_tx_st_clk_en == E400G_50G_0_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_aib3_rx_st_clk_en == E400G_50G_0_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_aib3_tx_st_clk_en == E400G_50G_0_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_duplex_mode == E400G_50G_0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_fec_clk_src == E400G_50G_0_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_fec_error == E400G_50G_0_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_fec_mode == E400G_50G_0_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_fec_spec == E400G_50G_0_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_lpbk_mode == E400G_50G_0_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_mac_mode == E400G_50G_0_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_ptp_mode == E400G_50G_0_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_rx_excvr_gb_ratio_mode == E400G_50G_0_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_rx_excvr_if_fifo_mode == E400G_50G_0_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_rx_fec_enable == E400G_50G_0_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_rx_pcs_mode == E400G_50G_0_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_rx_primary_use == E400G_50G_0_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_rx_stream_bonding == E400G_50G_0_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_rx_xcvr_bonded == E400G_50G_0_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_rx_xcvr_width == E400G_50G_0_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_speed_map == E400G_50G_0_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_sup_mode == E400G_50G_0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_sys_clk_src == E400G_50G_0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_tx_excvr_gb_ratio_mode == E400G_50G_0_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_tx_excvr_if_fifo_mode == E400G_50G_0_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_tx_fec_enable == E400G_50G_0_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_tx_pcs_mode == E400G_50G_0_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_tx_primary_use == E400G_50G_0_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_tx_stream_bonding == E400G_50G_0_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_tx_xcvr_bonded == E400G_50G_0_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_tx_xcvr_width == E400G_50G_0_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_xcvr_type == E400G_50G_0_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_0_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_aib2_rx_st_clk_en == E400G_50G_1_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_aib2_tx_st_clk_en == E400G_50G_1_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_aib3_rx_st_clk_en == E400G_50G_1_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_aib3_tx_st_clk_en == E400G_50G_1_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_duplex_mode == E400G_50G_1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_fec_clk_src == E400G_50G_1_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_fec_error == E400G_50G_1_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_fec_mode == E400G_50G_1_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_fec_spec == E400G_50G_1_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_lpbk_mode == E400G_50G_1_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_mac_mode == E400G_50G_1_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_ptp_mode == E400G_50G_1_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_rx_excvr_gb_ratio_mode == E400G_50G_1_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_rx_excvr_if_fifo_mode == E400G_50G_1_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_rx_fec_enable == E400G_50G_1_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_rx_pcs_mode == E400G_50G_1_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_rx_primary_use == E400G_50G_1_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_rx_stream_bonding == E400G_50G_1_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_rx_xcvr_bonded == E400G_50G_1_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_rx_xcvr_width == E400G_50G_1_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_speed_map == E400G_50G_1_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_sup_mode == E400G_50G_1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_sys_clk_src == E400G_50G_1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_tx_excvr_gb_ratio_mode == E400G_50G_1_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_tx_excvr_if_fifo_mode == E400G_50G_1_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_tx_fec_enable == E400G_50G_1_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_tx_pcs_mode == E400G_50G_1_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_tx_primary_use == E400G_50G_1_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_tx_stream_bonding == E400G_50G_1_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_tx_xcvr_bonded == E400G_50G_1_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_tx_xcvr_width == E400G_50G_1_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_xcvr_type == E400G_50G_1_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_1_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_aib2_rx_st_clk_en == E400G_50G_2_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_aib2_tx_st_clk_en == E400G_50G_2_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_aib3_rx_st_clk_en == E400G_50G_2_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_aib3_tx_st_clk_en == E400G_50G_2_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_duplex_mode == E400G_50G_2_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_fec_clk_src == E400G_50G_2_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_fec_error == E400G_50G_2_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_fec_mode == E400G_50G_2_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_fec_spec == E400G_50G_2_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_lpbk_mode == E400G_50G_2_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_mac_mode == E400G_50G_2_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_ptp_mode == E400G_50G_2_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_rx_excvr_gb_ratio_mode == E400G_50G_2_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_rx_excvr_if_fifo_mode == E400G_50G_2_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_rx_fec_enable == E400G_50G_2_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_rx_pcs_mode == E400G_50G_2_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_rx_primary_use == E400G_50G_2_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_rx_stream_bonding == E400G_50G_2_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_rx_xcvr_bonded == E400G_50G_2_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_rx_xcvr_width == E400G_50G_2_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_speed_map == E400G_50G_2_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_sup_mode == E400G_50G_2_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_sys_clk_src == E400G_50G_2_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_tx_excvr_gb_ratio_mode == E400G_50G_2_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_tx_excvr_if_fifo_mode == E400G_50G_2_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_tx_fec_enable == E400G_50G_2_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_tx_pcs_mode == E400G_50G_2_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_tx_primary_use == E400G_50G_2_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_tx_stream_bonding == E400G_50G_2_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_tx_xcvr_bonded == E400G_50G_2_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_tx_xcvr_width == E400G_50G_2_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_xcvr_type == E400G_50G_2_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_2_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_aib2_rx_st_clk_en == E400G_50G_3_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_aib2_tx_st_clk_en == E400G_50G_3_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_aib3_rx_st_clk_en == E400G_50G_3_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_aib3_tx_st_clk_en == E400G_50G_3_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_duplex_mode == E400G_50G_3_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_fec_clk_src == E400G_50G_3_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_fec_error == E400G_50G_3_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_fec_mode == E400G_50G_3_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_fec_spec == E400G_50G_3_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_lpbk_mode == E400G_50G_3_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_mac_mode == E400G_50G_3_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_ptp_mode == E400G_50G_3_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_rx_excvr_gb_ratio_mode == E400G_50G_3_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_rx_excvr_if_fifo_mode == E400G_50G_3_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_rx_fec_enable == E400G_50G_3_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_rx_pcs_mode == E400G_50G_3_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_rx_primary_use == E400G_50G_3_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_rx_stream_bonding == E400G_50G_3_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_rx_xcvr_bonded == E400G_50G_3_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_rx_xcvr_width == E400G_50G_3_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_speed_map == E400G_50G_3_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_sup_mode == E400G_50G_3_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_sys_clk_src == E400G_50G_3_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_tx_excvr_gb_ratio_mode == E400G_50G_3_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_tx_excvr_if_fifo_mode == E400G_50G_3_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_tx_fec_enable == E400G_50G_3_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_tx_pcs_mode == E400G_50G_3_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_tx_primary_use == E400G_50G_3_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_tx_stream_bonding == E400G_50G_3_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_tx_xcvr_bonded == E400G_50G_3_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_tx_xcvr_width == E400G_50G_3_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_xcvr_type == E400G_50G_3_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_3_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_aib2_rx_st_clk_en == E400G_50G_4_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_aib2_tx_st_clk_en == E400G_50G_4_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_aib3_rx_st_clk_en == E400G_50G_4_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_aib3_tx_st_clk_en == E400G_50G_4_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_duplex_mode == E400G_50G_4_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_fec_clk_src == E400G_50G_4_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_fec_error == E400G_50G_4_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_fec_mode == E400G_50G_4_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_fec_spec == E400G_50G_4_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_lpbk_mode == E400G_50G_4_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_mac_mode == E400G_50G_4_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_ptp_mode == E400G_50G_4_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_rx_excvr_gb_ratio_mode == E400G_50G_4_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_rx_excvr_if_fifo_mode == E400G_50G_4_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_rx_fec_enable == E400G_50G_4_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_rx_pcs_mode == E400G_50G_4_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_rx_primary_use == E400G_50G_4_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_rx_stream_bonding == E400G_50G_4_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_rx_xcvr_bonded == E400G_50G_4_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_rx_xcvr_width == E400G_50G_4_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_speed_map == E400G_50G_4_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_sup_mode == E400G_50G_4_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_sys_clk_src == E400G_50G_4_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_tx_excvr_gb_ratio_mode == E400G_50G_4_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_tx_excvr_if_fifo_mode == E400G_50G_4_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_tx_fec_enable == E400G_50G_4_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_tx_pcs_mode == E400G_50G_4_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_tx_primary_use == E400G_50G_4_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_tx_stream_bonding == E400G_50G_4_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_tx_xcvr_bonded == E400G_50G_4_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_tx_xcvr_width == E400G_50G_4_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_xcvr_type == E400G_50G_4_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_4_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_aib2_rx_st_clk_en == E400G_50G_5_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_aib2_tx_st_clk_en == E400G_50G_5_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_aib3_rx_st_clk_en == E400G_50G_5_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_aib3_tx_st_clk_en == E400G_50G_5_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_duplex_mode == E400G_50G_5_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_fec_clk_src == E400G_50G_5_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_fec_error == E400G_50G_5_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_fec_mode == E400G_50G_5_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_fec_spec == E400G_50G_5_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_lpbk_mode == E400G_50G_5_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_mac_mode == E400G_50G_5_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_ptp_mode == E400G_50G_5_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_rx_excvr_gb_ratio_mode == E400G_50G_5_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_rx_excvr_if_fifo_mode == E400G_50G_5_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_rx_fec_enable == E400G_50G_5_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_rx_pcs_mode == E400G_50G_5_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_rx_primary_use == E400G_50G_5_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_rx_stream_bonding == E400G_50G_5_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_rx_xcvr_bonded == E400G_50G_5_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_rx_xcvr_width == E400G_50G_5_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_speed_map == E400G_50G_5_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_sup_mode == E400G_50G_5_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_sys_clk_src == E400G_50G_5_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_tx_excvr_gb_ratio_mode == E400G_50G_5_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_tx_excvr_if_fifo_mode == E400G_50G_5_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_tx_fec_enable == E400G_50G_5_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_tx_pcs_mode == E400G_50G_5_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_tx_primary_use == E400G_50G_5_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_tx_stream_bonding == E400G_50G_5_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_tx_xcvr_bonded == E400G_50G_5_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_tx_xcvr_width == E400G_50G_5_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_xcvr_type == E400G_50G_5_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_5_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_aib2_rx_st_clk_en == E400G_50G_6_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_aib2_tx_st_clk_en == E400G_50G_6_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_aib3_rx_st_clk_en == E400G_50G_6_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_aib3_tx_st_clk_en == E400G_50G_6_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_duplex_mode == E400G_50G_6_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_fec_clk_src == E400G_50G_6_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_fec_error == E400G_50G_6_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_fec_mode == E400G_50G_6_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_fec_spec == E400G_50G_6_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_lpbk_mode == E400G_50G_6_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_mac_mode == E400G_50G_6_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_ptp_mode == E400G_50G_6_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_rx_excvr_gb_ratio_mode == E400G_50G_6_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_rx_excvr_if_fifo_mode == E400G_50G_6_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_rx_fec_enable == E400G_50G_6_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_rx_pcs_mode == E400G_50G_6_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_rx_primary_use == E400G_50G_6_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_rx_stream_bonding == E400G_50G_6_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_rx_xcvr_bonded == E400G_50G_6_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_rx_xcvr_width == E400G_50G_6_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_speed_map == E400G_50G_6_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_sup_mode == E400G_50G_6_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_sys_clk_src == E400G_50G_6_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_tx_excvr_gb_ratio_mode == E400G_50G_6_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_tx_excvr_if_fifo_mode == E400G_50G_6_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_tx_fec_enable == E400G_50G_6_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_tx_pcs_mode == E400G_50G_6_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_tx_primary_use == E400G_50G_6_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_tx_stream_bonding == E400G_50G_6_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_tx_xcvr_bonded == E400G_50G_6_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_tx_xcvr_width == E400G_50G_6_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_xcvr_type == E400G_50G_6_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_6_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_aib2_rx_st_clk_en == E400G_50G_7_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_aib2_tx_st_clk_en == E400G_50G_7_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_aib3_rx_st_clk_en == E400G_50G_7_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_aib3_tx_st_clk_en == E400G_50G_7_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_duplex_mode == E400G_50G_7_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_fec_clk_src == E400G_50G_7_FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_fec_error == E400G_50G_7_FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_fec_mode == E400G_50G_7_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_fec_spec == E400G_50G_7_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_lpbk_mode == E400G_50G_7_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_mac_mode == E400G_50G_7_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_ptp_mode == E400G_50G_7_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_rx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_rx_excvr_gb_ratio_mode == E400G_50G_7_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_rx_excvr_if_fifo_mode == E400G_50G_7_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_rx_fec_enable == E400G_50G_7_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_rx_pcs_mode == E400G_50G_7_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_rx_primary_use == E400G_50G_7_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_rx_stream_bonding == E400G_50G_7_RX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_rx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_rx_xcvr_bonded == E400G_50G_7_RX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_rx_xcvr_width == E400G_50G_7_RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_speed_map == E400G_50G_7_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_sup_mode == E400G_50G_7_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_sys_clk_src == E400G_50G_7_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_tx_datarate == 37'd1000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_tx_excvr_gb_ratio_mode == E400G_50G_7_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_tx_excvr_if_fifo_mode == E400G_50G_7_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_tx_fec_enable == E400G_50G_7_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_tx_pcs_mode == E400G_50G_7_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_tx_primary_use == E400G_50G_7_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_tx_stream_bonding == E400G_50G_7_TX_STREAM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_tx_system_bonding == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_tx_xcvr_bond_size == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_tx_xcvr_bonded == E400G_50G_7_TX_XCVR_BONDED_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_tx_xcvr_width == E400G_50G_7_TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_xcvr_type == E400G_50G_7_XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_50g_7_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_ptp0_aib2_div2_clk == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_ptp1_aib2_div2_clk == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream0_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream0_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream0_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream0_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream10_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream10_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream10_tx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream10_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream11_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream11_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream11_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream11_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream12_rx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream12_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream12_tx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream12_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream13_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream13_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream13_tx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream13_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream14_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream14_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream14_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream14_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream15_rx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream15_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream15_tx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream15_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream1_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream1_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream1_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream1_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream2_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream2_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream2_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream2_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream3_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream3_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream3_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream3_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream4_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream4_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream4_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream4_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream5_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream5_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream5_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream5_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream6_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream6_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream6_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream6_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream7_rx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream7_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream7_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream7_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream8_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream8_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream8_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream8_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream9_rx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream9_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream9_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.e400g_stream9_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.func_mode == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_112e4x0 == MAP_112E4X0_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_112e4x1 == MAP_112E4X1_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_112e4x2 == MAP_112E4X2_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_112e4x3 == MAP_112E4X3_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_25e4x0 == MAP_25E4X0_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_25e4x1 == MAP_25E4X1_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_25e4x10 == MAP_25E4X10_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_25e4x11 == MAP_25E4X11_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_25e4x12 == MAP_25E4X12_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_25e4x13 == MAP_25E4X13_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_25e4x14 == MAP_25E4X14_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_25e4x15 == MAP_25E4X15_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_25e4x2 == MAP_25E4X2_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_25e4x3 == MAP_25E4X3_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_25e4x4 == MAP_25E4X4_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_25e4x5 == MAP_25E4X5_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_25e4x6 == MAP_25E4X6_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_25e4x7 == MAP_25E4X7_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_25e4x8 == MAP_25E4X8_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_25e4x9 == MAP_25E4X9_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_56e4x0 == MAP_56E4X0_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_56e4x1 == MAP_56E4X1_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_56e4x2 == MAP_56E4X2_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_56e4x3 == MAP_56E4X3_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_56e4x4 == MAP_56E4X4_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_56e4x5 == MAP_56E4X5_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_56e4x6 == MAP_56E4X6_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_56e4x7 == MAP_56E4X7_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_bk0 == MAP_BK0_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_bk1 == MAP_BK1_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_bk2 == MAP_BK2_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_bk3 == MAP_BK3_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_ux0 == MAP_UX0_ENABLE_25E4X15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_ux1 == MAP_UX1_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_ux10 == MAP_UX10_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_ux11 == MAP_UX11_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_ux12 == MAP_UX12_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_ux13 == MAP_UX13_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_ux14 == MAP_UX14_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_ux15 == MAP_UX15_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_ux2 == MAP_UX2_ENABLE_25E4X13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_ux3 == MAP_UX3_ENABLE_25E4X12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_ux4 == MAP_UX4_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_ux5 == MAP_UX5_ENABLE_25E4X10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_ux6 == MAP_UX6_ENABLE_25E4X9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_ux7 == MAP_UX7_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_ux8 == MAP_UX8_ENABLE_25E4X7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.map_ux9 == MAP_UX9_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_100g_0 == OFF_100G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_100g_0_non_std_freq_comp == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_100g_0_non_std_static == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_100g_1 == OFF_100G_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_100g_1_non_std_freq_comp == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_100g_1_non_std_static == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_100g_2 == OFF_100G_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_100g_2_non_std_freq_comp == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_100g_2_non_std_static == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_100g_3 == OFF_100G_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_100g_3_non_std_freq_comp == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_100g_3_non_std_static == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_150g_0 == OFF_150G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_150g_1 == OFF_150G_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_150g_2 == OFF_150G_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_150g_3 == OFF_150G_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_200g_0 == OFF_200G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_200g_0_non_std_freq_comp == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_200g_0_non_std_static == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_200g_1 == OFF_200G_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_200g_1_non_std_freq_comp == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_200g_1_non_std_static == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_0 == OFF_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_0_non_std_freq_comp == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_0_non_std_static == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_1 == OFF_25G_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_10 == TX_25G_10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_10_non_std_freq_comp == ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_10_non_std_static == ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_11 == OFF_25G_11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_11_non_std_freq_comp == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_11_non_std_static == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_12 == DUPLEX_16G_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_12_non_std_freq_comp == ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_12_non_std_static == ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_13 == TX_25G_13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_13_non_std_freq_comp == ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_13_non_std_static == ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_14 == OFF_25G_14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_14_non_std_freq_comp == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_14_non_std_static == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_15 == DUPLEX_16G_15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_15_non_std_freq_comp == ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_15_non_std_static == ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_1_non_std_freq_comp == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_1_non_std_static == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_2 == OFF_25G_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_2_non_std_freq_comp == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_2_non_std_static == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_3 == OFF_25G_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_3_non_std_freq_comp == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_3_non_std_static == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_4 == OFF_25G_4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_4_non_std_freq_comp == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_4_non_std_static == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_5 == OFF_25G_5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_5_non_std_freq_comp == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_5_non_std_static == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_6 == OFF_25G_6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_6_non_std_freq_comp == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_6_non_std_static == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_7 == RX_25G_7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_7_non_std_freq_comp == ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_7_non_std_static == ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_8 == OFF_25G_8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_8_non_std_freq_comp == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_8_non_std_static == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_9 == RX_25G_9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_9_non_std_freq_comp == ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_25g_9_non_std_static == ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_300g_0 == OFF_300G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_300g_1 == OFF_300G_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_400g == OFF_400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_400g_non_std_freq_comp == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_400g_non_std_static == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_50g_0 == OFF_50G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_50g_0_non_std_freq_comp == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_50g_0_non_std_static == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_50g_1 == OFF_50G_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_50g_1_non_std_freq_comp == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_50g_1_non_std_static == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_50g_2 == OFF_50G_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_50g_2_non_std_freq_comp == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_50g_2_non_std_static == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_50g_3 == OFF_50G_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_50g_3_non_std_freq_comp == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_50g_3_non_std_static == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_50g_4 == OFF_50G_4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_50g_4_non_std_freq_comp == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_50g_4_non_std_static == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_50g_5 == OFF_50G_5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_50g_5_non_std_freq_comp == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_50g_5_non_std_static == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_50g_6 == OFF_50G_6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_50g_6_non_std_freq_comp == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_50g_6_non_std_static == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_50g_7 == OFF_50G_7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_50g_7_non_std_freq_comp == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_50g_7_non_std_static == OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_core0_clk == FEC_CORE0_CLK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_core1_clk == FEC_CORE1_CLK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_core2_clk == FEC_CORE2_CLK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_core3_clk == FEC_CORE3_CLK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_ac_global_avmm == GLOBAL_AVMM_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_rx_st0_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_rx_st10_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_rx_st11_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_rx_st12_clk == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_rx_st13_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_rx_st14_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_rx_st15_clk == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_rx_st1_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_rx_st2_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_rx_st3_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_rx_st4_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_rx_st5_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_rx_st6_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_rx_st7_clk == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_rx_st8_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_rx_st9_clk == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_tx_st0_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_tx_st0_clk_non_std == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_tx_st10_clk == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_tx_st10_clk_non_std == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_tx_st11_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_tx_st11_clk_non_std == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_tx_st12_clk == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_tx_st12_clk_non_std == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_tx_st13_clk == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_tx_st13_clk_non_std == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_tx_st14_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_tx_st14_clk_non_std == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_tx_st15_clk == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_tx_st15_clk_non_std == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_tx_st1_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_tx_st1_clk_non_std == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_tx_st2_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_tx_st2_clk_non_std == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_tx_st3_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_tx_st3_clk_non_std == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_tx_st4_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_tx_st4_clk_non_std == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_tx_st5_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_tx_st5_clk_non_std == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_tx_st6_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_tx_st6_clk_non_std == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_tx_st7_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_tx_st7_clk_non_std == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_tx_st8_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_tx_st8_clk_non_std == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_tx_st9_clk == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_eth_tx_st9_clk_non_std == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.powermode_freq_hz_global_avmm_clk == 37'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.speed_grade == DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.sys_pll0_div1_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.sys_pll0_div2_clk_hz == 37'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.sys_pll1_div1_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.sys_pll1_div2_clk_hz == 37'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.sys_pll2_div1_clk_hz == 37'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.sys_pll2_div2_clk_hz == 37'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.topology == UX16E400GPTP_XX_DISABLED_XX_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.transfer_clk0_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.transfer_clk10_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.transfer_clk11_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.transfer_clk12_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.transfer_clk13_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.transfer_clk14_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.transfer_clk15_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.transfer_clk1_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.transfer_clk2_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.transfer_clk3_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.transfer_clk4_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.transfer_clk5_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.transfer_clk6_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.transfer_clk7_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.transfer_clk8_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.transfer_clk9_hz == 37'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.use_bk0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.use_bk1 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux0_return_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux0_rx_user_clk_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux0_rxword_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux0_tx_user_clk1_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux0_tx_user_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux0_txword_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux10_return_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux10_rx_user_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux10_rxword_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux10_tx_user_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux10_tx_user_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux10_txword_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux11_return_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux11_rx_user_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux11_rxword_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux11_tx_user_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux11_tx_user_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux11_txword_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux12_return_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux12_rx_user_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux12_rxword_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux12_tx_user_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux12_tx_user_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux12_txword_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux13_return_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux13_rx_user_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux13_rxword_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux13_tx_user_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux13_tx_user_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux13_txword_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux14_return_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux14_rx_user_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux14_rxword_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux14_tx_user_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux14_tx_user_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux14_txword_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux15_return_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux15_rx_user_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux15_rxword_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux15_tx_user_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux15_tx_user_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux15_txword_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux1_return_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux1_rx_user_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux1_rxword_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux1_tx_user_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux1_tx_user_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux1_txword_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux2_return_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux2_rx_user_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux2_rxword_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux2_tx_user_clk1_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux2_tx_user_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux2_txword_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux3_return_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux3_rx_user_clk_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux3_rxword_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux3_tx_user_clk1_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux3_tx_user_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux3_txword_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux4_return_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux4_rx_user_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux4_rxword_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux4_tx_user_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux4_tx_user_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux4_txword_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux5_return_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux5_rx_user_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux5_rxword_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux5_tx_user_clk1_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux5_tx_user_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux5_txword_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux6_return_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux6_rx_user_clk_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux6_rxword_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux6_tx_user_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux6_tx_user_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux6_txword_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux7_return_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux7_rx_user_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux7_rxword_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux7_tx_user_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux7_tx_user_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux7_txword_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux8_return_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux8_rx_user_clk_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux8_rxword_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux8_tx_user_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux8_tx_user_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux8_txword_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux9_return_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux9_rx_user_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux9_rxword_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux9_tx_user_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux9_tx_user_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.ux9_txword_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_st0_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_st10_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_st11_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_st12_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_st13_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_st14_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_st15_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_st1_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_st2_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_st3_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_st4_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_st5_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_st6_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_st7_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_st8_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_st9_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_user_st0_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_user_st0_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_user_st10_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_user_st10_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_user_st11_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_user_st11_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_user_st12_clk1_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_user_st12_clk2_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_user_st13_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_user_st13_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_user_st14_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_user_st14_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_user_st15_clk1_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_user_st15_clk2_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_user_st1_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_user_st1_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_user_st2_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_user_st2_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_user_st3_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_user_st3_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_user_st4_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_user_st4_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_user_st5_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_user_st5_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_user_st6_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_user_st6_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_user_st7_clk1_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_user_st7_clk2_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_user_st8_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_user_st8_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_user_st9_clk1_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_rx_user_st9_clk2_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_select_112e4x0 == XCVR_SELECT_112E4X0_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_select_112e4x1 == XCVR_SELECT_112E4X1_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_select_112e4x2 == XCVR_SELECT_112E4X2_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_select_112e4x3 == XCVR_SELECT_112E4X3_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_select_25e4x0 == XCVR_SELECT_25E4X0_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_select_25e4x1 == XCVR_SELECT_25E4X1_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_select_25e4x10 == XCVR_SELECT_25E4X10_E4UX5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_select_25e4x11 == XCVR_SELECT_25E4X11_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_select_25e4x12 == XCVR_SELECT_25E4X12_E4UX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_select_25e4x13 == XCVR_SELECT_25E4X13_E4UX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_select_25e4x14 == XCVR_SELECT_25E4X14_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_select_25e4x15 == XCVR_SELECT_25E4X15_E4UX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_select_25e4x2 == XCVR_SELECT_25E4X2_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_select_25e4x3 == XCVR_SELECT_25E4X3_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_select_25e4x4 == XCVR_SELECT_25E4X4_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_select_25e4x5 == XCVR_SELECT_25E4X5_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_select_25e4x6 == XCVR_SELECT_25E4X6_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_select_25e4x7 == XCVR_SELECT_25E4X7_E4UX8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_select_25e4x8 == XCVR_SELECT_25E4X8_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_select_25e4x9 == XCVR_SELECT_25E4X9_E4UX6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_select_56e4x0 == XCVR_SELECT_56E4X0_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_select_56e4x1 == XCVR_SELECT_56E4X1_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_select_56e4x2 == XCVR_SELECT_56E4X2_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_select_56e4x3 == XCVR_SELECT_56E4X3_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_select_56e4x4 == XCVR_SELECT_56E4X4_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_select_56e4x5 == XCVR_SELECT_56E4X5_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_select_56e4x6 == XCVR_SELECT_56E4X6_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_select_56e4x7 == XCVR_SELECT_56E4X7_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_st0_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_st10_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_st11_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_st12_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_st13_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_st14_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_st15_clk_hz == 37'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_st1_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_st2_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_st3_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_st4_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_st5_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_st6_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_st7_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_st8_clk_hz == 37'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_st9_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_user_st0_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_user_st0_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_user_st10_clk1_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_user_st10_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_user_st11_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_user_st11_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_user_st12_clk1_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_user_st12_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_user_st13_clk1_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_user_st13_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_user_st14_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_user_st14_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_user_st15_clk1_hz == 37'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_user_st15_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_user_st1_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_user_st1_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_user_st2_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_user_st2_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_user_st3_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_user_st3_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_user_st4_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_user_st4_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_user_st5_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_user_st5_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_user_st6_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_user_st6_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_user_st7_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_user_st7_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_user_st8_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_user_st8_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_user_st9_clk1_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.xcvr_tx_user_st9_clk2_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_aib2_rx_st_clk_en == E400G_100G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_aib2_tx_st_clk_en == E400G_100G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_aib3_rx_st_clk_en == E400G_100G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_aib3_tx_st_clk_en == E400G_100G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_duplex_mode == E400G_100G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_fec_mode == E400G_100G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_fec_spec == E400G_100G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_mac_mode == E400G_100G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_rx_excvr_gb_ratio_mode == E400G_100G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_rx_excvr_if_fifo_mode == E400G_100G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_rx_fec_enable == E400G_100G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_rx_pcs_mode == E400G_100G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_rx_primary_use == E400G_100G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_speed_map == E400G_100G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_sup_mode == E400G_100G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_sys_clk_src == E400G_100G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_tx_excvr_gb_ratio_mode == E400G_100G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_tx_excvr_if_fifo_mode == E400G_100G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_tx_fec_enable == E400G_100G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_tx_pcs_mode == E400G_100G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_tx_primary_use == E400G_100G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.e400g_100g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.cfg_frac == FRAC_LN4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.cfg_frac == FRAC_LN4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.cfg_frac == FRAC_LN4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_aib2_rx_st_clk_en == E400G_100G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_aib2_tx_st_clk_en == E400G_100G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_aib3_rx_st_clk_en == E400G_100G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_aib3_tx_st_clk_en == E400G_100G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_duplex_mode == E400G_100G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_fec_mode == E400G_100G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_fec_spec == E400G_100G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_mac_mode == E400G_100G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_rx_excvr_gb_ratio_mode == E400G_100G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_rx_excvr_if_fifo_mode == E400G_100G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_rx_fec_enable == E400G_100G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_rx_pcs_mode == E400G_100G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_rx_primary_use == E400G_100G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_speed_map == E400G_100G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_sup_mode == E400G_100G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_sys_clk_src == E400G_100G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_tx_excvr_gb_ratio_mode == E400G_100G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_tx_excvr_if_fifo_mode == E400G_100G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_tx_fec_enable == E400G_100G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_tx_pcs_mode == E400G_100G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_tx_primary_use == E400G_100G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.e400g_100g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.cfg_frac == FRAC_LN4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.cfg_frac == FRAC_LN4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.cfg_frac == FRAC_LN4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch12.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_aib2_rx_st_clk_en == E400G_100G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_aib2_tx_st_clk_en == E400G_100G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_aib3_rx_st_clk_en == E400G_100G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_aib3_tx_st_clk_en == E400G_100G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_duplex_mode == E400G_100G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_fec_mode == E400G_100G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_fec_spec == E400G_100G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_mac_mode == E400G_100G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_rx_excvr_gb_ratio_mode == E400G_100G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_rx_excvr_if_fifo_mode == E400G_100G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_rx_fec_enable == E400G_100G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_rx_pcs_mode == E400G_100G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_rx_primary_use == E400G_100G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_speed_map == E400G_100G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_sup_mode == E400G_100G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_sys_clk_src == E400G_100G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_tx_excvr_gb_ratio_mode == E400G_100G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_tx_excvr_if_fifo_mode == E400G_100G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_tx_fec_enable == E400G_100G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_tx_pcs_mode == E400G_100G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_tx_primary_use == E400G_100G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.e400g_100g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.cfg_frac == FRAC_LN4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.cfg_frac == FRAC_LN4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.cfg_frac == FRAC_LN4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch4.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_aib2_rx_st_clk_en == E400G_100G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_aib2_tx_st_clk_en == E400G_100G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_aib3_rx_st_clk_en == E400G_100G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_aib3_tx_st_clk_en == E400G_100G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_duplex_mode == E400G_100G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_fec_mode == E400G_100G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_fec_spec == E400G_100G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_mac_mode == E400G_100G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_rx_excvr_gb_ratio_mode == E400G_100G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_rx_excvr_if_fifo_mode == E400G_100G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_rx_fec_enable == E400G_100G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_rx_pcs_mode == E400G_100G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_rx_primary_use == E400G_100G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_speed_map == E400G_100G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_sup_mode == E400G_100G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_sys_clk_src == E400G_100G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_tx_excvr_gb_ratio_mode == E400G_100G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_tx_excvr_if_fifo_mode == E400G_100G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_tx_fec_enable == E400G_100G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_tx_pcs_mode == E400G_100G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_tx_primary_use == E400G_100G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.e400g_100g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.cfg_frac == FRAC_LN4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.cfg_frac == FRAC_LN4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.cfg_frac == FRAC_LN4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e100g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_aib2_rx_st_clk_en == E400G_200G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_aib2_tx_st_clk_en == E400G_200G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_aib3_rx_st_clk_en == E400G_200G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_aib3_tx_st_clk_en == E400G_200G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_duplex_mode == E400G_200G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_fec_mode == E400G_200G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_fec_spec == E400G_200G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_mac_mode == E400G_200G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_rx_excvr_gb_ratio_mode == E400G_200G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_rx_excvr_if_fifo_mode == E400G_200G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_rx_fec_enable == E400G_200G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_rx_pcs_mode == E400G_200G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_rx_primary_use == E400G_200G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_speed_map == E400G_200G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_sup_mode == E400G_200G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_sys_clk_src == E400G_200G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_tx_excvr_gb_ratio_mode == E400G_200G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_tx_excvr_if_fifo_mode == E400G_200G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_tx_fec_enable == E400G_200G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_tx_pcs_mode == E400G_200G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_tx_primary_use == E400G_200G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.e400g_200g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.cfg_frac == FRAC_LN8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.cfg_frac == FRAC_LN8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.cfg_frac == FRAC_LN8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.cfg_frac == FRAC_LN8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.cfg_frac == FRAC_LN8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.cfg_frac == FRAC_LN8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.cfg_frac == FRAC_LN8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_aib2_rx_st_clk_en == E400G_200G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_aib2_tx_st_clk_en == E400G_200G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_aib3_rx_st_clk_en == E400G_200G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_aib3_tx_st_clk_en == E400G_200G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_duplex_mode == E400G_200G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_fec_mode == E400G_200G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_fec_spec == E400G_200G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_mac_mode == E400G_200G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_rx_excvr_gb_ratio_mode == E400G_200G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_rx_excvr_if_fifo_mode == E400G_200G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_rx_fec_enable == E400G_200G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_rx_pcs_mode == E400G_200G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_rx_primary_use == E400G_200G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_speed_map == E400G_200G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_sup_mode == E400G_200G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_sys_clk_src == E400G_200G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_tx_excvr_gb_ratio_mode == E400G_200G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_tx_excvr_if_fifo_mode == E400G_200G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_tx_fec_enable == E400G_200G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_tx_pcs_mode == E400G_200G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_tx_primary_use == E400G_200G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.e400g_200g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.cfg_frac == FRAC_LN8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.cfg_frac == FRAC_LN8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.cfg_frac == FRAC_LN8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.cfg_frac == FRAC_LN8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.cfg_frac == FRAC_LN8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.cfg_frac == FRAC_LN8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.cfg_frac == FRAC_LN8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e200g_reg_ch8.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_aib2_rx_st_clk_en == E400G_25G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_aib2_tx_st_clk_en == E400G_25G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_aib3_rx_st_clk_en == E400G_25G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_aib3_tx_st_clk_en == E400G_25G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_duplex_mode == E400G_25G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_fec_mode == E400G_25G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_fec_spec == E400G_25G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_mac_mode == E400G_25G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_rx_excvr_gb_ratio_mode == E400G_25G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_rx_excvr_if_fifo_mode == E400G_25G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_rx_fec_enable == E400G_25G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_rx_pcs_mode == E400G_25G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_rx_primary_use == E400G_25G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_speed_map == E400G_25G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_sup_mode == E400G_25G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_sys_clk_src == E400G_25G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_tx_excvr_gb_ratio_mode == E400G_25G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_tx_excvr_if_fifo_mode == E400G_25G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_tx_fec_enable == E400G_25G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_tx_pcs_mode == E400G_25G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_tx_primary_use == E400G_25G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.e400g_25g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN1111
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_aib2_rx_st_clk_en == E400G_25G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_aib2_tx_st_clk_en == E400G_25G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_aib3_rx_st_clk_en == E400G_25G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_aib3_tx_st_clk_en == E400G_25G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_duplex_mode == E400G_25G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_fec_mode == E400G_25G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_fec_spec == E400G_25G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_mac_mode == E400G_25G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_rx_excvr_gb_ratio_mode == E400G_25G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_rx_excvr_if_fifo_mode == E400G_25G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_rx_fec_enable == E400G_25G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_rx_pcs_mode == E400G_25G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_rx_primary_use == E400G_25G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_speed_map == E400G_25G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_sup_mode == E400G_25G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_sys_clk_src == E400G_25G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_tx_excvr_gb_ratio_mode == E400G_25G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_tx_excvr_if_fifo_mode == E400G_25G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_tx_fec_enable == E400G_25G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_tx_pcs_mode == E400G_25G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_tx_primary_use == E400G_25G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.e400g_25g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN1111
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch1.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_aib2_rx_st_clk_en == E400G_25G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_aib2_tx_st_clk_en == E400G_25G_AIB2_TX_ST_CLK_EN_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_aib3_rx_st_clk_en == E400G_25G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_aib3_tx_st_clk_en == E400G_25G_AIB3_TX_ST_CLK_EN_TX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_duplex_mode == E400G_25G_DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_fec_mode == E400G_25G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_fec_spec == E400G_25G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_mac_mode == E400G_25G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_rx_excvr_gb_ratio_mode == E400G_25G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_rx_excvr_if_fifo_mode == E400G_25G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_rx_fec_enable == E400G_25G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_rx_pcs_mode == E400G_25G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_rx_primary_use == E400G_25G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_speed_map == E400G_25G_SPEED_MAP_MAP_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_sup_mode == E400G_25G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_sys_clk_src == E400G_25G_SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_tx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_tx_excvr_gb_ratio_mode == E400G_25G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_tx_excvr_if_fifo_mode == E400G_25G_TX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_tx_fec_enable == E400G_25G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_tx_pcs_mode == E400G_25G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_tx_primary_use == E400G_25G_TX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.e400g_25g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_TX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.bk_return_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN1111
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXUSER1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_MAP_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvr_sel == UX_SEL_25G_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_aib2_rx_st_clk_en == E400G_25G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_aib2_tx_st_clk_en == E400G_25G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_aib3_rx_st_clk_en == E400G_25G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_aib3_tx_st_clk_en == E400G_25G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_duplex_mode == E400G_25G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_fec_mode == E400G_25G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_fec_spec == E400G_25G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_mac_mode == E400G_25G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_rx_excvr_gb_ratio_mode == E400G_25G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_rx_excvr_if_fifo_mode == E400G_25G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_rx_fec_enable == E400G_25G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_rx_pcs_mode == E400G_25G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_rx_primary_use == E400G_25G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_speed_map == E400G_25G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_sup_mode == E400G_25G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_sys_clk_src == E400G_25G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_tx_excvr_gb_ratio_mode == E400G_25G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_tx_excvr_if_fifo_mode == E400G_25G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_tx_fec_enable == E400G_25G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_tx_pcs_mode == E400G_25G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_tx_primary_use == E400G_25G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.e400g_25g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN1111
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch11.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_aib2_rx_st_clk_en == E400G_25G_AIB2_RX_ST_CLK_EN_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_aib2_tx_st_clk_en == E400G_25G_AIB2_TX_ST_CLK_EN_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_aib3_rx_st_clk_en == E400G_25G_AIB3_RX_ST_CLK_EN_RX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_aib3_tx_st_clk_en == E400G_25G_AIB3_TX_ST_CLK_EN_TX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_duplex_mode == E400G_25G_DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_fec_mode == E400G_25G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_fec_spec == E400G_25G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_mac_mode == E400G_25G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_rx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_rx_excvr_gb_ratio_mode == E400G_25G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_rx_excvr_if_fifo_mode == E400G_25G_RX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_rx_fec_enable == E400G_25G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_rx_pcs_mode == E400G_25G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_rx_primary_use == E400G_25G_RX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_speed_map == E400G_25G_SPEED_MAP_MAP_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_sup_mode == E400G_25G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_sys_clk_src == E400G_25G_SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_tx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_tx_excvr_gb_ratio_mode == E400G_25G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_tx_excvr_if_fifo_mode == E400G_25G_TX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_tx_fec_enable == E400G_25G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_tx_pcs_mode == E400G_25G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_tx_primary_use == E400G_25G_TX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.e400g_25g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_RX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_TX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.bk_return_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN1111
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXUSER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXUSER1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_MAP_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvr_sel == UX_SEL_25G_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_aib2_rx_st_clk_en == E400G_25G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_aib2_tx_st_clk_en == E400G_25G_AIB2_TX_ST_CLK_EN_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_aib3_rx_st_clk_en == E400G_25G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_aib3_tx_st_clk_en == E400G_25G_AIB3_TX_ST_CLK_EN_TX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_duplex_mode == E400G_25G_DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_fec_mode == E400G_25G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_fec_spec == E400G_25G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_mac_mode == E400G_25G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_rx_excvr_gb_ratio_mode == E400G_25G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_rx_excvr_if_fifo_mode == E400G_25G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_rx_fec_enable == E400G_25G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_rx_pcs_mode == E400G_25G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_rx_primary_use == E400G_25G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_speed_map == E400G_25G_SPEED_MAP_MAP_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_sup_mode == E400G_25G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_sys_clk_src == E400G_25G_SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_tx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_tx_excvr_gb_ratio_mode == E400G_25G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_tx_excvr_if_fifo_mode == E400G_25G_TX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_tx_fec_enable == E400G_25G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_tx_pcs_mode == E400G_25G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_tx_primary_use == E400G_25G_TX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.e400g_25g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_TX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.bk_return_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN1111
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXUSER1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_MAP_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvr_sel == UX_SEL_25G_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch13.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_aib2_rx_st_clk_en == E400G_25G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_aib2_tx_st_clk_en == E400G_25G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_aib3_rx_st_clk_en == E400G_25G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_aib3_tx_st_clk_en == E400G_25G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_duplex_mode == E400G_25G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_fec_mode == E400G_25G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_fec_spec == E400G_25G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_mac_mode == E400G_25G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_rx_excvr_gb_ratio_mode == E400G_25G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_rx_excvr_if_fifo_mode == E400G_25G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_rx_fec_enable == E400G_25G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_rx_pcs_mode == E400G_25G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_rx_primary_use == E400G_25G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_speed_map == E400G_25G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_sup_mode == E400G_25G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_sys_clk_src == E400G_25G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_tx_excvr_gb_ratio_mode == E400G_25G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_tx_excvr_if_fifo_mode == E400G_25G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_tx_fec_enable == E400G_25G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_tx_pcs_mode == E400G_25G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_tx_primary_use == E400G_25G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.e400g_25g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN1111
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_aib2_rx_st_clk_en == E400G_25G_AIB2_RX_ST_CLK_EN_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_aib2_tx_st_clk_en == E400G_25G_AIB2_TX_ST_CLK_EN_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_aib3_rx_st_clk_en == E400G_25G_AIB3_RX_ST_CLK_EN_RX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_aib3_tx_st_clk_en == E400G_25G_AIB3_TX_ST_CLK_EN_TX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_duplex_mode == E400G_25G_DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_fec_mode == E400G_25G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_fec_spec == E400G_25G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_mac_mode == E400G_25G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_rx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_rx_excvr_gb_ratio_mode == E400G_25G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_rx_excvr_if_fifo_mode == E400G_25G_RX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_rx_fec_enable == E400G_25G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_rx_pcs_mode == E400G_25G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_rx_primary_use == E400G_25G_RX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_speed_map == E400G_25G_SPEED_MAP_MAP_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_sup_mode == E400G_25G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_sys_clk_src == E400G_25G_SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_tx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_tx_excvr_gb_ratio_mode == E400G_25G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_tx_excvr_if_fifo_mode == E400G_25G_TX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_tx_fec_enable == E400G_25G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_tx_pcs_mode == E400G_25G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_tx_primary_use == E400G_25G_TX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.e400g_25g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_RX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_TX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.bk_return_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN1111
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXUSER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXUSER1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_MAP_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvr_sel == UX_SEL_25G_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch15.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_aib2_rx_st_clk_en == E400G_25G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_aib2_tx_st_clk_en == E400G_25G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_aib3_rx_st_clk_en == E400G_25G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_aib3_tx_st_clk_en == E400G_25G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_duplex_mode == E400G_25G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_fec_mode == E400G_25G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_fec_spec == E400G_25G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_mac_mode == E400G_25G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_rx_excvr_gb_ratio_mode == E400G_25G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_rx_excvr_if_fifo_mode == E400G_25G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_rx_fec_enable == E400G_25G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_rx_pcs_mode == E400G_25G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_rx_primary_use == E400G_25G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_speed_map == E400G_25G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_sup_mode == E400G_25G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_sys_clk_src == E400G_25G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_tx_excvr_gb_ratio_mode == E400G_25G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_tx_excvr_if_fifo_mode == E400G_25G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_tx_fec_enable == E400G_25G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_tx_pcs_mode == E400G_25G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_tx_primary_use == E400G_25G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.e400g_25g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN1111
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_aib2_rx_st_clk_en == E400G_25G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_aib2_tx_st_clk_en == E400G_25G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_aib3_rx_st_clk_en == E400G_25G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_aib3_tx_st_clk_en == E400G_25G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_duplex_mode == E400G_25G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_fec_mode == E400G_25G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_fec_spec == E400G_25G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_mac_mode == E400G_25G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_rx_excvr_gb_ratio_mode == E400G_25G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_rx_excvr_if_fifo_mode == E400G_25G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_rx_fec_enable == E400G_25G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_rx_pcs_mode == E400G_25G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_rx_primary_use == E400G_25G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_speed_map == E400G_25G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_sup_mode == E400G_25G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_sys_clk_src == E400G_25G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_tx_excvr_gb_ratio_mode == E400G_25G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_tx_excvr_if_fifo_mode == E400G_25G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_tx_fec_enable == E400G_25G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_tx_pcs_mode == E400G_25G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_tx_primary_use == E400G_25G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.e400g_25g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN1111
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch3.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_aib2_rx_st_clk_en == E400G_25G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_aib2_tx_st_clk_en == E400G_25G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_aib3_rx_st_clk_en == E400G_25G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_aib3_tx_st_clk_en == E400G_25G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_duplex_mode == E400G_25G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_fec_mode == E400G_25G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_fec_spec == E400G_25G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_mac_mode == E400G_25G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_rx_excvr_gb_ratio_mode == E400G_25G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_rx_excvr_if_fifo_mode == E400G_25G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_rx_fec_enable == E400G_25G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_rx_pcs_mode == E400G_25G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_rx_primary_use == E400G_25G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_speed_map == E400G_25G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_sup_mode == E400G_25G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_sys_clk_src == E400G_25G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_tx_excvr_gb_ratio_mode == E400G_25G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_tx_excvr_if_fifo_mode == E400G_25G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_tx_fec_enable == E400G_25G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_tx_pcs_mode == E400G_25G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_tx_primary_use == E400G_25G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.e400g_25g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN1111
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_aib2_rx_st_clk_en == E400G_25G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_aib2_tx_st_clk_en == E400G_25G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_aib3_rx_st_clk_en == E400G_25G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_aib3_tx_st_clk_en == E400G_25G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_duplex_mode == E400G_25G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_fec_mode == E400G_25G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_fec_spec == E400G_25G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_mac_mode == E400G_25G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_rx_excvr_gb_ratio_mode == E400G_25G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_rx_excvr_if_fifo_mode == E400G_25G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_rx_fec_enable == E400G_25G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_rx_pcs_mode == E400G_25G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_rx_primary_use == E400G_25G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_speed_map == E400G_25G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_sup_mode == E400G_25G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_sys_clk_src == E400G_25G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_tx_excvr_gb_ratio_mode == E400G_25G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_tx_excvr_if_fifo_mode == E400G_25G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_tx_fec_enable == E400G_25G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_tx_pcs_mode == E400G_25G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_tx_primary_use == E400G_25G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.e400g_25g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN1111
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch5.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_aib2_rx_st_clk_en == E400G_25G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_aib2_tx_st_clk_en == E400G_25G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_aib3_rx_st_clk_en == E400G_25G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_aib3_tx_st_clk_en == E400G_25G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_duplex_mode == E400G_25G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_fec_mode == E400G_25G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_fec_spec == E400G_25G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_mac_mode == E400G_25G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_rx_excvr_gb_ratio_mode == E400G_25G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_rx_excvr_if_fifo_mode == E400G_25G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_rx_fec_enable == E400G_25G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_rx_pcs_mode == E400G_25G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_rx_primary_use == E400G_25G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_speed_map == E400G_25G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_sup_mode == E400G_25G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_sys_clk_src == E400G_25G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_tx_excvr_gb_ratio_mode == E400G_25G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_tx_excvr_if_fifo_mode == E400G_25G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_tx_fec_enable == E400G_25G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_tx_pcs_mode == E400G_25G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_tx_primary_use == E400G_25G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.e400g_25g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN1111
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_aib2_rx_st_clk_en == E400G_25G_AIB2_RX_ST_CLK_EN_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_aib2_tx_st_clk_en == E400G_25G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_aib3_rx_st_clk_en == E400G_25G_AIB3_RX_ST_CLK_EN_RX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_aib3_tx_st_clk_en == E400G_25G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_duplex_mode == E400G_25G_DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_fec_mode == E400G_25G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_fec_spec == E400G_25G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_mac_mode == E400G_25G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_rx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_rx_excvr_gb_ratio_mode == E400G_25G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_rx_excvr_if_fifo_mode == E400G_25G_RX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_rx_fec_enable == E400G_25G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_rx_pcs_mode == E400G_25G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_rx_primary_use == E400G_25G_RX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_speed_map == E400G_25G_SPEED_MAP_MAP_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_sup_mode == E400G_25G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_sys_clk_src == E400G_25G_SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_tx_excvr_gb_ratio_mode == E400G_25G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_tx_excvr_if_fifo_mode == E400G_25G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_tx_fec_enable == E400G_25G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_tx_pcs_mode == E400G_25G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_tx_primary_use == E400G_25G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.e400g_25g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_RX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN1111
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXUSER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_MAP_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvr_sel == UX_SEL_25G_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch7.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_aib2_rx_st_clk_en == E400G_25G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_aib2_tx_st_clk_en == E400G_25G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_aib3_rx_st_clk_en == E400G_25G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_aib3_tx_st_clk_en == E400G_25G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_duplex_mode == E400G_25G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_fec_mode == E400G_25G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_fec_spec == E400G_25G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_mac_mode == E400G_25G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_rx_excvr_gb_ratio_mode == E400G_25G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_rx_excvr_if_fifo_mode == E400G_25G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_rx_fec_enable == E400G_25G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_rx_pcs_mode == E400G_25G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_rx_primary_use == E400G_25G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_speed_map == E400G_25G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_sup_mode == E400G_25G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_sys_clk_src == E400G_25G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_tx_excvr_gb_ratio_mode == E400G_25G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_tx_excvr_if_fifo_mode == E400G_25G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_tx_fec_enable == E400G_25G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_tx_pcs_mode == E400G_25G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_tx_primary_use == E400G_25G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.e400g_25g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN1111
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_aib2_rx_st_clk_en == E400G_25G_AIB2_RX_ST_CLK_EN_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_aib2_tx_st_clk_en == E400G_25G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_aib3_rx_st_clk_en == E400G_25G_AIB3_RX_ST_CLK_EN_RX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_aib3_tx_st_clk_en == E400G_25G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_duplex_mode == E400G_25G_DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_fec_mode == E400G_25G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_fec_spec == E400G_25G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_mac_mode == E400G_25G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_rx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_rx_excvr_gb_ratio_mode == E400G_25G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_rx_excvr_if_fifo_mode == E400G_25G_RX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_rx_fec_enable == E400G_25G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_rx_pcs_mode == E400G_25G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_rx_primary_use == E400G_25G_RX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_speed_map == E400G_25G_SPEED_MAP_MAP_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_sup_mode == E400G_25G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_sys_clk_src == E400G_25G_SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_tx_excvr_gb_ratio_mode == E400G_25G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_tx_excvr_if_fifo_mode == E400G_25G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_tx_fec_enable == E400G_25G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_tx_pcs_mode == E400G_25G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_tx_primary_use == E400G_25G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.e400g_25g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_RX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN1111
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_PLL1_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXUSER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_MAP_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvr_sel == UX_SEL_25G_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e25g_reg_ch9.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_aib2_rx_st_clk_en == E400G_400G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_aib2_tx_st_clk_en == E400G_400G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_aib3_rx_st_clk_en == E400G_400G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_aib3_tx_st_clk_en == E400G_400G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_duplex_mode == E400G_400G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_fec_mode == E400G_400G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_fec_spec == E400G_400G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_mac_mode == E400G_400G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_rx_excvr_gb_ratio_mode == E400G_400G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_rx_excvr_if_fifo_mode == E400G_400G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_rx_fec_enable == E400G_400G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_rx_pcs_mode == E400G_400G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_rx_primary_use == E400G_400G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_speed_map == E400G_400G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_sup_mode == E400G_400G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_sys_clk_src == E400G_400G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_tx_excvr_gb_ratio_mode == E400G_400G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_tx_excvr_if_fifo_mode == E400G_400G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_tx_fec_enable == E400G_400G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_tx_pcs_mode == E400G_400G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_tx_primary_use == E400G_400G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.e400g_400g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.cfg_frac == FRAC_LN16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.cfg_frac == FRAC_LN16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s10.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.cfg_frac == FRAC_LN16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s11.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.cfg_frac == FRAC_LN16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s12.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.cfg_frac == FRAC_LN16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s13.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.cfg_frac == FRAC_LN16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s14.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.cfg_frac == FRAC_LN16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s15.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.cfg_frac == FRAC_LN16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s2.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.cfg_frac == FRAC_LN16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s3.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.cfg_frac == FRAC_LN16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s4.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.cfg_frac == FRAC_LN16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s5.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.cfg_frac == FRAC_LN16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s6.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.cfg_frac == FRAC_LN16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s7.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.cfg_frac == FRAC_LN16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s8.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.cfg_frac == FRAC_LN16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e400g_reg_ch0.gdr_lphy_e25g_reg_base_s9.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_aib2_rx_st_clk_en == E400G_50G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_aib2_tx_st_clk_en == E400G_50G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_aib3_rx_st_clk_en == E400G_50G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_aib3_tx_st_clk_en == E400G_50G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_duplex_mode == E400G_50G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_fec_mode == E400G_50G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_fec_spec == E400G_50G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_mac_mode == E400G_50G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_rx_excvr_gb_ratio_mode == E400G_50G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_rx_excvr_if_fifo_mode == E400G_50G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_rx_fec_enable == E400G_50G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_rx_pcs_mode == E400G_50G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_rx_primary_use == E400G_50G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_speed_map == E400G_50G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_sup_mode == E400G_50G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_sys_clk_src == E400G_50G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_tx_excvr_gb_ratio_mode == E400G_50G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_tx_excvr_if_fifo_mode == E400G_50G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_tx_fec_enable == E400G_50G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_tx_pcs_mode == E400G_50G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_tx_primary_use == E400G_50G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.e400g_50g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.cfg_frac == FRAC_LN112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch0.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_aib2_rx_st_clk_en == E400G_50G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_aib2_tx_st_clk_en == E400G_50G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_aib3_rx_st_clk_en == E400G_50G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_aib3_tx_st_clk_en == E400G_50G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_duplex_mode == E400G_50G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_fec_mode == E400G_50G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_fec_spec == E400G_50G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_mac_mode == E400G_50G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_rx_excvr_gb_ratio_mode == E400G_50G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_rx_excvr_if_fifo_mode == E400G_50G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_rx_fec_enable == E400G_50G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_rx_pcs_mode == E400G_50G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_rx_primary_use == E400G_50G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_speed_map == E400G_50G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_sup_mode == E400G_50G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_sys_clk_src == E400G_50G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_tx_excvr_gb_ratio_mode == E400G_50G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_tx_excvr_if_fifo_mode == E400G_50G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_tx_fec_enable == E400G_50G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_tx_pcs_mode == E400G_50G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_tx_primary_use == E400G_50G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.e400g_50g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.cfg_frac == FRAC_LN112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch10.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_aib2_rx_st_clk_en == E400G_50G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_aib2_tx_st_clk_en == E400G_50G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_aib3_rx_st_clk_en == E400G_50G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_aib3_tx_st_clk_en == E400G_50G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_duplex_mode == E400G_50G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_fec_mode == E400G_50G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_fec_spec == E400G_50G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_mac_mode == E400G_50G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_rx_excvr_gb_ratio_mode == E400G_50G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_rx_excvr_if_fifo_mode == E400G_50G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_rx_fec_enable == E400G_50G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_rx_pcs_mode == E400G_50G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_rx_primary_use == E400G_50G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_speed_map == E400G_50G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_sup_mode == E400G_50G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_sys_clk_src == E400G_50G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_tx_excvr_gb_ratio_mode == E400G_50G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_tx_excvr_if_fifo_mode == E400G_50G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_tx_fec_enable == E400G_50G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_tx_pcs_mode == E400G_50G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_tx_primary_use == E400G_50G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.e400g_50g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.cfg_frac == FRAC_LN112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch12.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_aib2_rx_st_clk_en == E400G_50G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_aib2_tx_st_clk_en == E400G_50G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_aib3_rx_st_clk_en == E400G_50G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_aib3_tx_st_clk_en == E400G_50G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_duplex_mode == E400G_50G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_fec_mode == E400G_50G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_fec_spec == E400G_50G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_mac_mode == E400G_50G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_rx_excvr_gb_ratio_mode == E400G_50G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_rx_excvr_if_fifo_mode == E400G_50G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_rx_fec_enable == E400G_50G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_rx_pcs_mode == E400G_50G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_rx_primary_use == E400G_50G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_speed_map == E400G_50G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_sup_mode == E400G_50G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_sys_clk_src == E400G_50G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_tx_excvr_gb_ratio_mode == E400G_50G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_tx_excvr_if_fifo_mode == E400G_50G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_tx_fec_enable == E400G_50G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_tx_pcs_mode == E400G_50G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_tx_primary_use == E400G_50G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.e400g_50g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.cfg_frac == FRAC_LN112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch14.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_aib2_rx_st_clk_en == E400G_50G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_aib2_tx_st_clk_en == E400G_50G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_aib3_rx_st_clk_en == E400G_50G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_aib3_tx_st_clk_en == E400G_50G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_duplex_mode == E400G_50G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_fec_mode == E400G_50G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_fec_spec == E400G_50G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_mac_mode == E400G_50G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_rx_excvr_gb_ratio_mode == E400G_50G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_rx_excvr_if_fifo_mode == E400G_50G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_rx_fec_enable == E400G_50G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_rx_pcs_mode == E400G_50G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_rx_primary_use == E400G_50G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_speed_map == E400G_50G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_sup_mode == E400G_50G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_sys_clk_src == E400G_50G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_tx_excvr_gb_ratio_mode == E400G_50G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_tx_excvr_if_fifo_mode == E400G_50G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_tx_fec_enable == E400G_50G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_tx_pcs_mode == E400G_50G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_tx_primary_use == E400G_50G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.e400g_50g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.cfg_frac == FRAC_LN112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch2.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_aib2_rx_st_clk_en == E400G_50G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_aib2_tx_st_clk_en == E400G_50G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_aib3_rx_st_clk_en == E400G_50G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_aib3_tx_st_clk_en == E400G_50G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_duplex_mode == E400G_50G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_fec_mode == E400G_50G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_fec_spec == E400G_50G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_mac_mode == E400G_50G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_rx_excvr_gb_ratio_mode == E400G_50G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_rx_excvr_if_fifo_mode == E400G_50G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_rx_fec_enable == E400G_50G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_rx_pcs_mode == E400G_50G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_rx_primary_use == E400G_50G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_speed_map == E400G_50G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_sup_mode == E400G_50G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_sys_clk_src == E400G_50G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_tx_excvr_gb_ratio_mode == E400G_50G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_tx_excvr_if_fifo_mode == E400G_50G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_tx_fec_enable == E400G_50G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_tx_pcs_mode == E400G_50G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_tx_primary_use == E400G_50G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.e400g_50g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.cfg_frac == FRAC_LN112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch4.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_aib2_rx_st_clk_en == E400G_50G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_aib2_tx_st_clk_en == E400G_50G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_aib3_rx_st_clk_en == E400G_50G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_aib3_tx_st_clk_en == E400G_50G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_duplex_mode == E400G_50G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_fec_mode == E400G_50G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_fec_spec == E400G_50G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_mac_mode == E400G_50G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_rx_excvr_gb_ratio_mode == E400G_50G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_rx_excvr_if_fifo_mode == E400G_50G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_rx_fec_enable == E400G_50G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_rx_pcs_mode == E400G_50G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_rx_primary_use == E400G_50G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_speed_map == E400G_50G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_sup_mode == E400G_50G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_sys_clk_src == E400G_50G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_tx_excvr_gb_ratio_mode == E400G_50G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_tx_excvr_if_fifo_mode == E400G_50G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_tx_fec_enable == E400G_50G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_tx_pcs_mode == E400G_50G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_tx_primary_use == E400G_50G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.e400g_50g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.cfg_frac == FRAC_LN112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch6.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_aib2_rx_st_clk_en == E400G_50G_AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_aib2_tx_st_clk_en == E400G_50G_AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_aib3_rx_st_clk_en == E400G_50G_AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_aib3_tx_st_clk_en == E400G_50G_AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_duplex_mode == E400G_50G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_fec_mode == E400G_50G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_fec_spec == E400G_50G_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_mac_mode == E400G_50G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_rx_excvr_gb_ratio_mode == E400G_50G_RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_rx_excvr_if_fifo_mode == E400G_50G_RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_rx_fec_enable == E400G_50G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_rx_pcs_mode == E400G_50G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_rx_primary_use == E400G_50G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_speed_map == E400G_50G_SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_sup_mode == E400G_50G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_sys_clk_src == E400G_50G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_tx_excvr_gb_ratio_mode == E400G_50G_TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_tx_excvr_if_fifo_mode == E400G_50G_TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_tx_fec_enable == E400G_50G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_tx_pcs_mode == E400G_50G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_tx_primary_use == E400G_50G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_xcvrif_force_signal_ok == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.e400g_50g_xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.cfg_frac == FRAC_LN112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s0.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.aib1_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.aib1_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.aib2_ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.aib2_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.aib2_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.aib3_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.aib3_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.am_sf_tx_ld_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.am_sf_tx_rd_sel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.am_sf_tx_rsr_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.bk_pulse_space_sel == SPACEMODE_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.bk_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.bk_tx_rtrn_clk_sel == BK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.cfg_fec_rx_rst == UNUSED_CFG_FEC_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.cfg_fec_tx_rst == UNUSED_CFG_FEC_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.cfg_frac == FRAC_LN112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.cfg_xcvrif_rx_rst == UNUSED_CFG_XCVRIF_RX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.cfg_xcvrif_tx_rst == UNUSED_CFG_XCVRIF_TX_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.custom_am_1st == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.custom_am_2nd == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.custom_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.custom_log2mrk == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.cw_locking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.cw_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.degrade_ser_activate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.degrade_ser_deactivate == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.degrade_ser_interval == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.disable_3_bad_fec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.disable_scrambling == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.dual_fec_am_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.dual_fec_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.eng_2lane_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.eng_enter_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.eng_exit_align == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.eng_intrlv == INTRLV_BIT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.eng_test == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.engam5baddis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.engblkchkdis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.engcons25g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.engswaps == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.err_inj_tx_pat == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.err_inj_tx_rate == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.error_correction_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.error_indicator_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.eth_rx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.eth_tx_st_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.fec_bypass_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.fec_data_mux == SEL_AIB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.fec_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.fec_rx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.fec_sel == RS528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.fec_tx_core_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.fibre_channel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.inv_uniq_am_pat == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.join_lanes == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_aib_esys_clk_sel == TXTRANS_PTP0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_csr_ret_bond == DISABLE_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_dfd_csr_ctrl == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_eth_ptp0_clk == AIB1_PTP_ST0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_eth_triangle_en == ETH_TRIANGLE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_last_reg_dummy == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_ptp_st0_clk_sel == PLL0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_rx_clk_sel1 == UX_RX_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_rx_clk_sel2 == ETH_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_div2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel1 == UX_RX_USER_CLK_SEL1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel2 == RX_USER_CLK_SEL2_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_rx_user_clk_sel3 == RX_USER_CLK_SEL3_RXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_sfrz_rx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_sfrz_tx_bond_sel == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel1 == LOCAL_ESYS_CLK_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel2 == BOND_TX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel3 == AIB1_TX_XCVR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_tx_clk_sel4 == TX_AIB_ST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_div2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel1 == PLL0_DIV1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel2 == TX_USER_CLK_SEL2_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.lphy_tx_user_clk_sel3 == TX_USER_CLK_SEL3_TXWORD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.ptp_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_empty_hold == UNUSED_RX_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_empty_inten == UNUSED_RX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_full_hold == UNUSED_RX_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_full_inten == UNUSED_RX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_overflow_hold == UNUSED_RX_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_overflow_inten == UNUSED_RX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_pempty_hold == UNUSED_RX_FIFO_PMEPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_pempty_inten == UNUSED_RX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_pfull_hold == UNUSED_RX_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_pfull_inten == UNUSED_RX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_underrun_hold == UNUSED_RX_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_underrun_inten == UNUSED_RX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_gb_reserved_hold == UNUSED_RX_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_gb_reserved_inten == UNUSED_RX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_gb_restarted_hold == UNUSED_RX_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_gb_restarted_inten == UNUSED_RX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.sf_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.shadow_clear == UNUSED_SHADOW_CLEAR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.shadow_req == UNUSED_SHADOW_REQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.stream_rx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.stream_tx_width_is_forty == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.trans_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_en_fec_latency == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_empty_hold == UNUSED_TX_FIFO_EMPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_empty_inten == UNUSED_TX_INTEN_FIFO_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_full_hold == UNUSED_TX_FIFO_FULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_full_inten == UNUSED_TX_INTEN_FIFO_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_overflow_hold == UNUSED_TX_FIFO_OVERFLOW_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_overflow_inten == UNUSED_TX_INTEN_FIFO_OVERFLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_pempty_hold == UNUSED_TX_FIFO_PMEPTY_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_pempty_inten == UNUSED_TX_INTEN_FIFO_PEMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_pfull_hold == UNUSED_TX_FIFO_PFULL_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_pfull_inten == UNUSED_TX_INTEN_FIFO_PFULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_rd_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_underrun_hold == UNUSED_TX_FIFO_UNDERRUN_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_underrun_inten == UNUSED_TX_INTEN_FIFO_UNDERRUN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_fifo_wr_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_gb_reserved_hold == UNUSED_TX_GB_RESERVED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_gb_reserved_inten == UNUSED_TX_INTEN_GB_RESERVED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_gb_restarted_hold == UNUSED_TX_GB_RESTARTED_HOLD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_gb_restarted_inten == UNUSED_TX_INTEN_GB_RESTARTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate == UNUSED_RX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.unused_lphy_rx_clk_gate_bit2 == UNUSED_RX_CLK_GATE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.unused_lphy_tx_clk_gate == UNUSED_TX_CLK_GATE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.ux_return_clk_gate_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.ux_tx_rtrn_clk_sel == UX15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvr_sel == BK_SEL_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_force_signal_ok == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_lpbk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rst_rxbit_cntr == RST_RXBIT_CNTR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv2_en == RX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_intlv4_en == RX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_bk_map == RX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_en_deskew == DIS_RX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_mode == RX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pempty == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_idw == RX_GB_IDW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_gb_odw == RX_GB_ODW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_multi_ln_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_phcomp_rd_delay == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_tag_sel == RX_TAG_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_ux_intlv2_en == RX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rx_xcvr_bond == BOND_RX_E25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rxbit_cntr_pma == RXBIT_CNTR_PMA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_sel_rxbit_adder == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_signal_ok_sel == XCVRIF_SIGNAL_OK_SYNC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_40b_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv2_en == TX_BK_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_intlv4_en == TX_BK_INTLV4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_bk_map == TX_BK_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_en_deskew == DIS_TX_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_mode == TX_FIFO_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pempty == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_fifo_pfull == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gating_sel == GATE_SEL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_bp == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_idw == TX_GB_IDW_33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_gb_odw == TX_GB_ODW_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_multi_ln_sel == TX_ML_SEL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_phcomp_rd_delay == PHCOMP_RD_DEL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_source_sel == TX_ADAPTER_SOURCE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_ux_intlv2_en == TX_UX_INTLV2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e400g_lphy.gdr_lphy_e50g_reg_ch8.gdr_lphy_e25g_reg_base_s1.xcvrif_tx_ux_map == TX_UX_MAIN_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_aibif_data_valid == E400G_100G_0_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_duplex_mode == E400G_100G_0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_fec_mode == E400G_100G_0_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_lpbk_mode == E400G_100G_0_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_flow_control == E400G_100G_0_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_flow_control_holdoff_mode == E400G_100G_0_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_link_fault_mode == E400G_100G_0_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_mode == E400G_100G_0_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_rx_ptp_phy_lane_num == E400G_100G_0_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_tx_ipg_size == E400G_100G_0_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_tx_ptp_phy_lane_num == E400G_100G_0_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_pcs_ber_mon_mode == E400G_100G_0_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_pcs_pcs_ber_mon_mode == E400G_100G_0_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_ptp_mode == E400G_100G_0_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_rx_fec_enable == E400G_100G_0_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_rx_pcs_mode == E400G_100G_0_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_rx_primary_use == E400G_100G_0_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_rx_system_bonding == E400G_100G_0_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_sup_mode == E400G_100G_0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_sys_clk_src == E400G_100G_0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_tx_aib_if_fifo_mode == E400G_100G_0_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_tx_fec_enable == E400G_100G_0_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_tx_pcs_mode == E400G_100G_0_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_tx_primary_use == E400G_100G_0_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_tx_system_bonding == E400G_100G_0_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_0_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_aibif_data_valid == E400G_100G_1_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_duplex_mode == E400G_100G_1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_fec_mode == E400G_100G_1_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_lpbk_mode == E400G_100G_1_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_flow_control == E400G_100G_1_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_flow_control_holdoff_mode == E400G_100G_1_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_link_fault_mode == E400G_100G_1_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_mode == E400G_100G_1_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_rx_ptp_phy_lane_num == E400G_100G_1_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_tx_ipg_size == E400G_100G_1_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_tx_ptp_phy_lane_num == E400G_100G_1_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_pcs_ber_mon_mode == E400G_100G_1_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_pcs_pcs_ber_mon_mode == E400G_100G_1_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_ptp_mode == E400G_100G_1_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_rx_fec_enable == E400G_100G_1_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_rx_pcs_mode == E400G_100G_1_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_rx_primary_use == E400G_100G_1_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_rx_system_bonding == E400G_100G_1_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_sup_mode == E400G_100G_1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_sys_clk_src == E400G_100G_1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_tx_aib_if_fifo_mode == E400G_100G_1_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_tx_fec_enable == E400G_100G_1_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_tx_pcs_mode == E400G_100G_1_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_tx_primary_use == E400G_100G_1_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_tx_system_bonding == E400G_100G_1_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_1_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_aibif_data_valid == E400G_100G_2_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_duplex_mode == E400G_100G_2_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_fec_mode == E400G_100G_2_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_lpbk_mode == E400G_100G_2_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_flow_control == E400G_100G_2_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_flow_control_holdoff_mode == E400G_100G_2_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_link_fault_mode == E400G_100G_2_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_mode == E400G_100G_2_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_rx_ptp_phy_lane_num == E400G_100G_2_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_tx_ipg_size == E400G_100G_2_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_tx_ptp_phy_lane_num == E400G_100G_2_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_pcs_ber_mon_mode == E400G_100G_2_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_pcs_pcs_ber_mon_mode == E400G_100G_2_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_ptp_mode == E400G_100G_2_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_rx_fec_enable == E400G_100G_2_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_rx_pcs_mode == E400G_100G_2_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_rx_primary_use == E400G_100G_2_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_rx_system_bonding == E400G_100G_2_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_sup_mode == E400G_100G_2_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_sys_clk_src == E400G_100G_2_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_tx_aib_if_fifo_mode == E400G_100G_2_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_tx_fec_enable == E400G_100G_2_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_tx_pcs_mode == E400G_100G_2_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_tx_primary_use == E400G_100G_2_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_tx_system_bonding == E400G_100G_2_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_2_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_aibif_data_valid == E400G_100G_3_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_duplex_mode == E400G_100G_3_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_fec_mode == E400G_100G_3_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_lpbk_mode == E400G_100G_3_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_flow_control == E400G_100G_3_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_flow_control_holdoff_mode == E400G_100G_3_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_link_fault_mode == E400G_100G_3_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_mode == E400G_100G_3_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_rx_ptp_phy_lane_num == E400G_100G_3_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_tx_ipg_size == E400G_100G_3_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_tx_ptp_phy_lane_num == E400G_100G_3_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_pcs_ber_mon_mode == E400G_100G_3_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_pcs_pcs_ber_mon_mode == E400G_100G_3_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_ptp_mode == E400G_100G_3_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_rx_fec_enable == E400G_100G_3_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_rx_pcs_mode == E400G_100G_3_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_rx_primary_use == E400G_100G_3_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_rx_system_bonding == E400G_100G_3_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_sup_mode == E400G_100G_3_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_sys_clk_src == E400G_100G_3_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_tx_aib_if_fifo_mode == E400G_100G_3_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_tx_fec_enable == E400G_100G_3_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_tx_pcs_mode == E400G_100G_3_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_tx_primary_use == E400G_100G_3_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_tx_system_bonding == E400G_100G_3_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_100g_3_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_0_aibif_data_valid == E400G_150G_0_AIBIF_DATA_VALID_CUSTOM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_0_duplex_mode == E400G_150G_0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_0_fec_mode == E400G_150G_0_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_0_lpbk_mode == E400G_150G_0_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_0_mac_mode == E400G_150G_0_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_0_pcs_ber_mon_mode == E400G_150G_0_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_0_ptp_mode == E400G_150G_0_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_0_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_0_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_0_rx_fec_enable == E400G_150G_0_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_0_rx_pcs_mode == E400G_150G_0_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_0_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_0_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_0_rx_primary_use == E400G_150G_0_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_0_rx_system_bonding == E400G_150G_0_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_0_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_0_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_0_sup_mode == E400G_150G_0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_0_sys_clk_src == E400G_150G_0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_0_tx_aib_if_fifo_mode == E400G_150G_0_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_0_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_0_tx_fec_enable == E400G_150G_0_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_0_tx_pcs_mode == E400G_150G_0_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_0_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_0_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_0_tx_primary_use == E400G_150G_0_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_0_tx_system_bonding == E400G_150G_0_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_0_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_1_aibif_data_valid == E400G_150G_1_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_1_duplex_mode == E400G_150G_1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_1_fec_mode == E400G_150G_1_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_1_lpbk_mode == E400G_150G_1_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_1_mac_mode == E400G_150G_1_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_1_pcs_ber_mon_mode == E400G_150G_1_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_1_ptp_mode == E400G_150G_1_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_1_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_1_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_1_rx_fec_enable == E400G_150G_1_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_1_rx_pcs_mode == E400G_150G_1_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_1_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_1_rx_primary_use == E400G_150G_1_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_1_rx_system_bonding == E400G_150G_1_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_1_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_1_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_1_sup_mode == E400G_150G_1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_1_sys_clk_src == E400G_150G_1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_1_tx_aib_if_fifo_mode == E400G_150G_1_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_1_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_1_tx_fec_enable == E400G_150G_1_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_1_tx_pcs_mode == E400G_150G_1_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_1_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_1_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_1_tx_primary_use == E400G_150G_1_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_1_tx_system_bonding == E400G_150G_1_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_1_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_2_aibif_data_valid == E400G_150G_2_AIBIF_DATA_VALID_CUSTOM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_2_duplex_mode == E400G_150G_2_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_2_fec_mode == E400G_150G_2_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_2_lpbk_mode == E400G_150G_2_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_2_mac_mode == E400G_150G_2_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_2_pcs_ber_mon_mode == E400G_150G_2_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_2_ptp_mode == E400G_150G_2_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_2_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_2_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_2_rx_fec_enable == E400G_150G_2_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_2_rx_pcs_mode == E400G_150G_2_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_2_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_2_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_2_rx_primary_use == E400G_150G_2_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_2_rx_system_bonding == E400G_150G_2_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_2_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_2_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_2_sup_mode == E400G_150G_2_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_2_sys_clk_src == E400G_150G_2_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_2_tx_aib_if_fifo_mode == E400G_150G_2_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_2_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_2_tx_fec_enable == E400G_150G_2_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_2_tx_pcs_mode == E400G_150G_2_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_2_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_2_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_2_tx_primary_use == E400G_150G_2_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_2_tx_system_bonding == E400G_150G_2_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_2_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_3_aibif_data_valid == E400G_150G_3_AIBIF_DATA_VALID_CUSTOM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_3_duplex_mode == E400G_150G_3_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_3_fec_mode == E400G_150G_3_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_3_lpbk_mode == E400G_150G_3_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_3_mac_mode == E400G_150G_3_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_3_pcs_ber_mon_mode == E400G_150G_3_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_3_ptp_mode == E400G_150G_3_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_3_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_3_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_3_rx_fec_enable == E400G_150G_3_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_3_rx_pcs_mode == E400G_150G_3_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_3_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_3_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_3_rx_primary_use == E400G_150G_3_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_3_rx_system_bonding == E400G_150G_3_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_3_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_3_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_3_sup_mode == E400G_150G_3_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_3_sys_clk_src == E400G_150G_3_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_3_tx_aib_if_fifo_mode == E400G_150G_3_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_3_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_3_tx_fec_enable == E400G_150G_3_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_3_tx_pcs_mode == E400G_150G_3_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_3_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_3_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_3_tx_primary_use == E400G_150G_3_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_3_tx_system_bonding == E400G_150G_3_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_150g_3_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_aibif_data_valid == E400G_200G_0_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_duplex_mode == E400G_200G_0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_fec_mode == E400G_200G_0_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_lpbk_mode == E400G_200G_0_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_flow_control == E400G_200G_0_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_flow_control_holdoff_mode == E400G_200G_0_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_link_fault_mode == E400G_200G_0_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_mode == E400G_200G_0_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_rx_ptp_phy_lane_num == E400G_200G_0_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_tx_ipg_size == E400G_200G_0_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_tx_ptp_phy_lane_num == E400G_200G_0_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_pcs_ber_mon_mode == E400G_200G_0_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_pcs_pcs_ber_mon_mode == E400G_200G_0_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_ptp_mode == E400G_200G_0_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_rx_fec_enable == E400G_200G_0_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_rx_pcs_mode == E400G_200G_0_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_rx_primary_use == E400G_200G_0_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_rx_system_bonding == E400G_200G_0_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_sup_mode == E400G_200G_0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_sys_clk_src == E400G_200G_0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_tx_aib_if_fifo_mode == E400G_200G_0_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_tx_fec_enable == E400G_200G_0_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_tx_pcs_mode == E400G_200G_0_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_tx_primary_use == E400G_200G_0_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_tx_system_bonding == E400G_200G_0_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_0_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_aibif_data_valid == E400G_200G_1_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_duplex_mode == E400G_200G_1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_fec_mode == E400G_200G_1_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_lpbk_mode == E400G_200G_1_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_flow_control == E400G_200G_1_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_flow_control_holdoff_mode == E400G_200G_1_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_link_fault_mode == E400G_200G_1_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_mode == E400G_200G_1_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_rx_ptp_phy_lane_num == E400G_200G_1_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_tx_ipg_size == E400G_200G_1_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_tx_ptp_phy_lane_num == E400G_200G_1_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_pcs_ber_mon_mode == E400G_200G_1_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_pcs_pcs_ber_mon_mode == E400G_200G_1_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_ptp_mode == E400G_200G_1_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_rx_fec_enable == E400G_200G_1_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_rx_pcs_mode == E400G_200G_1_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_rx_primary_use == E400G_200G_1_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_rx_system_bonding == E400G_200G_1_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_sup_mode == E400G_200G_1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_sys_clk_src == E400G_200G_1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_tx_aib_if_fifo_mode == E400G_200G_1_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_tx_fec_enable == E400G_200G_1_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_tx_pcs_mode == E400G_200G_1_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_tx_primary_use == E400G_200G_1_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_tx_system_bonding == E400G_200G_1_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_200g_1_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_aibif_data_valid == E400G_25G_0_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_duplex_mode == E400G_25G_0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_fec_mode == E400G_25G_0_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_fec_spec == E400G_25G_0_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_lpbk_mode == E400G_25G_0_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_flow_control == E400G_25G_0_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_flow_control_holdoff_mode == E400G_25G_0_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_link_fault_mode == E400G_25G_0_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_mode == E400G_25G_0_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_rx_ptp_phy_lane_num == E400G_25G_0_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_tx_ipg_size == E400G_25G_0_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_tx_ptp_phy_lane_num == E400G_25G_0_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_pcs_ber_mon_mode == E400G_25G_0_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_pcs_pcs_ber_mon_mode == E400G_25G_0_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_ptp_mode == E400G_25G_0_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_rx_fec_enable == E400G_25G_0_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_rx_pcs_mode == E400G_25G_0_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_rx_primary_use == E400G_25G_0_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_rx_system_bonding == E400G_25G_0_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_sup_mode == E400G_25G_0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_sys_clk_src == E400G_25G_0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_tx_aib_if_fifo_mode == E400G_25G_0_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_tx_fec_enable == E400G_25G_0_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_tx_pcs_mode == E400G_25G_0_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_tx_primary_use == E400G_25G_0_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_tx_system_bonding == E400G_25G_0_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_0_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_aibif_data_valid == E400G_25G_10_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_duplex_mode == E400G_25G_10_DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_fec_mode == E400G_25G_10_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_fec_spec == E400G_25G_10_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_lpbk_mode == E400G_25G_10_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_flow_control == E400G_25G_10_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_flow_control_holdoff_mode == E400G_25G_10_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_link_fault_mode == E400G_25G_10_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_mode == E400G_25G_10_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_rx_ptp_phy_lane_num == E400G_25G_10_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_tx_ipg_size == E400G_25G_10_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_tx_ptp_phy_lane_num == E400G_25G_10_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_pcs_ber_mon_mode == E400G_25G_10_PCS_BER_MON_MODE_10G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_pcs_pcs_ber_mon_mode == E400G_25G_10_PCS_PCS_BER_MON_MODE_10G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_ptp_mode == E400G_25G_10_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_rx_fec_enable == E400G_25G_10_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_rx_pcs_mode == E400G_25G_10_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_rx_primary_use == E400G_25G_10_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_rx_system_bonding == E400G_25G_10_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_sup_mode == E400G_25G_10_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_sys_clk_src == E400G_25G_10_SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_tx_aib_if_fifo_mode == E400G_25G_10_TX_AIB_IF_FIFO_MODE_PHASECOMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_tx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_tx_fec_enable == E400G_25G_10_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_tx_pcs_mode == E400G_25G_10_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_tx_primary_use == E400G_25G_10_TX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_tx_system_bonding == E400G_25G_10_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_10_tx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_aibif_data_valid == E400G_25G_11_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_duplex_mode == E400G_25G_11_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_fec_mode == E400G_25G_11_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_fec_spec == E400G_25G_11_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_lpbk_mode == E400G_25G_11_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_flow_control == E400G_25G_11_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_flow_control_holdoff_mode == E400G_25G_11_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_link_fault_mode == E400G_25G_11_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_mode == E400G_25G_11_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_rx_ptp_phy_lane_num == E400G_25G_11_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_tx_ipg_size == E400G_25G_11_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_tx_ptp_phy_lane_num == E400G_25G_11_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_pcs_ber_mon_mode == E400G_25G_11_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_pcs_pcs_ber_mon_mode == E400G_25G_11_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_ptp_mode == E400G_25G_11_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_rx_fec_enable == E400G_25G_11_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_rx_pcs_mode == E400G_25G_11_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_rx_primary_use == E400G_25G_11_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_rx_system_bonding == E400G_25G_11_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_sup_mode == E400G_25G_11_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_sys_clk_src == E400G_25G_11_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_tx_aib_if_fifo_mode == E400G_25G_11_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_tx_fec_enable == E400G_25G_11_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_tx_pcs_mode == E400G_25G_11_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_tx_primary_use == E400G_25G_11_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_tx_system_bonding == E400G_25G_11_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_11_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_aibif_data_valid == E400G_25G_12_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_duplex_mode == E400G_25G_12_DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_fec_mode == E400G_25G_12_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_fec_spec == E400G_25G_12_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_lpbk_mode == E400G_25G_12_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_flow_control == E400G_25G_12_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_flow_control_holdoff_mode == E400G_25G_12_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_link_fault_mode == E400G_25G_12_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_mode == E400G_25G_12_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_rx_ptp_phy_lane_num == E400G_25G_12_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_tx_ipg_size == E400G_25G_12_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_tx_ptp_phy_lane_num == E400G_25G_12_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_pcs_ber_mon_mode == E400G_25G_12_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_pcs_pcs_ber_mon_mode == E400G_25G_12_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_ptp_mode == E400G_25G_12_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_rx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_rx_fec_enable == E400G_25G_12_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_rx_pcs_mode == E400G_25G_12_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_rx_primary_use == E400G_25G_12_RX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_rx_system_bonding == E400G_25G_12_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_rx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_sup_mode == E400G_25G_12_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_sys_clk_src == E400G_25G_12_SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_tx_aib_if_fifo_mode == E400G_25G_12_TX_AIB_IF_FIFO_MODE_PHASECOMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_tx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_tx_fec_enable == E400G_25G_12_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_tx_pcs_mode == E400G_25G_12_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_tx_primary_use == E400G_25G_12_TX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_tx_system_bonding == E400G_25G_12_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_12_tx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_aibif_data_valid == E400G_25G_13_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_duplex_mode == E400G_25G_13_DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_fec_mode == E400G_25G_13_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_fec_spec == E400G_25G_13_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_lpbk_mode == E400G_25G_13_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_flow_control == E400G_25G_13_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_flow_control_holdoff_mode == E400G_25G_13_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_link_fault_mode == E400G_25G_13_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_mode == E400G_25G_13_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_rx_ptp_phy_lane_num == E400G_25G_13_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_tx_ipg_size == E400G_25G_13_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_tx_ptp_phy_lane_num == E400G_25G_13_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_pcs_ber_mon_mode == E400G_25G_13_PCS_BER_MON_MODE_10G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_pcs_pcs_ber_mon_mode == E400G_25G_13_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_ptp_mode == E400G_25G_13_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_rx_fec_enable == E400G_25G_13_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_rx_pcs_mode == E400G_25G_13_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_rx_primary_use == E400G_25G_13_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_rx_system_bonding == E400G_25G_13_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_sup_mode == E400G_25G_13_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_sys_clk_src == E400G_25G_13_SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_tx_aib_if_fifo_mode == E400G_25G_13_TX_AIB_IF_FIFO_MODE_PHASECOMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_tx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_tx_fec_enable == E400G_25G_13_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_tx_pcs_mode == E400G_25G_13_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_tx_primary_use == E400G_25G_13_TX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_tx_system_bonding == E400G_25G_13_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_13_tx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_aibif_data_valid == E400G_25G_14_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_duplex_mode == E400G_25G_14_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_fec_mode == E400G_25G_14_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_fec_spec == E400G_25G_14_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_lpbk_mode == E400G_25G_14_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_flow_control == E400G_25G_14_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_flow_control_holdoff_mode == E400G_25G_14_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_link_fault_mode == E400G_25G_14_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_mode == E400G_25G_14_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_rx_ptp_phy_lane_num == E400G_25G_14_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_tx_ipg_size == E400G_25G_14_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_tx_ptp_phy_lane_num == E400G_25G_14_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_pcs_ber_mon_mode == E400G_25G_14_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_pcs_pcs_ber_mon_mode == E400G_25G_14_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_ptp_mode == E400G_25G_14_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_rx_fec_enable == E400G_25G_14_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_rx_pcs_mode == E400G_25G_14_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_rx_primary_use == E400G_25G_14_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_rx_system_bonding == E400G_25G_14_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_sup_mode == E400G_25G_14_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_sys_clk_src == E400G_25G_14_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_tx_aib_if_fifo_mode == E400G_25G_14_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_tx_fec_enable == E400G_25G_14_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_tx_pcs_mode == E400G_25G_14_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_tx_primary_use == E400G_25G_14_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_tx_system_bonding == E400G_25G_14_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_14_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_aibif_data_valid == E400G_25G_15_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_duplex_mode == E400G_25G_15_DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_fec_mode == E400G_25G_15_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_fec_spec == E400G_25G_15_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_lpbk_mode == E400G_25G_15_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_flow_control == E400G_25G_15_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_flow_control_holdoff_mode == E400G_25G_15_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_link_fault_mode == E400G_25G_15_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_mode == E400G_25G_15_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_rx_ptp_phy_lane_num == E400G_25G_15_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_tx_ipg_size == E400G_25G_15_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_tx_ptp_phy_lane_num == E400G_25G_15_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_pcs_ber_mon_mode == E400G_25G_15_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_pcs_pcs_ber_mon_mode == E400G_25G_15_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_ptp_mode == E400G_25G_15_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_rx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_rx_fec_enable == E400G_25G_15_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_rx_pcs_mode == E400G_25G_15_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_rx_primary_use == E400G_25G_15_RX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_rx_system_bonding == E400G_25G_15_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_rx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_sup_mode == E400G_25G_15_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_sys_clk_src == E400G_25G_15_SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_tx_aib_if_fifo_mode == E400G_25G_15_TX_AIB_IF_FIFO_MODE_PHASECOMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_tx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_tx_fec_enable == E400G_25G_15_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_tx_pcs_mode == E400G_25G_15_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_tx_primary_use == E400G_25G_15_TX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_tx_system_bonding == E400G_25G_15_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_15_tx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_aibif_data_valid == E400G_25G_1_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_duplex_mode == E400G_25G_1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_fec_mode == E400G_25G_1_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_fec_spec == E400G_25G_1_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_lpbk_mode == E400G_25G_1_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_flow_control == E400G_25G_1_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_flow_control_holdoff_mode == E400G_25G_1_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_link_fault_mode == E400G_25G_1_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_mode == E400G_25G_1_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_rx_ptp_phy_lane_num == E400G_25G_1_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_tx_ipg_size == E400G_25G_1_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_tx_ptp_phy_lane_num == E400G_25G_1_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_pcs_ber_mon_mode == E400G_25G_1_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_pcs_pcs_ber_mon_mode == E400G_25G_1_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_ptp_mode == E400G_25G_1_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_rx_fec_enable == E400G_25G_1_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_rx_pcs_mode == E400G_25G_1_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_rx_primary_use == E400G_25G_1_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_rx_system_bonding == E400G_25G_1_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_sup_mode == E400G_25G_1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_sys_clk_src == E400G_25G_1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_tx_aib_if_fifo_mode == E400G_25G_1_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_tx_fec_enable == E400G_25G_1_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_tx_pcs_mode == E400G_25G_1_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_tx_primary_use == E400G_25G_1_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_tx_system_bonding == E400G_25G_1_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_1_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_aibif_data_valid == E400G_25G_2_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_duplex_mode == E400G_25G_2_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_fec_mode == E400G_25G_2_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_fec_spec == E400G_25G_2_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_lpbk_mode == E400G_25G_2_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_flow_control == E400G_25G_2_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_flow_control_holdoff_mode == E400G_25G_2_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_link_fault_mode == E400G_25G_2_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_mode == E400G_25G_2_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_rx_ptp_phy_lane_num == E400G_25G_2_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_tx_ipg_size == E400G_25G_2_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_tx_ptp_phy_lane_num == E400G_25G_2_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_pcs_ber_mon_mode == E400G_25G_2_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_pcs_pcs_ber_mon_mode == E400G_25G_2_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_ptp_mode == E400G_25G_2_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_rx_fec_enable == E400G_25G_2_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_rx_pcs_mode == E400G_25G_2_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_rx_primary_use == E400G_25G_2_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_rx_system_bonding == E400G_25G_2_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_sup_mode == E400G_25G_2_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_sys_clk_src == E400G_25G_2_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_tx_aib_if_fifo_mode == E400G_25G_2_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_tx_fec_enable == E400G_25G_2_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_tx_pcs_mode == E400G_25G_2_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_tx_primary_use == E400G_25G_2_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_tx_system_bonding == E400G_25G_2_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_2_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_aibif_data_valid == E400G_25G_3_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_duplex_mode == E400G_25G_3_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_fec_mode == E400G_25G_3_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_fec_spec == E400G_25G_3_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_lpbk_mode == E400G_25G_3_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_flow_control == E400G_25G_3_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_flow_control_holdoff_mode == E400G_25G_3_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_link_fault_mode == E400G_25G_3_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_mode == E400G_25G_3_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_rx_ptp_phy_lane_num == E400G_25G_3_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_tx_ipg_size == E400G_25G_3_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_tx_ptp_phy_lane_num == E400G_25G_3_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_pcs_ber_mon_mode == E400G_25G_3_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_pcs_pcs_ber_mon_mode == E400G_25G_3_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_ptp_mode == E400G_25G_3_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_rx_fec_enable == E400G_25G_3_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_rx_pcs_mode == E400G_25G_3_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_rx_primary_use == E400G_25G_3_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_rx_system_bonding == E400G_25G_3_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_sup_mode == E400G_25G_3_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_sys_clk_src == E400G_25G_3_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_tx_aib_if_fifo_mode == E400G_25G_3_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_tx_fec_enable == E400G_25G_3_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_tx_pcs_mode == E400G_25G_3_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_tx_primary_use == E400G_25G_3_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_tx_system_bonding == E400G_25G_3_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_3_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_aibif_data_valid == E400G_25G_4_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_duplex_mode == E400G_25G_4_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_fec_mode == E400G_25G_4_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_fec_spec == E400G_25G_4_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_lpbk_mode == E400G_25G_4_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_flow_control == E400G_25G_4_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_flow_control_holdoff_mode == E400G_25G_4_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_link_fault_mode == E400G_25G_4_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_mode == E400G_25G_4_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_rx_ptp_phy_lane_num == E400G_25G_4_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_tx_ipg_size == E400G_25G_4_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_tx_ptp_phy_lane_num == E400G_25G_4_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_pcs_ber_mon_mode == E400G_25G_4_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_pcs_pcs_ber_mon_mode == E400G_25G_4_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_ptp_mode == E400G_25G_4_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_rx_fec_enable == E400G_25G_4_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_rx_pcs_mode == E400G_25G_4_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_rx_primary_use == E400G_25G_4_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_rx_system_bonding == E400G_25G_4_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_sup_mode == E400G_25G_4_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_sys_clk_src == E400G_25G_4_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_tx_aib_if_fifo_mode == E400G_25G_4_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_tx_fec_enable == E400G_25G_4_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_tx_pcs_mode == E400G_25G_4_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_tx_primary_use == E400G_25G_4_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_tx_system_bonding == E400G_25G_4_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_4_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_aibif_data_valid == E400G_25G_5_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_duplex_mode == E400G_25G_5_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_fec_mode == E400G_25G_5_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_fec_spec == E400G_25G_5_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_lpbk_mode == E400G_25G_5_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_flow_control == E400G_25G_5_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_flow_control_holdoff_mode == E400G_25G_5_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_link_fault_mode == E400G_25G_5_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_mode == E400G_25G_5_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_rx_ptp_phy_lane_num == E400G_25G_5_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_tx_ipg_size == E400G_25G_5_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_tx_ptp_phy_lane_num == E400G_25G_5_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_pcs_ber_mon_mode == E400G_25G_5_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_pcs_pcs_ber_mon_mode == E400G_25G_5_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_ptp_mode == E400G_25G_5_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_rx_fec_enable == E400G_25G_5_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_rx_pcs_mode == E400G_25G_5_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_rx_primary_use == E400G_25G_5_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_rx_system_bonding == E400G_25G_5_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_sup_mode == E400G_25G_5_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_sys_clk_src == E400G_25G_5_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_tx_aib_if_fifo_mode == E400G_25G_5_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_tx_fec_enable == E400G_25G_5_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_tx_pcs_mode == E400G_25G_5_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_tx_primary_use == E400G_25G_5_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_tx_system_bonding == E400G_25G_5_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_5_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_aibif_data_valid == E400G_25G_6_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_duplex_mode == E400G_25G_6_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_fec_mode == E400G_25G_6_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_fec_spec == E400G_25G_6_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_lpbk_mode == E400G_25G_6_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_flow_control == E400G_25G_6_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_flow_control_holdoff_mode == E400G_25G_6_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_link_fault_mode == E400G_25G_6_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_mode == E400G_25G_6_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_rx_ptp_phy_lane_num == E400G_25G_6_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_tx_ipg_size == E400G_25G_6_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_tx_ptp_phy_lane_num == E400G_25G_6_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_pcs_ber_mon_mode == E400G_25G_6_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_pcs_pcs_ber_mon_mode == E400G_25G_6_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_ptp_mode == E400G_25G_6_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_rx_fec_enable == E400G_25G_6_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_rx_pcs_mode == E400G_25G_6_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_rx_primary_use == E400G_25G_6_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_rx_system_bonding == E400G_25G_6_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_sup_mode == E400G_25G_6_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_sys_clk_src == E400G_25G_6_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_tx_aib_if_fifo_mode == E400G_25G_6_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_tx_fec_enable == E400G_25G_6_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_tx_pcs_mode == E400G_25G_6_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_tx_primary_use == E400G_25G_6_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_tx_system_bonding == E400G_25G_6_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_6_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_aibif_data_valid == E400G_25G_7_AIBIF_DATA_VALID_40G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_duplex_mode == E400G_25G_7_DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_fec_mode == E400G_25G_7_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_fec_spec == E400G_25G_7_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_lpbk_mode == E400G_25G_7_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_flow_control == E400G_25G_7_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_flow_control_holdoff_mode == E400G_25G_7_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_link_fault_mode == E400G_25G_7_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_mode == E400G_25G_7_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_rx_ptp_phy_lane_num == E400G_25G_7_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_tx_ipg_size == E400G_25G_7_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_tx_ptp_phy_lane_num == E400G_25G_7_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_pcs_ber_mon_mode == E400G_25G_7_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_pcs_pcs_ber_mon_mode == E400G_25G_7_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_ptp_mode == E400G_25G_7_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_rx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_rx_fec_enable == E400G_25G_7_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_rx_pcs_mode == E400G_25G_7_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_rx_primary_use == E400G_25G_7_RX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_rx_system_bonding == E400G_25G_7_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_rx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_sup_mode == E400G_25G_7_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_sys_clk_src == E400G_25G_7_SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_tx_aib_if_fifo_mode == E400G_25G_7_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_tx_fec_enable == E400G_25G_7_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_tx_pcs_mode == E400G_25G_7_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_tx_primary_use == E400G_25G_7_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_tx_system_bonding == E400G_25G_7_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_7_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_aibif_data_valid == E400G_25G_8_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_duplex_mode == E400G_25G_8_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_fec_mode == E400G_25G_8_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_fec_spec == E400G_25G_8_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_lpbk_mode == E400G_25G_8_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_flow_control == E400G_25G_8_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_flow_control_holdoff_mode == E400G_25G_8_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_link_fault_mode == E400G_25G_8_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_mode == E400G_25G_8_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_rx_ptp_phy_lane_num == E400G_25G_8_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_tx_ipg_size == E400G_25G_8_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_tx_ptp_phy_lane_num == E400G_25G_8_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_pcs_ber_mon_mode == E400G_25G_8_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_pcs_pcs_ber_mon_mode == E400G_25G_8_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_ptp_mode == E400G_25G_8_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_rx_fec_enable == E400G_25G_8_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_rx_pcs_mode == E400G_25G_8_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_rx_primary_use == E400G_25G_8_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_rx_system_bonding == E400G_25G_8_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_sup_mode == E400G_25G_8_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_sys_clk_src == E400G_25G_8_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_tx_aib_if_fifo_mode == E400G_25G_8_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_tx_fec_enable == E400G_25G_8_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_tx_pcs_mode == E400G_25G_8_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_tx_primary_use == E400G_25G_8_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_tx_system_bonding == E400G_25G_8_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_8_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_aibif_data_valid == E400G_25G_9_AIBIF_DATA_VALID_40G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_duplex_mode == E400G_25G_9_DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_fec_mode == E400G_25G_9_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_fec_spec == E400G_25G_9_FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_lpbk_mode == E400G_25G_9_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_flow_control == E400G_25G_9_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_flow_control_holdoff_mode == E400G_25G_9_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_link_fault_mode == E400G_25G_9_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_mode == E400G_25G_9_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_rx_ptp_phy_lane_num == E400G_25G_9_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_tx_ipg_size == E400G_25G_9_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_tx_ptp_phy_lane_num == E400G_25G_9_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_pcs_ber_mon_mode == E400G_25G_9_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_pcs_pcs_ber_mon_mode == E400G_25G_9_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_ptp_mode == E400G_25G_9_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_rx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_rx_fec_enable == E400G_25G_9_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_rx_pcs_mode == E400G_25G_9_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_rx_primary_use == E400G_25G_9_RX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_rx_system_bonding == E400G_25G_9_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_rx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_sup_mode == E400G_25G_9_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_sys_clk_src == E400G_25G_9_SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_tx_aib_if_fifo_mode == E400G_25G_9_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_tx_fec_enable == E400G_25G_9_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_tx_pcs_mode == E400G_25G_9_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_tx_primary_use == E400G_25G_9_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_tx_system_bonding == E400G_25G_9_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_25g_9_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_0_aibif_data_valid == E400G_300G_0_AIBIF_DATA_VALID_CUSTOM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_0_duplex_mode == E400G_300G_0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_0_fec_mode == E400G_300G_0_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_0_lpbk_mode == E400G_300G_0_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_0_mac_mode == E400G_300G_0_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_0_pcs_ber_mon_mode == E400G_300G_0_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_0_ptp_mode == E400G_300G_0_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_0_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_0_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_0_rx_fec_enable == E400G_300G_0_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_0_rx_pcs_mode == E400G_300G_0_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_0_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_0_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_0_rx_primary_use == E400G_300G_0_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_0_rx_system_bonding == E400G_300G_0_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_0_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_0_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_0_sup_mode == E400G_300G_0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_0_sys_clk_src == E400G_300G_0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_0_tx_aib_if_fifo_mode == E400G_300G_0_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_0_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_0_tx_fec_enable == E400G_300G_0_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_0_tx_pcs_mode == E400G_300G_0_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_0_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_0_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_0_tx_primary_use == E400G_300G_0_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_0_tx_system_bonding == E400G_300G_0_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_0_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_1_aibif_data_valid == E400G_300G_1_AIBIF_DATA_VALID_CUSTOM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_1_duplex_mode == E400G_300G_1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_1_fec_mode == E400G_300G_1_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_1_lpbk_mode == E400G_300G_1_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_1_mac_mode == E400G_300G_1_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_1_pcs_ber_mon_mode == E400G_300G_1_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_1_ptp_mode == E400G_300G_1_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_1_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_1_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_1_rx_fec_enable == E400G_300G_1_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_1_rx_pcs_mode == E400G_300G_1_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_1_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_1_rx_primary_use == E400G_300G_1_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_1_rx_system_bonding == E400G_300G_1_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_1_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_1_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_1_sup_mode == E400G_300G_1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_1_sys_clk_src == E400G_300G_1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_1_tx_aib_if_fifo_mode == E400G_300G_1_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_1_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_1_tx_fec_enable == E400G_300G_1_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_1_tx_pcs_mode == E400G_300G_1_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_1_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_1_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_1_tx_primary_use == E400G_300G_1_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_1_tx_system_bonding == E400G_300G_1_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_300g_1_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_aibif_data_valid == E400G_400G_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_duplex_mode == E400G_400G_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_fec_mode == E400G_400G_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_lpbk_mode == E400G_400G_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_flow_control == E400G_400G_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_flow_control_holdoff_mode == E400G_400G_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_link_fault_mode == E400G_400G_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_mode == E400G_400G_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_rx_ptp_phy_lane_num == E400G_400G_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_tx_ipg_size == E400G_400G_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_tx_ptp_phy_lane_num == E400G_400G_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_pcs_ber_mon_mode == E400G_400G_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_pcs_pcs_ber_mon_mode == E400G_400G_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_ptp_mode == E400G_400G_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_rx_fec_enable == E400G_400G_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_rx_pcs_mode == E400G_400G_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_rx_primary_use == E400G_400G_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_rx_system_bonding == E400G_400G_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_sup_mode == E400G_400G_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_sys_clk_src == E400G_400G_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_tx_aib_if_fifo_mode == E400G_400G_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_tx_fec_enable == E400G_400G_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_tx_pcs_mode == E400G_400G_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_tx_primary_use == E400G_400G_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_tx_system_bonding == E400G_400G_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_400g_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_aibif_data_valid == E400G_50G_0_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_duplex_mode == E400G_50G_0_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_fec_mode == E400G_50G_0_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_lpbk_mode == E400G_50G_0_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_flow_control == E400G_50G_0_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_flow_control_holdoff_mode == E400G_50G_0_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_link_fault_mode == E400G_50G_0_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_mode == E400G_50G_0_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_rx_ptp_phy_lane_num == E400G_50G_0_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_tx_ipg_size == E400G_50G_0_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_tx_ptp_phy_lane_num == E400G_50G_0_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_pcs_ber_mon_mode == E400G_50G_0_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_pcs_pcs_ber_mon_mode == E400G_50G_0_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_ptp_mode == E400G_50G_0_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_rx_fec_enable == E400G_50G_0_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_rx_pcs_mode == E400G_50G_0_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_rx_primary_use == E400G_50G_0_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_rx_system_bonding == E400G_50G_0_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_sup_mode == E400G_50G_0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_sys_clk_src == E400G_50G_0_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_tx_aib_if_fifo_mode == E400G_50G_0_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_tx_fec_enable == E400G_50G_0_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_tx_pcs_mode == E400G_50G_0_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_tx_primary_use == E400G_50G_0_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_tx_system_bonding == E400G_50G_0_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_0_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_aibif_data_valid == E400G_50G_1_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_duplex_mode == E400G_50G_1_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_fec_mode == E400G_50G_1_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_lpbk_mode == E400G_50G_1_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_flow_control == E400G_50G_1_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_flow_control_holdoff_mode == E400G_50G_1_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_link_fault_mode == E400G_50G_1_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_mode == E400G_50G_1_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_rx_ptp_phy_lane_num == E400G_50G_1_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_tx_ipg_size == E400G_50G_1_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_tx_ptp_phy_lane_num == E400G_50G_1_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_pcs_ber_mon_mode == E400G_50G_1_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_pcs_pcs_ber_mon_mode == E400G_50G_1_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_ptp_mode == E400G_50G_1_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_rx_fec_enable == E400G_50G_1_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_rx_pcs_mode == E400G_50G_1_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_rx_primary_use == E400G_50G_1_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_rx_system_bonding == E400G_50G_1_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_sup_mode == E400G_50G_1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_sys_clk_src == E400G_50G_1_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_tx_aib_if_fifo_mode == E400G_50G_1_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_tx_fec_enable == E400G_50G_1_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_tx_pcs_mode == E400G_50G_1_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_tx_primary_use == E400G_50G_1_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_tx_system_bonding == E400G_50G_1_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_1_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_aibif_data_valid == E400G_50G_2_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_duplex_mode == E400G_50G_2_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_fec_mode == E400G_50G_2_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_lpbk_mode == E400G_50G_2_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_flow_control == E400G_50G_2_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_flow_control_holdoff_mode == E400G_50G_2_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_link_fault_mode == E400G_50G_2_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_mode == E400G_50G_2_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_rx_ptp_phy_lane_num == E400G_50G_2_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_tx_ipg_size == E400G_50G_2_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_tx_ptp_phy_lane_num == E400G_50G_2_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_pcs_ber_mon_mode == E400G_50G_2_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_pcs_pcs_ber_mon_mode == E400G_50G_2_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_ptp_mode == E400G_50G_2_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_rx_fec_enable == E400G_50G_2_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_rx_pcs_mode == E400G_50G_2_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_rx_primary_use == E400G_50G_2_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_rx_system_bonding == E400G_50G_2_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_sup_mode == E400G_50G_2_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_sys_clk_src == E400G_50G_2_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_tx_aib_if_fifo_mode == E400G_50G_2_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_tx_fec_enable == E400G_50G_2_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_tx_pcs_mode == E400G_50G_2_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_tx_primary_use == E400G_50G_2_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_tx_system_bonding == E400G_50G_2_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_2_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_aibif_data_valid == E400G_50G_3_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_duplex_mode == E400G_50G_3_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_fec_mode == E400G_50G_3_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_lpbk_mode == E400G_50G_3_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_flow_control == E400G_50G_3_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_flow_control_holdoff_mode == E400G_50G_3_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_link_fault_mode == E400G_50G_3_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_mode == E400G_50G_3_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_rx_ptp_phy_lane_num == E400G_50G_3_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_tx_ipg_size == E400G_50G_3_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_tx_ptp_phy_lane_num == E400G_50G_3_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_pcs_ber_mon_mode == E400G_50G_3_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_pcs_pcs_ber_mon_mode == E400G_50G_3_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_ptp_mode == E400G_50G_3_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_rx_fec_enable == E400G_50G_3_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_rx_pcs_mode == E400G_50G_3_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_rx_primary_use == E400G_50G_3_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_rx_system_bonding == E400G_50G_3_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_sup_mode == E400G_50G_3_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_sys_clk_src == E400G_50G_3_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_tx_aib_if_fifo_mode == E400G_50G_3_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_tx_fec_enable == E400G_50G_3_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_tx_pcs_mode == E400G_50G_3_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_tx_primary_use == E400G_50G_3_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_tx_system_bonding == E400G_50G_3_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_3_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_aibif_data_valid == E400G_50G_4_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_duplex_mode == E400G_50G_4_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_fec_mode == E400G_50G_4_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_lpbk_mode == E400G_50G_4_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_flow_control == E400G_50G_4_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_flow_control_holdoff_mode == E400G_50G_4_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_link_fault_mode == E400G_50G_4_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_mode == E400G_50G_4_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_rx_ptp_phy_lane_num == E400G_50G_4_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_tx_ipg_size == E400G_50G_4_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_tx_ptp_phy_lane_num == E400G_50G_4_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_pcs_ber_mon_mode == E400G_50G_4_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_pcs_pcs_ber_mon_mode == E400G_50G_4_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_ptp_mode == E400G_50G_4_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_rx_fec_enable == E400G_50G_4_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_rx_pcs_mode == E400G_50G_4_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_rx_primary_use == E400G_50G_4_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_rx_system_bonding == E400G_50G_4_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_sup_mode == E400G_50G_4_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_sys_clk_src == E400G_50G_4_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_tx_aib_if_fifo_mode == E400G_50G_4_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_tx_fec_enable == E400G_50G_4_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_tx_pcs_mode == E400G_50G_4_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_tx_primary_use == E400G_50G_4_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_tx_system_bonding == E400G_50G_4_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_4_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_aibif_data_valid == E400G_50G_5_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_duplex_mode == E400G_50G_5_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_fec_mode == E400G_50G_5_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_lpbk_mode == E400G_50G_5_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_flow_control == E400G_50G_5_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_flow_control_holdoff_mode == E400G_50G_5_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_link_fault_mode == E400G_50G_5_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_mode == E400G_50G_5_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_rx_ptp_phy_lane_num == E400G_50G_5_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_tx_ipg_size == E400G_50G_5_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_tx_ptp_phy_lane_num == E400G_50G_5_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_pcs_ber_mon_mode == E400G_50G_5_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_pcs_pcs_ber_mon_mode == E400G_50G_5_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_ptp_mode == E400G_50G_5_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_rx_fec_enable == E400G_50G_5_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_rx_pcs_mode == E400G_50G_5_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_rx_primary_use == E400G_50G_5_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_rx_system_bonding == E400G_50G_5_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_sup_mode == E400G_50G_5_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_sys_clk_src == E400G_50G_5_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_tx_aib_if_fifo_mode == E400G_50G_5_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_tx_fec_enable == E400G_50G_5_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_tx_pcs_mode == E400G_50G_5_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_tx_primary_use == E400G_50G_5_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_tx_system_bonding == E400G_50G_5_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_5_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_aibif_data_valid == E400G_50G_6_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_duplex_mode == E400G_50G_6_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_fec_mode == E400G_50G_6_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_lpbk_mode == E400G_50G_6_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_flow_control == E400G_50G_6_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_flow_control_holdoff_mode == E400G_50G_6_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_link_fault_mode == E400G_50G_6_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_mode == E400G_50G_6_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_rx_ptp_phy_lane_num == E400G_50G_6_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_tx_ipg_size == E400G_50G_6_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_tx_ptp_phy_lane_num == E400G_50G_6_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_pcs_ber_mon_mode == E400G_50G_6_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_pcs_pcs_ber_mon_mode == E400G_50G_6_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_ptp_mode == E400G_50G_6_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_rx_fec_enable == E400G_50G_6_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_rx_pcs_mode == E400G_50G_6_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_rx_primary_use == E400G_50G_6_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_rx_system_bonding == E400G_50G_6_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_sup_mode == E400G_50G_6_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_sys_clk_src == E400G_50G_6_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_tx_aib_if_fifo_mode == E400G_50G_6_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_tx_fec_enable == E400G_50G_6_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_tx_pcs_mode == E400G_50G_6_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_tx_primary_use == E400G_50G_6_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_tx_system_bonding == E400G_50G_6_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_6_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_aibif_data_valid == E400G_50G_7_AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_duplex_mode == E400G_50G_7_DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_fec_mode == E400G_50G_7_FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_lpbk_mode == E400G_50G_7_LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_flow_control == E400G_50G_7_MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_flow_control_holdoff_mode == E400G_50G_7_MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_link_fault_mode == E400G_50G_7_MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_mode == E400G_50G_7_MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_rx_ptp_phy_lane_num == E400G_50G_7_MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_tx_ipg_size == E400G_50G_7_MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_tx_ptp_phy_lane_num == E400G_50G_7_MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_pcs_ber_mon_mode == E400G_50G_7_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_pcs_pcs_ber_mon_mode == E400G_50G_7_PCS_PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_ptp_mode == E400G_50G_7_PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_rx_fec_enable == E400G_50G_7_RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_rx_pcs_mode == E400G_50G_7_RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_rx_primary_use == E400G_50G_7_RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_rx_system_bonding == E400G_50G_7_RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_sup_mode == E400G_50G_7_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_sys_clk_src == E400G_50G_7_SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_tx_aib_if_fifo_mode == E400G_50G_7_TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_tx_fec_enable == E400G_50G_7_TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_tx_pcs_mode == E400G_50G_7_TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_tx_primary_use == E400G_50G_7_TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_tx_system_bonding == E400G_50G_7_TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_50g_7_tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_stream0_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_stream0_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_stream10_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_stream10_tx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_stream11_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_stream11_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_stream12_rx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_stream12_tx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_stream13_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_stream13_tx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_stream14_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_stream14_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_stream15_rx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_stream15_tx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_stream1_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_stream1_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_stream2_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_stream2_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_stream3_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_stream3_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_stream4_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_stream4_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_stream5_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_stream5_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_stream6_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_stream6_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_stream7_rx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_stream7_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_stream8_rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_stream8_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_stream9_rx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.e400g_stream9_tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_100g_0_mac == E400G_100G_0_MAC_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_100g_0_rx_aibif == E400G_100G_0_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_100g_0_rx_pcs == E400G_100G_0_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_100g_0_tx_aibif == E400G_100G_0_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_100g_0_tx_pcs == E400G_100G_0_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_100g_1_mac == E400G_100G_1_MAC_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_100g_1_rx_aibif == E400G_100G_1_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_100g_1_rx_pcs == E400G_100G_1_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_100g_1_tx_aibif == E400G_100G_1_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_100g_1_tx_pcs == E400G_100G_1_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_100g_2_mac == E400G_100G_2_MAC_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_100g_2_rx_aibif == E400G_100G_2_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_100g_2_rx_pcs == E400G_100G_2_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_100g_2_tx_aibif == E400G_100G_2_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_100g_2_tx_pcs == E400G_100G_2_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_100g_3_mac == E400G_100G_3_MAC_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_100g_3_rx_aibif == E400G_100G_3_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_100g_3_rx_pcs == E400G_100G_3_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_100g_3_tx_aibif == E400G_100G_3_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_100g_3_tx_pcs == E400G_100G_3_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_200g_0_mac == E400G_200G_0_MAC_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_200g_0_rx_aibif == E400G_200G_0_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_200g_0_rx_pcs == E400G_200G_0_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_200g_0_tx_aibif == E400G_200G_0_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_200g_0_tx_pcs == E400G_200G_0_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_200g_1_mac == E400G_200G_1_MAC_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_200g_1_rx_aibif == E400G_200G_1_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_200g_1_rx_pcs == E400G_200G_1_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_200g_1_tx_aibif == E400G_200G_1_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_200g_1_tx_pcs == E400G_200G_1_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_0_mac == E400G_25G_0_MAC_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_0_rx_aibif == E400G_25G_0_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_0_rx_pcs == E400G_25G_0_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_0_tx_aibif == E400G_25G_0_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_0_tx_pcs == E400G_25G_0_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_10_mac == E400G_25G_10_MAC_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_10_rx_aibif == E400G_25G_10_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_10_rx_pcs == E400G_25G_10_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_10_tx_aibif == E400G_25G_10_TX_AIBIF_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_10_tx_pcs == E400G_25G_10_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_11_mac == E400G_25G_11_MAC_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_11_rx_aibif == E400G_25G_11_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_11_rx_pcs == E400G_25G_11_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_11_tx_aibif == E400G_25G_11_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_11_tx_pcs == E400G_25G_11_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_12_mac == E400G_25G_12_MAC_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_12_rx_aibif == E400G_25G_12_RX_AIBIF_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_12_rx_pcs == E400G_25G_12_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_12_tx_aibif == E400G_25G_12_TX_AIBIF_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_12_tx_pcs == E400G_25G_12_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_13_mac == E400G_25G_13_MAC_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_13_rx_aibif == E400G_25G_13_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_13_rx_pcs == E400G_25G_13_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_13_tx_aibif == E400G_25G_13_TX_AIBIF_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_13_tx_pcs == E400G_25G_13_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_14_mac == E400G_25G_14_MAC_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_14_rx_aibif == E400G_25G_14_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_14_rx_pcs == E400G_25G_14_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_14_tx_aibif == E400G_25G_14_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_14_tx_pcs == E400G_25G_14_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_15_mac == E400G_25G_15_MAC_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_15_rx_aibif == E400G_25G_15_RX_AIBIF_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_15_rx_pcs == E400G_25G_15_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_15_tx_aibif == E400G_25G_15_TX_AIBIF_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_15_tx_pcs == E400G_25G_15_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_1_mac == E400G_25G_1_MAC_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_1_rx_aibif == E400G_25G_1_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_1_rx_pcs == E400G_25G_1_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_1_tx_aibif == E400G_25G_1_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_1_tx_pcs == E400G_25G_1_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_2_mac == E400G_25G_2_MAC_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_2_rx_aibif == E400G_25G_2_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_2_rx_pcs == E400G_25G_2_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_2_tx_aibif == E400G_25G_2_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_2_tx_pcs == E400G_25G_2_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_3_mac == E400G_25G_3_MAC_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_3_rx_aibif == E400G_25G_3_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_3_rx_pcs == E400G_25G_3_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_3_tx_aibif == E400G_25G_3_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_3_tx_pcs == E400G_25G_3_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_4_mac == E400G_25G_4_MAC_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_4_rx_aibif == E400G_25G_4_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_4_rx_pcs == E400G_25G_4_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_4_tx_aibif == E400G_25G_4_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_4_tx_pcs == E400G_25G_4_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_5_mac == E400G_25G_5_MAC_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_5_rx_aibif == E400G_25G_5_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_5_rx_pcs == E400G_25G_5_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_5_tx_aibif == E400G_25G_5_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_5_tx_pcs == E400G_25G_5_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_6_mac == E400G_25G_6_MAC_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_6_rx_aibif == E400G_25G_6_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_6_rx_pcs == E400G_25G_6_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_6_tx_aibif == E400G_25G_6_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_6_tx_pcs == E400G_25G_6_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_7_mac == E400G_25G_7_MAC_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_7_rx_aibif == E400G_25G_7_RX_AIBIF_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_7_rx_pcs == E400G_25G_7_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_7_tx_aibif == E400G_25G_7_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_7_tx_pcs == E400G_25G_7_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_8_mac == E400G_25G_8_MAC_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_8_rx_aibif == E400G_25G_8_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_8_rx_pcs == E400G_25G_8_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_8_tx_aibif == E400G_25G_8_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_8_tx_pcs == E400G_25G_8_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_9_mac == E400G_25G_9_MAC_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_9_rx_aibif == E400G_25G_9_RX_AIBIF_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_9_rx_pcs == E400G_25G_9_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_9_tx_aibif == E400G_25G_9_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_25g_9_tx_pcs == E400G_25G_9_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_400g_mac == E400G_400G_MAC_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_400g_rx_aibif == E400G_400G_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_400g_rx_pcs == E400G_400G_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_400g_tx_aibif == E400G_400G_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_400g_tx_pcs == E400G_400G_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_0_mac == E400G_50G_0_MAC_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_0_rx_aibif == E400G_50G_0_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_0_rx_pcs == E400G_50G_0_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_0_tx_aibif == E400G_50G_0_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_0_tx_pcs == E400G_50G_0_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_1_mac == E400G_50G_1_MAC_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_1_rx_aibif == E400G_50G_1_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_1_rx_pcs == E400G_50G_1_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_1_tx_aibif == E400G_50G_1_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_1_tx_pcs == E400G_50G_1_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_2_mac == E400G_50G_2_MAC_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_2_rx_aibif == E400G_50G_2_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_2_rx_pcs == E400G_50G_2_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_2_tx_aibif == E400G_50G_2_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_2_tx_pcs == E400G_50G_2_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_3_mac == E400G_50G_3_MAC_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_3_rx_aibif == E400G_50G_3_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_3_rx_pcs == E400G_50G_3_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_3_tx_aibif == E400G_50G_3_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_3_tx_pcs == E400G_50G_3_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_4_mac == E400G_50G_4_MAC_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_4_rx_aibif == E400G_50G_4_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_4_rx_pcs == E400G_50G_4_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_4_tx_aibif == E400G_50G_4_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_4_tx_pcs == E400G_50G_4_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_5_mac == E400G_50G_5_MAC_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_5_rx_aibif == E400G_50G_5_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_5_rx_pcs == E400G_50G_5_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_5_tx_aibif == E400G_50G_5_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_5_tx_pcs == E400G_50G_5_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_6_mac == E400G_50G_6_MAC_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_6_rx_aibif == E400G_50G_6_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_6_rx_pcs == E400G_50G_6_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_6_tx_aibif == E400G_50G_6_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_6_tx_pcs == E400G_50G_6_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_7_mac == E400G_50G_7_MAC_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_7_rx_aibif == E400G_50G_7_RX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_7_rx_pcs == E400G_50G_7_RX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_7_tx_aibif == E400G_50G_7_TX_AIBIF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_e400g_50g_7_tx_pcs == E400G_50G_7_TX_PCS_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_ehip_cfg == EHIP_CFG_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_ac_ehip_misc == EHIP_MISC_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_dc == POWERUP_DC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_freq_hz_ehip_cfg_clk == 31'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_freq_hz_ehip_ch0_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_freq_hz_ehip_ch10_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_freq_hz_ehip_ch11_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_freq_hz_ehip_ch12_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_freq_hz_ehip_ch13_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_freq_hz_ehip_ch14_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_freq_hz_ehip_ch15_clk == 31'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_freq_hz_ehip_ch1_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_freq_hz_ehip_ch2_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_freq_hz_ehip_ch3_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_freq_hz_ehip_ch4_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_freq_hz_ehip_ch5_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_freq_hz_ehip_ch6_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_freq_hz_ehip_ch7_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_freq_hz_ehip_ch8_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.powermode_freq_hz_ehip_ch9_clk == 31'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_asm.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_asm.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_asm.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_asm.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_asm.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_asm.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_asm.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_PHASECOMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_asm.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_asm.word_align == WA_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.dfd_mux_reserved == DFD_RES_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.dfd_mux_sel == DFD_PRE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.dfd_node_sel == DFD_400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.testbus_ip_sel == TESTBUS_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.testbus_rx_tx_sel == TESTBUS_TX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.tx_fifo_lat_pulse_sel == LPHY_LAT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.ehip_rate == RATE_100G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_100g.gdr_e4hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.dfd_mux_reserved == DFD_RES_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.dfd_mux_sel == DFD_PRE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.dfd_node_sel == DFD_400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.testbus_ip_sel == TESTBUS_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.testbus_rx_tx_sel == TESTBUS_TX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.tx_fifo_lat_pulse_sel == LPHY_LAT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.ehip_rate == RATE_200G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_200g.gdr_e4hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.dfd_mux_reserved == DFD_RES_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.dfd_mux_sel == DFD_PRE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.dfd_node_sel == DFD_400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.testbus_ip_sel == TESTBUS_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.testbus_rx_tx_sel == TESTBUS_TX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.tx_fifo_lat_pulse_sel == LPHY_LAT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.ehip_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_25g.gdr_e4hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.dfd_mux_reserved == DFD_RES_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.dfd_mux_sel == DFD_PRE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.dfd_node_sel == DFD_400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.testbus_ip_sel == TESTBUS_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.testbus_rx_tx_sel == TESTBUS_TX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.tx_fifo_lat_pulse_sel == LPHY_LAT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.ehip_rate == RATE_400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_400g.gdr_e4hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.dfd_mux_reserved == DFD_RES_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.dfd_mux_sel == DFD_PRE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.dfd_node_sel == DFD_400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.testbus_ip_sel == TESTBUS_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.testbus_rx_tx_sel == TESTBUS_TX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.tx_fifo_lat_pulse_sel == LPHY_LAT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.ehip_rate == RATE_50G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch0_50g.gdr_e4hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.dfd_mux_reserved == DFD_RES_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.dfd_mux_sel == DFD_PRE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.dfd_node_sel == DFD_400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.duplex_mode == DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.sys_clk_src == SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.testbus_ip_sel == TESTBUS_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.testbus_rx_tx_sel == TESTBUS_TX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_PHASECOMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.tx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.tx_fifo_lat_pulse_sel == LPHY_LAT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.tx_primary_use == TX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.tx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_aibif.word_align == WA_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.aib_word_align_dis == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.duplex_mode == DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.ehip_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_10G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.rx_ehip_mode == FORCE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.sys_clk_src == SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.tx_primary_use == TX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_25g.gdr_e4hip_pcs.xus_timer_window == 21'd20141
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.dfd_mux_reserved == DFD_RES_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.dfd_mux_sel == DFD_PRE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.dfd_node_sel == DFD_400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.testbus_ip_sel == TESTBUS_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.testbus_rx_tx_sel == TESTBUS_TX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.tx_fifo_lat_pulse_sel == LPHY_LAT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.ehip_rate == RATE_50G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch10_50g.gdr_e4hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.dfd_mux_reserved == DFD_RES_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.dfd_mux_sel == DFD_PRE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.dfd_node_sel == DFD_400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.testbus_ip_sel == TESTBUS_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.testbus_rx_tx_sel == TESTBUS_TX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.tx_fifo_lat_pulse_sel == LPHY_LAT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.ehip_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch11_25g.gdr_e4hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.dfd_mux_reserved == DFD_RES_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.dfd_mux_sel == DFD_PRE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.dfd_node_sel == DFD_400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.testbus_ip_sel == TESTBUS_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.testbus_rx_tx_sel == TESTBUS_TX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.tx_fifo_lat_pulse_sel == LPHY_LAT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.ehip_rate == RATE_100G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_100g.gdr_e4hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.dfd_mux_reserved == DFD_RES_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.dfd_mux_sel == DFD_PRE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.dfd_node_sel == DFD_400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.duplex_mode == DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.rx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.rx_primary_use == RX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.rx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.sys_clk_src == SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.testbus_ip_sel == TESTBUS_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.testbus_rx_tx_sel == TESTBUS_TX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_PHASECOMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.tx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.tx_fifo_lat_pulse_sel == LPHY_LAT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.tx_primary_use == TX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.tx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_aibif.word_align == WA_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.aib_word_align_dis == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.duplex_mode == DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.ehip_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.hi_ber_monitor == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.rx_ehip_mode == FORCE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.rx_primary_use == RX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.sys_clk_src == SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.tx_primary_use == TX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_25g.gdr_e4hip_pcs.xus_timer_window == 21'd806451
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.dfd_mux_reserved == DFD_RES_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.dfd_mux_sel == DFD_PRE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.dfd_node_sel == DFD_400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.testbus_ip_sel == TESTBUS_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.testbus_rx_tx_sel == TESTBUS_TX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.tx_fifo_lat_pulse_sel == LPHY_LAT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.ehip_rate == RATE_50G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch12_50g.gdr_e4hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.dfd_mux_reserved == DFD_RES_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.dfd_mux_sel == DFD_PRE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.dfd_node_sel == DFD_400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.duplex_mode == DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.sys_clk_src == SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.testbus_ip_sel == TESTBUS_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.testbus_rx_tx_sel == TESTBUS_TX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_PHASECOMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.tx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.tx_fifo_lat_pulse_sel == LPHY_LAT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.tx_primary_use == TX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.tx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_aibif.word_align == WA_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.aib_word_align_dis == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.duplex_mode == DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.ehip_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_10G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.rx_ehip_mode == FORCE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.sys_clk_src == SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.tx_primary_use == TX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch13_25g.gdr_e4hip_pcs.xus_timer_window == 21'd20141
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.dfd_mux_reserved == DFD_RES_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.dfd_mux_sel == DFD_PRE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.dfd_node_sel == DFD_400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.testbus_ip_sel == TESTBUS_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.testbus_rx_tx_sel == TESTBUS_TX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.tx_fifo_lat_pulse_sel == LPHY_LAT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.ehip_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_25g.gdr_e4hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.dfd_mux_reserved == DFD_RES_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.dfd_mux_sel == DFD_PRE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.dfd_node_sel == DFD_400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.testbus_ip_sel == TESTBUS_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.testbus_rx_tx_sel == TESTBUS_TX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.tx_fifo_lat_pulse_sel == LPHY_LAT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.ehip_rate == RATE_50G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch14_50g.gdr_e4hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.dfd_mux_reserved == DFD_RES_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.dfd_mux_sel == DFD_PRE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.dfd_node_sel == DFD_400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.duplex_mode == DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.rx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.rx_primary_use == RX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.rx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.sys_clk_src == SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.testbus_ip_sel == TESTBUS_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.testbus_rx_tx_sel == TESTBUS_TX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_PHASECOMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.tx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.tx_fifo_lat_pulse_sel == LPHY_LAT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.tx_primary_use == TX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.tx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_aibif.word_align == WA_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.aib_word_align_dis == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.duplex_mode == DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.ehip_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.hi_ber_monitor == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.rx_ehip_mode == FORCE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.rx_primary_use == RX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.sys_clk_src == SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.tx_primary_use == TX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch15_25g.gdr_e4hip_pcs.xus_timer_window == 21'd806451
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.dfd_mux_reserved == DFD_RES_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.dfd_mux_sel == DFD_PRE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.dfd_node_sel == DFD_400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.testbus_ip_sel == TESTBUS_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.testbus_rx_tx_sel == TESTBUS_TX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.tx_fifo_lat_pulse_sel == LPHY_LAT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.ehip_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch1_25g.gdr_e4hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.dfd_mux_reserved == DFD_RES_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.dfd_mux_sel == DFD_PRE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.dfd_node_sel == DFD_400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.testbus_ip_sel == TESTBUS_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.testbus_rx_tx_sel == TESTBUS_TX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.tx_fifo_lat_pulse_sel == LPHY_LAT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.ehip_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_25g.gdr_e4hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.dfd_mux_reserved == DFD_RES_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.dfd_mux_sel == DFD_PRE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.dfd_node_sel == DFD_400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.testbus_ip_sel == TESTBUS_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.testbus_rx_tx_sel == TESTBUS_TX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.tx_fifo_lat_pulse_sel == LPHY_LAT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.ehip_rate == RATE_50G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch2_50g.gdr_e4hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.dfd_mux_reserved == DFD_RES_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.dfd_mux_sel == DFD_PRE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.dfd_node_sel == DFD_400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.testbus_ip_sel == TESTBUS_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.testbus_rx_tx_sel == TESTBUS_TX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.tx_fifo_lat_pulse_sel == LPHY_LAT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.ehip_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch3_25g.gdr_e4hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.dfd_mux_reserved == DFD_RES_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.dfd_mux_sel == DFD_PRE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.dfd_node_sel == DFD_400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.testbus_ip_sel == TESTBUS_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.testbus_rx_tx_sel == TESTBUS_TX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.tx_fifo_lat_pulse_sel == LPHY_LAT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.ehip_rate == RATE_100G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_100g.gdr_e4hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.dfd_mux_reserved == DFD_RES_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.dfd_mux_sel == DFD_PRE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.dfd_node_sel == DFD_400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.testbus_ip_sel == TESTBUS_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.testbus_rx_tx_sel == TESTBUS_TX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.tx_fifo_lat_pulse_sel == LPHY_LAT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.ehip_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_25g.gdr_e4hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.dfd_mux_reserved == DFD_RES_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.dfd_mux_sel == DFD_PRE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.dfd_node_sel == DFD_400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.testbus_ip_sel == TESTBUS_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.testbus_rx_tx_sel == TESTBUS_TX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.tx_fifo_lat_pulse_sel == LPHY_LAT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.ehip_rate == RATE_50G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch4_50g.gdr_e4hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.dfd_mux_reserved == DFD_RES_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.dfd_mux_sel == DFD_PRE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.dfd_node_sel == DFD_400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.testbus_ip_sel == TESTBUS_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.testbus_rx_tx_sel == TESTBUS_TX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.tx_fifo_lat_pulse_sel == LPHY_LAT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.ehip_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch5_25g.gdr_e4hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.dfd_mux_reserved == DFD_RES_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.dfd_mux_sel == DFD_PRE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.dfd_node_sel == DFD_400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.testbus_ip_sel == TESTBUS_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.testbus_rx_tx_sel == TESTBUS_TX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.tx_fifo_lat_pulse_sel == LPHY_LAT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.ehip_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_25g.gdr_e4hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.dfd_mux_reserved == DFD_RES_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.dfd_mux_sel == DFD_PRE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.dfd_node_sel == DFD_400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.testbus_ip_sel == TESTBUS_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.testbus_rx_tx_sel == TESTBUS_TX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.tx_fifo_lat_pulse_sel == LPHY_LAT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.ehip_rate == RATE_50G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch6_50g.gdr_e4hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_40G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.dfd_mux_reserved == DFD_RES_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.dfd_mux_sel == DFD_PRE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.dfd_node_sel == DFD_400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.duplex_mode == DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.rx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.rx_primary_use == RX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.rx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.sys_clk_src == SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.testbus_ip_sel == TESTBUS_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.testbus_rx_tx_sel == TESTBUS_TX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.tx_fifo_lat_pulse_sel == LPHY_LAT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_aibif.word_align == WA_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.aib_word_align_dis == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.duplex_mode == DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.ehip_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.hi_ber_monitor == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.rx_ehip_mode == FORCE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.rx_primary_use == RX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.sys_clk_src == SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch7_25g.gdr_e4hip_pcs.xus_timer_window == 21'd806451
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.dfd_mux_reserved == DFD_RES_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.dfd_mux_sel == DFD_PRE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.dfd_node_sel == DFD_400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.testbus_ip_sel == TESTBUS_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.testbus_rx_tx_sel == TESTBUS_TX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.tx_fifo_lat_pulse_sel == LPHY_LAT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.ehip_rate == RATE_100G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_100g.gdr_e4hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.dfd_mux_reserved == DFD_RES_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.dfd_mux_sel == DFD_PRE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.dfd_node_sel == DFD_400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.testbus_ip_sel == TESTBUS_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.testbus_rx_tx_sel == TESTBUS_TX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.tx_fifo_lat_pulse_sel == LPHY_LAT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.ehip_rate == RATE_200G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_200g.gdr_e4hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.dfd_mux_reserved == DFD_RES_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.dfd_mux_sel == DFD_PRE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.dfd_node_sel == DFD_400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.testbus_ip_sel == TESTBUS_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.testbus_rx_tx_sel == TESTBUS_TX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.tx_fifo_lat_pulse_sel == LPHY_LAT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.ehip_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_25g.gdr_e4hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.dfd_mux_reserved == DFD_RES_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.dfd_mux_sel == DFD_PRE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.dfd_node_sel == DFD_400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.fifo_rd_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.fifo_stop_wr == N_WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.fifo_wr_clk_scg_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.testbus_ip_sel == TESTBUS_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.testbus_rx_tx_sel == TESTBUS_TX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.tx_fifo_lat_pulse_sel == LPHY_LAT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_aibif.word_align == WA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.aib_word_align_dis == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.ehip_rate == RATE_50G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.hi_ber_monitor == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.rx_ehip_mode == USE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch8_50g.gdr_e4hip_pcs.xus_timer_window == 21'd201415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.aibif_data_valid == AIBIF_DATA_VALID_40G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.aibif_tx_bundle_enable == AIBIF_BUNDLE_TX_ENABLE_NOT_BUNDLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.aibif_tx_bundle_size == AIBIF_BUNDLE_TX_SIZE_BUNDLE_SIZE_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.dfd_mux_reserved == DFD_RES_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.dfd_mux_sel == DFD_PRE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.dfd_node_sel == DFD_400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.dsk_wait_count == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.duplex_mode == DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.ehip_mode_rx == EHIP_RX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.ehip_mode_tx == EHIP_TX_PMADIR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.enable_rx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.enable_tx_stats_snapshot == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.flowreg_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.force_hip_ready == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.force_tx_pld_deskew_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.lb_txmac_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.lb_txpcs_rxaib == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.mac_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.mac_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.overclk_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.pcs_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.pcs_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.ptp_clock_en_rx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.ptp_clock_en_tx == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.rx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.rx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.rx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.rx_primary_use == RX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.rx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.rx_system_bonding == RX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.rx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.sys_clk_src == SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.testbus_ip_sel == TESTBUS_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.testbus_rx_tx_sel == TESTBUS_TX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.tx_deskew_clear == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.tx_deskew_en == DISABLE_DESKEW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.tx_fifo_lat_pulse_sel == LPHY_LAT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.tx_mac_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.tx_pcs_in_rst == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.tx_pld_fifo_afull == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.tx_ro_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.tx_system_bonding == TX_SYSTEM_BONDING_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.txfifo_empty == EMPTY_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.txfifo_full == FULL_SW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.txfifo_pfull == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_aibif.word_align == WA_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.aib_word_align_dis == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.aib_word_align_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.aib_word_align_override_init_on_am_value == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.aib_word_align_override_init_value == ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.ber_invalid_count == 7'd97
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.check_random_idles == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.dis_descram_am_filter == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.duplex_mode == DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.ehip_rate == RATE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.ena_100g_blkalign_timeout_dis_elane_wa_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.ena_400g_hiber_to_mii_decoder_dis_elane_blksync_srst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.hi_ber_monitor == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.otn_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.pcs_ctrl_reserved == PCS_RESERVED_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.return_to_neutral == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.rx_aib_word_align_lfb_ena == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.rx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.rx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.rx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.rx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.rx_am_interval == NO_RX_AM_INTERVAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.rx_am_interval_msb == NO_RX_AM_INTERVAL_MSB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.rx_ehip_mode == FORCE_PCS_STATUS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.rx_pcs_max_skew == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.rx_primary_use == RX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.rx_use_aligner == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.rx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.rx_use_dsc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.rxpcsmux_sel == RX_LPHY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.select_rx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.select_tx_am == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.sys_clk_src == SYS_CLK_SRC_PLL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.tx_am_encoding_0 == 24'd9467463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.tx_am_encoding_1 == 24'd15779046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.tx_am_encoding_2 == 24'd12936603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.tx_am_encoding_3 == 24'd10647869
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.tx_ehip_mode == DIS_PTP_ECO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.tx_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.tx_use_enc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.tx_use_scr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.tx_use_striper == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.txpcsmux_sel == TX_MAC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.use_rx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.use_tx_50g == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_ch9_25g.gdr_e4hip_pcs.xus_timer_window == 21'd806451
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_p2p.fifo_rd_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_p2p.fifo_stop_rd == RD_EMPTY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_p2p.fifo_stop_wr == WR_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_p2p.fifo_wr_clk_scg_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_p2p.phcomp_rd_del == PHCOMP_RD_DEL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_p2p.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_p2p.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_PHASECOMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_p2p.tx_fifo_power_mode == FULL_WIDTH_HALF_DEPTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_config_p2p.word_align == WA_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.custom_cadence == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.dbg_bus_sel_1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.dbg_bus_sel_2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.dbg_bus_sel_3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.dbg_bus_sel_4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.dbg_bus_sel_dbg == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.flow_control == NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.flow_control_holdoff_mode == PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.flowreg_rate == FLOWREG_STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.link_fault_mode == LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.mac_lb_mode == NO_LOOPBACK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.mac_rate == STANDARD_100G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rate_mode == E400G_100G_0_MAC_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rst_rx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rst_tx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_ap_filter == NO_FILTERING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_dbg_pkt_n_ts_ctr == 20'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_fec_mode == RX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_phy_lane_num == E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_ui == E25G_X1_RX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_offset_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_offset_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_offset_10 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_offset_11 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_offset_12 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_offset_13 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_offset_14 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_offset_15 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_offset_16 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_offset_17 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_offset_18 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_offset_19 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_offset_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_offset_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_offset_4 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_offset_5 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_offset_6 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_offset_7 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_offset_8 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_offset_9 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_to_pl_0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_to_pl_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_to_pl_10 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_to_pl_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_to_pl_12 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_to_pl_13 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_to_pl_14 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_to_pl_15 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_to_pl_16 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_to_pl_17 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_to_pl_18 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_to_pl_19 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_to_pl_2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_to_pl_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_to_pl_4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_to_pl_5 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_to_pl_6 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_to_pl_7 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_to_pl_8 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_ptp_vl_to_pl_9 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.tx_am_period == NO_TX_AM_PERIOD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.tx_ipg_size == IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.tx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.tx_ptp_fec_mode == TX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.tx_ptp_phy_lane_num == E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.tx_ptp_ui == E25G_X1_TX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.tx_ptp_vl_offset_0 == E10G_25G_VL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.tx_ptp_vl_offset_1 == E10G_25G_VL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.tx_ptp_vl_offset_10 == E10G_25G_VL10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.tx_ptp_vl_offset_11 == E10G_25G_VL11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.tx_ptp_vl_offset_12 == E10G_25G_VL12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.tx_ptp_vl_offset_13 == E10G_25G_VL13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.tx_ptp_vl_offset_14 == E10G_25G_VL14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.tx_ptp_vl_offset_15 == E10G_25G_VL15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.tx_ptp_vl_offset_16 == E10G_25G_VL16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.tx_ptp_vl_offset_17 == E10G_25G_VL17
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.tx_ptp_vl_offset_18 == E10G_25G_VL18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.tx_ptp_vl_offset_19 == E10G_25G_VL19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.tx_ptp_vl_offset_2 == E10G_25G_VL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.tx_ptp_vl_offset_3 == E10G_25G_VL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.tx_ptp_vl_offset_4 == E10G_25G_VL4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.tx_ptp_vl_offset_5 == E10G_25G_VL5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.tx_ptp_vl_offset_6 == E10G_25G_VL6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.tx_ptp_vl_offset_7 == E10G_25G_VL7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.tx_ptp_vl_offset_8 == E10G_25G_VL8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.tx_ptp_vl_offset_9 == E10G_25G_VL9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_100g.use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.custom_cadence == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.dbg_bus_sel_1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.dbg_bus_sel_2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.dbg_bus_sel_3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.dbg_bus_sel_4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.dbg_bus_sel_dbg == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.flow_control == NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.flow_control_holdoff_mode == PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.flowreg_rate == FLOWREG_STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.link_fault_mode == LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.mac_lb_mode == NO_LOOPBACK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.mac_rate == STANDARD_200G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rate_mode == E400G_200G_0_MAC_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rst_rx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rst_tx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_ap_filter == NO_FILTERING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_dbg_pkt_n_ts_ctr == 20'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_fec_mode == RX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_phy_lane_num == E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_ui == E25G_X1_RX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_offset_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_offset_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_offset_10 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_offset_11 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_offset_12 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_offset_13 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_offset_14 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_offset_15 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_offset_16 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_offset_17 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_offset_18 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_offset_19 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_offset_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_offset_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_offset_4 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_offset_5 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_offset_6 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_offset_7 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_offset_8 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_offset_9 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_to_pl_0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_to_pl_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_to_pl_10 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_to_pl_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_to_pl_12 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_to_pl_13 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_to_pl_14 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_to_pl_15 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_to_pl_16 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_to_pl_17 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_to_pl_18 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_to_pl_19 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_to_pl_2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_to_pl_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_to_pl_4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_to_pl_5 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_to_pl_6 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_to_pl_7 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_to_pl_8 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_ptp_vl_to_pl_9 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.tx_am_period == NO_TX_AM_PERIOD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.tx_ipg_size == IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.tx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.tx_ptp_fec_mode == TX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.tx_ptp_phy_lane_num == E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.tx_ptp_ui == E25G_X1_TX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.tx_ptp_vl_offset_0 == E10G_25G_VL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.tx_ptp_vl_offset_1 == E10G_25G_VL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.tx_ptp_vl_offset_10 == E10G_25G_VL10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.tx_ptp_vl_offset_11 == E10G_25G_VL11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.tx_ptp_vl_offset_12 == E10G_25G_VL12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.tx_ptp_vl_offset_13 == E10G_25G_VL13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.tx_ptp_vl_offset_14 == E10G_25G_VL14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.tx_ptp_vl_offset_15 == E10G_25G_VL15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.tx_ptp_vl_offset_16 == E10G_25G_VL16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.tx_ptp_vl_offset_17 == E10G_25G_VL17
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.tx_ptp_vl_offset_18 == E10G_25G_VL18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.tx_ptp_vl_offset_19 == E10G_25G_VL19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.tx_ptp_vl_offset_2 == E10G_25G_VL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.tx_ptp_vl_offset_3 == E10G_25G_VL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.tx_ptp_vl_offset_4 == E10G_25G_VL4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.tx_ptp_vl_offset_5 == E10G_25G_VL5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.tx_ptp_vl_offset_6 == E10G_25G_VL6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.tx_ptp_vl_offset_7 == E10G_25G_VL7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.tx_ptp_vl_offset_8 == E10G_25G_VL8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.tx_ptp_vl_offset_9 == E10G_25G_VL9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_200g.use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.custom_cadence == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.dbg_bus_sel_1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.dbg_bus_sel_2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.dbg_bus_sel_3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.dbg_bus_sel_4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.dbg_bus_sel_dbg == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.flow_control == NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.flow_control_holdoff_mode == PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.flowreg_rate == FLOWREG_STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.link_fault_mode == LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.mac_lb_mode == NO_LOOPBACK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.mac_rate == STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rate_mode == E400G_25G_0_MAC_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rst_rx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rst_tx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_ap_filter == NO_FILTERING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_dbg_pkt_n_ts_ctr == 20'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_fec_mode == RX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_phy_lane_num == E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_ui == E25G_X1_RX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_offset_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_offset_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_offset_10 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_offset_11 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_offset_12 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_offset_13 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_offset_14 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_offset_15 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_offset_16 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_offset_17 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_offset_18 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_offset_19 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_offset_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_offset_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_offset_4 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_offset_5 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_offset_6 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_offset_7 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_offset_8 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_offset_9 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_to_pl_0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_to_pl_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_to_pl_10 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_to_pl_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_to_pl_12 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_to_pl_13 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_to_pl_14 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_to_pl_15 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_to_pl_16 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_to_pl_17 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_to_pl_18 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_to_pl_19 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_to_pl_2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_to_pl_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_to_pl_4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_to_pl_5 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_to_pl_6 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_to_pl_7 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_to_pl_8 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_ptp_vl_to_pl_9 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.tx_am_period == NO_TX_AM_PERIOD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.tx_ipg_size == IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.tx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.tx_ptp_fec_mode == TX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.tx_ptp_phy_lane_num == E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.tx_ptp_ui == E25G_X1_TX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.tx_ptp_vl_offset_0 == E10G_25G_VL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.tx_ptp_vl_offset_1 == E10G_25G_VL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.tx_ptp_vl_offset_10 == E10G_25G_VL10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.tx_ptp_vl_offset_11 == E10G_25G_VL11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.tx_ptp_vl_offset_12 == E10G_25G_VL12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.tx_ptp_vl_offset_13 == E10G_25G_VL13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.tx_ptp_vl_offset_14 == E10G_25G_VL14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.tx_ptp_vl_offset_15 == E10G_25G_VL15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.tx_ptp_vl_offset_16 == E10G_25G_VL16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.tx_ptp_vl_offset_17 == E10G_25G_VL17
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.tx_ptp_vl_offset_18 == E10G_25G_VL18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.tx_ptp_vl_offset_19 == E10G_25G_VL19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.tx_ptp_vl_offset_2 == E10G_25G_VL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.tx_ptp_vl_offset_3 == E10G_25G_VL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.tx_ptp_vl_offset_4 == E10G_25G_VL4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.tx_ptp_vl_offset_5 == E10G_25G_VL5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.tx_ptp_vl_offset_6 == E10G_25G_VL6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.tx_ptp_vl_offset_7 == E10G_25G_VL7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.tx_ptp_vl_offset_8 == E10G_25G_VL8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.tx_ptp_vl_offset_9 == E10G_25G_VL9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_25g.use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.custom_cadence == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.dbg_bus_sel_1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.dbg_bus_sel_2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.dbg_bus_sel_3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.dbg_bus_sel_4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.dbg_bus_sel_dbg == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.flow_control == NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.flow_control_holdoff_mode == PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.flowreg_rate == FLOWREG_STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.link_fault_mode == LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.mac_lb_mode == NO_LOOPBACK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.mac_rate == STANDARD_400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rate_mode == E400G_400G_MAC_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rst_rx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rst_tx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_ap_filter == NO_FILTERING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_dbg_pkt_n_ts_ctr == 20'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_fec_mode == RX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_phy_lane_num == E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_ui == E25G_X1_RX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_offset_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_offset_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_offset_10 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_offset_11 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_offset_12 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_offset_13 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_offset_14 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_offset_15 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_offset_16 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_offset_17 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_offset_18 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_offset_19 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_offset_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_offset_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_offset_4 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_offset_5 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_offset_6 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_offset_7 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_offset_8 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_offset_9 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_to_pl_0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_to_pl_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_to_pl_10 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_to_pl_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_to_pl_12 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_to_pl_13 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_to_pl_14 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_to_pl_15 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_to_pl_16 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_to_pl_17 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_to_pl_18 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_to_pl_19 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_to_pl_2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_to_pl_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_to_pl_4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_to_pl_5 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_to_pl_6 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_to_pl_7 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_to_pl_8 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_ptp_vl_to_pl_9 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.tx_am_period == NO_TX_AM_PERIOD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.tx_ipg_size == IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.tx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.tx_ptp_fec_mode == TX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.tx_ptp_phy_lane_num == E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.tx_ptp_ui == E25G_X1_TX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.tx_ptp_vl_offset_0 == E10G_25G_VL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.tx_ptp_vl_offset_1 == E10G_25G_VL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.tx_ptp_vl_offset_10 == E10G_25G_VL10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.tx_ptp_vl_offset_11 == E10G_25G_VL11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.tx_ptp_vl_offset_12 == E10G_25G_VL12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.tx_ptp_vl_offset_13 == E10G_25G_VL13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.tx_ptp_vl_offset_14 == E10G_25G_VL14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.tx_ptp_vl_offset_15 == E10G_25G_VL15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.tx_ptp_vl_offset_16 == E10G_25G_VL16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.tx_ptp_vl_offset_17 == E10G_25G_VL17
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.tx_ptp_vl_offset_18 == E10G_25G_VL18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.tx_ptp_vl_offset_19 == E10G_25G_VL19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.tx_ptp_vl_offset_2 == E10G_25G_VL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.tx_ptp_vl_offset_3 == E10G_25G_VL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.tx_ptp_vl_offset_4 == E10G_25G_VL4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.tx_ptp_vl_offset_5 == E10G_25G_VL5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.tx_ptp_vl_offset_6 == E10G_25G_VL6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.tx_ptp_vl_offset_7 == E10G_25G_VL7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.tx_ptp_vl_offset_8 == E10G_25G_VL8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.tx_ptp_vl_offset_9 == E10G_25G_VL9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_400g.use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.custom_cadence == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.dbg_bus_sel_1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.dbg_bus_sel_2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.dbg_bus_sel_3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.dbg_bus_sel_4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.dbg_bus_sel_dbg == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.flow_control == NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.flow_control_holdoff_mode == PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.flowreg_rate == FLOWREG_STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.link_fault_mode == LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.mac_lb_mode == NO_LOOPBACK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.mac_rate == STANDARD_50G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rate_mode == E400G_50G_0_MAC_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rst_rx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rst_tx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_ap_filter == NO_FILTERING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_dbg_pkt_n_ts_ctr == 20'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_fec_mode == RX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_phy_lane_num == E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_ui == E25G_X1_RX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_offset_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_offset_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_offset_10 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_offset_11 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_offset_12 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_offset_13 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_offset_14 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_offset_15 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_offset_16 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_offset_17 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_offset_18 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_offset_19 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_offset_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_offset_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_offset_4 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_offset_5 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_offset_6 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_offset_7 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_offset_8 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_offset_9 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_to_pl_0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_to_pl_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_to_pl_10 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_to_pl_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_to_pl_12 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_to_pl_13 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_to_pl_14 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_to_pl_15 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_to_pl_16 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_to_pl_17 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_to_pl_18 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_to_pl_19 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_to_pl_2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_to_pl_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_to_pl_4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_to_pl_5 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_to_pl_6 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_to_pl_7 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_to_pl_8 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_ptp_vl_to_pl_9 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.tx_am_period == NO_TX_AM_PERIOD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.tx_ipg_size == IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.tx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.tx_ptp_fec_mode == TX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.tx_ptp_phy_lane_num == E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.tx_ptp_ui == E25G_X1_TX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.tx_ptp_vl_offset_0 == E10G_25G_VL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.tx_ptp_vl_offset_1 == E10G_25G_VL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.tx_ptp_vl_offset_10 == E10G_25G_VL10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.tx_ptp_vl_offset_11 == E10G_25G_VL11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.tx_ptp_vl_offset_12 == E10G_25G_VL12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.tx_ptp_vl_offset_13 == E10G_25G_VL13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.tx_ptp_vl_offset_14 == E10G_25G_VL14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.tx_ptp_vl_offset_15 == E10G_25G_VL15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.tx_ptp_vl_offset_16 == E10G_25G_VL16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.tx_ptp_vl_offset_17 == E10G_25G_VL17
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.tx_ptp_vl_offset_18 == E10G_25G_VL18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.tx_ptp_vl_offset_19 == E10G_25G_VL19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.tx_ptp_vl_offset_2 == E10G_25G_VL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.tx_ptp_vl_offset_3 == E10G_25G_VL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.tx_ptp_vl_offset_4 == E10G_25G_VL4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.tx_ptp_vl_offset_5 == E10G_25G_VL5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.tx_ptp_vl_offset_6 == E10G_25G_VL6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.tx_ptp_vl_offset_7 == E10G_25G_VL7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.tx_ptp_vl_offset_8 == E10G_25G_VL8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.tx_ptp_vl_offset_9 == E10G_25G_VL9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch0_50g.use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.custom_cadence == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.dbg_bus_sel_1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.dbg_bus_sel_2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.dbg_bus_sel_3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.dbg_bus_sel_4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.dbg_bus_sel_dbg == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.flow_control == NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.flow_control_holdoff_mode == PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.flowreg_rate == FLOWREG_STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.link_fault_mode == LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.mac_lb_mode == NO_LOOPBACK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.mac_rate == STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rate_mode == E400G_25G_10_MAC_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rst_rx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rst_tx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_ap_filter == NO_FILTERING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_dbg_pkt_n_ts_ctr == 20'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_fec_mode == RX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_phy_lane_num == E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_ui == E25G_X1_RX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_offset_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_offset_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_offset_10 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_offset_11 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_offset_12 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_offset_13 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_offset_14 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_offset_15 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_offset_16 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_offset_17 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_offset_18 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_offset_19 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_offset_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_offset_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_offset_4 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_offset_5 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_offset_6 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_offset_7 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_offset_8 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_offset_9 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_to_pl_0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_to_pl_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_to_pl_10 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_to_pl_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_to_pl_12 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_to_pl_13 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_to_pl_14 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_to_pl_15 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_to_pl_16 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_to_pl_17 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_to_pl_18 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_to_pl_19 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_to_pl_2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_to_pl_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_to_pl_4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_to_pl_5 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_to_pl_6 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_to_pl_7 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_to_pl_8 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_ptp_vl_to_pl_9 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.tx_am_period == NO_TX_AM_PERIOD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.tx_ipg_size == IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.tx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.tx_ptp_fec_mode == TX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.tx_ptp_phy_lane_num == E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.tx_ptp_ui == E25G_X1_TX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.tx_ptp_vl_offset_0 == E10G_25G_VL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.tx_ptp_vl_offset_1 == E10G_25G_VL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.tx_ptp_vl_offset_10 == E10G_25G_VL10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.tx_ptp_vl_offset_11 == E10G_25G_VL11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.tx_ptp_vl_offset_12 == E10G_25G_VL12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.tx_ptp_vl_offset_13 == E10G_25G_VL13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.tx_ptp_vl_offset_14 == E10G_25G_VL14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.tx_ptp_vl_offset_15 == E10G_25G_VL15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.tx_ptp_vl_offset_16 == E10G_25G_VL16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.tx_ptp_vl_offset_17 == E10G_25G_VL17
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.tx_ptp_vl_offset_18 == E10G_25G_VL18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.tx_ptp_vl_offset_19 == E10G_25G_VL19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.tx_ptp_vl_offset_2 == E10G_25G_VL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.tx_ptp_vl_offset_3 == E10G_25G_VL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.tx_ptp_vl_offset_4 == E10G_25G_VL4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.tx_ptp_vl_offset_5 == E10G_25G_VL5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.tx_ptp_vl_offset_6 == E10G_25G_VL6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.tx_ptp_vl_offset_7 == E10G_25G_VL7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.tx_ptp_vl_offset_8 == E10G_25G_VL8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.tx_ptp_vl_offset_9 == E10G_25G_VL9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_25g.use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.custom_cadence == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.dbg_bus_sel_1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.dbg_bus_sel_2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.dbg_bus_sel_3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.dbg_bus_sel_4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.dbg_bus_sel_dbg == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.flow_control == NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.flow_control_holdoff_mode == PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.flowreg_rate == FLOWREG_STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.link_fault_mode == LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.mac_lb_mode == NO_LOOPBACK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.mac_rate == STANDARD_50G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rate_mode == E400G_50G_5_MAC_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rst_rx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rst_tx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_ap_filter == NO_FILTERING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_dbg_pkt_n_ts_ctr == 20'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_fec_mode == RX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_phy_lane_num == E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_ui == E25G_X1_RX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_offset_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_offset_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_offset_10 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_offset_11 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_offset_12 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_offset_13 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_offset_14 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_offset_15 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_offset_16 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_offset_17 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_offset_18 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_offset_19 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_offset_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_offset_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_offset_4 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_offset_5 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_offset_6 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_offset_7 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_offset_8 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_offset_9 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_to_pl_0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_to_pl_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_to_pl_10 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_to_pl_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_to_pl_12 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_to_pl_13 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_to_pl_14 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_to_pl_15 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_to_pl_16 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_to_pl_17 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_to_pl_18 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_to_pl_19 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_to_pl_2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_to_pl_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_to_pl_4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_to_pl_5 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_to_pl_6 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_to_pl_7 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_to_pl_8 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_ptp_vl_to_pl_9 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.tx_am_period == NO_TX_AM_PERIOD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.tx_ipg_size == IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.tx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.tx_ptp_fec_mode == TX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.tx_ptp_phy_lane_num == E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.tx_ptp_ui == E25G_X1_TX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.tx_ptp_vl_offset_0 == E10G_25G_VL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.tx_ptp_vl_offset_1 == E10G_25G_VL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.tx_ptp_vl_offset_10 == E10G_25G_VL10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.tx_ptp_vl_offset_11 == E10G_25G_VL11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.tx_ptp_vl_offset_12 == E10G_25G_VL12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.tx_ptp_vl_offset_13 == E10G_25G_VL13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.tx_ptp_vl_offset_14 == E10G_25G_VL14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.tx_ptp_vl_offset_15 == E10G_25G_VL15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.tx_ptp_vl_offset_16 == E10G_25G_VL16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.tx_ptp_vl_offset_17 == E10G_25G_VL17
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.tx_ptp_vl_offset_18 == E10G_25G_VL18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.tx_ptp_vl_offset_19 == E10G_25G_VL19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.tx_ptp_vl_offset_2 == E10G_25G_VL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.tx_ptp_vl_offset_3 == E10G_25G_VL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.tx_ptp_vl_offset_4 == E10G_25G_VL4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.tx_ptp_vl_offset_5 == E10G_25G_VL5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.tx_ptp_vl_offset_6 == E10G_25G_VL6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.tx_ptp_vl_offset_7 == E10G_25G_VL7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.tx_ptp_vl_offset_8 == E10G_25G_VL8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.tx_ptp_vl_offset_9 == E10G_25G_VL9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch10_50g.use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.custom_cadence == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.dbg_bus_sel_1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.dbg_bus_sel_2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.dbg_bus_sel_3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.dbg_bus_sel_4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.dbg_bus_sel_dbg == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.flow_control == NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.flow_control_holdoff_mode == PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.flowreg_rate == FLOWREG_STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.link_fault_mode == LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.mac_lb_mode == NO_LOOPBACK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.mac_rate == STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rate_mode == E400G_25G_11_MAC_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rst_rx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rst_tx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_ap_filter == NO_FILTERING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_dbg_pkt_n_ts_ctr == 20'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_fec_mode == RX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_phy_lane_num == E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_ui == E25G_X1_RX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_offset_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_offset_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_offset_10 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_offset_11 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_offset_12 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_offset_13 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_offset_14 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_offset_15 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_offset_16 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_offset_17 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_offset_18 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_offset_19 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_offset_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_offset_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_offset_4 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_offset_5 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_offset_6 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_offset_7 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_offset_8 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_offset_9 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_to_pl_0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_to_pl_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_to_pl_10 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_to_pl_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_to_pl_12 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_to_pl_13 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_to_pl_14 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_to_pl_15 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_to_pl_16 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_to_pl_17 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_to_pl_18 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_to_pl_19 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_to_pl_2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_to_pl_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_to_pl_4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_to_pl_5 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_to_pl_6 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_to_pl_7 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_to_pl_8 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_ptp_vl_to_pl_9 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.tx_am_period == NO_TX_AM_PERIOD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.tx_ipg_size == IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.tx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.tx_ptp_fec_mode == TX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.tx_ptp_phy_lane_num == E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.tx_ptp_ui == E25G_X1_TX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.tx_ptp_vl_offset_0 == E10G_25G_VL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.tx_ptp_vl_offset_1 == E10G_25G_VL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.tx_ptp_vl_offset_10 == E10G_25G_VL10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.tx_ptp_vl_offset_11 == E10G_25G_VL11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.tx_ptp_vl_offset_12 == E10G_25G_VL12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.tx_ptp_vl_offset_13 == E10G_25G_VL13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.tx_ptp_vl_offset_14 == E10G_25G_VL14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.tx_ptp_vl_offset_15 == E10G_25G_VL15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.tx_ptp_vl_offset_16 == E10G_25G_VL16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.tx_ptp_vl_offset_17 == E10G_25G_VL17
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.tx_ptp_vl_offset_18 == E10G_25G_VL18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.tx_ptp_vl_offset_19 == E10G_25G_VL19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.tx_ptp_vl_offset_2 == E10G_25G_VL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.tx_ptp_vl_offset_3 == E10G_25G_VL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.tx_ptp_vl_offset_4 == E10G_25G_VL4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.tx_ptp_vl_offset_5 == E10G_25G_VL5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.tx_ptp_vl_offset_6 == E10G_25G_VL6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.tx_ptp_vl_offset_7 == E10G_25G_VL7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.tx_ptp_vl_offset_8 == E10G_25G_VL8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.tx_ptp_vl_offset_9 == E10G_25G_VL9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch11_25g.use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.custom_cadence == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.dbg_bus_sel_1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.dbg_bus_sel_2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.dbg_bus_sel_3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.dbg_bus_sel_4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.dbg_bus_sel_dbg == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.flow_control == NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.flow_control_holdoff_mode == PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.flowreg_rate == FLOWREG_STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.link_fault_mode == LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.mac_lb_mode == NO_LOOPBACK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.mac_rate == STANDARD_100G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rate_mode == E400G_100G_3_MAC_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rst_rx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rst_tx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_ap_filter == NO_FILTERING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_dbg_pkt_n_ts_ctr == 20'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_fec_mode == RX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_phy_lane_num == E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_ui == E25G_X1_RX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_offset_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_offset_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_offset_10 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_offset_11 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_offset_12 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_offset_13 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_offset_14 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_offset_15 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_offset_16 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_offset_17 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_offset_18 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_offset_19 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_offset_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_offset_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_offset_4 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_offset_5 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_offset_6 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_offset_7 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_offset_8 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_offset_9 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_to_pl_0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_to_pl_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_to_pl_10 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_to_pl_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_to_pl_12 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_to_pl_13 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_to_pl_14 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_to_pl_15 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_to_pl_16 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_to_pl_17 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_to_pl_18 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_to_pl_19 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_to_pl_2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_to_pl_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_to_pl_4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_to_pl_5 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_to_pl_6 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_to_pl_7 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_to_pl_8 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_ptp_vl_to_pl_9 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.tx_am_period == NO_TX_AM_PERIOD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.tx_ipg_size == IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.tx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.tx_ptp_fec_mode == TX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.tx_ptp_phy_lane_num == E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.tx_ptp_ui == E25G_X1_TX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.tx_ptp_vl_offset_0 == E10G_25G_VL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.tx_ptp_vl_offset_1 == E10G_25G_VL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.tx_ptp_vl_offset_10 == E10G_25G_VL10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.tx_ptp_vl_offset_11 == E10G_25G_VL11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.tx_ptp_vl_offset_12 == E10G_25G_VL12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.tx_ptp_vl_offset_13 == E10G_25G_VL13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.tx_ptp_vl_offset_14 == E10G_25G_VL14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.tx_ptp_vl_offset_15 == E10G_25G_VL15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.tx_ptp_vl_offset_16 == E10G_25G_VL16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.tx_ptp_vl_offset_17 == E10G_25G_VL17
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.tx_ptp_vl_offset_18 == E10G_25G_VL18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.tx_ptp_vl_offset_19 == E10G_25G_VL19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.tx_ptp_vl_offset_2 == E10G_25G_VL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.tx_ptp_vl_offset_3 == E10G_25G_VL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.tx_ptp_vl_offset_4 == E10G_25G_VL4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.tx_ptp_vl_offset_5 == E10G_25G_VL5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.tx_ptp_vl_offset_6 == E10G_25G_VL6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.tx_ptp_vl_offset_7 == E10G_25G_VL7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.tx_ptp_vl_offset_8 == E10G_25G_VL8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.tx_ptp_vl_offset_9 == E10G_25G_VL9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_100g.use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.custom_cadence == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.dbg_bus_sel_1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.dbg_bus_sel_2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.dbg_bus_sel_3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.dbg_bus_sel_4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.dbg_bus_sel_dbg == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.flow_control == NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.flow_control_holdoff_mode == PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.flowreg_rate == FLOWREG_STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.link_fault_mode == LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.mac_lb_mode == NO_LOOPBACK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.mac_rate == STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rate_mode == E400G_25G_12_MAC_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rst_rx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rst_tx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_ap_filter == NO_FILTERING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_dbg_pkt_n_ts_ctr == 20'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_fec_mode == RX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_phy_lane_num == E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_ui == E25G_X1_RX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_offset_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_offset_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_offset_10 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_offset_11 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_offset_12 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_offset_13 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_offset_14 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_offset_15 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_offset_16 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_offset_17 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_offset_18 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_offset_19 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_offset_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_offset_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_offset_4 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_offset_5 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_offset_6 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_offset_7 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_offset_8 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_offset_9 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_to_pl_0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_to_pl_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_to_pl_10 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_to_pl_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_to_pl_12 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_to_pl_13 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_to_pl_14 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_to_pl_15 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_to_pl_16 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_to_pl_17 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_to_pl_18 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_to_pl_19 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_to_pl_2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_to_pl_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_to_pl_4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_to_pl_5 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_to_pl_6 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_to_pl_7 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_to_pl_8 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_ptp_vl_to_pl_9 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.tx_am_period == NO_TX_AM_PERIOD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.tx_ipg_size == IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.tx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.tx_ptp_fec_mode == TX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.tx_ptp_phy_lane_num == E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.tx_ptp_ui == E25G_X1_TX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.tx_ptp_vl_offset_0 == E10G_25G_VL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.tx_ptp_vl_offset_1 == E10G_25G_VL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.tx_ptp_vl_offset_10 == E10G_25G_VL10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.tx_ptp_vl_offset_11 == E10G_25G_VL11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.tx_ptp_vl_offset_12 == E10G_25G_VL12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.tx_ptp_vl_offset_13 == E10G_25G_VL13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.tx_ptp_vl_offset_14 == E10G_25G_VL14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.tx_ptp_vl_offset_15 == E10G_25G_VL15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.tx_ptp_vl_offset_16 == E10G_25G_VL16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.tx_ptp_vl_offset_17 == E10G_25G_VL17
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.tx_ptp_vl_offset_18 == E10G_25G_VL18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.tx_ptp_vl_offset_19 == E10G_25G_VL19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.tx_ptp_vl_offset_2 == E10G_25G_VL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.tx_ptp_vl_offset_3 == E10G_25G_VL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.tx_ptp_vl_offset_4 == E10G_25G_VL4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.tx_ptp_vl_offset_5 == E10G_25G_VL5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.tx_ptp_vl_offset_6 == E10G_25G_VL6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.tx_ptp_vl_offset_7 == E10G_25G_VL7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.tx_ptp_vl_offset_8 == E10G_25G_VL8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.tx_ptp_vl_offset_9 == E10G_25G_VL9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_25g.use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.custom_cadence == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.dbg_bus_sel_1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.dbg_bus_sel_2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.dbg_bus_sel_3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.dbg_bus_sel_4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.dbg_bus_sel_dbg == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.flow_control == NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.flow_control_holdoff_mode == PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.flowreg_rate == FLOWREG_STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.link_fault_mode == LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.mac_lb_mode == NO_LOOPBACK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.mac_rate == STANDARD_50G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rate_mode == E400G_50G_6_MAC_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rst_rx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rst_tx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_ap_filter == NO_FILTERING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_dbg_pkt_n_ts_ctr == 20'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_fec_mode == RX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_phy_lane_num == E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_ui == E25G_X1_RX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_offset_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_offset_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_offset_10 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_offset_11 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_offset_12 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_offset_13 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_offset_14 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_offset_15 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_offset_16 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_offset_17 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_offset_18 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_offset_19 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_offset_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_offset_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_offset_4 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_offset_5 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_offset_6 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_offset_7 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_offset_8 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_offset_9 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_to_pl_0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_to_pl_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_to_pl_10 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_to_pl_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_to_pl_12 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_to_pl_13 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_to_pl_14 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_to_pl_15 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_to_pl_16 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_to_pl_17 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_to_pl_18 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_to_pl_19 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_to_pl_2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_to_pl_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_to_pl_4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_to_pl_5 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_to_pl_6 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_to_pl_7 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_to_pl_8 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_ptp_vl_to_pl_9 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.tx_am_period == NO_TX_AM_PERIOD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.tx_ipg_size == IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.tx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.tx_ptp_fec_mode == TX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.tx_ptp_phy_lane_num == E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.tx_ptp_ui == E25G_X1_TX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.tx_ptp_vl_offset_0 == E10G_25G_VL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.tx_ptp_vl_offset_1 == E10G_25G_VL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.tx_ptp_vl_offset_10 == E10G_25G_VL10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.tx_ptp_vl_offset_11 == E10G_25G_VL11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.tx_ptp_vl_offset_12 == E10G_25G_VL12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.tx_ptp_vl_offset_13 == E10G_25G_VL13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.tx_ptp_vl_offset_14 == E10G_25G_VL14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.tx_ptp_vl_offset_15 == E10G_25G_VL15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.tx_ptp_vl_offset_16 == E10G_25G_VL16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.tx_ptp_vl_offset_17 == E10G_25G_VL17
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.tx_ptp_vl_offset_18 == E10G_25G_VL18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.tx_ptp_vl_offset_19 == E10G_25G_VL19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.tx_ptp_vl_offset_2 == E10G_25G_VL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.tx_ptp_vl_offset_3 == E10G_25G_VL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.tx_ptp_vl_offset_4 == E10G_25G_VL4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.tx_ptp_vl_offset_5 == E10G_25G_VL5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.tx_ptp_vl_offset_6 == E10G_25G_VL6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.tx_ptp_vl_offset_7 == E10G_25G_VL7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.tx_ptp_vl_offset_8 == E10G_25G_VL8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.tx_ptp_vl_offset_9 == E10G_25G_VL9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch12_50g.use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.custom_cadence == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.dbg_bus_sel_1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.dbg_bus_sel_2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.dbg_bus_sel_3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.dbg_bus_sel_4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.dbg_bus_sel_dbg == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.flow_control == NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.flow_control_holdoff_mode == PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.flowreg_rate == FLOWREG_STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.link_fault_mode == LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.mac_lb_mode == NO_LOOPBACK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.mac_rate == STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rate_mode == E400G_25G_13_MAC_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rst_rx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rst_tx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_ap_filter == NO_FILTERING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_dbg_pkt_n_ts_ctr == 20'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_fec_mode == RX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_phy_lane_num == E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_ui == E25G_X1_RX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_offset_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_offset_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_offset_10 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_offset_11 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_offset_12 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_offset_13 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_offset_14 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_offset_15 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_offset_16 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_offset_17 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_offset_18 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_offset_19 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_offset_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_offset_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_offset_4 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_offset_5 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_offset_6 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_offset_7 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_offset_8 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_offset_9 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_to_pl_0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_to_pl_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_to_pl_10 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_to_pl_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_to_pl_12 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_to_pl_13 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_to_pl_14 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_to_pl_15 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_to_pl_16 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_to_pl_17 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_to_pl_18 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_to_pl_19 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_to_pl_2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_to_pl_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_to_pl_4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_to_pl_5 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_to_pl_6 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_to_pl_7 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_to_pl_8 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_ptp_vl_to_pl_9 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.tx_am_period == NO_TX_AM_PERIOD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.tx_ipg_size == IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.tx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.tx_ptp_fec_mode == TX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.tx_ptp_phy_lane_num == E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.tx_ptp_ui == E25G_X1_TX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.tx_ptp_vl_offset_0 == E10G_25G_VL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.tx_ptp_vl_offset_1 == E10G_25G_VL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.tx_ptp_vl_offset_10 == E10G_25G_VL10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.tx_ptp_vl_offset_11 == E10G_25G_VL11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.tx_ptp_vl_offset_12 == E10G_25G_VL12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.tx_ptp_vl_offset_13 == E10G_25G_VL13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.tx_ptp_vl_offset_14 == E10G_25G_VL14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.tx_ptp_vl_offset_15 == E10G_25G_VL15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.tx_ptp_vl_offset_16 == E10G_25G_VL16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.tx_ptp_vl_offset_17 == E10G_25G_VL17
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.tx_ptp_vl_offset_18 == E10G_25G_VL18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.tx_ptp_vl_offset_19 == E10G_25G_VL19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.tx_ptp_vl_offset_2 == E10G_25G_VL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.tx_ptp_vl_offset_3 == E10G_25G_VL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.tx_ptp_vl_offset_4 == E10G_25G_VL4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.tx_ptp_vl_offset_5 == E10G_25G_VL5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.tx_ptp_vl_offset_6 == E10G_25G_VL6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.tx_ptp_vl_offset_7 == E10G_25G_VL7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.tx_ptp_vl_offset_8 == E10G_25G_VL8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.tx_ptp_vl_offset_9 == E10G_25G_VL9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch13_25g.use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.custom_cadence == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.dbg_bus_sel_1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.dbg_bus_sel_2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.dbg_bus_sel_3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.dbg_bus_sel_4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.dbg_bus_sel_dbg == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.flow_control == NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.flow_control_holdoff_mode == PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.flowreg_rate == FLOWREG_STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.link_fault_mode == LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.mac_lb_mode == NO_LOOPBACK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.mac_rate == STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rate_mode == E400G_25G_14_MAC_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rst_rx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rst_tx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_ap_filter == NO_FILTERING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_dbg_pkt_n_ts_ctr == 20'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_fec_mode == RX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_phy_lane_num == E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_ui == E25G_X1_RX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_offset_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_offset_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_offset_10 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_offset_11 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_offset_12 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_offset_13 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_offset_14 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_offset_15 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_offset_16 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_offset_17 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_offset_18 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_offset_19 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_offset_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_offset_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_offset_4 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_offset_5 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_offset_6 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_offset_7 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_offset_8 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_offset_9 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_to_pl_0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_to_pl_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_to_pl_10 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_to_pl_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_to_pl_12 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_to_pl_13 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_to_pl_14 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_to_pl_15 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_to_pl_16 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_to_pl_17 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_to_pl_18 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_to_pl_19 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_to_pl_2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_to_pl_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_to_pl_4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_to_pl_5 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_to_pl_6 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_to_pl_7 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_to_pl_8 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_ptp_vl_to_pl_9 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.tx_am_period == NO_TX_AM_PERIOD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.tx_ipg_size == IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.tx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.tx_ptp_fec_mode == TX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.tx_ptp_phy_lane_num == E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.tx_ptp_ui == E25G_X1_TX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.tx_ptp_vl_offset_0 == E10G_25G_VL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.tx_ptp_vl_offset_1 == E10G_25G_VL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.tx_ptp_vl_offset_10 == E10G_25G_VL10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.tx_ptp_vl_offset_11 == E10G_25G_VL11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.tx_ptp_vl_offset_12 == E10G_25G_VL12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.tx_ptp_vl_offset_13 == E10G_25G_VL13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.tx_ptp_vl_offset_14 == E10G_25G_VL14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.tx_ptp_vl_offset_15 == E10G_25G_VL15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.tx_ptp_vl_offset_16 == E10G_25G_VL16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.tx_ptp_vl_offset_17 == E10G_25G_VL17
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.tx_ptp_vl_offset_18 == E10G_25G_VL18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.tx_ptp_vl_offset_19 == E10G_25G_VL19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.tx_ptp_vl_offset_2 == E10G_25G_VL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.tx_ptp_vl_offset_3 == E10G_25G_VL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.tx_ptp_vl_offset_4 == E10G_25G_VL4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.tx_ptp_vl_offset_5 == E10G_25G_VL5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.tx_ptp_vl_offset_6 == E10G_25G_VL6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.tx_ptp_vl_offset_7 == E10G_25G_VL7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.tx_ptp_vl_offset_8 == E10G_25G_VL8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.tx_ptp_vl_offset_9 == E10G_25G_VL9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_25g.use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.custom_cadence == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.dbg_bus_sel_1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.dbg_bus_sel_2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.dbg_bus_sel_3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.dbg_bus_sel_4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.dbg_bus_sel_dbg == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.flow_control == NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.flow_control_holdoff_mode == PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.flowreg_rate == FLOWREG_STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.link_fault_mode == LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.mac_lb_mode == NO_LOOPBACK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.mac_rate == STANDARD_50G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rate_mode == E400G_50G_7_MAC_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rst_rx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rst_tx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_ap_filter == NO_FILTERING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_dbg_pkt_n_ts_ctr == 20'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_fec_mode == RX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_phy_lane_num == E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_ui == E25G_X1_RX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_offset_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_offset_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_offset_10 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_offset_11 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_offset_12 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_offset_13 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_offset_14 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_offset_15 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_offset_16 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_offset_17 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_offset_18 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_offset_19 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_offset_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_offset_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_offset_4 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_offset_5 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_offset_6 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_offset_7 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_offset_8 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_offset_9 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_to_pl_0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_to_pl_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_to_pl_10 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_to_pl_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_to_pl_12 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_to_pl_13 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_to_pl_14 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_to_pl_15 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_to_pl_16 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_to_pl_17 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_to_pl_18 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_to_pl_19 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_to_pl_2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_to_pl_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_to_pl_4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_to_pl_5 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_to_pl_6 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_to_pl_7 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_to_pl_8 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_ptp_vl_to_pl_9 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.tx_am_period == NO_TX_AM_PERIOD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.tx_ipg_size == IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.tx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.tx_ptp_fec_mode == TX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.tx_ptp_phy_lane_num == E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.tx_ptp_ui == E25G_X1_TX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.tx_ptp_vl_offset_0 == E10G_25G_VL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.tx_ptp_vl_offset_1 == E10G_25G_VL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.tx_ptp_vl_offset_10 == E10G_25G_VL10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.tx_ptp_vl_offset_11 == E10G_25G_VL11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.tx_ptp_vl_offset_12 == E10G_25G_VL12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.tx_ptp_vl_offset_13 == E10G_25G_VL13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.tx_ptp_vl_offset_14 == E10G_25G_VL14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.tx_ptp_vl_offset_15 == E10G_25G_VL15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.tx_ptp_vl_offset_16 == E10G_25G_VL16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.tx_ptp_vl_offset_17 == E10G_25G_VL17
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.tx_ptp_vl_offset_18 == E10G_25G_VL18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.tx_ptp_vl_offset_19 == E10G_25G_VL19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.tx_ptp_vl_offset_2 == E10G_25G_VL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.tx_ptp_vl_offset_3 == E10G_25G_VL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.tx_ptp_vl_offset_4 == E10G_25G_VL4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.tx_ptp_vl_offset_5 == E10G_25G_VL5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.tx_ptp_vl_offset_6 == E10G_25G_VL6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.tx_ptp_vl_offset_7 == E10G_25G_VL7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.tx_ptp_vl_offset_8 == E10G_25G_VL8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.tx_ptp_vl_offset_9 == E10G_25G_VL9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch14_50g.use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.custom_cadence == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.dbg_bus_sel_1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.dbg_bus_sel_2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.dbg_bus_sel_3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.dbg_bus_sel_4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.dbg_bus_sel_dbg == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.flow_control == NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.flow_control_holdoff_mode == PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.flowreg_rate == FLOWREG_STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.link_fault_mode == LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.mac_lb_mode == NO_LOOPBACK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.mac_rate == STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rate_mode == E400G_25G_15_MAC_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rst_rx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rst_tx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_ap_filter == NO_FILTERING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_dbg_pkt_n_ts_ctr == 20'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_fec_mode == RX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_phy_lane_num == E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_ui == E25G_X1_RX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_offset_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_offset_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_offset_10 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_offset_11 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_offset_12 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_offset_13 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_offset_14 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_offset_15 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_offset_16 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_offset_17 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_offset_18 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_offset_19 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_offset_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_offset_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_offset_4 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_offset_5 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_offset_6 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_offset_7 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_offset_8 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_offset_9 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_to_pl_0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_to_pl_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_to_pl_10 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_to_pl_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_to_pl_12 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_to_pl_13 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_to_pl_14 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_to_pl_15 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_to_pl_16 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_to_pl_17 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_to_pl_18 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_to_pl_19 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_to_pl_2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_to_pl_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_to_pl_4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_to_pl_5 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_to_pl_6 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_to_pl_7 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_to_pl_8 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_ptp_vl_to_pl_9 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.tx_am_period == NO_TX_AM_PERIOD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.tx_ipg_size == IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.tx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.tx_ptp_fec_mode == TX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.tx_ptp_phy_lane_num == E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.tx_ptp_ui == E25G_X1_TX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.tx_ptp_vl_offset_0 == E10G_25G_VL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.tx_ptp_vl_offset_1 == E10G_25G_VL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.tx_ptp_vl_offset_10 == E10G_25G_VL10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.tx_ptp_vl_offset_11 == E10G_25G_VL11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.tx_ptp_vl_offset_12 == E10G_25G_VL12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.tx_ptp_vl_offset_13 == E10G_25G_VL13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.tx_ptp_vl_offset_14 == E10G_25G_VL14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.tx_ptp_vl_offset_15 == E10G_25G_VL15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.tx_ptp_vl_offset_16 == E10G_25G_VL16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.tx_ptp_vl_offset_17 == E10G_25G_VL17
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.tx_ptp_vl_offset_18 == E10G_25G_VL18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.tx_ptp_vl_offset_19 == E10G_25G_VL19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.tx_ptp_vl_offset_2 == E10G_25G_VL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.tx_ptp_vl_offset_3 == E10G_25G_VL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.tx_ptp_vl_offset_4 == E10G_25G_VL4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.tx_ptp_vl_offset_5 == E10G_25G_VL5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.tx_ptp_vl_offset_6 == E10G_25G_VL6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.tx_ptp_vl_offset_7 == E10G_25G_VL7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.tx_ptp_vl_offset_8 == E10G_25G_VL8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.tx_ptp_vl_offset_9 == E10G_25G_VL9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch15_25g.use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.custom_cadence == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.dbg_bus_sel_1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.dbg_bus_sel_2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.dbg_bus_sel_3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.dbg_bus_sel_4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.dbg_bus_sel_dbg == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.flow_control == NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.flow_control_holdoff_mode == PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.flowreg_rate == FLOWREG_STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.link_fault_mode == LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.mac_lb_mode == NO_LOOPBACK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.mac_rate == STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rate_mode == E400G_25G_1_MAC_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rst_rx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rst_tx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_ap_filter == NO_FILTERING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_dbg_pkt_n_ts_ctr == 20'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_fec_mode == RX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_phy_lane_num == E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_ui == E25G_X1_RX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_offset_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_offset_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_offset_10 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_offset_11 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_offset_12 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_offset_13 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_offset_14 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_offset_15 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_offset_16 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_offset_17 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_offset_18 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_offset_19 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_offset_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_offset_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_offset_4 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_offset_5 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_offset_6 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_offset_7 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_offset_8 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_offset_9 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_to_pl_0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_to_pl_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_to_pl_10 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_to_pl_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_to_pl_12 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_to_pl_13 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_to_pl_14 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_to_pl_15 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_to_pl_16 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_to_pl_17 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_to_pl_18 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_to_pl_19 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_to_pl_2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_to_pl_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_to_pl_4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_to_pl_5 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_to_pl_6 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_to_pl_7 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_to_pl_8 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_ptp_vl_to_pl_9 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.tx_am_period == NO_TX_AM_PERIOD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.tx_ipg_size == IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.tx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.tx_ptp_fec_mode == TX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.tx_ptp_phy_lane_num == E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.tx_ptp_ui == E25G_X1_TX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.tx_ptp_vl_offset_0 == E10G_25G_VL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.tx_ptp_vl_offset_1 == E10G_25G_VL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.tx_ptp_vl_offset_10 == E10G_25G_VL10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.tx_ptp_vl_offset_11 == E10G_25G_VL11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.tx_ptp_vl_offset_12 == E10G_25G_VL12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.tx_ptp_vl_offset_13 == E10G_25G_VL13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.tx_ptp_vl_offset_14 == E10G_25G_VL14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.tx_ptp_vl_offset_15 == E10G_25G_VL15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.tx_ptp_vl_offset_16 == E10G_25G_VL16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.tx_ptp_vl_offset_17 == E10G_25G_VL17
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.tx_ptp_vl_offset_18 == E10G_25G_VL18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.tx_ptp_vl_offset_19 == E10G_25G_VL19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.tx_ptp_vl_offset_2 == E10G_25G_VL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.tx_ptp_vl_offset_3 == E10G_25G_VL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.tx_ptp_vl_offset_4 == E10G_25G_VL4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.tx_ptp_vl_offset_5 == E10G_25G_VL5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.tx_ptp_vl_offset_6 == E10G_25G_VL6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.tx_ptp_vl_offset_7 == E10G_25G_VL7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.tx_ptp_vl_offset_8 == E10G_25G_VL8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.tx_ptp_vl_offset_9 == E10G_25G_VL9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch1_25g.use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.custom_cadence == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.dbg_bus_sel_1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.dbg_bus_sel_2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.dbg_bus_sel_3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.dbg_bus_sel_4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.dbg_bus_sel_dbg == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.flow_control == NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.flow_control_holdoff_mode == PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.flowreg_rate == FLOWREG_STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.link_fault_mode == LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.mac_lb_mode == NO_LOOPBACK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.mac_rate == STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rate_mode == E400G_25G_2_MAC_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rst_rx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rst_tx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_ap_filter == NO_FILTERING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_dbg_pkt_n_ts_ctr == 20'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_fec_mode == RX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_phy_lane_num == E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_ui == E25G_X1_RX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_offset_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_offset_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_offset_10 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_offset_11 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_offset_12 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_offset_13 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_offset_14 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_offset_15 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_offset_16 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_offset_17 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_offset_18 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_offset_19 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_offset_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_offset_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_offset_4 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_offset_5 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_offset_6 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_offset_7 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_offset_8 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_offset_9 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_to_pl_0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_to_pl_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_to_pl_10 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_to_pl_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_to_pl_12 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_to_pl_13 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_to_pl_14 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_to_pl_15 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_to_pl_16 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_to_pl_17 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_to_pl_18 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_to_pl_19 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_to_pl_2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_to_pl_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_to_pl_4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_to_pl_5 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_to_pl_6 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_to_pl_7 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_to_pl_8 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_ptp_vl_to_pl_9 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.tx_am_period == NO_TX_AM_PERIOD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.tx_ipg_size == IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.tx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.tx_ptp_fec_mode == TX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.tx_ptp_phy_lane_num == E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.tx_ptp_ui == E25G_X1_TX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.tx_ptp_vl_offset_0 == E10G_25G_VL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.tx_ptp_vl_offset_1 == E10G_25G_VL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.tx_ptp_vl_offset_10 == E10G_25G_VL10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.tx_ptp_vl_offset_11 == E10G_25G_VL11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.tx_ptp_vl_offset_12 == E10G_25G_VL12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.tx_ptp_vl_offset_13 == E10G_25G_VL13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.tx_ptp_vl_offset_14 == E10G_25G_VL14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.tx_ptp_vl_offset_15 == E10G_25G_VL15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.tx_ptp_vl_offset_16 == E10G_25G_VL16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.tx_ptp_vl_offset_17 == E10G_25G_VL17
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.tx_ptp_vl_offset_18 == E10G_25G_VL18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.tx_ptp_vl_offset_19 == E10G_25G_VL19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.tx_ptp_vl_offset_2 == E10G_25G_VL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.tx_ptp_vl_offset_3 == E10G_25G_VL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.tx_ptp_vl_offset_4 == E10G_25G_VL4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.tx_ptp_vl_offset_5 == E10G_25G_VL5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.tx_ptp_vl_offset_6 == E10G_25G_VL6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.tx_ptp_vl_offset_7 == E10G_25G_VL7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.tx_ptp_vl_offset_8 == E10G_25G_VL8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.tx_ptp_vl_offset_9 == E10G_25G_VL9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_25g.use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.custom_cadence == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.dbg_bus_sel_1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.dbg_bus_sel_2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.dbg_bus_sel_3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.dbg_bus_sel_4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.dbg_bus_sel_dbg == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.flow_control == NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.flow_control_holdoff_mode == PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.flowreg_rate == FLOWREG_STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.link_fault_mode == LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.mac_lb_mode == NO_LOOPBACK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.mac_rate == STANDARD_50G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rate_mode == E400G_50G_1_MAC_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rst_rx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rst_tx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_ap_filter == NO_FILTERING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_dbg_pkt_n_ts_ctr == 20'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_fec_mode == RX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_phy_lane_num == E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_ui == E25G_X1_RX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_offset_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_offset_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_offset_10 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_offset_11 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_offset_12 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_offset_13 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_offset_14 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_offset_15 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_offset_16 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_offset_17 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_offset_18 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_offset_19 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_offset_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_offset_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_offset_4 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_offset_5 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_offset_6 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_offset_7 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_offset_8 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_offset_9 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_to_pl_0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_to_pl_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_to_pl_10 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_to_pl_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_to_pl_12 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_to_pl_13 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_to_pl_14 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_to_pl_15 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_to_pl_16 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_to_pl_17 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_to_pl_18 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_to_pl_19 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_to_pl_2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_to_pl_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_to_pl_4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_to_pl_5 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_to_pl_6 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_to_pl_7 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_to_pl_8 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_ptp_vl_to_pl_9 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.tx_am_period == NO_TX_AM_PERIOD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.tx_ipg_size == IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.tx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.tx_ptp_fec_mode == TX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.tx_ptp_phy_lane_num == E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.tx_ptp_ui == E25G_X1_TX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.tx_ptp_vl_offset_0 == E10G_25G_VL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.tx_ptp_vl_offset_1 == E10G_25G_VL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.tx_ptp_vl_offset_10 == E10G_25G_VL10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.tx_ptp_vl_offset_11 == E10G_25G_VL11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.tx_ptp_vl_offset_12 == E10G_25G_VL12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.tx_ptp_vl_offset_13 == E10G_25G_VL13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.tx_ptp_vl_offset_14 == E10G_25G_VL14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.tx_ptp_vl_offset_15 == E10G_25G_VL15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.tx_ptp_vl_offset_16 == E10G_25G_VL16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.tx_ptp_vl_offset_17 == E10G_25G_VL17
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.tx_ptp_vl_offset_18 == E10G_25G_VL18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.tx_ptp_vl_offset_19 == E10G_25G_VL19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.tx_ptp_vl_offset_2 == E10G_25G_VL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.tx_ptp_vl_offset_3 == E10G_25G_VL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.tx_ptp_vl_offset_4 == E10G_25G_VL4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.tx_ptp_vl_offset_5 == E10G_25G_VL5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.tx_ptp_vl_offset_6 == E10G_25G_VL6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.tx_ptp_vl_offset_7 == E10G_25G_VL7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.tx_ptp_vl_offset_8 == E10G_25G_VL8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.tx_ptp_vl_offset_9 == E10G_25G_VL9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch2_50g.use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.custom_cadence == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.dbg_bus_sel_1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.dbg_bus_sel_2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.dbg_bus_sel_3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.dbg_bus_sel_4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.dbg_bus_sel_dbg == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.flow_control == NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.flow_control_holdoff_mode == PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.flowreg_rate == FLOWREG_STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.link_fault_mode == LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.mac_lb_mode == NO_LOOPBACK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.mac_rate == STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rate_mode == E400G_25G_3_MAC_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rst_rx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rst_tx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_ap_filter == NO_FILTERING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_dbg_pkt_n_ts_ctr == 20'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_fec_mode == RX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_phy_lane_num == E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_ui == E25G_X1_RX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_offset_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_offset_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_offset_10 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_offset_11 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_offset_12 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_offset_13 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_offset_14 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_offset_15 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_offset_16 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_offset_17 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_offset_18 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_offset_19 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_offset_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_offset_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_offset_4 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_offset_5 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_offset_6 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_offset_7 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_offset_8 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_offset_9 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_to_pl_0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_to_pl_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_to_pl_10 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_to_pl_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_to_pl_12 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_to_pl_13 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_to_pl_14 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_to_pl_15 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_to_pl_16 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_to_pl_17 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_to_pl_18 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_to_pl_19 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_to_pl_2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_to_pl_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_to_pl_4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_to_pl_5 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_to_pl_6 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_to_pl_7 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_to_pl_8 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_ptp_vl_to_pl_9 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.tx_am_period == NO_TX_AM_PERIOD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.tx_ipg_size == IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.tx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.tx_ptp_fec_mode == TX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.tx_ptp_phy_lane_num == E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.tx_ptp_ui == E25G_X1_TX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.tx_ptp_vl_offset_0 == E10G_25G_VL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.tx_ptp_vl_offset_1 == E10G_25G_VL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.tx_ptp_vl_offset_10 == E10G_25G_VL10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.tx_ptp_vl_offset_11 == E10G_25G_VL11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.tx_ptp_vl_offset_12 == E10G_25G_VL12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.tx_ptp_vl_offset_13 == E10G_25G_VL13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.tx_ptp_vl_offset_14 == E10G_25G_VL14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.tx_ptp_vl_offset_15 == E10G_25G_VL15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.tx_ptp_vl_offset_16 == E10G_25G_VL16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.tx_ptp_vl_offset_17 == E10G_25G_VL17
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.tx_ptp_vl_offset_18 == E10G_25G_VL18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.tx_ptp_vl_offset_19 == E10G_25G_VL19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.tx_ptp_vl_offset_2 == E10G_25G_VL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.tx_ptp_vl_offset_3 == E10G_25G_VL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.tx_ptp_vl_offset_4 == E10G_25G_VL4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.tx_ptp_vl_offset_5 == E10G_25G_VL5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.tx_ptp_vl_offset_6 == E10G_25G_VL6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.tx_ptp_vl_offset_7 == E10G_25G_VL7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.tx_ptp_vl_offset_8 == E10G_25G_VL8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.tx_ptp_vl_offset_9 == E10G_25G_VL9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch3_25g.use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.custom_cadence == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.dbg_bus_sel_1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.dbg_bus_sel_2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.dbg_bus_sel_3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.dbg_bus_sel_4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.dbg_bus_sel_dbg == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.flow_control == NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.flow_control_holdoff_mode == PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.flowreg_rate == FLOWREG_STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.link_fault_mode == LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.mac_lb_mode == NO_LOOPBACK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.mac_rate == STANDARD_100G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rate_mode == E400G_100G_1_MAC_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rst_rx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rst_tx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_ap_filter == NO_FILTERING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_dbg_pkt_n_ts_ctr == 20'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_fec_mode == RX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_phy_lane_num == E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_ui == E25G_X1_RX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_offset_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_offset_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_offset_10 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_offset_11 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_offset_12 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_offset_13 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_offset_14 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_offset_15 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_offset_16 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_offset_17 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_offset_18 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_offset_19 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_offset_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_offset_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_offset_4 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_offset_5 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_offset_6 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_offset_7 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_offset_8 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_offset_9 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_to_pl_0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_to_pl_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_to_pl_10 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_to_pl_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_to_pl_12 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_to_pl_13 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_to_pl_14 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_to_pl_15 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_to_pl_16 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_to_pl_17 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_to_pl_18 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_to_pl_19 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_to_pl_2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_to_pl_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_to_pl_4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_to_pl_5 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_to_pl_6 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_to_pl_7 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_to_pl_8 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_ptp_vl_to_pl_9 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.tx_am_period == NO_TX_AM_PERIOD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.tx_ipg_size == IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.tx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.tx_ptp_fec_mode == TX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.tx_ptp_phy_lane_num == E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.tx_ptp_ui == E25G_X1_TX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.tx_ptp_vl_offset_0 == E10G_25G_VL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.tx_ptp_vl_offset_1 == E10G_25G_VL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.tx_ptp_vl_offset_10 == E10G_25G_VL10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.tx_ptp_vl_offset_11 == E10G_25G_VL11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.tx_ptp_vl_offset_12 == E10G_25G_VL12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.tx_ptp_vl_offset_13 == E10G_25G_VL13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.tx_ptp_vl_offset_14 == E10G_25G_VL14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.tx_ptp_vl_offset_15 == E10G_25G_VL15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.tx_ptp_vl_offset_16 == E10G_25G_VL16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.tx_ptp_vl_offset_17 == E10G_25G_VL17
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.tx_ptp_vl_offset_18 == E10G_25G_VL18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.tx_ptp_vl_offset_19 == E10G_25G_VL19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.tx_ptp_vl_offset_2 == E10G_25G_VL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.tx_ptp_vl_offset_3 == E10G_25G_VL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.tx_ptp_vl_offset_4 == E10G_25G_VL4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.tx_ptp_vl_offset_5 == E10G_25G_VL5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.tx_ptp_vl_offset_6 == E10G_25G_VL6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.tx_ptp_vl_offset_7 == E10G_25G_VL7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.tx_ptp_vl_offset_8 == E10G_25G_VL8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.tx_ptp_vl_offset_9 == E10G_25G_VL9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_100g.use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.custom_cadence == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.dbg_bus_sel_1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.dbg_bus_sel_2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.dbg_bus_sel_3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.dbg_bus_sel_4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.dbg_bus_sel_dbg == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.flow_control == NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.flow_control_holdoff_mode == PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.flowreg_rate == FLOWREG_STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.link_fault_mode == LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.mac_lb_mode == NO_LOOPBACK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.mac_rate == STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rate_mode == E400G_25G_4_MAC_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rst_rx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rst_tx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_ap_filter == NO_FILTERING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_dbg_pkt_n_ts_ctr == 20'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_fec_mode == RX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_phy_lane_num == E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_ui == E25G_X1_RX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_offset_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_offset_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_offset_10 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_offset_11 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_offset_12 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_offset_13 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_offset_14 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_offset_15 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_offset_16 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_offset_17 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_offset_18 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_offset_19 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_offset_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_offset_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_offset_4 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_offset_5 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_offset_6 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_offset_7 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_offset_8 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_offset_9 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_to_pl_0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_to_pl_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_to_pl_10 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_to_pl_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_to_pl_12 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_to_pl_13 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_to_pl_14 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_to_pl_15 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_to_pl_16 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_to_pl_17 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_to_pl_18 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_to_pl_19 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_to_pl_2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_to_pl_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_to_pl_4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_to_pl_5 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_to_pl_6 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_to_pl_7 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_to_pl_8 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_ptp_vl_to_pl_9 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.tx_am_period == NO_TX_AM_PERIOD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.tx_ipg_size == IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.tx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.tx_ptp_fec_mode == TX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.tx_ptp_phy_lane_num == E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.tx_ptp_ui == E25G_X1_TX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.tx_ptp_vl_offset_0 == E10G_25G_VL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.tx_ptp_vl_offset_1 == E10G_25G_VL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.tx_ptp_vl_offset_10 == E10G_25G_VL10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.tx_ptp_vl_offset_11 == E10G_25G_VL11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.tx_ptp_vl_offset_12 == E10G_25G_VL12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.tx_ptp_vl_offset_13 == E10G_25G_VL13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.tx_ptp_vl_offset_14 == E10G_25G_VL14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.tx_ptp_vl_offset_15 == E10G_25G_VL15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.tx_ptp_vl_offset_16 == E10G_25G_VL16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.tx_ptp_vl_offset_17 == E10G_25G_VL17
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.tx_ptp_vl_offset_18 == E10G_25G_VL18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.tx_ptp_vl_offset_19 == E10G_25G_VL19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.tx_ptp_vl_offset_2 == E10G_25G_VL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.tx_ptp_vl_offset_3 == E10G_25G_VL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.tx_ptp_vl_offset_4 == E10G_25G_VL4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.tx_ptp_vl_offset_5 == E10G_25G_VL5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.tx_ptp_vl_offset_6 == E10G_25G_VL6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.tx_ptp_vl_offset_7 == E10G_25G_VL7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.tx_ptp_vl_offset_8 == E10G_25G_VL8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.tx_ptp_vl_offset_9 == E10G_25G_VL9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_25g.use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.custom_cadence == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.dbg_bus_sel_1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.dbg_bus_sel_2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.dbg_bus_sel_3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.dbg_bus_sel_4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.dbg_bus_sel_dbg == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.flow_control == NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.flow_control_holdoff_mode == PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.flowreg_rate == FLOWREG_STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.link_fault_mode == LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.mac_lb_mode == NO_LOOPBACK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.mac_rate == STANDARD_50G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rate_mode == E400G_50G_2_MAC_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rst_rx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rst_tx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_ap_filter == NO_FILTERING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_dbg_pkt_n_ts_ctr == 20'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_fec_mode == RX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_phy_lane_num == E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_ui == E25G_X1_RX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_offset_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_offset_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_offset_10 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_offset_11 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_offset_12 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_offset_13 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_offset_14 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_offset_15 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_offset_16 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_offset_17 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_offset_18 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_offset_19 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_offset_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_offset_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_offset_4 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_offset_5 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_offset_6 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_offset_7 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_offset_8 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_offset_9 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_to_pl_0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_to_pl_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_to_pl_10 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_to_pl_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_to_pl_12 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_to_pl_13 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_to_pl_14 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_to_pl_15 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_to_pl_16 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_to_pl_17 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_to_pl_18 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_to_pl_19 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_to_pl_2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_to_pl_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_to_pl_4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_to_pl_5 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_to_pl_6 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_to_pl_7 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_to_pl_8 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_ptp_vl_to_pl_9 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.tx_am_period == NO_TX_AM_PERIOD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.tx_ipg_size == IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.tx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.tx_ptp_fec_mode == TX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.tx_ptp_phy_lane_num == E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.tx_ptp_ui == E25G_X1_TX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.tx_ptp_vl_offset_0 == E10G_25G_VL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.tx_ptp_vl_offset_1 == E10G_25G_VL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.tx_ptp_vl_offset_10 == E10G_25G_VL10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.tx_ptp_vl_offset_11 == E10G_25G_VL11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.tx_ptp_vl_offset_12 == E10G_25G_VL12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.tx_ptp_vl_offset_13 == E10G_25G_VL13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.tx_ptp_vl_offset_14 == E10G_25G_VL14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.tx_ptp_vl_offset_15 == E10G_25G_VL15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.tx_ptp_vl_offset_16 == E10G_25G_VL16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.tx_ptp_vl_offset_17 == E10G_25G_VL17
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.tx_ptp_vl_offset_18 == E10G_25G_VL18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.tx_ptp_vl_offset_19 == E10G_25G_VL19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.tx_ptp_vl_offset_2 == E10G_25G_VL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.tx_ptp_vl_offset_3 == E10G_25G_VL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.tx_ptp_vl_offset_4 == E10G_25G_VL4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.tx_ptp_vl_offset_5 == E10G_25G_VL5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.tx_ptp_vl_offset_6 == E10G_25G_VL6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.tx_ptp_vl_offset_7 == E10G_25G_VL7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.tx_ptp_vl_offset_8 == E10G_25G_VL8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.tx_ptp_vl_offset_9 == E10G_25G_VL9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch4_50g.use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.custom_cadence == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.dbg_bus_sel_1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.dbg_bus_sel_2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.dbg_bus_sel_3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.dbg_bus_sel_4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.dbg_bus_sel_dbg == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.flow_control == NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.flow_control_holdoff_mode == PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.flowreg_rate == FLOWREG_STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.link_fault_mode == LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.mac_lb_mode == NO_LOOPBACK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.mac_rate == STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rate_mode == E400G_25G_5_MAC_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rst_rx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rst_tx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_ap_filter == NO_FILTERING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_dbg_pkt_n_ts_ctr == 20'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_fec_mode == RX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_phy_lane_num == E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_ui == E25G_X1_RX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_offset_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_offset_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_offset_10 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_offset_11 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_offset_12 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_offset_13 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_offset_14 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_offset_15 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_offset_16 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_offset_17 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_offset_18 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_offset_19 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_offset_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_offset_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_offset_4 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_offset_5 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_offset_6 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_offset_7 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_offset_8 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_offset_9 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_to_pl_0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_to_pl_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_to_pl_10 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_to_pl_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_to_pl_12 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_to_pl_13 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_to_pl_14 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_to_pl_15 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_to_pl_16 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_to_pl_17 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_to_pl_18 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_to_pl_19 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_to_pl_2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_to_pl_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_to_pl_4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_to_pl_5 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_to_pl_6 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_to_pl_7 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_to_pl_8 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_ptp_vl_to_pl_9 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.tx_am_period == NO_TX_AM_PERIOD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.tx_ipg_size == IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.tx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.tx_ptp_fec_mode == TX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.tx_ptp_phy_lane_num == E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.tx_ptp_ui == E25G_X1_TX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.tx_ptp_vl_offset_0 == E10G_25G_VL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.tx_ptp_vl_offset_1 == E10G_25G_VL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.tx_ptp_vl_offset_10 == E10G_25G_VL10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.tx_ptp_vl_offset_11 == E10G_25G_VL11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.tx_ptp_vl_offset_12 == E10G_25G_VL12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.tx_ptp_vl_offset_13 == E10G_25G_VL13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.tx_ptp_vl_offset_14 == E10G_25G_VL14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.tx_ptp_vl_offset_15 == E10G_25G_VL15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.tx_ptp_vl_offset_16 == E10G_25G_VL16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.tx_ptp_vl_offset_17 == E10G_25G_VL17
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.tx_ptp_vl_offset_18 == E10G_25G_VL18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.tx_ptp_vl_offset_19 == E10G_25G_VL19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.tx_ptp_vl_offset_2 == E10G_25G_VL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.tx_ptp_vl_offset_3 == E10G_25G_VL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.tx_ptp_vl_offset_4 == E10G_25G_VL4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.tx_ptp_vl_offset_5 == E10G_25G_VL5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.tx_ptp_vl_offset_6 == E10G_25G_VL6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.tx_ptp_vl_offset_7 == E10G_25G_VL7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.tx_ptp_vl_offset_8 == E10G_25G_VL8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.tx_ptp_vl_offset_9 == E10G_25G_VL9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch5_25g.use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.custom_cadence == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.dbg_bus_sel_1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.dbg_bus_sel_2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.dbg_bus_sel_3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.dbg_bus_sel_4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.dbg_bus_sel_dbg == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.flow_control == NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.flow_control_holdoff_mode == PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.flowreg_rate == FLOWREG_STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.link_fault_mode == LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.mac_lb_mode == NO_LOOPBACK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.mac_rate == STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rate_mode == E400G_25G_6_MAC_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rst_rx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rst_tx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_ap_filter == NO_FILTERING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_dbg_pkt_n_ts_ctr == 20'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_fec_mode == RX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_phy_lane_num == E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_ui == E25G_X1_RX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_offset_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_offset_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_offset_10 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_offset_11 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_offset_12 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_offset_13 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_offset_14 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_offset_15 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_offset_16 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_offset_17 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_offset_18 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_offset_19 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_offset_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_offset_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_offset_4 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_offset_5 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_offset_6 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_offset_7 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_offset_8 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_offset_9 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_to_pl_0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_to_pl_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_to_pl_10 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_to_pl_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_to_pl_12 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_to_pl_13 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_to_pl_14 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_to_pl_15 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_to_pl_16 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_to_pl_17 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_to_pl_18 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_to_pl_19 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_to_pl_2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_to_pl_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_to_pl_4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_to_pl_5 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_to_pl_6 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_to_pl_7 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_to_pl_8 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_ptp_vl_to_pl_9 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.tx_am_period == NO_TX_AM_PERIOD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.tx_ipg_size == IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.tx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.tx_ptp_fec_mode == TX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.tx_ptp_phy_lane_num == E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.tx_ptp_ui == E25G_X1_TX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.tx_ptp_vl_offset_0 == E10G_25G_VL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.tx_ptp_vl_offset_1 == E10G_25G_VL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.tx_ptp_vl_offset_10 == E10G_25G_VL10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.tx_ptp_vl_offset_11 == E10G_25G_VL11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.tx_ptp_vl_offset_12 == E10G_25G_VL12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.tx_ptp_vl_offset_13 == E10G_25G_VL13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.tx_ptp_vl_offset_14 == E10G_25G_VL14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.tx_ptp_vl_offset_15 == E10G_25G_VL15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.tx_ptp_vl_offset_16 == E10G_25G_VL16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.tx_ptp_vl_offset_17 == E10G_25G_VL17
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.tx_ptp_vl_offset_18 == E10G_25G_VL18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.tx_ptp_vl_offset_19 == E10G_25G_VL19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.tx_ptp_vl_offset_2 == E10G_25G_VL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.tx_ptp_vl_offset_3 == E10G_25G_VL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.tx_ptp_vl_offset_4 == E10G_25G_VL4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.tx_ptp_vl_offset_5 == E10G_25G_VL5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.tx_ptp_vl_offset_6 == E10G_25G_VL6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.tx_ptp_vl_offset_7 == E10G_25G_VL7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.tx_ptp_vl_offset_8 == E10G_25G_VL8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.tx_ptp_vl_offset_9 == E10G_25G_VL9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_25g.use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.custom_cadence == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.dbg_bus_sel_1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.dbg_bus_sel_2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.dbg_bus_sel_3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.dbg_bus_sel_4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.dbg_bus_sel_dbg == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.flow_control == NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.flow_control_holdoff_mode == PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.flowreg_rate == FLOWREG_STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.link_fault_mode == LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.mac_lb_mode == NO_LOOPBACK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.mac_rate == STANDARD_50G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rate_mode == E400G_50G_3_MAC_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rst_rx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rst_tx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_ap_filter == NO_FILTERING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_dbg_pkt_n_ts_ctr == 20'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_fec_mode == RX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_phy_lane_num == E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_ui == E25G_X1_RX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_offset_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_offset_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_offset_10 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_offset_11 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_offset_12 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_offset_13 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_offset_14 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_offset_15 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_offset_16 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_offset_17 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_offset_18 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_offset_19 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_offset_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_offset_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_offset_4 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_offset_5 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_offset_6 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_offset_7 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_offset_8 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_offset_9 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_to_pl_0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_to_pl_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_to_pl_10 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_to_pl_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_to_pl_12 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_to_pl_13 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_to_pl_14 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_to_pl_15 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_to_pl_16 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_to_pl_17 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_to_pl_18 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_to_pl_19 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_to_pl_2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_to_pl_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_to_pl_4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_to_pl_5 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_to_pl_6 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_to_pl_7 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_to_pl_8 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_ptp_vl_to_pl_9 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.tx_am_period == NO_TX_AM_PERIOD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.tx_ipg_size == IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.tx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.tx_ptp_fec_mode == TX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.tx_ptp_phy_lane_num == E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.tx_ptp_ui == E25G_X1_TX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.tx_ptp_vl_offset_0 == E10G_25G_VL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.tx_ptp_vl_offset_1 == E10G_25G_VL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.tx_ptp_vl_offset_10 == E10G_25G_VL10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.tx_ptp_vl_offset_11 == E10G_25G_VL11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.tx_ptp_vl_offset_12 == E10G_25G_VL12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.tx_ptp_vl_offset_13 == E10G_25G_VL13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.tx_ptp_vl_offset_14 == E10G_25G_VL14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.tx_ptp_vl_offset_15 == E10G_25G_VL15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.tx_ptp_vl_offset_16 == E10G_25G_VL16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.tx_ptp_vl_offset_17 == E10G_25G_VL17
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.tx_ptp_vl_offset_18 == E10G_25G_VL18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.tx_ptp_vl_offset_19 == E10G_25G_VL19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.tx_ptp_vl_offset_2 == E10G_25G_VL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.tx_ptp_vl_offset_3 == E10G_25G_VL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.tx_ptp_vl_offset_4 == E10G_25G_VL4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.tx_ptp_vl_offset_5 == E10G_25G_VL5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.tx_ptp_vl_offset_6 == E10G_25G_VL6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.tx_ptp_vl_offset_7 == E10G_25G_VL7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.tx_ptp_vl_offset_8 == E10G_25G_VL8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.tx_ptp_vl_offset_9 == E10G_25G_VL9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch6_50g.use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.custom_cadence == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.dbg_bus_sel_1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.dbg_bus_sel_2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.dbg_bus_sel_3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.dbg_bus_sel_4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.dbg_bus_sel_dbg == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.flow_control == NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.flow_control_holdoff_mode == PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.flowreg_rate == FLOWREG_STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.link_fault_mode == LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.mac_lb_mode == NO_LOOPBACK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.mac_rate == STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rate_mode == E400G_25G_7_MAC_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rst_rx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rst_tx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_ap_filter == NO_FILTERING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_dbg_pkt_n_ts_ctr == 20'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_fec_mode == RX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_phy_lane_num == E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_ui == E25G_X1_RX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_offset_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_offset_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_offset_10 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_offset_11 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_offset_12 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_offset_13 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_offset_14 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_offset_15 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_offset_16 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_offset_17 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_offset_18 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_offset_19 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_offset_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_offset_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_offset_4 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_offset_5 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_offset_6 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_offset_7 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_offset_8 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_offset_9 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_to_pl_0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_to_pl_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_to_pl_10 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_to_pl_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_to_pl_12 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_to_pl_13 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_to_pl_14 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_to_pl_15 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_to_pl_16 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_to_pl_17 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_to_pl_18 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_to_pl_19 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_to_pl_2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_to_pl_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_to_pl_4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_to_pl_5 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_to_pl_6 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_to_pl_7 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_to_pl_8 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_ptp_vl_to_pl_9 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.tx_am_period == NO_TX_AM_PERIOD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.tx_ipg_size == IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.tx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.tx_ptp_fec_mode == TX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.tx_ptp_phy_lane_num == E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.tx_ptp_ui == E25G_X1_TX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.tx_ptp_vl_offset_0 == E10G_25G_VL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.tx_ptp_vl_offset_1 == E10G_25G_VL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.tx_ptp_vl_offset_10 == E10G_25G_VL10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.tx_ptp_vl_offset_11 == E10G_25G_VL11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.tx_ptp_vl_offset_12 == E10G_25G_VL12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.tx_ptp_vl_offset_13 == E10G_25G_VL13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.tx_ptp_vl_offset_14 == E10G_25G_VL14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.tx_ptp_vl_offset_15 == E10G_25G_VL15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.tx_ptp_vl_offset_16 == E10G_25G_VL16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.tx_ptp_vl_offset_17 == E10G_25G_VL17
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.tx_ptp_vl_offset_18 == E10G_25G_VL18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.tx_ptp_vl_offset_19 == E10G_25G_VL19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.tx_ptp_vl_offset_2 == E10G_25G_VL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.tx_ptp_vl_offset_3 == E10G_25G_VL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.tx_ptp_vl_offset_4 == E10G_25G_VL4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.tx_ptp_vl_offset_5 == E10G_25G_VL5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.tx_ptp_vl_offset_6 == E10G_25G_VL6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.tx_ptp_vl_offset_7 == E10G_25G_VL7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.tx_ptp_vl_offset_8 == E10G_25G_VL8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.tx_ptp_vl_offset_9 == E10G_25G_VL9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch7_25g.use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.custom_cadence == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.dbg_bus_sel_1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.dbg_bus_sel_2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.dbg_bus_sel_3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.dbg_bus_sel_4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.dbg_bus_sel_dbg == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.flow_control == NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.flow_control_holdoff_mode == PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.flowreg_rate == FLOWREG_STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.link_fault_mode == LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.mac_lb_mode == NO_LOOPBACK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.mac_rate == STANDARD_100G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rate_mode == E400G_100G_2_MAC_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rst_rx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rst_tx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_ap_filter == NO_FILTERING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_dbg_pkt_n_ts_ctr == 20'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_fec_mode == RX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_phy_lane_num == E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_ui == E25G_X1_RX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_offset_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_offset_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_offset_10 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_offset_11 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_offset_12 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_offset_13 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_offset_14 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_offset_15 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_offset_16 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_offset_17 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_offset_18 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_offset_19 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_offset_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_offset_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_offset_4 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_offset_5 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_offset_6 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_offset_7 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_offset_8 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_offset_9 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_to_pl_0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_to_pl_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_to_pl_10 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_to_pl_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_to_pl_12 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_to_pl_13 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_to_pl_14 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_to_pl_15 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_to_pl_16 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_to_pl_17 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_to_pl_18 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_to_pl_19 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_to_pl_2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_to_pl_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_to_pl_4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_to_pl_5 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_to_pl_6 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_to_pl_7 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_to_pl_8 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_ptp_vl_to_pl_9 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.tx_am_period == NO_TX_AM_PERIOD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.tx_ipg_size == IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.tx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.tx_ptp_fec_mode == TX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.tx_ptp_phy_lane_num == E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.tx_ptp_ui == E25G_X1_TX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.tx_ptp_vl_offset_0 == E10G_25G_VL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.tx_ptp_vl_offset_1 == E10G_25G_VL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.tx_ptp_vl_offset_10 == E10G_25G_VL10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.tx_ptp_vl_offset_11 == E10G_25G_VL11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.tx_ptp_vl_offset_12 == E10G_25G_VL12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.tx_ptp_vl_offset_13 == E10G_25G_VL13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.tx_ptp_vl_offset_14 == E10G_25G_VL14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.tx_ptp_vl_offset_15 == E10G_25G_VL15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.tx_ptp_vl_offset_16 == E10G_25G_VL16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.tx_ptp_vl_offset_17 == E10G_25G_VL17
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.tx_ptp_vl_offset_18 == E10G_25G_VL18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.tx_ptp_vl_offset_19 == E10G_25G_VL19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.tx_ptp_vl_offset_2 == E10G_25G_VL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.tx_ptp_vl_offset_3 == E10G_25G_VL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.tx_ptp_vl_offset_4 == E10G_25G_VL4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.tx_ptp_vl_offset_5 == E10G_25G_VL5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.tx_ptp_vl_offset_6 == E10G_25G_VL6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.tx_ptp_vl_offset_7 == E10G_25G_VL7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.tx_ptp_vl_offset_8 == E10G_25G_VL8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.tx_ptp_vl_offset_9 == E10G_25G_VL9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_100g.use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.custom_cadence == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.dbg_bus_sel_1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.dbg_bus_sel_2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.dbg_bus_sel_3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.dbg_bus_sel_4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.dbg_bus_sel_dbg == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.flow_control == NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.flow_control_holdoff_mode == PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.flowreg_rate == FLOWREG_STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.link_fault_mode == LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.mac_lb_mode == NO_LOOPBACK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.mac_rate == STANDARD_200G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rate_mode == E400G_200G_1_MAC_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rst_rx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rst_tx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_ap_filter == NO_FILTERING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_dbg_pkt_n_ts_ctr == 20'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_fec_mode == RX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_phy_lane_num == E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_ui == E25G_X1_RX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_offset_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_offset_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_offset_10 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_offset_11 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_offset_12 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_offset_13 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_offset_14 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_offset_15 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_offset_16 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_offset_17 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_offset_18 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_offset_19 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_offset_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_offset_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_offset_4 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_offset_5 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_offset_6 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_offset_7 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_offset_8 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_offset_9 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_to_pl_0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_to_pl_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_to_pl_10 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_to_pl_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_to_pl_12 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_to_pl_13 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_to_pl_14 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_to_pl_15 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_to_pl_16 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_to_pl_17 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_to_pl_18 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_to_pl_19 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_to_pl_2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_to_pl_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_to_pl_4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_to_pl_5 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_to_pl_6 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_to_pl_7 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_to_pl_8 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_ptp_vl_to_pl_9 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.tx_am_period == NO_TX_AM_PERIOD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.tx_ipg_size == IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.tx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.tx_ptp_fec_mode == TX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.tx_ptp_phy_lane_num == E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.tx_ptp_ui == E25G_X1_TX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.tx_ptp_vl_offset_0 == E10G_25G_VL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.tx_ptp_vl_offset_1 == E10G_25G_VL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.tx_ptp_vl_offset_10 == E10G_25G_VL10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.tx_ptp_vl_offset_11 == E10G_25G_VL11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.tx_ptp_vl_offset_12 == E10G_25G_VL12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.tx_ptp_vl_offset_13 == E10G_25G_VL13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.tx_ptp_vl_offset_14 == E10G_25G_VL14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.tx_ptp_vl_offset_15 == E10G_25G_VL15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.tx_ptp_vl_offset_16 == E10G_25G_VL16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.tx_ptp_vl_offset_17 == E10G_25G_VL17
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.tx_ptp_vl_offset_18 == E10G_25G_VL18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.tx_ptp_vl_offset_19 == E10G_25G_VL19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.tx_ptp_vl_offset_2 == E10G_25G_VL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.tx_ptp_vl_offset_3 == E10G_25G_VL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.tx_ptp_vl_offset_4 == E10G_25G_VL4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.tx_ptp_vl_offset_5 == E10G_25G_VL5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.tx_ptp_vl_offset_6 == E10G_25G_VL6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.tx_ptp_vl_offset_7 == E10G_25G_VL7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.tx_ptp_vl_offset_8 == E10G_25G_VL8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.tx_ptp_vl_offset_9 == E10G_25G_VL9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_200g.use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.custom_cadence == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.dbg_bus_sel_1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.dbg_bus_sel_2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.dbg_bus_sel_3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.dbg_bus_sel_4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.dbg_bus_sel_dbg == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.flow_control == NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.flow_control_holdoff_mode == PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.flowreg_rate == FLOWREG_STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.link_fault_mode == LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.mac_lb_mode == NO_LOOPBACK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.mac_rate == STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rate_mode == E400G_25G_8_MAC_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rst_rx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rst_tx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_ap_filter == NO_FILTERING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_dbg_pkt_n_ts_ctr == 20'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_fec_mode == RX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_phy_lane_num == E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_ui == E25G_X1_RX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_offset_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_offset_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_offset_10 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_offset_11 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_offset_12 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_offset_13 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_offset_14 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_offset_15 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_offset_16 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_offset_17 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_offset_18 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_offset_19 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_offset_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_offset_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_offset_4 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_offset_5 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_offset_6 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_offset_7 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_offset_8 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_offset_9 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_to_pl_0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_to_pl_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_to_pl_10 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_to_pl_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_to_pl_12 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_to_pl_13 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_to_pl_14 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_to_pl_15 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_to_pl_16 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_to_pl_17 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_to_pl_18 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_to_pl_19 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_to_pl_2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_to_pl_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_to_pl_4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_to_pl_5 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_to_pl_6 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_to_pl_7 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_to_pl_8 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_ptp_vl_to_pl_9 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.tx_am_period == NO_TX_AM_PERIOD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.tx_ipg_size == IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.tx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.tx_ptp_fec_mode == TX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.tx_ptp_phy_lane_num == E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.tx_ptp_ui == E25G_X1_TX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.tx_ptp_vl_offset_0 == E10G_25G_VL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.tx_ptp_vl_offset_1 == E10G_25G_VL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.tx_ptp_vl_offset_10 == E10G_25G_VL10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.tx_ptp_vl_offset_11 == E10G_25G_VL11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.tx_ptp_vl_offset_12 == E10G_25G_VL12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.tx_ptp_vl_offset_13 == E10G_25G_VL13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.tx_ptp_vl_offset_14 == E10G_25G_VL14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.tx_ptp_vl_offset_15 == E10G_25G_VL15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.tx_ptp_vl_offset_16 == E10G_25G_VL16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.tx_ptp_vl_offset_17 == E10G_25G_VL17
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.tx_ptp_vl_offset_18 == E10G_25G_VL18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.tx_ptp_vl_offset_19 == E10G_25G_VL19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.tx_ptp_vl_offset_2 == E10G_25G_VL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.tx_ptp_vl_offset_3 == E10G_25G_VL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.tx_ptp_vl_offset_4 == E10G_25G_VL4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.tx_ptp_vl_offset_5 == E10G_25G_VL5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.tx_ptp_vl_offset_6 == E10G_25G_VL6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.tx_ptp_vl_offset_7 == E10G_25G_VL7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.tx_ptp_vl_offset_8 == E10G_25G_VL8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.tx_ptp_vl_offset_9 == E10G_25G_VL9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_25g.use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.custom_cadence == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.dbg_bus_sel_1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.dbg_bus_sel_2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.dbg_bus_sel_3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.dbg_bus_sel_4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.dbg_bus_sel_dbg == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.flow_control == NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.flow_control_holdoff_mode == PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.flowreg_rate == FLOWREG_STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.link_fault_mode == LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.mac_lb_mode == NO_LOOPBACK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.mac_rate == STANDARD_50G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rate_mode == E400G_50G_4_MAC_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rst_rx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rst_tx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_ap_filter == NO_FILTERING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_dbg_pkt_n_ts_ctr == 20'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_fec_mode == RX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_phy_lane_num == E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_ui == E25G_X1_RX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_offset_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_offset_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_offset_10 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_offset_11 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_offset_12 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_offset_13 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_offset_14 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_offset_15 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_offset_16 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_offset_17 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_offset_18 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_offset_19 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_offset_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_offset_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_offset_4 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_offset_5 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_offset_6 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_offset_7 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_offset_8 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_offset_9 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_to_pl_0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_to_pl_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_to_pl_10 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_to_pl_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_to_pl_12 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_to_pl_13 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_to_pl_14 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_to_pl_15 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_to_pl_16 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_to_pl_17 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_to_pl_18 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_to_pl_19 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_to_pl_2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_to_pl_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_to_pl_4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_to_pl_5 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_to_pl_6 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_to_pl_7 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_to_pl_8 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_ptp_vl_to_pl_9 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.tx_am_period == NO_TX_AM_PERIOD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.tx_ipg_size == IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.tx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.tx_ptp_fec_mode == TX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.tx_ptp_phy_lane_num == E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.tx_ptp_ui == E25G_X1_TX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.tx_ptp_vl_offset_0 == E10G_25G_VL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.tx_ptp_vl_offset_1 == E10G_25G_VL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.tx_ptp_vl_offset_10 == E10G_25G_VL10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.tx_ptp_vl_offset_11 == E10G_25G_VL11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.tx_ptp_vl_offset_12 == E10G_25G_VL12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.tx_ptp_vl_offset_13 == E10G_25G_VL13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.tx_ptp_vl_offset_14 == E10G_25G_VL14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.tx_ptp_vl_offset_15 == E10G_25G_VL15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.tx_ptp_vl_offset_16 == E10G_25G_VL16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.tx_ptp_vl_offset_17 == E10G_25G_VL17
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.tx_ptp_vl_offset_18 == E10G_25G_VL18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.tx_ptp_vl_offset_19 == E10G_25G_VL19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.tx_ptp_vl_offset_2 == E10G_25G_VL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.tx_ptp_vl_offset_3 == E10G_25G_VL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.tx_ptp_vl_offset_4 == E10G_25G_VL4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.tx_ptp_vl_offset_5 == E10G_25G_VL5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.tx_ptp_vl_offset_6 == E10G_25G_VL6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.tx_ptp_vl_offset_7 == E10G_25G_VL7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.tx_ptp_vl_offset_8 == E10G_25G_VL8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.tx_ptp_vl_offset_9 == E10G_25G_VL9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch8_50g.use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.avmm_timeout == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.custom_cadence == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.dbg_bus_sel_1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.dbg_bus_sel_2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.dbg_bus_sel_3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.dbg_bus_sel_4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.dbg_bus_sel_dbg == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.flow_control == NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.flow_control_holdoff_mode == PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.flowreg_rate == FLOWREG_STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.link_fault_mode == LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.mac_lb_mode == NO_LOOPBACK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.mac_rate == STANDARD_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rate_mode == E400G_25G_9_MAC_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rst_rx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rst_tx_stats == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_ap_filter == NO_FILTERING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_dbg_pkt_n_ts_ctr == 20'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_fec_mode == RX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_phy_lane_num == E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_ui == E25G_X1_RX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_offset_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_offset_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_offset_10 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_offset_11 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_offset_12 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_offset_13 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_offset_14 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_offset_15 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_offset_16 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_offset_17 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_offset_18 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_offset_19 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_offset_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_offset_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_offset_4 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_offset_5 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_offset_6 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_offset_7 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_offset_8 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_offset_9 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_to_pl_0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_to_pl_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_to_pl_10 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_to_pl_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_to_pl_12 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_to_pl_13 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_to_pl_14 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_to_pl_15 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_to_pl_16 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_to_pl_17 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_to_pl_18 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_to_pl_19 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_to_pl_2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_to_pl_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_to_pl_4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_to_pl_5 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_to_pl_6 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_to_pl_7 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_to_pl_8 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_ptp_vl_to_pl_9 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.tx_am_period == NO_TX_AM_PERIOD
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.tx_ipg_size == IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.tx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.tx_ptp_fec_mode == TX_NO_FEC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.tx_ptp_phy_lane_num == E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.tx_ptp_ui == E25G_X1_TX_UI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.tx_ptp_vl_offset_0 == E10G_25G_VL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.tx_ptp_vl_offset_1 == E10G_25G_VL1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.tx_ptp_vl_offset_10 == E10G_25G_VL10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.tx_ptp_vl_offset_11 == E10G_25G_VL11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.tx_ptp_vl_offset_12 == E10G_25G_VL12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.tx_ptp_vl_offset_13 == E10G_25G_VL13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.tx_ptp_vl_offset_14 == E10G_25G_VL14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.tx_ptp_vl_offset_15 == E10G_25G_VL15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.tx_ptp_vl_offset_16 == E10G_25G_VL16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.tx_ptp_vl_offset_17 == E10G_25G_VL17
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.tx_ptp_vl_offset_18 == E10G_25G_VL18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.tx_ptp_vl_offset_19 == E10G_25G_VL19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.tx_ptp_vl_offset_2 == E10G_25G_VL2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.tx_ptp_vl_offset_3 == E10G_25G_VL3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.tx_ptp_vl_offset_4 == E10G_25G_VL4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.tx_ptp_vl_offset_5 == E10G_25G_VL5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.tx_ptp_vl_offset_6 == E10G_25G_VL6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.tx_ptp_vl_offset_7 == E10G_25G_VL7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.tx_ptp_vl_offset_8 == E10G_25G_VL8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.tx_ptp_vl_offset_9 == E10G_25G_VL9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_e400g_top.u_gdr_e4hip_top.u_maccfg_ch9_25g.use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_clkrst_aibrc_ds_0_sclk == OFF_AIB_CLKRST_AIBRC_DS_0_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_clkrst_aibrc_ds_10_sclk == OFF_AIB_CLKRST_AIBRC_DS_10_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_clkrst_aibrc_ds_11_sclk == OFF_AIB_CLKRST_AIBRC_DS_11_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_clkrst_aibrc_ds_12_sclk == OFF_AIB_CLKRST_AIBRC_DS_12_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_clkrst_aibrc_ds_13_sclk == OFF_AIB_CLKRST_AIBRC_DS_13_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_clkrst_aibrc_ds_14_sclk == OFF_AIB_CLKRST_AIBRC_DS_14_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_clkrst_aibrc_ds_15_sclk == OFF_AIB_CLKRST_AIBRC_DS_15_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_clkrst_aibrc_ds_16_sclk == OFF_AIB_CLKRST_AIBRC_DS_16_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_clkrst_aibrc_ds_17_sclk == OFF_AIB_CLKRST_AIBRC_DS_17_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_clkrst_aibrc_ds_18_sclk == OFF_AIB_CLKRST_AIBRC_DS_18_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_clkrst_aibrc_ds_19_sclk == OFF_AIB_CLKRST_AIBRC_DS_19_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_clkrst_aibrc_ds_1_sclk == OFF_AIB_CLKRST_AIBRC_DS_1_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_clkrst_aibrc_ds_20_sclk == OFF_AIB_CLKRST_AIBRC_DS_20_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_clkrst_aibrc_ds_21_sclk == OFF_AIB_CLKRST_AIBRC_DS_21_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_clkrst_aibrc_ds_22_sclk == OFF_AIB_CLKRST_AIBRC_DS_22_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_clkrst_aibrc_ds_23_sclk == OFF_AIB_CLKRST_AIBRC_DS_23_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_clkrst_aibrc_ds_2_sclk == OFF_AIB_CLKRST_AIBRC_DS_2_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_clkrst_aibrc_ds_3_sclk == OFF_AIB_CLKRST_AIBRC_DS_3_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_clkrst_aibrc_ds_4_sclk == OFF_AIB_CLKRST_AIBRC_DS_4_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_clkrst_aibrc_ds_5_sclk == OFF_AIB_CLKRST_AIBRC_DS_5_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_clkrst_aibrc_ds_6_sclk == OFF_AIB_CLKRST_AIBRC_DS_6_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_clkrst_aibrc_ds_7_sclk == OFF_AIB_CLKRST_AIBRC_DS_7_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_clkrst_aibrc_ds_8_sclk == OFF_AIB_CLKRST_AIBRC_DS_8_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_clkrst_aibrc_ds_9_sclk == OFF_AIB_CLKRST_AIBRC_DS_9_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_0_sclk == OFF_AIB_IE200G_DS_0_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_0_tx_clk == OFF_AIB_IE200G_DS_0_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_10_sclk == OFF_AIB_IE200G_DS_10_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_10_tx_clk == OFF_AIB_IE200G_DS_10_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_11_sclk == OFF_AIB_IE200G_DS_11_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_11_tx_clk == OFF_AIB_IE200G_DS_11_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_12_sclk == OFF_AIB_IE200G_DS_12_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_12_tx_clk == OFF_AIB_IE200G_DS_12_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_13_sclk == OFF_AIB_IE200G_DS_13_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_13_tx_clk == OFF_AIB_IE200G_DS_13_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_14_sclk == OFF_AIB_IE200G_DS_14_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_14_tx_clk == OFF_AIB_IE200G_DS_14_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_15_sclk == OFF_AIB_IE200G_DS_15_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_15_tx_clk == OFF_AIB_IE200G_DS_15_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_16_sclk == OFF_AIB_IE200G_DS_16_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_16_tx_clk == OFF_AIB_IE200G_DS_16_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_17_sclk == OFF_AIB_IE200G_DS_17_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_17_tx_clk == OFF_AIB_IE200G_DS_17_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_18_sclk == OFF_AIB_IE200G_DS_18_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_18_tx_clk == OFF_AIB_IE200G_DS_18_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_19_sclk == OFF_AIB_IE200G_DS_19_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_19_tx_clk == OFF_AIB_IE200G_DS_19_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_1_sclk == OFF_AIB_IE200G_DS_1_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_1_tx_clk == OFF_AIB_IE200G_DS_1_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_20_sclk == OFF_AIB_IE200G_DS_20_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_20_tx_clk == OFF_AIB_IE200G_DS_20_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_21_sclk == OFF_AIB_IE200G_DS_21_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_21_tx_clk == OFF_AIB_IE200G_DS_21_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_22_sclk == OFF_AIB_IE200G_DS_22_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_22_tx_clk == OFF_AIB_IE200G_DS_22_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_23_sclk == OFF_AIB_IE200G_DS_23_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_23_tx_clk == OFF_AIB_IE200G_DS_23_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_2_sclk == OFF_AIB_IE200G_DS_2_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_2_tx_clk == OFF_AIB_IE200G_DS_2_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_3_sclk == OFF_AIB_IE200G_DS_3_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_3_tx_clk == OFF_AIB_IE200G_DS_3_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_4_sclk == OFF_AIB_IE200G_DS_4_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_4_tx_clk == OFF_AIB_IE200G_DS_4_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_5_sclk == OFF_AIB_IE200G_DS_5_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_5_tx_clk == OFF_AIB_IE200G_DS_5_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_6_sclk == OFF_AIB_IE200G_DS_6_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_6_tx_clk == OFF_AIB_IE200G_DS_6_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_7_sclk == OFF_AIB_IE200G_DS_7_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_7_tx_clk == OFF_AIB_IE200G_DS_7_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_8_sclk == OFF_AIB_IE200G_DS_8_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_8_tx_clk == OFF_AIB_IE200G_DS_8_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_9_sclk == OFF_AIB_IE200G_DS_9_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie200g_ds_9_tx_clk == OFF_AIB_IE200G_DS_9_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_0_sclk == OFF_AIB_IE400G_DS_0_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_0_tx_clk == PWR_AIB_IE400G_DS_0_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_10_sclk == OFF_AIB_IE400G_DS_10_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_10_tx_clk == PWR_AIB_IE400G_DS_10_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_11_sclk == OFF_AIB_IE400G_DS_11_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_11_tx_clk == PWR_AIB_IE400G_DS_11_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_12_sclk == OFF_AIB_IE400G_DS_12_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_12_tx_clk == PWR_AIB_IE400G_DS_12_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_13_sclk == OFF_AIB_IE400G_DS_13_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_13_tx_clk == PWR_AIB_IE400G_DS_13_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_14_sclk == OFF_AIB_IE400G_DS_14_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_14_tx_clk == PWR_AIB_IE400G_DS_14_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_15_sclk == OFF_AIB_IE400G_DS_15_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_15_tx_clk == PWR_AIB_IE400G_DS_15_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_16_sclk == OFF_AIB_IE400G_DS_16_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_16_tx_clk == PWR_AIB_IE400G_DS_16_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_17_sclk == OFF_AIB_IE400G_DS_17_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_17_tx_clk == PWR_AIB_IE400G_DS_17_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_18_sclk == OFF_AIB_IE400G_DS_18_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_18_tx_clk == OFF_AIB_IE400G_DS_18_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_19_sclk == OFF_AIB_IE400G_DS_19_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_19_tx_clk == OFF_AIB_IE400G_DS_19_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_1_sclk == OFF_AIB_IE400G_DS_1_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_1_tx_clk == PWR_AIB_IE400G_DS_1_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_20_sclk == OFF_AIB_IE400G_DS_20_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_20_tx_clk == OFF_AIB_IE400G_DS_20_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_21_sclk == OFF_AIB_IE400G_DS_21_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_21_tx_clk == OFF_AIB_IE400G_DS_21_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_22_sclk == OFF_AIB_IE400G_DS_22_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_22_tx_clk == OFF_AIB_IE400G_DS_22_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_23_sclk == OFF_AIB_IE400G_DS_23_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_23_tx_clk == OFF_AIB_IE400G_DS_23_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_2_sclk == OFF_AIB_IE400G_DS_2_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_2_tx_clk == PWR_AIB_IE400G_DS_2_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_3_sclk == OFF_AIB_IE400G_DS_3_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_3_tx_clk == PWR_AIB_IE400G_DS_3_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_4_sclk == OFF_AIB_IE400G_DS_4_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_4_tx_clk == PWR_AIB_IE400G_DS_4_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_5_sclk == OFF_AIB_IE400G_DS_5_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_5_tx_clk == PWR_AIB_IE400G_DS_5_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_6_sclk == OFF_AIB_IE400G_DS_6_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_6_tx_clk == PWR_AIB_IE400G_DS_6_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_7_sclk == OFF_AIB_IE400G_DS_7_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_7_tx_clk == PWR_AIB_IE400G_DS_7_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_8_sclk == OFF_AIB_IE400G_DS_8_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_8_tx_clk == PWR_AIB_IE400G_DS_8_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_9_sclk == OFF_AIB_IE400G_DS_9_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aib_ie400g_ds_9_tx_clk == PWR_AIB_IE400G_DS_9_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e200g_us_0_pma_internal_clk1 == OFF_AIBRC_CLKRST_E200G_US_0_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e200g_us_0_pma_internal_clk2 == OFF_AIBRC_CLKRST_E200G_US_0_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e200g_us_0_standalonecoreclk == OFF_AIBRC_CLKRST_E200G_US_0_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e200g_us_0_xcvr_quad_refclk1 == OFF_AIBRC_CLKRST_E200G_US_0_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e200g_us_0_xcvr_quad_refclk2 == OFF_AIBRC_CLKRST_E200G_US_0_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e200g_us_1_pma_internal_clk1 == OFF_AIBRC_CLKRST_E200G_US_1_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e200g_us_1_pma_internal_clk2 == OFF_AIBRC_CLKRST_E200G_US_1_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e200g_us_1_standalonecoreclk == OFF_AIBRC_CLKRST_E200G_US_1_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e200g_us_1_xcvr_quad_refclk1 == OFF_AIBRC_CLKRST_E200G_US_1_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e200g_us_1_xcvr_quad_refclk2 == OFF_AIBRC_CLKRST_E200G_US_1_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e200g_us_2_pma_internal_clk1 == OFF_AIBRC_CLKRST_E200G_US_2_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e200g_us_2_pma_internal_clk2 == OFF_AIBRC_CLKRST_E200G_US_2_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e200g_us_2_standalonecoreclk == OFF_AIBRC_CLKRST_E200G_US_2_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e200g_us_2_xcvr_quad_refclk1 == OFF_AIBRC_CLKRST_E200G_US_2_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e200g_us_2_xcvr_quad_refclk2 == OFF_AIBRC_CLKRST_E200G_US_2_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e200g_us_3_pma_internal_clk1 == OFF_AIBRC_CLKRST_E200G_US_3_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e200g_us_3_pma_internal_clk2 == OFF_AIBRC_CLKRST_E200G_US_3_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e200g_us_3_standalonecoreclk == OFF_AIBRC_CLKRST_E200G_US_3_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e200g_us_3_xcvr_quad_refclk1 == OFF_AIBRC_CLKRST_E200G_US_3_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e200g_us_3_xcvr_quad_refclk2 == OFF_AIBRC_CLKRST_E200G_US_3_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_0_pma_internal_clk1 == OFF_AIBRC_CLKRST_E400G_US_0_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_0_pma_internal_clk2 == OFF_AIBRC_CLKRST_E400G_US_0_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_0_standalonecoreclk == OFF_AIBRC_CLKRST_E400G_US_0_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_0_xcvr_quad_refclk1 == OFF_AIBRC_CLKRST_E400G_US_0_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_0_xcvr_quad_refclk2 == OFF_AIBRC_CLKRST_E400G_US_0_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_10_pma_internal_clk1 == OFF_AIBRC_CLKRST_E400G_US_10_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_10_pma_internal_clk2 == OFF_AIBRC_CLKRST_E400G_US_10_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_10_standalonecoreclk == OFF_AIBRC_CLKRST_E400G_US_10_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_10_xcvr_quad_refclk1 == OFF_AIBRC_CLKRST_E400G_US_10_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_10_xcvr_quad_refclk2 == OFF_AIBRC_CLKRST_E400G_US_10_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_11_pma_internal_clk1 == OFF_AIBRC_CLKRST_E400G_US_11_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_11_pma_internal_clk2 == OFF_AIBRC_CLKRST_E400G_US_11_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_11_standalonecoreclk == OFF_AIBRC_CLKRST_E400G_US_11_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_11_xcvr_quad_refclk1 == OFF_AIBRC_CLKRST_E400G_US_11_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_11_xcvr_quad_refclk2 == OFF_AIBRC_CLKRST_E400G_US_11_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_1_pma_internal_clk1 == OFF_AIBRC_CLKRST_E400G_US_1_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_1_pma_internal_clk2 == OFF_AIBRC_CLKRST_E400G_US_1_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_1_standalonecoreclk == OFF_AIBRC_CLKRST_E400G_US_1_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_1_xcvr_quad_refclk1 == OFF_AIBRC_CLKRST_E400G_US_1_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_1_xcvr_quad_refclk2 == OFF_AIBRC_CLKRST_E400G_US_1_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_2_pma_internal_clk1 == OFF_AIBRC_CLKRST_E400G_US_2_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_2_pma_internal_clk2 == OFF_AIBRC_CLKRST_E400G_US_2_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_2_standalonecoreclk == OFF_AIBRC_CLKRST_E400G_US_2_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_2_xcvr_quad_refclk1 == OFF_AIBRC_CLKRST_E400G_US_2_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_2_xcvr_quad_refclk2 == OFF_AIBRC_CLKRST_E400G_US_2_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_3_pma_internal_clk1 == OFF_AIBRC_CLKRST_E400G_US_3_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_3_pma_internal_clk2 == OFF_AIBRC_CLKRST_E400G_US_3_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_3_standalonecoreclk == OFF_AIBRC_CLKRST_E400G_US_3_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_3_xcvr_quad_refclk1 == OFF_AIBRC_CLKRST_E400G_US_3_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_3_xcvr_quad_refclk2 == OFF_AIBRC_CLKRST_E400G_US_3_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_4_pma_internal_clk1 == OFF_AIBRC_CLKRST_E400G_US_4_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_4_pma_internal_clk2 == OFF_AIBRC_CLKRST_E400G_US_4_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_4_standalonecoreclk == OFF_AIBRC_CLKRST_E400G_US_4_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_4_xcvr_quad_refclk1 == OFF_AIBRC_CLKRST_E400G_US_4_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_4_xcvr_quad_refclk2 == OFF_AIBRC_CLKRST_E400G_US_4_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_5_pma_internal_clk1 == OFF_AIBRC_CLKRST_E400G_US_5_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_5_pma_internal_clk2 == OFF_AIBRC_CLKRST_E400G_US_5_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_5_standalonecoreclk == OFF_AIBRC_CLKRST_E400G_US_5_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_5_xcvr_quad_refclk1 == OFF_AIBRC_CLKRST_E400G_US_5_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_5_xcvr_quad_refclk2 == OFF_AIBRC_CLKRST_E400G_US_5_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_6_pma_internal_clk1 == OFF_AIBRC_CLKRST_E400G_US_6_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_6_pma_internal_clk2 == OFF_AIBRC_CLKRST_E400G_US_6_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_6_standalonecoreclk == OFF_AIBRC_CLKRST_E400G_US_6_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_6_xcvr_quad_refclk1 == OFF_AIBRC_CLKRST_E400G_US_6_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_6_xcvr_quad_refclk2 == OFF_AIBRC_CLKRST_E400G_US_6_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_7_pma_internal_clk1 == OFF_AIBRC_CLKRST_E400G_US_7_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_7_pma_internal_clk2 == OFF_AIBRC_CLKRST_E400G_US_7_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_7_standalonecoreclk == OFF_AIBRC_CLKRST_E400G_US_7_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_7_xcvr_quad_refclk1 == OFF_AIBRC_CLKRST_E400G_US_7_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_7_xcvr_quad_refclk2 == OFF_AIBRC_CLKRST_E400G_US_7_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_8_pma_internal_clk1 == OFF_AIBRC_CLKRST_E400G_US_8_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_8_pma_internal_clk2 == OFF_AIBRC_CLKRST_E400G_US_8_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_8_standalonecoreclk == OFF_AIBRC_CLKRST_E400G_US_8_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_8_xcvr_quad_refclk1 == OFF_AIBRC_CLKRST_E400G_US_8_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_8_xcvr_quad_refclk2 == OFF_AIBRC_CLKRST_E400G_US_8_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_9_pma_internal_clk1 == OFF_AIBRC_CLKRST_E400G_US_9_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_9_pma_internal_clk2 == OFF_AIBRC_CLKRST_E400G_US_9_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_9_standalonecoreclk == OFF_AIBRC_CLKRST_E400G_US_9_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_9_xcvr_quad_refclk1 == OFF_AIBRC_CLKRST_E400G_US_9_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_e400g_us_9_xcvr_quad_refclk2 == OFF_AIBRC_CLKRST_E400G_US_9_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_0_pma_internal_clk1 == OFF_AIBRC_CLKRST_PCIE_US_0_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_0_pma_internal_clk2 == OFF_AIBRC_CLKRST_PCIE_US_0_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_0_standalonecoreclk == OFF_AIBRC_CLKRST_PCIE_US_0_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_0_xcvr_quad_refclk1 == OFF_AIBRC_CLKRST_PCIE_US_0_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_0_xcvr_quad_refclk2 == OFF_AIBRC_CLKRST_PCIE_US_0_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_1_pma_internal_clk1 == OFF_AIBRC_CLKRST_PCIE_US_1_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_1_pma_internal_clk2 == OFF_AIBRC_CLKRST_PCIE_US_1_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_1_standalonecoreclk == OFF_AIBRC_CLKRST_PCIE_US_1_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_1_xcvr_quad_refclk1 == OFF_AIBRC_CLKRST_PCIE_US_1_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_1_xcvr_quad_refclk2 == OFF_AIBRC_CLKRST_PCIE_US_1_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_2_pma_internal_clk1 == OFF_AIBRC_CLKRST_PCIE_US_2_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_2_pma_internal_clk2 == OFF_AIBRC_CLKRST_PCIE_US_2_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_2_standalonecoreclk == OFF_AIBRC_CLKRST_PCIE_US_2_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_2_xcvr_quad_refclk1 == OFF_AIBRC_CLKRST_PCIE_US_2_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_2_xcvr_quad_refclk2 == OFF_AIBRC_CLKRST_PCIE_US_2_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_3_pma_internal_clk1 == OFF_AIBRC_CLKRST_PCIE_US_3_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_3_pma_internal_clk2 == OFF_AIBRC_CLKRST_PCIE_US_3_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_3_standalonecoreclk == OFF_AIBRC_CLKRST_PCIE_US_3_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_3_xcvr_quad_refclk1 == OFF_AIBRC_CLKRST_PCIE_US_3_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_3_xcvr_quad_refclk2 == OFF_AIBRC_CLKRST_PCIE_US_3_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_4_pma_internal_clk1 == OFF_AIBRC_CLKRST_PCIE_US_4_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_4_pma_internal_clk2 == OFF_AIBRC_CLKRST_PCIE_US_4_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_4_standalonecoreclk == OFF_AIBRC_CLKRST_PCIE_US_4_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_4_xcvr_quad_refclk1 == OFF_AIBRC_CLKRST_PCIE_US_4_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_4_xcvr_quad_refclk2 == OFF_AIBRC_CLKRST_PCIE_US_4_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_5_pma_internal_clk1 == OFF_AIBRC_CLKRST_PCIE_US_5_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_5_pma_internal_clk2 == OFF_AIBRC_CLKRST_PCIE_US_5_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_5_standalonecoreclk == OFF_AIBRC_CLKRST_PCIE_US_5_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_5_xcvr_quad_refclk1 == OFF_AIBRC_CLKRST_PCIE_US_5_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_5_xcvr_quad_refclk2 == OFF_AIBRC_CLKRST_PCIE_US_5_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_6_pma_internal_clk1 == OFF_AIBRC_CLKRST_PCIE_US_6_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_6_pma_internal_clk2 == OFF_AIBRC_CLKRST_PCIE_US_6_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_6_standalonecoreclk == OFF_AIBRC_CLKRST_PCIE_US_6_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_6_xcvr_quad_refclk1 == OFF_AIBRC_CLKRST_PCIE_US_6_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_6_xcvr_quad_refclk2 == OFF_AIBRC_CLKRST_PCIE_US_6_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_7_pma_internal_clk1 == OFF_AIBRC_CLKRST_PCIE_US_7_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_7_pma_internal_clk2 == OFF_AIBRC_CLKRST_PCIE_US_7_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_7_standalonecoreclk == OFF_AIBRC_CLKRST_PCIE_US_7_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_7_xcvr_quad_refclk1 == OFF_AIBRC_CLKRST_PCIE_US_7_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_aibrc_clkrst_pcie_us_7_xcvr_quad_refclk2 == OFF_AIBRC_CLKRST_PCIE_US_7_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_ctrl_dft_ie2hip_ip_dfx_clk == OFF_CTRL_DFT_IE2HIP_IP_DFX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_ctrl_dft_ie2lphy_ip_dfx_clk == OFF_CTRL_DFT_IE2LPHY_IP_DFX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_ctrl_dft_ie4hip_ip_dfx_clk == OFF_CTRL_DFT_IE4HIP_IP_DFX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_ctrl_dft_ie4lphy_ip_dfx_clk == OFF_CTRL_DFT_IE4LPHY_IP_DFX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_ctrl_dft_ipcie_ip_dfx_clk == OFF_CTRL_DFT_IPCIE_IP_DFX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_ctrl_dft_ipcie_pcs_ip_dfx_clk == OFF_CTRL_DFT_IPCIE_PCS_IP_DFX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_ctrl_lpct_aibrc_slv_lpct_clk == OFF_CTRL_LPCT_AIBRC_SLV_LPCT_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_ctrl_pll_aibrc_ip_pll_0_slice0_clk == PWR_CTRL_PLL_AIBRC_IP_PLL_0_SLICE0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_ctrl_pll_aibrc_ip_pll_0_slice1_clk == PWR_CTRL_PLL_AIBRC_IP_PLL_0_SLICE1_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_ctrl_pll_aibrc_ip_pll_0_slice2_clk == PWR_CTRL_PLL_AIBRC_IP_PLL_0_SLICE2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_ctrl_pll_aibrc_ip_pll_0_slice3_clk == OFF_CTRL_PLL_AIBRC_IP_PLL_0_SLICE3_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_ctrl_pll_aibrc_ip_pll_1_slice0_clk == PWR_CTRL_PLL_AIBRC_IP_PLL_1_SLICE0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_ctrl_pll_aibrc_ip_pll_1_slice1_clk == PWR_CTRL_PLL_AIBRC_IP_PLL_1_SLICE1_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_ctrl_pll_aibrc_ip_pll_1_slice2_clk == PWR_CTRL_PLL_AIBRC_IP_PLL_1_SLICE2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_ctrl_pll_aibrc_ip_pll_1_slice3_clk == OFF_CTRL_PLL_AIBRC_IP_PLL_1_SLICE3_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_ctrl_pll_aibrc_ip_pll_2_slice0_clk == PWR_CTRL_PLL_AIBRC_IP_PLL_2_SLICE0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_ctrl_pll_aibrc_ip_pll_2_slice1_clk == PWR_CTRL_PLL_AIBRC_IP_PLL_2_SLICE1_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_ctrl_pll_aibrc_ip_pll_2_slice2_clk == PWR_CTRL_PLL_AIBRC_IP_PLL_2_SLICE2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_ctrl_pll_aibrc_ip_pll_2_slice3_clk == PWR_CTRL_PLL_AIBRC_IP_PLL_2_SLICE3_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_e400g_idvp1_aibrc_ip_idvfreqa_clk == OFF_E400G_IDVP1_AIBRC_IP_IDVFREQA_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_e400g_idvp1_aibrc_ip_idvfreqb_clk == OFF_E400G_IDVP1_AIBRC_IP_IDVFREQB_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_e400g_idvp1_aibrc_ip_idvtclk == OFF_E400G_IDVP1_AIBRC_IP_IDVTCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_global_avmm_ctrl_ie2hip_slv_clk == OFF_GLOBAL_AVMM_CTRL_IE2HIP_SLV_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_global_avmm_ctrl_ie2lphy_slv_clk == OFF_GLOBAL_AVMM_CTRL_IE2LPHY_SLV_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_global_avmm_ctrl_ie4hip_slv_clk == OFF_GLOBAL_AVMM_CTRL_IE4HIP_SLV_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_global_avmm_ctrl_ie4lphy_slv_clk == OFF_GLOBAL_AVMM_CTRL_IE4LPHY_SLV_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_global_avmm_ctrl_ipcie_slv_clk == OFF_GLOBAL_AVMM_CTRL_IPCIE_SLV_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_0_aib1_tx_st_clk == PWR_IAIB_E200G_US_0_AIB1_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_0_aib2_rx_st_clk == OFF_IAIB_E200G_US_0_AIB2_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_0_aib2_tx_st_clk == OFF_IAIB_E200G_US_0_AIB2_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_0_aib3_rx_st_clk == OFF_IAIB_E200G_US_0_AIB3_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_0_aib3_tx_st_clk == OFF_IAIB_E200G_US_0_AIB3_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_0_rx_clk == PWR_IAIB_E200G_US_0_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_1_aib1_tx_st_clk == PWR_IAIB_E200G_US_1_AIB1_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_1_aib2_rx_st_clk == OFF_IAIB_E200G_US_1_AIB2_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_1_aib2_tx_st_clk == OFF_IAIB_E200G_US_1_AIB2_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_1_aib3_rx_st_clk == OFF_IAIB_E200G_US_1_AIB3_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_1_aib3_tx_st_clk == OFF_IAIB_E200G_US_1_AIB3_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_1_rx_clk == PWR_IAIB_E200G_US_1_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_2_aib1_tx_st_clk == PWR_IAIB_E200G_US_2_AIB1_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_2_aib2_rx_st_clk == OFF_IAIB_E200G_US_2_AIB2_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_2_aib2_tx_st_clk == OFF_IAIB_E200G_US_2_AIB2_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_2_aib3_rx_st_clk == OFF_IAIB_E200G_US_2_AIB3_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_2_aib3_tx_st_clk == OFF_IAIB_E200G_US_2_AIB3_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_2_rx_clk == PWR_IAIB_E200G_US_2_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_3_aib1_tx_st_clk == PWR_IAIB_E200G_US_3_AIB1_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_3_aib2_rx_st_clk == OFF_IAIB_E200G_US_3_AIB2_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_3_aib2_tx_st_clk == OFF_IAIB_E200G_US_3_AIB2_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_3_aib3_rx_st_clk == OFF_IAIB_E200G_US_3_AIB3_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_3_aib3_tx_st_clk == OFF_IAIB_E200G_US_3_AIB3_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_3_rx_clk == PWR_IAIB_E200G_US_3_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_4_aib1_tx_st_clk == PWR_IAIB_E200G_US_4_AIB1_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_4_aib2_rx_st_clk == OFF_IAIB_E200G_US_4_AIB2_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_4_aib2_tx_st_clk == OFF_IAIB_E200G_US_4_AIB2_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_4_aib3_rx_st_clk == OFF_IAIB_E200G_US_4_AIB3_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_4_aib3_tx_st_clk == OFF_IAIB_E200G_US_4_AIB3_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_4_rx_clk == PWR_IAIB_E200G_US_4_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_5_aib1_tx_st_clk == PWR_IAIB_E200G_US_5_AIB1_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_5_aib2_rx_st_clk == OFF_IAIB_E200G_US_5_AIB2_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_5_aib2_tx_st_clk == OFF_IAIB_E200G_US_5_AIB2_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_5_aib3_rx_st_clk == OFF_IAIB_E200G_US_5_AIB3_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_5_aib3_tx_st_clk == OFF_IAIB_E200G_US_5_AIB3_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_5_rx_clk == PWR_IAIB_E200G_US_5_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_6_aib1_tx_st_clk == PWR_IAIB_E200G_US_6_AIB1_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_6_aib2_rx_st_clk == OFF_IAIB_E200G_US_6_AIB2_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_6_aib2_tx_st_clk == OFF_IAIB_E200G_US_6_AIB2_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_6_aib3_rx_st_clk == OFF_IAIB_E200G_US_6_AIB3_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_6_aib3_tx_st_clk == OFF_IAIB_E200G_US_6_AIB3_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_6_rx_clk == PWR_IAIB_E200G_US_6_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_7_aib1_tx_st_clk == PWR_IAIB_E200G_US_7_AIB1_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_7_aib2_rx_st_clk == OFF_IAIB_E200G_US_7_AIB2_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_7_aib2_tx_st_clk == OFF_IAIB_E200G_US_7_AIB2_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_7_aib3_rx_st_clk == OFF_IAIB_E200G_US_7_AIB3_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_7_aib3_tx_st_clk == OFF_IAIB_E200G_US_7_AIB3_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e200g_us_7_rx_clk == PWR_IAIB_E200G_US_7_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_test_us_0_test_clk == OFF_IAIB_E400G_TEST_US_0_TEST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_test_us_1_test_clk == OFF_IAIB_E400G_TEST_US_1_TEST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_test_us_2_test_clk == OFF_IAIB_E400G_TEST_US_2_TEST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_test_us_3_test_clk == OFF_IAIB_E400G_TEST_US_3_TEST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_test_us_4_test_clk == OFF_IAIB_E400G_TEST_US_4_TEST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_test_us_5_test_clk == OFF_IAIB_E400G_TEST_US_5_TEST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_0_aib1_tx_st_clk == PWR_IAIB_E400G_US_0_AIB1_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_0_aib2_rx_st_clk == OFF_IAIB_E400G_US_0_AIB2_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_0_aib2_tx_st_clk == OFF_IAIB_E400G_US_0_AIB2_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_0_aib3_rx_st_clk == OFF_IAIB_E400G_US_0_AIB3_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_0_aib3_tx_st_clk == OFF_IAIB_E400G_US_0_AIB3_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_0_rx_clk == PWR_IAIB_E400G_US_0_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_10_aib1_tx_st_clk == PWR_IAIB_E400G_US_10_AIB1_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_10_aib2_rx_st_clk == OFF_IAIB_E400G_US_10_AIB2_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_10_aib2_tx_st_clk == PWR_IAIB_E400G_US_10_AIB2_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_10_aib3_rx_st_clk == OFF_IAIB_E400G_US_10_AIB3_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_10_aib3_tx_st_clk == PWR_IAIB_E400G_US_10_AIB3_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_10_rx_clk == PWR_IAIB_E400G_US_10_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_11_aib1_tx_st_clk == PWR_IAIB_E400G_US_11_AIB1_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_11_aib2_rx_st_clk == OFF_IAIB_E400G_US_11_AIB2_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_11_aib2_tx_st_clk == OFF_IAIB_E400G_US_11_AIB2_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_11_aib3_rx_st_clk == OFF_IAIB_E400G_US_11_AIB3_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_11_aib3_tx_st_clk == OFF_IAIB_E400G_US_11_AIB3_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_11_rx_clk == PWR_IAIB_E400G_US_11_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_12_aib1_tx_st_clk == PWR_IAIB_E400G_US_12_AIB1_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_12_aib2_rx_st_clk == PWR_IAIB_E400G_US_12_AIB2_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_12_aib2_tx_st_clk == PWR_IAIB_E400G_US_12_AIB2_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_12_aib3_rx_st_clk == PWR_IAIB_E400G_US_12_AIB3_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_12_aib3_tx_st_clk == PWR_IAIB_E400G_US_12_AIB3_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_12_rx_clk == PWR_IAIB_E400G_US_12_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_13_aib1_tx_st_clk == PWR_IAIB_E400G_US_13_AIB1_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_13_aib2_rx_st_clk == OFF_IAIB_E400G_US_13_AIB2_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_13_aib2_tx_st_clk == PWR_IAIB_E400G_US_13_AIB2_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_13_aib3_rx_st_clk == OFF_IAIB_E400G_US_13_AIB3_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_13_aib3_tx_st_clk == PWR_IAIB_E400G_US_13_AIB3_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_13_rx_clk == PWR_IAIB_E400G_US_13_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_14_aib1_tx_st_clk == PWR_IAIB_E400G_US_14_AIB1_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_14_aib2_rx_st_clk == OFF_IAIB_E400G_US_14_AIB2_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_14_aib2_tx_st_clk == OFF_IAIB_E400G_US_14_AIB2_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_14_aib3_rx_st_clk == OFF_IAIB_E400G_US_14_AIB3_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_14_aib3_tx_st_clk == OFF_IAIB_E400G_US_14_AIB3_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_14_rx_clk == PWR_IAIB_E400G_US_14_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_15_aib1_tx_st_clk == PWR_IAIB_E400G_US_15_AIB1_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_15_aib2_rx_st_clk == PWR_IAIB_E400G_US_15_AIB2_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_15_aib2_tx_st_clk == PWR_IAIB_E400G_US_15_AIB2_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_15_aib3_rx_st_clk == PWR_IAIB_E400G_US_15_AIB3_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_15_aib3_tx_st_clk == PWR_IAIB_E400G_US_15_AIB3_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_15_rx_clk == PWR_IAIB_E400G_US_15_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_16_aib1_tx_st_clk == PWR_IAIB_E400G_US_16_AIB1_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_16_aib2_rx_st_clk == PWR_IAIB_E400G_US_16_AIB2_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_16_aib2_tx_st_clk == PWR_IAIB_E400G_US_16_AIB2_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_16_aib3_rx_st_clk == PWR_IAIB_E400G_US_16_AIB3_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_16_aib3_tx_st_clk == PWR_IAIB_E400G_US_16_AIB3_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_16_rx_clk == PWR_IAIB_E400G_US_16_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_17_aib1_tx_st_clk == PWR_IAIB_E400G_US_17_AIB1_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_17_aib2_rx_st_clk == PWR_IAIB_E400G_US_17_AIB2_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_17_aib2_tx_st_clk == PWR_IAIB_E400G_US_17_AIB2_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_17_aib3_rx_st_clk == PWR_IAIB_E400G_US_17_AIB3_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_17_aib3_tx_st_clk == PWR_IAIB_E400G_US_17_AIB3_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_17_rx_clk == PWR_IAIB_E400G_US_17_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_1_aib1_tx_st_clk == PWR_IAIB_E400G_US_1_AIB1_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_1_aib2_rx_st_clk == OFF_IAIB_E400G_US_1_AIB2_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_1_aib2_tx_st_clk == OFF_IAIB_E400G_US_1_AIB2_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_1_aib3_rx_st_clk == OFF_IAIB_E400G_US_1_AIB3_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_1_aib3_tx_st_clk == OFF_IAIB_E400G_US_1_AIB3_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_1_rx_clk == PWR_IAIB_E400G_US_1_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_2_aib1_tx_st_clk == PWR_IAIB_E400G_US_2_AIB1_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_2_aib2_rx_st_clk == OFF_IAIB_E400G_US_2_AIB2_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_2_aib2_tx_st_clk == OFF_IAIB_E400G_US_2_AIB2_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_2_aib3_rx_st_clk == OFF_IAIB_E400G_US_2_AIB3_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_2_aib3_tx_st_clk == OFF_IAIB_E400G_US_2_AIB3_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_2_rx_clk == PWR_IAIB_E400G_US_2_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_3_aib1_tx_st_clk == PWR_IAIB_E400G_US_3_AIB1_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_3_aib2_rx_st_clk == OFF_IAIB_E400G_US_3_AIB2_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_3_aib2_tx_st_clk == OFF_IAIB_E400G_US_3_AIB2_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_3_aib3_rx_st_clk == OFF_IAIB_E400G_US_3_AIB3_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_3_aib3_tx_st_clk == OFF_IAIB_E400G_US_3_AIB3_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_3_rx_clk == PWR_IAIB_E400G_US_3_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_4_aib1_tx_st_clk == PWR_IAIB_E400G_US_4_AIB1_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_4_aib2_rx_st_clk == OFF_IAIB_E400G_US_4_AIB2_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_4_aib2_tx_st_clk == OFF_IAIB_E400G_US_4_AIB2_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_4_aib3_rx_st_clk == OFF_IAIB_E400G_US_4_AIB3_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_4_aib3_tx_st_clk == OFF_IAIB_E400G_US_4_AIB3_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_4_rx_clk == PWR_IAIB_E400G_US_4_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_5_aib1_tx_st_clk == PWR_IAIB_E400G_US_5_AIB1_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_5_aib2_rx_st_clk == OFF_IAIB_E400G_US_5_AIB2_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_5_aib2_tx_st_clk == OFF_IAIB_E400G_US_5_AIB2_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_5_aib3_rx_st_clk == OFF_IAIB_E400G_US_5_AIB3_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_5_aib3_tx_st_clk == OFF_IAIB_E400G_US_5_AIB3_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_5_rx_clk == PWR_IAIB_E400G_US_5_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_6_aib1_tx_st_clk == PWR_IAIB_E400G_US_6_AIB1_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_6_aib2_rx_st_clk == OFF_IAIB_E400G_US_6_AIB2_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_6_aib2_tx_st_clk == OFF_IAIB_E400G_US_6_AIB2_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_6_aib3_rx_st_clk == OFF_IAIB_E400G_US_6_AIB3_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_6_aib3_tx_st_clk == OFF_IAIB_E400G_US_6_AIB3_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_6_rx_clk == PWR_IAIB_E400G_US_6_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_7_aib1_tx_st_clk == PWR_IAIB_E400G_US_7_AIB1_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_7_aib2_rx_st_clk == PWR_IAIB_E400G_US_7_AIB2_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_7_aib2_tx_st_clk == OFF_IAIB_E400G_US_7_AIB2_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_7_aib3_rx_st_clk == PWR_IAIB_E400G_US_7_AIB3_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_7_aib3_tx_st_clk == OFF_IAIB_E400G_US_7_AIB3_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_7_rx_clk == PWR_IAIB_E400G_US_7_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_8_aib1_tx_st_clk == PWR_IAIB_E400G_US_8_AIB1_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_8_aib2_rx_st_clk == OFF_IAIB_E400G_US_8_AIB2_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_8_aib2_tx_st_clk == OFF_IAIB_E400G_US_8_AIB2_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_8_aib3_rx_st_clk == OFF_IAIB_E400G_US_8_AIB3_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_8_aib3_tx_st_clk == OFF_IAIB_E400G_US_8_AIB3_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_8_rx_clk == PWR_IAIB_E400G_US_8_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_9_aib1_tx_st_clk == PWR_IAIB_E400G_US_9_AIB1_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_9_aib2_rx_st_clk == PWR_IAIB_E400G_US_9_AIB2_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_9_aib2_tx_st_clk == OFF_IAIB_E400G_US_9_AIB2_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_9_aib3_rx_st_clk == PWR_IAIB_E400G_US_9_AIB3_RX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_9_aib3_tx_st_clk == OFF_IAIB_E400G_US_9_AIB3_TX_ST_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_e400g_us_9_rx_clk == PWR_IAIB_E400G_US_9_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_0_pld_clk == PWR_IAIB_PCIE_AIB_0_PLD_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_0_pld_clk_2x == PWR_IAIB_PCIE_AIB_0_PLD_CLK_2X
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_10_pld_clk == PWR_IAIB_PCIE_AIB_10_PLD_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_10_pld_clk_2x == PWR_IAIB_PCIE_AIB_10_PLD_CLK_2X
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_11_pld_clk == PWR_IAIB_PCIE_AIB_11_PLD_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_11_pld_clk_2x == PWR_IAIB_PCIE_AIB_11_PLD_CLK_2X
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_12_pld_clk == PWR_IAIB_PCIE_AIB_12_PLD_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_12_pld_clk_2x == PWR_IAIB_PCIE_AIB_12_PLD_CLK_2X
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_13_pld_clk == PWR_IAIB_PCIE_AIB_13_PLD_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_13_pld_clk_2x == PWR_IAIB_PCIE_AIB_13_PLD_CLK_2X
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_14_pld_clk == PWR_IAIB_PCIE_AIB_14_PLD_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_14_pld_clk_2x == PWR_IAIB_PCIE_AIB_14_PLD_CLK_2X
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_15_pld_clk == PWR_IAIB_PCIE_AIB_15_PLD_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_15_pld_clk_2x == PWR_IAIB_PCIE_AIB_15_PLD_CLK_2X
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_16_pld_clk == PWR_IAIB_PCIE_AIB_16_PLD_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_16_pld_clk_2x == PWR_IAIB_PCIE_AIB_16_PLD_CLK_2X
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_17_pld_clk == PWR_IAIB_PCIE_AIB_17_PLD_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_17_pld_clk_2x == PWR_IAIB_PCIE_AIB_17_PLD_CLK_2X
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_18_pld_clk == PWR_IAIB_PCIE_AIB_18_PLD_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_18_pld_clk_2x == PWR_IAIB_PCIE_AIB_18_PLD_CLK_2X
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_19_pld_clk == PWR_IAIB_PCIE_AIB_19_PLD_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_19_pld_clk_2x == PWR_IAIB_PCIE_AIB_19_PLD_CLK_2X
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_1_pld_clk == PWR_IAIB_PCIE_AIB_1_PLD_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_1_pld_clk_2x == PWR_IAIB_PCIE_AIB_1_PLD_CLK_2X
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_20_pld_clk == PWR_IAIB_PCIE_AIB_20_PLD_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_20_pld_clk_2x == PWR_IAIB_PCIE_AIB_20_PLD_CLK_2X
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_21_pld_clk == PWR_IAIB_PCIE_AIB_21_PLD_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_21_pld_clk_2x == PWR_IAIB_PCIE_AIB_21_PLD_CLK_2X
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_22_pld_clk == PWR_IAIB_PCIE_AIB_22_PLD_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_22_pld_clk_2x == PWR_IAIB_PCIE_AIB_22_PLD_CLK_2X
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_23_pld_clk == PWR_IAIB_PCIE_AIB_23_PLD_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_23_pld_clk_2x == PWR_IAIB_PCIE_AIB_23_PLD_CLK_2X
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_2_pld_clk == PWR_IAIB_PCIE_AIB_2_PLD_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_2_pld_clk_2x == PWR_IAIB_PCIE_AIB_2_PLD_CLK_2X
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_3_pld_clk == PWR_IAIB_PCIE_AIB_3_PLD_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_3_pld_clk_2x == PWR_IAIB_PCIE_AIB_3_PLD_CLK_2X
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_4_pld_clk == PWR_IAIB_PCIE_AIB_4_PLD_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_4_pld_clk_2x == PWR_IAIB_PCIE_AIB_4_PLD_CLK_2X
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_5_pld_clk == PWR_IAIB_PCIE_AIB_5_PLD_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_5_pld_clk_2x == PWR_IAIB_PCIE_AIB_5_PLD_CLK_2X
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_6_pld_clk == PWR_IAIB_PCIE_AIB_6_PLD_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_6_pld_clk_2x == PWR_IAIB_PCIE_AIB_6_PLD_CLK_2X
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_7_pld_clk == PWR_IAIB_PCIE_AIB_7_PLD_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_7_pld_clk_2x == PWR_IAIB_PCIE_AIB_7_PLD_CLK_2X
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_8_pld_clk == PWR_IAIB_PCIE_AIB_8_PLD_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_8_pld_clk_2x == PWR_IAIB_PCIE_AIB_8_PLD_CLK_2X
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_9_pld_clk == PWR_IAIB_PCIE_AIB_9_PLD_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_aib_9_pld_clk_2x == PWR_IAIB_PCIE_AIB_9_PLD_CLK_2X
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_0_tx_transfer_clk == OFF_IAIB_PCIE_IP_0_TX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_0_tx_transfer_div2_clk == OFF_IAIB_PCIE_IP_0_TX_TRANSFER_DIV2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_10_tx_transfer_clk == OFF_IAIB_PCIE_IP_10_TX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_10_tx_transfer_div2_clk == OFF_IAIB_PCIE_IP_10_TX_TRANSFER_DIV2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_11_tx_transfer_clk == OFF_IAIB_PCIE_IP_11_TX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_11_tx_transfer_div2_clk == OFF_IAIB_PCIE_IP_11_TX_TRANSFER_DIV2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_12_tx_transfer_clk == OFF_IAIB_PCIE_IP_12_TX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_12_tx_transfer_div2_clk == OFF_IAIB_PCIE_IP_12_TX_TRANSFER_DIV2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_13_tx_transfer_clk == OFF_IAIB_PCIE_IP_13_TX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_13_tx_transfer_div2_clk == OFF_IAIB_PCIE_IP_13_TX_TRANSFER_DIV2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_14_tx_transfer_clk == OFF_IAIB_PCIE_IP_14_TX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_14_tx_transfer_div2_clk == OFF_IAIB_PCIE_IP_14_TX_TRANSFER_DIV2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_15_tx_transfer_clk == OFF_IAIB_PCIE_IP_15_TX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_15_tx_transfer_div2_clk == OFF_IAIB_PCIE_IP_15_TX_TRANSFER_DIV2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_16_tx_transfer_clk == OFF_IAIB_PCIE_IP_16_TX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_16_tx_transfer_div2_clk == OFF_IAIB_PCIE_IP_16_TX_TRANSFER_DIV2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_17_tx_transfer_clk == OFF_IAIB_PCIE_IP_17_TX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_17_tx_transfer_div2_clk == OFF_IAIB_PCIE_IP_17_TX_TRANSFER_DIV2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_18_tx_transfer_clk == OFF_IAIB_PCIE_IP_18_TX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_18_tx_transfer_div2_clk == OFF_IAIB_PCIE_IP_18_TX_TRANSFER_DIV2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_19_tx_transfer_clk == OFF_IAIB_PCIE_IP_19_TX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_19_tx_transfer_div2_clk == OFF_IAIB_PCIE_IP_19_TX_TRANSFER_DIV2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_1_tx_transfer_clk == OFF_IAIB_PCIE_IP_1_TX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_1_tx_transfer_div2_clk == OFF_IAIB_PCIE_IP_1_TX_TRANSFER_DIV2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_20_tx_transfer_clk == OFF_IAIB_PCIE_IP_20_TX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_20_tx_transfer_div2_clk == OFF_IAIB_PCIE_IP_20_TX_TRANSFER_DIV2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_21_tx_transfer_clk == OFF_IAIB_PCIE_IP_21_TX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_21_tx_transfer_div2_clk == OFF_IAIB_PCIE_IP_21_TX_TRANSFER_DIV2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_22_tx_transfer_clk == OFF_IAIB_PCIE_IP_22_TX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_22_tx_transfer_div2_clk == OFF_IAIB_PCIE_IP_22_TX_TRANSFER_DIV2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_23_tx_transfer_clk == OFF_IAIB_PCIE_IP_23_TX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_23_tx_transfer_div2_clk == OFF_IAIB_PCIE_IP_23_TX_TRANSFER_DIV2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_2_tx_transfer_clk == OFF_IAIB_PCIE_IP_2_TX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_2_tx_transfer_div2_clk == OFF_IAIB_PCIE_IP_2_TX_TRANSFER_DIV2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_3_tx_transfer_clk == OFF_IAIB_PCIE_IP_3_TX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_3_tx_transfer_div2_clk == OFF_IAIB_PCIE_IP_3_TX_TRANSFER_DIV2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_4_tx_transfer_clk == OFF_IAIB_PCIE_IP_4_TX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_4_tx_transfer_div2_clk == OFF_IAIB_PCIE_IP_4_TX_TRANSFER_DIV2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_5_tx_transfer_clk == OFF_IAIB_PCIE_IP_5_TX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_5_tx_transfer_div2_clk == OFF_IAIB_PCIE_IP_5_TX_TRANSFER_DIV2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_6_tx_transfer_clk == OFF_IAIB_PCIE_IP_6_TX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_6_tx_transfer_div2_clk == OFF_IAIB_PCIE_IP_6_TX_TRANSFER_DIV2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_7_tx_transfer_clk == OFF_IAIB_PCIE_IP_7_TX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_7_tx_transfer_div2_clk == OFF_IAIB_PCIE_IP_7_TX_TRANSFER_DIV2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_8_tx_transfer_clk == OFF_IAIB_PCIE_IP_8_TX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_8_tx_transfer_div2_clk == OFF_IAIB_PCIE_IP_8_TX_TRANSFER_DIV2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_9_tx_transfer_clk == OFF_IAIB_PCIE_IP_9_TX_TRANSFER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_iaib_pcie_ip_9_tx_transfer_div2_clk == OFF_IAIB_PCIE_IP_9_TX_TRANSFER_DIV2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_ictrl_dfd_e200_hub_0_clk == OFF_ICTRL_DFD_E200_HUB_0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_ictrl_dfd_e200_hub_1_clk == OFF_ICTRL_DFD_E200_HUB_1_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_ictrl_dfd_e200_hub_2_clk == OFF_ICTRL_DFD_E200_HUB_2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_ictrl_dfd_e200_hub_3_clk == OFF_ICTRL_DFD_E200_HUB_3_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_ictrl_dfd_e400_hub_0_clk == OFF_ICTRL_DFD_E400_HUB_0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_ictrl_dfd_e400_hub_1_clk == OFF_ICTRL_DFD_E400_HUB_1_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_ictrl_dfd_e400_hub_2_clk == OFF_ICTRL_DFD_E400_HUB_2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_ictrl_dfd_e400_hub_3_clk == OFF_ICTRL_DFD_E400_HUB_3_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_ictrl_dfd_pcie_hub_0_clk == OFF_ICTRL_DFD_PCIE_HUB_0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_ictrl_dfd_pcie_hub_1_clk == OFF_ICTRL_DFD_PCIE_HUB_1_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_ictrl_dfd_pcie_hub_2_clk == OFF_ICTRL_DFD_PCIE_HUB_2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_ictrl_dfd_pcie_hub_3_clk == OFF_ICTRL_DFD_PCIE_HUB_3_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_ipcie_cvp_ep_avmm_clk_in == OFF_IPCIE_CVP_EP_AVMM_CLK_IN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_ac_pcie_cvp_issm_avmm_clk_out == OFF_PCIE_CVP_ISSM_AVMM_CLK_OUT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_clkrst_aibrc_ds_0_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_clkrst_aibrc_ds_10_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_clkrst_aibrc_ds_11_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_clkrst_aibrc_ds_12_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_clkrst_aibrc_ds_13_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_clkrst_aibrc_ds_14_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_clkrst_aibrc_ds_15_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_clkrst_aibrc_ds_16_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_clkrst_aibrc_ds_17_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_clkrst_aibrc_ds_18_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_clkrst_aibrc_ds_19_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_clkrst_aibrc_ds_1_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_clkrst_aibrc_ds_20_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_clkrst_aibrc_ds_21_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_clkrst_aibrc_ds_22_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_clkrst_aibrc_ds_23_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_clkrst_aibrc_ds_2_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_clkrst_aibrc_ds_3_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_clkrst_aibrc_ds_4_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_clkrst_aibrc_ds_5_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_clkrst_aibrc_ds_6_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_clkrst_aibrc_ds_7_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_clkrst_aibrc_ds_8_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_clkrst_aibrc_ds_9_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_0_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_0_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_10_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_10_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_11_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_11_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_12_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_12_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_13_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_13_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_14_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_14_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_15_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_15_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_16_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_16_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_17_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_17_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_18_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_18_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_19_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_19_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_1_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_1_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_20_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_20_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_21_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_21_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_22_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_22_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_23_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_23_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_2_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_2_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_3_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_3_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_4_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_4_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_5_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_5_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_6_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_6_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_7_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_7_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_8_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_8_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_9_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie200g_ds_9_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_0_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_0_tx_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_10_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_10_tx_clk_hz == 36'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_11_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_11_tx_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_12_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_12_tx_clk_hz == 36'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_13_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_13_tx_clk_hz == 36'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_14_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_14_tx_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_15_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_15_tx_clk_hz == 36'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_16_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_16_tx_clk_hz == 36'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_17_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_17_tx_clk_hz == 36'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_18_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_18_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_19_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_19_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_1_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_1_tx_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_20_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_20_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_21_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_21_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_22_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_22_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_23_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_23_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_2_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_2_tx_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_3_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_3_tx_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_4_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_4_tx_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_5_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_5_tx_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_6_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_6_tx_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_7_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_7_tx_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_8_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_8_tx_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_9_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aib_ie400g_ds_9_tx_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e200g_us_0_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e200g_us_0_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e200g_us_0_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e200g_us_0_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e200g_us_0_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e200g_us_1_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e200g_us_1_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e200g_us_1_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e200g_us_1_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e200g_us_1_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e200g_us_2_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e200g_us_2_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e200g_us_2_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e200g_us_2_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e200g_us_2_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e200g_us_3_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e200g_us_3_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e200g_us_3_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e200g_us_3_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e200g_us_3_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_0_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_0_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_0_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_0_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_0_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_10_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_10_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_10_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_10_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_10_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_11_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_11_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_11_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_11_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_11_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_1_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_1_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_1_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_1_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_1_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_2_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_2_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_2_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_2_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_2_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_3_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_3_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_3_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_3_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_3_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_4_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_4_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_4_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_4_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_4_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_5_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_5_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_5_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_5_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_5_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_6_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_6_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_6_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_6_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_6_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_7_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_7_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_7_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_7_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_7_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_8_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_8_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_8_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_8_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_8_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_9_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_9_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_9_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_9_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_e400g_us_9_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_0_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_0_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_0_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_0_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_0_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_1_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_1_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_1_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_1_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_1_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_2_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_2_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_2_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_2_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_2_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_3_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_3_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_3_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_3_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_3_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_4_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_4_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_4_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_4_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_4_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_5_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_5_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_5_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_5_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_5_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_6_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_6_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_6_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_6_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_6_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_7_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_7_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_7_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_7_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_aibrc_clkrst_pcie_us_7_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_ctrl_dft_ie2hip_ip_dfx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_ctrl_dft_ie2lphy_ip_dfx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_ctrl_dft_ie4hip_ip_dfx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_ctrl_dft_ie4lphy_ip_dfx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_ctrl_dft_ipcie_ip_dfx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_ctrl_dft_ipcie_pcs_ip_dfx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_ctrl_lpct_aibrc_slv_lpct_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_ctrl_pll_aibrc_ip_pll_0_slice0_clk_hz == 36'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_ctrl_pll_aibrc_ip_pll_0_slice1_clk_hz == 36'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_ctrl_pll_aibrc_ip_pll_0_slice2_clk_hz == 36'd250000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_ctrl_pll_aibrc_ip_pll_0_slice3_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_ctrl_pll_aibrc_ip_pll_1_slice0_clk_hz == 36'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_ctrl_pll_aibrc_ip_pll_1_slice1_clk_hz == 36'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_ctrl_pll_aibrc_ip_pll_1_slice2_clk_hz == 36'd250000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_ctrl_pll_aibrc_ip_pll_1_slice3_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_ctrl_pll_aibrc_ip_pll_2_slice0_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_ctrl_pll_aibrc_ip_pll_2_slice1_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_ctrl_pll_aibrc_ip_pll_2_slice2_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_ctrl_pll_aibrc_ip_pll_2_slice3_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_e400g_idvp1_aibrc_ip_idvfreqa_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_e400g_idvp1_aibrc_ip_idvfreqb_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_e400g_idvp1_aibrc_ip_idvtclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_global_avmm_ctrl_ie2hip_slv_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_global_avmm_ctrl_ie2lphy_slv_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_global_avmm_ctrl_ie4hip_slv_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_global_avmm_ctrl_ie4lphy_slv_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_global_avmm_ctrl_ipcie_slv_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_0_aib1_tx_st_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_0_aib2_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_0_aib2_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_0_aib3_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_0_aib3_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_0_rx_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_1_aib1_tx_st_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_1_aib2_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_1_aib2_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_1_aib3_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_1_aib3_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_1_rx_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_2_aib1_tx_st_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_2_aib2_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_2_aib2_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_2_aib3_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_2_aib3_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_2_rx_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_3_aib1_tx_st_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_3_aib2_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_3_aib2_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_3_aib3_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_3_aib3_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_3_rx_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_4_aib1_tx_st_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_4_aib2_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_4_aib2_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_4_aib3_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_4_aib3_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_4_rx_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_5_aib1_tx_st_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_5_aib2_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_5_aib2_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_5_aib3_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_5_aib3_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_5_rx_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_6_aib1_tx_st_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_6_aib2_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_6_aib2_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_6_aib3_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_6_aib3_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_6_rx_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_7_aib1_tx_st_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_7_aib2_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_7_aib2_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_7_aib3_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_7_aib3_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e200g_us_7_rx_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_test_us_0_test_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_test_us_1_test_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_test_us_2_test_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_test_us_3_test_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_test_us_4_test_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_test_us_5_test_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_0_aib1_tx_st_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_0_aib2_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_0_aib2_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_0_aib3_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_0_aib3_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_0_rx_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_10_aib1_tx_st_clk_hz == 36'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_10_aib2_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_10_aib2_tx_st_clk_hz == 36'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_10_aib3_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_10_aib3_tx_st_clk_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_10_rx_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_11_aib1_tx_st_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_11_aib2_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_11_aib2_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_11_aib3_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_11_aib3_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_11_rx_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_12_aib1_tx_st_clk_hz == 36'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_12_aib2_rx_st_clk_hz == 36'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_12_aib2_tx_st_clk_hz == 36'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_12_aib3_rx_st_clk_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_12_aib3_tx_st_clk_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_12_rx_clk_hz == 36'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_13_aib1_tx_st_clk_hz == 36'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_13_aib2_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_13_aib2_tx_st_clk_hz == 36'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_13_aib3_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_13_aib3_tx_st_clk_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_13_rx_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_14_aib1_tx_st_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_14_aib2_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_14_aib2_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_14_aib3_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_14_aib3_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_14_rx_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_15_aib1_tx_st_clk_hz == 36'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_15_aib2_rx_st_clk_hz == 36'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_15_aib2_tx_st_clk_hz == 36'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_15_aib3_rx_st_clk_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_15_aib3_tx_st_clk_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_15_rx_clk_hz == 36'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_16_aib1_tx_st_clk_hz == 36'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_16_aib2_rx_st_clk_hz == 36'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_16_aib2_tx_st_clk_hz == 36'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_16_aib3_rx_st_clk_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_16_aib3_tx_st_clk_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_16_rx_clk_hz == 36'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_17_aib1_tx_st_clk_hz == 36'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_17_aib2_rx_st_clk_hz == 36'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_17_aib2_tx_st_clk_hz == 36'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_17_aib3_rx_st_clk_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_17_aib3_tx_st_clk_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_17_rx_clk_hz == 36'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_1_aib1_tx_st_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_1_aib2_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_1_aib2_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_1_aib3_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_1_aib3_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_1_rx_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_2_aib1_tx_st_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_2_aib2_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_2_aib2_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_2_aib3_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_2_aib3_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_2_rx_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_3_aib1_tx_st_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_3_aib2_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_3_aib2_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_3_aib3_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_3_aib3_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_3_rx_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_4_aib1_tx_st_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_4_aib2_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_4_aib2_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_4_aib3_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_4_aib3_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_4_rx_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_5_aib1_tx_st_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_5_aib2_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_5_aib2_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_5_aib3_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_5_aib3_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_5_rx_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_6_aib1_tx_st_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_6_aib2_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_6_aib2_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_6_aib3_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_6_aib3_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_6_rx_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_7_aib1_tx_st_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_7_aib2_rx_st_clk_hz == 36'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_7_aib2_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_7_aib3_rx_st_clk_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_7_aib3_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_7_rx_clk_hz == 36'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_8_aib1_tx_st_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_8_aib2_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_8_aib2_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_8_aib3_rx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_8_aib3_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_8_rx_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_9_aib1_tx_st_clk_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_9_aib2_rx_st_clk_hz == 36'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_9_aib2_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_9_aib3_rx_st_clk_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_9_aib3_tx_st_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_e400g_us_9_rx_clk_hz == 36'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_0_pld_clk_2x_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_0_pld_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_10_pld_clk_2x_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_10_pld_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_11_pld_clk_2x_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_11_pld_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_12_pld_clk_2x_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_12_pld_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_13_pld_clk_2x_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_13_pld_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_14_pld_clk_2x_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_14_pld_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_15_pld_clk_2x_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_15_pld_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_16_pld_clk_2x_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_16_pld_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_17_pld_clk_2x_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_17_pld_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_18_pld_clk_2x_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_18_pld_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_19_pld_clk_2x_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_19_pld_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_1_pld_clk_2x_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_1_pld_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_20_pld_clk_2x_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_20_pld_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_21_pld_clk_2x_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_21_pld_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_22_pld_clk_2x_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_22_pld_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_23_pld_clk_2x_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_23_pld_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_2_pld_clk_2x_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_2_pld_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_3_pld_clk_2x_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_3_pld_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_4_pld_clk_2x_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_4_pld_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_5_pld_clk_2x_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_5_pld_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_6_pld_clk_2x_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_6_pld_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_7_pld_clk_2x_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_7_pld_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_8_pld_clk_2x_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_8_pld_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_9_pld_clk_2x_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_aib_9_pld_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_0_tx_transfer_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_0_tx_transfer_div2_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_10_tx_transfer_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_10_tx_transfer_div2_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_11_tx_transfer_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_11_tx_transfer_div2_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_12_tx_transfer_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_12_tx_transfer_div2_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_13_tx_transfer_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_13_tx_transfer_div2_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_14_tx_transfer_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_14_tx_transfer_div2_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_15_tx_transfer_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_15_tx_transfer_div2_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_16_tx_transfer_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_16_tx_transfer_div2_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_17_tx_transfer_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_17_tx_transfer_div2_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_18_tx_transfer_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_18_tx_transfer_div2_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_19_tx_transfer_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_19_tx_transfer_div2_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_1_tx_transfer_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_1_tx_transfer_div2_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_20_tx_transfer_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_20_tx_transfer_div2_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_21_tx_transfer_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_21_tx_transfer_div2_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_22_tx_transfer_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_22_tx_transfer_div2_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_23_tx_transfer_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_23_tx_transfer_div2_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_2_tx_transfer_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_2_tx_transfer_div2_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_3_tx_transfer_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_3_tx_transfer_div2_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_4_tx_transfer_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_4_tx_transfer_div2_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_5_tx_transfer_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_5_tx_transfer_div2_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_6_tx_transfer_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_6_tx_transfer_div2_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_7_tx_transfer_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_7_tx_transfer_div2_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_8_tx_transfer_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_8_tx_transfer_div2_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_9_tx_transfer_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_iaib_pcie_ip_9_tx_transfer_div2_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_ictrl_dfd_e200_hub_0_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_ictrl_dfd_e200_hub_1_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_ictrl_dfd_e200_hub_2_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_ictrl_dfd_e200_hub_3_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_ictrl_dfd_e400_hub_0_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_ictrl_dfd_e400_hub_1_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_ictrl_dfd_e400_hub_2_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_ictrl_dfd_e400_hub_3_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_ictrl_dfd_pcie_hub_0_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_ictrl_dfd_pcie_hub_1_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_ictrl_dfd_pcie_hub_2_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_ictrl_dfd_pcie_hub_3_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_ipcie_cvp_ep_avmm_clk_in_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.powermode_freq_hz_i_pcie_cvp_issm_avmm_clk_out_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_aib_rc.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.io_dfx_cfg_idrvctrl == DFX_PAD_CFG_DRIVE_STRENGTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.io_dfx_cfg_ilowpowermode == DFX_PAD_CFG_NORMAL_POWER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.io_dfx_cfg_ioden == DFX_PAD_CFG_NORMAL_DRAIN_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.io_dfx_cfg_ipupdconfig == DFX_PAD_CFG_PUPD_DISABLED_1_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.io_pinperst_cfg_idrvctrl == PINPERST_PAD_CFG_DRIVE_STRENGTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.io_pinperst_cfg_ilowpowermode == PINPERST_PAD_CFG_NORMAL_POWER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.io_pinperst_cfg_ioden == PINPERST_PAD_CFG_NORMAL_DRAIN_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.io_pinperst_cfg_ipupdconfig == PINPERST_PAD_CFG_PUPD_DISABLED_1_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.io_pinperst_cfg_irxen == PINPERST_PAD_CFG_RX_ENABLE_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.io_pinperst_cfg_itxen == PINPERST_PAD_CFG_TX_ENABLE_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.io_refclk_cfg_idrvctrl == REFCLK_PAD_CFG_DRIVE_STRENGTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.io_refclk_cfg_ilowpowermode == REFCLK_PAD_CFG_NORMAL_POWER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.io_refclk_cfg_ioden == REFCLK_PAD_CFG_NORMAL_DRAIN_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.io_refclk_cfg_ipupdconfig == REFCLK_PAD_CFG_PUPD_DISABLED_1_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.io_refclk_cfg_irxen == REFCLK_PAD_CFG_RX_ENABLE_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.io_refclk_cfg_itxen == REFCLK_PAD_CFG_TX_ENABLE_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_ctrl_dfd_barak_rc_hub_clk == OFF_CTRL_DFD_BARAK_RC_HUB_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_ctrl_dfd_ux_rc_hub_0_clk == OFF_CTRL_DFD_UX_RC_HUB_0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_ctrl_dfd_ux_rc_hub_1_clk == OFF_CTRL_DFD_UX_RC_HUB_1_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_ctrl_dfd_ux_rc_hub_2_clk == OFF_CTRL_DFD_UX_RC_HUB_2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_ctrl_dfd_ux_rc_hub_3_clk == OFF_CTRL_DFD_UX_RC_HUB_3_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_ctrl_dft_ibarak_ip_brk_aon_sys_clk == OFF_CTRL_DFT_IBARAK_IP_BRK_AON_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_ctrl_dft_ibarak_ip_brk_bti_clk == OFF_CTRL_DFT_IBARAK_IP_BRK_BTI_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_ctrl_dft_ibarak_ip_dfx_clk == OFF_CTRL_DFT_IBARAK_IP_DFX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_ctrl_dft_iux_ip_0_dfx_clk == OFF_CTRL_DFT_IUX_IP_0_DFX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_ctrl_dft_iux_ip_1_dfx_clk == OFF_CTRL_DFT_IUX_IP_1_DFX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_ctrl_dft_iux_ip_2_dfx_clk == OFF_CTRL_DFT_IUX_IP_2_DFX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_ctrl_dft_iux_ip_3_dfx_clk == OFF_CTRL_DFT_IUX_IP_3_DFX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_ctrl_idvp_iopads_ip_idvfreqa_clk == OFF_CTRL_IDVP_IOPADS_IP_IDVFREQA_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_ctrl_idvp_iopads_ip_idvfreqb_clk == OFF_CTRL_IDVP_IOPADS_IP_IDVFREQB_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_ctrl_idvp_iopads_ip_idvtclk == OFF_CTRL_IDVP_IOPADS_IP_IDVTCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_ctrl_iopads_us_bs_clock_dr_clk == OFF_CTRL_IOPADS_US_BS_CLOCK_DR_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_ctrl_iopads_us_bs_update_dr_clk == OFF_CTRL_IOPADS_US_BS_UPDATE_DR_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_ctrl_iopads_us_jtag_ctrl == OFF_CTRL_IOPADS_US_JTAG_CTRL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_ctrl_pll_iopads_ip_pll_0_slice0_clk == PWR_CTRL_PLL_IOPADS_IP_PLL_0_SLICE0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_ctrl_pll_iopads_ip_pll_0_slice1_clk == PWR_CTRL_PLL_IOPADS_IP_PLL_0_SLICE1_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_ctrl_pll_iopads_ip_pll_0_slice2_clk == PWR_CTRL_PLL_IOPADS_IP_PLL_0_SLICE2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_ctrl_pll_iopads_ip_pll_0_slice3_clk == OFF_CTRL_PLL_IOPADS_IP_PLL_0_SLICE3_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_ctrl_pll_iopads_ip_pll_1_slice0_clk == PWR_CTRL_PLL_IOPADS_IP_PLL_1_SLICE0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_ctrl_pll_iopads_ip_pll_1_slice1_clk == PWR_CTRL_PLL_IOPADS_IP_PLL_1_SLICE1_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_ctrl_pll_iopads_ip_pll_1_slice2_clk == PWR_CTRL_PLL_IOPADS_IP_PLL_1_SLICE2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_ctrl_pll_iopads_ip_pll_1_slice3_clk == OFF_CTRL_PLL_IOPADS_IP_PLL_1_SLICE3_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_ctrl_pll_iopads_ip_pll_2_slice0_clk == PWR_CTRL_PLL_IOPADS_IP_PLL_2_SLICE0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_ctrl_pll_iopads_ip_pll_2_slice1_clk == PWR_CTRL_PLL_IOPADS_IP_PLL_2_SLICE1_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_ctrl_pll_iopads_ip_pll_2_slice2_clk == PWR_CTRL_PLL_IOPADS_IP_PLL_2_SLICE2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_ctrl_pll_iopads_ip_pll_2_slice3_clk == PWR_CTRL_PLL_IOPADS_IP_PLL_2_SLICE3_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_global_avmm_ctrl_ibarak_slv_clk == PWR_GLOBAL_AVMM_CTRL_IBARAK_SLV_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_global_avmm_ctrl_iux_slv_0_clk == PWR_GLOBAL_AVMM_CTRL_IUX_SLV_0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_global_avmm_ctrl_iux_slv_1_clk == PWR_GLOBAL_AVMM_CTRL_IUX_SLV_1_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_global_avmm_ctrl_iux_slv_2_clk == PWR_GLOBAL_AVMM_CTRL_IUX_SLV_2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_global_avmm_ctrl_iux_slv_3_clk == PWR_GLOBAL_AVMM_CTRL_IUX_SLV_3_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_ictrl_dft_ux_tcb_0_ref_clk == OFF_ICTRL_DFT_UX_TCB_0_REF_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_ictrl_dft_ux_tcb_1_ref_clk == OFF_ICTRL_DFT_UX_TCB_1_REF_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_ictrl_dft_ux_tcb_2_ref_clk == OFF_ICTRL_DFT_UX_TCB_2_REF_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_ictrl_dft_ux_tcb_3_ref_clk == OFF_ICTRL_DFT_UX_TCB_3_REF_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_xcvrrc_idvp2_iopads_ip_idvfreqa_clk == OFF_XCVRRC_IDVP2_IOPADS_IP_IDVFREQA_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_xcvrrc_idvp2_iopads_ip_idvfreqb_clk == OFF_XCVRRC_IDVP2_IOPADS_IP_IDVFREQB_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_xcvrrc_idvp2_iopads_ip_idvtclk == OFF_XCVRRC_IDVP2_IOPADS_IP_IDVTCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_xcvrrc_uxpll_iopads_slv_0_clk0 == PWR_XCVRRC_UXPLL_IOPADS_SLV_0_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_xcvrrc_uxpll_iopads_slv_0_clk1 == OFF_XCVRRC_UXPLL_IOPADS_SLV_0_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_xcvrrc_uxpll_iopads_slv_1_clk0 == PWR_XCVRRC_UXPLL_IOPADS_SLV_1_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_xcvrrc_uxpll_iopads_slv_1_clk1 == PWR_XCVRRC_UXPLL_IOPADS_SLV_1_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_xcvrrc_uxpll_iopads_slv_2_clk0 == PWR_XCVRRC_UXPLL_IOPADS_SLV_2_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_xcvrrc_uxpll_iopads_slv_2_clk1 == OFF_XCVRRC_UXPLL_IOPADS_SLV_2_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_xcvrrc_uxpll_iopads_slv_3_clk0 == OFF_XCVRRC_UXPLL_IOPADS_SLV_3_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_ac_xcvrrc_uxpll_iopads_slv_3_clk1 == OFF_XCVRRC_UXPLL_IOPADS_SLV_3_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_ctrl_dfd_barak_rc_hub_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_ctrl_dfd_ux_rc_hub_0_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_ctrl_dfd_ux_rc_hub_1_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_ctrl_dfd_ux_rc_hub_2_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_ctrl_dfd_ux_rc_hub_3_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_ctrl_dft_ibarak_ip_brk_aon_sys_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_ctrl_dft_ibarak_ip_brk_bti_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_ctrl_dft_ibarak_ip_dfx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_ctrl_dft_iux_ip_0_dfx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_ctrl_dft_iux_ip_1_dfx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_ctrl_dft_iux_ip_2_dfx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_ctrl_dft_iux_ip_3_dfx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_ctrl_idvp_iopads_ip_idvfreqa_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_ctrl_idvp_iopads_ip_idvfreqb_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_ctrl_idvp_iopads_ip_idvtclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_ctrl_iopads_us_bs_clock_dr_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_ctrl_iopads_us_bs_update_dr_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_ctrl_iopads_us_jtag_ctrl_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_ctrl_pll_iopads_ip_pll_0_slice0_clk_hz == 36'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_ctrl_pll_iopads_ip_pll_0_slice1_clk_hz == 36'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_ctrl_pll_iopads_ip_pll_0_slice2_clk_hz == 36'd250000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_ctrl_pll_iopads_ip_pll_0_slice3_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_ctrl_pll_iopads_ip_pll_1_slice0_clk_hz == 36'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_ctrl_pll_iopads_ip_pll_1_slice1_clk_hz == 36'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_ctrl_pll_iopads_ip_pll_1_slice2_clk_hz == 36'd250000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_ctrl_pll_iopads_ip_pll_1_slice3_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_ctrl_pll_iopads_ip_pll_2_slice0_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_ctrl_pll_iopads_ip_pll_2_slice1_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_ctrl_pll_iopads_ip_pll_2_slice2_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_ctrl_pll_iopads_ip_pll_2_slice3_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_global_avmm_ctrl_ibarak_slv_clk_hz == 36'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_global_avmm_ctrl_iux_slv_0_clk_hz == 36'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_global_avmm_ctrl_iux_slv_1_clk_hz == 36'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_global_avmm_ctrl_iux_slv_2_clk_hz == 36'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_global_avmm_ctrl_iux_slv_3_clk_hz == 36'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_ictrl_dft_ux_tcb_0_ref_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_ictrl_dft_ux_tcb_1_ref_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_ictrl_dft_ux_tcb_2_ref_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_ictrl_dft_ux_tcb_3_ref_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_xcvrrc_idvp2_iopads_ip_idvfreqa_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_xcvrrc_idvp2_iopads_ip_idvfreqb_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_xcvrrc_idvp2_iopads_ip_idvtclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_xcvrrc_uxpll_iopads_slv_0_clk0_hz == 36'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_xcvrrc_uxpll_iopads_slv_0_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_xcvrrc_uxpll_iopads_slv_1_clk0_hz == 36'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_xcvrrc_uxpll_iopads_slv_1_clk1_hz == 36'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_xcvrrc_uxpll_iopads_slv_2_clk0_hz == 36'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_xcvrrc_uxpll_iopads_slv_2_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_xcvrrc_uxpll_iopads_slv_3_clk0_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.powermode_freq_hz_i_xcvrrc_uxpll_iopads_slv_3_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_iopads.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_barak_idvp2_xcvrrc_ip_idvfreqa_clk == OFF_BARAK_IDVP2_XCVRRC_IP_IDVFREQA_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_barak_idvp2_xcvrrc_ip_idvfreqb_clk == OFF_BARAK_IDVP2_XCVRRC_IP_IDVFREQB_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_barak_idvp2_xcvrrc_ip_idvtclk == OFF_BARAK_IDVP2_XCVRRC_IP_IDVTCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ctrl_dft_ux_rc_tcb_0_ref_clk == OFF_CTRL_DFT_UX_RC_TCB_0_REF_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ctrl_dft_ux_rc_tcb_1_ref_clk == OFF_CTRL_DFT_UX_RC_TCB_1_REF_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ctrl_dft_ux_rc_tcb_2_ref_clk == OFF_CTRL_DFT_UX_RC_TCB_2_REF_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ctrl_dft_ux_rc_tcb_3_ref_clk == OFF_CTRL_DFT_UX_RC_TCB_3_REF_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_e200g_clkrst_xcvrrc_ds_0_sclk == OFF_E200G_CLKRST_XCVRRC_DS_0_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_e200g_clkrst_xcvrrc_ds_1_sclk == OFF_E200G_CLKRST_XCVRRC_DS_1_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_e200g_clkrst_xcvrrc_ds_2_sclk == OFF_E200G_CLKRST_XCVRRC_DS_2_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_e200g_clkrst_xcvrrc_ds_3_sclk == OFF_E200G_CLKRST_XCVRRC_DS_3_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_e400g_clkrst_xcvrrc_ds_0_sclk == OFF_E400G_CLKRST_XCVRRC_DS_0_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_e400g_clkrst_xcvrrc_ds_10_sclk == OFF_E400G_CLKRST_XCVRRC_DS_10_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_e400g_clkrst_xcvrrc_ds_11_sclk == OFF_E400G_CLKRST_XCVRRC_DS_11_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_e400g_clkrst_xcvrrc_ds_1_sclk == OFF_E400G_CLKRST_XCVRRC_DS_1_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_e400g_clkrst_xcvrrc_ds_2_sclk == OFF_E400G_CLKRST_XCVRRC_DS_2_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_e400g_clkrst_xcvrrc_ds_3_sclk == OFF_E400G_CLKRST_XCVRRC_DS_3_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_e400g_clkrst_xcvrrc_ds_4_sclk == OFF_E400G_CLKRST_XCVRRC_DS_4_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_e400g_clkrst_xcvrrc_ds_5_sclk == OFF_E400G_CLKRST_XCVRRC_DS_5_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_e400g_clkrst_xcvrrc_ds_6_sclk == OFF_E400G_CLKRST_XCVRRC_DS_6_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_e400g_clkrst_xcvrrc_ds_7_sclk == OFF_E400G_CLKRST_XCVRRC_DS_7_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_e400g_clkrst_xcvrrc_ds_8_sclk == OFF_E400G_CLKRST_XCVRRC_DS_8_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_e400g_clkrst_xcvrrc_ds_9_sclk == OFF_E400G_CLKRST_XCVRRC_DS_9_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_e200g_iux_ds_0_ux_tx_clk_ds == OFF_GDR_E200G_IUX_DS_0_UX_TX_CLK_DS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_e200g_iux_ds_1_ux_tx_clk_ds == OFF_GDR_E200G_IUX_DS_1_UX_TX_CLK_DS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_e200g_iux_ds_2_ux_tx_clk_ds == OFF_GDR_E200G_IUX_DS_2_UX_TX_CLK_DS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_e200g_iux_ds_3_ux_tx_clk_ds == OFF_GDR_E200G_IUX_DS_3_UX_TX_CLK_DS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_e200g_iux_ds_4_ux_tx_clk_ds == OFF_GDR_E200G_IUX_DS_4_UX_TX_CLK_DS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_e200g_iux_ds_5_ux_tx_clk_ds == OFF_GDR_E200G_IUX_DS_5_UX_TX_CLK_DS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_e200g_iux_ds_6_ux_tx_clk_ds == OFF_GDR_E200G_IUX_DS_6_UX_TX_CLK_DS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_e200g_iux_ds_7_ux_tx_clk_ds == OFF_GDR_E200G_IUX_DS_7_UX_TX_CLK_DS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_e400g_ibarak_ds_0_brk_pcs_srds_tx_clki_lanex == OFF_GDR_E400G_IBARAK_DS_0_BRK_PCS_SRDS_TX_CLKI_LANEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_e400g_ibarak_ds_1_brk_pcs_srds_tx_clki_lanex == OFF_GDR_E400G_IBARAK_DS_1_BRK_PCS_SRDS_TX_CLKI_LANEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_e400g_ibarak_ds_2_brk_pcs_srds_tx_clki_lanex == OFF_GDR_E400G_IBARAK_DS_2_BRK_PCS_SRDS_TX_CLKI_LANEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_e400g_ibarak_ds_3_brk_pcs_srds_tx_clki_lanex == OFF_GDR_E400G_IBARAK_DS_3_BRK_PCS_SRDS_TX_CLKI_LANEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_e400g_iux_ds_0_ux_tx_clk_ds == PWR_GDR_E400G_IUX_DS_0_UX_TX_CLK_DS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_e400g_iux_ds_10_ux_tx_clk_ds == OFF_GDR_E400G_IUX_DS_10_UX_TX_CLK_DS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_e400g_iux_ds_11_ux_tx_clk_ds == OFF_GDR_E400G_IUX_DS_11_UX_TX_CLK_DS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_e400g_iux_ds_12_ux_tx_clk_ds == OFF_GDR_E400G_IUX_DS_12_UX_TX_CLK_DS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_e400g_iux_ds_13_ux_tx_clk_ds == OFF_GDR_E400G_IUX_DS_13_UX_TX_CLK_DS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_e400g_iux_ds_14_ux_tx_clk_ds == OFF_GDR_E400G_IUX_DS_14_UX_TX_CLK_DS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_e400g_iux_ds_15_ux_tx_clk_ds == OFF_GDR_E400G_IUX_DS_15_UX_TX_CLK_DS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_e400g_iux_ds_1_ux_tx_clk_ds == OFF_GDR_E400G_IUX_DS_1_UX_TX_CLK_DS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_e400g_iux_ds_2_ux_tx_clk_ds == PWR_GDR_E400G_IUX_DS_2_UX_TX_CLK_DS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_e400g_iux_ds_3_ux_tx_clk_ds == PWR_GDR_E400G_IUX_DS_3_UX_TX_CLK_DS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_e400g_iux_ds_4_ux_tx_clk_ds == OFF_GDR_E400G_IUX_DS_4_UX_TX_CLK_DS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_e400g_iux_ds_5_ux_tx_clk_ds == PWR_GDR_E400G_IUX_DS_5_UX_TX_CLK_DS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_e400g_iux_ds_6_ux_tx_clk_ds == OFF_GDR_E400G_IUX_DS_6_UX_TX_CLK_DS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_e400g_iux_ds_7_ux_tx_clk_ds == OFF_GDR_E400G_IUX_DS_7_UX_TX_CLK_DS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_e400g_iux_ds_8_ux_tx_clk_ds == OFF_GDR_E400G_IUX_DS_8_UX_TX_CLK_DS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_e400g_iux_ds_9_ux_tx_clk_ds == OFF_GDR_E400G_IUX_DS_9_UX_TX_CLK_DS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_0_ux_clk == OFF_GDR_IE200G_UX_US_0_UX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_0_ux_rx_clk == PWR_GDR_IE200G_UX_US_0_UX_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_0_ux_rx_user_clk == PWR_GDR_IE200G_UX_US_0_UX_RX_USER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_0_ux_tx_clk == PWR_GDR_IE200G_UX_US_0_UX_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_0_ux_tx_user_clk_1 == PWR_GDR_IE200G_UX_US_0_UX_TX_USER_CLK_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_0_ux_tx_user_clk_2 == OFF_GDR_IE200G_UX_US_0_UX_TX_USER_CLK_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_10_ux_clk == OFF_GDR_IE200G_UX_US_10_UX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_10_ux_rx_clk == OFF_GDR_IE200G_UX_US_10_UX_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_10_ux_rx_user_clk == OFF_GDR_IE200G_UX_US_10_UX_RX_USER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_10_ux_tx_clk == OFF_GDR_IE200G_UX_US_10_UX_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_10_ux_tx_user_clk_1 == OFF_GDR_IE200G_UX_US_10_UX_TX_USER_CLK_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_10_ux_tx_user_clk_2 == OFF_GDR_IE200G_UX_US_10_UX_TX_USER_CLK_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_11_ux_clk == OFF_GDR_IE200G_UX_US_11_UX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_11_ux_rx_clk == OFF_GDR_IE200G_UX_US_11_UX_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_11_ux_rx_user_clk == OFF_GDR_IE200G_UX_US_11_UX_RX_USER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_11_ux_tx_clk == OFF_GDR_IE200G_UX_US_11_UX_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_11_ux_tx_user_clk_1 == OFF_GDR_IE200G_UX_US_11_UX_TX_USER_CLK_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_11_ux_tx_user_clk_2 == OFF_GDR_IE200G_UX_US_11_UX_TX_USER_CLK_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_12_ux_clk == OFF_GDR_IE200G_UX_US_12_UX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_12_ux_rx_clk == OFF_GDR_IE200G_UX_US_12_UX_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_12_ux_rx_user_clk == OFF_GDR_IE200G_UX_US_12_UX_RX_USER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_12_ux_tx_clk == OFF_GDR_IE200G_UX_US_12_UX_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_12_ux_tx_user_clk_1 == OFF_GDR_IE200G_UX_US_12_UX_TX_USER_CLK_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_12_ux_tx_user_clk_2 == OFF_GDR_IE200G_UX_US_12_UX_TX_USER_CLK_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_13_ux_clk == OFF_GDR_IE200G_UX_US_13_UX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_13_ux_rx_clk == OFF_GDR_IE200G_UX_US_13_UX_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_13_ux_rx_user_clk == OFF_GDR_IE200G_UX_US_13_UX_RX_USER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_13_ux_tx_clk == OFF_GDR_IE200G_UX_US_13_UX_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_13_ux_tx_user_clk_1 == OFF_GDR_IE200G_UX_US_13_UX_TX_USER_CLK_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_13_ux_tx_user_clk_2 == OFF_GDR_IE200G_UX_US_13_UX_TX_USER_CLK_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_14_ux_clk == OFF_GDR_IE200G_UX_US_14_UX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_14_ux_rx_clk == OFF_GDR_IE200G_UX_US_14_UX_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_14_ux_rx_user_clk == OFF_GDR_IE200G_UX_US_14_UX_RX_USER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_14_ux_tx_clk == OFF_GDR_IE200G_UX_US_14_UX_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_14_ux_tx_user_clk_1 == OFF_GDR_IE200G_UX_US_14_UX_TX_USER_CLK_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_14_ux_tx_user_clk_2 == OFF_GDR_IE200G_UX_US_14_UX_TX_USER_CLK_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_15_ux_clk == OFF_GDR_IE200G_UX_US_15_UX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_15_ux_rx_clk == OFF_GDR_IE200G_UX_US_15_UX_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_15_ux_rx_user_clk == OFF_GDR_IE200G_UX_US_15_UX_RX_USER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_15_ux_tx_clk == OFF_GDR_IE200G_UX_US_15_UX_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_15_ux_tx_user_clk_1 == OFF_GDR_IE200G_UX_US_15_UX_TX_USER_CLK_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_15_ux_tx_user_clk_2 == OFF_GDR_IE200G_UX_US_15_UX_TX_USER_CLK_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_1_ux_clk == OFF_GDR_IE200G_UX_US_1_UX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_1_ux_rx_clk == PWR_GDR_IE200G_UX_US_1_UX_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_1_ux_rx_user_clk == OFF_GDR_IE200G_UX_US_1_UX_RX_USER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_1_ux_tx_clk == PWR_GDR_IE200G_UX_US_1_UX_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_1_ux_tx_user_clk_1 == OFF_GDR_IE200G_UX_US_1_UX_TX_USER_CLK_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_1_ux_tx_user_clk_2 == OFF_GDR_IE200G_UX_US_1_UX_TX_USER_CLK_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_2_ux_clk == OFF_GDR_IE200G_UX_US_2_UX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_2_ux_rx_clk == OFF_GDR_IE200G_UX_US_2_UX_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_2_ux_rx_user_clk == PWR_GDR_IE200G_UX_US_2_UX_RX_USER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_2_ux_tx_clk == PWR_GDR_IE200G_UX_US_2_UX_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_2_ux_tx_user_clk_1 == PWR_GDR_IE200G_UX_US_2_UX_TX_USER_CLK_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_2_ux_tx_user_clk_2 == OFF_GDR_IE200G_UX_US_2_UX_TX_USER_CLK_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_3_ux_clk == OFF_GDR_IE200G_UX_US_3_UX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_3_ux_rx_clk == PWR_GDR_IE200G_UX_US_3_UX_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_3_ux_rx_user_clk == PWR_GDR_IE200G_UX_US_3_UX_RX_USER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_3_ux_tx_clk == PWR_GDR_IE200G_UX_US_3_UX_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_3_ux_tx_user_clk_1 == PWR_GDR_IE200G_UX_US_3_UX_TX_USER_CLK_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_3_ux_tx_user_clk_2 == OFF_GDR_IE200G_UX_US_3_UX_TX_USER_CLK_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_4_ux_clk == OFF_GDR_IE200G_UX_US_4_UX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_4_ux_rx_clk == PWR_GDR_IE200G_UX_US_4_UX_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_4_ux_rx_user_clk == OFF_GDR_IE200G_UX_US_4_UX_RX_USER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_4_ux_tx_clk == PWR_GDR_IE200G_UX_US_4_UX_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_4_ux_tx_user_clk_1 == OFF_GDR_IE200G_UX_US_4_UX_TX_USER_CLK_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_4_ux_tx_user_clk_2 == OFF_GDR_IE200G_UX_US_4_UX_TX_USER_CLK_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_5_ux_clk == OFF_GDR_IE200G_UX_US_5_UX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_5_ux_rx_clk == OFF_GDR_IE200G_UX_US_5_UX_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_5_ux_rx_user_clk == PWR_GDR_IE200G_UX_US_5_UX_RX_USER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_5_ux_tx_clk == PWR_GDR_IE200G_UX_US_5_UX_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_5_ux_tx_user_clk_1 == PWR_GDR_IE200G_UX_US_5_UX_TX_USER_CLK_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_5_ux_tx_user_clk_2 == OFF_GDR_IE200G_UX_US_5_UX_TX_USER_CLK_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_6_ux_clk == OFF_GDR_IE200G_UX_US_6_UX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_6_ux_rx_clk == PWR_GDR_IE200G_UX_US_6_UX_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_6_ux_rx_user_clk == PWR_GDR_IE200G_UX_US_6_UX_RX_USER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_6_ux_tx_clk == OFF_GDR_IE200G_UX_US_6_UX_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_6_ux_tx_user_clk_1 == OFF_GDR_IE200G_UX_US_6_UX_TX_USER_CLK_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_6_ux_tx_user_clk_2 == OFF_GDR_IE200G_UX_US_6_UX_TX_USER_CLK_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_7_ux_clk == OFF_GDR_IE200G_UX_US_7_UX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_7_ux_rx_clk == PWR_GDR_IE200G_UX_US_7_UX_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_7_ux_rx_user_clk == OFF_GDR_IE200G_UX_US_7_UX_RX_USER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_7_ux_tx_clk == PWR_GDR_IE200G_UX_US_7_UX_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_7_ux_tx_user_clk_1 == OFF_GDR_IE200G_UX_US_7_UX_TX_USER_CLK_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_7_ux_tx_user_clk_2 == OFF_GDR_IE200G_UX_US_7_UX_TX_USER_CLK_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_8_ux_clk == OFF_GDR_IE200G_UX_US_8_UX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_8_ux_rx_clk == OFF_GDR_IE200G_UX_US_8_UX_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_8_ux_rx_user_clk == OFF_GDR_IE200G_UX_US_8_UX_RX_USER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_8_ux_tx_clk == OFF_GDR_IE200G_UX_US_8_UX_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_8_ux_tx_user_clk_1 == OFF_GDR_IE200G_UX_US_8_UX_TX_USER_CLK_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_8_ux_tx_user_clk_2 == OFF_GDR_IE200G_UX_US_8_UX_TX_USER_CLK_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_9_ux_clk == OFF_GDR_IE200G_UX_US_9_UX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_9_ux_rx_clk == OFF_GDR_IE200G_UX_US_9_UX_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_9_ux_rx_user_clk == OFF_GDR_IE200G_UX_US_9_UX_RX_USER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_9_ux_tx_clk == OFF_GDR_IE200G_UX_US_9_UX_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_9_ux_tx_user_clk_1 == OFF_GDR_IE200G_UX_US_9_UX_TX_USER_CLK_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie200g_ux_us_9_ux_tx_user_clk_2 == OFF_GDR_IE200G_UX_US_9_UX_TX_USER_CLK_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_barak_us_0_brk_pcs_srds_rx_clk_lanex == PWR_GDR_IE400G_BARAK_US_0_BRK_PCS_SRDS_RX_CLK_LANEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_barak_us_0_brk_pcs_srds_rx_usr_clk1_lanex == OFF_GDR_IE400G_BARAK_US_0_BRK_PCS_SRDS_RX_USR_CLK1_LANEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_barak_us_0_brk_pcs_srds_rx_usr_clk2_lanex == OFF_GDR_IE400G_BARAK_US_0_BRK_PCS_SRDS_RX_USR_CLK2_LANEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_barak_us_0_brk_pcs_srds_tx_clko_lanex == PWR_GDR_IE400G_BARAK_US_0_BRK_PCS_SRDS_TX_CLKO_LANEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_barak_us_0_brk_pcs_srds_tx_usr_clk1_lanex == OFF_GDR_IE400G_BARAK_US_0_BRK_PCS_SRDS_TX_USR_CLK1_LANEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_barak_us_0_brk_pcs_srds_tx_usr_clk2_lanex == OFF_GDR_IE400G_BARAK_US_0_BRK_PCS_SRDS_TX_USR_CLK2_LANEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_barak_us_1_brk_pcs_srds_rx_clk_lanex == PWR_GDR_IE400G_BARAK_US_1_BRK_PCS_SRDS_RX_CLK_LANEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_barak_us_1_brk_pcs_srds_rx_usr_clk1_lanex == OFF_GDR_IE400G_BARAK_US_1_BRK_PCS_SRDS_RX_USR_CLK1_LANEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_barak_us_1_brk_pcs_srds_rx_usr_clk2_lanex == OFF_GDR_IE400G_BARAK_US_1_BRK_PCS_SRDS_RX_USR_CLK2_LANEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_barak_us_1_brk_pcs_srds_tx_clko_lanex == PWR_GDR_IE400G_BARAK_US_1_BRK_PCS_SRDS_TX_CLKO_LANEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_barak_us_1_brk_pcs_srds_tx_usr_clk1_lanex == OFF_GDR_IE400G_BARAK_US_1_BRK_PCS_SRDS_TX_USR_CLK1_LANEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_barak_us_1_brk_pcs_srds_tx_usr_clk2_lanex == OFF_GDR_IE400G_BARAK_US_1_BRK_PCS_SRDS_TX_USR_CLK2_LANEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_barak_us_2_brk_pcs_srds_rx_clk_lanex == PWR_GDR_IE400G_BARAK_US_2_BRK_PCS_SRDS_RX_CLK_LANEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_barak_us_2_brk_pcs_srds_rx_usr_clk1_lanex == OFF_GDR_IE400G_BARAK_US_2_BRK_PCS_SRDS_RX_USR_CLK1_LANEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_barak_us_2_brk_pcs_srds_rx_usr_clk2_lanex == OFF_GDR_IE400G_BARAK_US_2_BRK_PCS_SRDS_RX_USR_CLK2_LANEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_barak_us_2_brk_pcs_srds_tx_clko_lanex == PWR_GDR_IE400G_BARAK_US_2_BRK_PCS_SRDS_TX_CLKO_LANEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_barak_us_2_brk_pcs_srds_tx_usr_clk1_lanex == OFF_GDR_IE400G_BARAK_US_2_BRK_PCS_SRDS_TX_USR_CLK1_LANEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_barak_us_2_brk_pcs_srds_tx_usr_clk2_lanex == OFF_GDR_IE400G_BARAK_US_2_BRK_PCS_SRDS_TX_USR_CLK2_LANEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_barak_us_3_brk_pcs_srds_rx_clk_lanex == PWR_GDR_IE400G_BARAK_US_3_BRK_PCS_SRDS_RX_CLK_LANEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_barak_us_3_brk_pcs_srds_rx_usr_clk1_lanex == OFF_GDR_IE400G_BARAK_US_3_BRK_PCS_SRDS_RX_USR_CLK1_LANEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_barak_us_3_brk_pcs_srds_rx_usr_clk2_lanex == OFF_GDR_IE400G_BARAK_US_3_BRK_PCS_SRDS_RX_USR_CLK2_LANEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_barak_us_3_brk_pcs_srds_tx_clko_lanex == PWR_GDR_IE400G_BARAK_US_3_BRK_PCS_SRDS_TX_CLKO_LANEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_barak_us_3_brk_pcs_srds_tx_usr_clk1_lanex == OFF_GDR_IE400G_BARAK_US_3_BRK_PCS_SRDS_TX_USR_CLK1_LANEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_barak_us_3_brk_pcs_srds_tx_usr_clk2_lanex == OFF_GDR_IE400G_BARAK_US_3_BRK_PCS_SRDS_TX_USR_CLK2_LANEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_0_ux_clk == OFF_GDR_IE400G_UX_US_0_UX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_0_ux_rx_clk == PWR_GDR_IE400G_UX_US_0_UX_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_0_ux_rx_user_clk == PWR_GDR_IE400G_UX_US_0_UX_RX_USER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_0_ux_tx_clk == PWR_GDR_IE400G_UX_US_0_UX_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_0_ux_tx_user_clk_1 == PWR_GDR_IE400G_UX_US_0_UX_TX_USER_CLK_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_0_ux_tx_user_clk_2 == OFF_GDR_IE400G_UX_US_0_UX_TX_USER_CLK_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_10_ux_clk == OFF_GDR_IE400G_UX_US_10_UX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_10_ux_rx_clk == PWR_GDR_IE400G_UX_US_10_UX_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_10_ux_rx_user_clk == OFF_GDR_IE400G_UX_US_10_UX_RX_USER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_10_ux_tx_clk == PWR_GDR_IE400G_UX_US_10_UX_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_10_ux_tx_user_clk_1 == OFF_GDR_IE400G_UX_US_10_UX_TX_USER_CLK_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_10_ux_tx_user_clk_2 == OFF_GDR_IE400G_UX_US_10_UX_TX_USER_CLK_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_11_ux_clk == OFF_GDR_IE400G_UX_US_11_UX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_11_ux_rx_clk == PWR_GDR_IE400G_UX_US_11_UX_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_11_ux_rx_user_clk == OFF_GDR_IE400G_UX_US_11_UX_RX_USER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_11_ux_tx_clk == PWR_GDR_IE400G_UX_US_11_UX_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_11_ux_tx_user_clk_1 == OFF_GDR_IE400G_UX_US_11_UX_TX_USER_CLK_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_11_ux_tx_user_clk_2 == OFF_GDR_IE400G_UX_US_11_UX_TX_USER_CLK_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_12_ux_clk == OFF_GDR_IE400G_UX_US_12_UX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_12_ux_rx_clk == PWR_GDR_IE400G_UX_US_12_UX_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_12_ux_rx_user_clk == OFF_GDR_IE400G_UX_US_12_UX_RX_USER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_12_ux_tx_clk == PWR_GDR_IE400G_UX_US_12_UX_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_12_ux_tx_user_clk_1 == OFF_GDR_IE400G_UX_US_12_UX_TX_USER_CLK_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_12_ux_tx_user_clk_2 == OFF_GDR_IE400G_UX_US_12_UX_TX_USER_CLK_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_13_ux_clk == OFF_GDR_IE400G_UX_US_13_UX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_13_ux_rx_clk == PWR_GDR_IE400G_UX_US_13_UX_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_13_ux_rx_user_clk == OFF_GDR_IE400G_UX_US_13_UX_RX_USER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_13_ux_tx_clk == PWR_GDR_IE400G_UX_US_13_UX_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_13_ux_tx_user_clk_1 == OFF_GDR_IE400G_UX_US_13_UX_TX_USER_CLK_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_13_ux_tx_user_clk_2 == OFF_GDR_IE400G_UX_US_13_UX_TX_USER_CLK_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_14_ux_clk == OFF_GDR_IE400G_UX_US_14_UX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_14_ux_rx_clk == PWR_GDR_IE400G_UX_US_14_UX_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_14_ux_rx_user_clk == OFF_GDR_IE400G_UX_US_14_UX_RX_USER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_14_ux_tx_clk == PWR_GDR_IE400G_UX_US_14_UX_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_14_ux_tx_user_clk_1 == OFF_GDR_IE400G_UX_US_14_UX_TX_USER_CLK_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_14_ux_tx_user_clk_2 == OFF_GDR_IE400G_UX_US_14_UX_TX_USER_CLK_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_15_ux_clk == OFF_GDR_IE400G_UX_US_15_UX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_15_ux_rx_clk == PWR_GDR_IE400G_UX_US_15_UX_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_15_ux_rx_user_clk == OFF_GDR_IE400G_UX_US_15_UX_RX_USER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_15_ux_tx_clk == PWR_GDR_IE400G_UX_US_15_UX_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_15_ux_tx_user_clk_1 == OFF_GDR_IE400G_UX_US_15_UX_TX_USER_CLK_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_15_ux_tx_user_clk_2 == OFF_GDR_IE400G_UX_US_15_UX_TX_USER_CLK_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_1_ux_clk == OFF_GDR_IE400G_UX_US_1_UX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_1_ux_rx_clk == PWR_GDR_IE400G_UX_US_1_UX_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_1_ux_rx_user_clk == OFF_GDR_IE400G_UX_US_1_UX_RX_USER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_1_ux_tx_clk == PWR_GDR_IE400G_UX_US_1_UX_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_1_ux_tx_user_clk_1 == OFF_GDR_IE400G_UX_US_1_UX_TX_USER_CLK_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_1_ux_tx_user_clk_2 == OFF_GDR_IE400G_UX_US_1_UX_TX_USER_CLK_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_2_ux_clk == OFF_GDR_IE400G_UX_US_2_UX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_2_ux_rx_clk == OFF_GDR_IE400G_UX_US_2_UX_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_2_ux_rx_user_clk == OFF_GDR_IE400G_UX_US_2_UX_RX_USER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_2_ux_tx_clk == PWR_GDR_IE400G_UX_US_2_UX_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_2_ux_tx_user_clk_1 == PWR_GDR_IE400G_UX_US_2_UX_TX_USER_CLK_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_2_ux_tx_user_clk_2 == OFF_GDR_IE400G_UX_US_2_UX_TX_USER_CLK_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_3_ux_clk == OFF_GDR_IE400G_UX_US_3_UX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_3_ux_rx_clk == PWR_GDR_IE400G_UX_US_3_UX_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_3_ux_rx_user_clk == PWR_GDR_IE400G_UX_US_3_UX_RX_USER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_3_ux_tx_clk == PWR_GDR_IE400G_UX_US_3_UX_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_3_ux_tx_user_clk_1 == PWR_GDR_IE400G_UX_US_3_UX_TX_USER_CLK_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_3_ux_tx_user_clk_2 == OFF_GDR_IE400G_UX_US_3_UX_TX_USER_CLK_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_4_ux_clk == OFF_GDR_IE400G_UX_US_4_UX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_4_ux_rx_clk == PWR_GDR_IE400G_UX_US_4_UX_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_4_ux_rx_user_clk == OFF_GDR_IE400G_UX_US_4_UX_RX_USER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_4_ux_tx_clk == PWR_GDR_IE400G_UX_US_4_UX_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_4_ux_tx_user_clk_1 == OFF_GDR_IE400G_UX_US_4_UX_TX_USER_CLK_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_4_ux_tx_user_clk_2 == OFF_GDR_IE400G_UX_US_4_UX_TX_USER_CLK_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_5_ux_clk == OFF_GDR_IE400G_UX_US_5_UX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_5_ux_rx_clk == OFF_GDR_IE400G_UX_US_5_UX_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_5_ux_rx_user_clk == OFF_GDR_IE400G_UX_US_5_UX_RX_USER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_5_ux_tx_clk == PWR_GDR_IE400G_UX_US_5_UX_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_5_ux_tx_user_clk_1 == PWR_GDR_IE400G_UX_US_5_UX_TX_USER_CLK_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_5_ux_tx_user_clk_2 == OFF_GDR_IE400G_UX_US_5_UX_TX_USER_CLK_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_6_ux_clk == OFF_GDR_IE400G_UX_US_6_UX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_6_ux_rx_clk == PWR_GDR_IE400G_UX_US_6_UX_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_6_ux_rx_user_clk == PWR_GDR_IE400G_UX_US_6_UX_RX_USER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_6_ux_tx_clk == OFF_GDR_IE400G_UX_US_6_UX_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_6_ux_tx_user_clk_1 == OFF_GDR_IE400G_UX_US_6_UX_TX_USER_CLK_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_6_ux_tx_user_clk_2 == OFF_GDR_IE400G_UX_US_6_UX_TX_USER_CLK_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_7_ux_clk == OFF_GDR_IE400G_UX_US_7_UX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_7_ux_rx_clk == PWR_GDR_IE400G_UX_US_7_UX_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_7_ux_rx_user_clk == OFF_GDR_IE400G_UX_US_7_UX_RX_USER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_7_ux_tx_clk == PWR_GDR_IE400G_UX_US_7_UX_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_7_ux_tx_user_clk_1 == OFF_GDR_IE400G_UX_US_7_UX_TX_USER_CLK_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_7_ux_tx_user_clk_2 == OFF_GDR_IE400G_UX_US_7_UX_TX_USER_CLK_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_8_ux_clk == OFF_GDR_IE400G_UX_US_8_UX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_8_ux_rx_clk == PWR_GDR_IE400G_UX_US_8_UX_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_8_ux_rx_user_clk == PWR_GDR_IE400G_UX_US_8_UX_RX_USER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_8_ux_tx_clk == OFF_GDR_IE400G_UX_US_8_UX_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_8_ux_tx_user_clk_1 == OFF_GDR_IE400G_UX_US_8_UX_TX_USER_CLK_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_8_ux_tx_user_clk_2 == OFF_GDR_IE400G_UX_US_8_UX_TX_USER_CLK_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_9_ux_clk == OFF_GDR_IE400G_UX_US_9_UX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_9_ux_rx_clk == PWR_GDR_IE400G_UX_US_9_UX_RX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_9_ux_rx_user_clk == OFF_GDR_IE400G_UX_US_9_UX_RX_USER_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_9_ux_tx_clk == PWR_GDR_IE400G_UX_US_9_UX_TX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_9_ux_tx_user_clk_1 == OFF_GDR_IE400G_UX_US_9_UX_TX_USER_CLK_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_gdr_ie400g_ux_us_9_ux_tx_user_clk_2 == OFF_GDR_IE400G_UX_US_9_UX_TX_USER_CLK_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_global_avmm_ctrl_barak_rc_slv_clk == PWR_GLOBAL_AVMM_CTRL_BARAK_RC_SLV_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_global_avmm_ctrl_ux_rc_slv_0_clk == PWR_GLOBAL_AVMM_CTRL_UX_RC_SLV_0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_global_avmm_ctrl_ux_rc_slv_1_clk == PWR_GLOBAL_AVMM_CTRL_UX_RC_SLV_1_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_global_avmm_ctrl_ux_rc_slv_2_clk == PWR_GLOBAL_AVMM_CTRL_UX_RC_SLV_2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_global_avmm_ctrl_ux_rc_slv_3_clk == PWR_GLOBAL_AVMM_CTRL_UX_RC_SLV_3_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ictrl_dfd_barak_hub_clk == OFF_ICTRL_DFD_BARAK_HUB_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ictrl_dfd_ux_hub_0_clk == OFF_ICTRL_DFD_UX_HUB_0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ictrl_dfd_ux_hub_1_clk == OFF_ICTRL_DFD_UX_HUB_1_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ictrl_dfd_ux_hub_2_clk == OFF_ICTRL_DFD_UX_HUB_2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ictrl_dfd_ux_hub_3_clk == OFF_ICTRL_DFD_UX_HUB_3_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ictrl_dft_barak_ip_brk_aon_sys_clk == OFF_ICTRL_DFT_BARAK_IP_BRK_AON_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ictrl_dft_barak_ip_brk_bti_clk == OFF_ICTRL_DFT_BARAK_IP_BRK_BTI_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ictrl_dft_barak_ip_dfx_clk == OFF_ICTRL_DFT_BARAK_IP_DFX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ictrl_dft_ux_ip_0_dfx_clk == OFF_ICTRL_DFT_UX_IP_0_DFX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ictrl_dft_ux_ip_1_dfx_clk == OFF_ICTRL_DFT_UX_IP_1_DFX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ictrl_dft_ux_ip_2_dfx_clk == OFF_ICTRL_DFT_UX_IP_2_DFX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ictrl_dft_ux_ip_3_dfx_clk == OFF_ICTRL_DFT_UX_IP_3_DFX_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_iopads_idvp2_xcvrrc_ip_idvfreqa_clk == OFF_IOPADS_IDVP2_XCVRRC_IP_IDVFREQA_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_iopads_idvp2_xcvrrc_ip_idvfreqb_clk == OFF_IOPADS_IDVP2_XCVRRC_IP_IDVFREQB_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_iopads_idvp2_xcvrrc_ip_idvtclk == OFF_IOPADS_IDVP2_XCVRRC_IP_IDVTCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_iopads_pll_xcvrrc_ip_pll_0_slice0_clk == PWR_IOPADS_PLL_XCVRRC_IP_PLL_0_SLICE0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_iopads_pll_xcvrrc_ip_pll_0_slice1_clk == PWR_IOPADS_PLL_XCVRRC_IP_PLL_0_SLICE1_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_iopads_pll_xcvrrc_ip_pll_0_slice2_clk == PWR_IOPADS_PLL_XCVRRC_IP_PLL_0_SLICE2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_iopads_pll_xcvrrc_ip_pll_0_slice3_clk == OFF_IOPADS_PLL_XCVRRC_IP_PLL_0_SLICE3_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_iopads_pll_xcvrrc_ip_pll_1_slice0_clk == PWR_IOPADS_PLL_XCVRRC_IP_PLL_1_SLICE0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_iopads_pll_xcvrrc_ip_pll_1_slice1_clk == PWR_IOPADS_PLL_XCVRRC_IP_PLL_1_SLICE1_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_iopads_pll_xcvrrc_ip_pll_1_slice2_clk == PWR_IOPADS_PLL_XCVRRC_IP_PLL_1_SLICE2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_iopads_pll_xcvrrc_ip_pll_1_slice3_clk == OFF_IOPADS_PLL_XCVRRC_IP_PLL_1_SLICE3_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_iopads_pll_xcvrrc_ip_pll_2_slice0_clk == PWR_IOPADS_PLL_XCVRRC_IP_PLL_2_SLICE0_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_iopads_pll_xcvrrc_ip_pll_2_slice1_clk == PWR_IOPADS_PLL_XCVRRC_IP_PLL_2_SLICE1_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_iopads_pll_xcvrrc_ip_pll_2_slice2_clk == PWR_IOPADS_PLL_XCVRRC_IP_PLL_2_SLICE2_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_iopads_pll_xcvrrc_ip_pll_2_slice3_clk == PWR_IOPADS_PLL_XCVRRC_IP_PLL_2_SLICE3_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_0_pma_pclk == OFF_IPCIE_UX_PCS_0_PMA_PCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_0_pma_ref == OFF_IPCIE_UX_PCS_0_PMA_REF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_0_pma_rxclk == OFF_IPCIE_UX_PCS_0_PMA_RXCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_10_pma_pclk == OFF_IPCIE_UX_PCS_10_PMA_PCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_10_pma_ref == OFF_IPCIE_UX_PCS_10_PMA_REF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_10_pma_rxclk == OFF_IPCIE_UX_PCS_10_PMA_RXCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_11_pma_pclk == OFF_IPCIE_UX_PCS_11_PMA_PCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_11_pma_ref == OFF_IPCIE_UX_PCS_11_PMA_REF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_11_pma_rxclk == OFF_IPCIE_UX_PCS_11_PMA_RXCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_12_pma_pclk == OFF_IPCIE_UX_PCS_12_PMA_PCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_12_pma_ref == OFF_IPCIE_UX_PCS_12_PMA_REF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_12_pma_rxclk == OFF_IPCIE_UX_PCS_12_PMA_RXCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_13_pma_pclk == OFF_IPCIE_UX_PCS_13_PMA_PCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_13_pma_ref == OFF_IPCIE_UX_PCS_13_PMA_REF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_13_pma_rxclk == OFF_IPCIE_UX_PCS_13_PMA_RXCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_14_pma_pclk == OFF_IPCIE_UX_PCS_14_PMA_PCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_14_pma_ref == OFF_IPCIE_UX_PCS_14_PMA_REF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_14_pma_rxclk == OFF_IPCIE_UX_PCS_14_PMA_RXCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_15_pma_pclk == OFF_IPCIE_UX_PCS_15_PMA_PCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_15_pma_ref == OFF_IPCIE_UX_PCS_15_PMA_REF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_15_pma_rxclk == OFF_IPCIE_UX_PCS_15_PMA_RXCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_1_pma_pclk == OFF_IPCIE_UX_PCS_1_PMA_PCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_1_pma_ref == OFF_IPCIE_UX_PCS_1_PMA_REF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_1_pma_rxclk == OFF_IPCIE_UX_PCS_1_PMA_RXCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_2_pma_pclk == OFF_IPCIE_UX_PCS_2_PMA_PCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_2_pma_ref == OFF_IPCIE_UX_PCS_2_PMA_REF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_2_pma_rxclk == OFF_IPCIE_UX_PCS_2_PMA_RXCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_3_pma_pclk == OFF_IPCIE_UX_PCS_3_PMA_PCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_3_pma_ref == OFF_IPCIE_UX_PCS_3_PMA_REF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_3_pma_rxclk == OFF_IPCIE_UX_PCS_3_PMA_RXCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_4_pma_pclk == OFF_IPCIE_UX_PCS_4_PMA_PCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_4_pma_ref == OFF_IPCIE_UX_PCS_4_PMA_REF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_4_pma_rxclk == OFF_IPCIE_UX_PCS_4_PMA_RXCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_5_pma_pclk == OFF_IPCIE_UX_PCS_5_PMA_PCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_5_pma_ref == OFF_IPCIE_UX_PCS_5_PMA_REF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_5_pma_rxclk == OFF_IPCIE_UX_PCS_5_PMA_RXCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_6_pma_pclk == OFF_IPCIE_UX_PCS_6_PMA_PCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_6_pma_ref == OFF_IPCIE_UX_PCS_6_PMA_REF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_6_pma_rxclk == OFF_IPCIE_UX_PCS_6_PMA_RXCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_7_pma_pclk == OFF_IPCIE_UX_PCS_7_PMA_PCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_7_pma_ref == OFF_IPCIE_UX_PCS_7_PMA_REF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_7_pma_rxclk == OFF_IPCIE_UX_PCS_7_PMA_RXCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_8_pma_pclk == OFF_IPCIE_UX_PCS_8_PMA_PCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_8_pma_ref == OFF_IPCIE_UX_PCS_8_PMA_REF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_8_pma_rxclk == OFF_IPCIE_UX_PCS_8_PMA_RXCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_9_pma_pclk == OFF_IPCIE_UX_PCS_9_PMA_PCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_9_pma_ref == OFF_IPCIE_UX_PCS_9_PMA_REF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ipcie_ux_pcs_9_pma_rxclk == OFF_IPCIE_UX_PCS_9_PMA_RXCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_clkrst_xcvrrc_ds_0_sclk == OFF_PCIE_CLKRST_XCVRRC_DS_0_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_clkrst_xcvrrc_ds_1_sclk == OFF_PCIE_CLKRST_XCVRRC_DS_1_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_clkrst_xcvrrc_ds_2_sclk == OFF_PCIE_CLKRST_XCVRRC_DS_2_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_clkrst_xcvrrc_ds_3_sclk == OFF_PCIE_CLKRST_XCVRRC_DS_3_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_clkrst_xcvrrc_ds_4_sclk == OFF_PCIE_CLKRST_XCVRRC_DS_4_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_clkrst_xcvrrc_ds_5_sclk == OFF_PCIE_CLKRST_XCVRRC_DS_5_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_clkrst_xcvrrc_ds_6_sclk == OFF_PCIE_CLKRST_XCVRRC_DS_6_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_clkrst_xcvrrc_ds_7_sclk == OFF_PCIE_CLKRST_XCVRRC_DS_7_SCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_0_pipe_pclk == OFF_PCIE_IUX_PMA_0_PIPE_PCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_0_pma_cmn_ctrl == PWR_PCIE_IUX_PMA_0_PMA_CMN_CTRL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_0_pma_ctrl == PWR_PCIE_IUX_PMA_0_PMA_CTRL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_10_pipe_pclk == OFF_PCIE_IUX_PMA_10_PIPE_PCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_10_pma_cmn_ctrl == PWR_PCIE_IUX_PMA_10_PMA_CMN_CTRL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_10_pma_ctrl == PWR_PCIE_IUX_PMA_10_PMA_CTRL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_11_pipe_pclk == OFF_PCIE_IUX_PMA_11_PIPE_PCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_11_pma_cmn_ctrl == PWR_PCIE_IUX_PMA_11_PMA_CMN_CTRL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_11_pma_ctrl == PWR_PCIE_IUX_PMA_11_PMA_CTRL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_12_pipe_pclk == OFF_PCIE_IUX_PMA_12_PIPE_PCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_12_pma_cmn_ctrl == PWR_PCIE_IUX_PMA_12_PMA_CMN_CTRL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_12_pma_ctrl == PWR_PCIE_IUX_PMA_12_PMA_CTRL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_13_pipe_pclk == OFF_PCIE_IUX_PMA_13_PIPE_PCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_13_pma_cmn_ctrl == PWR_PCIE_IUX_PMA_13_PMA_CMN_CTRL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_13_pma_ctrl == PWR_PCIE_IUX_PMA_13_PMA_CTRL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_14_pipe_pclk == OFF_PCIE_IUX_PMA_14_PIPE_PCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_14_pma_cmn_ctrl == PWR_PCIE_IUX_PMA_14_PMA_CMN_CTRL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_14_pma_ctrl == PWR_PCIE_IUX_PMA_14_PMA_CTRL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_15_pipe_pclk == OFF_PCIE_IUX_PMA_15_PIPE_PCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_15_pma_cmn_ctrl == PWR_PCIE_IUX_PMA_15_PMA_CMN_CTRL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_15_pma_ctrl == PWR_PCIE_IUX_PMA_15_PMA_CTRL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_1_pipe_pclk == OFF_PCIE_IUX_PMA_1_PIPE_PCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_1_pma_cmn_ctrl == PWR_PCIE_IUX_PMA_1_PMA_CMN_CTRL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_1_pma_ctrl == PWR_PCIE_IUX_PMA_1_PMA_CTRL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_2_pipe_pclk == OFF_PCIE_IUX_PMA_2_PIPE_PCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_2_pma_cmn_ctrl == PWR_PCIE_IUX_PMA_2_PMA_CMN_CTRL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_2_pma_ctrl == PWR_PCIE_IUX_PMA_2_PMA_CTRL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_3_pipe_pclk == OFF_PCIE_IUX_PMA_3_PIPE_PCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_3_pma_cmn_ctrl == PWR_PCIE_IUX_PMA_3_PMA_CMN_CTRL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_3_pma_ctrl == PWR_PCIE_IUX_PMA_3_PMA_CTRL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_4_pipe_pclk == OFF_PCIE_IUX_PMA_4_PIPE_PCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_4_pma_cmn_ctrl == PWR_PCIE_IUX_PMA_4_PMA_CMN_CTRL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_4_pma_ctrl == PWR_PCIE_IUX_PMA_4_PMA_CTRL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_5_pipe_pclk == OFF_PCIE_IUX_PMA_5_PIPE_PCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_5_pma_cmn_ctrl == PWR_PCIE_IUX_PMA_5_PMA_CMN_CTRL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_5_pma_ctrl == PWR_PCIE_IUX_PMA_5_PMA_CTRL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_6_pipe_pclk == OFF_PCIE_IUX_PMA_6_PIPE_PCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_6_pma_cmn_ctrl == PWR_PCIE_IUX_PMA_6_PMA_CMN_CTRL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_6_pma_ctrl == PWR_PCIE_IUX_PMA_6_PMA_CTRL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_7_pipe_pclk == OFF_PCIE_IUX_PMA_7_PIPE_PCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_7_pma_cmn_ctrl == PWR_PCIE_IUX_PMA_7_PMA_CMN_CTRL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_7_pma_ctrl == PWR_PCIE_IUX_PMA_7_PMA_CTRL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_8_pipe_pclk == OFF_PCIE_IUX_PMA_8_PIPE_PCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_8_pma_cmn_ctrl == PWR_PCIE_IUX_PMA_8_PMA_CMN_CTRL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_8_pma_ctrl == PWR_PCIE_IUX_PMA_8_PMA_CTRL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_9_pipe_pclk == OFF_PCIE_IUX_PMA_9_PIPE_PCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_9_pma_cmn_ctrl == PWR_PCIE_IUX_PMA_9_PMA_CMN_CTRL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_pcie_iux_pma_9_pma_ctrl == PWR_PCIE_IUX_PMA_9_PMA_CTRL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ux_pll_xvrrc_slv_0_clk0 == PWR_UX_PLL_XVRRC_SLV_0_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ux_pll_xvrrc_slv_0_clk1 == OFF_UX_PLL_XVRRC_SLV_0_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ux_pll_xvrrc_slv_1_clk0 == PWR_UX_PLL_XVRRC_SLV_1_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ux_pll_xvrrc_slv_1_clk1 == PWR_UX_PLL_XVRRC_SLV_1_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ux_pll_xvrrc_slv_2_clk0 == PWR_UX_PLL_XVRRC_SLV_2_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ux_pll_xvrrc_slv_2_clk1 == OFF_UX_PLL_XVRRC_SLV_2_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ux_pll_xvrrc_slv_3_clk0 == OFF_UX_PLL_XVRRC_SLV_3_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_ux_pll_xvrrc_slv_3_clk1 == OFF_UX_PLL_XVRRC_SLV_3_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_barak_us_0_pma_internal_clk1 == OFF_XCVRRC_CLKRST_BARAK_US_0_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_barak_us_0_pma_internal_clk2 == OFF_XCVRRC_CLKRST_BARAK_US_0_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_barak_us_0_standalonecoreclk == OFF_XCVRRC_CLKRST_BARAK_US_0_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_barak_us_0_xcvr_quad_refclk1 == OFF_XCVRRC_CLKRST_BARAK_US_0_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_barak_us_0_xcvr_quad_refclk2 == OFF_XCVRRC_CLKRST_BARAK_US_0_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_barak_us_1_pma_internal_clk1 == OFF_XCVRRC_CLKRST_BARAK_US_1_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_barak_us_1_pma_internal_clk2 == OFF_XCVRRC_CLKRST_BARAK_US_1_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_barak_us_1_standalonecoreclk == OFF_XCVRRC_CLKRST_BARAK_US_1_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_barak_us_1_xcvr_quad_refclk1 == OFF_XCVRRC_CLKRST_BARAK_US_1_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_barak_us_1_xcvr_quad_refclk2 == OFF_XCVRRC_CLKRST_BARAK_US_1_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_barak_us_2_pma_internal_clk1 == OFF_XCVRRC_CLKRST_BARAK_US_2_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_barak_us_2_pma_internal_clk2 == OFF_XCVRRC_CLKRST_BARAK_US_2_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_barak_us_2_standalonecoreclk == OFF_XCVRRC_CLKRST_BARAK_US_2_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_barak_us_2_xcvr_quad_refclk1 == OFF_XCVRRC_CLKRST_BARAK_US_2_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_barak_us_2_xcvr_quad_refclk2 == OFF_XCVRRC_CLKRST_BARAK_US_2_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_barak_us_3_pma_internal_clk1 == OFF_XCVRRC_CLKRST_BARAK_US_3_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_barak_us_3_pma_internal_clk2 == OFF_XCVRRC_CLKRST_BARAK_US_3_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_barak_us_3_standalonecoreclk == OFF_XCVRRC_CLKRST_BARAK_US_3_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_barak_us_3_xcvr_quad_refclk1 == OFF_XCVRRC_CLKRST_BARAK_US_3_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_barak_us_3_xcvr_quad_refclk2 == OFF_XCVRRC_CLKRST_BARAK_US_3_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_0_pma_internal_clk1 == OFF_XCVRRC_CLKRST_UX_US_0_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_0_pma_internal_clk2 == OFF_XCVRRC_CLKRST_UX_US_0_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_0_standalonecoreclk == OFF_XCVRRC_CLKRST_UX_US_0_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_0_xcvr_quad_refclk1 == OFF_XCVRRC_CLKRST_UX_US_0_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_0_xcvr_quad_refclk2 == OFF_XCVRRC_CLKRST_UX_US_0_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_10_pma_internal_clk1 == OFF_XCVRRC_CLKRST_UX_US_10_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_10_pma_internal_clk2 == OFF_XCVRRC_CLKRST_UX_US_10_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_10_standalonecoreclk == OFF_XCVRRC_CLKRST_UX_US_10_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_10_xcvr_quad_refclk1 == OFF_XCVRRC_CLKRST_UX_US_10_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_10_xcvr_quad_refclk2 == OFF_XCVRRC_CLKRST_UX_US_10_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_11_pma_internal_clk1 == OFF_XCVRRC_CLKRST_UX_US_11_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_11_pma_internal_clk2 == OFF_XCVRRC_CLKRST_UX_US_11_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_11_standalonecoreclk == OFF_XCVRRC_CLKRST_UX_US_11_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_11_xcvr_quad_refclk1 == OFF_XCVRRC_CLKRST_UX_US_11_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_11_xcvr_quad_refclk2 == OFF_XCVRRC_CLKRST_UX_US_11_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_12_pma_internal_clk1 == OFF_XCVRRC_CLKRST_UX_US_12_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_12_pma_internal_clk2 == OFF_XCVRRC_CLKRST_UX_US_12_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_12_standalonecoreclk == OFF_XCVRRC_CLKRST_UX_US_12_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_12_xcvr_quad_refclk1 == OFF_XCVRRC_CLKRST_UX_US_12_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_12_xcvr_quad_refclk2 == OFF_XCVRRC_CLKRST_UX_US_12_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_13_pma_internal_clk1 == OFF_XCVRRC_CLKRST_UX_US_13_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_13_pma_internal_clk2 == OFF_XCVRRC_CLKRST_UX_US_13_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_13_standalonecoreclk == OFF_XCVRRC_CLKRST_UX_US_13_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_13_xcvr_quad_refclk1 == OFF_XCVRRC_CLKRST_UX_US_13_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_13_xcvr_quad_refclk2 == OFF_XCVRRC_CLKRST_UX_US_13_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_14_pma_internal_clk1 == OFF_XCVRRC_CLKRST_UX_US_14_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_14_pma_internal_clk2 == OFF_XCVRRC_CLKRST_UX_US_14_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_14_standalonecoreclk == OFF_XCVRRC_CLKRST_UX_US_14_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_14_xcvr_quad_refclk1 == OFF_XCVRRC_CLKRST_UX_US_14_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_14_xcvr_quad_refclk2 == OFF_XCVRRC_CLKRST_UX_US_14_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_15_pma_internal_clk1 == OFF_XCVRRC_CLKRST_UX_US_15_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_15_pma_internal_clk2 == OFF_XCVRRC_CLKRST_UX_US_15_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_15_standalonecoreclk == OFF_XCVRRC_CLKRST_UX_US_15_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_15_xcvr_quad_refclk1 == OFF_XCVRRC_CLKRST_UX_US_15_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_15_xcvr_quad_refclk2 == OFF_XCVRRC_CLKRST_UX_US_15_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_1_pma_internal_clk1 == OFF_XCVRRC_CLKRST_UX_US_1_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_1_pma_internal_clk2 == OFF_XCVRRC_CLKRST_UX_US_1_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_1_standalonecoreclk == OFF_XCVRRC_CLKRST_UX_US_1_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_1_xcvr_quad_refclk1 == OFF_XCVRRC_CLKRST_UX_US_1_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_1_xcvr_quad_refclk2 == OFF_XCVRRC_CLKRST_UX_US_1_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_2_pma_internal_clk1 == OFF_XCVRRC_CLKRST_UX_US_2_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_2_pma_internal_clk2 == OFF_XCVRRC_CLKRST_UX_US_2_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_2_standalonecoreclk == OFF_XCVRRC_CLKRST_UX_US_2_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_2_xcvr_quad_refclk1 == OFF_XCVRRC_CLKRST_UX_US_2_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_2_xcvr_quad_refclk2 == OFF_XCVRRC_CLKRST_UX_US_2_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_3_pma_internal_clk1 == OFF_XCVRRC_CLKRST_UX_US_3_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_3_pma_internal_clk2 == OFF_XCVRRC_CLKRST_UX_US_3_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_3_standalonecoreclk == OFF_XCVRRC_CLKRST_UX_US_3_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_3_xcvr_quad_refclk1 == OFF_XCVRRC_CLKRST_UX_US_3_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_3_xcvr_quad_refclk2 == OFF_XCVRRC_CLKRST_UX_US_3_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_4_pma_internal_clk1 == OFF_XCVRRC_CLKRST_UX_US_4_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_4_pma_internal_clk2 == OFF_XCVRRC_CLKRST_UX_US_4_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_4_standalonecoreclk == OFF_XCVRRC_CLKRST_UX_US_4_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_4_xcvr_quad_refclk1 == OFF_XCVRRC_CLKRST_UX_US_4_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_4_xcvr_quad_refclk2 == OFF_XCVRRC_CLKRST_UX_US_4_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_5_pma_internal_clk1 == OFF_XCVRRC_CLKRST_UX_US_5_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_5_pma_internal_clk2 == OFF_XCVRRC_CLKRST_UX_US_5_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_5_standalonecoreclk == OFF_XCVRRC_CLKRST_UX_US_5_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_5_xcvr_quad_refclk1 == OFF_XCVRRC_CLKRST_UX_US_5_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_5_xcvr_quad_refclk2 == OFF_XCVRRC_CLKRST_UX_US_5_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_6_pma_internal_clk1 == OFF_XCVRRC_CLKRST_UX_US_6_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_6_pma_internal_clk2 == OFF_XCVRRC_CLKRST_UX_US_6_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_6_standalonecoreclk == OFF_XCVRRC_CLKRST_UX_US_6_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_6_xcvr_quad_refclk1 == OFF_XCVRRC_CLKRST_UX_US_6_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_6_xcvr_quad_refclk2 == OFF_XCVRRC_CLKRST_UX_US_6_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_7_pma_internal_clk1 == OFF_XCVRRC_CLKRST_UX_US_7_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_7_pma_internal_clk2 == OFF_XCVRRC_CLKRST_UX_US_7_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_7_standalonecoreclk == OFF_XCVRRC_CLKRST_UX_US_7_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_7_xcvr_quad_refclk1 == OFF_XCVRRC_CLKRST_UX_US_7_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_7_xcvr_quad_refclk2 == OFF_XCVRRC_CLKRST_UX_US_7_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_8_pma_internal_clk1 == OFF_XCVRRC_CLKRST_UX_US_8_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_8_pma_internal_clk2 == OFF_XCVRRC_CLKRST_UX_US_8_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_8_standalonecoreclk == OFF_XCVRRC_CLKRST_UX_US_8_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_8_xcvr_quad_refclk1 == OFF_XCVRRC_CLKRST_UX_US_8_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_8_xcvr_quad_refclk2 == OFF_XCVRRC_CLKRST_UX_US_8_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_9_pma_internal_clk1 == OFF_XCVRRC_CLKRST_UX_US_9_PMA_INTERNAL_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_9_pma_internal_clk2 == OFF_XCVRRC_CLKRST_UX_US_9_PMA_INTERNAL_CLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_9_standalonecoreclk == OFF_XCVRRC_CLKRST_UX_US_9_STANDALONECORECLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_9_xcvr_quad_refclk1 == OFF_XCVRRC_CLKRST_UX_US_9_XCVR_QUAD_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_ac_xcvrrc_clkrst_ux_us_9_xcvr_quad_refclk2 == OFF_XCVRRC_CLKRST_UX_US_9_XCVR_QUAD_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_barak_idvp2_xcvrrc_ip_idvfreqa_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_barak_idvp2_xcvrrc_ip_idvfreqb_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_barak_idvp2_xcvrrc_ip_idvtclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ctrl_dft_ux_rc_tcb_0_ref_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ctrl_dft_ux_rc_tcb_1_ref_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ctrl_dft_ux_rc_tcb_2_ref_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ctrl_dft_ux_rc_tcb_3_ref_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_e200g_clkrst_xcvrrc_ds_0_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_e200g_clkrst_xcvrrc_ds_1_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_e200g_clkrst_xcvrrc_ds_2_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_e200g_clkrst_xcvrrc_ds_3_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_e400g_clkrst_xcvrrc_ds_0_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_e400g_clkrst_xcvrrc_ds_10_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_e400g_clkrst_xcvrrc_ds_11_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_e400g_clkrst_xcvrrc_ds_1_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_e400g_clkrst_xcvrrc_ds_2_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_e400g_clkrst_xcvrrc_ds_3_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_e400g_clkrst_xcvrrc_ds_4_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_e400g_clkrst_xcvrrc_ds_5_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_e400g_clkrst_xcvrrc_ds_6_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_e400g_clkrst_xcvrrc_ds_7_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_e400g_clkrst_xcvrrc_ds_8_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_e400g_clkrst_xcvrrc_ds_9_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_e200g_iux_ds_0_ux_tx_clk_ds_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_e200g_iux_ds_1_ux_tx_clk_ds_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_e200g_iux_ds_2_ux_tx_clk_ds_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_e200g_iux_ds_3_ux_tx_clk_ds_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_e200g_iux_ds_4_ux_tx_clk_ds_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_e200g_iux_ds_5_ux_tx_clk_ds_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_e200g_iux_ds_6_ux_tx_clk_ds_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_e200g_iux_ds_7_ux_tx_clk_ds_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_e400g_ibarak_ds_0_brk_pcs_srds_tx_clki_lanex_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_e400g_ibarak_ds_1_brk_pcs_srds_tx_clki_lanex_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_e400g_ibarak_ds_2_brk_pcs_srds_tx_clki_lanex_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_e400g_ibarak_ds_3_brk_pcs_srds_tx_clki_lanex_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_e400g_iux_ds_0_ux_tx_clk_ds_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_e400g_iux_ds_10_ux_tx_clk_ds_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_e400g_iux_ds_11_ux_tx_clk_ds_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_e400g_iux_ds_12_ux_tx_clk_ds_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_e400g_iux_ds_13_ux_tx_clk_ds_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_e400g_iux_ds_14_ux_tx_clk_ds_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_e400g_iux_ds_15_ux_tx_clk_ds_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_e400g_iux_ds_1_ux_tx_clk_ds_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_e400g_iux_ds_2_ux_tx_clk_ds_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_e400g_iux_ds_3_ux_tx_clk_ds_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_e400g_iux_ds_4_ux_tx_clk_ds_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_e400g_iux_ds_5_ux_tx_clk_ds_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_e400g_iux_ds_6_ux_tx_clk_ds_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_e400g_iux_ds_7_ux_tx_clk_ds_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_e400g_iux_ds_8_ux_tx_clk_ds_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_e400g_iux_ds_9_ux_tx_clk_ds_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_0_ux_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_0_ux_rx_clk_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_0_ux_rx_user_clk_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_0_ux_tx_clk_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_0_ux_tx_user_clk_1_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_0_ux_tx_user_clk_2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_10_ux_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_10_ux_rx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_10_ux_rx_user_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_10_ux_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_10_ux_tx_user_clk_1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_10_ux_tx_user_clk_2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_11_ux_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_11_ux_rx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_11_ux_rx_user_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_11_ux_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_11_ux_tx_user_clk_1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_11_ux_tx_user_clk_2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_12_ux_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_12_ux_rx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_12_ux_rx_user_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_12_ux_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_12_ux_tx_user_clk_1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_12_ux_tx_user_clk_2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_13_ux_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_13_ux_rx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_13_ux_rx_user_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_13_ux_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_13_ux_tx_user_clk_1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_13_ux_tx_user_clk_2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_14_ux_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_14_ux_rx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_14_ux_rx_user_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_14_ux_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_14_ux_tx_user_clk_1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_14_ux_tx_user_clk_2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_15_ux_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_15_ux_rx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_15_ux_rx_user_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_15_ux_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_15_ux_tx_user_clk_1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_15_ux_tx_user_clk_2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_1_ux_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_1_ux_rx_clk_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_1_ux_rx_user_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_1_ux_tx_clk_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_1_ux_tx_user_clk_1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_1_ux_tx_user_clk_2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_2_ux_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_2_ux_rx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_2_ux_rx_user_clk_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_2_ux_tx_clk_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_2_ux_tx_user_clk_1_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_2_ux_tx_user_clk_2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_3_ux_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_3_ux_rx_clk_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_3_ux_rx_user_clk_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_3_ux_tx_clk_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_3_ux_tx_user_clk_1_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_3_ux_tx_user_clk_2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_4_ux_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_4_ux_rx_clk_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_4_ux_rx_user_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_4_ux_tx_clk_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_4_ux_tx_user_clk_1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_4_ux_tx_user_clk_2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_5_ux_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_5_ux_rx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_5_ux_rx_user_clk_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_5_ux_tx_clk_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_5_ux_tx_user_clk_1_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_5_ux_tx_user_clk_2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_6_ux_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_6_ux_rx_clk_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_6_ux_rx_user_clk_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_6_ux_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_6_ux_tx_user_clk_1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_6_ux_tx_user_clk_2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_7_ux_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_7_ux_rx_clk_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_7_ux_rx_user_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_7_ux_tx_clk_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_7_ux_tx_user_clk_1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_7_ux_tx_user_clk_2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_8_ux_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_8_ux_rx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_8_ux_rx_user_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_8_ux_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_8_ux_tx_user_clk_1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_8_ux_tx_user_clk_2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_9_ux_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_9_ux_rx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_9_ux_rx_user_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_9_ux_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_9_ux_tx_user_clk_1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie200g_ux_us_9_ux_tx_user_clk_2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_barak_us_0_brk_pcs_srds_rx_clk_lanex_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_barak_us_0_brk_pcs_srds_rx_usr_clk1_lanex_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_barak_us_0_brk_pcs_srds_rx_usr_clk2_lanex_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_barak_us_0_brk_pcs_srds_tx_clko_lanex_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_barak_us_0_brk_pcs_srds_tx_usr_clk1_lanex_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_barak_us_0_brk_pcs_srds_tx_usr_clk2_lanex_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_barak_us_1_brk_pcs_srds_rx_clk_lanex_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_barak_us_1_brk_pcs_srds_rx_usr_clk1_lanex_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_barak_us_1_brk_pcs_srds_rx_usr_clk2_lanex_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_barak_us_1_brk_pcs_srds_tx_clko_lanex_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_barak_us_1_brk_pcs_srds_tx_usr_clk1_lanex_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_barak_us_1_brk_pcs_srds_tx_usr_clk2_lanex_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_barak_us_2_brk_pcs_srds_rx_clk_lanex_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_barak_us_2_brk_pcs_srds_rx_usr_clk1_lanex_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_barak_us_2_brk_pcs_srds_rx_usr_clk2_lanex_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_barak_us_2_brk_pcs_srds_tx_clko_lanex_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_barak_us_2_brk_pcs_srds_tx_usr_clk1_lanex_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_barak_us_2_brk_pcs_srds_tx_usr_clk2_lanex_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_barak_us_3_brk_pcs_srds_rx_clk_lanex_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_barak_us_3_brk_pcs_srds_rx_usr_clk1_lanex_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_barak_us_3_brk_pcs_srds_rx_usr_clk2_lanex_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_barak_us_3_brk_pcs_srds_tx_clko_lanex_hz == 36'd10000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_barak_us_3_brk_pcs_srds_tx_usr_clk1_lanex_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_barak_us_3_brk_pcs_srds_tx_usr_clk2_lanex_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_0_ux_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_0_ux_rx_clk_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_0_ux_rx_user_clk_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_0_ux_tx_clk_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_0_ux_tx_user_clk_1_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_0_ux_tx_user_clk_2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_10_ux_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_10_ux_rx_clk_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_10_ux_rx_user_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_10_ux_tx_clk_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_10_ux_tx_user_clk_1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_10_ux_tx_user_clk_2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_11_ux_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_11_ux_rx_clk_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_11_ux_rx_user_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_11_ux_tx_clk_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_11_ux_tx_user_clk_1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_11_ux_tx_user_clk_2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_12_ux_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_12_ux_rx_clk_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_12_ux_rx_user_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_12_ux_tx_clk_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_12_ux_tx_user_clk_1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_12_ux_tx_user_clk_2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_13_ux_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_13_ux_rx_clk_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_13_ux_rx_user_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_13_ux_tx_clk_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_13_ux_tx_user_clk_1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_13_ux_tx_user_clk_2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_14_ux_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_14_ux_rx_clk_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_14_ux_rx_user_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_14_ux_tx_clk_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_14_ux_tx_user_clk_1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_14_ux_tx_user_clk_2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_15_ux_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_15_ux_rx_clk_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_15_ux_rx_user_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_15_ux_tx_clk_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_15_ux_tx_user_clk_1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_15_ux_tx_user_clk_2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_1_ux_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_1_ux_rx_clk_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_1_ux_rx_user_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_1_ux_tx_clk_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_1_ux_tx_user_clk_1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_1_ux_tx_user_clk_2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_2_ux_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_2_ux_rx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_2_ux_rx_user_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_2_ux_tx_clk_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_2_ux_tx_user_clk_1_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_2_ux_tx_user_clk_2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_3_ux_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_3_ux_rx_clk_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_3_ux_rx_user_clk_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_3_ux_tx_clk_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_3_ux_tx_user_clk_1_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_3_ux_tx_user_clk_2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_4_ux_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_4_ux_rx_clk_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_4_ux_rx_user_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_4_ux_tx_clk_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_4_ux_tx_user_clk_1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_4_ux_tx_user_clk_2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_5_ux_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_5_ux_rx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_5_ux_rx_user_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_5_ux_tx_clk_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_5_ux_tx_user_clk_1_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_5_ux_tx_user_clk_2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_6_ux_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_6_ux_rx_clk_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_6_ux_rx_user_clk_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_6_ux_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_6_ux_tx_user_clk_1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_6_ux_tx_user_clk_2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_7_ux_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_7_ux_rx_clk_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_7_ux_rx_user_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_7_ux_tx_clk_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_7_ux_tx_user_clk_1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_7_ux_tx_user_clk_2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_8_ux_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_8_ux_rx_clk_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_8_ux_rx_user_clk_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_8_ux_tx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_8_ux_tx_user_clk_1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_8_ux_tx_user_clk_2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_9_ux_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_9_ux_rx_clk_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_9_ux_rx_user_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_9_ux_tx_clk_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_9_ux_tx_user_clk_1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_gdr_ie400g_ux_us_9_ux_tx_user_clk_2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_global_avmm_ctrl_barak_rc_slv_clk_hz == 36'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_global_avmm_ctrl_ux_rc_slv_0_clk_hz == 36'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_global_avmm_ctrl_ux_rc_slv_1_clk_hz == 36'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_global_avmm_ctrl_ux_rc_slv_2_clk_hz == 36'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_global_avmm_ctrl_ux_rc_slv_3_clk_hz == 36'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ictrl_dfd_barak_hub_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ictrl_dfd_ux_hub_0_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ictrl_dfd_ux_hub_1_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ictrl_dfd_ux_hub_2_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ictrl_dfd_ux_hub_3_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ictrl_dft_barak_ip_brk_aon_sys_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ictrl_dft_barak_ip_brk_bti_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ictrl_dft_barak_ip_dfx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ictrl_dft_ux_ip_0_dfx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ictrl_dft_ux_ip_1_dfx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ictrl_dft_ux_ip_2_dfx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ictrl_dft_ux_ip_3_dfx_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_iopads_idvp2_xcvrrc_ip_idvfreqa_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_iopads_idvp2_xcvrrc_ip_idvfreqb_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_iopads_idvp2_xcvrrc_ip_idvtclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_iopads_pll_xcvrrc_ip_pll_0_slice0_clk_hz == 36'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_iopads_pll_xcvrrc_ip_pll_0_slice1_clk_hz == 36'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_iopads_pll_xcvrrc_ip_pll_0_slice2_clk_hz == 36'd250000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_iopads_pll_xcvrrc_ip_pll_0_slice3_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_iopads_pll_xcvrrc_ip_pll_1_slice0_clk_hz == 36'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_iopads_pll_xcvrrc_ip_pll_1_slice1_clk_hz == 36'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_iopads_pll_xcvrrc_ip_pll_1_slice2_clk_hz == 36'd250000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_iopads_pll_xcvrrc_ip_pll_1_slice3_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_iopads_pll_xcvrrc_ip_pll_2_slice0_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_iopads_pll_xcvrrc_ip_pll_2_slice1_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_iopads_pll_xcvrrc_ip_pll_2_slice2_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_iopads_pll_xcvrrc_ip_pll_2_slice3_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_0_pma_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_0_pma_ref_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_0_pma_rxclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_10_pma_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_10_pma_ref_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_10_pma_rxclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_11_pma_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_11_pma_ref_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_11_pma_rxclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_12_pma_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_12_pma_ref_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_12_pma_rxclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_13_pma_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_13_pma_ref_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_13_pma_rxclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_14_pma_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_14_pma_ref_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_14_pma_rxclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_15_pma_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_15_pma_ref_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_15_pma_rxclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_1_pma_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_1_pma_ref_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_1_pma_rxclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_2_pma_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_2_pma_ref_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_2_pma_rxclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_3_pma_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_3_pma_ref_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_3_pma_rxclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_4_pma_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_4_pma_ref_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_4_pma_rxclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_5_pma_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_5_pma_ref_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_5_pma_rxclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_6_pma_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_6_pma_ref_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_6_pma_rxclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_7_pma_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_7_pma_ref_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_7_pma_rxclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_8_pma_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_8_pma_ref_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_8_pma_rxclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_9_pma_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_9_pma_ref_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ipcie_ux_pcs_9_pma_rxclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_clkrst_xcvrrc_ds_0_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_clkrst_xcvrrc_ds_1_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_clkrst_xcvrrc_ds_2_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_clkrst_xcvrrc_ds_3_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_clkrst_xcvrrc_ds_4_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_clkrst_xcvrrc_ds_5_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_clkrst_xcvrrc_ds_6_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_clkrst_xcvrrc_ds_7_sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_0_pipe_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_0_pma_cmn_ctrl_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_0_pma_ctrl_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_10_pipe_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_10_pma_cmn_ctrl_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_10_pma_ctrl_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_11_pipe_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_11_pma_cmn_ctrl_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_11_pma_ctrl_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_12_pipe_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_12_pma_cmn_ctrl_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_12_pma_ctrl_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_13_pipe_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_13_pma_cmn_ctrl_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_13_pma_ctrl_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_14_pipe_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_14_pma_cmn_ctrl_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_14_pma_ctrl_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_15_pipe_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_15_pma_cmn_ctrl_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_15_pma_ctrl_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_1_pipe_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_1_pma_cmn_ctrl_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_1_pma_ctrl_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_2_pipe_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_2_pma_cmn_ctrl_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_2_pma_ctrl_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_3_pipe_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_3_pma_cmn_ctrl_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_3_pma_ctrl_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_4_pipe_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_4_pma_cmn_ctrl_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_4_pma_ctrl_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_5_pipe_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_5_pma_cmn_ctrl_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_5_pma_ctrl_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_6_pipe_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_6_pma_cmn_ctrl_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_6_pma_ctrl_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_7_pipe_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_7_pma_cmn_ctrl_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_7_pma_ctrl_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_8_pipe_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_8_pma_cmn_ctrl_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_8_pma_ctrl_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_9_pipe_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_9_pma_cmn_ctrl_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_pcie_iux_pma_9_pma_ctrl_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ux_pll_xvrrc_slv_0_clk0_hz == 36'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ux_pll_xvrrc_slv_0_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ux_pll_xvrrc_slv_1_clk0_hz == 36'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ux_pll_xvrrc_slv_1_clk1_hz == 36'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ux_pll_xvrrc_slv_2_clk0_hz == 36'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ux_pll_xvrrc_slv_2_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ux_pll_xvrrc_slv_3_clk0_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_ux_pll_xvrrc_slv_3_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_barak_us_0_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_barak_us_0_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_barak_us_0_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_barak_us_0_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_barak_us_0_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_barak_us_1_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_barak_us_1_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_barak_us_1_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_barak_us_1_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_barak_us_1_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_barak_us_2_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_barak_us_2_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_barak_us_2_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_barak_us_2_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_barak_us_2_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_barak_us_3_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_barak_us_3_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_barak_us_3_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_barak_us_3_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_barak_us_3_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_0_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_0_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_0_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_0_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_0_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_10_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_10_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_10_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_10_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_10_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_11_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_11_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_11_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_11_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_11_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_12_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_12_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_12_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_12_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_12_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_13_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_13_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_13_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_13_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_13_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_14_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_14_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_14_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_14_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_14_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_15_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_15_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_15_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_15_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_15_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_1_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_1_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_1_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_1_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_1_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_2_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_2_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_2_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_2_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_2_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_3_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_3_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_3_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_3_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_3_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_4_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_4_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_4_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_4_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_4_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_5_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_5_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_5_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_5_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_5_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_6_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_6_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_6_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_6_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_6_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_7_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_7_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_7_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_7_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_7_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_8_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_8_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_8_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_8_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_8_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_9_pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_9_pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_9_standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_9_xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.powermode_freq_hz_i_xcvrrc_clkrst_ux_us_9_xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_gdr_xcvr_rc.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib0_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib0_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib10_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib10_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib11_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib11_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib12_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib12_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib13_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib13_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib14_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib14_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib15_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib15_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib16_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib16_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib17_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib17_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib18_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib18_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib19_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib19_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib1_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib1_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib20_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib20_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib21_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib21_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib22_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib22_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib23_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib23_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib2_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib2_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib3_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib3_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib4_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib4_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib5_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib5_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib6_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib6_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib7_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib7_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib8_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib8_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib9_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aib9_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aibrc_clkrst_pcie_ds_0sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aibrc_clkrst_pcie_ds_1sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aibrc_clkrst_pcie_ds_2sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aibrc_clkrst_pcie_ds_3sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aibrc_clkrst_pcie_ds_4sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aibrc_clkrst_pcie_ds_5sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aibrc_clkrst_pcie_ds_6sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.aibrc_clkrst_pcie_ds_7sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.cfg_avmmclk_hz == 36'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.cvp_enable == CVP_IS_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.cvpavmm_clk_in_hz == 36'd250000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.dfd_enable == DFD_IS_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.dwip_x16_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.dwip_x16_uses_pin_perstn == PERSTN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.dwip_x40_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.dwip_x41_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.dwip_x8_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.e200g_idvp1_pcie_ipidvfreqa_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.e200g_idvp1_pcie_ipidvfreqb_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.e200g_idvp1_pcie_ipidvtclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.ippwrmod_freq == CLK1G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_0pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_0pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_0standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_0xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_0xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_1pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_1pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_1standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_1xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_1xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_2pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_2pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_2standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_2xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_2xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_3pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_3pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_3standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_3xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_3xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_4pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_4pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_4standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_4xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_4xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_5pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_5pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_5standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_5xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_5xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_6pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_6pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_6standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_6xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_6xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_7pma_internal_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_7pma_internal_clk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_7standalonecoreclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_7xcvr_quad_refclk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_clkrst_xcvrrc_us_7xcvr_quad_refclk2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pcie_gen_capable == GEN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pld_clk_2x_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pld_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pllpll_0_slice0_clk_hz == 36'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pllpll_0_slice1_clk_hz == 36'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pllpll_1_slice0_clk_hz == 36'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pllpll_1_slice1_clk_hz == 36'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pllpll_2_slice0_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.pllpll_2_slice1_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.powermode_ac == PCIE_PWR_G4_X16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.sys_clk_select == PLL_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.tcbctldfx_clk0_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.tcbctldfx_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.tcbpcsdfx_clk0_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.tcbpcsdfx_clk1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.topology == DISABLED_SYSTEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq0pma_cmn_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq0pma_ctrl_l_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq0pma_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq0pma_ref_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq0pma_rxclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq10pma_cmn_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq10pma_ctrl_l_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq10pma_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq10pma_ref_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq10pma_rxclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq11pma_cmn_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq11pma_ctrl_l_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq11pma_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq11pma_ref_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq11pma_rxclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq12pma_cmn_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq12pma_ctrl_l_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq12pma_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq12pma_ref_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq12pma_rxclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq13pma_cmn_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq13pma_ctrl_l_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq13pma_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq13pma_ref_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq13pma_rxclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq14pma_cmn_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq14pma_ctrl_l_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq14pma_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq14pma_ref_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq14pma_rxclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq15pma_cmn_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq15pma_ctrl_l_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq15pma_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq15pma_ref_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq15pma_rxclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq1pma_cmn_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq1pma_ctrl_l_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq1pma_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq1pma_ref_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq1pma_rxclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq2pma_cmn_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq2pma_ctrl_l_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq2pma_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq2pma_ref_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq2pma_rxclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq3pma_cmn_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq3pma_ctrl_l_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq3pma_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq3pma_ref_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq3pma_rxclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq4pma_cmn_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq4pma_ctrl_l_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq4pma_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq4pma_ref_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq4pma_rxclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq5pma_cmn_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq5pma_ctrl_l_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq5pma_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq5pma_ref_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq5pma_rxclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq6pma_cmn_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq6pma_ctrl_l_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq6pma_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq6pma_ref_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq6pma_rxclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq7pma_cmn_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq7pma_ctrl_l_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq7pma_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq7pma_ref_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq7pma_rxclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq8pma_cmn_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq8pma_ctrl_l_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq8pma_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq8pma_ref_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq8pma_rxclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq9pma_cmn_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq9pma_ctrl_l_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq9pma_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq9pma_ref_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.uxq9pma_rxclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.virtual_cfg_func_mode == PCIE_G4_X16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.virtual_dwip_x16_negociated_speed == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.virtual_dwip_x4_0_negociated_speed == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.virtual_dwip_x4_1_negociated_speed == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.virtual_dwip_x8_negociated_speed == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.virtual_port_type == EP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.virtual_powerdown_mode == POWER_DOWN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.virtual_sim_mode == DISABLE_VSIM_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.virtual_sris_enable == DISABLE_SRIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.virtual_sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.virtual_tlp_bypass_en == DISABLE_TLBP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib0_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib0_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib10_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib10_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib11_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib11_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib12_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib12_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib13_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib13_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib14_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib14_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib15_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib15_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib16_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib16_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib17_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib17_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib18_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib18_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib19_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib19_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib1_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib1_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib20_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib20_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib21_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib21_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib22_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib22_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib23_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib23_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib2_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib2_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib3_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib3_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib4_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib4_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib5_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib5_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib6_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib6_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib7_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib7_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib8_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib8_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib9_rx_transfer_clk_div2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aib9_rx_transfer_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aibrc_clkrst_pcie_ds_0sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aibrc_clkrst_pcie_ds_1sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aibrc_clkrst_pcie_ds_2sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aibrc_clkrst_pcie_ds_3sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aibrc_clkrst_pcie_ds_4sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aibrc_clkrst_pcie_ds_5sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aibrc_clkrst_pcie_ds_6sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.aibrc_clkrst_pcie_ds_7sclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.cfg_avmmclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.cvpavmm_clk_in_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.dwip_x16_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.dwip_x40_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.dwip_x41_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.dwip_x8_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.e200g_idvp1_pcie_ipidvfreqa_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.e200g_idvp1_pcie_ipidvfreqb_clk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.e200g_idvp1_pcie_ipidvtclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ippwrmod_freq == CLK1G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.pld_clk_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.powermode_ac == DISABLED_AC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.powermode_ac_global_avmm == GLOBAL_AVMM_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.powermode_freq_hz_o_dwip_x16_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.powermode_freq_hz_o_dwip_x40_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.powermode_freq_hz_o_dwip_x41_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.powermode_freq_hz_o_dwip_x8_pclk_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.powermode_freq_hz_pcie_ctrltop_global_avmm == 37'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.topology == DISABLED_SYSTEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.virtual_dwip_x16_negociated_speed == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.virtual_dwip_x4_0_negociated_speed == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.virtual_dwip_x4_1_negociated_speed == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.virtual_dwip_x8_negociated_speed == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.virtual_pcie_rate == PCIE_GEN4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.virtual_pcie_x4_tlpbp == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.virtual_port_type == EP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.virtual_ptm == DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.virtual_sris_enable == DISABLE_SRIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.virtual_sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.virtual_tlp_bypass_en == DISABLE_TLPBP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.virtual_x16_perst_sel == CMN_HARD_X16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.virtual_x40_perst_sel == CMN_HARD_X40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.virtual_x41_perst_sel == CMN_HARD_X41
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.virtual_x8_perst_sel == CMN_HARD_X8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.app_err_func_num == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.app_err_hdr_log0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.app_err_hdr_log1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.app_err_hdr_log2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.app_err_hdr_log3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.app_err_info == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.app_err_prefix == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.app_err_valid == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cfg_bad_dllp_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cfg_bad_tlp_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cfg_blk_crs_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cfg_corrected_internal_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cfg_dbi_pf0_table_size == 12'd347
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cfg_dbi_pf1_start_addr == 12'd384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cfg_dbi_pf1_table_size == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cfg_dbi_pf2_start_addr == 12'd640
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cfg_dbi_pf2_table_size == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cfg_dbi_pf3_start_addr == 12'd896
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cfg_dbi_pf3_table_size == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cfg_dbi_pf4_start_addr == 12'd1152
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cfg_dbi_pf4_table_size == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cfg_dbi_pf5_start_addr == 12'd1408
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cfg_dbi_pf5_table_size == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cfg_dbi_pf6_start_addr == 12'd1664
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cfg_dbi_pf6_table_size == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cfg_dbi_pf7_start_addr == 12'd1920
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cfg_dbi_pf7_table_size == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cfg_dl_protocol_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cfg_ecrc_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cfg_fc_protocol_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cfg_mlf_tlp_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cfg_ptm_auto_update_signal == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cfg_ptm_local_clock_adj_lsb == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cfg_ptm_local_clock_adj_msb == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cfg_ram_ecc_chk_val == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cfg_ram_ecc_gen_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cfg_rcvr_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cfg_rcvr_overflow_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cfg_replay_number_rollover_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cfg_replay_timer_timeout_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cfg_surprise_down_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cfg_uncor_internal_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.clrhip_not_rst_sticky == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.crs_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.crs_override_value == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cvp_blocking_dis == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cvp_data_compressed == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cvp_data_encrypted == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cvp_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cvp_hard_reset_bypass == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cvp_hip_clk_sel_default == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cvp_irq_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cvp_jtag0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cvp_jtag1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cvp_jtag2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cvp_jtag3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cvp_mode_default == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cvp_mode_gating_dis == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cvp_update_no_reset == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cvp_user_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cvp_vsec_id == 16'd4466
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cvp_vsec_rev == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cvp_warm_rst_ready_force_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cvp_warm_rst_ready_force_bit1 == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cvp_warm_rst_req_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.cvp_write_mask_ctl == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.dbg_clk_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.dbi_ro_wr_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.device_type == DEV_NEP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.device_width == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.disable_ct_ur == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.disable_msg_ur == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.disable_ur_nf == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.dyngate_sriov_clk_dis == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.dyngate_vfspfnum_core_clk_dis == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.ecrc_strip == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.enable_poison_nf == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.ep_signal_mask == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.err_tlp_bypass == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_acs_nxtptr_pf0 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_acs_nxtptr_pf1 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_acs_nxtptr_pf2 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_acs_nxtptr_pf3 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_acs_nxtptr_pf4 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_acs_nxtptr_pf5 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_acs_nxtptr_pf6 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_acs_nxtptr_pf7 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_acscap_enable_pf0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_acscap_enable_pf1 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_acscap_enable_pf2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_acscap_enable_pf3 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_acscap_enable_pf4 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_acscap_enable_pf5 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_acscap_enable_pf6 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_acscap_enable_pf7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_aricap_enable == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_aricap_nxtptr_pf0 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_aricap_nxtptr_pf1 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_aricap_nxtptr_pf2 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_aricap_nxtptr_pf3 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_aricap_nxtptr_pf4 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_aricap_nxtptr_pf5 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_aricap_nxtptr_pf6 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_aricap_nxtptr_pf7 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_ats_globalinvalidate_pf0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_ats_globalinvalidate_pf1 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_ats_globalinvalidate_pf2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_ats_globalinvalidate_pf3 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_ats_globalinvalidate_pf4 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_ats_globalinvalidate_pf5 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_ats_globalinvalidate_pf6 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_ats_globalinvalidate_pf7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_ats_invalidateqdepth_pf0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_ats_invalidateqdepth_pf1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_ats_invalidateqdepth_pf2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_ats_invalidateqdepth_pf3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_ats_invalidateqdepth_pf4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_ats_invalidateqdepth_pf5 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_ats_invalidateqdepth_pf6 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_ats_invalidateqdepth_pf7 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_ats_nxtptr_pf0 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_ats_nxtptr_pf1 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_ats_nxtptr_pf2 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_ats_nxtptr_pf3 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_ats_nxtptr_pf4 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_ats_nxtptr_pf5 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_ats_nxtptr_pf6 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_ats_nxtptr_pf7 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_ats_pagealignreq_pf0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_ats_pagealignreq_pf1 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_ats_pagealignreq_pf2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_ats_pagealignreq_pf3 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_ats_pagealignreq_pf4 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_ats_pagealignreq_pf5 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_ats_pagealignreq_pf6 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_ats_pagealignreq_pf7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_atscap_enable == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msix_nxtptr_pf0 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msix_nxtptr_pf1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msix_nxtptr_pf2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msix_nxtptr_pf3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msix_nxtptr_pf4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msix_nxtptr_pf5 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msix_nxtptr_pf6 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msix_nxtptr_pf7 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msix_tablesize_pf0 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msix_tablesize_pf1 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msix_tablesize_pf2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msix_tablesize_pf3 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msix_tablesize_pf4 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msix_tablesize_pf5 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msix_tablesize_pf6 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msix_tablesize_pf7 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msixcap_enable == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msixpba_bir_pf0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msixpba_bir_pf1 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msixpba_bir_pf2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msixpba_bir_pf3 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msixpba_bir_pf4 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msixpba_bir_pf5 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msixpba_bir_pf6 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msixpba_bir_pf7 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msixpba_offset_pf0 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msixpba_offset_pf1 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msixpba_offset_pf2 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msixpba_offset_pf3 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msixpba_offset_pf4 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msixpba_offset_pf5 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msixpba_offset_pf6 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msixpba_offset_pf7 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msixtable_bir_pf0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msixtable_bir_pf1 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msixtable_bir_pf2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msixtable_bir_pf3 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msixtable_bir_pf4 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msixtable_bir_pf5 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msixtable_bir_pf6 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msixtable_bir_pf7 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msixtable_offset_pf0 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msixtable_offset_pf1 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msixtable_offset_pf2 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msixtable_offset_pf3 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msixtable_offset_pf4 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msixtable_offset_pf5 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msixtable_offset_pf6 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_msixtable_offset_pf7 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_pciecap_nxtptr_pf0 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_pciecap_nxtptr_pf1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_pciecap_nxtptr_pf2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_pciecap_nxtptr_pf3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_pciecap_nxtptr_pf4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_pciecap_nxtptr_pf5 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_pciecap_nxtptr_pf6 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_pciecap_nxtptr_pf7 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_revisionid_pf0 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_revisionid_pf1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_revisionid_pf2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_revisionid_pf3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_revisionid_pf4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_revisionid_pf5 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_revisionid_pf6 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_revisionid_pf7 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_subsysid_pf0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_subsysid_pf1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_subsysid_pf2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_subsysid_pf3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_subsysid_pf4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_subsysid_pf5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_subsysid_pf6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_subsysid_pf7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_devspecificmode_pf0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_devspecificmode_pf1 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_devspecificmode_pf2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_devspecificmode_pf3 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_devspecificmode_pf4 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_devspecificmode_pf5 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_devspecificmode_pf6 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_devspecificmode_pf7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_exttphrequester_pf0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_exttphrequester_pf1 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_exttphrequester_pf2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_exttphrequester_pf3 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_exttphrequester_pf4 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_exttphrequester_pf5 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_exttphrequester_pf6 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_exttphrequester_pf7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_intvecmode_pf0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_intvecmode_pf1 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_intvecmode_pf2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_intvecmode_pf3 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_intvecmode_pf4 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_intvecmode_pf5 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_intvecmode_pf6 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_intvecmode_pf7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_nxtptr_pf0 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_nxtptr_pf1 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_nxtptr_pf2 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_nxtptr_pf3 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_nxtptr_pf4 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_nxtptr_pf5 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_nxtptr_pf6 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_nxtptr_pf7 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_sttablelocation_pf0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_sttablelocation_pf1 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_sttablelocation_pf2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_sttablelocation_pf3 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_sttablelocation_pf4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_sttablelocation_pf5 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_sttablelocation_pf6 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_sttablelocation_pf7 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_sttablesize_pf0 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_sttablesize_pf1 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_sttablesize_pf2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_sttablesize_pf3 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_sttablesize_pf4 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_sttablesize_pf5 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_sttablesize_pf6 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tph_sttablesize_pf7 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_tphcap_enable == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_type0cap_nxtptr_pf0 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_type0cap_nxtptr_pf1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_type0cap_nxtptr_pf2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_type0cap_nxtptr_pf3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_type0cap_nxtptr_pf4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_type0cap_nxtptr_pf5 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_type0cap_nxtptr_pf6 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.exvf_type0cap_nxtptr_pf7 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.func_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.gate_clk_in_reset_dis == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.gate_radm_clk_dis == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.gpio_irq == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.intel_marker == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.irq_misc_ctrl == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.margining_ready == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.margining_software_ready == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.nonsriov_mode == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pcie_parity_bypass == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ack_n_fts == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_acs_cap_acs_at_block == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_acs_cap_acs_cap_hdr_reg_addr_byte2 == 24'd8389386
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_acs_cap_acs_cap_hdr_reg_addr_byte3 == 24'd8389387
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_acs_cap_acs_capalities_ctrl_reg_addr_byte0 == 24'd8389388
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_acs_cap_acs_capalities_ctrl_reg_addr_byte1 == 24'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_acs_cap_acs_direct_translated_p2p == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_acs_cap_acs_egress_ctrl_size == 8'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_acs_cap_acs_p2p_cpl_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_acs_cap_acs_p2p_egress_control == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_acs_cap_acs_p2p_req_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_acs_cap_acs_src_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_acs_cap_acs_usp_forwarding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_acs_cap_rsvdp_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_acs_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_acs_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_adv_err_int_msg_num == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_aer_cap_aer_ext_cap_hdr_off_addr_byte2 == 24'd8388866
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_aer_cap_aer_ext_cap_hdr_off_addr_byte3 == 24'd8388867
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_aer_cap_root_err_status_off_addr_byte0 == 24'd304
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_aer_cap_version == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_aer_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ari_acs_fun_grp_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ari_cap_ari_base_addr_byte2 == 24'd8388982
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ari_cap_ari_base_addr_byte3 == 24'd8388983
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ari_cap_cap_reg_addr_byte0 == 24'd8388984
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ari_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ari_device_number == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ari_mfvc_fun_grp_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ari_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ats_cap_ats_cap_hdr_reg_addr_byte2 == 24'd8389370
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ats_cap_ats_cap_hdr_reg_addr_byte3 == 24'd8389371
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ats_cap_ats_capabilities_ctrl_reg_addr_byte0 == 24'd8389372
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ats_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ats_capabilities_ctrl_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ats_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_auto_eq_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_auto_eq_disable_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_auto_lane_flip_ctrl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_aux_clk_freq == 10'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_aux_clk_freq_off_rsvdp_10 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_aux_curr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_bar0_mem_io == PF0_BAR0_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_bar0_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_bar0_type == PF0_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_bar1_mem_io == PF0_BAR1_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_bar1_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_bar1_type == PF0_BAR1_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_bar2_mem_io == PF0_BAR2_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_bar2_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_bar2_type == PF0_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_bar3_mem_io == PF0_BAR3_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_bar3_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_bar3_type == PF0_BAR3_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_bar4_mem_io == PF0_BAR4_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_bar4_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_bar4_type == PF0_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_bar5_mem_io == PF0_BAR5_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_bar5_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_bar5_type == PF0_BAR5_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_base_class_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_cap_id_nxt_ptr_reg_rsvdp_20 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_cap_pointer == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_cardbus_cis_pointer == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_common_clk_n_fts == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_con_status_reg_rsvdp_2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_con_status_reg_rsvdp_4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_config_limit == 10'd831
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_config_phy_tx_change == PF0_FULL_SWING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_config_tx_comp_rx == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_cross_link_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_cross_link_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_d1_support == PF0_D1_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_d2_support == PF0_D2_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_10 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_11 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_12 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_13 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_14 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_15 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_16 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_17 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_18 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_19 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_20 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_21 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_22 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_23 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_24 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_25 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_26 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_27 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_28 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_29 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_30 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_31 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_32 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_33 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_34 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_35 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_36 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_37 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_38 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_39 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_40 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_41 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_42 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_43 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_44 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_7 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_8 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_reserved_9 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dbi_ro_wr_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_default_target == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_device_capabilities_reg_rsvdp_12 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_device_capabilities_reg_rsvdp_16 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_device_capabilities_reg_rsvdp_29 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_direct_speed_change == PF0_AUTO_SPEED_CHG
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_disable_auto_ltr_clr_msg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_disable_fc_wd_timer == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_disable_scrambler_gen_3 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_disable_scrambler_gen_3_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dlink_cap_dlink_fea_ext_hdr_off_addr_byte2 == 24'd8389742
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dlink_cap_dlink_fea_ext_hdr_off_addr_byte3 == 24'd8389743
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dlink_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dlink_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dll_link_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsi == PF0_NOT_REQUIRED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_16g_tx_preset0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_16g_tx_preset1 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_16g_tx_preset10 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_16g_tx_preset11 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_16g_tx_preset12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_16g_tx_preset13 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_16g_tx_preset14 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_16g_tx_preset15 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_16g_tx_preset2 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_16g_tx_preset3 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_16g_tx_preset4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_16g_tx_preset5 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_16g_tx_preset6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_16g_tx_preset7 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_16g_tx_preset8 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_16g_tx_preset9 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_rx_preset_hint0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_rx_preset_hint1 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_rx_preset_hint10 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_rx_preset_hint11 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_rx_preset_hint12 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_rx_preset_hint13 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_rx_preset_hint14 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_rx_preset_hint15 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_rx_preset_hint2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_rx_preset_hint3 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_rx_preset_hint4 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_rx_preset_hint5 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_rx_preset_hint6 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_rx_preset_hint7 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_rx_preset_hint8 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_rx_preset_hint9 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_tx_preset0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_tx_preset1 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_tx_preset10 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_tx_preset11 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_tx_preset12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_tx_preset13 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_tx_preset14 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_tx_preset15 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_tx_preset2 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_tx_preset3 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_tx_preset4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_tx_preset5 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_tx_preset6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_tx_preset7 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_tx_preset8 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_dsp_tx_preset9 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_eidle_timer == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_eq_eieos_cnt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_eq_eieos_cnt_atg4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_eq_phase_2_3 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_eq_phase_2_3_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_eq_redo == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_eq_redo_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_exp_rom_bar_mask_reg_rsvdp_1 == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_exp_rom_base_addr_reg_rsvdp_1 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_fast_link_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_fast_training_seq == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen1_ei_inference == PF0_USE_RX_EIDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen2_ctrl_off_rsvdp_22 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_dc_balance_disable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_dc_balance_disable_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_dllp_xmt_delay_disable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_dllp_xmt_delay_disable_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_eq_control_off_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_eq_control_off_rsvdp_27_atg4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_eq_control_off_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_eq_control_off_rsvdp_7_atg4 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_eq_eval_2ms_disable == PF0_CONTINUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_eq_eval_2ms_disable_atg4 == PF0_CONTINUE_ATG4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_eq_fb_mode == PF0_FOM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_eq_fb_mode_atg4 == PF0_FOM_ATG4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_eq_fom_inc_initial_eval == PF0_IGNORE_INIT_FOM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_eq_fom_inc_initial_eval_atg4 == PF0_IGNORE_INIT_FOM_ATG4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_eq_invreq_eva_diff_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_eq_invreq_eva_diff_disable_atg4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_eq_phase23_exit_mode == PF0_NEXT_REC_SPEED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_eq_phase23_exit_mode_atg4 == PF0_NEXT_REC_SPEED_ATG4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_eq_pset_req_as_coef == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_eq_pset_req_as_coef_atg4 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_eq_pset_req_vec == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_eq_pset_req_vec_atg4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_equalization_disable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_equalization_disable_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_lower_rate_eq_redo_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_lower_rate_eq_redo_enable_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_related_off_rsvdp_1 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_related_off_rsvdp_14 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_related_off_rsvdp_14_atg4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_related_off_rsvdp_19 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_related_off_rsvdp_19_atg4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_related_off_rsvdp_1_atg4 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_related_off_rsvdp_26 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_related_off_rsvdp_26_atg4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_req_send_consec_eieos_for_pset_map == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_req_send_consec_eieos_for_pset_map_atg4 == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_zrxdc_noncompl == PF0_COMPLIANT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_gen3_zrxdc_noncompl_atg4 == PF0_COMPLIANT_ATG4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_global_inval_spprtd == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_header_type == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_int_pin == PF0_NO_INT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_invalidate_q_depth == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_lane_equalization_control01_reg_rsvdp_15 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_lane_equalization_control01_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_lane_equalization_control01_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_lane_equalization_control01_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_lane_equalization_control1011_reg_rsvdp_15 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_lane_equalization_control1011_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_lane_equalization_control1011_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_lane_equalization_control1011_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_lane_equalization_control1213_reg_rsvdp_15 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_lane_equalization_control1213_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_lane_equalization_control1213_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_lane_equalization_control1213_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_lane_equalization_control1415_reg_rsvdp_15 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_lane_equalization_control1415_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_lane_equalization_control1415_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_lane_equalization_control1415_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_lane_equalization_control23_reg_rsvdp_15 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_lane_equalization_control23_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_lane_equalization_control23_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_lane_equalization_control23_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_lane_equalization_control45_reg_rsvdp_15 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_lane_equalization_control45_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_lane_equalization_control45_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_lane_equalization_control45_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_lane_equalization_control67_reg_rsvdp_15 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_lane_equalization_control67_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_lane_equalization_control67_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_lane_equalization_control67_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_lane_equalization_control89_reg_rsvdp_15 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_lane_equalization_control89_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_lane_equalization_control89_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_lane_equalization_control89_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_link_capabilities_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_link_capable == PF0_CONN_X1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_link_control_link_status_reg_rsvdp_12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_link_control_link_status_reg_rsvdp_2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_link_control_link_status_reg_rsvdp_26 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_link_control_link_status_reg_rsvdp_9 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_link_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_link_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_loopback_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ltr_cap_ltr_cap_hdr_reg_addr_byte2 == 24'd8389414
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ltr_cap_ltr_cap_hdr_reg_addr_byte3 == 24'd8389415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ltr_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ltr_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_margin_cap_margin_ext_cap_hdr_reg_addr_byte2 == 24'd8389094
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_margin_cap_margin_ext_cap_hdr_reg_addr_byte3 == 24'd8389095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_margin_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_margin_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_mask_radm_1 == 16'd8200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_mask_radm_2 == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_mask_ur_ca_4_trgt1 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_max_func_num == PF0_ONE_FUNCTION
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_misc_control_1_off_rsvdp_6 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_misc_control_1_rsvdp_21 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte1 == 24'd8388689
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte2 == 24'd8388690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte3 == 24'd8388691
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_msi_cap_pci_msi_cap_id_next_ctrl_reg_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_msix_cap_msix_pba_offset_reg_addr_byte0 == 24'd8388792
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_msix_cap_msix_pba_offset_reg_addr_byte1 == 24'd8388793
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_msix_cap_msix_pba_offset_reg_addr_byte2 == 24'd8388794
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_msix_cap_msix_pba_offset_reg_addr_byte3 == 24'd8388795
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_msix_cap_msix_table_offset_reg_addr_byte0 == 24'd8388788
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_msix_cap_msix_table_offset_reg_addr_byte1 == 24'd8388789
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_msix_cap_msix_table_offset_reg_addr_byte2 == 24'd8388790
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_msix_cap_msix_table_offset_reg_addr_byte3 == 24'd8388791
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte1 == 24'd8388785
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte2 == 24'd8388786
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte3 == 24'd8388787
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte2 == 24'd10485938
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte3 == 24'd10485939
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_multi_func == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_no_soft_rst == PF0_INTERNALLY_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_num_of_lanes == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_p2p_err_rpt_ctrl == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_p2p_track_cpl_to_reg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_page_aligned_req == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pasid_cap_execute_permission_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pasid_cap_max_pasid_width == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pasid_cap_pasid_cap_cntrl_reg_addr_byte0 == 24'd8389424
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pasid_cap_pasid_cap_cntrl_reg_addr_byte1 == 24'd8389425
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pasid_cap_pasid_ext_hdr_reg_addr_byte2 == 24'd8389422
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pasid_cap_pasid_ext_hdr_reg_addr_byte3 == 24'd8389423
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pasid_cap_privileged_mode_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pasid_cap_rsvdp_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pasid_cap_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pasid_cap_rsvpd_13 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pasid_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pasid_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_msi_64_bit_addr_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_msi_cap_next_offset == 8'd112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_msi_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_msi_ext_data_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_msi_ext_data_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_msi_multiple_msg_cap == PF0_MSI_VEC_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_msi_multiple_msg_en == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_msix_bir == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_msix_cap_id_next_ctrl_reg_rsvdp_27 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_msix_cap_next_offset == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_msix_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_msix_enable_vfcomm_cs2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_msix_function_mask == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_msix_function_mask_vfcomm_cs2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_msix_pba == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_msix_pba_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_msix_table_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_msix_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_msix_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_pvm_support == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_type0_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_type0_bar0_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_type0_bar1_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_type0_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_type0_bar1_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_type0_bar1_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_type0_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_type0_bar2_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_type0_bar3_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_type0_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_type0_bar3_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_type0_bar3_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_type0_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_type0_bar4_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_type0_bar5_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_type0_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_type0_bar5_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_type0_bar5_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_type0_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pci_type0_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_active_state_link_pm_control == PF0_ASPM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_active_state_link_pm_support == PF0_NO_ASPM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_aspm_opt_compliance == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_attention_indicator == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_attention_indicator_button == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_aux_power_pm_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_clock_power_man == PF0_REFCLK_REMOVE_NOT_OK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_common_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_crs_sw_visibility == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_device_capabilities_reg_addr_byte0 == 24'd8388724
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_device_capabilities_reg_addr_byte1 == 24'd8388725
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_device_capabilities_reg_addr_byte3 == 24'd8388727
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_device_control_device_status_addr_byte1 == 24'd8388729
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_dll_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_dll_active_rep_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_electromech_interlock == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_en_clk_power_man == PF0_CLKREQ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_en_no_snoop == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_enter_compliance == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_ep_l0s_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_ep_l1_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_ext_tag_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_ext_tag_supp == PF0_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_extended_synch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_flr_cap == PF0_NOT_CAPABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_hot_plug_capable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_hot_plug_surprise == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_hw_auto_speed_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvd == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_initiate_flr == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_l0s_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_l1_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_link_auto_bw_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_link_auto_bw_status == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_link_bw_man_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_link_bw_man_status == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_link_bw_not_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_link_capabilities_reg_addr_byte0 == 24'd8388732
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_link_capabilities_reg_addr_byte1 == 24'd8388733
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_link_capabilities_reg_addr_byte2 == 24'd8388734
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_link_capabilities_reg_addr_byte3 == 24'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_link_control2_link_status2_reg_addr_byte0 == 24'd12583072
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_link_control_link_status_reg_addr_byte0 == 24'd4194432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_link_control_link_status_reg_addr_byte1 == 24'd12583041
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_link_control_link_status_reg_addr_byte3 == 24'd4194435
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_link_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_link_training == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_max_link_speed == PF0_MAX_2P5GTS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_max_link_width == PF0_X1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_max_payload_size == PF0_PAYLOAD_128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_max_read_req_size == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_mrl_sensor == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_nego_link_width == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_next_ptr == 8'd176
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_no_cmd_cpl_support == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte1 == 24'd8388721
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte3 == 24'd8388723
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_phantom_func_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_phantom_func_support == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_phy_slot_num == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_port_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_power_controller == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_power_indicator == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_rcb == PF0_RCB_64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_retrain_link == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_role_based_err_report == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_root_control_root_capabilities_reg_addr_byte2 == 24'd142
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_sel_deemphasis == PF0_MINUS_6DB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_slot_capabilities_reg_addr_byte0 == 24'd132
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_slot_capabilities_reg_addr_byte1 == 24'd133
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_slot_capabilities_reg_addr_byte2 == 24'd134
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_slot_capabilities_reg_addr_byte3 == 24'd135
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_slot_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_slot_power_limit_scale == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_slot_power_limit_value == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_surprise_down_err_rep_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_target_link_speed == PF0_TRGT_GEN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_cap_tx_margin == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_int_msg_num == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pcie_slot_imp == PF0_NOT_IMPLEMENTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pipe_loopback == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pipe_loopback_control_off_rsvdp_27 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pl16g_cap_pl16g_cap_off_20h_reg_addr_byte0 == 24'd468
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pl16g_cap_pl16g_cap_off_20h_reg_addr_byte1 == 24'd469
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pl16g_cap_pl16g_cap_off_20h_reg_addr_byte2 == 24'd470
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pl16g_cap_pl16g_cap_off_20h_reg_addr_byte3 == 24'd471
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pl16g_cap_pl16g_cap_off_24h_reg_addr_byte0 == 24'd472
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pl16g_cap_pl16g_cap_off_24h_reg_addr_byte1 == 24'd473
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pl16g_cap_pl16g_cap_off_24h_reg_addr_byte2 == 24'd474
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pl16g_cap_pl16g_cap_off_24h_reg_addr_byte3 == 24'd475
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pl16g_cap_pl16g_cap_off_28h_reg_addr_byte0 == 24'd476
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pl16g_cap_pl16g_cap_off_28h_reg_addr_byte1 == 24'd477
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pl16g_cap_pl16g_cap_off_28h_reg_addr_byte2 == 24'd478
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pl16g_cap_pl16g_cap_off_28h_reg_addr_byte3 == 24'd479
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pl16g_cap_pl16g_cap_off_2ch_reg_addr_byte0 == 24'd480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pl16g_cap_pl16g_cap_off_2ch_reg_addr_byte1 == 24'd481
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pl16g_cap_pl16g_cap_off_2ch_reg_addr_byte2 == 24'd482
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pl16g_cap_pl16g_cap_off_2ch_reg_addr_byte3 == 24'd483
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pl16g_cap_pl16g_ext_cap_hdr_reg_addr_byte2 == 24'd8389046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pl16g_cap_pl16g_ext_cap_hdr_reg_addr_byte3 == 24'd8389047
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pl16g_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pl16g_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pm_cap_cap_id_nxt_ptr_reg_addr_byte1 == 24'd8388673
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pm_cap_cap_id_nxt_ptr_reg_addr_byte2 == 24'd8388674
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pm_cap_cap_id_nxt_ptr_reg_addr_byte3 == 24'd8388675
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pm_cap_con_status_reg_addr_byte0 == 24'd8388676
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pm_next_pointer == 8'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pm_spec_ver == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pme_clk == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pme_support == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_link_ctrl_off_rsvdp_4 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_ack_f_aspm_ctrl_off_addr_byte1 == 24'd8390413
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_ack_f_aspm_ctrl_off_addr_byte2 == 24'd1806
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_aux_clk_freq_off_addr_byte0 == 24'd8391488
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_aux_clk_freq_off_addr_byte1 == 24'd8391489
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_filter_mask_2_off_addr_byte0 == 24'd8390432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_filter_mask_2_off_addr_byte1 == 24'd8390433
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_filter_mask_2_off_addr_byte2 == 24'd8390434
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_filter_mask_2_off_addr_byte3 == 24'd8390435
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_gen2_ctrl_off_addr_byte0 == 24'd8390668
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_gen2_ctrl_off_addr_byte1 == 24'd8390669
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_gen2_ctrl_off_addr_byte2 == 24'd4196366
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_gen3_eq_control_off_addr_byte0 == 24'd8390824
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_gen3_eq_control_off_addr_byte1 == 24'd8390825
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_gen3_eq_control_off_addr_byte2 == 24'd8390826
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_gen3_eq_control_off_addr_byte3 == 24'd8390827
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_gen3_eq_control_off_atg4_addr_byte0 == 24'd8390824
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_gen3_eq_control_off_atg4_addr_byte1 == 24'd8390825
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_gen3_eq_control_off_atg4_addr_byte2 == 24'd8390826
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_gen3_eq_control_off_atg4_addr_byte3 == 24'd8390827
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_gen3_eq_local_fs_lf_off_addr_byte1 == 24'd8390825
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_gen3_related_off_addr_byte0 == 24'd8390800
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_gen3_related_off_addr_byte1 == 24'd8390801
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_gen3_related_off_addr_byte2 == 24'd8390802
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_gen3_related_off_addr_byte3 == 24'd8390803
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_gen3_related_off_atg4_addr_byte0 == 24'd8390800
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_gen3_related_off_atg4_addr_byte1 == 24'd8390801
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_gen3_related_off_atg4_addr_byte2 == 24'd8390802
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_gen3_related_off_atg4_addr_byte3 == 24'd8390803
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_misc_control_1_off_addr_byte0 == 24'd2236
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_misc_control_1_off_addr_byte1 == 24'd2237
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_misc_control_1_off_addr_byte2 == 24'd2238
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_pipe_loopback_control_off_addr_byte3 == 24'd2235
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_port_force_off_addr_byte0 == 24'd8390408
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_port_link_ctrl_off_addr_byte0 == 24'd1808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_port_link_ctrl_off_addr_byte2 == 24'd8390418
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_queue_status_off_addr_byte2 == 24'd8390462
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_queue_status_off_addr_byte3 == 24'd8390463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_symbol_timer_filter_1_off_addr_byte0 == 24'd8390428
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_symbol_timer_filter_1_off_addr_byte1 == 24'd8390429
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_symbol_timer_filter_1_off_addr_byte2 == 24'd8390430
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_symbol_timer_filter_1_off_addr_byte3 == 24'd8390431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_timer_ctrl_max_func_num_off_addr_byte0 == 24'd8390424
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_vc0_cpl_rx_q_ctrl_off_addr_byte0 == 24'd8390480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_vc0_cpl_rx_q_ctrl_off_addr_byte1 == 24'd8390481
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_vc0_cpl_rx_q_ctrl_off_addr_byte2 == 24'd8390482
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_vc0_cpl_rx_q_ctrl_off_addr_byte3 == 24'd8390483
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_vc0_np_rx_q_ctrl_off_addr_byte0 == 24'd8390476
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_vc0_np_rx_q_ctrl_off_addr_byte1 == 24'd8390477
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_vc0_np_rx_q_ctrl_off_addr_byte2 == 24'd8390478
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_vc0_p_rx_q_ctrl_off_addr_byte0 == 24'd8390472
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_vc0_p_rx_q_ctrl_off_addr_byte1 == 24'd8390473
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_port_logic_vc0_p_rx_q_ctrl_off_addr_byte2 == 24'd8390474
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_power_state == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_pre_det_lane == PF0_DET_ALL_LANES
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_program_interface == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte2 == 24'd8389398
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte3 == 24'd8389399
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_prs_ext_cap_prs_req_capacity_reg_addr_byte0 == 24'd8389404
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_prs_ext_cap_prs_req_capacity_reg_addr_byte1 == 24'd8389405
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_prs_ext_cap_prs_req_capacity_reg_addr_byte2 == 24'd8389406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_prs_ext_cap_prs_req_capacity_reg_addr_byte3 == 24'd8389407
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_prs_ext_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_prs_ext_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_prs_outstanding_capacity == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_cap_off_reserved3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_cap_off_reserved3_dup == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_cap_ptm_cap_off_addr_byte0 == 24'd8389756
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_cap_ptm_cap_off_addr_byte0_dup == 24'd8389756
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_cap_ptm_ext_cap_hdr_off_addr_byte2 == 24'd8389754
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_cap_ptm_ext_cap_hdr_off_addr_byte3 == 24'd8389755
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_capable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_capable_dup == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_capi_ptm_req_cap_hdr_off_dbi_addr_byte2 == 24'd8389766
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_capi_ptm_req_cap_hdr_off_dbi_addr_byte3 == 24'd8389767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_capi_ptm_req_control_off_dbi_addr_byte0 == 24'd8389772
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_capi_ptm_req_control_off_dbi_addr_byte1 == 24'd8389773
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_capi_ptm_req_latency_reg_sel_off_gen1_dbi_addr_byte0 == 24'd8389864
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_capi_ptm_req_latency_reg_sel_off_gen2_dbi_addr_byte0 == 24'd8389864
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_capi_ptm_req_latency_reg_sel_off_gen3_dbi_addr_byte0 == 24'd8389864
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_capi_ptm_req_latency_reg_sel_off_gen4_dbi_addr_byte0 == 24'd8389864
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_capi_ptm_req_rx_latency_off_gen1_dbi_addr_byte0 == 24'd8389844
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_capi_ptm_req_rx_latency_off_gen1_dbi_addr_byte1 == 24'd8389845
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_capi_ptm_req_rx_latency_off_gen2_dbi_addr_byte0 == 24'd8389844
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_capi_ptm_req_rx_latency_off_gen2_dbi_addr_byte1 == 24'd8389845
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_capi_ptm_req_rx_latency_off_gen3_dbi_addr_byte0 == 24'd8389844
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_capi_ptm_req_rx_latency_off_gen3_dbi_addr_byte1 == 24'd8389845
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_capi_ptm_req_rx_latency_off_gen4_dbi_addr_byte0 == 24'd8389844
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_capi_ptm_req_rx_latency_off_gen4_dbi_addr_byte1 == 24'd8389845
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_capi_ptm_req_tx_latency_off_gen1_dbi_addr_byte0 == 24'd8389840
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_capi_ptm_req_tx_latency_off_gen1_dbi_addr_byte1 == 24'd8389841
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_capi_ptm_req_tx_latency_off_gen2_dbi_addr_byte0 == 24'd8389840
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_capi_ptm_req_tx_latency_off_gen2_dbi_addr_byte1 == 24'd8389841
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_capi_ptm_req_tx_latency_off_gen3_dbi_addr_byte0 == 24'd8389840
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_capi_ptm_req_tx_latency_off_gen3_dbi_addr_byte1 == 24'd8389841
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_capi_ptm_req_tx_latency_off_gen4_dbi_addr_byte0 == 24'd8389840
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_capi_ptm_req_tx_latency_off_gen4_dbi_addr_byte1 == 24'd8389841
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_control_off_ptm_req_auto_update_enabled == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_control_off_ptm_req_fast_timers == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_control_off_ptm_req_long_timer == 8'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_control_off_ptm_req_start_update == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_control_off_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_ext_cap_next_offs == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_ext_cap_ver == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_latency_reg_sel_gen1 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_latency_reg_sel_gen2 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_latency_reg_sel_gen3 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_latency_reg_sel_gen4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_latency_reg_sel_off_gen1_reserved4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_latency_reg_sel_off_gen2_reserved4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_latency_reg_sel_off_gen3_reserved4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_latency_reg_sel_off_gen4_reserved4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_rx_latency_gen1 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_rx_latency_gen2 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_rx_latency_gen3 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_rx_latency_gen4 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_rx_latency_off_gen1_reserved12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_rx_latency_off_gen2_reserved12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_rx_latency_off_gen3_reserved12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_rx_latency_off_gen4_reserved12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_tx_latency_gen1 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_tx_latency_gen2 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_tx_latency_gen3 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_tx_latency_gen4 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_tx_latency_off_gen1_reserved12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_tx_latency_off_gen2_reserved12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_tx_latency_off_gen3_reserved12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_req_tx_latency_off_gen4_reserved12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_res_capable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_res_capable_dup == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_root_capable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ptm_root_capable_dup == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_queue_status_off_rsvdp_29 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ras_des_cap_event_counter_ctrl_reg_addr_byte0 == 24'd828
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ras_des_cap_event_counter_ctrl_reg_g5_addr_byte3 == 24'd8389439
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ras_des_cap_event_counter_ctrl_reg_g6_addr_byte3 == 24'd8389439
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ras_des_cap_event_counter_ctrl_reg_g7_addr_byte3 == 24'd8389439
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ras_des_cap_force_detect_lane == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ras_des_cap_force_detect_lane_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ras_des_cap_ras_des_hdr_reg_addr_byte2 == 24'd822
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ras_des_cap_ras_des_hdr_reg_addr_byte3 == 24'd823
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ras_des_cap_sd_control1_reg_addr_byte0 == 24'd8389588
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ras_des_cap_sd_control1_reg_addr_byte1 == 24'd8389589
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ras_des_cap_sd_control1_reg_addr_byte2 == 24'd8389590
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ras_des_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ras_des_event_counter_en == 8'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ras_des_event_counter_event_select_g5 == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ras_des_event_counter_event_select_g6 == 8'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ras_des_event_counter_event_select_g7 == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_ras_des_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_rate_shadow_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_rate_shadow_sel_atg4 == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved10 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved250 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved4 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved6 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved8 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved9 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_10_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_11_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_12_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_13_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_14_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_15_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_16_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_17_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_18_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_19_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_20_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_21_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_22_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_23_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_24_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_25_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_26_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_27_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_28_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_29_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_30_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_31_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_32_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_33_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_34_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_35_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_36_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_37_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_38_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_39_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_40_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_41_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_42_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_43_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_44_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_8_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reserved_9_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_reset_assert == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_revision_id == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_rom_bar_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_rom_bar_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_root_control_root_capabilities_reg_rsvdp_17 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_root_err_status_off_rsvdp_7 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_rp_exp_rom_bar_mask_reg_rp_rom_rsvdp_1 == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_rp_rom_bar_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_rp_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_rxeq_ph01_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_rxeq_ph01_en_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_rxeq_rgrdless_rxts == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_rxeq_rgrdless_rxts_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_rxstatus_value == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_scramble_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sel_deemphasis == PF0_MINUS_6DB_CTL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_shadow_sriov_vf_stride_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_simplified_replay_timer == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_skp_int_val == 11'd640
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sn_cap_ser_num_reg_dw_1_addr_byte0 == 24'd8388968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sn_cap_ser_num_reg_dw_1_addr_byte1 == 24'd8388969
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sn_cap_ser_num_reg_dw_1_addr_byte2 == 24'd8388970
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sn_cap_ser_num_reg_dw_1_addr_byte3 == 24'd8388971
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sn_cap_ser_num_reg_dw_2_addr_byte0 == 24'd8388972
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sn_cap_ser_num_reg_dw_2_addr_byte1 == 24'd8388973
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sn_cap_ser_num_reg_dw_2_addr_byte2 == 24'd8388974
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sn_cap_ser_num_reg_dw_2_addr_byte3 == 24'd8388975
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sn_cap_sn_base_addr_byte2 == 24'd8388966
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sn_cap_sn_base_addr_byte3 == 24'd8388967
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sn_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sn_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sn_ser_num_reg_1_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sn_ser_num_reg_2_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_spcie_cap_lane_equalization_control01_reg_addr_byte0 == 24'd400
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_spcie_cap_lane_equalization_control01_reg_addr_byte1 == 24'd8389009
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_spcie_cap_lane_equalization_control01_reg_addr_byte2 == 24'd402
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_spcie_cap_lane_equalization_control01_reg_addr_byte3 == 24'd8389011
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_spcie_cap_lane_equalization_control1011_reg_addr_byte0 == 24'd420
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_spcie_cap_lane_equalization_control1011_reg_addr_byte1 == 24'd8389029
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_spcie_cap_lane_equalization_control1011_reg_addr_byte2 == 24'd422
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_spcie_cap_lane_equalization_control1011_reg_addr_byte3 == 24'd8389031
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_spcie_cap_lane_equalization_control1213_reg_addr_byte0 == 24'd424
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_spcie_cap_lane_equalization_control1213_reg_addr_byte1 == 24'd8389033
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_spcie_cap_lane_equalization_control1213_reg_addr_byte2 == 24'd426
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_spcie_cap_lane_equalization_control1213_reg_addr_byte3 == 24'd8389035
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_spcie_cap_lane_equalization_control1415_reg_addr_byte0 == 24'd428
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_spcie_cap_lane_equalization_control1415_reg_addr_byte1 == 24'd8389037
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_spcie_cap_lane_equalization_control1415_reg_addr_byte2 == 24'd430
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_spcie_cap_lane_equalization_control1415_reg_addr_byte3 == 24'd8389039
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_spcie_cap_lane_equalization_control23_reg_addr_byte0 == 24'd404
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_spcie_cap_lane_equalization_control23_reg_addr_byte1 == 24'd8389013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_spcie_cap_lane_equalization_control23_reg_addr_byte2 == 24'd406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_spcie_cap_lane_equalization_control23_reg_addr_byte3 == 24'd8389015
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_spcie_cap_lane_equalization_control45_reg_addr_byte0 == 24'd408
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_spcie_cap_lane_equalization_control45_reg_addr_byte1 == 24'd8389017
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_spcie_cap_lane_equalization_control45_reg_addr_byte2 == 24'd410
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_spcie_cap_lane_equalization_control45_reg_addr_byte3 == 24'd8389019
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_spcie_cap_lane_equalization_control67_reg_addr_byte0 == 24'd412
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_spcie_cap_lane_equalization_control67_reg_addr_byte1 == 24'd8389021
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_spcie_cap_lane_equalization_control67_reg_addr_byte2 == 24'd414
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_spcie_cap_lane_equalization_control67_reg_addr_byte3 == 24'd8389023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_spcie_cap_lane_equalization_control89_reg_addr_byte0 == 24'd416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_spcie_cap_lane_equalization_control89_reg_addr_byte1 == 24'd8389025
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_spcie_cap_lane_equalization_control89_reg_addr_byte2 == 24'd418
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_spcie_cap_lane_equalization_control89_reg_addr_byte3 == 24'd8389027
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_spcie_cap_spcie_cap_header_reg_addr_byte2 == 24'd8388998
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_spcie_cap_spcie_cap_header_reg_addr_byte3 == 24'd8388999
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_spcie_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_spcie_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_shadow_sriov_initial_vfs_addr_byte0 == 24'd10486328
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_shadow_sriov_initial_vfs_addr_byte1 == 24'd10486329
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_shadow_sriov_vf_offset_position_addr_byte0 == 24'd10486336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_shadow_sriov_vf_offset_position_addr_byte1 == 24'd10486337
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_shadow_sriov_vf_offset_position_addr_byte2 == 24'd10486338
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_shadow_sriov_vf_offset_position_addr_byte3 == 24'd10486339
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_shadow_vf_bar0_reg_addr_byte0 == 24'd2097744
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_shadow_vf_bar0_reg_addr_byte1 == 24'd2097745
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_shadow_vf_bar0_reg_addr_byte2 == 24'd2097746
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_shadow_vf_bar0_reg_addr_byte3 == 24'd2097747
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_shadow_vf_bar1_reg_addr_byte0 == 24'd2097748
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_shadow_vf_bar1_reg_addr_byte1 == 24'd2097749
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_shadow_vf_bar1_reg_addr_byte2 == 24'd2097750
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_shadow_vf_bar1_reg_addr_byte3 == 24'd2097751
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_shadow_vf_bar2_reg_addr_byte0 == 24'd2097752
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_shadow_vf_bar2_reg_addr_byte1 == 24'd2097753
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_shadow_vf_bar2_reg_addr_byte2 == 24'd2097754
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_shadow_vf_bar2_reg_addr_byte3 == 24'd2097755
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_shadow_vf_bar3_reg_addr_byte0 == 24'd2097756
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_shadow_vf_bar3_reg_addr_byte1 == 24'd2097757
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_shadow_vf_bar3_reg_addr_byte2 == 24'd2097758
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_shadow_vf_bar3_reg_addr_byte3 == 24'd2097759
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_shadow_vf_bar4_reg_addr_byte0 == 24'd2097760
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_shadow_vf_bar4_reg_addr_byte1 == 24'd2097761
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_shadow_vf_bar4_reg_addr_byte2 == 24'd2097762
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_shadow_vf_bar4_reg_addr_byte3 == 24'd2097763
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_shadow_vf_bar5_reg_addr_byte0 == 24'd2097764
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_shadow_vf_bar5_reg_addr_byte1 == 24'd2097765
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_shadow_vf_bar5_reg_addr_byte2 == 24'd2097766
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_shadow_vf_bar5_reg_addr_byte3 == 24'd2097767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_sriov_bar1_enable_reg_addr_byte0 == 24'd2097748
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_sriov_bar3_enable_reg_addr_byte0 == 24'd2097756
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_sriov_bar5_enable_reg_addr_byte0 == 24'd2097764
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_sriov_base_reg_addr_byte2 == 24'd8389166
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_sriov_base_reg_addr_byte3 == 24'd8389167
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_sriov_initial_vfs_addr_byte0 == 24'd8389176
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_sriov_initial_vfs_addr_byte1 == 24'd8389177
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_sriov_vf_offset_position_addr_byte0 == 24'd8389184
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_sriov_vf_offset_position_addr_byte1 == 24'd8389185
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_sriov_vf_offset_position_addr_byte2 == 24'd8389186
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_sriov_vf_offset_position_addr_byte3 == 24'd8389187
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_sup_page_sizes_reg_addr_byte0 == 24'd8389192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_sup_page_sizes_reg_addr_byte1 == 24'd8389193
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_sup_page_sizes_reg_addr_byte2 == 24'd8389194
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_sup_page_sizes_reg_addr_byte3 == 24'd8389195
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_vf_bar0_reg_addr_byte0 == 24'd592
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_vf_bar1_reg_addr_byte0 == 24'd596
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_vf_bar2_reg_addr_byte0 == 24'd600
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_vf_bar3_reg_addr_byte0 == 24'd604
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_vf_bar4_reg_addr_byte0 == 24'd608
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_vf_bar5_reg_addr_byte0 == 24'd612
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_vf_device_id_reg_addr_byte2 == 24'd8389190
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_cap_vf_device_id_reg_addr_byte3 == 24'd8389191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_initial_vfs_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_initial_vfs_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_sup_page_size == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_vf_bar0_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_vf_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_vf_bar0_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_vf_bar0_type == PF0_SRIOV_VF_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_vf_bar1_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_vf_bar1_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_vf_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_vf_bar1_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_vf_bar1_type == PF0_SRIOV_VF_BAR1_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_vf_bar2_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_vf_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_vf_bar2_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_vf_bar2_type == PF0_SRIOV_VF_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_vf_bar3_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_vf_bar3_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_vf_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_vf_bar3_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_vf_bar3_type == PF0_SRIOV_VF_BAR3_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_vf_bar4_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_vf_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_vf_bar4_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_vf_bar4_type == PF0_SRIOV_VF_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_vf_bar5_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_vf_bar5_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_vf_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_vf_bar5_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_vf_bar5_type == PF0_SRIOV_VF_BAR5_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_vf_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_vf_offset_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_vf_offset_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_sriov_vf_stride_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_subclass_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_subsys_dev_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_subsys_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_target_above_config_limit == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_timer_mod_flow_control == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_timer_mod_flow_control_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_tlp_bypass_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_tph_cap_tph_ext_cap_hdr_reg_addr_byte2 == 24'd8389230
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_tph_cap_tph_ext_cap_hdr_reg_addr_byte3 == 24'd8389231
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_tph_cap_tph_req_cap_reg_addr_byte0 == 24'd8389232
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_tph_cap_tph_req_cap_reg_addr_byte1 == 24'd8389233
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_tph_cap_tph_req_cap_reg_addr_byte2 == 24'd8389234
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_tph_cap_tph_req_cap_reg_addr_byte3 == 24'd8389235
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte0 == 24'd10486384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte1 == 24'd10486385
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte2 == 24'd10486386
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte3 == 24'd10486387
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_tph_req_cap_int_vec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_tph_req_cap_int_vec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_tph_req_cap_reg_rsvdp_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_tph_req_cap_reg_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_tph_req_cap_reg_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_tph_req_cap_reg_vfcomm_cs2_rsvdp_11_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_tph_req_cap_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_tph_req_cap_reg_vfcomm_cs2_rsvdp_3_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_tph_req_cap_st_table_loc_0 == PF0_NOT_IN_TPH_STRUCT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_tph_req_cap_st_table_loc_0_vfcomm_cs2 == PF0_NOT_IN_TPH_STRUCT_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_tph_req_cap_st_table_loc_1 == PF0_NOT_IN_MSIX_TABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_tph_req_cap_st_table_loc_1_vfcomm_cs2 == PF0_NOT_IN_MSIX_TABLE_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_tph_req_cap_st_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_tph_req_cap_st_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_tph_req_cap_ver == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_tph_req_device_spec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_tph_req_device_spec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_tph_req_extended_tph == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_tph_req_extended_tph_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_tph_req_next_ptr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_tph_req_no_st_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_tph_req_no_st_mode_vfcomm_cs2 == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_bar0_mask_reg_addr_byte0 == 24'd2097168
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_bar0_mask_reg_addr_byte1 == 24'd2097169
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_bar0_mask_reg_addr_byte2 == 24'd2097170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_bar0_mask_reg_addr_byte3 == 24'd2097171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_bar0_reg_addr_byte0 == 24'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_bar1_enable_reg_addr_byte0 == 24'd2097172
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_bar1_mask_reg_addr_byte0 == 24'd2097172
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_bar1_mask_reg_addr_byte1 == 24'd2097173
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_bar1_mask_reg_addr_byte2 == 24'd2097174
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_bar1_mask_reg_addr_byte3 == 24'd2097175
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_bar1_reg_addr_byte0 == 24'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_bar2_mask_reg_addr_byte0 == 24'd2097176
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_bar2_mask_reg_addr_byte1 == 24'd2097177
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_bar2_mask_reg_addr_byte2 == 24'd2097178
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_bar2_mask_reg_addr_byte3 == 24'd2097179
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_bar2_reg_addr_byte0 == 24'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_bar3_enable_reg_addr_byte0 == 24'd2097180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_bar3_mask_reg_addr_byte0 == 24'd2097180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_bar3_mask_reg_addr_byte1 == 24'd2097181
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_bar3_mask_reg_addr_byte2 == 24'd2097182
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_bar3_mask_reg_addr_byte3 == 24'd2097183
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_bar3_reg_addr_byte0 == 24'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_bar4_mask_reg_addr_byte0 == 24'd2097184
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_bar4_mask_reg_addr_byte1 == 24'd2097185
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_bar4_mask_reg_addr_byte2 == 24'd2097186
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_bar4_mask_reg_addr_byte3 == 24'd2097187
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_bar4_reg_addr_byte0 == 24'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_bar5_enable_reg_addr_byte0 == 24'd2097188
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_bar5_mask_reg_addr_byte0 == 24'd2097188
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_bar5_mask_reg_addr_byte1 == 24'd2097189
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_bar5_mask_reg_addr_byte2 == 24'd2097190
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_bar5_mask_reg_addr_byte3 == 24'd2097191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_bar5_reg_addr_byte0 == 24'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_bist_header_type_latency_cache_line_size_reg_addr_byte2 == 24'd8388622
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_cardbus_cis_ptr_reg_addr_byte0 == 24'd8388648
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_cardbus_cis_ptr_reg_addr_byte1 == 24'd8388649
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_cardbus_cis_ptr_reg_addr_byte2 == 24'd8388650
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_cardbus_cis_ptr_reg_addr_byte3 == 24'd8388651
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_class_code_revision_id_addr_byte0 == 24'd8388616
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_class_code_revision_id_addr_byte1 == 24'd8388617
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_class_code_revision_id_addr_byte2 == 24'd8388618
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_class_code_revision_id_addr_byte3 == 24'd8388619
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_device_id_vendor_id_reg_addr_byte0 == 24'd8388608
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_device_id_vendor_id_reg_addr_byte1 == 24'd8388609
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_device_id_vendor_id_reg_addr_byte2 == 24'd8388610
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_device_id_vendor_id_reg_addr_byte3 == 24'd8388611
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_exp_rom_bar_mask_reg_addr_byte0 == 24'd2097200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_exp_rom_bar_mask_reg_addr_byte1 == 24'd2097201
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_exp_rom_bar_mask_reg_addr_byte2 == 24'd2097202
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_exp_rom_bar_mask_reg_addr_byte3 == 24'd2097203
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_exp_rom_base_addr_reg_addr_byte0 == 24'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_max_latency_min_grant_interrupt_pin_interrupt_line_reg_addr_byte1 == 24'd8388669
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_pci_cap_ptr_reg_addr_byte0 == 24'd8388660
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_rp_exp_rom_bar_mask_reg_addr_byte0 == 24'd2097208
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_rp_exp_rom_bar_mask_reg_addr_byte1 == 24'd2097209
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_rp_exp_rom_bar_mask_reg_addr_byte2 == 24'd2097210
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_rp_exp_rom_bar_mask_reg_addr_byte3 == 24'd2097211
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte0 == 24'd8388652
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte1 == 24'd8388653
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte2 == 24'd8388654
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte3 == 24'd8388655
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_16g_tx_preset0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_16g_tx_preset1 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_16g_tx_preset10 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_16g_tx_preset11 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_16g_tx_preset12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_16g_tx_preset13 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_16g_tx_preset14 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_16g_tx_preset15 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_16g_tx_preset2 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_16g_tx_preset3 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_16g_tx_preset4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_16g_tx_preset5 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_16g_tx_preset6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_16g_tx_preset7 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_16g_tx_preset8 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_16g_tx_preset9 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_rx_preset_hint0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_rx_preset_hint1 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_rx_preset_hint10 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_rx_preset_hint11 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_rx_preset_hint12 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_rx_preset_hint13 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_rx_preset_hint14 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_rx_preset_hint15 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_rx_preset_hint2 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_rx_preset_hint3 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_rx_preset_hint4 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_rx_preset_hint5 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_rx_preset_hint6 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_rx_preset_hint7 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_rx_preset_hint8 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_rx_preset_hint9 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_send_8gt_eq_ts2_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_send_8gt_eq_ts2_disable_atg4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_tx_preset0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_tx_preset1 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_tx_preset10 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_tx_preset11 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_tx_preset12 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_tx_preset13 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_tx_preset14 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_tx_preset15 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_tx_preset2 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_tx_preset3 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_tx_preset4 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_tx_preset5 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_tx_preset6 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_tx_preset7 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_tx_preset8 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_usp_tx_preset9 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_vc0_cpl_data_credit == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_vc0_cpl_data_scale == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_vc0_cpl_hdr_scale == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_vc0_cpl_header_credit == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_vc0_cpl_tlp_q_mode == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_vc0_np_data_credit == 12'd392
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_vc0_np_header_credit == 8'd49
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_vc0_np_tlp_q_mode == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_vc0_p_data_credit == 12'd1456
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_vc0_p_header_credit == 8'd49
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_vc0_p_tlp_q_mode == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_vc_cap_vc_base_addr_byte2 == 24'd8388938
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_vc_cap_vc_base_addr_byte3 == 24'd8388939
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_vc_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_vc_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_vendor_specific_dllp_req == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_vf_bar0_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_vf_bar1_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_vf_bar2_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_vf_bar3_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_vf_bar4_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_vf_bar5_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_vsecras_cap_rasdp_ext_hdr_off_addr_byte2 == 24'd8389686
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_vsecras_cap_rasdp_ext_hdr_off_addr_byte3 == 24'd8389687
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_vsecras_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf0_vsecras_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_acs_cap_acs_at_block == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_acs_cap_acs_cap_hdr_reg_addr_byte2 == 24'd8393482
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_acs_cap_acs_cap_hdr_reg_addr_byte3 == 24'd8393483
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_acs_cap_acs_capalities_ctrl_reg_addr_byte0 == 24'd8393484
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_acs_cap_acs_capalities_ctrl_reg_addr_byte1 == 24'd4877
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_acs_cap_acs_direct_translated_p2p == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_acs_cap_acs_egress_ctrl_size == 8'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_acs_cap_acs_p2p_cpl_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_acs_cap_acs_p2p_egress_control == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_acs_cap_acs_p2p_req_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_acs_cap_acs_src_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_acs_cap_acs_usp_forwarding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_acs_cap_rsvdp_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_acs_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_acs_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_aer_cap_aer_ext_cap_hdr_off_addr_byte2 == 24'd8392962
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_aer_cap_aer_ext_cap_hdr_off_addr_byte3 == 24'd8392963
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_aer_cap_version == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_aer_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_ari_cap_ari_base_addr_byte2 == 24'd8393078
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_ari_cap_ari_base_addr_byte3 == 24'd8393079
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_ari_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_ari_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_ats_cap_ats_cap_hdr_reg_addr_byte2 == 24'd8393466
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_ats_cap_ats_cap_hdr_reg_addr_byte3 == 24'd8393467
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_ats_cap_ats_capabilities_ctrl_reg_addr_byte0 == 24'd8393468
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_ats_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_ats_capabilities_ctrl_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_ats_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_aux_curr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_bar0_mem_io == PF1_BAR0_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_bar0_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_bar0_type == PF1_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_bar1_mem_io == PF1_BAR1_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_bar1_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_bar1_type == PF1_BAR1_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_bar2_mem_io == PF1_BAR2_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_bar2_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_bar2_type == PF1_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_bar3_mem_io == PF1_BAR3_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_bar3_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_bar3_type == PF1_BAR3_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_bar4_mem_io == PF1_BAR4_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_bar4_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_bar4_type == PF1_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_bar5_mem_io == PF1_BAR5_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_bar5_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_bar5_type == PF1_BAR5_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_base_class_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_cap_id_nxt_ptr_reg_rsvdp_20 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_cap_pointer == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_cardbus_cis_pointer == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_con_status_reg_rsvdp_2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_con_status_reg_rsvdp_4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_d1_support == PF1_D1_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_d2_support == PF1_D2_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_10 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_11 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_12 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_13 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_14 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_15 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_16 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_17 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_18 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_19 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_20 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_21 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_22 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_23 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_24 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_25 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_26 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_27 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_28 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_29 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_30 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_31 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_32 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_33 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_34 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_35 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_36 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_37 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_38 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_39 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_40 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_41 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_42 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_43 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_44 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_45 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_46 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_47 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_48 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_49 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_50 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_51 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_52 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_53 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_54 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_55 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_56 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_57 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_58 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_59 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_6 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_60 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_61 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_62 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_63 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_64 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_65 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_7 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_8 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dbi_reserved_9 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_device_capabilities_reg_rsvdp_12 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_device_capabilities_reg_rsvdp_16 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_device_capabilities_reg_rsvdp_29 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_dsi == PF1_NOT_REQUIRED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_exp_rom_bar_mask_reg_rsvdp_1 == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_exp_rom_base_addr_reg_rsvdp_1 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_global_inval_spprtd == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_header_type == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_int_pin == PF1_NO_INT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_invalidate_q_depth == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_link_capabilities_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_link_control_link_status_reg_rsvdp_12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_link_control_link_status_reg_rsvdp_2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_link_control_link_status_reg_rsvdp_26 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_link_control_link_status_reg_rsvdp_9 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte1 == 24'd8392785
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte2 == 24'd8392786
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte3 == 24'd8392787
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_msi_cap_pci_msi_cap_id_next_ctrl_reg_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_msix_cap_msix_pba_offset_reg_addr_byte0 == 24'd8392888
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_msix_cap_msix_pba_offset_reg_addr_byte1 == 24'd8392889
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_msix_cap_msix_pba_offset_reg_addr_byte2 == 24'd8392890
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_msix_cap_msix_pba_offset_reg_addr_byte3 == 24'd8392891
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_msix_cap_msix_table_offset_reg_addr_byte0 == 24'd8392884
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_msix_cap_msix_table_offset_reg_addr_byte1 == 24'd8392885
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_msix_cap_msix_table_offset_reg_addr_byte2 == 24'd8392886
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_msix_cap_msix_table_offset_reg_addr_byte3 == 24'd8392887
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte1 == 24'd8392881
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte2 == 24'd8392882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte3 == 24'd8392883
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte2 == 24'd10490034
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte3 == 24'd10490035
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_multi_func == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_no_soft_rst == PF1_INTERNALLY_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_page_aligned_req == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pasid_cap_execute_permission_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pasid_cap_max_pasid_width == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pasid_cap_pasid_cap_cntrl_reg_addr_byte0 == 24'd8393520
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pasid_cap_pasid_cap_cntrl_reg_addr_byte1 == 24'd8393521
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pasid_cap_pasid_ext_hdr_reg_addr_byte2 == 24'd8393518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pasid_cap_pasid_ext_hdr_reg_addr_byte3 == 24'd8393519
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pasid_cap_privileged_mode_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pasid_cap_rsvdp_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pasid_cap_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pasid_cap_rsvpd_13 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pasid_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pasid_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_msi_64_bit_addr_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_msi_cap_next_offset == 8'd112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_msi_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_msi_ext_data_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_msi_ext_data_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_msi_multiple_msg_cap == PF1_MSI_VEC_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_msi_multiple_msg_en == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_msix_bir == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_msix_cap_id_next_ctrl_reg_rsvdp_27 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_msix_cap_next_offset == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_msix_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_msix_enable_vfcomm_cs2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_msix_function_mask == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_msix_function_mask_vfcomm_cs2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_msix_pba == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_msix_pba_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_msix_table_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_msix_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_msix_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_pvm_support == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_type0_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_type0_bar0_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_type0_bar1_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_type0_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_type0_bar1_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_type0_bar1_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_type0_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_type0_bar2_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_type0_bar3_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_type0_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_type0_bar3_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_type0_bar3_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_type0_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_type0_bar4_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_type0_bar5_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_type0_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_type0_bar5_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_type0_bar5_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_type0_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pci_type0_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_active_state_link_pm_control == PF1_ASPM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_active_state_link_pm_support == PF1_NO_ASPM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_aspm_opt_compliance == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_aux_power_pm_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_clock_power_man == PF1_REFCLK_REMOVE_NOT_OK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_common_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_device_capabilities_reg_addr_byte0 == 24'd8392820
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_device_capabilities_reg_addr_byte1 == 24'd8392821
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_device_capabilities_reg_addr_byte3 == 24'd8392823
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_device_control_device_status_addr_byte1 == 24'd8392825
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_dll_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_dll_active_rep_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_en_clk_power_man == PF1_CLKREQ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_en_no_snoop == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_enter_compliance == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_ep_l0s_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_ep_l1_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_ext_tag_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_ext_tag_supp == PF1_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_extended_synch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_flr_cap == PF1_NOT_CAPABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_hw_auto_speed_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvd == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_initiate_flr == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_l0s_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_l1_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_link_auto_bw_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_link_auto_bw_status == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_link_bw_man_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_link_bw_man_status == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_link_bw_not_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_link_capabilities_reg_addr_byte0 == 24'd8392828
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_link_capabilities_reg_addr_byte1 == 24'd8392829
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_link_capabilities_reg_addr_byte2 == 24'd8392830
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_link_capabilities_reg_addr_byte3 == 24'd4223
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_link_control2_link_status2_reg_addr_byte0 == 24'd12587168
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_link_control_link_status_reg_addr_byte0 == 24'd4198528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_link_control_link_status_reg_addr_byte1 == 24'd12587137
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_link_control_link_status_reg_addr_byte3 == 24'd4198531
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_link_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_link_training == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_max_link_speed == PF1_MAX_2P5GTS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_max_link_width == PF1_X1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_max_payload_size == PF1_PAYLOAD_128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_max_read_req_size == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_nego_link_width == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_next_ptr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte1 == 24'd8392817
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte3 == 24'd8392819
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_phantom_func_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_phantom_func_support == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_port_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_rcb == PF1_RCB_64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_retrain_link == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_role_based_err_report == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_sel_deemphasis == PF1_MINUS_6DB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_slot_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_surprise_down_err_rep_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_target_link_speed == PF1_TRGT_GEN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_cap_tx_margin == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_int_msg_num == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pcie_slot_imp == PF1_NOT_IMPLEMENTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pf0_ari_device_number == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pf0_dbi_ro_wr_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pf0_default_target == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pf0_disable_auto_ltr_clr_msg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pf0_mask_ur_ca_4_trgt1 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pf0_misc_control_1_off_rsvdp_6 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pf0_port_logic_misc_control_1_off_addr_byte0 == 24'd2236
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pf0_simplified_replay_timer == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pf0_tlp_bypass_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pm_cap_cap_id_nxt_ptr_reg_addr_byte1 == 24'd8392769
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pm_cap_cap_id_nxt_ptr_reg_addr_byte2 == 24'd8392770
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pm_cap_cap_id_nxt_ptr_reg_addr_byte3 == 24'd8392771
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pm_cap_con_status_reg_addr_byte0 == 24'd8392772
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pm_next_pointer == 8'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pm_spec_ver == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pme_clk == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_pme_support == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_power_state == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_program_interface == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte2 == 24'd8393494
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte3 == 24'd8393495
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_prs_ext_cap_prs_req_capacity_reg_addr_byte0 == 24'd8393500
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_prs_ext_cap_prs_req_capacity_reg_addr_byte1 == 24'd8393501
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_prs_ext_cap_prs_req_capacity_reg_addr_byte2 == 24'd8393502
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_prs_ext_cap_prs_req_capacity_reg_addr_byte3 == 24'd8393503
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_prs_ext_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_prs_ext_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_prs_outstanding_capacity == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_ras_des_cap_event_counter_ctrl_reg_addr_byte0 == 24'd4924
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_ras_des_cap_event_counter_ctrl_reg_g5_addr_byte3 == 24'd8393535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_ras_des_cap_event_counter_ctrl_reg_g6_addr_byte3 == 24'd8393535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_ras_des_cap_event_counter_ctrl_reg_g7_addr_byte3 == 24'd8393535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_ras_des_cap_force_detect_lane == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_ras_des_cap_force_detect_lane_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_ras_des_cap_ras_des_hdr_reg_addr_byte2 == 24'd4918
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_ras_des_cap_ras_des_hdr_reg_addr_byte3 == 24'd4919
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_ras_des_cap_sd_control1_reg_addr_byte0 == 24'd8393684
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_ras_des_cap_sd_control1_reg_addr_byte1 == 24'd8393685
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_ras_des_cap_sd_control1_reg_addr_byte2 == 24'd8393686
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_ras_des_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_ras_des_event_counter_en == 8'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_ras_des_event_counter_event_select_g5 == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_ras_des_event_counter_event_select_g6 == 8'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_ras_des_event_counter_event_select_g7 == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_ras_des_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_10_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_11_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_12_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_13_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_14_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_15_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_16_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_17_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_18_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_19_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_20_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_21_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_22_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_23_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_24_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_25_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_26_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_27_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_28_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_29_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_30_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_31_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_32_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_33_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_34_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_35_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_36_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_37_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_38_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_39_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_40_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_41_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_42_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_43_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_44_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_45_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_46_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_47_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_48_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_49_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_50_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_51_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_52_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_53_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_54_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_55_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_56_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_57_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_58_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_59_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_60_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_61_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_62_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_63_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_64_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_65_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_7_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_8_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_reserved_9_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_revision_id == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_rom_bar_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_rom_bar_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_shadow_sriov_vf_stride_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sn_cap_ser_num_reg_dw_1_addr_byte0 == 24'd8393064
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sn_cap_ser_num_reg_dw_1_addr_byte1 == 24'd8393065
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sn_cap_ser_num_reg_dw_1_addr_byte2 == 24'd8393066
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sn_cap_ser_num_reg_dw_1_addr_byte3 == 24'd8393067
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sn_cap_ser_num_reg_dw_2_addr_byte0 == 24'd8393068
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sn_cap_ser_num_reg_dw_2_addr_byte1 == 24'd8393069
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sn_cap_ser_num_reg_dw_2_addr_byte2 == 24'd8393070
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sn_cap_ser_num_reg_dw_2_addr_byte3 == 24'd8393071
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sn_cap_sn_base_addr_byte2 == 24'd8393062
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sn_cap_sn_base_addr_byte3 == 24'd8393063
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sn_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sn_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sn_ser_num_reg_1_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sn_ser_num_reg_2_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_shadow_sriov_initial_vfs_addr_byte0 == 24'd10490424
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_shadow_sriov_initial_vfs_addr_byte1 == 24'd10490425
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_shadow_sriov_vf_offset_position_addr_byte0 == 24'd10490432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_shadow_sriov_vf_offset_position_addr_byte1 == 24'd10490433
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_shadow_sriov_vf_offset_position_addr_byte2 == 24'd10490434
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_shadow_sriov_vf_offset_position_addr_byte3 == 24'd10490435
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_shadow_vf_bar0_reg_addr_byte0 == 24'd2101840
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_shadow_vf_bar0_reg_addr_byte1 == 24'd2101841
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_shadow_vf_bar0_reg_addr_byte2 == 24'd2101842
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_shadow_vf_bar0_reg_addr_byte3 == 24'd2101843
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_shadow_vf_bar1_reg_addr_byte0 == 24'd2101844
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_shadow_vf_bar1_reg_addr_byte1 == 24'd2101845
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_shadow_vf_bar1_reg_addr_byte2 == 24'd2101846
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_shadow_vf_bar1_reg_addr_byte3 == 24'd2101847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_shadow_vf_bar2_reg_addr_byte0 == 24'd2101848
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_shadow_vf_bar2_reg_addr_byte1 == 24'd2101849
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_shadow_vf_bar2_reg_addr_byte2 == 24'd2101850
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_shadow_vf_bar2_reg_addr_byte3 == 24'd2101851
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_shadow_vf_bar3_reg_addr_byte0 == 24'd2101852
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_shadow_vf_bar3_reg_addr_byte1 == 24'd2101853
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_shadow_vf_bar3_reg_addr_byte2 == 24'd2101854
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_shadow_vf_bar3_reg_addr_byte3 == 24'd2101855
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_shadow_vf_bar4_reg_addr_byte0 == 24'd2101856
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_shadow_vf_bar4_reg_addr_byte1 == 24'd2101857
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_shadow_vf_bar4_reg_addr_byte2 == 24'd2101858
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_shadow_vf_bar4_reg_addr_byte3 == 24'd2101859
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_shadow_vf_bar5_reg_addr_byte0 == 24'd2101860
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_shadow_vf_bar5_reg_addr_byte1 == 24'd2101861
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_shadow_vf_bar5_reg_addr_byte2 == 24'd2101862
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_shadow_vf_bar5_reg_addr_byte3 == 24'd2101863
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_sriov_bar1_enable_reg_addr_byte0 == 24'd2101844
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_sriov_bar3_enable_reg_addr_byte0 == 24'd2101852
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_sriov_bar5_enable_reg_addr_byte0 == 24'd2101860
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_sriov_base_reg_addr_byte2 == 24'd8393262
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_sriov_base_reg_addr_byte3 == 24'd8393263
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_sriov_initial_vfs_addr_byte0 == 24'd8393272
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_sriov_initial_vfs_addr_byte1 == 24'd8393273
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_sriov_vf_offset_position_addr_byte0 == 24'd8393280
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_sriov_vf_offset_position_addr_byte1 == 24'd8393281
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_sriov_vf_offset_position_addr_byte2 == 24'd8393282
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_sriov_vf_offset_position_addr_byte3 == 24'd8393283
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_sup_page_sizes_reg_addr_byte0 == 24'd8393288
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_sup_page_sizes_reg_addr_byte1 == 24'd8393289
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_sup_page_sizes_reg_addr_byte2 == 24'd8393290
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_sup_page_sizes_reg_addr_byte3 == 24'd8393291
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_vf_bar0_reg_addr_byte0 == 24'd4688
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_vf_bar1_reg_addr_byte0 == 24'd4692
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_vf_bar2_reg_addr_byte0 == 24'd4696
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_vf_bar3_reg_addr_byte0 == 24'd4700
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_vf_bar4_reg_addr_byte0 == 24'd4704
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_vf_bar5_reg_addr_byte0 == 24'd4708
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_vf_device_id_reg_addr_byte2 == 24'd8393286
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_cap_vf_device_id_reg_addr_byte3 == 24'd8393287
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_initial_vfs_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_initial_vfs_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_sup_page_size == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_vf_bar0_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_vf_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_vf_bar0_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_vf_bar0_type == PF1_SRIOV_VF_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_vf_bar1_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_vf_bar1_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_vf_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_vf_bar1_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_vf_bar1_type == PF1_SRIOV_VF_BAR1_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_vf_bar2_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_vf_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_vf_bar2_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_vf_bar2_type == PF1_SRIOV_VF_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_vf_bar3_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_vf_bar3_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_vf_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_vf_bar3_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_vf_bar3_type == PF1_SRIOV_VF_BAR3_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_vf_bar4_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_vf_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_vf_bar4_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_vf_bar4_type == PF1_SRIOV_VF_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_vf_bar5_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_vf_bar5_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_vf_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_vf_bar5_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_vf_bar5_type == PF1_SRIOV_VF_BAR5_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_vf_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_vf_offset_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_vf_offset_position_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_sriov_vf_stride_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_subclass_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_subsys_dev_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_subsys_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_tph_cap_tph_ext_cap_hdr_reg_addr_byte2 == 24'd8393326
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_tph_cap_tph_ext_cap_hdr_reg_addr_byte3 == 24'd8393327
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_tph_cap_tph_req_cap_reg_addr_byte0 == 24'd8393328
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_tph_cap_tph_req_cap_reg_addr_byte1 == 24'd8393329
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_tph_cap_tph_req_cap_reg_addr_byte2 == 24'd8393330
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_tph_cap_tph_req_cap_reg_addr_byte3 == 24'd8393331
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte0 == 24'd10490480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte1 == 24'd10490481
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte2 == 24'd10490482
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte3 == 24'd10490483
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_tph_req_cap_int_vec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_tph_req_cap_int_vec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_tph_req_cap_reg_rsvdp_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_tph_req_cap_reg_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_tph_req_cap_reg_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_tph_req_cap_reg_vfcomm_cs2_rsvdp_11_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_tph_req_cap_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_tph_req_cap_reg_vfcomm_cs2_rsvdp_3_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_tph_req_cap_st_table_loc_0 == PF1_NOT_IN_TPH_STRUCT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_tph_req_cap_st_table_loc_0_vfcomm_cs2 == PF1_NOT_IN_TPH_STRUCT_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_tph_req_cap_st_table_loc_1 == PF1_NOT_IN_MSIX_TABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_tph_req_cap_st_table_loc_1_vfcomm_cs2 == PF1_NOT_IN_MSIX_TABLE_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_tph_req_cap_st_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_tph_req_cap_st_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_tph_req_cap_ver == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_tph_req_device_spec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_tph_req_device_spec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_tph_req_extended_tph == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_tph_req_extended_tph_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_tph_req_next_ptr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_tph_req_no_st_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_tph_req_no_st_mode_vfcomm_cs2 == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_bar0_mask_reg_addr_byte0 == 24'd2101264
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_bar0_mask_reg_addr_byte1 == 24'd2101265
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_bar0_mask_reg_addr_byte2 == 24'd2101266
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_bar0_mask_reg_addr_byte3 == 24'd2101267
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_bar0_reg_addr_byte0 == 24'd4112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_bar1_enable_reg_addr_byte0 == 24'd2101268
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_bar1_mask_reg_addr_byte0 == 24'd2101268
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_bar1_mask_reg_addr_byte1 == 24'd2101269
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_bar1_mask_reg_addr_byte2 == 24'd2101270
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_bar1_mask_reg_addr_byte3 == 24'd2101271
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_bar1_reg_addr_byte0 == 24'd4116
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_bar2_mask_reg_addr_byte0 == 24'd2101272
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_bar2_mask_reg_addr_byte1 == 24'd2101273
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_bar2_mask_reg_addr_byte2 == 24'd2101274
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_bar2_mask_reg_addr_byte3 == 24'd2101275
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_bar2_reg_addr_byte0 == 24'd4120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_bar3_enable_reg_addr_byte0 == 24'd2101276
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_bar3_mask_reg_addr_byte0 == 24'd2101276
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_bar3_mask_reg_addr_byte1 == 24'd2101277
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_bar3_mask_reg_addr_byte2 == 24'd2101278
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_bar3_mask_reg_addr_byte3 == 24'd2101279
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_bar3_reg_addr_byte0 == 24'd4124
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_bar4_mask_reg_addr_byte0 == 24'd2101280
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_bar4_mask_reg_addr_byte1 == 24'd2101281
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_bar4_mask_reg_addr_byte2 == 24'd2101282
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_bar4_mask_reg_addr_byte3 == 24'd2101283
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_bar4_reg_addr_byte0 == 24'd4128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_bar5_enable_reg_addr_byte0 == 24'd2101284
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_bar5_mask_reg_addr_byte0 == 24'd2101284
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_bar5_mask_reg_addr_byte1 == 24'd2101285
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_bar5_mask_reg_addr_byte2 == 24'd2101286
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_bar5_mask_reg_addr_byte3 == 24'd2101287
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_bar5_reg_addr_byte0 == 24'd4132
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_bist_header_type_latency_cache_line_size_reg_addr_byte2 == 24'd8392718
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_cardbus_cis_ptr_reg_addr_byte0 == 24'd8392744
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_cardbus_cis_ptr_reg_addr_byte1 == 24'd8392745
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_cardbus_cis_ptr_reg_addr_byte2 == 24'd8392746
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_cardbus_cis_ptr_reg_addr_byte3 == 24'd8392747
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_class_code_revision_id_addr_byte0 == 24'd8392712
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_class_code_revision_id_addr_byte1 == 24'd8392713
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_class_code_revision_id_addr_byte2 == 24'd8392714
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_class_code_revision_id_addr_byte3 == 24'd8392715
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_device_id_vendor_id_reg_addr_byte0 == 24'd8392704
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_device_id_vendor_id_reg_addr_byte1 == 24'd8392705
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_device_id_vendor_id_reg_addr_byte2 == 24'd8392706
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_device_id_vendor_id_reg_addr_byte3 == 24'd8392707
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_exp_rom_bar_mask_reg_addr_byte0 == 24'd2101296
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_exp_rom_bar_mask_reg_addr_byte1 == 24'd2101297
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_exp_rom_bar_mask_reg_addr_byte2 == 24'd2101298
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_exp_rom_bar_mask_reg_addr_byte3 == 24'd2101299
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_exp_rom_base_addr_reg_addr_byte0 == 24'd4144
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_max_latency_min_grant_interrupt_pin_interrupt_line_reg_addr_byte1 == 24'd8392765
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_pci_cap_ptr_reg_addr_byte0 == 24'd8392756
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte0 == 24'd8392748
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte1 == 24'd8392749
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte2 == 24'd8392750
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte3 == 24'd8392751
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_vf_bar0_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_vf_bar1_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_vf_bar2_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_vf_bar3_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_vf_bar4_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_vf_bar5_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_vsecras_cap_rasdp_ext_hdr_off_addr_byte2 == 24'd8393782
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_vsecras_cap_rasdp_ext_hdr_off_addr_byte3 == 24'd8393783
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_vsecras_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf1_vsecras_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_acs_cap_acs_at_block == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_acs_cap_acs_cap_hdr_reg_addr_byte2 == 24'd8397578
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_acs_cap_acs_cap_hdr_reg_addr_byte3 == 24'd8397579
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_acs_cap_acs_capalities_ctrl_reg_addr_byte0 == 24'd8397580
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_acs_cap_acs_capalities_ctrl_reg_addr_byte1 == 24'd8973
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_acs_cap_acs_direct_translated_p2p == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_acs_cap_acs_egress_ctrl_size == 8'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_acs_cap_acs_p2p_cpl_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_acs_cap_acs_p2p_egress_control == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_acs_cap_acs_p2p_req_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_acs_cap_acs_src_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_acs_cap_acs_usp_forwarding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_acs_cap_rsvdp_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_acs_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_acs_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_aer_cap_aer_ext_cap_hdr_off_addr_byte2 == 24'd8397058
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_aer_cap_aer_ext_cap_hdr_off_addr_byte3 == 24'd8397059
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_aer_cap_version == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_aer_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_ari_cap_ari_base_addr_byte2 == 24'd8397174
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_ari_cap_ari_base_addr_byte3 == 24'd8397175
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_ari_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_ari_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_ats_cap_ats_cap_hdr_reg_addr_byte2 == 24'd8397562
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_ats_cap_ats_cap_hdr_reg_addr_byte3 == 24'd8397563
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_ats_cap_ats_capabilities_ctrl_reg_addr_byte0 == 24'd8397564
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_ats_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_ats_capabilities_ctrl_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_ats_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_aux_curr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_bar0_mem_io == PF2_BAR0_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_bar0_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_bar0_type == PF2_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_bar1_mem_io == PF2_BAR1_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_bar1_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_bar1_type == PF2_BAR1_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_bar2_mem_io == PF2_BAR2_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_bar2_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_bar2_type == PF2_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_bar3_mem_io == PF2_BAR3_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_bar3_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_bar3_type == PF2_BAR3_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_bar4_mem_io == PF2_BAR4_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_bar4_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_bar4_type == PF2_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_bar5_mem_io == PF2_BAR5_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_bar5_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_bar5_type == PF2_BAR5_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_base_class_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_cap_id_nxt_ptr_reg_rsvdp_20 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_cap_pointer == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_cardbus_cis_pointer == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_con_status_reg_rsvdp_2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_con_status_reg_rsvdp_4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_d1_support == PF2_D1_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_d2_support == PF2_D2_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_10 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_11 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_12 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_13 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_14 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_15 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_16 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_17 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_18 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_19 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_20 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_21 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_22 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_23 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_24 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_25 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_26 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_27 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_28 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_29 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_30 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_31 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_32 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_33 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_34 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_35 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_36 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_37 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_38 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_39 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_40 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_41 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_42 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_43 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_44 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_45 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_46 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_47 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_48 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_49 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_50 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_51 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_52 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_53 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_54 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_55 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_56 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_57 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_58 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_59 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_6 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_60 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_61 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_62 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_63 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_64 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_65 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_7 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_8 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dbi_reserved_9 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_device_capabilities_reg_rsvdp_12 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_device_capabilities_reg_rsvdp_16 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_device_capabilities_reg_rsvdp_29 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_dsi == PF2_NOT_REQUIRED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_exp_rom_bar_mask_reg_rsvdp_1 == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_exp_rom_base_addr_reg_rsvdp_1 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_global_inval_spprtd == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_header_type == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_int_pin == PF2_NO_INT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_invalidate_q_depth == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_link_capabilities_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_link_control_link_status_reg_rsvdp_12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_link_control_link_status_reg_rsvdp_2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_link_control_link_status_reg_rsvdp_26 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_link_control_link_status_reg_rsvdp_9 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte1 == 24'd8396881
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte2 == 24'd8396882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte3 == 24'd8396883
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_msi_cap_pci_msi_cap_id_next_ctrl_reg_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_msix_cap_msix_pba_offset_reg_addr_byte0 == 24'd8396984
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_msix_cap_msix_pba_offset_reg_addr_byte1 == 24'd8396985
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_msix_cap_msix_pba_offset_reg_addr_byte2 == 24'd8396986
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_msix_cap_msix_pba_offset_reg_addr_byte3 == 24'd8396987
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_msix_cap_msix_table_offset_reg_addr_byte0 == 24'd8396980
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_msix_cap_msix_table_offset_reg_addr_byte1 == 24'd8396981
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_msix_cap_msix_table_offset_reg_addr_byte2 == 24'd8396982
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_msix_cap_msix_table_offset_reg_addr_byte3 == 24'd8396983
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte1 == 24'd8396977
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte2 == 24'd8396978
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte3 == 24'd8396979
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte2 == 24'd10494130
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte3 == 24'd10494131
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_multi_func == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_no_soft_rst == PF2_INTERNALLY_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_page_aligned_req == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pasid_cap_execute_permission_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pasid_cap_max_pasid_width == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pasid_cap_pasid_cap_cntrl_reg_addr_byte0 == 24'd8397616
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pasid_cap_pasid_cap_cntrl_reg_addr_byte1 == 24'd8397617
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pasid_cap_pasid_ext_hdr_reg_addr_byte2 == 24'd8397614
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pasid_cap_pasid_ext_hdr_reg_addr_byte3 == 24'd8397615
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pasid_cap_privileged_mode_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pasid_cap_rsvdp_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pasid_cap_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pasid_cap_rsvpd_13 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pasid_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pasid_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_msi_64_bit_addr_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_msi_cap_next_offset == 8'd112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_msi_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_msi_ext_data_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_msi_ext_data_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_msi_multiple_msg_cap == PF2_MSI_VEC_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_msi_multiple_msg_en == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_msix_bir == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_msix_cap_id_next_ctrl_reg_rsvdp_27 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_msix_cap_next_offset == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_msix_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_msix_enable_vfcomm_cs2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_msix_function_mask == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_msix_function_mask_vfcomm_cs2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_msix_pba == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_msix_pba_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_msix_table_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_msix_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_msix_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_pvm_support == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_type0_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_type0_bar0_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_type0_bar1_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_type0_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_type0_bar1_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_type0_bar1_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_type0_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_type0_bar2_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_type0_bar3_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_type0_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_type0_bar3_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_type0_bar3_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_type0_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_type0_bar4_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_type0_bar5_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_type0_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_type0_bar5_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_type0_bar5_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_type0_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pci_type0_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_active_state_link_pm_control == PF2_ASPM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_active_state_link_pm_support == PF2_NO_ASPM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_aspm_opt_compliance == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_aux_power_pm_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_clock_power_man == PF2_REFCLK_REMOVE_NOT_OK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_common_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_device_capabilities_reg_addr_byte0 == 24'd8396916
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_device_capabilities_reg_addr_byte1 == 24'd8396917
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_device_capabilities_reg_addr_byte3 == 24'd8396919
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_device_control_device_status_addr_byte1 == 24'd8396921
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_dll_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_dll_active_rep_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_en_clk_power_man == PF2_CLKREQ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_en_no_snoop == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_enter_compliance == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_ep_l0s_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_ep_l1_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_ext_tag_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_ext_tag_supp == PF2_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_extended_synch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_flr_cap == PF2_NOT_CAPABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_hw_auto_speed_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvd == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_initiate_flr == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_l0s_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_l1_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_link_auto_bw_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_link_auto_bw_status == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_link_bw_man_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_link_bw_man_status == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_link_bw_not_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_link_capabilities_reg_addr_byte0 == 24'd8396924
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_link_capabilities_reg_addr_byte1 == 24'd8396925
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_link_capabilities_reg_addr_byte2 == 24'd8396926
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_link_capabilities_reg_addr_byte3 == 24'd8319
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_link_control2_link_status2_reg_addr_byte0 == 24'd12591264
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_link_control_link_status_reg_addr_byte0 == 24'd4202624
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_link_control_link_status_reg_addr_byte1 == 24'd12591233
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_link_control_link_status_reg_addr_byte3 == 24'd4202627
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_link_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_link_training == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_max_link_speed == PF2_MAX_2P5GTS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_max_link_width == PF2_X1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_max_payload_size == PF2_PAYLOAD_128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_max_read_req_size == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_nego_link_width == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_next_ptr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte1 == 24'd8396913
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte3 == 24'd8396915
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_phantom_func_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_phantom_func_support == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_port_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_rcb == PF2_RCB_64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_retrain_link == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_role_based_err_report == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_sel_deemphasis == PF2_MINUS_6DB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_slot_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_surprise_down_err_rep_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_target_link_speed == PF2_TRGT_GEN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_cap_tx_margin == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_int_msg_num == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pcie_slot_imp == PF2_NOT_IMPLEMENTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pf0_ari_device_number == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pf0_dbi_ro_wr_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pf0_default_target == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pf0_disable_auto_ltr_clr_msg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pf0_mask_ur_ca_4_trgt1 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pf0_misc_control_1_off_rsvdp_6 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pf0_port_logic_misc_control_1_off_addr_byte0 == 24'd2236
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pf0_simplified_replay_timer == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pf0_tlp_bypass_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pm_cap_cap_id_nxt_ptr_reg_addr_byte1 == 24'd8396865
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pm_cap_cap_id_nxt_ptr_reg_addr_byte2 == 24'd8396866
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pm_cap_cap_id_nxt_ptr_reg_addr_byte3 == 24'd8396867
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pm_cap_con_status_reg_addr_byte0 == 24'd8396868
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pm_next_pointer == 8'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pm_spec_ver == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pme_clk == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_pme_support == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_power_state == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_program_interface == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte2 == 24'd8982
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte3 == 24'd8983
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_prs_ext_cap_prs_req_capacity_reg_addr_byte0 == 24'd8397596
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_prs_ext_cap_prs_req_capacity_reg_addr_byte1 == 24'd8397597
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_prs_ext_cap_prs_req_capacity_reg_addr_byte2 == 24'd8397598
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_prs_ext_cap_prs_req_capacity_reg_addr_byte3 == 24'd8397599
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_prs_ext_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_prs_ext_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_prs_outstanding_capacity == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_ras_des_cap_event_counter_ctrl_reg_addr_byte0 == 24'd9020
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_ras_des_cap_event_counter_ctrl_reg_g5_addr_byte3 == 24'd8397631
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_ras_des_cap_event_counter_ctrl_reg_g6_addr_byte3 == 24'd8397631
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_ras_des_cap_event_counter_ctrl_reg_g7_addr_byte3 == 24'd8397631
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_ras_des_cap_force_detect_lane == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_ras_des_cap_force_detect_lane_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_ras_des_cap_ras_des_hdr_reg_addr_byte2 == 24'd8397622
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_ras_des_cap_ras_des_hdr_reg_addr_byte3 == 24'd8397623
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_ras_des_cap_sd_control1_reg_addr_byte0 == 24'd8397780
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_ras_des_cap_sd_control1_reg_addr_byte1 == 24'd8397781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_ras_des_cap_sd_control1_reg_addr_byte2 == 24'd8397782
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_ras_des_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_ras_des_event_counter_en == 8'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_ras_des_event_counter_event_select_g5 == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_ras_des_event_counter_event_select_g6 == 8'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_ras_des_event_counter_event_select_g7 == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_ras_des_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_10_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_11_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_12_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_13_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_14_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_15_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_16_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_17_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_18_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_19_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_20_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_21_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_22_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_23_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_24_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_25_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_26_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_27_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_28_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_29_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_30_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_31_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_32_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_33_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_34_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_35_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_36_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_37_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_38_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_39_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_40_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_41_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_42_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_43_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_44_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_45_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_46_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_47_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_48_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_49_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_50_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_51_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_52_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_53_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_54_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_55_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_56_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_57_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_58_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_59_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_60_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_61_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_62_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_63_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_64_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_65_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_7_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_8_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_reserved_9_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_revision_id == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_rom_bar_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_rom_bar_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_shadow_sriov_vf_stride_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sn_cap_ser_num_reg_dw_1_addr_byte0 == 24'd8397160
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sn_cap_ser_num_reg_dw_1_addr_byte1 == 24'd8397161
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sn_cap_ser_num_reg_dw_1_addr_byte2 == 24'd8397162
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sn_cap_ser_num_reg_dw_1_addr_byte3 == 24'd8397163
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sn_cap_ser_num_reg_dw_2_addr_byte0 == 24'd8397164
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sn_cap_ser_num_reg_dw_2_addr_byte1 == 24'd8397165
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sn_cap_ser_num_reg_dw_2_addr_byte2 == 24'd8397166
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sn_cap_ser_num_reg_dw_2_addr_byte3 == 24'd8397167
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sn_cap_sn_base_addr_byte2 == 24'd8397158
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sn_cap_sn_base_addr_byte3 == 24'd8397159
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sn_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sn_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sn_ser_num_reg_1_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sn_ser_num_reg_2_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_shadow_sriov_initial_vfs_addr_byte0 == 24'd10494520
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_shadow_sriov_initial_vfs_addr_byte1 == 24'd10494521
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_shadow_sriov_vf_offset_position_addr_byte0 == 24'd10494528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_shadow_sriov_vf_offset_position_addr_byte1 == 24'd10494529
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_shadow_sriov_vf_offset_position_addr_byte2 == 24'd10494530
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_shadow_sriov_vf_offset_position_addr_byte3 == 24'd10494531
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_shadow_vf_bar0_reg_addr_byte0 == 24'd2105936
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_shadow_vf_bar0_reg_addr_byte1 == 24'd2105937
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_shadow_vf_bar0_reg_addr_byte2 == 24'd2105938
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_shadow_vf_bar0_reg_addr_byte3 == 24'd2105939
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_shadow_vf_bar1_reg_addr_byte0 == 24'd2105940
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_shadow_vf_bar1_reg_addr_byte1 == 24'd2105941
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_shadow_vf_bar1_reg_addr_byte2 == 24'd2105942
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_shadow_vf_bar1_reg_addr_byte3 == 24'd2105943
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_shadow_vf_bar2_reg_addr_byte0 == 24'd2105944
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_shadow_vf_bar2_reg_addr_byte1 == 24'd2105945
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_shadow_vf_bar2_reg_addr_byte2 == 24'd2105946
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_shadow_vf_bar2_reg_addr_byte3 == 24'd2105947
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_shadow_vf_bar3_reg_addr_byte0 == 24'd2105948
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_shadow_vf_bar3_reg_addr_byte1 == 24'd2105949
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_shadow_vf_bar3_reg_addr_byte2 == 24'd2105950
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_shadow_vf_bar3_reg_addr_byte3 == 24'd2105951
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_shadow_vf_bar4_reg_addr_byte0 == 24'd2105952
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_shadow_vf_bar4_reg_addr_byte1 == 24'd2105953
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_shadow_vf_bar4_reg_addr_byte2 == 24'd2105954
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_shadow_vf_bar4_reg_addr_byte3 == 24'd2105955
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_shadow_vf_bar5_reg_addr_byte0 == 24'd2105956
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_shadow_vf_bar5_reg_addr_byte1 == 24'd2105957
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_shadow_vf_bar5_reg_addr_byte2 == 24'd2105958
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_shadow_vf_bar5_reg_addr_byte3 == 24'd2105959
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_sriov_bar1_enable_reg_addr_byte0 == 24'd2105940
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_sriov_bar3_enable_reg_addr_byte0 == 24'd2105948
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_sriov_bar5_enable_reg_addr_byte0 == 24'd2105956
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_sriov_base_reg_addr_byte2 == 24'd8397358
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_sriov_base_reg_addr_byte3 == 24'd8397359
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_sriov_initial_vfs_addr_byte0 == 24'd8397368
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_sriov_initial_vfs_addr_byte1 == 24'd8397369
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_sriov_vf_offset_position_addr_byte0 == 24'd8397376
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_sriov_vf_offset_position_addr_byte1 == 24'd8397377
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_sriov_vf_offset_position_addr_byte2 == 24'd8397378
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_sriov_vf_offset_position_addr_byte3 == 24'd8397379
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_sup_page_sizes_reg_addr_byte0 == 24'd8397384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_sup_page_sizes_reg_addr_byte1 == 24'd8397385
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_sup_page_sizes_reg_addr_byte2 == 24'd8397386
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_sup_page_sizes_reg_addr_byte3 == 24'd8397387
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_vf_bar0_reg_addr_byte0 == 24'd8784
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_vf_bar1_reg_addr_byte0 == 24'd8788
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_vf_bar2_reg_addr_byte0 == 24'd8792
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_vf_bar3_reg_addr_byte0 == 24'd8796
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_vf_bar4_reg_addr_byte0 == 24'd8800
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_vf_bar5_reg_addr_byte0 == 24'd8804
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_vf_device_id_reg_addr_byte2 == 24'd8397382
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_cap_vf_device_id_reg_addr_byte3 == 24'd8397383
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_initial_vfs_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_initial_vfs_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_sup_page_size == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_vf_bar0_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_vf_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_vf_bar0_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_vf_bar0_type == PF2_SRIOV_VF_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_vf_bar1_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_vf_bar1_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_vf_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_vf_bar1_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_vf_bar1_type == PF2_SRIOV_VF_BAR1_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_vf_bar2_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_vf_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_vf_bar2_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_vf_bar2_type == PF2_SRIOV_VF_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_vf_bar3_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_vf_bar3_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_vf_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_vf_bar3_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_vf_bar3_type == PF2_SRIOV_VF_BAR3_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_vf_bar4_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_vf_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_vf_bar4_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_vf_bar4_type == PF2_SRIOV_VF_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_vf_bar5_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_vf_bar5_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_vf_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_vf_bar5_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_vf_bar5_type == PF2_SRIOV_VF_BAR5_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_vf_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_vf_offset_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_vf_offset_position_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_sriov_vf_stride_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_subclass_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_subsys_dev_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_subsys_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_tph_cap_tph_ext_cap_hdr_reg_addr_byte2 == 24'd8397422
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_tph_cap_tph_ext_cap_hdr_reg_addr_byte3 == 24'd8397423
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_tph_cap_tph_req_cap_reg_addr_byte0 == 24'd8397424
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_tph_cap_tph_req_cap_reg_addr_byte1 == 24'd8397425
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_tph_cap_tph_req_cap_reg_addr_byte2 == 24'd8397426
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_tph_cap_tph_req_cap_reg_addr_byte3 == 24'd8397427
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte0 == 24'd10494576
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte1 == 24'd10494577
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte2 == 24'd10494578
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte3 == 24'd10494579
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_tph_req_cap_int_vec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_tph_req_cap_int_vec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_tph_req_cap_reg_rsvdp_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_tph_req_cap_reg_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_tph_req_cap_reg_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_tph_req_cap_reg_vfcomm_cs2_rsvdp_11_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_tph_req_cap_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_tph_req_cap_reg_vfcomm_cs2_rsvdp_3_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_tph_req_cap_st_table_loc_0 == PF2_NOT_IN_TPH_STRUCT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_tph_req_cap_st_table_loc_0_vfcomm_cs2 == PF2_NOT_IN_TPH_STRUCT_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_tph_req_cap_st_table_loc_1 == PF2_NOT_IN_MSIX_TABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_tph_req_cap_st_table_loc_1_vfcomm_cs2 == PF2_NOT_IN_MSIX_TABLE_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_tph_req_cap_st_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_tph_req_cap_st_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_tph_req_cap_ver == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_tph_req_device_spec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_tph_req_device_spec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_tph_req_extended_tph == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_tph_req_extended_tph_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_tph_req_next_ptr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_tph_req_no_st_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_tph_req_no_st_mode_vfcomm_cs2 == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_bar0_mask_reg_addr_byte0 == 24'd2105360
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_bar0_mask_reg_addr_byte1 == 24'd2105361
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_bar0_mask_reg_addr_byte2 == 24'd2105362
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_bar0_mask_reg_addr_byte3 == 24'd2105363
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_bar0_reg_addr_byte0 == 24'd8208
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_bar1_enable_reg_addr_byte0 == 24'd2105364
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_bar1_mask_reg_addr_byte0 == 24'd2105364
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_bar1_mask_reg_addr_byte1 == 24'd2105365
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_bar1_mask_reg_addr_byte2 == 24'd2105366
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_bar1_mask_reg_addr_byte3 == 24'd2105367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_bar1_reg_addr_byte0 == 24'd8212
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_bar2_mask_reg_addr_byte0 == 24'd2105368
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_bar2_mask_reg_addr_byte1 == 24'd2105369
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_bar2_mask_reg_addr_byte2 == 24'd2105370
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_bar2_mask_reg_addr_byte3 == 24'd2105371
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_bar2_reg_addr_byte0 == 24'd8216
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_bar3_enable_reg_addr_byte0 == 24'd2105372
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_bar3_mask_reg_addr_byte0 == 24'd2105372
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_bar3_mask_reg_addr_byte1 == 24'd2105373
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_bar3_mask_reg_addr_byte2 == 24'd2105374
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_bar3_mask_reg_addr_byte3 == 24'd2105375
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_bar3_reg_addr_byte0 == 24'd8220
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_bar4_mask_reg_addr_byte0 == 24'd2105376
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_bar4_mask_reg_addr_byte1 == 24'd2105377
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_bar4_mask_reg_addr_byte2 == 24'd2105378
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_bar4_mask_reg_addr_byte3 == 24'd2105379
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_bar4_reg_addr_byte0 == 24'd8224
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_bar5_enable_reg_addr_byte0 == 24'd2105380
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_bar5_mask_reg_addr_byte0 == 24'd2105380
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_bar5_mask_reg_addr_byte1 == 24'd2105381
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_bar5_mask_reg_addr_byte2 == 24'd2105382
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_bar5_mask_reg_addr_byte3 == 24'd2105383
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_bar5_reg_addr_byte0 == 24'd8228
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_bist_header_type_latency_cache_line_size_reg_addr_byte2 == 24'd8396814
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_cardbus_cis_ptr_reg_addr_byte0 == 24'd8396840
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_cardbus_cis_ptr_reg_addr_byte1 == 24'd8396841
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_cardbus_cis_ptr_reg_addr_byte2 == 24'd8396842
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_cardbus_cis_ptr_reg_addr_byte3 == 24'd8396843
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_class_code_revision_id_addr_byte0 == 24'd8396808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_class_code_revision_id_addr_byte1 == 24'd8396809
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_class_code_revision_id_addr_byte2 == 24'd8396810
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_class_code_revision_id_addr_byte3 == 24'd8396811
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_device_id_vendor_id_reg_addr_byte0 == 24'd8396800
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_device_id_vendor_id_reg_addr_byte1 == 24'd8396801
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_device_id_vendor_id_reg_addr_byte2 == 24'd8396802
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_device_id_vendor_id_reg_addr_byte3 == 24'd8396803
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_exp_rom_bar_mask_reg_addr_byte0 == 24'd2105392
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_exp_rom_bar_mask_reg_addr_byte1 == 24'd2105393
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_exp_rom_bar_mask_reg_addr_byte2 == 24'd2105394
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_exp_rom_bar_mask_reg_addr_byte3 == 24'd2105395
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_exp_rom_base_addr_reg_addr_byte0 == 24'd8240
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_max_latency_min_grant_interrupt_pin_interrupt_line_reg_addr_byte1 == 24'd8253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_pci_cap_ptr_reg_addr_byte0 == 24'd8396852
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte0 == 24'd8396844
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte1 == 24'd8396845
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte2 == 24'd8396846
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte3 == 24'd8396847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_vf_bar0_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_vf_bar1_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_vf_bar2_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_vf_bar3_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_vf_bar4_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_vf_bar5_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_vsecras_cap_rasdp_ext_hdr_off_addr_byte2 == 24'd8397878
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_vsecras_cap_rasdp_ext_hdr_off_addr_byte3 == 24'd8397879
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_vsecras_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf2_vsecras_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_acs_cap_acs_at_block == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_acs_cap_acs_cap_hdr_reg_addr_byte2 == 24'd8401674
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_acs_cap_acs_cap_hdr_reg_addr_byte3 == 24'd8401675
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_acs_cap_acs_capalities_ctrl_reg_addr_byte0 == 24'd8401676
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_acs_cap_acs_capalities_ctrl_reg_addr_byte1 == 24'd13069
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_acs_cap_acs_direct_translated_p2p == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_acs_cap_acs_egress_ctrl_size == 8'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_acs_cap_acs_p2p_cpl_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_acs_cap_acs_p2p_egress_control == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_acs_cap_acs_p2p_req_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_acs_cap_acs_src_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_acs_cap_acs_usp_forwarding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_acs_cap_rsvdp_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_acs_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_acs_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_aer_cap_aer_ext_cap_hdr_off_addr_byte2 == 24'd8401154
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_aer_cap_aer_ext_cap_hdr_off_addr_byte3 == 24'd8401155
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_aer_cap_version == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_aer_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_ari_cap_ari_base_addr_byte2 == 24'd8401270
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_ari_cap_ari_base_addr_byte3 == 24'd8401271
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_ari_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_ari_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_ats_cap_ats_cap_hdr_reg_addr_byte2 == 24'd8401658
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_ats_cap_ats_cap_hdr_reg_addr_byte3 == 24'd8401659
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_ats_cap_ats_capabilities_ctrl_reg_addr_byte0 == 24'd8401660
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_ats_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_ats_capabilities_ctrl_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_ats_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_aux_curr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_bar0_mem_io == PF3_BAR0_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_bar0_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_bar0_type == PF3_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_bar1_mem_io == PF3_BAR1_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_bar1_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_bar1_type == PF3_BAR1_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_bar2_mem_io == PF3_BAR2_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_bar2_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_bar2_type == PF3_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_bar3_mem_io == PF3_BAR3_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_bar3_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_bar3_type == PF3_BAR3_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_bar4_mem_io == PF3_BAR4_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_bar4_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_bar4_type == PF3_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_bar5_mem_io == PF3_BAR5_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_bar5_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_bar5_type == PF3_BAR5_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_base_class_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_cap_id_nxt_ptr_reg_rsvdp_20 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_cap_pointer == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_cardbus_cis_pointer == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_con_status_reg_rsvdp_2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_con_status_reg_rsvdp_4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_d1_support == PF3_D1_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_d2_support == PF3_D2_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_10 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_11 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_12 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_13 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_14 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_15 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_16 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_17 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_18 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_19 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_20 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_21 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_22 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_23 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_24 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_25 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_26 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_27 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_28 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_29 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_30 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_31 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_32 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_33 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_34 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_35 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_36 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_37 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_38 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_39 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_40 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_41 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_42 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_43 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_44 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_45 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_46 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_47 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_48 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_49 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_50 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_51 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_52 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_53 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_54 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_55 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_56 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_57 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_58 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_59 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_6 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_60 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_61 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_62 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_63 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_64 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_65 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_7 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_8 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dbi_reserved_9 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_device_capabilities_reg_rsvdp_12 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_device_capabilities_reg_rsvdp_16 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_device_capabilities_reg_rsvdp_29 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_dsi == PF3_NOT_REQUIRED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_exp_rom_bar_mask_reg_rsvdp_1 == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_exp_rom_base_addr_reg_rsvdp_1 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_global_inval_spprtd == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_header_type == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_int_pin == PF3_NO_INT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_invalidate_q_depth == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_link_capabilities_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_link_control_link_status_reg_rsvdp_12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_link_control_link_status_reg_rsvdp_2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_link_control_link_status_reg_rsvdp_26 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_link_control_link_status_reg_rsvdp_9 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte1 == 24'd8400977
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte2 == 24'd8400978
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte3 == 24'd8400979
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_msi_cap_pci_msi_cap_id_next_ctrl_reg_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_msix_cap_msix_pba_offset_reg_addr_byte0 == 24'd8401080
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_msix_cap_msix_pba_offset_reg_addr_byte1 == 24'd8401081
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_msix_cap_msix_pba_offset_reg_addr_byte2 == 24'd8401082
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_msix_cap_msix_pba_offset_reg_addr_byte3 == 24'd8401083
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_msix_cap_msix_table_offset_reg_addr_byte0 == 24'd8401076
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_msix_cap_msix_table_offset_reg_addr_byte1 == 24'd8401077
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_msix_cap_msix_table_offset_reg_addr_byte2 == 24'd8401078
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_msix_cap_msix_table_offset_reg_addr_byte3 == 24'd8401079
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte1 == 24'd8401073
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte2 == 24'd8401074
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte3 == 24'd8401075
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte2 == 24'd10498226
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte3 == 24'd10498227
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_multi_func == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_no_soft_rst == PF3_INTERNALLY_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_page_aligned_req == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pasid_cap_execute_permission_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pasid_cap_max_pasid_width == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pasid_cap_pasid_cap_cntrl_reg_addr_byte0 == 24'd8401712
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pasid_cap_pasid_cap_cntrl_reg_addr_byte1 == 24'd8401713
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pasid_cap_pasid_ext_hdr_reg_addr_byte2 == 24'd8401710
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pasid_cap_pasid_ext_hdr_reg_addr_byte3 == 24'd8401711
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pasid_cap_privileged_mode_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pasid_cap_rsvdp_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pasid_cap_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pasid_cap_rsvpd_13 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pasid_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pasid_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_msi_64_bit_addr_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_msi_cap_next_offset == 8'd112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_msi_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_msi_ext_data_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_msi_ext_data_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_msi_multiple_msg_cap == PF3_MSI_VEC_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_msi_multiple_msg_en == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_msix_bir == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_msix_cap_id_next_ctrl_reg_rsvdp_27 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_msix_cap_next_offset == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_msix_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_msix_enable_vfcomm_cs2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_msix_function_mask == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_msix_function_mask_vfcomm_cs2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_msix_pba == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_msix_pba_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_msix_table_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_msix_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_msix_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_pvm_support == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_type0_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_type0_bar0_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_type0_bar1_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_type0_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_type0_bar1_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_type0_bar1_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_type0_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_type0_bar2_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_type0_bar3_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_type0_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_type0_bar3_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_type0_bar3_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_type0_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_type0_bar4_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_type0_bar5_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_type0_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_type0_bar5_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_type0_bar5_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_type0_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pci_type0_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_active_state_link_pm_control == PF3_ASPM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_active_state_link_pm_support == PF3_NO_ASPM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_aspm_opt_compliance == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_aux_power_pm_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_clock_power_man == PF3_REFCLK_REMOVE_NOT_OK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_common_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_device_capabilities_reg_addr_byte0 == 24'd8401012
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_device_capabilities_reg_addr_byte1 == 24'd8401013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_device_capabilities_reg_addr_byte3 == 24'd8401015
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_device_control_device_status_addr_byte1 == 24'd8401017
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_dll_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_dll_active_rep_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_en_clk_power_man == PF3_CLKREQ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_en_no_snoop == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_enter_compliance == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_ep_l0s_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_ep_l1_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_ext_tag_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_ext_tag_supp == PF3_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_extended_synch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_flr_cap == PF3_NOT_CAPABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_hw_auto_speed_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvd == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_initiate_flr == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_l0s_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_l1_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_link_auto_bw_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_link_auto_bw_status == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_link_bw_man_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_link_bw_man_status == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_link_bw_not_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_link_capabilities_reg_addr_byte0 == 24'd8401020
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_link_capabilities_reg_addr_byte1 == 24'd8401021
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_link_capabilities_reg_addr_byte2 == 24'd8401022
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_link_capabilities_reg_addr_byte3 == 24'd12415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_link_control2_link_status2_reg_addr_byte0 == 24'd12595360
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_link_control_link_status_reg_addr_byte0 == 24'd4206720
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_link_control_link_status_reg_addr_byte1 == 24'd12595329
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_link_control_link_status_reg_addr_byte3 == 24'd4206723
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_link_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_link_training == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_max_link_speed == PF3_MAX_2P5GTS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_max_link_width == PF3_X1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_max_payload_size == PF3_PAYLOAD_128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_max_read_req_size == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_nego_link_width == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_next_ptr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte1 == 24'd8401009
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte3 == 24'd8401011
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_phantom_func_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_phantom_func_support == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_port_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_rcb == PF3_RCB_64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_retrain_link == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_role_based_err_report == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_sel_deemphasis == PF3_MINUS_6DB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_slot_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_surprise_down_err_rep_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_target_link_speed == PF3_TRGT_GEN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_cap_tx_margin == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_int_msg_num == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pcie_slot_imp == PF3_NOT_IMPLEMENTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pf0_ari_device_number == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pf0_dbi_ro_wr_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pf0_default_target == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pf0_disable_auto_ltr_clr_msg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pf0_mask_ur_ca_4_trgt1 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pf0_misc_control_1_off_rsvdp_6 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pf0_port_logic_misc_control_1_off_addr_byte0 == 24'd2236
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pf0_simplified_replay_timer == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pf0_tlp_bypass_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pm_cap_cap_id_nxt_ptr_reg_addr_byte1 == 24'd8400961
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pm_cap_cap_id_nxt_ptr_reg_addr_byte2 == 24'd8400962
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pm_cap_cap_id_nxt_ptr_reg_addr_byte3 == 24'd8400963
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pm_cap_con_status_reg_addr_byte0 == 24'd8400964
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pm_next_pointer == 8'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pm_spec_ver == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pme_clk == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_pme_support == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_power_state == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_program_interface == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte2 == 24'd8401686
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte3 == 24'd8401687
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_prs_ext_cap_prs_req_capacity_reg_addr_byte0 == 24'd8401692
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_prs_ext_cap_prs_req_capacity_reg_addr_byte1 == 24'd8401693
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_prs_ext_cap_prs_req_capacity_reg_addr_byte2 == 24'd8401694
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_prs_ext_cap_prs_req_capacity_reg_addr_byte3 == 24'd8401695
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_prs_ext_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_prs_ext_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_prs_outstanding_capacity == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_ras_des_cap_event_counter_ctrl_reg_addr_byte0 == 24'd13116
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_ras_des_cap_event_counter_ctrl_reg_g5_addr_byte3 == 24'd8401727
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_ras_des_cap_event_counter_ctrl_reg_g6_addr_byte3 == 24'd8401727
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_ras_des_cap_event_counter_ctrl_reg_g7_addr_byte3 == 24'd8401727
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_ras_des_cap_force_detect_lane == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_ras_des_cap_force_detect_lane_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_ras_des_cap_ras_des_hdr_reg_addr_byte2 == 24'd8401718
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_ras_des_cap_ras_des_hdr_reg_addr_byte3 == 24'd8401719
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_ras_des_cap_sd_control1_reg_addr_byte0 == 24'd8401876
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_ras_des_cap_sd_control1_reg_addr_byte1 == 24'd8401877
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_ras_des_cap_sd_control1_reg_addr_byte2 == 24'd8401878
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_ras_des_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_ras_des_event_counter_en == 8'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_ras_des_event_counter_event_select_g5 == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_ras_des_event_counter_event_select_g6 == 8'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_ras_des_event_counter_event_select_g7 == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_ras_des_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_10_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_11_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_12_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_13_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_14_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_15_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_16_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_17_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_18_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_19_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_20_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_21_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_22_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_23_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_24_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_25_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_26_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_27_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_28_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_29_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_30_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_31_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_32_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_33_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_34_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_35_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_36_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_37_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_38_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_39_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_40_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_41_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_42_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_43_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_44_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_45_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_46_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_47_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_48_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_49_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_50_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_51_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_52_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_53_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_54_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_55_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_56_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_57_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_58_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_59_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_60_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_61_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_62_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_63_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_64_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_65_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_7_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_8_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_reserved_9_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_revision_id == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_rom_bar_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_rom_bar_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_shadow_sriov_vf_stride_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sn_cap_ser_num_reg_dw_1_addr_byte0 == 24'd8401256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sn_cap_ser_num_reg_dw_1_addr_byte1 == 24'd8401257
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sn_cap_ser_num_reg_dw_1_addr_byte2 == 24'd8401258
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sn_cap_ser_num_reg_dw_1_addr_byte3 == 24'd8401259
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sn_cap_ser_num_reg_dw_2_addr_byte0 == 24'd8401260
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sn_cap_ser_num_reg_dw_2_addr_byte1 == 24'd8401261
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sn_cap_ser_num_reg_dw_2_addr_byte2 == 24'd8401262
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sn_cap_ser_num_reg_dw_2_addr_byte3 == 24'd8401263
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sn_cap_sn_base_addr_byte2 == 24'd8401254
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sn_cap_sn_base_addr_byte3 == 24'd8401255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sn_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sn_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sn_ser_num_reg_1_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sn_ser_num_reg_2_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_shadow_sriov_initial_vfs_addr_byte0 == 24'd10498616
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_shadow_sriov_initial_vfs_addr_byte1 == 24'd10498617
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_shadow_sriov_vf_offset_position_addr_byte0 == 24'd10498624
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_shadow_sriov_vf_offset_position_addr_byte1 == 24'd10498625
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_shadow_sriov_vf_offset_position_addr_byte2 == 24'd10498626
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_shadow_sriov_vf_offset_position_addr_byte3 == 24'd10498627
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_shadow_vf_bar0_reg_addr_byte0 == 24'd2110032
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_shadow_vf_bar0_reg_addr_byte1 == 24'd2110033
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_shadow_vf_bar0_reg_addr_byte2 == 24'd2110034
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_shadow_vf_bar0_reg_addr_byte3 == 24'd2110035
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_shadow_vf_bar1_reg_addr_byte0 == 24'd2110036
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_shadow_vf_bar1_reg_addr_byte1 == 24'd2110037
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_shadow_vf_bar1_reg_addr_byte2 == 24'd2110038
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_shadow_vf_bar1_reg_addr_byte3 == 24'd2110039
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_shadow_vf_bar2_reg_addr_byte0 == 24'd2110040
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_shadow_vf_bar2_reg_addr_byte1 == 24'd2110041
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_shadow_vf_bar2_reg_addr_byte2 == 24'd2110042
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_shadow_vf_bar2_reg_addr_byte3 == 24'd2110043
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_shadow_vf_bar3_reg_addr_byte0 == 24'd2110044
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_shadow_vf_bar3_reg_addr_byte1 == 24'd2110045
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_shadow_vf_bar3_reg_addr_byte2 == 24'd2110046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_shadow_vf_bar3_reg_addr_byte3 == 24'd2110047
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_shadow_vf_bar4_reg_addr_byte0 == 24'd2110048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_shadow_vf_bar4_reg_addr_byte1 == 24'd2110049
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_shadow_vf_bar4_reg_addr_byte2 == 24'd2110050
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_shadow_vf_bar4_reg_addr_byte3 == 24'd2110051
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_shadow_vf_bar5_reg_addr_byte0 == 24'd2110052
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_shadow_vf_bar5_reg_addr_byte1 == 24'd2110053
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_shadow_vf_bar5_reg_addr_byte2 == 24'd2110054
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_shadow_vf_bar5_reg_addr_byte3 == 24'd2110055
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_sriov_bar1_enable_reg_addr_byte0 == 24'd2110036
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_sriov_bar3_enable_reg_addr_byte0 == 24'd2110044
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_sriov_bar5_enable_reg_addr_byte0 == 24'd2110052
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_sriov_base_reg_addr_byte2 == 24'd8401454
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_sriov_base_reg_addr_byte3 == 24'd8401455
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_sriov_initial_vfs_addr_byte0 == 24'd8401464
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_sriov_initial_vfs_addr_byte1 == 24'd8401465
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_sriov_vf_offset_position_addr_byte0 == 24'd8401472
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_sriov_vf_offset_position_addr_byte1 == 24'd8401473
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_sriov_vf_offset_position_addr_byte2 == 24'd8401474
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_sriov_vf_offset_position_addr_byte3 == 24'd8401475
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_sup_page_sizes_reg_addr_byte0 == 24'd8401480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_sup_page_sizes_reg_addr_byte1 == 24'd8401481
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_sup_page_sizes_reg_addr_byte2 == 24'd8401482
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_sup_page_sizes_reg_addr_byte3 == 24'd8401483
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_vf_bar0_reg_addr_byte0 == 24'd12880
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_vf_bar1_reg_addr_byte0 == 24'd12884
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_vf_bar2_reg_addr_byte0 == 24'd12888
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_vf_bar3_reg_addr_byte0 == 24'd12892
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_vf_bar4_reg_addr_byte0 == 24'd12896
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_vf_bar5_reg_addr_byte0 == 24'd12900
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_vf_device_id_reg_addr_byte2 == 24'd8401478
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_cap_vf_device_id_reg_addr_byte3 == 24'd8401479
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_initial_vfs_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_initial_vfs_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_sup_page_size == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_vf_bar0_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_vf_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_vf_bar0_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_vf_bar0_type == PF3_SRIOV_VF_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_vf_bar1_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_vf_bar1_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_vf_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_vf_bar1_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_vf_bar1_type == PF3_SRIOV_VF_BAR1_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_vf_bar2_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_vf_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_vf_bar2_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_vf_bar2_type == PF3_SRIOV_VF_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_vf_bar3_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_vf_bar3_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_vf_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_vf_bar3_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_vf_bar3_type == PF3_SRIOV_VF_BAR3_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_vf_bar4_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_vf_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_vf_bar4_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_vf_bar4_type == PF3_SRIOV_VF_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_vf_bar5_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_vf_bar5_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_vf_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_vf_bar5_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_vf_bar5_type == PF3_SRIOV_VF_BAR5_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_vf_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_vf_offset_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_vf_offset_position_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_sriov_vf_stride_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_subclass_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_subsys_dev_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_subsys_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_tph_cap_tph_ext_cap_hdr_reg_addr_byte2 == 24'd8401518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_tph_cap_tph_ext_cap_hdr_reg_addr_byte3 == 24'd8401519
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_tph_cap_tph_req_cap_reg_addr_byte0 == 24'd8401520
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_tph_cap_tph_req_cap_reg_addr_byte1 == 24'd8401521
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_tph_cap_tph_req_cap_reg_addr_byte2 == 24'd8401522
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_tph_cap_tph_req_cap_reg_addr_byte3 == 24'd8401523
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte0 == 24'd10498672
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte1 == 24'd10498673
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte2 == 24'd10498674
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte3 == 24'd10498675
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_tph_req_cap_int_vec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_tph_req_cap_int_vec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_tph_req_cap_reg_rsvdp_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_tph_req_cap_reg_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_tph_req_cap_reg_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_tph_req_cap_reg_vfcomm_cs2_rsvdp_11_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_tph_req_cap_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_tph_req_cap_reg_vfcomm_cs2_rsvdp_3_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_tph_req_cap_st_table_loc_0 == PF3_NOT_IN_TPH_STRUCT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_tph_req_cap_st_table_loc_0_vfcomm_cs2 == PF3_NOT_IN_TPH_STRUCT_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_tph_req_cap_st_table_loc_1 == PF3_NOT_IN_MSIX_TABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_tph_req_cap_st_table_loc_1_vfcomm_cs2 == PF3_NOT_IN_MSIX_TABLE_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_tph_req_cap_st_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_tph_req_cap_st_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_tph_req_cap_ver == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_tph_req_device_spec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_tph_req_device_spec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_tph_req_extended_tph == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_tph_req_extended_tph_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_tph_req_next_ptr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_tph_req_no_st_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_tph_req_no_st_mode_vfcomm_cs2 == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_bar0_mask_reg_addr_byte0 == 24'd2109456
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_bar0_mask_reg_addr_byte1 == 24'd2109457
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_bar0_mask_reg_addr_byte2 == 24'd2109458
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_bar0_mask_reg_addr_byte3 == 24'd2109459
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_bar0_reg_addr_byte0 == 24'd12304
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_bar1_enable_reg_addr_byte0 == 24'd2109460
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_bar1_mask_reg_addr_byte0 == 24'd2109460
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_bar1_mask_reg_addr_byte1 == 24'd2109461
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_bar1_mask_reg_addr_byte2 == 24'd2109462
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_bar1_mask_reg_addr_byte3 == 24'd2109463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_bar1_reg_addr_byte0 == 24'd12308
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_bar2_mask_reg_addr_byte0 == 24'd2109464
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_bar2_mask_reg_addr_byte1 == 24'd2109465
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_bar2_mask_reg_addr_byte2 == 24'd2109466
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_bar2_mask_reg_addr_byte3 == 24'd2109467
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_bar2_reg_addr_byte0 == 24'd12312
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_bar3_enable_reg_addr_byte0 == 24'd2109468
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_bar3_mask_reg_addr_byte0 == 24'd2109468
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_bar3_mask_reg_addr_byte1 == 24'd2109469
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_bar3_mask_reg_addr_byte2 == 24'd2109470
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_bar3_mask_reg_addr_byte3 == 24'd2109471
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_bar3_reg_addr_byte0 == 24'd12316
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_bar4_mask_reg_addr_byte0 == 24'd2109472
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_bar4_mask_reg_addr_byte1 == 24'd2109473
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_bar4_mask_reg_addr_byte2 == 24'd2109474
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_bar4_mask_reg_addr_byte3 == 24'd2109475
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_bar4_reg_addr_byte0 == 24'd12320
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_bar5_enable_reg_addr_byte0 == 24'd2109476
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_bar5_mask_reg_addr_byte0 == 24'd2109476
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_bar5_mask_reg_addr_byte1 == 24'd2109477
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_bar5_mask_reg_addr_byte2 == 24'd2109478
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_bar5_mask_reg_addr_byte3 == 24'd2109479
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_bar5_reg_addr_byte0 == 24'd12324
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_bist_header_type_latency_cache_line_size_reg_addr_byte2 == 24'd8400910
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_cardbus_cis_ptr_reg_addr_byte0 == 24'd8400936
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_cardbus_cis_ptr_reg_addr_byte1 == 24'd8400937
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_cardbus_cis_ptr_reg_addr_byte2 == 24'd8400938
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_cardbus_cis_ptr_reg_addr_byte3 == 24'd8400939
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_class_code_revision_id_addr_byte0 == 24'd8400904
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_class_code_revision_id_addr_byte1 == 24'd8400905
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_class_code_revision_id_addr_byte2 == 24'd8400906
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_class_code_revision_id_addr_byte3 == 24'd8400907
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_device_id_vendor_id_reg_addr_byte0 == 24'd8400896
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_device_id_vendor_id_reg_addr_byte1 == 24'd8400897
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_device_id_vendor_id_reg_addr_byte2 == 24'd8400898
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_device_id_vendor_id_reg_addr_byte3 == 24'd8400899
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_exp_rom_bar_mask_reg_addr_byte0 == 24'd2109488
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_exp_rom_bar_mask_reg_addr_byte1 == 24'd2109489
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_exp_rom_bar_mask_reg_addr_byte2 == 24'd2109490
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_exp_rom_bar_mask_reg_addr_byte3 == 24'd2109491
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_exp_rom_base_addr_reg_addr_byte0 == 24'd12336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_max_latency_min_grant_interrupt_pin_interrupt_line_reg_addr_byte1 == 24'd8400957
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_pci_cap_ptr_reg_addr_byte0 == 24'd8400948
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte0 == 24'd8400940
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte1 == 24'd8400941
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte2 == 24'd8400942
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte3 == 24'd8400943
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_vf_bar0_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_vf_bar1_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_vf_bar2_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_vf_bar3_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_vf_bar4_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_vf_bar5_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_vsecras_cap_rasdp_ext_hdr_off_addr_byte2 == 24'd8401974
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_vsecras_cap_rasdp_ext_hdr_off_addr_byte3 == 24'd8401975
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_vsecras_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf3_vsecras_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_acs_cap_acs_at_block == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_acs_cap_acs_cap_hdr_reg_addr_byte2 == 24'd8405770
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_acs_cap_acs_cap_hdr_reg_addr_byte3 == 24'd8405771
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_acs_cap_acs_capalities_ctrl_reg_addr_byte0 == 24'd8405772
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_acs_cap_acs_capalities_ctrl_reg_addr_byte1 == 24'd17165
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_acs_cap_acs_direct_translated_p2p == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_acs_cap_acs_egress_ctrl_size == 8'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_acs_cap_acs_p2p_cpl_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_acs_cap_acs_p2p_egress_control == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_acs_cap_acs_p2p_req_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_acs_cap_acs_src_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_acs_cap_acs_usp_forwarding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_acs_cap_rsvdp_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_acs_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_acs_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_aer_cap_aer_ext_cap_hdr_off_addr_byte2 == 24'd8405250
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_aer_cap_aer_ext_cap_hdr_off_addr_byte3 == 24'd8405251
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_aer_cap_version == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_aer_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_ari_cap_ari_base_addr_byte2 == 24'd8405366
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_ari_cap_ari_base_addr_byte3 == 24'd8405367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_ari_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_ari_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_ats_cap_ats_cap_hdr_reg_addr_byte2 == 24'd8405754
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_ats_cap_ats_cap_hdr_reg_addr_byte3 == 24'd8405755
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_ats_cap_ats_capabilities_ctrl_reg_addr_byte0 == 24'd8405756
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_ats_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_ats_capabilities_ctrl_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_ats_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_aux_curr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_bar0_mem_io == PF4_BAR0_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_bar0_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_bar0_type == PF4_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_bar1_mem_io == PF4_BAR1_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_bar1_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_bar1_type == PF4_BAR1_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_bar2_mem_io == PF4_BAR2_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_bar2_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_bar2_type == PF4_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_bar3_mem_io == PF4_BAR3_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_bar3_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_bar3_type == PF4_BAR3_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_bar4_mem_io == PF4_BAR4_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_bar4_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_bar4_type == PF4_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_bar5_mem_io == PF4_BAR5_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_bar5_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_bar5_type == PF4_BAR5_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_base_class_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_cap_id_nxt_ptr_reg_rsvdp_20 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_cap_pointer == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_cardbus_cis_pointer == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_con_status_reg_rsvdp_2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_con_status_reg_rsvdp_4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_d1_support == PF4_D1_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_d2_support == PF4_D2_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_10 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_11 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_12 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_13 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_14 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_15 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_16 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_17 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_18 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_19 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_20 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_21 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_22 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_23 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_24 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_25 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_26 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_27 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_28 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_29 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_30 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_31 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_32 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_33 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_34 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_35 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_36 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_37 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_38 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_39 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_40 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_41 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_42 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_43 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_44 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_45 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_46 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_47 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_48 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_49 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_50 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_51 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_52 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_53 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_54 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_55 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_56 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_57 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_58 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_59 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_6 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_60 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_61 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_62 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_63 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_64 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_65 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_7 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_8 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dbi_reserved_9 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_device_capabilities_reg_rsvdp_12 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_device_capabilities_reg_rsvdp_16 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_device_capabilities_reg_rsvdp_29 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_dsi == PF4_NOT_REQUIRED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_exp_rom_bar_mask_reg_rsvdp_1 == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_exp_rom_base_addr_reg_rsvdp_1 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_global_inval_spprtd == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_header_type == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_int_pin == PF4_NO_INT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_invalidate_q_depth == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_link_capabilities_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_link_control_link_status_reg_rsvdp_12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_link_control_link_status_reg_rsvdp_2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_link_control_link_status_reg_rsvdp_26 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_link_control_link_status_reg_rsvdp_9 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte1 == 24'd8405073
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte2 == 24'd8405074
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte3 == 24'd8405075
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_msi_cap_pci_msi_cap_id_next_ctrl_reg_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_msix_cap_msix_pba_offset_reg_addr_byte0 == 24'd8405176
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_msix_cap_msix_pba_offset_reg_addr_byte1 == 24'd8405177
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_msix_cap_msix_pba_offset_reg_addr_byte2 == 24'd8405178
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_msix_cap_msix_pba_offset_reg_addr_byte3 == 24'd8405179
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_msix_cap_msix_table_offset_reg_addr_byte0 == 24'd8405172
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_msix_cap_msix_table_offset_reg_addr_byte1 == 24'd8405173
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_msix_cap_msix_table_offset_reg_addr_byte2 == 24'd8405174
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_msix_cap_msix_table_offset_reg_addr_byte3 == 24'd8405175
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte1 == 24'd8405169
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte2 == 24'd8405170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte3 == 24'd8405171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte2 == 24'd10502322
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte3 == 24'd10502323
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_multi_func == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_no_soft_rst == PF4_INTERNALLY_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_page_aligned_req == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pasid_cap_execute_permission_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pasid_cap_max_pasid_width == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pasid_cap_pasid_cap_cntrl_reg_addr_byte0 == 24'd8405808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pasid_cap_pasid_cap_cntrl_reg_addr_byte1 == 24'd8405809
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pasid_cap_pasid_ext_hdr_reg_addr_byte2 == 24'd8405806
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pasid_cap_pasid_ext_hdr_reg_addr_byte3 == 24'd8405807
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pasid_cap_privileged_mode_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pasid_cap_rsvdp_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pasid_cap_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pasid_cap_rsvpd_13 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pasid_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pasid_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_msi_64_bit_addr_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_msi_cap_next_offset == 8'd112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_msi_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_msi_ext_data_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_msi_ext_data_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_msi_multiple_msg_cap == PF4_MSI_VEC_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_msi_multiple_msg_en == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_msix_bir == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_msix_cap_id_next_ctrl_reg_rsvdp_27 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_msix_cap_next_offset == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_msix_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_msix_enable_vfcomm_cs2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_msix_function_mask == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_msix_function_mask_vfcomm_cs2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_msix_pba == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_msix_pba_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_msix_table_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_msix_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_msix_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_pvm_support == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_type0_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_type0_bar0_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_type0_bar1_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_type0_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_type0_bar1_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_type0_bar1_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_type0_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_type0_bar2_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_type0_bar3_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_type0_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_type0_bar3_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_type0_bar3_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_type0_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_type0_bar4_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_type0_bar5_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_type0_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_type0_bar5_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_type0_bar5_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_type0_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pci_type0_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_active_state_link_pm_control == PF4_ASPM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_active_state_link_pm_support == PF4_NO_ASPM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_aspm_opt_compliance == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_aux_power_pm_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_clock_power_man == PF4_REFCLK_REMOVE_NOT_OK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_common_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_device_capabilities_reg_addr_byte0 == 24'd8405108
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_device_capabilities_reg_addr_byte1 == 24'd8405109
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_device_capabilities_reg_addr_byte3 == 24'd8405111
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_device_control_device_status_addr_byte1 == 24'd8405113
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_dll_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_dll_active_rep_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_en_clk_power_man == PF4_CLKREQ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_en_no_snoop == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_enter_compliance == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_ep_l0s_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_ep_l1_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_ext_tag_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_ext_tag_supp == PF4_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_extended_synch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_flr_cap == PF4_NOT_CAPABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_hw_auto_speed_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvd == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_initiate_flr == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_l0s_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_l1_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_link_auto_bw_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_link_auto_bw_status == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_link_bw_man_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_link_bw_man_status == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_link_bw_not_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_link_capabilities_reg_addr_byte0 == 24'd8405116
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_link_capabilities_reg_addr_byte1 == 24'd8405117
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_link_capabilities_reg_addr_byte2 == 24'd8405118
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_link_capabilities_reg_addr_byte3 == 24'd16511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_link_control2_link_status2_reg_addr_byte0 == 24'd12599456
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_link_control_link_status_reg_addr_byte0 == 24'd4210816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_link_control_link_status_reg_addr_byte1 == 24'd12599425
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_link_control_link_status_reg_addr_byte3 == 24'd4210819
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_link_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_link_training == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_max_link_speed == PF4_MAX_2P5GTS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_max_link_width == PF4_X1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_max_payload_size == PF4_PAYLOAD_128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_max_read_req_size == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_nego_link_width == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_next_ptr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte1 == 24'd8405105
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte3 == 24'd8405107
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_phantom_func_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_phantom_func_support == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_port_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_rcb == PF4_RCB_64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_retrain_link == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_role_based_err_report == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_sel_deemphasis == PF4_MINUS_6DB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_slot_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_surprise_down_err_rep_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_target_link_speed == PF4_TRGT_GEN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_cap_tx_margin == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_int_msg_num == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pcie_slot_imp == PF4_NOT_IMPLEMENTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pf0_ari_device_number == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pf0_dbi_ro_wr_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pf0_default_target == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pf0_disable_auto_ltr_clr_msg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pf0_mask_ur_ca_4_trgt1 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pf0_misc_control_1_off_rsvdp_6 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pf0_port_logic_misc_control_1_off_addr_byte0 == 24'd2236
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pf0_simplified_replay_timer == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pf0_tlp_bypass_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pm_cap_cap_id_nxt_ptr_reg_addr_byte1 == 24'd8405057
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pm_cap_cap_id_nxt_ptr_reg_addr_byte2 == 24'd8405058
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pm_cap_cap_id_nxt_ptr_reg_addr_byte3 == 24'd8405059
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pm_cap_con_status_reg_addr_byte0 == 24'd8405060
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pm_next_pointer == 8'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pm_spec_ver == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pme_clk == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_pme_support == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_power_state == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_program_interface == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte2 == 24'd8405782
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte3 == 24'd8405783
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_prs_ext_cap_prs_req_capacity_reg_addr_byte0 == 24'd8405788
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_prs_ext_cap_prs_req_capacity_reg_addr_byte1 == 24'd8405789
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_prs_ext_cap_prs_req_capacity_reg_addr_byte2 == 24'd8405790
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_prs_ext_cap_prs_req_capacity_reg_addr_byte3 == 24'd8405791
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_prs_ext_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_prs_ext_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_prs_outstanding_capacity == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_ras_des_cap_event_counter_ctrl_reg_addr_byte0 == 24'd17212
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_ras_des_cap_event_counter_ctrl_reg_g5_addr_byte3 == 24'd8405823
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_ras_des_cap_event_counter_ctrl_reg_g6_addr_byte3 == 24'd8405823
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_ras_des_cap_event_counter_ctrl_reg_g7_addr_byte3 == 24'd8405823
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_ras_des_cap_force_detect_lane == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_ras_des_cap_force_detect_lane_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_ras_des_cap_ras_des_hdr_reg_addr_byte2 == 24'd8405814
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_ras_des_cap_ras_des_hdr_reg_addr_byte3 == 24'd8405815
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_ras_des_cap_sd_control1_reg_addr_byte0 == 24'd8405972
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_ras_des_cap_sd_control1_reg_addr_byte1 == 24'd8405973
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_ras_des_cap_sd_control1_reg_addr_byte2 == 24'd8405974
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_ras_des_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_ras_des_event_counter_en == 8'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_ras_des_event_counter_event_select_g5 == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_ras_des_event_counter_event_select_g6 == 8'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_ras_des_event_counter_event_select_g7 == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_ras_des_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_10_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_11_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_12_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_13_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_14_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_15_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_16_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_17_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_18_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_19_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_20_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_21_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_22_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_23_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_24_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_25_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_26_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_27_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_28_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_29_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_30_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_31_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_32_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_33_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_34_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_35_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_36_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_37_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_38_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_39_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_40_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_41_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_42_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_43_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_44_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_45_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_46_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_47_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_48_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_49_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_50_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_51_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_52_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_53_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_54_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_55_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_56_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_57_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_58_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_59_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_60_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_61_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_62_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_63_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_64_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_65_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_7_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_8_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_reserved_9_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_revision_id == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_rom_bar_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_rom_bar_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_shadow_sriov_vf_stride_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sn_cap_ser_num_reg_dw_1_addr_byte0 == 24'd8405352
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sn_cap_ser_num_reg_dw_1_addr_byte1 == 24'd8405353
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sn_cap_ser_num_reg_dw_1_addr_byte2 == 24'd8405354
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sn_cap_ser_num_reg_dw_1_addr_byte3 == 24'd8405355
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sn_cap_ser_num_reg_dw_2_addr_byte0 == 24'd8405356
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sn_cap_ser_num_reg_dw_2_addr_byte1 == 24'd8405357
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sn_cap_ser_num_reg_dw_2_addr_byte2 == 24'd8405358
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sn_cap_ser_num_reg_dw_2_addr_byte3 == 24'd8405359
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sn_cap_sn_base_addr_byte2 == 24'd8405350
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sn_cap_sn_base_addr_byte3 == 24'd8405351
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sn_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sn_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sn_ser_num_reg_1_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sn_ser_num_reg_2_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_shadow_sriov_initial_vfs_addr_byte0 == 24'd10502712
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_shadow_sriov_initial_vfs_addr_byte1 == 24'd10502713
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_shadow_sriov_vf_offset_position_addr_byte0 == 24'd10502720
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_shadow_sriov_vf_offset_position_addr_byte1 == 24'd10502721
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_shadow_sriov_vf_offset_position_addr_byte2 == 24'd10502722
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_shadow_sriov_vf_offset_position_addr_byte3 == 24'd10502723
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_shadow_vf_bar0_reg_addr_byte0 == 24'd2114128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_shadow_vf_bar0_reg_addr_byte1 == 24'd2114129
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_shadow_vf_bar0_reg_addr_byte2 == 24'd2114130
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_shadow_vf_bar0_reg_addr_byte3 == 24'd2114131
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_shadow_vf_bar1_reg_addr_byte0 == 24'd2114132
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_shadow_vf_bar1_reg_addr_byte1 == 24'd2114133
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_shadow_vf_bar1_reg_addr_byte2 == 24'd2114134
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_shadow_vf_bar1_reg_addr_byte3 == 24'd2114135
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_shadow_vf_bar2_reg_addr_byte0 == 24'd2114136
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_shadow_vf_bar2_reg_addr_byte1 == 24'd2114137
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_shadow_vf_bar2_reg_addr_byte2 == 24'd2114138
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_shadow_vf_bar2_reg_addr_byte3 == 24'd2114139
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_shadow_vf_bar3_reg_addr_byte0 == 24'd2114140
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_shadow_vf_bar3_reg_addr_byte1 == 24'd2114141
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_shadow_vf_bar3_reg_addr_byte2 == 24'd2114142
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_shadow_vf_bar3_reg_addr_byte3 == 24'd2114143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_shadow_vf_bar4_reg_addr_byte0 == 24'd2114144
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_shadow_vf_bar4_reg_addr_byte1 == 24'd2114145
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_shadow_vf_bar4_reg_addr_byte2 == 24'd2114146
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_shadow_vf_bar4_reg_addr_byte3 == 24'd2114147
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_shadow_vf_bar5_reg_addr_byte0 == 24'd2114148
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_shadow_vf_bar5_reg_addr_byte1 == 24'd2114149
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_shadow_vf_bar5_reg_addr_byte2 == 24'd2114150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_shadow_vf_bar5_reg_addr_byte3 == 24'd2114151
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_sriov_bar1_enable_reg_addr_byte0 == 24'd2114132
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_sriov_bar3_enable_reg_addr_byte0 == 24'd2114140
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_sriov_bar5_enable_reg_addr_byte0 == 24'd2114148
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_sriov_base_reg_addr_byte2 == 24'd8405550
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_sriov_base_reg_addr_byte3 == 24'd8405551
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_sriov_initial_vfs_addr_byte0 == 24'd8405560
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_sriov_initial_vfs_addr_byte1 == 24'd8405561
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_sriov_vf_offset_position_addr_byte0 == 24'd8405568
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_sriov_vf_offset_position_addr_byte1 == 24'd8405569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_sriov_vf_offset_position_addr_byte2 == 24'd8405570
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_sriov_vf_offset_position_addr_byte3 == 24'd8405571
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_sup_page_sizes_reg_addr_byte0 == 24'd8405576
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_sup_page_sizes_reg_addr_byte1 == 24'd8405577
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_sup_page_sizes_reg_addr_byte2 == 24'd8405578
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_sup_page_sizes_reg_addr_byte3 == 24'd8405579
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_vf_bar0_reg_addr_byte0 == 24'd16976
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_vf_bar1_reg_addr_byte0 == 24'd16980
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_vf_bar2_reg_addr_byte0 == 24'd16984
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_vf_bar3_reg_addr_byte0 == 24'd16988
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_vf_bar4_reg_addr_byte0 == 24'd16992
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_vf_bar5_reg_addr_byte0 == 24'd16996
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_vf_device_id_reg_addr_byte2 == 24'd8405574
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_cap_vf_device_id_reg_addr_byte3 == 24'd8405575
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_initial_vfs_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_initial_vfs_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_sup_page_size == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_vf_bar0_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_vf_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_vf_bar0_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_vf_bar0_type == PF4_SRIOV_VF_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_vf_bar1_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_vf_bar1_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_vf_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_vf_bar1_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_vf_bar1_type == PF4_SRIOV_VF_BAR1_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_vf_bar2_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_vf_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_vf_bar2_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_vf_bar2_type == PF4_SRIOV_VF_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_vf_bar3_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_vf_bar3_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_vf_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_vf_bar3_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_vf_bar3_type == PF4_SRIOV_VF_BAR3_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_vf_bar4_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_vf_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_vf_bar4_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_vf_bar4_type == PF4_SRIOV_VF_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_vf_bar5_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_vf_bar5_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_vf_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_vf_bar5_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_vf_bar5_type == PF4_SRIOV_VF_BAR5_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_vf_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_vf_offset_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_vf_offset_position_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_sriov_vf_stride_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_subclass_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_subsys_dev_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_subsys_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_tph_cap_tph_ext_cap_hdr_reg_addr_byte2 == 24'd8405614
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_tph_cap_tph_ext_cap_hdr_reg_addr_byte3 == 24'd8405615
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_tph_cap_tph_req_cap_reg_addr_byte0 == 24'd8405616
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_tph_cap_tph_req_cap_reg_addr_byte1 == 24'd8405617
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_tph_cap_tph_req_cap_reg_addr_byte2 == 24'd8405618
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_tph_cap_tph_req_cap_reg_addr_byte3 == 24'd8405619
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte0 == 24'd10502768
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte1 == 24'd10502769
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte2 == 24'd10502770
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte3 == 24'd10502771
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_tph_req_cap_int_vec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_tph_req_cap_int_vec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_tph_req_cap_reg_rsvdp_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_tph_req_cap_reg_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_tph_req_cap_reg_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_tph_req_cap_reg_vfcomm_cs2_rsvdp_11_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_tph_req_cap_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_tph_req_cap_reg_vfcomm_cs2_rsvdp_3_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_tph_req_cap_st_table_loc_0 == PF4_NOT_IN_TPH_STRUCT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_tph_req_cap_st_table_loc_0_vfcomm_cs2 == PF4_NOT_IN_TPH_STRUCT_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_tph_req_cap_st_table_loc_1 == PF4_NOT_IN_MSIX_TABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_tph_req_cap_st_table_loc_1_vfcomm_cs2 == PF4_NOT_IN_MSIX_TABLE_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_tph_req_cap_st_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_tph_req_cap_st_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_tph_req_cap_ver == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_tph_req_device_spec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_tph_req_device_spec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_tph_req_extended_tph == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_tph_req_extended_tph_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_tph_req_next_ptr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_tph_req_no_st_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_tph_req_no_st_mode_vfcomm_cs2 == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_bar0_mask_reg_addr_byte0 == 24'd2113552
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_bar0_mask_reg_addr_byte1 == 24'd2113553
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_bar0_mask_reg_addr_byte2 == 24'd2113554
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_bar0_mask_reg_addr_byte3 == 24'd2113555
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_bar0_reg_addr_byte0 == 24'd16400
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_bar1_enable_reg_addr_byte0 == 24'd2113556
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_bar1_mask_reg_addr_byte0 == 24'd2113556
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_bar1_mask_reg_addr_byte1 == 24'd2113557
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_bar1_mask_reg_addr_byte2 == 24'd2113558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_bar1_mask_reg_addr_byte3 == 24'd2113559
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_bar1_reg_addr_byte0 == 24'd16404
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_bar2_mask_reg_addr_byte0 == 24'd2113560
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_bar2_mask_reg_addr_byte1 == 24'd2113561
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_bar2_mask_reg_addr_byte2 == 24'd2113562
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_bar2_mask_reg_addr_byte3 == 24'd2113563
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_bar2_reg_addr_byte0 == 24'd16408
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_bar3_enable_reg_addr_byte0 == 24'd2113564
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_bar3_mask_reg_addr_byte0 == 24'd2113564
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_bar3_mask_reg_addr_byte1 == 24'd2113565
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_bar3_mask_reg_addr_byte2 == 24'd2113566
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_bar3_mask_reg_addr_byte3 == 24'd2113567
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_bar3_reg_addr_byte0 == 24'd16412
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_bar4_mask_reg_addr_byte0 == 24'd2113568
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_bar4_mask_reg_addr_byte1 == 24'd2113569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_bar4_mask_reg_addr_byte2 == 24'd2113570
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_bar4_mask_reg_addr_byte3 == 24'd2113571
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_bar4_reg_addr_byte0 == 24'd16416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_bar5_enable_reg_addr_byte0 == 24'd2113572
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_bar5_mask_reg_addr_byte0 == 24'd2113572
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_bar5_mask_reg_addr_byte1 == 24'd2113573
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_bar5_mask_reg_addr_byte2 == 24'd2113574
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_bar5_mask_reg_addr_byte3 == 24'd2113575
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_bar5_reg_addr_byte0 == 24'd16420
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_bist_header_type_latency_cache_line_size_reg_addr_byte2 == 24'd8405006
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_cardbus_cis_ptr_reg_addr_byte0 == 24'd8405032
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_cardbus_cis_ptr_reg_addr_byte1 == 24'd8405033
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_cardbus_cis_ptr_reg_addr_byte2 == 24'd8405034
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_cardbus_cis_ptr_reg_addr_byte3 == 24'd8405035
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_class_code_revision_id_addr_byte0 == 24'd8405000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_class_code_revision_id_addr_byte1 == 24'd8405001
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_class_code_revision_id_addr_byte2 == 24'd8405002
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_class_code_revision_id_addr_byte3 == 24'd8405003
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_device_id_vendor_id_reg_addr_byte0 == 24'd8404992
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_device_id_vendor_id_reg_addr_byte1 == 24'd8404993
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_device_id_vendor_id_reg_addr_byte2 == 24'd8404994
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_device_id_vendor_id_reg_addr_byte3 == 24'd8404995
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_exp_rom_bar_mask_reg_addr_byte0 == 24'd2113584
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_exp_rom_bar_mask_reg_addr_byte1 == 24'd2113585
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_exp_rom_bar_mask_reg_addr_byte2 == 24'd2113586
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_exp_rom_bar_mask_reg_addr_byte3 == 24'd2113587
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_exp_rom_base_addr_reg_addr_byte0 == 24'd16432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_max_latency_min_grant_interrupt_pin_interrupt_line_reg_addr_byte1 == 24'd8405053
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_pci_cap_ptr_reg_addr_byte0 == 24'd8405044
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte0 == 24'd8405036
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte1 == 24'd8405037
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte2 == 24'd8405038
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte3 == 24'd8405039
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_vf_bar0_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_vf_bar1_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_vf_bar2_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_vf_bar3_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_vf_bar4_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_vf_bar5_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_vsecras_cap_rasdp_ext_hdr_off_addr_byte2 == 24'd8406070
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_vsecras_cap_rasdp_ext_hdr_off_addr_byte3 == 24'd8406071
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_vsecras_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf4_vsecras_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_acs_cap_acs_at_block == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_acs_cap_acs_cap_hdr_reg_addr_byte2 == 24'd8409866
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_acs_cap_acs_cap_hdr_reg_addr_byte3 == 24'd8409867
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_acs_cap_acs_capalities_ctrl_reg_addr_byte0 == 24'd8409868
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_acs_cap_acs_capalities_ctrl_reg_addr_byte1 == 24'd21261
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_acs_cap_acs_direct_translated_p2p == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_acs_cap_acs_egress_ctrl_size == 8'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_acs_cap_acs_p2p_cpl_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_acs_cap_acs_p2p_egress_control == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_acs_cap_acs_p2p_req_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_acs_cap_acs_src_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_acs_cap_acs_usp_forwarding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_acs_cap_rsvdp_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_acs_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_acs_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_aer_cap_aer_ext_cap_hdr_off_addr_byte2 == 24'd8409346
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_aer_cap_aer_ext_cap_hdr_off_addr_byte3 == 24'd8409347
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_aer_cap_version == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_aer_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_ari_cap_ari_base_addr_byte2 == 24'd8409462
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_ari_cap_ari_base_addr_byte3 == 24'd8409463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_ari_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_ari_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_ats_cap_ats_cap_hdr_reg_addr_byte2 == 24'd8409850
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_ats_cap_ats_cap_hdr_reg_addr_byte3 == 24'd8409851
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_ats_cap_ats_capabilities_ctrl_reg_addr_byte0 == 24'd8409852
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_ats_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_ats_capabilities_ctrl_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_ats_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_aux_curr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_bar0_mem_io == PF5_BAR0_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_bar0_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_bar0_type == PF5_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_bar1_mem_io == PF5_BAR1_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_bar1_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_bar1_type == PF5_BAR1_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_bar2_mem_io == PF5_BAR2_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_bar2_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_bar2_type == PF5_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_bar3_mem_io == PF5_BAR3_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_bar3_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_bar3_type == PF5_BAR3_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_bar4_mem_io == PF5_BAR4_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_bar4_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_bar4_type == PF5_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_bar5_mem_io == PF5_BAR5_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_bar5_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_bar5_type == PF5_BAR5_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_base_class_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_cap_id_nxt_ptr_reg_rsvdp_20 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_cap_pointer == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_cardbus_cis_pointer == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_con_status_reg_rsvdp_2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_con_status_reg_rsvdp_4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_d1_support == PF5_D1_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_d2_support == PF5_D2_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_10 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_11 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_12 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_13 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_14 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_15 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_16 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_17 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_18 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_19 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_20 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_21 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_22 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_23 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_24 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_25 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_26 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_27 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_28 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_29 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_30 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_31 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_32 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_33 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_34 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_35 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_36 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_37 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_38 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_39 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_40 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_41 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_42 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_43 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_44 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_45 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_46 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_47 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_48 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_49 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_50 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_51 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_52 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_53 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_54 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_55 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_56 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_57 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_58 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_59 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_6 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_60 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_61 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_62 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_63 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_64 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_65 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_7 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_8 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dbi_reserved_9 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_device_capabilities_reg_rsvdp_12 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_device_capabilities_reg_rsvdp_16 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_device_capabilities_reg_rsvdp_29 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_dsi == PF5_NOT_REQUIRED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_exp_rom_bar_mask_reg_rsvdp_1 == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_exp_rom_base_addr_reg_rsvdp_1 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_global_inval_spprtd == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_header_type == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_int_pin == PF5_NO_INT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_invalidate_q_depth == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_link_capabilities_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_link_control_link_status_reg_rsvdp_12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_link_control_link_status_reg_rsvdp_2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_link_control_link_status_reg_rsvdp_26 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_link_control_link_status_reg_rsvdp_9 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte1 == 24'd8409169
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte2 == 24'd8409170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte3 == 24'd8409171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_msi_cap_pci_msi_cap_id_next_ctrl_reg_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_msix_cap_msix_pba_offset_reg_addr_byte0 == 24'd8409272
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_msix_cap_msix_pba_offset_reg_addr_byte1 == 24'd8409273
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_msix_cap_msix_pba_offset_reg_addr_byte2 == 24'd8409274
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_msix_cap_msix_pba_offset_reg_addr_byte3 == 24'd8409275
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_msix_cap_msix_table_offset_reg_addr_byte0 == 24'd8409268
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_msix_cap_msix_table_offset_reg_addr_byte1 == 24'd8409269
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_msix_cap_msix_table_offset_reg_addr_byte2 == 24'd8409270
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_msix_cap_msix_table_offset_reg_addr_byte3 == 24'd8409271
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte1 == 24'd8409265
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte2 == 24'd8409266
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte3 == 24'd8409267
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte2 == 24'd10506418
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte3 == 24'd10506419
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_multi_func == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_no_soft_rst == PF5_INTERNALLY_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_page_aligned_req == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pasid_cap_execute_permission_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pasid_cap_max_pasid_width == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pasid_cap_pasid_cap_cntrl_reg_addr_byte0 == 24'd8409904
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pasid_cap_pasid_cap_cntrl_reg_addr_byte1 == 24'd8409905
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pasid_cap_pasid_ext_hdr_reg_addr_byte2 == 24'd8409902
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pasid_cap_pasid_ext_hdr_reg_addr_byte3 == 24'd8409903
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pasid_cap_privileged_mode_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pasid_cap_rsvdp_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pasid_cap_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pasid_cap_rsvpd_13 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pasid_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pasid_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_msi_64_bit_addr_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_msi_cap_next_offset == 8'd112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_msi_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_msi_ext_data_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_msi_ext_data_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_msi_multiple_msg_cap == PF5_MSI_VEC_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_msi_multiple_msg_en == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_msix_bir == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_msix_cap_id_next_ctrl_reg_rsvdp_27 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_msix_cap_next_offset == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_msix_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_msix_enable_vfcomm_cs2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_msix_function_mask == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_msix_function_mask_vfcomm_cs2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_msix_pba == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_msix_pba_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_msix_table_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_msix_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_msix_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_pvm_support == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_type0_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_type0_bar0_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_type0_bar1_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_type0_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_type0_bar1_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_type0_bar1_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_type0_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_type0_bar2_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_type0_bar3_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_type0_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_type0_bar3_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_type0_bar3_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_type0_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_type0_bar4_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_type0_bar5_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_type0_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_type0_bar5_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_type0_bar5_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_type0_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pci_type0_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_active_state_link_pm_control == PF5_ASPM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_active_state_link_pm_support == PF5_NO_ASPM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_aspm_opt_compliance == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_aux_power_pm_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_clock_power_man == PF5_REFCLK_REMOVE_NOT_OK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_common_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_device_capabilities_reg_addr_byte0 == 24'd8409204
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_device_capabilities_reg_addr_byte1 == 24'd8409205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_device_capabilities_reg_addr_byte3 == 24'd8409207
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_device_control_device_status_addr_byte1 == 24'd8409209
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_dll_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_dll_active_rep_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_en_clk_power_man == PF5_CLKREQ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_en_no_snoop == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_enter_compliance == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_ep_l0s_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_ep_l1_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_ext_tag_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_ext_tag_supp == PF5_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_extended_synch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_flr_cap == PF5_NOT_CAPABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_hw_auto_speed_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvd == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_initiate_flr == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_l0s_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_l1_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_link_auto_bw_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_link_auto_bw_status == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_link_bw_man_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_link_bw_man_status == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_link_bw_not_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_link_capabilities_reg_addr_byte0 == 24'd8409212
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_link_capabilities_reg_addr_byte1 == 24'd8409213
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_link_capabilities_reg_addr_byte2 == 24'd8409214
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_link_capabilities_reg_addr_byte3 == 24'd20607
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_link_control2_link_status2_reg_addr_byte0 == 24'd12603552
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_link_control_link_status_reg_addr_byte0 == 24'd4214912
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_link_control_link_status_reg_addr_byte1 == 24'd12603521
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_link_control_link_status_reg_addr_byte3 == 24'd4214915
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_link_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_link_training == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_max_link_speed == PF5_MAX_2P5GTS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_max_link_width == PF5_X1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_max_payload_size == PF5_PAYLOAD_128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_max_read_req_size == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_nego_link_width == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_next_ptr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte1 == 24'd8409201
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte3 == 24'd8409203
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_phantom_func_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_phantom_func_support == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_port_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_rcb == PF5_RCB_64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_retrain_link == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_role_based_err_report == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_sel_deemphasis == PF5_MINUS_6DB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_slot_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_surprise_down_err_rep_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_target_link_speed == PF5_TRGT_GEN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_cap_tx_margin == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_int_msg_num == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pcie_slot_imp == PF5_NOT_IMPLEMENTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pf0_ari_device_number == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pf0_dbi_ro_wr_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pf0_default_target == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pf0_disable_auto_ltr_clr_msg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pf0_mask_ur_ca_4_trgt1 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pf0_misc_control_1_off_rsvdp_6 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pf0_port_logic_misc_control_1_off_addr_byte0 == 24'd2236
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pf0_simplified_replay_timer == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pf0_tlp_bypass_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pm_cap_cap_id_nxt_ptr_reg_addr_byte1 == 24'd8409153
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pm_cap_cap_id_nxt_ptr_reg_addr_byte2 == 24'd8409154
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pm_cap_cap_id_nxt_ptr_reg_addr_byte3 == 24'd8409155
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pm_cap_con_status_reg_addr_byte0 == 24'd8409156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pm_next_pointer == 8'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pm_spec_ver == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pme_clk == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_pme_support == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_power_state == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_program_interface == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte2 == 24'd8409878
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte3 == 24'd8409879
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_prs_ext_cap_prs_req_capacity_reg_addr_byte0 == 24'd8409884
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_prs_ext_cap_prs_req_capacity_reg_addr_byte1 == 24'd8409885
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_prs_ext_cap_prs_req_capacity_reg_addr_byte2 == 24'd8409886
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_prs_ext_cap_prs_req_capacity_reg_addr_byte3 == 24'd8409887
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_prs_ext_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_prs_ext_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_prs_outstanding_capacity == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_ras_des_cap_event_counter_ctrl_reg_addr_byte0 == 24'd21308
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_ras_des_cap_event_counter_ctrl_reg_g5_addr_byte3 == 24'd8409919
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_ras_des_cap_event_counter_ctrl_reg_g6_addr_byte3 == 24'd8409919
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_ras_des_cap_event_counter_ctrl_reg_g7_addr_byte3 == 24'd8409919
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_ras_des_cap_force_detect_lane == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_ras_des_cap_force_detect_lane_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_ras_des_cap_ras_des_hdr_reg_addr_byte2 == 24'd8409910
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_ras_des_cap_ras_des_hdr_reg_addr_byte3 == 24'd8409911
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_ras_des_cap_sd_control1_reg_addr_byte0 == 24'd8410068
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_ras_des_cap_sd_control1_reg_addr_byte1 == 24'd8410069
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_ras_des_cap_sd_control1_reg_addr_byte2 == 24'd8410070
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_ras_des_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_ras_des_event_counter_en == 8'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_ras_des_event_counter_event_select_g5 == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_ras_des_event_counter_event_select_g6 == 8'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_ras_des_event_counter_event_select_g7 == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_ras_des_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_10_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_11_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_12_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_13_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_14_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_15_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_16_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_17_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_18_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_19_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_20_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_21_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_22_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_23_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_24_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_25_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_26_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_27_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_28_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_29_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_30_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_31_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_32_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_33_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_34_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_35_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_36_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_37_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_38_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_39_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_40_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_41_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_42_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_43_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_44_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_45_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_46_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_47_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_48_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_49_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_50_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_51_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_52_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_53_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_54_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_55_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_56_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_57_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_58_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_59_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_60_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_61_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_62_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_63_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_64_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_65_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_7_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_8_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_reserved_9_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_revision_id == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_rom_bar_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_rom_bar_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_shadow_sriov_vf_stride_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sn_cap_ser_num_reg_dw_1_addr_byte0 == 24'd8409448
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sn_cap_ser_num_reg_dw_1_addr_byte1 == 24'd8409449
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sn_cap_ser_num_reg_dw_1_addr_byte2 == 24'd8409450
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sn_cap_ser_num_reg_dw_1_addr_byte3 == 24'd8409451
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sn_cap_ser_num_reg_dw_2_addr_byte0 == 24'd8409452
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sn_cap_ser_num_reg_dw_2_addr_byte1 == 24'd8409453
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sn_cap_ser_num_reg_dw_2_addr_byte2 == 24'd8409454
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sn_cap_ser_num_reg_dw_2_addr_byte3 == 24'd8409455
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sn_cap_sn_base_addr_byte2 == 24'd8409446
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sn_cap_sn_base_addr_byte3 == 24'd8409447
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sn_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sn_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sn_ser_num_reg_1_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sn_ser_num_reg_2_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_shadow_sriov_initial_vfs_addr_byte0 == 24'd10506808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_shadow_sriov_initial_vfs_addr_byte1 == 24'd10506809
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_shadow_sriov_vf_offset_position_addr_byte0 == 24'd10506816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_shadow_sriov_vf_offset_position_addr_byte1 == 24'd10506817
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_shadow_sriov_vf_offset_position_addr_byte2 == 24'd10506818
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_shadow_sriov_vf_offset_position_addr_byte3 == 24'd10506819
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_shadow_vf_bar0_reg_addr_byte0 == 24'd2118224
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_shadow_vf_bar0_reg_addr_byte1 == 24'd2118225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_shadow_vf_bar0_reg_addr_byte2 == 24'd2118226
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_shadow_vf_bar0_reg_addr_byte3 == 24'd2118227
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_shadow_vf_bar1_reg_addr_byte0 == 24'd2118228
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_shadow_vf_bar1_reg_addr_byte1 == 24'd2118229
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_shadow_vf_bar1_reg_addr_byte2 == 24'd2118230
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_shadow_vf_bar1_reg_addr_byte3 == 24'd2118231
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_shadow_vf_bar2_reg_addr_byte0 == 24'd2118232
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_shadow_vf_bar2_reg_addr_byte1 == 24'd2118233
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_shadow_vf_bar2_reg_addr_byte2 == 24'd2118234
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_shadow_vf_bar2_reg_addr_byte3 == 24'd2118235
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_shadow_vf_bar3_reg_addr_byte0 == 24'd2118236
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_shadow_vf_bar3_reg_addr_byte1 == 24'd2118237
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_shadow_vf_bar3_reg_addr_byte2 == 24'd2118238
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_shadow_vf_bar3_reg_addr_byte3 == 24'd2118239
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_shadow_vf_bar4_reg_addr_byte0 == 24'd2118240
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_shadow_vf_bar4_reg_addr_byte1 == 24'd2118241
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_shadow_vf_bar4_reg_addr_byte2 == 24'd2118242
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_shadow_vf_bar4_reg_addr_byte3 == 24'd2118243
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_shadow_vf_bar5_reg_addr_byte0 == 24'd2118244
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_shadow_vf_bar5_reg_addr_byte1 == 24'd2118245
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_shadow_vf_bar5_reg_addr_byte2 == 24'd2118246
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_shadow_vf_bar5_reg_addr_byte3 == 24'd2118247
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_sriov_bar1_enable_reg_addr_byte0 == 24'd2118228
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_sriov_bar3_enable_reg_addr_byte0 == 24'd2118236
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_sriov_bar5_enable_reg_addr_byte0 == 24'd2118244
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_sriov_base_reg_addr_byte2 == 24'd8409646
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_sriov_base_reg_addr_byte3 == 24'd8409647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_sriov_initial_vfs_addr_byte0 == 24'd8409656
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_sriov_initial_vfs_addr_byte1 == 24'd8409657
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_sriov_vf_offset_position_addr_byte0 == 24'd8409664
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_sriov_vf_offset_position_addr_byte1 == 24'd8409665
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_sriov_vf_offset_position_addr_byte2 == 24'd8409666
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_sriov_vf_offset_position_addr_byte3 == 24'd8409667
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_sup_page_sizes_reg_addr_byte0 == 24'd8409672
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_sup_page_sizes_reg_addr_byte1 == 24'd8409673
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_sup_page_sizes_reg_addr_byte2 == 24'd8409674
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_sup_page_sizes_reg_addr_byte3 == 24'd8409675
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_vf_bar0_reg_addr_byte0 == 24'd21072
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_vf_bar1_reg_addr_byte0 == 24'd21076
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_vf_bar2_reg_addr_byte0 == 24'd21080
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_vf_bar3_reg_addr_byte0 == 24'd21084
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_vf_bar4_reg_addr_byte0 == 24'd21088
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_vf_bar5_reg_addr_byte0 == 24'd21092
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_vf_device_id_reg_addr_byte2 == 24'd8409670
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_cap_vf_device_id_reg_addr_byte3 == 24'd8409671
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_initial_vfs_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_initial_vfs_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_sup_page_size == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_vf_bar0_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_vf_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_vf_bar0_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_vf_bar0_type == PF5_SRIOV_VF_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_vf_bar1_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_vf_bar1_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_vf_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_vf_bar1_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_vf_bar1_type == PF5_SRIOV_VF_BAR1_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_vf_bar2_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_vf_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_vf_bar2_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_vf_bar2_type == PF5_SRIOV_VF_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_vf_bar3_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_vf_bar3_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_vf_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_vf_bar3_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_vf_bar3_type == PF5_SRIOV_VF_BAR3_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_vf_bar4_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_vf_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_vf_bar4_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_vf_bar4_type == PF5_SRIOV_VF_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_vf_bar5_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_vf_bar5_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_vf_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_vf_bar5_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_vf_bar5_type == PF5_SRIOV_VF_BAR5_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_vf_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_vf_offset_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_vf_offset_position_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_sriov_vf_stride_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_subclass_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_subsys_dev_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_subsys_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_tph_cap_tph_ext_cap_hdr_reg_addr_byte2 == 24'd8409710
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_tph_cap_tph_ext_cap_hdr_reg_addr_byte3 == 24'd8409711
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_tph_cap_tph_req_cap_reg_addr_byte0 == 24'd8409712
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_tph_cap_tph_req_cap_reg_addr_byte1 == 24'd8409713
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_tph_cap_tph_req_cap_reg_addr_byte2 == 24'd8409714
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_tph_cap_tph_req_cap_reg_addr_byte3 == 24'd8409715
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte0 == 24'd10506864
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte1 == 24'd10506865
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte2 == 24'd10506866
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte3 == 24'd10506867
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_tph_req_cap_int_vec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_tph_req_cap_int_vec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_tph_req_cap_reg_rsvdp_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_tph_req_cap_reg_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_tph_req_cap_reg_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_tph_req_cap_reg_vfcomm_cs2_rsvdp_11_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_tph_req_cap_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_tph_req_cap_reg_vfcomm_cs2_rsvdp_3_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_tph_req_cap_st_table_loc_0 == PF5_NOT_IN_TPH_STRUCT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_tph_req_cap_st_table_loc_0_vfcomm_cs2 == PF5_NOT_IN_TPH_STRUCT_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_tph_req_cap_st_table_loc_1 == PF5_NOT_IN_MSIX_TABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_tph_req_cap_st_table_loc_1_vfcomm_cs2 == PF5_NOT_IN_MSIX_TABLE_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_tph_req_cap_st_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_tph_req_cap_st_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_tph_req_cap_ver == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_tph_req_device_spec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_tph_req_device_spec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_tph_req_extended_tph == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_tph_req_extended_tph_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_tph_req_next_ptr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_tph_req_no_st_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_tph_req_no_st_mode_vfcomm_cs2 == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_bar0_mask_reg_addr_byte0 == 24'd2117648
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_bar0_mask_reg_addr_byte1 == 24'd2117649
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_bar0_mask_reg_addr_byte2 == 24'd2117650
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_bar0_mask_reg_addr_byte3 == 24'd2117651
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_bar0_reg_addr_byte0 == 24'd20496
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_bar1_enable_reg_addr_byte0 == 24'd2117652
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_bar1_mask_reg_addr_byte0 == 24'd2117652
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_bar1_mask_reg_addr_byte1 == 24'd2117653
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_bar1_mask_reg_addr_byte2 == 24'd2117654
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_bar1_mask_reg_addr_byte3 == 24'd2117655
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_bar1_reg_addr_byte0 == 24'd20500
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_bar2_mask_reg_addr_byte0 == 24'd2117656
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_bar2_mask_reg_addr_byte1 == 24'd2117657
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_bar2_mask_reg_addr_byte2 == 24'd2117658
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_bar2_mask_reg_addr_byte3 == 24'd2117659
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_bar2_reg_addr_byte0 == 24'd20504
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_bar3_enable_reg_addr_byte0 == 24'd2117660
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_bar3_mask_reg_addr_byte0 == 24'd2117660
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_bar3_mask_reg_addr_byte1 == 24'd2117661
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_bar3_mask_reg_addr_byte2 == 24'd2117662
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_bar3_mask_reg_addr_byte3 == 24'd2117663
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_bar3_reg_addr_byte0 == 24'd20508
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_bar4_mask_reg_addr_byte0 == 24'd2117664
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_bar4_mask_reg_addr_byte1 == 24'd2117665
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_bar4_mask_reg_addr_byte2 == 24'd2117666
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_bar4_mask_reg_addr_byte3 == 24'd2117667
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_bar4_reg_addr_byte0 == 24'd20512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_bar5_enable_reg_addr_byte0 == 24'd2117668
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_bar5_mask_reg_addr_byte0 == 24'd2117668
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_bar5_mask_reg_addr_byte1 == 24'd2117669
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_bar5_mask_reg_addr_byte2 == 24'd2117670
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_bar5_mask_reg_addr_byte3 == 24'd2117671
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_bar5_reg_addr_byte0 == 24'd20516
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_bist_header_type_latency_cache_line_size_reg_addr_byte2 == 24'd8409102
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_cardbus_cis_ptr_reg_addr_byte0 == 24'd8409128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_cardbus_cis_ptr_reg_addr_byte1 == 24'd8409129
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_cardbus_cis_ptr_reg_addr_byte2 == 24'd8409130
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_cardbus_cis_ptr_reg_addr_byte3 == 24'd8409131
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_class_code_revision_id_addr_byte0 == 24'd8409096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_class_code_revision_id_addr_byte1 == 24'd8409097
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_class_code_revision_id_addr_byte2 == 24'd8409098
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_class_code_revision_id_addr_byte3 == 24'd8409099
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_device_id_vendor_id_reg_addr_byte0 == 24'd8409088
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_device_id_vendor_id_reg_addr_byte1 == 24'd8409089
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_device_id_vendor_id_reg_addr_byte2 == 24'd8409090
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_device_id_vendor_id_reg_addr_byte3 == 24'd8409091
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_exp_rom_bar_mask_reg_addr_byte0 == 24'd2117680
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_exp_rom_bar_mask_reg_addr_byte1 == 24'd2117681
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_exp_rom_bar_mask_reg_addr_byte2 == 24'd2117682
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_exp_rom_bar_mask_reg_addr_byte3 == 24'd2117683
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_exp_rom_base_addr_reg_addr_byte0 == 24'd20528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_max_latency_min_grant_interrupt_pin_interrupt_line_reg_addr_byte1 == 24'd8409149
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_pci_cap_ptr_reg_addr_byte0 == 24'd8409140
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte0 == 24'd8409132
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte1 == 24'd8409133
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte2 == 24'd8409134
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte3 == 24'd8409135
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_vf_bar0_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_vf_bar1_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_vf_bar2_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_vf_bar3_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_vf_bar4_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_vf_bar5_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_vsecras_cap_rasdp_ext_hdr_off_addr_byte2 == 24'd8410166
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_vsecras_cap_rasdp_ext_hdr_off_addr_byte3 == 24'd8410167
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_vsecras_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf5_vsecras_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_acs_cap_acs_at_block == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_acs_cap_acs_cap_hdr_reg_addr_byte2 == 24'd8413962
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_acs_cap_acs_cap_hdr_reg_addr_byte3 == 24'd8413963
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_acs_cap_acs_capalities_ctrl_reg_addr_byte0 == 24'd8413964
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_acs_cap_acs_capalities_ctrl_reg_addr_byte1 == 24'd25357
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_acs_cap_acs_direct_translated_p2p == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_acs_cap_acs_egress_ctrl_size == 8'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_acs_cap_acs_p2p_cpl_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_acs_cap_acs_p2p_egress_control == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_acs_cap_acs_p2p_req_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_acs_cap_acs_src_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_acs_cap_acs_usp_forwarding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_acs_cap_rsvdp_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_acs_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_acs_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_aer_cap_aer_ext_cap_hdr_off_addr_byte2 == 24'd8413442
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_aer_cap_aer_ext_cap_hdr_off_addr_byte3 == 24'd8413443
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_aer_cap_version == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_aer_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_ari_cap_ari_base_addr_byte2 == 24'd8413558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_ari_cap_ari_base_addr_byte3 == 24'd8413559
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_ari_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_ari_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_ats_cap_ats_cap_hdr_reg_addr_byte2 == 24'd8413946
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_ats_cap_ats_cap_hdr_reg_addr_byte3 == 24'd8413947
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_ats_cap_ats_capabilities_ctrl_reg_addr_byte0 == 24'd8413948
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_ats_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_ats_capabilities_ctrl_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_ats_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_aux_curr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_bar0_mem_io == PF6_BAR0_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_bar0_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_bar0_type == PF6_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_bar1_mem_io == PF6_BAR1_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_bar1_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_bar1_type == PF6_BAR1_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_bar2_mem_io == PF6_BAR2_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_bar2_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_bar2_type == PF6_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_bar3_mem_io == PF6_BAR3_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_bar3_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_bar3_type == PF6_BAR3_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_bar4_mem_io == PF6_BAR4_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_bar4_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_bar4_type == PF6_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_bar5_mem_io == PF6_BAR5_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_bar5_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_bar5_type == PF6_BAR5_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_base_class_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_cap_id_nxt_ptr_reg_rsvdp_20 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_cap_pointer == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_cardbus_cis_pointer == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_con_status_reg_rsvdp_2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_con_status_reg_rsvdp_4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_d1_support == PF6_D1_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_d2_support == PF6_D2_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_10 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_11 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_12 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_13 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_14 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_15 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_16 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_17 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_18 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_19 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_20 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_21 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_22 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_23 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_24 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_25 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_26 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_27 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_28 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_29 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_30 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_31 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_32 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_33 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_34 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_35 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_36 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_37 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_38 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_39 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_40 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_41 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_42 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_43 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_44 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_45 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_46 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_47 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_48 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_49 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_50 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_51 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_52 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_53 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_54 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_55 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_56 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_57 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_58 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_59 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_6 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_60 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_61 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_62 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_63 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_64 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_65 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_7 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_8 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dbi_reserved_9 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_device_capabilities_reg_rsvdp_12 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_device_capabilities_reg_rsvdp_16 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_device_capabilities_reg_rsvdp_29 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_dsi == PF6_NOT_REQUIRED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_exp_rom_bar_mask_reg_rsvdp_1 == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_exp_rom_base_addr_reg_rsvdp_1 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_global_inval_spprtd == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_header_type == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_int_pin == PF6_NO_INT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_invalidate_q_depth == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_link_capabilities_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_link_control_link_status_reg_rsvdp_12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_link_control_link_status_reg_rsvdp_2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_link_control_link_status_reg_rsvdp_26 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_link_control_link_status_reg_rsvdp_9 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte1 == 24'd8413265
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte2 == 24'd8413266
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte3 == 24'd8413267
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_msi_cap_pci_msi_cap_id_next_ctrl_reg_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_msix_cap_msix_pba_offset_reg_addr_byte0 == 24'd8413368
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_msix_cap_msix_pba_offset_reg_addr_byte1 == 24'd8413369
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_msix_cap_msix_pba_offset_reg_addr_byte2 == 24'd8413370
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_msix_cap_msix_pba_offset_reg_addr_byte3 == 24'd8413371
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_msix_cap_msix_table_offset_reg_addr_byte0 == 24'd8413364
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_msix_cap_msix_table_offset_reg_addr_byte1 == 24'd8413365
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_msix_cap_msix_table_offset_reg_addr_byte2 == 24'd8413366
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_msix_cap_msix_table_offset_reg_addr_byte3 == 24'd8413367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte1 == 24'd8413361
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte2 == 24'd8413362
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte3 == 24'd8413363
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte2 == 24'd10510514
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte3 == 24'd10510515
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_multi_func == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_no_soft_rst == PF6_INTERNALLY_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_page_aligned_req == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pasid_cap_execute_permission_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pasid_cap_max_pasid_width == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pasid_cap_pasid_cap_cntrl_reg_addr_byte0 == 24'd8414000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pasid_cap_pasid_cap_cntrl_reg_addr_byte1 == 24'd8414001
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pasid_cap_pasid_ext_hdr_reg_addr_byte2 == 24'd8413998
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pasid_cap_pasid_ext_hdr_reg_addr_byte3 == 24'd8413999
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pasid_cap_privileged_mode_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pasid_cap_rsvdp_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pasid_cap_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pasid_cap_rsvpd_13 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pasid_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pasid_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_msi_64_bit_addr_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_msi_cap_next_offset == 8'd112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_msi_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_msi_ext_data_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_msi_ext_data_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_msi_multiple_msg_cap == PF6_MSI_VEC_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_msi_multiple_msg_en == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_msix_bir == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_msix_cap_id_next_ctrl_reg_rsvdp_27 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_msix_cap_next_offset == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_msix_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_msix_enable_vfcomm_cs2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_msix_function_mask == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_msix_function_mask_vfcomm_cs2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_msix_pba == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_msix_pba_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_msix_table_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_msix_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_msix_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_pvm_support == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_type0_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_type0_bar0_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_type0_bar1_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_type0_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_type0_bar1_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_type0_bar1_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_type0_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_type0_bar2_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_type0_bar3_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_type0_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_type0_bar3_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_type0_bar3_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_type0_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_type0_bar4_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_type0_bar5_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_type0_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_type0_bar5_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_type0_bar5_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_type0_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pci_type0_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_active_state_link_pm_control == PF6_ASPM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_active_state_link_pm_support == PF6_NO_ASPM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_aspm_opt_compliance == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_aux_power_pm_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_clock_power_man == PF6_REFCLK_REMOVE_NOT_OK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_common_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_device_capabilities_reg_addr_byte0 == 24'd8413300
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_device_capabilities_reg_addr_byte1 == 24'd8413301
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_device_capabilities_reg_addr_byte3 == 24'd24695
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_device_control_device_status_addr_byte1 == 24'd8413305
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_dll_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_dll_active_rep_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_en_clk_power_man == PF6_CLKREQ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_en_no_snoop == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_enter_compliance == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_ep_l0s_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_ep_l1_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_ext_tag_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_ext_tag_supp == PF6_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_extended_synch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_flr_cap == PF6_NOT_CAPABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_hw_auto_speed_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvd == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_initiate_flr == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_l0s_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_l1_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_link_auto_bw_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_link_auto_bw_status == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_link_bw_man_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_link_bw_man_status == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_link_bw_not_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_link_capabilities_reg_addr_byte0 == 24'd8413308
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_link_capabilities_reg_addr_byte1 == 24'd8413309
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_link_capabilities_reg_addr_byte2 == 24'd8413310
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_link_capabilities_reg_addr_byte3 == 24'd24703
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_link_control2_link_status2_reg_addr_byte0 == 24'd12607648
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_link_control_link_status_reg_addr_byte0 == 24'd4219008
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_link_control_link_status_reg_addr_byte1 == 24'd12607617
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_link_control_link_status_reg_addr_byte3 == 24'd4219011
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_link_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_link_training == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_max_link_speed == PF6_MAX_2P5GTS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_max_link_width == PF6_X1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_max_payload_size == PF6_PAYLOAD_128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_max_read_req_size == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_nego_link_width == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_next_ptr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte1 == 24'd8413297
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte3 == 24'd8413299
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_phantom_func_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_phantom_func_support == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_port_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_rcb == PF6_RCB_64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_retrain_link == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_role_based_err_report == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_sel_deemphasis == PF6_MINUS_6DB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_slot_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_surprise_down_err_rep_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_target_link_speed == PF6_TRGT_GEN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_cap_tx_margin == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_int_msg_num == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pcie_slot_imp == PF6_NOT_IMPLEMENTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pf0_ari_device_number == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pf0_dbi_ro_wr_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pf0_default_target == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pf0_disable_auto_ltr_clr_msg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pf0_mask_ur_ca_4_trgt1 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pf0_misc_control_1_off_rsvdp_6 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pf0_port_logic_misc_control_1_off_addr_byte0 == 24'd2236
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pf0_simplified_replay_timer == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pf0_tlp_bypass_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pm_cap_cap_id_nxt_ptr_reg_addr_byte1 == 24'd8413249
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pm_cap_cap_id_nxt_ptr_reg_addr_byte2 == 24'd8413250
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pm_cap_cap_id_nxt_ptr_reg_addr_byte3 == 24'd8413251
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pm_cap_con_status_reg_addr_byte0 == 24'd8413252
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pm_next_pointer == 8'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pm_spec_ver == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pme_clk == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_pme_support == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_power_state == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_program_interface == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte2 == 24'd8413974
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte3 == 24'd8413975
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_prs_ext_cap_prs_req_capacity_reg_addr_byte0 == 24'd8413980
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_prs_ext_cap_prs_req_capacity_reg_addr_byte1 == 24'd8413981
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_prs_ext_cap_prs_req_capacity_reg_addr_byte2 == 24'd8413982
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_prs_ext_cap_prs_req_capacity_reg_addr_byte3 == 24'd8413983
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_prs_ext_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_prs_ext_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_prs_outstanding_capacity == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_ras_des_cap_event_counter_ctrl_reg_addr_byte0 == 24'd25404
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_ras_des_cap_event_counter_ctrl_reg_g5_addr_byte3 == 24'd8414015
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_ras_des_cap_event_counter_ctrl_reg_g6_addr_byte3 == 24'd8414015
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_ras_des_cap_event_counter_ctrl_reg_g7_addr_byte3 == 24'd8414015
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_ras_des_cap_force_detect_lane == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_ras_des_cap_force_detect_lane_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_ras_des_cap_ras_des_hdr_reg_addr_byte2 == 24'd8414006
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_ras_des_cap_ras_des_hdr_reg_addr_byte3 == 24'd8414007
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_ras_des_cap_sd_control1_reg_addr_byte0 == 24'd8414164
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_ras_des_cap_sd_control1_reg_addr_byte1 == 24'd8414165
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_ras_des_cap_sd_control1_reg_addr_byte2 == 24'd8414166
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_ras_des_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_ras_des_event_counter_en == 8'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_ras_des_event_counter_event_select_g5 == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_ras_des_event_counter_event_select_g6 == 8'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_ras_des_event_counter_event_select_g7 == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_ras_des_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_10_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_11_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_12_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_13_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_14_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_15_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_16_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_17_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_18_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_19_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_20_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_21_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_22_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_23_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_24_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_25_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_26_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_27_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_28_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_29_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_30_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_31_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_32_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_33_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_34_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_35_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_36_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_37_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_38_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_39_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_40_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_41_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_42_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_43_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_44_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_45_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_46_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_47_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_48_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_49_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_50_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_51_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_52_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_53_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_54_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_55_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_56_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_57_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_58_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_59_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_60_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_61_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_62_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_63_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_64_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_65_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_7_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_8_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_reserved_9_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_revision_id == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_rom_bar_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_rom_bar_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_shadow_sriov_vf_stride_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sn_cap_ser_num_reg_dw_1_addr_byte0 == 24'd8413544
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sn_cap_ser_num_reg_dw_1_addr_byte1 == 24'd8413545
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sn_cap_ser_num_reg_dw_1_addr_byte2 == 24'd8413546
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sn_cap_ser_num_reg_dw_1_addr_byte3 == 24'd8413547
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sn_cap_ser_num_reg_dw_2_addr_byte0 == 24'd8413548
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sn_cap_ser_num_reg_dw_2_addr_byte1 == 24'd8413549
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sn_cap_ser_num_reg_dw_2_addr_byte2 == 24'd8413550
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sn_cap_ser_num_reg_dw_2_addr_byte3 == 24'd8413551
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sn_cap_sn_base_addr_byte2 == 24'd8413542
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sn_cap_sn_base_addr_byte3 == 24'd8413543
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sn_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sn_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sn_ser_num_reg_1_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sn_ser_num_reg_2_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_shadow_sriov_initial_vfs_addr_byte0 == 24'd10510904
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_shadow_sriov_initial_vfs_addr_byte1 == 24'd10510905
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_shadow_sriov_vf_offset_position_addr_byte0 == 24'd10510912
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_shadow_sriov_vf_offset_position_addr_byte1 == 24'd10510913
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_shadow_sriov_vf_offset_position_addr_byte2 == 24'd10510914
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_shadow_sriov_vf_offset_position_addr_byte3 == 24'd10510915
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_shadow_vf_bar0_reg_addr_byte0 == 24'd2122320
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_shadow_vf_bar0_reg_addr_byte1 == 24'd2122321
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_shadow_vf_bar0_reg_addr_byte2 == 24'd2122322
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_shadow_vf_bar0_reg_addr_byte3 == 24'd2122323
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_shadow_vf_bar1_reg_addr_byte0 == 24'd2122324
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_shadow_vf_bar1_reg_addr_byte1 == 24'd2122325
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_shadow_vf_bar1_reg_addr_byte2 == 24'd2122326
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_shadow_vf_bar1_reg_addr_byte3 == 24'd2122327
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_shadow_vf_bar2_reg_addr_byte0 == 24'd2122328
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_shadow_vf_bar2_reg_addr_byte1 == 24'd2122329
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_shadow_vf_bar2_reg_addr_byte2 == 24'd2122330
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_shadow_vf_bar2_reg_addr_byte3 == 24'd2122331
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_shadow_vf_bar3_reg_addr_byte0 == 24'd2122332
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_shadow_vf_bar3_reg_addr_byte1 == 24'd2122333
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_shadow_vf_bar3_reg_addr_byte2 == 24'd2122334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_shadow_vf_bar3_reg_addr_byte3 == 24'd2122335
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_shadow_vf_bar4_reg_addr_byte0 == 24'd2122336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_shadow_vf_bar4_reg_addr_byte1 == 24'd2122337
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_shadow_vf_bar4_reg_addr_byte2 == 24'd2122338
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_shadow_vf_bar4_reg_addr_byte3 == 24'd2122339
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_shadow_vf_bar5_reg_addr_byte0 == 24'd2122340
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_shadow_vf_bar5_reg_addr_byte1 == 24'd2122341
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_shadow_vf_bar5_reg_addr_byte2 == 24'd2122342
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_shadow_vf_bar5_reg_addr_byte3 == 24'd2122343
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_sriov_bar1_enable_reg_addr_byte0 == 24'd2122324
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_sriov_bar3_enable_reg_addr_byte0 == 24'd2122332
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_sriov_bar5_enable_reg_addr_byte0 == 24'd2122340
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_sriov_base_reg_addr_byte2 == 24'd8413742
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_sriov_base_reg_addr_byte3 == 24'd8413743
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_sriov_initial_vfs_addr_byte0 == 24'd8413752
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_sriov_initial_vfs_addr_byte1 == 24'd8413753
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_sriov_vf_offset_position_addr_byte0 == 24'd8413760
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_sriov_vf_offset_position_addr_byte1 == 24'd8413761
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_sriov_vf_offset_position_addr_byte2 == 24'd8413762
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_sriov_vf_offset_position_addr_byte3 == 24'd8413763
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_sup_page_sizes_reg_addr_byte0 == 24'd8413768
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_sup_page_sizes_reg_addr_byte1 == 24'd8413769
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_sup_page_sizes_reg_addr_byte2 == 24'd8413770
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_sup_page_sizes_reg_addr_byte3 == 24'd8413771
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_vf_bar0_reg_addr_byte0 == 24'd25168
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_vf_bar1_reg_addr_byte0 == 24'd25172
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_vf_bar2_reg_addr_byte0 == 24'd25176
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_vf_bar3_reg_addr_byte0 == 24'd25180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_vf_bar4_reg_addr_byte0 == 24'd25184
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_vf_bar5_reg_addr_byte0 == 24'd25188
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_vf_device_id_reg_addr_byte2 == 24'd8413766
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_cap_vf_device_id_reg_addr_byte3 == 24'd8413767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_initial_vfs_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_initial_vfs_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_sup_page_size == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_vf_bar0_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_vf_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_vf_bar0_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_vf_bar0_type == PF6_SRIOV_VF_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_vf_bar1_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_vf_bar1_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_vf_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_vf_bar1_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_vf_bar1_type == PF6_SRIOV_VF_BAR1_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_vf_bar2_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_vf_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_vf_bar2_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_vf_bar2_type == PF6_SRIOV_VF_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_vf_bar3_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_vf_bar3_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_vf_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_vf_bar3_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_vf_bar3_type == PF6_SRIOV_VF_BAR3_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_vf_bar4_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_vf_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_vf_bar4_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_vf_bar4_type == PF6_SRIOV_VF_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_vf_bar5_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_vf_bar5_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_vf_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_vf_bar5_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_vf_bar5_type == PF6_SRIOV_VF_BAR5_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_vf_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_vf_offset_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_vf_offset_position_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_sriov_vf_stride_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_subclass_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_subsys_dev_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_subsys_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_tph_cap_tph_ext_cap_hdr_reg_addr_byte2 == 24'd8413806
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_tph_cap_tph_ext_cap_hdr_reg_addr_byte3 == 24'd8413807
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_tph_cap_tph_req_cap_reg_addr_byte0 == 24'd8413808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_tph_cap_tph_req_cap_reg_addr_byte1 == 24'd8413809
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_tph_cap_tph_req_cap_reg_addr_byte2 == 24'd8413810
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_tph_cap_tph_req_cap_reg_addr_byte3 == 24'd8413811
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte0 == 24'd10510960
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte1 == 24'd10510961
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte2 == 24'd10510962
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte3 == 24'd10510963
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_tph_req_cap_int_vec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_tph_req_cap_int_vec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_tph_req_cap_reg_rsvdp_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_tph_req_cap_reg_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_tph_req_cap_reg_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_tph_req_cap_reg_vfcomm_cs2_rsvdp_11_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_tph_req_cap_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_tph_req_cap_reg_vfcomm_cs2_rsvdp_3_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_tph_req_cap_st_table_loc_0 == PF6_NOT_IN_TPH_STRUCT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_tph_req_cap_st_table_loc_0_vfcomm_cs2 == PF6_NOT_IN_TPH_STRUCT_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_tph_req_cap_st_table_loc_1 == PF6_NOT_IN_MSIX_TABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_tph_req_cap_st_table_loc_1_vfcomm_cs2 == PF6_NOT_IN_MSIX_TABLE_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_tph_req_cap_st_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_tph_req_cap_st_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_tph_req_cap_ver == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_tph_req_device_spec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_tph_req_device_spec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_tph_req_extended_tph == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_tph_req_extended_tph_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_tph_req_next_ptr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_tph_req_no_st_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_tph_req_no_st_mode_vfcomm_cs2 == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_bar0_mask_reg_addr_byte0 == 24'd2121744
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_bar0_mask_reg_addr_byte1 == 24'd2121745
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_bar0_mask_reg_addr_byte2 == 24'd2121746
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_bar0_mask_reg_addr_byte3 == 24'd2121747
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_bar0_reg_addr_byte0 == 24'd24592
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_bar1_enable_reg_addr_byte0 == 24'd2121748
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_bar1_mask_reg_addr_byte0 == 24'd2121748
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_bar1_mask_reg_addr_byte1 == 24'd2121749
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_bar1_mask_reg_addr_byte2 == 24'd2121750
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_bar1_mask_reg_addr_byte3 == 24'd2121751
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_bar1_reg_addr_byte0 == 24'd24596
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_bar2_mask_reg_addr_byte0 == 24'd2121752
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_bar2_mask_reg_addr_byte1 == 24'd2121753
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_bar2_mask_reg_addr_byte2 == 24'd2121754
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_bar2_mask_reg_addr_byte3 == 24'd2121755
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_bar2_reg_addr_byte0 == 24'd24600
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_bar3_enable_reg_addr_byte0 == 24'd2121756
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_bar3_mask_reg_addr_byte0 == 24'd2121756
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_bar3_mask_reg_addr_byte1 == 24'd2121757
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_bar3_mask_reg_addr_byte2 == 24'd2121758
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_bar3_mask_reg_addr_byte3 == 24'd2121759
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_bar3_reg_addr_byte0 == 24'd24604
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_bar4_mask_reg_addr_byte0 == 24'd2121760
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_bar4_mask_reg_addr_byte1 == 24'd2121761
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_bar4_mask_reg_addr_byte2 == 24'd2121762
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_bar4_mask_reg_addr_byte3 == 24'd2121763
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_bar4_reg_addr_byte0 == 24'd24608
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_bar5_enable_reg_addr_byte0 == 24'd2121764
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_bar5_mask_reg_addr_byte0 == 24'd2121764
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_bar5_mask_reg_addr_byte1 == 24'd2121765
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_bar5_mask_reg_addr_byte2 == 24'd2121766
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_bar5_mask_reg_addr_byte3 == 24'd2121767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_bar5_reg_addr_byte0 == 24'd24612
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_bist_header_type_latency_cache_line_size_reg_addr_byte2 == 24'd8413198
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_cardbus_cis_ptr_reg_addr_byte0 == 24'd8413224
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_cardbus_cis_ptr_reg_addr_byte1 == 24'd8413225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_cardbus_cis_ptr_reg_addr_byte2 == 24'd8413226
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_cardbus_cis_ptr_reg_addr_byte3 == 24'd8413227
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_class_code_revision_id_addr_byte0 == 24'd8413192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_class_code_revision_id_addr_byte1 == 24'd8413193
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_class_code_revision_id_addr_byte2 == 24'd8413194
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_class_code_revision_id_addr_byte3 == 24'd8413195
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_device_id_vendor_id_reg_addr_byte0 == 24'd8413184
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_device_id_vendor_id_reg_addr_byte1 == 24'd8413185
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_device_id_vendor_id_reg_addr_byte2 == 24'd8413186
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_device_id_vendor_id_reg_addr_byte3 == 24'd8413187
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_exp_rom_bar_mask_reg_addr_byte0 == 24'd2121776
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_exp_rom_bar_mask_reg_addr_byte1 == 24'd2121777
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_exp_rom_bar_mask_reg_addr_byte2 == 24'd2121778
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_exp_rom_bar_mask_reg_addr_byte3 == 24'd2121779
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_exp_rom_base_addr_reg_addr_byte0 == 24'd24624
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_max_latency_min_grant_interrupt_pin_interrupt_line_reg_addr_byte1 == 24'd8413245
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_pci_cap_ptr_reg_addr_byte0 == 24'd8413236
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte0 == 24'd8413228
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte1 == 24'd8413229
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte2 == 24'd8413230
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte3 == 24'd8413231
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_vf_bar0_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_vf_bar1_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_vf_bar2_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_vf_bar3_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_vf_bar4_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_vf_bar5_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_vsecras_cap_rasdp_ext_hdr_off_addr_byte2 == 24'd8414262
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_vsecras_cap_rasdp_ext_hdr_off_addr_byte3 == 24'd8414263
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_vsecras_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf6_vsecras_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_acs_cap_acs_at_block == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_acs_cap_acs_cap_hdr_reg_addr_byte2 == 24'd8418058
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_acs_cap_acs_cap_hdr_reg_addr_byte3 == 24'd8418059
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_acs_cap_acs_capalities_ctrl_reg_addr_byte0 == 24'd8418060
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_acs_cap_acs_capalities_ctrl_reg_addr_byte1 == 24'd29453
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_acs_cap_acs_direct_translated_p2p == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_acs_cap_acs_egress_ctrl_size == 8'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_acs_cap_acs_p2p_cpl_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_acs_cap_acs_p2p_egress_control == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_acs_cap_acs_p2p_req_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_acs_cap_acs_src_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_acs_cap_acs_usp_forwarding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_acs_cap_rsvdp_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_acs_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_acs_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_aer_cap_aer_ext_cap_hdr_off_addr_byte2 == 24'd8417538
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_aer_cap_aer_ext_cap_hdr_off_addr_byte3 == 24'd8417539
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_aer_cap_version == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_aer_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_ari_cap_ari_base_addr_byte2 == 24'd8417654
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_ari_cap_ari_base_addr_byte3 == 24'd8417655
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_ari_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_ari_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_ats_cap_ats_cap_hdr_reg_addr_byte2 == 24'd8418042
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_ats_cap_ats_cap_hdr_reg_addr_byte3 == 24'd8418043
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_ats_cap_ats_capabilities_ctrl_reg_addr_byte0 == 24'd8418044
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_ats_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_ats_capabilities_ctrl_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_ats_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_aux_curr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_bar0_mem_io == PF7_BAR0_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_bar0_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_bar0_type == PF7_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_bar1_mem_io == PF7_BAR1_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_bar1_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_bar1_type == PF7_BAR1_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_bar2_mem_io == PF7_BAR2_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_bar2_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_bar2_type == PF7_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_bar3_mem_io == PF7_BAR3_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_bar3_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_bar3_type == PF7_BAR3_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_bar4_mem_io == PF7_BAR4_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_bar4_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_bar4_type == PF7_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_bar5_mem_io == PF7_BAR5_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_bar5_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_bar5_type == PF7_BAR5_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_base_class_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_cap_id_nxt_ptr_reg_rsvdp_20 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_cap_pointer == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_cardbus_cis_pointer == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_con_status_reg_rsvdp_2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_con_status_reg_rsvdp_4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_d1_support == PF7_D1_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_d2_support == PF7_D2_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_10 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_11 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_12 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_13 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_14 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_15 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_16 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_17 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_18 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_19 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_20 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_21 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_22 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_23 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_24 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_25 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_26 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_27 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_28 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_29 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_30 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_31 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_32 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_33 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_34 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_35 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_36 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_37 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_38 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_39 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_40 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_41 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_42 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_43 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_44 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_45 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_46 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_47 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_48 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_49 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_50 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_51 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_52 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_53 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_54 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_55 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_56 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_57 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_58 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_59 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_6 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_60 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_61 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_62 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_63 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_64 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_65 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_7 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_8 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dbi_reserved_9 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_device_capabilities_reg_rsvdp_12 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_device_capabilities_reg_rsvdp_16 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_device_capabilities_reg_rsvdp_29 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_dsi == PF7_NOT_REQUIRED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_exp_rom_bar_mask_reg_rsvdp_1 == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_exp_rom_base_addr_reg_rsvdp_1 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_global_inval_spprtd == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_header_type == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_int_pin == PF7_NO_INT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_invalidate_q_depth == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_link_capabilities_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_link_control_link_status_reg_rsvdp_12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_link_control_link_status_reg_rsvdp_2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_link_control_link_status_reg_rsvdp_26 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_link_control_link_status_reg_rsvdp_9 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte1 == 24'd8417361
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte2 == 24'd8417362
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte3 == 24'd8417363
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_msi_cap_pci_msi_cap_id_next_ctrl_reg_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_msix_cap_msix_pba_offset_reg_addr_byte0 == 24'd8417464
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_msix_cap_msix_pba_offset_reg_addr_byte1 == 24'd8417465
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_msix_cap_msix_pba_offset_reg_addr_byte2 == 24'd8417466
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_msix_cap_msix_pba_offset_reg_addr_byte3 == 24'd8417467
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_msix_cap_msix_table_offset_reg_addr_byte0 == 24'd8417460
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_msix_cap_msix_table_offset_reg_addr_byte1 == 24'd8417461
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_msix_cap_msix_table_offset_reg_addr_byte2 == 24'd8417462
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_msix_cap_msix_table_offset_reg_addr_byte3 == 24'd8417463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte1 == 24'd8417457
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte2 == 24'd8417458
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte3 == 24'd8417459
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte2 == 24'd10514610
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte3 == 24'd10514611
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_multi_func == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_no_soft_rst == PF7_INTERNALLY_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_page_aligned_req == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pasid_cap_execute_permission_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pasid_cap_max_pasid_width == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pasid_cap_pasid_cap_cntrl_reg_addr_byte0 == 24'd8418096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pasid_cap_pasid_cap_cntrl_reg_addr_byte1 == 24'd29489
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pasid_cap_pasid_ext_hdr_reg_addr_byte2 == 24'd8418094
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pasid_cap_pasid_ext_hdr_reg_addr_byte3 == 24'd8418095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pasid_cap_privileged_mode_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pasid_cap_rsvdp_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pasid_cap_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pasid_cap_rsvpd_13 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pasid_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pasid_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_msi_64_bit_addr_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_msi_cap_next_offset == 8'd112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_msi_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_msi_ext_data_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_msi_ext_data_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_msi_multiple_msg_cap == PF7_MSI_VEC_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_msi_multiple_msg_en == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_msix_bir == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_msix_cap_id_next_ctrl_reg_rsvdp_27 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_msix_cap_next_offset == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_msix_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_msix_enable_vfcomm_cs2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_msix_function_mask == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_msix_function_mask_vfcomm_cs2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_msix_pba == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_msix_pba_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_msix_table_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_msix_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_msix_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_pvm_support == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_type0_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_type0_bar0_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_type0_bar1_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_type0_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_type0_bar1_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_type0_bar1_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_type0_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_type0_bar2_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_type0_bar3_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_type0_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_type0_bar3_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_type0_bar3_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_type0_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_type0_bar4_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_type0_bar5_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_type0_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_type0_bar5_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_type0_bar5_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_type0_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pci_type0_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_active_state_link_pm_control == PF7_ASPM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_active_state_link_pm_support == PF7_NO_ASPM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_aspm_opt_compliance == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_aux_power_pm_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_clock_power_man == PF7_REFCLK_REMOVE_NOT_OK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_common_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_device_capabilities_reg_addr_byte0 == 24'd8417396
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_device_capabilities_reg_addr_byte1 == 24'd8417397
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_device_capabilities_reg_addr_byte3 == 24'd8417399
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_device_control_device_status_addr_byte1 == 24'd8417401
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_dll_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_dll_active_rep_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_en_clk_power_man == PF7_CLKREQ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_en_no_snoop == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_enter_compliance == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_ep_l0s_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_ep_l1_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_ext_tag_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_ext_tag_supp == PF7_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_extended_synch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_flr_cap == PF7_NOT_CAPABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_hw_auto_speed_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvd == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_initiate_flr == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_l0s_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_l1_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_link_auto_bw_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_link_auto_bw_status == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_link_bw_man_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_link_bw_man_status == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_link_bw_not_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_link_capabilities_reg_addr_byte0 == 24'd8417404
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_link_capabilities_reg_addr_byte1 == 24'd8417405
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_link_capabilities_reg_addr_byte2 == 24'd8417406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_link_capabilities_reg_addr_byte3 == 24'd28799
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_link_control2_link_status2_reg_addr_byte0 == 24'd12611744
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_link_control_link_status_reg_addr_byte0 == 24'd4223104
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_link_control_link_status_reg_addr_byte1 == 24'd12611713
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_link_control_link_status_reg_addr_byte3 == 24'd4223107
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_link_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_link_training == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_max_link_speed == PF7_MAX_2P5GTS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_max_link_width == PF7_X1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_max_payload_size == PF7_PAYLOAD_128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_max_read_req_size == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_nego_link_width == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_next_ptr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte1 == 24'd8417393
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte3 == 24'd8417395
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_phantom_func_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_phantom_func_support == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_port_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_rcb == PF7_RCB_64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_retrain_link == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_role_based_err_report == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_sel_deemphasis == PF7_MINUS_6DB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_slot_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_surprise_down_err_rep_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_target_link_speed == PF7_TRGT_GEN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_cap_tx_margin == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_int_msg_num == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pcie_slot_imp == PF7_NOT_IMPLEMENTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pf0_ari_device_number == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pf0_dbi_ro_wr_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pf0_default_target == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pf0_disable_auto_ltr_clr_msg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pf0_mask_ur_ca_4_trgt1 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pf0_misc_control_1_off_rsvdp_6 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pf0_port_logic_misc_control_1_off_addr_byte0 == 24'd2236
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pf0_simplified_replay_timer == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pf0_tlp_bypass_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pm_cap_cap_id_nxt_ptr_reg_addr_byte1 == 24'd8417345
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pm_cap_cap_id_nxt_ptr_reg_addr_byte2 == 24'd8417346
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pm_cap_cap_id_nxt_ptr_reg_addr_byte3 == 24'd8417347
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pm_cap_con_status_reg_addr_byte0 == 24'd8417348
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pm_next_pointer == 8'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pm_spec_ver == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pme_clk == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_pme_support == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_power_state == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_program_interface == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte2 == 24'd8418070
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte3 == 24'd8418071
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_prs_ext_cap_prs_req_capacity_reg_addr_byte0 == 24'd8418076
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_prs_ext_cap_prs_req_capacity_reg_addr_byte1 == 24'd8418077
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_prs_ext_cap_prs_req_capacity_reg_addr_byte2 == 24'd8418078
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_prs_ext_cap_prs_req_capacity_reg_addr_byte3 == 24'd8418079
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_prs_ext_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_prs_ext_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_prs_outstanding_capacity == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_ras_des_cap_event_counter_ctrl_reg_addr_byte0 == 24'd29500
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_ras_des_cap_event_counter_ctrl_reg_g5_addr_byte3 == 24'd8418111
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_ras_des_cap_event_counter_ctrl_reg_g6_addr_byte3 == 24'd8418111
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_ras_des_cap_event_counter_ctrl_reg_g7_addr_byte3 == 24'd8418111
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_ras_des_cap_force_detect_lane == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_ras_des_cap_force_detect_lane_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_ras_des_cap_ras_des_hdr_reg_addr_byte2 == 24'd8418102
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_ras_des_cap_ras_des_hdr_reg_addr_byte3 == 24'd8418103
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_ras_des_cap_sd_control1_reg_addr_byte0 == 24'd8418260
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_ras_des_cap_sd_control1_reg_addr_byte1 == 24'd8418261
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_ras_des_cap_sd_control1_reg_addr_byte2 == 24'd8418262
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_ras_des_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_ras_des_event_counter_en == 8'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_ras_des_event_counter_event_select_g5 == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_ras_des_event_counter_event_select_g6 == 8'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_ras_des_event_counter_event_select_g7 == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_ras_des_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_10_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_11_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_12_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_13_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_14_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_15_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_16_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_17_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_18_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_19_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_20_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_21_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_22_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_23_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_24_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_25_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_26_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_27_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_28_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_29_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_30_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_31_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_32_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_33_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_34_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_35_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_36_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_37_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_38_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_39_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_40_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_41_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_42_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_43_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_44_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_45_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_46_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_47_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_48_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_49_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_50_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_51_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_52_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_53_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_54_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_55_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_56_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_57_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_58_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_59_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_60_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_61_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_62_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_63_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_64_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_65_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_7_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_8_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_reserved_9_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_revision_id == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_rom_bar_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_rom_bar_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_shadow_sriov_vf_stride_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sn_cap_ser_num_reg_dw_1_addr_byte0 == 24'd8417640
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sn_cap_ser_num_reg_dw_1_addr_byte1 == 24'd8417641
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sn_cap_ser_num_reg_dw_1_addr_byte2 == 24'd8417642
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sn_cap_ser_num_reg_dw_1_addr_byte3 == 24'd8417643
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sn_cap_ser_num_reg_dw_2_addr_byte0 == 24'd8417644
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sn_cap_ser_num_reg_dw_2_addr_byte1 == 24'd8417645
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sn_cap_ser_num_reg_dw_2_addr_byte2 == 24'd8417646
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sn_cap_ser_num_reg_dw_2_addr_byte3 == 24'd8417647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sn_cap_sn_base_addr_byte2 == 24'd8417638
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sn_cap_sn_base_addr_byte3 == 24'd8417639
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sn_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sn_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sn_ser_num_reg_1_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sn_ser_num_reg_2_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_shadow_sriov_initial_vfs_addr_byte0 == 24'd10515000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_shadow_sriov_initial_vfs_addr_byte1 == 24'd10515001
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_shadow_sriov_vf_offset_position_addr_byte0 == 24'd10515008
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_shadow_sriov_vf_offset_position_addr_byte1 == 24'd10515009
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_shadow_sriov_vf_offset_position_addr_byte2 == 24'd10515010
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_shadow_sriov_vf_offset_position_addr_byte3 == 24'd10515011
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_shadow_vf_bar0_reg_addr_byte0 == 24'd2126416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_shadow_vf_bar0_reg_addr_byte1 == 24'd2126417
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_shadow_vf_bar0_reg_addr_byte2 == 24'd2126418
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_shadow_vf_bar0_reg_addr_byte3 == 24'd2126419
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_shadow_vf_bar1_reg_addr_byte0 == 24'd2126420
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_shadow_vf_bar1_reg_addr_byte1 == 24'd2126421
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_shadow_vf_bar1_reg_addr_byte2 == 24'd2126422
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_shadow_vf_bar1_reg_addr_byte3 == 24'd2126423
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_shadow_vf_bar2_reg_addr_byte0 == 24'd2126424
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_shadow_vf_bar2_reg_addr_byte1 == 24'd2126425
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_shadow_vf_bar2_reg_addr_byte2 == 24'd2126426
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_shadow_vf_bar2_reg_addr_byte3 == 24'd2126427
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_shadow_vf_bar3_reg_addr_byte0 == 24'd2126428
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_shadow_vf_bar3_reg_addr_byte1 == 24'd2126429
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_shadow_vf_bar3_reg_addr_byte2 == 24'd2126430
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_shadow_vf_bar3_reg_addr_byte3 == 24'd2126431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_shadow_vf_bar4_reg_addr_byte0 == 24'd2126432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_shadow_vf_bar4_reg_addr_byte1 == 24'd2126433
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_shadow_vf_bar4_reg_addr_byte2 == 24'd2126434
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_shadow_vf_bar4_reg_addr_byte3 == 24'd2126435
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_shadow_vf_bar5_reg_addr_byte0 == 24'd2126436
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_shadow_vf_bar5_reg_addr_byte1 == 24'd2126437
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_shadow_vf_bar5_reg_addr_byte2 == 24'd2126438
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_shadow_vf_bar5_reg_addr_byte3 == 24'd2126439
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_sriov_bar1_enable_reg_addr_byte0 == 24'd2126420
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_sriov_bar3_enable_reg_addr_byte0 == 24'd2126428
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_sriov_bar5_enable_reg_addr_byte0 == 24'd2126436
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_sriov_base_reg_addr_byte2 == 24'd8417838
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_sriov_base_reg_addr_byte3 == 24'd8417839
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_sriov_initial_vfs_addr_byte0 == 24'd8417848
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_sriov_initial_vfs_addr_byte1 == 24'd8417849
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_sriov_vf_offset_position_addr_byte0 == 24'd8417856
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_sriov_vf_offset_position_addr_byte1 == 24'd8417857
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_sriov_vf_offset_position_addr_byte2 == 24'd8417858
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_sriov_vf_offset_position_addr_byte3 == 24'd8417859
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_sup_page_sizes_reg_addr_byte0 == 24'd8417864
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_sup_page_sizes_reg_addr_byte1 == 24'd8417865
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_sup_page_sizes_reg_addr_byte2 == 24'd8417866
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_sup_page_sizes_reg_addr_byte3 == 24'd8417867
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_vf_bar0_reg_addr_byte0 == 24'd29264
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_vf_bar1_reg_addr_byte0 == 24'd29268
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_vf_bar2_reg_addr_byte0 == 24'd29272
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_vf_bar3_reg_addr_byte0 == 24'd29276
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_vf_bar4_reg_addr_byte0 == 24'd29280
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_vf_bar5_reg_addr_byte0 == 24'd29284
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_vf_device_id_reg_addr_byte2 == 24'd8417862
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_cap_vf_device_id_reg_addr_byte3 == 24'd8417863
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_initial_vfs_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_initial_vfs_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_sup_page_size == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_vf_bar0_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_vf_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_vf_bar0_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_vf_bar0_type == PF7_SRIOV_VF_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_vf_bar1_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_vf_bar1_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_vf_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_vf_bar1_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_vf_bar1_type == PF7_SRIOV_VF_BAR1_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_vf_bar2_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_vf_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_vf_bar2_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_vf_bar2_type == PF7_SRIOV_VF_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_vf_bar3_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_vf_bar3_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_vf_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_vf_bar3_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_vf_bar3_type == PF7_SRIOV_VF_BAR3_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_vf_bar4_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_vf_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_vf_bar4_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_vf_bar4_type == PF7_SRIOV_VF_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_vf_bar5_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_vf_bar5_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_vf_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_vf_bar5_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_vf_bar5_type == PF7_SRIOV_VF_BAR5_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_vf_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_vf_offset_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_vf_offset_position_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_sriov_vf_stride_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_subclass_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_subsys_dev_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_subsys_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_tph_cap_tph_ext_cap_hdr_reg_addr_byte2 == 24'd8417902
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_tph_cap_tph_ext_cap_hdr_reg_addr_byte3 == 24'd8417903
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_tph_cap_tph_req_cap_reg_addr_byte0 == 24'd8417904
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_tph_cap_tph_req_cap_reg_addr_byte1 == 24'd8417905
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_tph_cap_tph_req_cap_reg_addr_byte2 == 24'd8417906
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_tph_cap_tph_req_cap_reg_addr_byte3 == 24'd8417907
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte0 == 24'd10515056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte1 == 24'd10515057
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte2 == 24'd10515058
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte3 == 24'd10515059
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_tph_req_cap_int_vec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_tph_req_cap_int_vec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_tph_req_cap_reg_rsvdp_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_tph_req_cap_reg_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_tph_req_cap_reg_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_tph_req_cap_reg_vfcomm_cs2_rsvdp_11_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_tph_req_cap_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_tph_req_cap_reg_vfcomm_cs2_rsvdp_3_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_tph_req_cap_st_table_loc_0 == PF7_NOT_IN_TPH_STRUCT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_tph_req_cap_st_table_loc_0_vfcomm_cs2 == PF7_NOT_IN_TPH_STRUCT_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_tph_req_cap_st_table_loc_1 == PF7_NOT_IN_MSIX_TABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_tph_req_cap_st_table_loc_1_vfcomm_cs2 == PF7_NOT_IN_MSIX_TABLE_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_tph_req_cap_st_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_tph_req_cap_st_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_tph_req_cap_ver == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_tph_req_device_spec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_tph_req_device_spec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_tph_req_extended_tph == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_tph_req_extended_tph_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_tph_req_next_ptr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_tph_req_no_st_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_tph_req_no_st_mode_vfcomm_cs2 == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_bar0_mask_reg_addr_byte0 == 24'd2125840
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_bar0_mask_reg_addr_byte1 == 24'd2125841
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_bar0_mask_reg_addr_byte2 == 24'd2125842
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_bar0_mask_reg_addr_byte3 == 24'd2125843
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_bar0_reg_addr_byte0 == 24'd28688
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_bar1_enable_reg_addr_byte0 == 24'd2125844
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_bar1_mask_reg_addr_byte0 == 24'd2125844
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_bar1_mask_reg_addr_byte1 == 24'd2125845
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_bar1_mask_reg_addr_byte2 == 24'd2125846
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_bar1_mask_reg_addr_byte3 == 24'd2125847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_bar1_reg_addr_byte0 == 24'd28692
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_bar2_mask_reg_addr_byte0 == 24'd2125848
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_bar2_mask_reg_addr_byte1 == 24'd2125849
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_bar2_mask_reg_addr_byte2 == 24'd2125850
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_bar2_mask_reg_addr_byte3 == 24'd2125851
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_bar2_reg_addr_byte0 == 24'd28696
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_bar3_enable_reg_addr_byte0 == 24'd2125852
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_bar3_mask_reg_addr_byte0 == 24'd2125852
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_bar3_mask_reg_addr_byte1 == 24'd2125853
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_bar3_mask_reg_addr_byte2 == 24'd2125854
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_bar3_mask_reg_addr_byte3 == 24'd2125855
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_bar3_reg_addr_byte0 == 24'd28700
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_bar4_mask_reg_addr_byte0 == 24'd2125856
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_bar4_mask_reg_addr_byte1 == 24'd2125857
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_bar4_mask_reg_addr_byte2 == 24'd2125858
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_bar4_mask_reg_addr_byte3 == 24'd2125859
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_bar4_reg_addr_byte0 == 24'd28704
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_bar5_enable_reg_addr_byte0 == 24'd2125860
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_bar5_mask_reg_addr_byte0 == 24'd2125860
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_bar5_mask_reg_addr_byte1 == 24'd2125861
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_bar5_mask_reg_addr_byte2 == 24'd2125862
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_bar5_mask_reg_addr_byte3 == 24'd2125863
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_bar5_reg_addr_byte0 == 24'd28708
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_bist_header_type_latency_cache_line_size_reg_addr_byte2 == 24'd8417294
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_cardbus_cis_ptr_reg_addr_byte0 == 24'd8417320
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_cardbus_cis_ptr_reg_addr_byte1 == 24'd8417321
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_cardbus_cis_ptr_reg_addr_byte2 == 24'd8417322
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_cardbus_cis_ptr_reg_addr_byte3 == 24'd8417323
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_class_code_revision_id_addr_byte0 == 24'd8417288
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_class_code_revision_id_addr_byte1 == 24'd8417289
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_class_code_revision_id_addr_byte2 == 24'd8417290
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_class_code_revision_id_addr_byte3 == 24'd8417291
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_device_id_vendor_id_reg_addr_byte0 == 24'd8417280
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_device_id_vendor_id_reg_addr_byte1 == 24'd8417281
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_device_id_vendor_id_reg_addr_byte2 == 24'd8417282
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_device_id_vendor_id_reg_addr_byte3 == 24'd8417283
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_exp_rom_bar_mask_reg_addr_byte0 == 24'd2125872
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_exp_rom_bar_mask_reg_addr_byte1 == 24'd2125873
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_exp_rom_bar_mask_reg_addr_byte2 == 24'd2125874
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_exp_rom_bar_mask_reg_addr_byte3 == 24'd2125875
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_exp_rom_base_addr_reg_addr_byte0 == 24'd28720
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_max_latency_min_grant_interrupt_pin_interrupt_line_reg_addr_byte1 == 24'd8417341
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_pci_cap_ptr_reg_addr_byte0 == 24'd8417332
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte0 == 24'd8417324
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte1 == 24'd8417325
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte2 == 24'd8417326
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte3 == 24'd8417327
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_vf_bar0_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_vf_bar1_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_vf_bar2_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_vf_bar3_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_vf_bar4_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_vf_bar5_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_vsecras_cap_rasdp_ext_hdr_off_addr_byte2 == 24'd8418358
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_vsecras_cap_rasdp_ext_hdr_off_addr_byte3 == 24'd8418359
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_vsecras_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pf7_vsecras_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pld_aib_loopback_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pld_clk_dis == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pld_crs_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pld_tx_fifo_dyn_empty_dis == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.pldif_fifo_clk_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.rstctl_timer_a == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.rstctl_timer_b == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.rx_lane_flip_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.rxbuf_limit_bypass == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.rxbuf_limit_init == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.rxbuf_pfull_th == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.shadow_select == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.sriov_clk_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.sris_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.test_in_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.tx_cdts_rst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.tx_fifo_empty_threshold_1 == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.tx_fifo_empty_threshold_2 == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.tx_fifo_empty_threshold_3 == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.tx_fifo_empty_threshold_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.tx_fifo_full_threshold == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.tx_lane_flip_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.user_mode_del_count == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.vf == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.vf_select == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_drop_vendor0_msg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_drop_vendor1_msg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_ep_native == NATIVE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_ip_port_num == PCIE_PORT0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_link_rate == GEN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_link_width == X1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_maxpayload_size == MAX_PAYLOAD_128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_num_of_lanes == NUM_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_bar1_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_bar3_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_bar5_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_dlink_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_exvf_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_exvf_aricap_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_exvf_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_exvf_msix_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_exvf_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_exvf_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_io_decode == IO32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_ltr_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_margin_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_msi_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_msix_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_pb_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_pl16g_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_prefetch_decode == PREF64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_sn_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_sriov_num_vf_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_sriov_num_vf_non_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_sriov_vf_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_sriov_vf_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_sriov_vf_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_user_vsec_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf0_vsecras_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf1_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf1_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf1_bar1_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf1_bar3_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf1_bar5_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf1_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf1_exvf_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf1_exvf_aricap_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf1_exvf_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf1_exvf_msix_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf1_exvf_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf1_exvf_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf1_msi_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf1_msix_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf1_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf1_pb_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf1_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf1_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf1_sn_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf1_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf1_sriov_num_vf_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf1_sriov_num_vf_non_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf1_sriov_vf_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf1_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf1_sriov_vf_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf1_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf1_sriov_vf_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf1_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf1_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf1_user_vsec_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf1_user_vsec_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf1_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf1_vsecras_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf2_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf2_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf2_bar1_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf2_bar3_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf2_bar5_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf2_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf2_exvf_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf2_exvf_aricap_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf2_exvf_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf2_exvf_msix_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf2_exvf_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf2_exvf_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf2_msi_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf2_msix_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf2_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf2_pb_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf2_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf2_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf2_sn_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf2_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf2_sriov_num_vf_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf2_sriov_num_vf_non_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf2_sriov_vf_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf2_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf2_sriov_vf_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf2_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf2_sriov_vf_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf2_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf2_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf2_user_vsec_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf2_user_vsec_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf2_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf2_vsecras_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf3_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf3_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf3_bar1_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf3_bar3_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf3_bar5_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf3_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf3_exvf_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf3_exvf_aricap_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf3_exvf_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf3_exvf_msix_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf3_exvf_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf3_exvf_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf3_msi_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf3_msix_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf3_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf3_pb_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf3_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf3_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf3_sn_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf3_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf3_sriov_num_vf_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf3_sriov_num_vf_non_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf3_sriov_vf_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf3_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf3_sriov_vf_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf3_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf3_sriov_vf_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf3_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf3_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf3_user_vsec_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf3_user_vsec_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf3_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf3_vsecras_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf4_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf4_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf4_bar1_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf4_bar3_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf4_bar5_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf4_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf4_exvf_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf4_exvf_aricap_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf4_exvf_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf4_exvf_msix_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf4_exvf_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf4_exvf_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf4_msi_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf4_msix_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf4_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf4_pb_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf4_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf4_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf4_sn_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf4_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf4_sriov_num_vf_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf4_sriov_num_vf_non_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf4_sriov_vf_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf4_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf4_sriov_vf_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf4_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf4_sriov_vf_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf4_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf4_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf4_user_vsec_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf4_user_vsec_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf4_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf4_vsecras_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf5_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf5_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf5_bar1_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf5_bar3_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf5_bar5_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf5_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf5_exvf_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf5_exvf_aricap_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf5_exvf_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf5_exvf_msix_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf5_exvf_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf5_exvf_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf5_msi_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf5_msix_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf5_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf5_pb_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf5_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf5_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf5_sn_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf5_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf5_sriov_num_vf_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf5_sriov_num_vf_non_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf5_sriov_vf_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf5_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf5_sriov_vf_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf5_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf5_sriov_vf_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf5_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf5_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf5_user_vsec_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf5_user_vsec_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf5_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf5_vsecras_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf6_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf6_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf6_bar1_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf6_bar3_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf6_bar5_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf6_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf6_exvf_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf6_exvf_aricap_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf6_exvf_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf6_exvf_msix_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf6_exvf_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf6_exvf_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf6_msi_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf6_msix_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf6_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf6_pb_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf6_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf6_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf6_sn_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf6_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf6_sriov_num_vf_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf6_sriov_num_vf_non_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf6_sriov_vf_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf6_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf6_sriov_vf_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf6_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf6_sriov_vf_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf6_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf6_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf6_user_vsec_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf6_user_vsec_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf6_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf6_vsecras_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf7_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf7_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf7_bar1_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf7_bar3_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf7_bar5_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf7_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf7_exvf_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf7_exvf_aricap_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf7_exvf_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf7_exvf_msix_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf7_exvf_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf7_exvf_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf7_msi_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf7_msix_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf7_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf7_pb_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf7_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf7_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf7_sn_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf7_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf7_sriov_num_vf_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf7_sriov_num_vf_non_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf7_sriov_vf_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf7_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf7_sriov_vf_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf7_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf7_sriov_vf_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf7_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf7_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf7_user_vsec_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf7_user_vsec_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf7_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pf7_vsecras_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_phase23_txpreset == PRESET0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_phase23_txpreset_atg4 == GEN4_PRESET0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_pldclk_rate == SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_ptm_autoupdate == AUTOUPDATE_10MS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_ptm_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_rp_ep_mode == EP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_tlp_bypass_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.virtual_txeq_mode == EQ_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.vsec_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.vsec_select == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core16.wait_pld_warm_rst_rdy == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cfg_bad_dllp_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cfg_bad_tlp_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cfg_blk_crs_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cfg_corrected_internal_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cfg_dbi_pf0_table_size == 12'd319
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cfg_dbi_pf1_start_addr == 12'd384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cfg_dbi_pf1_table_size == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cfg_dbi_pf2_start_addr == 12'd640
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cfg_dbi_pf2_table_size == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cfg_dbi_pf3_start_addr == 12'd896
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cfg_dbi_pf3_table_size == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cfg_dbi_pf4_start_addr == 12'd1152
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cfg_dbi_pf4_table_size == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cfg_dbi_pf5_start_addr == 12'd1408
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cfg_dbi_pf5_table_size == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cfg_dbi_pf6_start_addr == 12'd1664
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cfg_dbi_pf6_table_size == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cfg_dbi_pf7_start_addr == 12'd1920
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cfg_dbi_pf7_table_size == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cfg_dl_protocol_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cfg_ecrc_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cfg_fc_protocol_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cfg_mlf_tlp_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cfg_ram_ecc_chk_val == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cfg_ram_ecc_gen_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cfg_rcvr_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cfg_rcvr_overflow_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cfg_replay_number_rollover_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cfg_replay_timer_timeout_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cfg_surprise_down_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cfg_uncor_internal_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.clrhip_not_rst_sticky == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.crs_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.crs_override_value == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cvp_blocking_dis == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cvp_data_compressed == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cvp_data_encrypted == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cvp_hard_reset_bypass == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cvp_hip_clk_sel_default == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cvp_irq_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cvp_jtag0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cvp_jtag1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cvp_jtag2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cvp_jtag3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cvp_mode_default == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cvp_mode_gating_dis == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cvp_update_no_reset == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cvp_user_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cvp_vsec_id == 16'd4466
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cvp_vsec_rev == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cvp_warm_rst_ready_force_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cvp_warm_rst_ready_force_bit1 == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cvp_warm_rst_req_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.cvp_write_mask_ctl == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.dbg_clk_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.dbi_ro_wr_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.device_type == DEV_NEP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.device_width == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.dyngate_sriov_clk_dis == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.dyngate_vfspfnum_core_clk_dis == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.ecrc_strip == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.ep_signal_mask == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.err_tlp_bypass == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.func_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.gate_clk_in_reset_dis == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.gate_radm_clk_dis == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.gpio_irq == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.intel_marker == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.irq_misc_ctrl == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.margining_ready == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.margining_software_ready == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pcie_parity_bypass == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_ack_n_fts == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_acs_cap_acs_at_block == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_acs_cap_acs_cap_hdr_reg_addr_byte2 == 24'd8389246
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_acs_cap_acs_cap_hdr_reg_addr_byte3 == 24'd8389247
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_acs_cap_acs_capalities_ctrl_reg_addr_byte0 == 24'd8389248
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_acs_cap_acs_capalities_ctrl_reg_addr_byte1 == 24'd641
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_acs_cap_acs_direct_translated_p2p == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_acs_cap_acs_egress_ctrl_size == 8'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_acs_cap_acs_p2p_cpl_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_acs_cap_acs_p2p_egress_control == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_acs_cap_acs_p2p_req_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_acs_cap_acs_src_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_acs_cap_acs_usp_forwarding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_acs_cap_rsvdp_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_acs_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_acs_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_adv_err_int_msg_num == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_aer_cap_aer_ext_cap_hdr_off_addr_byte2 == 24'd8388866
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_aer_cap_aer_ext_cap_hdr_off_addr_byte3 == 24'd8388867
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_aer_cap_root_err_status_off_addr_byte0 == 24'd304
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_aer_cap_version == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_aer_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_ari_acs_fun_grp_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_ari_cap_ari_base_addr_byte2 == 24'd8388982
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_ari_cap_ari_base_addr_byte3 == 24'd8388983
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_ari_cap_cap_reg_addr_byte0 == 24'd8388984
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_ari_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_ari_device_number == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_ari_mfvc_fun_grp_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_ari_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_ats_cap_ats_cap_hdr_reg_addr_byte2 == 24'd8389230
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_ats_cap_ats_cap_hdr_reg_addr_byte3 == 24'd8389231
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_ats_cap_ats_capabilities_ctrl_reg_addr_byte0 == 24'd8389232
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_ats_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_ats_capabilities_ctrl_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_ats_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_auto_eq_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_auto_eq_disable_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_auto_lane_flip_ctrl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_aux_clk_freq == 10'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_aux_clk_freq_off_rsvdp_10 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_aux_curr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_bar0_mem_io == PF0_BAR0_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_bar0_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_bar0_type == PF0_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_bar1_mem_io == PF0_BAR1_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_bar1_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_bar1_type == PF0_BAR1_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_bar2_mem_io == PF0_BAR2_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_bar2_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_bar2_type == PF0_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_bar3_mem_io == PF0_BAR3_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_bar3_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_bar3_type == PF0_BAR3_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_bar4_mem_io == PF0_BAR4_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_bar4_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_bar4_type == PF0_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_bar5_mem_io == PF0_BAR5_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_bar5_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_bar5_type == PF0_BAR5_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_base_class_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_cap_id_nxt_ptr_reg_rsvdp_20 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_cap_pointer == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_cardbus_cis_pointer == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_common_clk_n_fts == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_con_status_reg_rsvdp_2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_con_status_reg_rsvdp_4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_config_limit == 10'd831
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_config_phy_tx_change == PF0_FULL_SWING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_config_tx_comp_rx == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_cross_link_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_cross_link_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_d1_support == PF0_D1_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_d2_support == PF0_D2_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_10 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_11 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_12 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_13 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_14 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_15 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_16 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_17 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_18 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_19 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_20 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_21 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_22 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_23 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_24 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_25 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_26 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_27 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_28 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_29 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_30 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_31 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_32 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_33 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_34 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_35 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_36 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_37 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_38 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_39 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_40 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_41 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_42 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_43 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_44 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_45 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_46 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_47 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_48 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_49 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_50 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_51 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_52 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_53 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_54 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_55 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_56 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_57 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_58 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_59 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_60 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_61 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_62 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_63 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_64 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_65 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_66 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_67 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_68 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_69 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_70 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_71 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_72 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_73 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_8 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_reserved_9 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dbi_ro_wr_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_default_target == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_device_capabilities_reg_rsvdp_12 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_device_capabilities_reg_rsvdp_16 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_device_capabilities_reg_rsvdp_29 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_direct_speed_change == PF0_AUTO_SPEED_CHG
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_disable_auto_ltr_clr_msg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_disable_fc_wd_timer == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_disable_scrambler_gen_3 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_disable_scrambler_gen_3_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dlink_cap_dlink_fea_ext_hdr_off_addr_byte2 == 24'd8389602
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dlink_cap_dlink_fea_ext_hdr_off_addr_byte3 == 24'd8389603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dlink_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dlink_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dll_link_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsi == PF0_NOT_REQUIRED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_16g_tx_preset0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_16g_tx_preset1 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_16g_tx_preset10 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_16g_tx_preset11 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_16g_tx_preset12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_16g_tx_preset13 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_16g_tx_preset14 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_16g_tx_preset15 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_16g_tx_preset2 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_16g_tx_preset3 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_16g_tx_preset4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_16g_tx_preset5 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_16g_tx_preset6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_16g_tx_preset7 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_16g_tx_preset8 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_16g_tx_preset9 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_rx_preset_hint0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_rx_preset_hint1 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_rx_preset_hint10 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_rx_preset_hint11 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_rx_preset_hint12 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_rx_preset_hint13 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_rx_preset_hint14 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_rx_preset_hint15 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_rx_preset_hint2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_rx_preset_hint3 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_rx_preset_hint4 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_rx_preset_hint5 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_rx_preset_hint6 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_rx_preset_hint7 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_rx_preset_hint8 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_rx_preset_hint9 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_tx_preset0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_tx_preset1 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_tx_preset10 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_tx_preset11 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_tx_preset12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_tx_preset13 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_tx_preset14 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_tx_preset15 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_tx_preset2 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_tx_preset3 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_tx_preset4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_tx_preset5 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_tx_preset6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_tx_preset7 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_tx_preset8 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_dsp_tx_preset9 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_eidle_timer == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_eq_eieos_cnt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_eq_eieos_cnt_atg4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_eq_phase_2_3 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_eq_phase_2_3_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_eq_redo == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_eq_redo_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_exp_rom_bar_mask_reg_rsvdp_1 == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_exp_rom_base_addr_reg_rsvdp_1 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_fast_link_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_fast_training_seq == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen1_ei_inference == PF0_USE_RX_EIDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen2_ctrl_off_rsvdp_22 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_dc_balance_disable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_dc_balance_disable_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_dllp_xmt_delay_disable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_dllp_xmt_delay_disable_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_eq_control_off_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_eq_control_off_rsvdp_27_atg4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_eq_control_off_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_eq_control_off_rsvdp_7_atg4 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_eq_eval_2ms_disable == PF0_CONTINUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_eq_eval_2ms_disable_atg4 == PF0_CONTINUE_ATG4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_eq_fb_mode == PF0_FOM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_eq_fb_mode_atg4 == PF0_FOM_ATG4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_eq_fom_inc_initial_eval == PF0_IGNORE_INIT_FOM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_eq_fom_inc_initial_eval_atg4 == PF0_IGNORE_INIT_FOM_ATG4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_eq_invreq_eva_diff_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_eq_invreq_eva_diff_disable_atg4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_eq_phase23_exit_mode == PF0_NEXT_REC_SPEED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_eq_phase23_exit_mode_atg4 == PF0_NEXT_REC_SPEED_ATG4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_eq_pset_req_as_coef == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_eq_pset_req_as_coef_atg4 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_eq_pset_req_vec == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_eq_pset_req_vec_atg4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_equalization_disable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_equalization_disable_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_lower_rate_eq_redo_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_lower_rate_eq_redo_enable_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_related_off_rsvdp_1 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_related_off_rsvdp_14 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_related_off_rsvdp_14_atg4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_related_off_rsvdp_19 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_related_off_rsvdp_19_atg4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_related_off_rsvdp_1_atg4 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_related_off_rsvdp_26 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_related_off_rsvdp_26_atg4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_req_send_consec_eieos_for_pset_map == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_req_send_consec_eieos_for_pset_map_atg4 == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_zrxdc_noncompl == PF0_COMPLIANT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_gen3_zrxdc_noncompl_atg4 == PF0_COMPLIANT_ATG4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_global_inval_spprtd == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_header_type == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_int_pin == PF0_NO_INT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_invalidate_q_depth == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_lane_equalization_control01_reg_rsvdp_15 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_lane_equalization_control01_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_lane_equalization_control01_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_lane_equalization_control01_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_lane_equalization_control1011_reg_rsvdp_15 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_lane_equalization_control1011_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_lane_equalization_control1011_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_lane_equalization_control1011_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_lane_equalization_control1213_reg_rsvdp_15 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_lane_equalization_control1213_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_lane_equalization_control1213_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_lane_equalization_control1213_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_lane_equalization_control1415_reg_rsvdp_15 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_lane_equalization_control1415_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_lane_equalization_control1415_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_lane_equalization_control1415_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_lane_equalization_control23_reg_rsvdp_15 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_lane_equalization_control23_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_lane_equalization_control23_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_lane_equalization_control23_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_lane_equalization_control45_reg_rsvdp_15 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_lane_equalization_control45_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_lane_equalization_control45_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_lane_equalization_control45_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_lane_equalization_control67_reg_rsvdp_15 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_lane_equalization_control67_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_lane_equalization_control67_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_lane_equalization_control67_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_lane_equalization_control89_reg_rsvdp_15 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_lane_equalization_control89_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_lane_equalization_control89_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_lane_equalization_control89_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_link_capabilities_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_link_capable == PF0_CONN_X1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_link_control_link_status_reg_rsvdp_12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_link_control_link_status_reg_rsvdp_2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_link_control_link_status_reg_rsvdp_26 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_link_control_link_status_reg_rsvdp_9 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_link_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_link_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_loopback_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_ltr_cap_ltr_cap_hdr_reg_addr_byte2 == 24'd8389274
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_ltr_cap_ltr_cap_hdr_reg_addr_byte3 == 24'd8389275
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_ltr_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_ltr_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_margin_cap_margin_ext_cap_hdr_reg_addr_byte2 == 24'd8389066
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_margin_cap_margin_ext_cap_hdr_reg_addr_byte3 == 24'd8389067
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_margin_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_margin_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_mask_radm_1 == 16'd8200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_mask_radm_2 == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_mask_ur_ca_4_trgt1 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_max_func_num == PF0_ONE_FUNCTION
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_misc_control_1_off_rsvdp_6 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_misc_control_1_rsvdp_21 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte1 == 24'd8388689
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte2 == 24'd8388690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte3 == 24'd8388691
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_msi_cap_pci_msi_cap_id_next_ctrl_reg_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_msix_cap_msix_pba_offset_reg_addr_byte0 == 24'd8388792
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_msix_cap_msix_pba_offset_reg_addr_byte1 == 24'd8388793
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_msix_cap_msix_pba_offset_reg_addr_byte2 == 24'd8388794
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_msix_cap_msix_pba_offset_reg_addr_byte3 == 24'd8388795
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_msix_cap_msix_table_offset_reg_addr_byte0 == 24'd8388788
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_msix_cap_msix_table_offset_reg_addr_byte1 == 24'd8388789
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_msix_cap_msix_table_offset_reg_addr_byte2 == 24'd8388790
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_msix_cap_msix_table_offset_reg_addr_byte3 == 24'd8388791
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte1 == 24'd8388785
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte2 == 24'd8388786
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte3 == 24'd8388787
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte2 == 24'd10485938
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte3 == 24'd10485939
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_multi_func == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_no_soft_rst == PF0_INTERNALLY_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_num_of_lanes == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_p2p_err_rpt_ctrl == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_p2p_track_cpl_to_reg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_page_aligned_req == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pasid_cap_execute_permission_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pasid_cap_max_pasid_width == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pasid_cap_pasid_cap_cntrl_reg_addr_byte0 == 24'd8389284
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pasid_cap_pasid_cap_cntrl_reg_addr_byte1 == 24'd8389285
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pasid_cap_pasid_ext_hdr_reg_addr_byte2 == 24'd8389282
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pasid_cap_pasid_ext_hdr_reg_addr_byte3 == 24'd8389283
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pasid_cap_privileged_mode_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pasid_cap_rsvdp_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pasid_cap_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pasid_cap_rsvpd_13 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pasid_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pasid_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_msi_64_bit_addr_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_msi_cap_next_offset == 8'd112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_msi_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_msi_ext_data_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_msi_ext_data_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_msi_multiple_msg_cap == PF0_MSI_VEC_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_msi_multiple_msg_en == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_msix_bir == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_msix_cap_id_next_ctrl_reg_rsvdp_27 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_msix_cap_next_offset == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_msix_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_msix_enable_vfcomm_cs2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_msix_function_mask == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_msix_function_mask_vfcomm_cs2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_msix_pba == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_msix_pba_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_msix_table_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_msix_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_msix_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_pvm_support == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_type0_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_type0_bar0_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_type0_bar1_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_type0_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_type0_bar1_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_type0_bar1_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_type0_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_type0_bar2_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_type0_bar3_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_type0_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_type0_bar3_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_type0_bar3_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_type0_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_type0_bar4_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_type0_bar5_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_type0_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_type0_bar5_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_type0_bar5_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_type0_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pci_type0_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_active_state_link_pm_control == PF0_ASPM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_active_state_link_pm_support == PF0_NO_ASPM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_aspm_opt_compliance == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_attention_indicator == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_attention_indicator_button == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_aux_power_pm_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_clock_power_man == PF0_REFCLK_REMOVE_NOT_OK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_common_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_crs_sw_visibility == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_device_capabilities_reg_addr_byte0 == 24'd8388724
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_device_capabilities_reg_addr_byte1 == 24'd8388725
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_device_capabilities_reg_addr_byte3 == 24'd8388727
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_device_control_device_status_addr_byte1 == 24'd8388729
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_dll_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_dll_active_rep_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_electromech_interlock == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_en_clk_power_man == PF0_CLKREQ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_en_no_snoop == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_enter_compliance == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_ep_l0s_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_ep_l1_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_ext_tag_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_ext_tag_supp == PF0_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_extended_synch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_flr_cap == PF0_NOT_CAPABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_hot_plug_capable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_hot_plug_surprise == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_hw_auto_speed_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvd == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_initiate_flr == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_l0s_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_l1_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_link_auto_bw_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_link_auto_bw_status == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_link_bw_man_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_link_bw_man_status == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_link_bw_not_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_link_capabilities_reg_addr_byte0 == 24'd8388732
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_link_capabilities_reg_addr_byte1 == 24'd8388733
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_link_capabilities_reg_addr_byte2 == 24'd8388734
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_link_capabilities_reg_addr_byte3 == 24'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_link_control2_link_status2_reg_addr_byte0 == 24'd12583072
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_link_control_link_status_reg_addr_byte0 == 24'd4194432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_link_control_link_status_reg_addr_byte1 == 24'd12583041
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_link_control_link_status_reg_addr_byte3 == 24'd4194435
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_link_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_link_training == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_max_link_speed == PF0_MAX_2P5GTS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_max_link_width == PF0_X1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_max_payload_size == PF0_PAYLOAD_128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_max_read_req_size == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_mrl_sensor == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_nego_link_width == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_next_ptr == 8'd176
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_no_cmd_cpl_support == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte1 == 24'd8388721
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte3 == 24'd8388723
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_phantom_func_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_phantom_func_support == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_phy_slot_num == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_port_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_power_controller == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_power_indicator == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_rcb == PF0_RCB_64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_retrain_link == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_role_based_err_report == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_root_control_root_capabilities_reg_addr_byte2 == 24'd8388750
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_sel_deemphasis == PF0_MINUS_6DB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_slot_capabilities_reg_addr_byte0 == 24'd132
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_slot_capabilities_reg_addr_byte1 == 24'd133
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_slot_capabilities_reg_addr_byte2 == 24'd134
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_slot_capabilities_reg_addr_byte3 == 24'd135
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_slot_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_slot_power_limit_scale == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_slot_power_limit_value == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_surprise_down_err_rep_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_target_link_speed == PF0_TRGT_GEN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_cap_tx_margin == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_int_msg_num == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pcie_slot_imp == PF0_NOT_IMPLEMENTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pipe_loopback == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pipe_loopback_control_off_rsvdp_27 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pl16g_cap_pl16g_cap_off_20h_reg_addr_byte0 == 24'd452
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pl16g_cap_pl16g_cap_off_20h_reg_addr_byte1 == 24'd453
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pl16g_cap_pl16g_cap_off_20h_reg_addr_byte2 == 24'd454
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pl16g_cap_pl16g_cap_off_20h_reg_addr_byte3 == 24'd455
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pl16g_cap_pl16g_cap_off_24h_reg_addr_byte0 == 24'd452
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pl16g_cap_pl16g_cap_off_24h_reg_addr_byte1 == 24'd453
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pl16g_cap_pl16g_cap_off_24h_reg_addr_byte2 == 24'd454
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pl16g_cap_pl16g_cap_off_24h_reg_addr_byte3 == 24'd455
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pl16g_cap_pl16g_cap_off_28h_reg_addr_byte0 == 24'd452
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pl16g_cap_pl16g_cap_off_28h_reg_addr_byte1 == 24'd453
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pl16g_cap_pl16g_cap_off_28h_reg_addr_byte2 == 24'd454
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pl16g_cap_pl16g_cap_off_28h_reg_addr_byte3 == 24'd455
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pl16g_cap_pl16g_cap_off_2ch_reg_addr_byte0 == 24'd452
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pl16g_cap_pl16g_cap_off_2ch_reg_addr_byte1 == 24'd453
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pl16g_cap_pl16g_cap_off_2ch_reg_addr_byte2 == 24'd454
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pl16g_cap_pl16g_cap_off_2ch_reg_addr_byte3 == 24'd455
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pl16g_cap_pl16g_ext_cap_hdr_reg_addr_byte2 == 24'd8389030
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pl16g_cap_pl16g_ext_cap_hdr_reg_addr_byte3 == 24'd8389031
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pl16g_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pl16g_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pm_cap_cap_id_nxt_ptr_reg_addr_byte1 == 24'd8388673
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pm_cap_cap_id_nxt_ptr_reg_addr_byte2 == 24'd8388674
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pm_cap_cap_id_nxt_ptr_reg_addr_byte3 == 24'd8388675
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pm_cap_con_status_reg_addr_byte0 == 24'd8388676
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pm_next_pointer == 8'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pm_spec_ver == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pme_clk == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pme_support == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_link_ctrl_off_rsvdp_4 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_ack_f_aspm_ctrl_off_addr_byte1 == 24'd8390413
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_ack_f_aspm_ctrl_off_addr_byte2 == 24'd1806
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_aux_clk_freq_off_addr_byte0 == 24'd8391488
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_aux_clk_freq_off_addr_byte1 == 24'd8391489
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_filter_mask_2_off_addr_byte0 == 24'd8390432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_filter_mask_2_off_addr_byte1 == 24'd8390433
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_filter_mask_2_off_addr_byte2 == 24'd8390434
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_filter_mask_2_off_addr_byte3 == 24'd8390435
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_gen2_ctrl_off_addr_byte0 == 24'd8390668
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_gen2_ctrl_off_addr_byte1 == 24'd8390669
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_gen2_ctrl_off_addr_byte2 == 24'd12584974
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_gen3_eq_control_off_addr_byte0 == 24'd8390824
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_gen3_eq_control_off_addr_byte1 == 24'd8390825
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_gen3_eq_control_off_addr_byte2 == 24'd8390826
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_gen3_eq_control_off_addr_byte3 == 24'd8390827
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_gen3_eq_control_off_atg4_addr_byte0 == 24'd8390824
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_gen3_eq_control_off_atg4_addr_byte1 == 24'd8390825
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_gen3_eq_control_off_atg4_addr_byte2 == 24'd8390826
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_gen3_eq_control_off_atg4_addr_byte3 == 24'd8390827
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_gen3_eq_local_fs_lf_off_addr_byte1 == 24'd8390825
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_gen3_related_off_addr_byte0 == 24'd8390800
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_gen3_related_off_addr_byte1 == 24'd8390801
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_gen3_related_off_addr_byte2 == 24'd8390802
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_gen3_related_off_addr_byte3 == 24'd8390803
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_gen3_related_off_atg4_addr_byte0 == 24'd8390800
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_gen3_related_off_atg4_addr_byte1 == 24'd8390801
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_gen3_related_off_atg4_addr_byte2 == 24'd8390802
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_gen3_related_off_atg4_addr_byte3 == 24'd8390803
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_misc_control_1_off_addr_byte0 == 24'd2236
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_misc_control_1_off_addr_byte1 == 24'd2237
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_misc_control_1_off_addr_byte2 == 24'd2238
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_pipe_loopback_control_off_addr_byte3 == 24'd8390843
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_port_force_off_addr_byte0 == 24'd8390408
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_port_link_ctrl_off_addr_byte0 == 24'd8390416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_port_link_ctrl_off_addr_byte2 == 24'd8390418
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_queue_status_off_addr_byte2 == 24'd8390462
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_queue_status_off_addr_byte3 == 24'd8390463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_symbol_timer_filter_1_off_addr_byte0 == 24'd8390428
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_symbol_timer_filter_1_off_addr_byte1 == 24'd8390429
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_symbol_timer_filter_1_off_addr_byte2 == 24'd8390430
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_symbol_timer_filter_1_off_addr_byte3 == 24'd8390431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_timer_ctrl_max_func_num_off_addr_byte0 == 24'd8390424
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_vc0_cpl_rx_q_ctrl_off_addr_byte0 == 24'd8390480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_vc0_cpl_rx_q_ctrl_off_addr_byte1 == 24'd8390481
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_vc0_cpl_rx_q_ctrl_off_addr_byte2 == 24'd8390482
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_vc0_cpl_rx_q_ctrl_off_addr_byte3 == 24'd8390483
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_vc0_np_rx_q_ctrl_off_addr_byte0 == 24'd8390476
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_vc0_np_rx_q_ctrl_off_addr_byte1 == 24'd8390477
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_vc0_np_rx_q_ctrl_off_addr_byte2 == 24'd8390478
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_vc0_p_rx_q_ctrl_off_addr_byte0 == 24'd8390472
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_vc0_p_rx_q_ctrl_off_addr_byte1 == 24'd8390473
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_port_logic_vc0_p_rx_q_ctrl_off_addr_byte2 == 24'd8390474
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_power_state == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_pre_det_lane == PF0_DET_ALL_LANES
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_program_interface == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte2 == 24'd8389258
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte3 == 24'd8389259
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_prs_ext_cap_prs_req_capacity_reg_addr_byte0 == 24'd8389264
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_prs_ext_cap_prs_req_capacity_reg_addr_byte1 == 24'd8389265
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_prs_ext_cap_prs_req_capacity_reg_addr_byte2 == 24'd8389266
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_prs_ext_cap_prs_req_capacity_reg_addr_byte3 == 24'd8389267
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_prs_ext_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_prs_ext_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_prs_outstanding_capacity == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_queue_status_off_rsvdp_29 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_ras_des_cap_event_counter_ctrl_reg_addr_byte0 == 24'd688
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_ras_des_cap_event_counter_ctrl_reg_g5_addr_byte3 == 24'd8389299
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_ras_des_cap_event_counter_ctrl_reg_g6_addr_byte3 == 24'd8389299
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_ras_des_cap_event_counter_ctrl_reg_g7_addr_byte3 == 24'd8389299
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_ras_des_cap_force_detect_lane == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_ras_des_cap_force_detect_lane_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_ras_des_cap_ras_des_hdr_reg_addr_byte2 == 24'd8389290
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_ras_des_cap_ras_des_hdr_reg_addr_byte3 == 24'd8389291
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_ras_des_cap_sd_control1_reg_addr_byte0 == 24'd8389448
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_ras_des_cap_sd_control1_reg_addr_byte1 == 24'd8389449
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_ras_des_cap_sd_control1_reg_addr_byte2 == 24'd8389450
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_ras_des_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_ras_des_event_counter_en == 8'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_ras_des_event_counter_event_select_g5 == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_ras_des_event_counter_event_select_g6 == 8'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_ras_des_event_counter_event_select_g7 == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_ras_des_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_rate_shadow_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_rate_shadow_sel_atg4 == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved10 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved250 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved4 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved6 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved8 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved9 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_10_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_11_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_12_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_13_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_14_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_15_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_16_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_17_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_18_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_19_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_20_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_21_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_22_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_23_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_24_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_25_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_26_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_27_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_28_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_29_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_30_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_31_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_32_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_33_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_34_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_35_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_36_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_37_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_38_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_39_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_40_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_41_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_42_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_43_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_44_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_45_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_46_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_47_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_48_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_49_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_50_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_51_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_52_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_53_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_54_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_55_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_56_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_57_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_58_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_59_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_60_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_61_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_62_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_63_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_64_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_65_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_66_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_67_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_68_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_69_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_70_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_71_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_72_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_73_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reserved_9_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_reset_assert == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_revision_id == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_rom_bar_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_rom_bar_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_root_control_root_capabilities_reg_rsvdp_17 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_root_err_status_off_rsvdp_7 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_rp_exp_rom_bar_mask_reg_rp_rom_rsvdp_1 == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_rp_rom_bar_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_rp_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_rxeq_ph01_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_rxeq_ph01_en_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_rxeq_rgrdless_rxts == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_rxeq_rgrdless_rxts_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_rxstatus_value == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_scramble_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sel_deemphasis == PF0_MINUS_6DB_CTL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_shadow_sriov_vf_stride_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_simplified_replay_timer == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_skp_int_val == 11'd640
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sn_cap_ser_num_reg_dw_1_addr_byte0 == 24'd8388968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sn_cap_ser_num_reg_dw_1_addr_byte1 == 24'd8388969
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sn_cap_ser_num_reg_dw_1_addr_byte2 == 24'd8388970
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sn_cap_ser_num_reg_dw_1_addr_byte3 == 24'd8388971
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sn_cap_ser_num_reg_dw_2_addr_byte0 == 24'd8388972
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sn_cap_ser_num_reg_dw_2_addr_byte1 == 24'd8388973
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sn_cap_ser_num_reg_dw_2_addr_byte2 == 24'd8388974
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sn_cap_ser_num_reg_dw_2_addr_byte3 == 24'd8388975
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sn_cap_sn_base_addr_byte2 == 24'd8388966
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sn_cap_sn_base_addr_byte3 == 24'd8388967
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sn_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sn_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sn_ser_num_reg_1_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sn_ser_num_reg_2_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_spcie_cap_lane_equalization_control01_reg_addr_byte0 == 24'd400
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_spcie_cap_lane_equalization_control01_reg_addr_byte1 == 24'd8389009
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_spcie_cap_lane_equalization_control01_reg_addr_byte2 == 24'd402
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_spcie_cap_lane_equalization_control01_reg_addr_byte3 == 24'd8389011
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_spcie_cap_lane_equalization_control1011_reg_addr_byte0 == 24'd404
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_spcie_cap_lane_equalization_control1011_reg_addr_byte1 == 24'd8389013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_spcie_cap_lane_equalization_control1011_reg_addr_byte2 == 24'd406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_spcie_cap_lane_equalization_control1011_reg_addr_byte3 == 24'd8389015
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_spcie_cap_lane_equalization_control1213_reg_addr_byte0 == 24'd404
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_spcie_cap_lane_equalization_control1213_reg_addr_byte1 == 24'd8389013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_spcie_cap_lane_equalization_control1213_reg_addr_byte2 == 24'd406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_spcie_cap_lane_equalization_control1213_reg_addr_byte3 == 24'd8389015
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_spcie_cap_lane_equalization_control1415_reg_addr_byte0 == 24'd404
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_spcie_cap_lane_equalization_control1415_reg_addr_byte1 == 24'd8389013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_spcie_cap_lane_equalization_control1415_reg_addr_byte2 == 24'd406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_spcie_cap_lane_equalization_control1415_reg_addr_byte3 == 24'd8389015
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_spcie_cap_lane_equalization_control23_reg_addr_byte0 == 24'd404
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_spcie_cap_lane_equalization_control23_reg_addr_byte1 == 24'd8389013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_spcie_cap_lane_equalization_control23_reg_addr_byte2 == 24'd406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_spcie_cap_lane_equalization_control23_reg_addr_byte3 == 24'd8389015
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_spcie_cap_lane_equalization_control45_reg_addr_byte0 == 24'd404
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_spcie_cap_lane_equalization_control45_reg_addr_byte1 == 24'd8389013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_spcie_cap_lane_equalization_control45_reg_addr_byte2 == 24'd406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_spcie_cap_lane_equalization_control45_reg_addr_byte3 == 24'd8389015
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_spcie_cap_lane_equalization_control67_reg_addr_byte0 == 24'd404
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_spcie_cap_lane_equalization_control67_reg_addr_byte1 == 24'd8389013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_spcie_cap_lane_equalization_control67_reg_addr_byte2 == 24'd406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_spcie_cap_lane_equalization_control67_reg_addr_byte3 == 24'd8389015
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_spcie_cap_lane_equalization_control89_reg_addr_byte0 == 24'd404
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_spcie_cap_lane_equalization_control89_reg_addr_byte1 == 24'd8389013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_spcie_cap_lane_equalization_control89_reg_addr_byte2 == 24'd406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_spcie_cap_lane_equalization_control89_reg_addr_byte3 == 24'd8389015
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_spcie_cap_spcie_cap_header_reg_addr_byte2 == 24'd8388998
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_spcie_cap_spcie_cap_header_reg_addr_byte3 == 24'd8388999
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_spcie_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_spcie_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_shadow_sriov_initial_vfs_addr_byte0 == 24'd10486328
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_shadow_sriov_initial_vfs_addr_byte1 == 24'd10486329
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_shadow_sriov_vf_offset_position_addr_byte0 == 24'd10486336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_shadow_sriov_vf_offset_position_addr_byte1 == 24'd10486337
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_shadow_sriov_vf_offset_position_addr_byte2 == 24'd10486338
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_shadow_sriov_vf_offset_position_addr_byte3 == 24'd10486339
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_shadow_vf_bar0_reg_addr_byte0 == 24'd2097744
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_shadow_vf_bar0_reg_addr_byte1 == 24'd2097745
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_shadow_vf_bar0_reg_addr_byte2 == 24'd2097746
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_shadow_vf_bar0_reg_addr_byte3 == 24'd2097747
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_shadow_vf_bar1_reg_addr_byte0 == 24'd2097748
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_shadow_vf_bar1_reg_addr_byte1 == 24'd2097749
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_shadow_vf_bar1_reg_addr_byte2 == 24'd2097750
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_shadow_vf_bar1_reg_addr_byte3 == 24'd2097751
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_shadow_vf_bar2_reg_addr_byte0 == 24'd2097752
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_shadow_vf_bar2_reg_addr_byte1 == 24'd2097753
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_shadow_vf_bar2_reg_addr_byte2 == 24'd2097754
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_shadow_vf_bar2_reg_addr_byte3 == 24'd2097755
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_shadow_vf_bar3_reg_addr_byte0 == 24'd2097756
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_shadow_vf_bar3_reg_addr_byte1 == 24'd2097757
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_shadow_vf_bar3_reg_addr_byte2 == 24'd2097758
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_shadow_vf_bar3_reg_addr_byte3 == 24'd2097759
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_shadow_vf_bar4_reg_addr_byte0 == 24'd2097760
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_shadow_vf_bar4_reg_addr_byte1 == 24'd2097761
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_shadow_vf_bar4_reg_addr_byte2 == 24'd2097762
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_shadow_vf_bar4_reg_addr_byte3 == 24'd2097763
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_shadow_vf_bar5_reg_addr_byte0 == 24'd2097764
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_shadow_vf_bar5_reg_addr_byte1 == 24'd2097765
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_shadow_vf_bar5_reg_addr_byte2 == 24'd2097766
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_shadow_vf_bar5_reg_addr_byte3 == 24'd2097767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_sriov_bar1_enable_reg_addr_byte0 == 24'd2097748
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_sriov_bar3_enable_reg_addr_byte0 == 24'd2097756
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_sriov_bar5_enable_reg_addr_byte0 == 24'd2097764
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_sriov_base_reg_addr_byte2 == 24'd558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_sriov_base_reg_addr_byte3 == 24'd559
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_sriov_initial_vfs_addr_byte0 == 24'd8389176
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_sriov_initial_vfs_addr_byte1 == 24'd8389177
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_sriov_vf_offset_position_addr_byte0 == 24'd8389184
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_sriov_vf_offset_position_addr_byte1 == 24'd8389185
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_sriov_vf_offset_position_addr_byte2 == 24'd8389186
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_sriov_vf_offset_position_addr_byte3 == 24'd8389187
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_sup_page_sizes_reg_addr_byte0 == 24'd8389192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_sup_page_sizes_reg_addr_byte1 == 24'd8389193
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_sup_page_sizes_reg_addr_byte2 == 24'd8389194
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_sup_page_sizes_reg_addr_byte3 == 24'd8389195
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_vf_bar0_reg_addr_byte0 == 24'd592
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_vf_bar1_reg_addr_byte0 == 24'd596
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_vf_bar2_reg_addr_byte0 == 24'd600
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_vf_bar3_reg_addr_byte0 == 24'd604
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_vf_bar4_reg_addr_byte0 == 24'd608
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_vf_bar5_reg_addr_byte0 == 24'd612
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_vf_device_id_reg_addr_byte2 == 24'd8389190
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_cap_vf_device_id_reg_addr_byte3 == 24'd8389191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_initial_vfs_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_initial_vfs_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_sup_page_size == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_vf_bar0_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_vf_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_vf_bar0_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_vf_bar0_type == PF0_SRIOV_VF_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_vf_bar1_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_vf_bar1_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_vf_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_vf_bar1_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_vf_bar1_type == PF0_SRIOV_VF_BAR1_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_vf_bar2_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_vf_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_vf_bar2_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_vf_bar2_type == PF0_SRIOV_VF_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_vf_bar3_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_vf_bar3_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_vf_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_vf_bar3_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_vf_bar3_type == PF0_SRIOV_VF_BAR3_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_vf_bar4_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_vf_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_vf_bar4_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_vf_bar4_type == PF0_SRIOV_VF_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_vf_bar5_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_vf_bar5_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_vf_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_vf_bar5_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_vf_bar5_type == PF0_SRIOV_VF_BAR5_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_vf_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_vf_offset_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_vf_offset_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_sriov_vf_stride_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_subclass_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_subsys_dev_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_subsys_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_target_above_config_limit == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_timer_mod_flow_control == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_timer_mod_flow_control_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_tlp_bypass_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_tph_cap_tph_ext_cap_hdr_reg_addr_byte2 == 24'd8389090
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_tph_cap_tph_ext_cap_hdr_reg_addr_byte3 == 24'd8389091
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_tph_cap_tph_req_cap_reg_addr_byte0 == 24'd8389092
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_tph_cap_tph_req_cap_reg_addr_byte1 == 24'd8389093
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_tph_cap_tph_req_cap_reg_addr_byte2 == 24'd8389094
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_tph_cap_tph_req_cap_reg_addr_byte3 == 24'd8389095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte0 == 24'd10486244
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte1 == 24'd10486245
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte2 == 24'd10486246
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte3 == 24'd10486247
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_tph_req_cap_int_vec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_tph_req_cap_int_vec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_tph_req_cap_reg_rsvdp_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_tph_req_cap_reg_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_tph_req_cap_reg_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_tph_req_cap_reg_vfcomm_cs2_rsvdp_11_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_tph_req_cap_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_tph_req_cap_reg_vfcomm_cs2_rsvdp_3_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_tph_req_cap_st_table_loc_0 == PF0_NOT_IN_TPH_STRUCT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_tph_req_cap_st_table_loc_0_vfcomm_cs2 == PF0_NOT_IN_TPH_STRUCT_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_tph_req_cap_st_table_loc_1 == PF0_NOT_IN_MSIX_TABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_tph_req_cap_st_table_loc_1_vfcomm_cs2 == PF0_NOT_IN_MSIX_TABLE_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_tph_req_cap_st_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_tph_req_cap_st_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_tph_req_cap_ver == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_tph_req_device_spec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_tph_req_device_spec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_tph_req_extended_tph == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_tph_req_extended_tph_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_tph_req_next_ptr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_tph_req_no_st_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_tph_req_no_st_mode_vfcomm_cs2 == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_bar0_mask_reg_addr_byte0 == 24'd2097168
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_bar0_mask_reg_addr_byte1 == 24'd2097169
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_bar0_mask_reg_addr_byte2 == 24'd2097170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_bar0_mask_reg_addr_byte3 == 24'd2097171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_bar0_reg_addr_byte0 == 24'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_bar1_enable_reg_addr_byte0 == 24'd2097172
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_bar1_mask_reg_addr_byte0 == 24'd2097172
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_bar1_mask_reg_addr_byte1 == 24'd2097173
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_bar1_mask_reg_addr_byte2 == 24'd2097174
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_bar1_mask_reg_addr_byte3 == 24'd2097175
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_bar1_reg_addr_byte0 == 24'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_bar2_mask_reg_addr_byte0 == 24'd2097176
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_bar2_mask_reg_addr_byte1 == 24'd2097177
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_bar2_mask_reg_addr_byte2 == 24'd2097178
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_bar2_mask_reg_addr_byte3 == 24'd2097179
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_bar2_reg_addr_byte0 == 24'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_bar3_enable_reg_addr_byte0 == 24'd2097180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_bar3_mask_reg_addr_byte0 == 24'd2097180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_bar3_mask_reg_addr_byte1 == 24'd2097181
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_bar3_mask_reg_addr_byte2 == 24'd2097182
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_bar3_mask_reg_addr_byte3 == 24'd2097183
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_bar3_reg_addr_byte0 == 24'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_bar4_mask_reg_addr_byte0 == 24'd2097184
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_bar4_mask_reg_addr_byte1 == 24'd2097185
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_bar4_mask_reg_addr_byte2 == 24'd2097186
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_bar4_mask_reg_addr_byte3 == 24'd2097187
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_bar4_reg_addr_byte0 == 24'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_bar5_enable_reg_addr_byte0 == 24'd2097188
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_bar5_mask_reg_addr_byte0 == 24'd2097188
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_bar5_mask_reg_addr_byte1 == 24'd2097189
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_bar5_mask_reg_addr_byte2 == 24'd2097190
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_bar5_mask_reg_addr_byte3 == 24'd2097191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_bar5_reg_addr_byte0 == 24'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_bist_header_type_latency_cache_line_size_reg_addr_byte2 == 24'd8388622
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_cardbus_cis_ptr_reg_addr_byte0 == 24'd8388648
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_cardbus_cis_ptr_reg_addr_byte1 == 24'd8388649
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_cardbus_cis_ptr_reg_addr_byte2 == 24'd8388650
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_cardbus_cis_ptr_reg_addr_byte3 == 24'd8388651
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_class_code_revision_id_addr_byte0 == 24'd8388616
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_class_code_revision_id_addr_byte1 == 24'd8388617
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_class_code_revision_id_addr_byte2 == 24'd8388618
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_class_code_revision_id_addr_byte3 == 24'd8388619
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_device_id_vendor_id_reg_addr_byte0 == 24'd8388608
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_device_id_vendor_id_reg_addr_byte1 == 24'd8388609
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_device_id_vendor_id_reg_addr_byte2 == 24'd8388610
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_device_id_vendor_id_reg_addr_byte3 == 24'd8388611
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_exp_rom_bar_mask_reg_addr_byte0 == 24'd2097200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_exp_rom_bar_mask_reg_addr_byte1 == 24'd2097201
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_exp_rom_bar_mask_reg_addr_byte2 == 24'd2097202
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_exp_rom_bar_mask_reg_addr_byte3 == 24'd2097203
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_exp_rom_base_addr_reg_addr_byte0 == 24'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_max_latency_min_grant_interrupt_pin_interrupt_line_reg_addr_byte1 == 24'd8388669
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_pci_cap_ptr_reg_addr_byte0 == 24'd8388660
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_rp_exp_rom_bar_mask_reg_addr_byte0 == 24'd2097208
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_rp_exp_rom_bar_mask_reg_addr_byte1 == 24'd2097209
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_rp_exp_rom_bar_mask_reg_addr_byte2 == 24'd2097210
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_rp_exp_rom_bar_mask_reg_addr_byte3 == 24'd2097211
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte0 == 24'd8388652
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte1 == 24'd8388653
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte2 == 24'd8388654
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte3 == 24'd8388655
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_16g_tx_preset0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_16g_tx_preset1 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_16g_tx_preset10 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_16g_tx_preset11 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_16g_tx_preset12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_16g_tx_preset13 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_16g_tx_preset14 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_16g_tx_preset15 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_16g_tx_preset2 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_16g_tx_preset3 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_16g_tx_preset4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_16g_tx_preset5 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_16g_tx_preset6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_16g_tx_preset7 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_16g_tx_preset8 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_16g_tx_preset9 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_rx_preset_hint0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_rx_preset_hint1 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_rx_preset_hint10 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_rx_preset_hint11 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_rx_preset_hint12 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_rx_preset_hint13 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_rx_preset_hint14 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_rx_preset_hint15 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_rx_preset_hint2 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_rx_preset_hint3 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_rx_preset_hint4 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_rx_preset_hint5 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_rx_preset_hint6 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_rx_preset_hint7 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_rx_preset_hint8 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_rx_preset_hint9 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_send_8gt_eq_ts2_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_send_8gt_eq_ts2_disable_atg4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_tx_preset0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_tx_preset1 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_tx_preset10 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_tx_preset11 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_tx_preset12 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_tx_preset13 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_tx_preset14 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_tx_preset15 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_tx_preset2 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_tx_preset3 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_tx_preset4 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_tx_preset5 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_tx_preset6 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_tx_preset7 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_tx_preset8 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_usp_tx_preset9 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_vc0_cpl_data_credit == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_vc0_cpl_data_scale == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_vc0_cpl_hdr_scale == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_vc0_cpl_header_credit == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_vc0_cpl_tlp_q_mode == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_vc0_np_data_credit == 12'd112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_vc0_np_header_credit == 8'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_vc0_np_tlp_q_mode == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_vc0_p_data_credit == 12'd444
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_vc0_p_header_credit == 8'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_vc0_p_tlp_q_mode == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_vc_cap_vc_base_addr_byte2 == 24'd8388938
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_vc_cap_vc_base_addr_byte3 == 24'd8388939
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_vc_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_vc_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_vendor_specific_dllp_req == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_vf_bar0_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_vf_bar1_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_vf_bar2_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_vf_bar3_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_vf_bar4_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_vf_bar5_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_vsecras_cap_rasdp_ext_hdr_off_addr_byte2 == 24'd8389546
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_vsecras_cap_rasdp_ext_hdr_off_addr_byte3 == 24'd8389547
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_vsecras_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_vsecras_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pld_aib_loopback_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pld_clk_dis == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pld_crs_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pld_tx_fifo_dyn_empty_dis == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pldif_fifo_clk_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.rstctl_timer_a == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.rstctl_timer_b == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.rx_lane_flip_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.rxbuf_limit_bypass == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.rxbuf_limit_init == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.rxbuf_pfull_th == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.shadow_select == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.sriov_clk_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.sris_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.test_in_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.tx_cdts_rst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.tx_fifo_empty_threshold_1 == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.tx_fifo_empty_threshold_2 == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.tx_fifo_empty_threshold_3 == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.tx_fifo_empty_threshold_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.tx_fifo_full_threshold == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.tx_lane_flip_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.user_mode_del_count == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.vf == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.vf_select == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_drop_vendor0_msg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_drop_vendor1_msg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_ep_native == NATIVE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_ip_port_num == PCIE_PORT2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_link_rate == GEN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_link_width == X1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_maxpayload_size == MAX_PAYLOAD_128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_num_of_lanes == NUM_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf0_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf0_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf0_bar1_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf0_bar3_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf0_bar5_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf0_dlink_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf0_io_decode == IO32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf0_ltr_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf0_margin_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf0_msi_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf0_msix_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf0_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf0_pb_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf0_pl16g_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf0_prefetch_decode == PREF64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf0_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf0_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf0_sn_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf0_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf0_sriov_num_vf_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf0_sriov_num_vf_non_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf0_sriov_vf_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf0_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf0_sriov_vf_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf0_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf0_sriov_vf_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf0_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf0_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf0_user_vsec_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf0_vsecras_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf1_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf1_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf1_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf1_pb_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf1_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf1_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf1_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf2_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf2_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf2_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf2_pb_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf2_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf2_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf2_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf3_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf3_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf3_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf3_pb_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf3_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf3_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf3_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf4_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf4_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf4_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf4_pb_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf4_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf4_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf4_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf5_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf5_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf5_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf5_pb_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf5_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf5_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf5_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf6_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf6_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf6_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf6_pb_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf6_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf6_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf6_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf7_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf7_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf7_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf7_pb_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf7_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf7_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pf7_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_phase23_txpreset == PRESET0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_phase23_txpreset_atg4 == GEN4_PRESET0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_pldclk_rate == SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_rp_ep_mode == EP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_tlp_bypass_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.virtual_txeq_mode == EQ_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.vsec_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.vsec_select == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.wait_pld_warm_rst_rdy == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cfg_bad_dllp_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cfg_bad_tlp_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cfg_blk_crs_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cfg_corrected_internal_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cfg_dbi_pf0_table_size == 12'd319
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cfg_dbi_pf1_start_addr == 12'd384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cfg_dbi_pf1_table_size == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cfg_dbi_pf2_start_addr == 12'd640
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cfg_dbi_pf2_table_size == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cfg_dbi_pf3_start_addr == 12'd896
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cfg_dbi_pf3_table_size == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cfg_dbi_pf4_start_addr == 12'd1152
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cfg_dbi_pf4_table_size == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cfg_dbi_pf5_start_addr == 12'd1408
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cfg_dbi_pf5_table_size == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cfg_dbi_pf6_start_addr == 12'd1664
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cfg_dbi_pf6_table_size == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cfg_dbi_pf7_start_addr == 12'd1920
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cfg_dbi_pf7_table_size == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cfg_dl_protocol_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cfg_ecrc_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cfg_fc_protocol_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cfg_mlf_tlp_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cfg_ram_ecc_chk_val == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cfg_ram_ecc_gen_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cfg_rcvr_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cfg_rcvr_overflow_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cfg_replay_number_rollover_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cfg_replay_timer_timeout_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cfg_surprise_down_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cfg_uncor_internal_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.clrhip_not_rst_sticky == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.crs_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.crs_override_value == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cvp_blocking_dis == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cvp_data_compressed == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cvp_data_encrypted == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cvp_hard_reset_bypass == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cvp_hip_clk_sel_default == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cvp_irq_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cvp_jtag0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cvp_jtag1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cvp_jtag2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cvp_jtag3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cvp_mode_default == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cvp_mode_gating_dis == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cvp_update_no_reset == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cvp_user_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cvp_vsec_id == 16'd4466
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cvp_vsec_rev == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cvp_warm_rst_ready_force_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cvp_warm_rst_ready_force_bit1 == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cvp_warm_rst_req_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.cvp_write_mask_ctl == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.dbg_clk_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.dbi_ro_wr_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.device_type == DEV_NEP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.device_width == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.dyngate_sriov_clk_dis == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.dyngate_vfspfnum_core_clk_dis == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.ecrc_strip == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.ep_signal_mask == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.err_tlp_bypass == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.func_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.gate_clk_in_reset_dis == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.gate_radm_clk_dis == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.gpio_irq == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.intel_marker == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.irq_misc_ctrl == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.margining_ready == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.margining_software_ready == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pcie_parity_bypass == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_ack_n_fts == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_acs_cap_acs_at_block == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_acs_cap_acs_cap_hdr_reg_addr_byte2 == 24'd8389246
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_acs_cap_acs_cap_hdr_reg_addr_byte3 == 24'd8389247
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_acs_cap_acs_capalities_ctrl_reg_addr_byte0 == 24'd8389248
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_acs_cap_acs_capalities_ctrl_reg_addr_byte1 == 24'd641
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_acs_cap_acs_direct_translated_p2p == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_acs_cap_acs_egress_ctrl_size == 8'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_acs_cap_acs_p2p_cpl_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_acs_cap_acs_p2p_egress_control == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_acs_cap_acs_p2p_req_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_acs_cap_acs_src_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_acs_cap_acs_usp_forwarding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_acs_cap_rsvdp_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_acs_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_acs_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_adv_err_int_msg_num == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_aer_cap_aer_ext_cap_hdr_off_addr_byte2 == 24'd8388866
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_aer_cap_aer_ext_cap_hdr_off_addr_byte3 == 24'd8388867
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_aer_cap_root_err_status_off_addr_byte0 == 24'd304
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_aer_cap_version == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_aer_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_ari_acs_fun_grp_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_ari_cap_ari_base_addr_byte2 == 24'd8388982
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_ari_cap_ari_base_addr_byte3 == 24'd8388983
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_ari_cap_cap_reg_addr_byte0 == 24'd8388984
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_ari_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_ari_device_number == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_ari_mfvc_fun_grp_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_ari_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_ats_cap_ats_cap_hdr_reg_addr_byte2 == 24'd8389230
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_ats_cap_ats_cap_hdr_reg_addr_byte3 == 24'd8389231
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_ats_cap_ats_capabilities_ctrl_reg_addr_byte0 == 24'd8389232
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_ats_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_ats_capabilities_ctrl_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_ats_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_auto_eq_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_auto_eq_disable_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_auto_lane_flip_ctrl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_aux_clk_freq == 10'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_aux_clk_freq_off_rsvdp_10 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_aux_curr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_bar0_mem_io == PF0_BAR0_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_bar0_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_bar0_type == PF0_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_bar1_mem_io == PF0_BAR1_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_bar1_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_bar1_type == PF0_BAR1_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_bar2_mem_io == PF0_BAR2_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_bar2_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_bar2_type == PF0_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_bar3_mem_io == PF0_BAR3_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_bar3_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_bar3_type == PF0_BAR3_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_bar4_mem_io == PF0_BAR4_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_bar4_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_bar4_type == PF0_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_bar5_mem_io == PF0_BAR5_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_bar5_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_bar5_type == PF0_BAR5_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_base_class_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_cap_id_nxt_ptr_reg_rsvdp_20 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_cap_pointer == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_cardbus_cis_pointer == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_common_clk_n_fts == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_con_status_reg_rsvdp_2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_con_status_reg_rsvdp_4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_config_limit == 10'd831
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_config_phy_tx_change == PF0_FULL_SWING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_config_tx_comp_rx == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_cross_link_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_cross_link_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_d1_support == PF0_D1_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_d2_support == PF0_D2_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_10 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_11 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_12 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_13 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_14 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_15 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_16 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_17 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_18 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_19 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_20 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_21 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_22 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_23 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_24 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_25 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_26 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_27 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_28 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_29 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_30 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_31 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_32 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_33 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_34 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_35 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_36 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_37 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_38 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_39 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_40 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_41 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_42 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_43 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_44 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_45 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_46 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_47 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_48 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_49 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_50 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_51 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_52 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_53 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_54 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_55 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_56 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_57 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_58 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_59 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_60 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_61 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_62 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_63 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_64 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_65 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_66 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_67 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_68 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_69 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_70 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_71 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_72 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_73 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_8 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_reserved_9 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dbi_ro_wr_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_default_target == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_device_capabilities_reg_rsvdp_12 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_device_capabilities_reg_rsvdp_16 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_device_capabilities_reg_rsvdp_29 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_direct_speed_change == PF0_AUTO_SPEED_CHG
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_disable_auto_ltr_clr_msg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_disable_fc_wd_timer == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_disable_scrambler_gen_3 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_disable_scrambler_gen_3_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dlink_cap_dlink_fea_ext_hdr_off_addr_byte2 == 24'd8389602
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dlink_cap_dlink_fea_ext_hdr_off_addr_byte3 == 24'd8389603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dlink_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dlink_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dll_link_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsi == PF0_NOT_REQUIRED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_16g_tx_preset0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_16g_tx_preset1 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_16g_tx_preset10 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_16g_tx_preset11 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_16g_tx_preset12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_16g_tx_preset13 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_16g_tx_preset14 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_16g_tx_preset15 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_16g_tx_preset2 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_16g_tx_preset3 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_16g_tx_preset4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_16g_tx_preset5 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_16g_tx_preset6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_16g_tx_preset7 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_16g_tx_preset8 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_16g_tx_preset9 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_rx_preset_hint0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_rx_preset_hint1 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_rx_preset_hint10 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_rx_preset_hint11 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_rx_preset_hint12 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_rx_preset_hint13 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_rx_preset_hint14 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_rx_preset_hint15 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_rx_preset_hint2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_rx_preset_hint3 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_rx_preset_hint4 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_rx_preset_hint5 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_rx_preset_hint6 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_rx_preset_hint7 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_rx_preset_hint8 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_rx_preset_hint9 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_tx_preset0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_tx_preset1 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_tx_preset10 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_tx_preset11 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_tx_preset12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_tx_preset13 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_tx_preset14 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_tx_preset15 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_tx_preset2 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_tx_preset3 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_tx_preset4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_tx_preset5 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_tx_preset6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_tx_preset7 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_tx_preset8 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_dsp_tx_preset9 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_eidle_timer == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_eq_eieos_cnt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_eq_eieos_cnt_atg4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_eq_phase_2_3 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_eq_phase_2_3_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_eq_redo == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_eq_redo_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_exp_rom_bar_mask_reg_rsvdp_1 == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_exp_rom_base_addr_reg_rsvdp_1 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_fast_link_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_fast_training_seq == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen1_ei_inference == PF0_USE_RX_EIDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen2_ctrl_off_rsvdp_22 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_dc_balance_disable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_dc_balance_disable_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_dllp_xmt_delay_disable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_dllp_xmt_delay_disable_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_eq_control_off_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_eq_control_off_rsvdp_27_atg4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_eq_control_off_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_eq_control_off_rsvdp_7_atg4 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_eq_eval_2ms_disable == PF0_CONTINUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_eq_eval_2ms_disable_atg4 == PF0_CONTINUE_ATG4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_eq_fb_mode == PF0_FOM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_eq_fb_mode_atg4 == PF0_FOM_ATG4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_eq_fom_inc_initial_eval == PF0_IGNORE_INIT_FOM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_eq_fom_inc_initial_eval_atg4 == PF0_IGNORE_INIT_FOM_ATG4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_eq_invreq_eva_diff_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_eq_invreq_eva_diff_disable_atg4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_eq_phase23_exit_mode == PF0_NEXT_REC_SPEED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_eq_phase23_exit_mode_atg4 == PF0_NEXT_REC_SPEED_ATG4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_eq_pset_req_as_coef == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_eq_pset_req_as_coef_atg4 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_eq_pset_req_vec == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_eq_pset_req_vec_atg4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_equalization_disable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_equalization_disable_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_lower_rate_eq_redo_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_lower_rate_eq_redo_enable_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_related_off_rsvdp_1 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_related_off_rsvdp_14 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_related_off_rsvdp_14_atg4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_related_off_rsvdp_19 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_related_off_rsvdp_19_atg4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_related_off_rsvdp_1_atg4 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_related_off_rsvdp_26 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_related_off_rsvdp_26_atg4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_req_send_consec_eieos_for_pset_map == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_req_send_consec_eieos_for_pset_map_atg4 == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_zrxdc_noncompl == PF0_COMPLIANT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_gen3_zrxdc_noncompl_atg4 == PF0_COMPLIANT_ATG4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_global_inval_spprtd == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_header_type == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_int_pin == PF0_NO_INT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_invalidate_q_depth == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_lane_equalization_control01_reg_rsvdp_15 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_lane_equalization_control01_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_lane_equalization_control01_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_lane_equalization_control01_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_lane_equalization_control1011_reg_rsvdp_15 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_lane_equalization_control1011_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_lane_equalization_control1011_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_lane_equalization_control1011_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_lane_equalization_control1213_reg_rsvdp_15 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_lane_equalization_control1213_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_lane_equalization_control1213_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_lane_equalization_control1213_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_lane_equalization_control1415_reg_rsvdp_15 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_lane_equalization_control1415_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_lane_equalization_control1415_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_lane_equalization_control1415_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_lane_equalization_control23_reg_rsvdp_15 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_lane_equalization_control23_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_lane_equalization_control23_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_lane_equalization_control23_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_lane_equalization_control45_reg_rsvdp_15 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_lane_equalization_control45_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_lane_equalization_control45_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_lane_equalization_control45_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_lane_equalization_control67_reg_rsvdp_15 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_lane_equalization_control67_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_lane_equalization_control67_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_lane_equalization_control67_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_lane_equalization_control89_reg_rsvdp_15 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_lane_equalization_control89_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_lane_equalization_control89_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_lane_equalization_control89_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_link_capabilities_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_link_capable == PF0_CONN_X1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_link_control_link_status_reg_rsvdp_12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_link_control_link_status_reg_rsvdp_2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_link_control_link_status_reg_rsvdp_26 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_link_control_link_status_reg_rsvdp_9 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_link_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_link_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_loopback_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_ltr_cap_ltr_cap_hdr_reg_addr_byte2 == 24'd8389274
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_ltr_cap_ltr_cap_hdr_reg_addr_byte3 == 24'd8389275
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_ltr_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_ltr_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_margin_cap_margin_ext_cap_hdr_reg_addr_byte2 == 24'd8389066
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_margin_cap_margin_ext_cap_hdr_reg_addr_byte3 == 24'd8389067
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_margin_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_margin_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_mask_radm_1 == 16'd8200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_mask_radm_2 == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_mask_ur_ca_4_trgt1 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_max_func_num == PF0_ONE_FUNCTION
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_misc_control_1_off_rsvdp_6 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_misc_control_1_rsvdp_21 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte1 == 24'd8388689
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte2 == 24'd8388690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte3 == 24'd8388691
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_msi_cap_pci_msi_cap_id_next_ctrl_reg_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_msix_cap_msix_pba_offset_reg_addr_byte0 == 24'd8388792
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_msix_cap_msix_pba_offset_reg_addr_byte1 == 24'd8388793
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_msix_cap_msix_pba_offset_reg_addr_byte2 == 24'd8388794
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_msix_cap_msix_pba_offset_reg_addr_byte3 == 24'd8388795
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_msix_cap_msix_table_offset_reg_addr_byte0 == 24'd8388788
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_msix_cap_msix_table_offset_reg_addr_byte1 == 24'd8388789
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_msix_cap_msix_table_offset_reg_addr_byte2 == 24'd8388790
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_msix_cap_msix_table_offset_reg_addr_byte3 == 24'd8388791
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte1 == 24'd8388785
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte2 == 24'd8388786
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte3 == 24'd8388787
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte2 == 24'd10485938
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte3 == 24'd10485939
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_multi_func == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_no_soft_rst == PF0_INTERNALLY_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_num_of_lanes == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_p2p_err_rpt_ctrl == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_p2p_track_cpl_to_reg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_page_aligned_req == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pasid_cap_execute_permission_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pasid_cap_max_pasid_width == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pasid_cap_pasid_cap_cntrl_reg_addr_byte0 == 24'd8389284
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pasid_cap_pasid_cap_cntrl_reg_addr_byte1 == 24'd8389285
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pasid_cap_pasid_ext_hdr_reg_addr_byte2 == 24'd8389282
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pasid_cap_pasid_ext_hdr_reg_addr_byte3 == 24'd8389283
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pasid_cap_privileged_mode_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pasid_cap_rsvdp_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pasid_cap_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pasid_cap_rsvpd_13 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pasid_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pasid_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_msi_64_bit_addr_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_msi_cap_next_offset == 8'd112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_msi_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_msi_ext_data_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_msi_ext_data_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_msi_multiple_msg_cap == PF0_MSI_VEC_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_msi_multiple_msg_en == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_msix_bir == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_msix_cap_id_next_ctrl_reg_rsvdp_27 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_msix_cap_next_offset == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_msix_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_msix_enable_vfcomm_cs2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_msix_function_mask == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_msix_function_mask_vfcomm_cs2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_msix_pba == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_msix_pba_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_msix_table_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_msix_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_msix_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_pvm_support == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_type0_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_type0_bar0_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_type0_bar1_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_type0_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_type0_bar1_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_type0_bar1_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_type0_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_type0_bar2_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_type0_bar3_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_type0_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_type0_bar3_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_type0_bar3_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_type0_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_type0_bar4_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_type0_bar5_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_type0_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_type0_bar5_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_type0_bar5_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_type0_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pci_type0_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_active_state_link_pm_control == PF0_ASPM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_active_state_link_pm_support == PF0_NO_ASPM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_aspm_opt_compliance == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_attention_indicator == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_attention_indicator_button == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_aux_power_pm_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_clock_power_man == PF0_REFCLK_REMOVE_NOT_OK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_common_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_crs_sw_visibility == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_device_capabilities_reg_addr_byte0 == 24'd8388724
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_device_capabilities_reg_addr_byte1 == 24'd8388725
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_device_capabilities_reg_addr_byte3 == 24'd8388727
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_device_control_device_status_addr_byte1 == 24'd8388729
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_dll_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_dll_active_rep_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_electromech_interlock == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_en_clk_power_man == PF0_CLKREQ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_en_no_snoop == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_enter_compliance == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_ep_l0s_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_ep_l1_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_ext_tag_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_ext_tag_supp == PF0_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_extended_synch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_flr_cap == PF0_NOT_CAPABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_hot_plug_capable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_hot_plug_surprise == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_hw_auto_speed_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvd == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_initiate_flr == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_l0s_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_l1_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_link_auto_bw_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_link_auto_bw_status == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_link_bw_man_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_link_bw_man_status == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_link_bw_not_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_link_capabilities_reg_addr_byte0 == 24'd8388732
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_link_capabilities_reg_addr_byte1 == 24'd8388733
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_link_capabilities_reg_addr_byte2 == 24'd8388734
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_link_capabilities_reg_addr_byte3 == 24'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_link_control2_link_status2_reg_addr_byte0 == 24'd12583072
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_link_control_link_status_reg_addr_byte0 == 24'd4194432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_link_control_link_status_reg_addr_byte1 == 24'd12583041
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_link_control_link_status_reg_addr_byte3 == 24'd4194435
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_link_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_link_training == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_max_link_speed == PF0_MAX_2P5GTS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_max_link_width == PF0_X1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_max_payload_size == PF0_PAYLOAD_128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_max_read_req_size == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_mrl_sensor == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_nego_link_width == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_next_ptr == 8'd176
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_no_cmd_cpl_support == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte1 == 24'd8388721
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte3 == 24'd8388723
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_phantom_func_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_phantom_func_support == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_phy_slot_num == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_port_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_power_controller == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_power_indicator == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_rcb == PF0_RCB_64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_retrain_link == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_role_based_err_report == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_root_control_root_capabilities_reg_addr_byte2 == 24'd8388750
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_sel_deemphasis == PF0_MINUS_6DB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_slot_capabilities_reg_addr_byte0 == 24'd132
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_slot_capabilities_reg_addr_byte1 == 24'd133
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_slot_capabilities_reg_addr_byte2 == 24'd134
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_slot_capabilities_reg_addr_byte3 == 24'd135
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_slot_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_slot_power_limit_scale == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_slot_power_limit_value == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_surprise_down_err_rep_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_target_link_speed == PF0_TRGT_GEN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_cap_tx_margin == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_int_msg_num == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pcie_slot_imp == PF0_NOT_IMPLEMENTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pipe_loopback == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pipe_loopback_control_off_rsvdp_27 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pl16g_cap_pl16g_cap_off_20h_reg_addr_byte0 == 24'd452
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pl16g_cap_pl16g_cap_off_20h_reg_addr_byte1 == 24'd453
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pl16g_cap_pl16g_cap_off_20h_reg_addr_byte2 == 24'd454
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pl16g_cap_pl16g_cap_off_20h_reg_addr_byte3 == 24'd455
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pl16g_cap_pl16g_cap_off_24h_reg_addr_byte0 == 24'd452
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pl16g_cap_pl16g_cap_off_24h_reg_addr_byte1 == 24'd453
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pl16g_cap_pl16g_cap_off_24h_reg_addr_byte2 == 24'd454
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pl16g_cap_pl16g_cap_off_24h_reg_addr_byte3 == 24'd455
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pl16g_cap_pl16g_cap_off_28h_reg_addr_byte0 == 24'd452
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pl16g_cap_pl16g_cap_off_28h_reg_addr_byte1 == 24'd453
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pl16g_cap_pl16g_cap_off_28h_reg_addr_byte2 == 24'd454
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pl16g_cap_pl16g_cap_off_28h_reg_addr_byte3 == 24'd455
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pl16g_cap_pl16g_cap_off_2ch_reg_addr_byte0 == 24'd452
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pl16g_cap_pl16g_cap_off_2ch_reg_addr_byte1 == 24'd453
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pl16g_cap_pl16g_cap_off_2ch_reg_addr_byte2 == 24'd454
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pl16g_cap_pl16g_cap_off_2ch_reg_addr_byte3 == 24'd455
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pl16g_cap_pl16g_ext_cap_hdr_reg_addr_byte2 == 24'd8389030
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pl16g_cap_pl16g_ext_cap_hdr_reg_addr_byte3 == 24'd8389031
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pl16g_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pl16g_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pm_cap_cap_id_nxt_ptr_reg_addr_byte1 == 24'd8388673
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pm_cap_cap_id_nxt_ptr_reg_addr_byte2 == 24'd8388674
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pm_cap_cap_id_nxt_ptr_reg_addr_byte3 == 24'd8388675
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pm_cap_con_status_reg_addr_byte0 == 24'd8388676
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pm_next_pointer == 8'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pm_spec_ver == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pme_clk == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pme_support == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_link_ctrl_off_rsvdp_4 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_ack_f_aspm_ctrl_off_addr_byte1 == 24'd8390413
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_ack_f_aspm_ctrl_off_addr_byte2 == 24'd1806
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_aux_clk_freq_off_addr_byte0 == 24'd8391488
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_aux_clk_freq_off_addr_byte1 == 24'd8391489
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_filter_mask_2_off_addr_byte0 == 24'd8390432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_filter_mask_2_off_addr_byte1 == 24'd8390433
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_filter_mask_2_off_addr_byte2 == 24'd8390434
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_filter_mask_2_off_addr_byte3 == 24'd8390435
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_gen2_ctrl_off_addr_byte0 == 24'd8390668
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_gen2_ctrl_off_addr_byte1 == 24'd8390669
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_gen2_ctrl_off_addr_byte2 == 24'd12584974
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_gen3_eq_control_off_addr_byte0 == 24'd8390824
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_gen3_eq_control_off_addr_byte1 == 24'd8390825
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_gen3_eq_control_off_addr_byte2 == 24'd8390826
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_gen3_eq_control_off_addr_byte3 == 24'd8390827
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_gen3_eq_control_off_atg4_addr_byte0 == 24'd8390824
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_gen3_eq_control_off_atg4_addr_byte1 == 24'd8390825
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_gen3_eq_control_off_atg4_addr_byte2 == 24'd8390826
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_gen3_eq_control_off_atg4_addr_byte3 == 24'd8390827
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_gen3_eq_local_fs_lf_off_addr_byte1 == 24'd8390825
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_gen3_related_off_addr_byte0 == 24'd8390800
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_gen3_related_off_addr_byte1 == 24'd8390801
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_gen3_related_off_addr_byte2 == 24'd8390802
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_gen3_related_off_addr_byte3 == 24'd8390803
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_gen3_related_off_atg4_addr_byte0 == 24'd8390800
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_gen3_related_off_atg4_addr_byte1 == 24'd8390801
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_gen3_related_off_atg4_addr_byte2 == 24'd8390802
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_gen3_related_off_atg4_addr_byte3 == 24'd8390803
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_misc_control_1_off_addr_byte0 == 24'd2236
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_misc_control_1_off_addr_byte1 == 24'd2237
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_misc_control_1_off_addr_byte2 == 24'd2238
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_pipe_loopback_control_off_addr_byte3 == 24'd8390843
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_port_force_off_addr_byte0 == 24'd8390408
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_port_link_ctrl_off_addr_byte0 == 24'd8390416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_port_link_ctrl_off_addr_byte2 == 24'd8390418
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_queue_status_off_addr_byte2 == 24'd8390462
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_queue_status_off_addr_byte3 == 24'd8390463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_symbol_timer_filter_1_off_addr_byte0 == 24'd8390428
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_symbol_timer_filter_1_off_addr_byte1 == 24'd8390429
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_symbol_timer_filter_1_off_addr_byte2 == 24'd8390430
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_symbol_timer_filter_1_off_addr_byte3 == 24'd8390431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_timer_ctrl_max_func_num_off_addr_byte0 == 24'd8390424
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_vc0_cpl_rx_q_ctrl_off_addr_byte0 == 24'd8390480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_vc0_cpl_rx_q_ctrl_off_addr_byte1 == 24'd8390481
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_vc0_cpl_rx_q_ctrl_off_addr_byte2 == 24'd8390482
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_vc0_cpl_rx_q_ctrl_off_addr_byte3 == 24'd8390483
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_vc0_np_rx_q_ctrl_off_addr_byte0 == 24'd8390476
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_vc0_np_rx_q_ctrl_off_addr_byte1 == 24'd8390477
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_vc0_np_rx_q_ctrl_off_addr_byte2 == 24'd8390478
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_vc0_p_rx_q_ctrl_off_addr_byte0 == 24'd8390472
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_vc0_p_rx_q_ctrl_off_addr_byte1 == 24'd8390473
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_port_logic_vc0_p_rx_q_ctrl_off_addr_byte2 == 24'd8390474
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_power_state == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_pre_det_lane == PF0_DET_ALL_LANES
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_program_interface == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte2 == 24'd8389258
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte3 == 24'd8389259
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_prs_ext_cap_prs_req_capacity_reg_addr_byte0 == 24'd8389264
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_prs_ext_cap_prs_req_capacity_reg_addr_byte1 == 24'd8389265
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_prs_ext_cap_prs_req_capacity_reg_addr_byte2 == 24'd8389266
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_prs_ext_cap_prs_req_capacity_reg_addr_byte3 == 24'd8389267
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_prs_ext_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_prs_ext_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_prs_outstanding_capacity == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_queue_status_off_rsvdp_29 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_ras_des_cap_event_counter_ctrl_reg_addr_byte0 == 24'd688
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_ras_des_cap_event_counter_ctrl_reg_g5_addr_byte3 == 24'd8389299
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_ras_des_cap_event_counter_ctrl_reg_g6_addr_byte3 == 24'd8389299
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_ras_des_cap_event_counter_ctrl_reg_g7_addr_byte3 == 24'd8389299
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_ras_des_cap_force_detect_lane == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_ras_des_cap_force_detect_lane_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_ras_des_cap_ras_des_hdr_reg_addr_byte2 == 24'd8389290
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_ras_des_cap_ras_des_hdr_reg_addr_byte3 == 24'd8389291
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_ras_des_cap_sd_control1_reg_addr_byte0 == 24'd8389448
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_ras_des_cap_sd_control1_reg_addr_byte1 == 24'd8389449
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_ras_des_cap_sd_control1_reg_addr_byte2 == 24'd8389450
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_ras_des_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_ras_des_event_counter_en == 8'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_ras_des_event_counter_event_select_g5 == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_ras_des_event_counter_event_select_g6 == 8'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_ras_des_event_counter_event_select_g7 == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_ras_des_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_rate_shadow_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_rate_shadow_sel_atg4 == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved10 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved250 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved4 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved6 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved8 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved9 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_10_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_11_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_12_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_13_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_14_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_15_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_16_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_17_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_18_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_19_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_20_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_21_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_22_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_23_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_24_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_25_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_26_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_27_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_28_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_29_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_30_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_31_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_32_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_33_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_34_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_35_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_36_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_37_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_38_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_39_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_40_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_41_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_42_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_43_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_44_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_45_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_46_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_47_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_48_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_49_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_50_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_51_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_52_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_53_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_54_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_55_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_56_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_57_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_58_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_59_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_60_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_61_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_62_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_63_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_64_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_65_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_66_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_67_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_68_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_69_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_70_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_71_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_72_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_73_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reserved_9_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_reset_assert == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_revision_id == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_rom_bar_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_rom_bar_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_root_control_root_capabilities_reg_rsvdp_17 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_root_err_status_off_rsvdp_7 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_rp_exp_rom_bar_mask_reg_rp_rom_rsvdp_1 == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_rp_rom_bar_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_rp_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_rxeq_ph01_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_rxeq_ph01_en_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_rxeq_rgrdless_rxts == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_rxeq_rgrdless_rxts_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_rxstatus_value == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_scramble_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sel_deemphasis == PF0_MINUS_6DB_CTL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_shadow_sriov_vf_stride_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_simplified_replay_timer == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_skp_int_val == 11'd640
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sn_cap_ser_num_reg_dw_1_addr_byte0 == 24'd8388968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sn_cap_ser_num_reg_dw_1_addr_byte1 == 24'd8388969
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sn_cap_ser_num_reg_dw_1_addr_byte2 == 24'd8388970
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sn_cap_ser_num_reg_dw_1_addr_byte3 == 24'd8388971
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sn_cap_ser_num_reg_dw_2_addr_byte0 == 24'd8388972
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sn_cap_ser_num_reg_dw_2_addr_byte1 == 24'd8388973
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sn_cap_ser_num_reg_dw_2_addr_byte2 == 24'd8388974
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sn_cap_ser_num_reg_dw_2_addr_byte3 == 24'd8388975
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sn_cap_sn_base_addr_byte2 == 24'd8388966
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sn_cap_sn_base_addr_byte3 == 24'd8388967
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sn_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sn_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sn_ser_num_reg_1_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sn_ser_num_reg_2_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_spcie_cap_lane_equalization_control01_reg_addr_byte0 == 24'd400
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_spcie_cap_lane_equalization_control01_reg_addr_byte1 == 24'd8389009
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_spcie_cap_lane_equalization_control01_reg_addr_byte2 == 24'd402
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_spcie_cap_lane_equalization_control01_reg_addr_byte3 == 24'd8389011
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_spcie_cap_lane_equalization_control1011_reg_addr_byte0 == 24'd404
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_spcie_cap_lane_equalization_control1011_reg_addr_byte1 == 24'd8389013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_spcie_cap_lane_equalization_control1011_reg_addr_byte2 == 24'd406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_spcie_cap_lane_equalization_control1011_reg_addr_byte3 == 24'd8389015
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_spcie_cap_lane_equalization_control1213_reg_addr_byte0 == 24'd404
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_spcie_cap_lane_equalization_control1213_reg_addr_byte1 == 24'd8389013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_spcie_cap_lane_equalization_control1213_reg_addr_byte2 == 24'd406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_spcie_cap_lane_equalization_control1213_reg_addr_byte3 == 24'd8389015
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_spcie_cap_lane_equalization_control1415_reg_addr_byte0 == 24'd404
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_spcie_cap_lane_equalization_control1415_reg_addr_byte1 == 24'd8389013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_spcie_cap_lane_equalization_control1415_reg_addr_byte2 == 24'd406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_spcie_cap_lane_equalization_control1415_reg_addr_byte3 == 24'd8389015
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_spcie_cap_lane_equalization_control23_reg_addr_byte0 == 24'd404
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_spcie_cap_lane_equalization_control23_reg_addr_byte1 == 24'd8389013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_spcie_cap_lane_equalization_control23_reg_addr_byte2 == 24'd406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_spcie_cap_lane_equalization_control23_reg_addr_byte3 == 24'd8389015
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_spcie_cap_lane_equalization_control45_reg_addr_byte0 == 24'd404
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_spcie_cap_lane_equalization_control45_reg_addr_byte1 == 24'd8389013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_spcie_cap_lane_equalization_control45_reg_addr_byte2 == 24'd406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_spcie_cap_lane_equalization_control45_reg_addr_byte3 == 24'd8389015
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_spcie_cap_lane_equalization_control67_reg_addr_byte0 == 24'd404
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_spcie_cap_lane_equalization_control67_reg_addr_byte1 == 24'd8389013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_spcie_cap_lane_equalization_control67_reg_addr_byte2 == 24'd406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_spcie_cap_lane_equalization_control67_reg_addr_byte3 == 24'd8389015
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_spcie_cap_lane_equalization_control89_reg_addr_byte0 == 24'd404
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_spcie_cap_lane_equalization_control89_reg_addr_byte1 == 24'd8389013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_spcie_cap_lane_equalization_control89_reg_addr_byte2 == 24'd406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_spcie_cap_lane_equalization_control89_reg_addr_byte3 == 24'd8389015
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_spcie_cap_spcie_cap_header_reg_addr_byte2 == 24'd8388998
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_spcie_cap_spcie_cap_header_reg_addr_byte3 == 24'd8388999
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_spcie_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_spcie_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_shadow_sriov_initial_vfs_addr_byte0 == 24'd10486328
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_shadow_sriov_initial_vfs_addr_byte1 == 24'd10486329
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_shadow_sriov_vf_offset_position_addr_byte0 == 24'd10486336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_shadow_sriov_vf_offset_position_addr_byte1 == 24'd10486337
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_shadow_sriov_vf_offset_position_addr_byte2 == 24'd10486338
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_shadow_sriov_vf_offset_position_addr_byte3 == 24'd10486339
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_shadow_vf_bar0_reg_addr_byte0 == 24'd2097744
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_shadow_vf_bar0_reg_addr_byte1 == 24'd2097745
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_shadow_vf_bar0_reg_addr_byte2 == 24'd2097746
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_shadow_vf_bar0_reg_addr_byte3 == 24'd2097747
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_shadow_vf_bar1_reg_addr_byte0 == 24'd2097748
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_shadow_vf_bar1_reg_addr_byte1 == 24'd2097749
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_shadow_vf_bar1_reg_addr_byte2 == 24'd2097750
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_shadow_vf_bar1_reg_addr_byte3 == 24'd2097751
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_shadow_vf_bar2_reg_addr_byte0 == 24'd2097752
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_shadow_vf_bar2_reg_addr_byte1 == 24'd2097753
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_shadow_vf_bar2_reg_addr_byte2 == 24'd2097754
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_shadow_vf_bar2_reg_addr_byte3 == 24'd2097755
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_shadow_vf_bar3_reg_addr_byte0 == 24'd2097756
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_shadow_vf_bar3_reg_addr_byte1 == 24'd2097757
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_shadow_vf_bar3_reg_addr_byte2 == 24'd2097758
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_shadow_vf_bar3_reg_addr_byte3 == 24'd2097759
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_shadow_vf_bar4_reg_addr_byte0 == 24'd2097760
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_shadow_vf_bar4_reg_addr_byte1 == 24'd2097761
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_shadow_vf_bar4_reg_addr_byte2 == 24'd2097762
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_shadow_vf_bar4_reg_addr_byte3 == 24'd2097763
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_shadow_vf_bar5_reg_addr_byte0 == 24'd2097764
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_shadow_vf_bar5_reg_addr_byte1 == 24'd2097765
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_shadow_vf_bar5_reg_addr_byte2 == 24'd2097766
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_shadow_vf_bar5_reg_addr_byte3 == 24'd2097767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_sriov_bar1_enable_reg_addr_byte0 == 24'd2097748
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_sriov_bar3_enable_reg_addr_byte0 == 24'd2097756
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_sriov_bar5_enable_reg_addr_byte0 == 24'd2097764
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_sriov_base_reg_addr_byte2 == 24'd558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_sriov_base_reg_addr_byte3 == 24'd559
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_sriov_initial_vfs_addr_byte0 == 24'd8389176
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_sriov_initial_vfs_addr_byte1 == 24'd8389177
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_sriov_vf_offset_position_addr_byte0 == 24'd8389184
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_sriov_vf_offset_position_addr_byte1 == 24'd8389185
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_sriov_vf_offset_position_addr_byte2 == 24'd8389186
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_sriov_vf_offset_position_addr_byte3 == 24'd8389187
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_sup_page_sizes_reg_addr_byte0 == 24'd8389192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_sup_page_sizes_reg_addr_byte1 == 24'd8389193
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_sup_page_sizes_reg_addr_byte2 == 24'd8389194
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_sup_page_sizes_reg_addr_byte3 == 24'd8389195
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_vf_bar0_reg_addr_byte0 == 24'd592
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_vf_bar1_reg_addr_byte0 == 24'd596
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_vf_bar2_reg_addr_byte0 == 24'd600
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_vf_bar3_reg_addr_byte0 == 24'd604
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_vf_bar4_reg_addr_byte0 == 24'd608
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_vf_bar5_reg_addr_byte0 == 24'd612
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_vf_device_id_reg_addr_byte2 == 24'd8389190
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_cap_vf_device_id_reg_addr_byte3 == 24'd8389191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_initial_vfs_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_initial_vfs_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_sup_page_size == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_vf_bar0_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_vf_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_vf_bar0_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_vf_bar0_type == PF0_SRIOV_VF_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_vf_bar1_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_vf_bar1_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_vf_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_vf_bar1_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_vf_bar1_type == PF0_SRIOV_VF_BAR1_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_vf_bar2_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_vf_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_vf_bar2_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_vf_bar2_type == PF0_SRIOV_VF_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_vf_bar3_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_vf_bar3_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_vf_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_vf_bar3_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_vf_bar3_type == PF0_SRIOV_VF_BAR3_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_vf_bar4_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_vf_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_vf_bar4_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_vf_bar4_type == PF0_SRIOV_VF_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_vf_bar5_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_vf_bar5_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_vf_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_vf_bar5_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_vf_bar5_type == PF0_SRIOV_VF_BAR5_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_vf_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_vf_offset_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_vf_offset_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_sriov_vf_stride_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_subclass_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_subsys_dev_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_subsys_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_target_above_config_limit == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_timer_mod_flow_control == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_timer_mod_flow_control_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_tlp_bypass_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_tph_cap_tph_ext_cap_hdr_reg_addr_byte2 == 24'd8389090
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_tph_cap_tph_ext_cap_hdr_reg_addr_byte3 == 24'd8389091
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_tph_cap_tph_req_cap_reg_addr_byte0 == 24'd8389092
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_tph_cap_tph_req_cap_reg_addr_byte1 == 24'd8389093
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_tph_cap_tph_req_cap_reg_addr_byte2 == 24'd8389094
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_tph_cap_tph_req_cap_reg_addr_byte3 == 24'd8389095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte0 == 24'd10486244
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte1 == 24'd10486245
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte2 == 24'd10486246
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte3 == 24'd10486247
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_tph_req_cap_int_vec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_tph_req_cap_int_vec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_tph_req_cap_reg_rsvdp_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_tph_req_cap_reg_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_tph_req_cap_reg_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_tph_req_cap_reg_vfcomm_cs2_rsvdp_11_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_tph_req_cap_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_tph_req_cap_reg_vfcomm_cs2_rsvdp_3_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_tph_req_cap_st_table_loc_0 == PF0_NOT_IN_TPH_STRUCT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_tph_req_cap_st_table_loc_0_vfcomm_cs2 == PF0_NOT_IN_TPH_STRUCT_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_tph_req_cap_st_table_loc_1 == PF0_NOT_IN_MSIX_TABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_tph_req_cap_st_table_loc_1_vfcomm_cs2 == PF0_NOT_IN_MSIX_TABLE_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_tph_req_cap_st_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_tph_req_cap_st_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_tph_req_cap_ver == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_tph_req_device_spec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_tph_req_device_spec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_tph_req_extended_tph == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_tph_req_extended_tph_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_tph_req_next_ptr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_tph_req_no_st_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_tph_req_no_st_mode_vfcomm_cs2 == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_bar0_mask_reg_addr_byte0 == 24'd2097168
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_bar0_mask_reg_addr_byte1 == 24'd2097169
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_bar0_mask_reg_addr_byte2 == 24'd2097170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_bar0_mask_reg_addr_byte3 == 24'd2097171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_bar0_reg_addr_byte0 == 24'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_bar1_enable_reg_addr_byte0 == 24'd2097172
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_bar1_mask_reg_addr_byte0 == 24'd2097172
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_bar1_mask_reg_addr_byte1 == 24'd2097173
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_bar1_mask_reg_addr_byte2 == 24'd2097174
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_bar1_mask_reg_addr_byte3 == 24'd2097175
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_bar1_reg_addr_byte0 == 24'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_bar2_mask_reg_addr_byte0 == 24'd2097176
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_bar2_mask_reg_addr_byte1 == 24'd2097177
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_bar2_mask_reg_addr_byte2 == 24'd2097178
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_bar2_mask_reg_addr_byte3 == 24'd2097179
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_bar2_reg_addr_byte0 == 24'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_bar3_enable_reg_addr_byte0 == 24'd2097180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_bar3_mask_reg_addr_byte0 == 24'd2097180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_bar3_mask_reg_addr_byte1 == 24'd2097181
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_bar3_mask_reg_addr_byte2 == 24'd2097182
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_bar3_mask_reg_addr_byte3 == 24'd2097183
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_bar3_reg_addr_byte0 == 24'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_bar4_mask_reg_addr_byte0 == 24'd2097184
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_bar4_mask_reg_addr_byte1 == 24'd2097185
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_bar4_mask_reg_addr_byte2 == 24'd2097186
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_bar4_mask_reg_addr_byte3 == 24'd2097187
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_bar4_reg_addr_byte0 == 24'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_bar5_enable_reg_addr_byte0 == 24'd2097188
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_bar5_mask_reg_addr_byte0 == 24'd2097188
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_bar5_mask_reg_addr_byte1 == 24'd2097189
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_bar5_mask_reg_addr_byte2 == 24'd2097190
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_bar5_mask_reg_addr_byte3 == 24'd2097191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_bar5_reg_addr_byte0 == 24'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_bist_header_type_latency_cache_line_size_reg_addr_byte2 == 24'd8388622
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_cardbus_cis_ptr_reg_addr_byte0 == 24'd8388648
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_cardbus_cis_ptr_reg_addr_byte1 == 24'd8388649
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_cardbus_cis_ptr_reg_addr_byte2 == 24'd8388650
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_cardbus_cis_ptr_reg_addr_byte3 == 24'd8388651
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_class_code_revision_id_addr_byte0 == 24'd8388616
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_class_code_revision_id_addr_byte1 == 24'd8388617
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_class_code_revision_id_addr_byte2 == 24'd8388618
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_class_code_revision_id_addr_byte3 == 24'd8388619
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_device_id_vendor_id_reg_addr_byte0 == 24'd8388608
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_device_id_vendor_id_reg_addr_byte1 == 24'd8388609
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_device_id_vendor_id_reg_addr_byte2 == 24'd8388610
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_device_id_vendor_id_reg_addr_byte3 == 24'd8388611
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_exp_rom_bar_mask_reg_addr_byte0 == 24'd2097200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_exp_rom_bar_mask_reg_addr_byte1 == 24'd2097201
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_exp_rom_bar_mask_reg_addr_byte2 == 24'd2097202
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_exp_rom_bar_mask_reg_addr_byte3 == 24'd2097203
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_exp_rom_base_addr_reg_addr_byte0 == 24'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_max_latency_min_grant_interrupt_pin_interrupt_line_reg_addr_byte1 == 24'd8388669
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_pci_cap_ptr_reg_addr_byte0 == 24'd8388660
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_rp_exp_rom_bar_mask_reg_addr_byte0 == 24'd2097208
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_rp_exp_rom_bar_mask_reg_addr_byte1 == 24'd2097209
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_rp_exp_rom_bar_mask_reg_addr_byte2 == 24'd2097210
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_rp_exp_rom_bar_mask_reg_addr_byte3 == 24'd2097211
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte0 == 24'd8388652
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte1 == 24'd8388653
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte2 == 24'd8388654
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte3 == 24'd8388655
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_16g_tx_preset0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_16g_tx_preset1 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_16g_tx_preset10 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_16g_tx_preset11 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_16g_tx_preset12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_16g_tx_preset13 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_16g_tx_preset14 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_16g_tx_preset15 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_16g_tx_preset2 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_16g_tx_preset3 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_16g_tx_preset4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_16g_tx_preset5 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_16g_tx_preset6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_16g_tx_preset7 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_16g_tx_preset8 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_16g_tx_preset9 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_rx_preset_hint0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_rx_preset_hint1 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_rx_preset_hint10 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_rx_preset_hint11 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_rx_preset_hint12 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_rx_preset_hint13 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_rx_preset_hint14 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_rx_preset_hint15 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_rx_preset_hint2 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_rx_preset_hint3 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_rx_preset_hint4 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_rx_preset_hint5 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_rx_preset_hint6 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_rx_preset_hint7 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_rx_preset_hint8 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_rx_preset_hint9 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_send_8gt_eq_ts2_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_send_8gt_eq_ts2_disable_atg4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_tx_preset0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_tx_preset1 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_tx_preset10 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_tx_preset11 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_tx_preset12 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_tx_preset13 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_tx_preset14 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_tx_preset15 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_tx_preset2 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_tx_preset3 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_tx_preset4 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_tx_preset5 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_tx_preset6 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_tx_preset7 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_tx_preset8 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_usp_tx_preset9 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_vc0_cpl_data_credit == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_vc0_cpl_data_scale == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_vc0_cpl_hdr_scale == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_vc0_cpl_header_credit == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_vc0_cpl_tlp_q_mode == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_vc0_np_data_credit == 12'd112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_vc0_np_header_credit == 8'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_vc0_np_tlp_q_mode == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_vc0_p_data_credit == 12'd444
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_vc0_p_header_credit == 8'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_vc0_p_tlp_q_mode == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_vc_cap_vc_base_addr_byte2 == 24'd8388938
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_vc_cap_vc_base_addr_byte3 == 24'd8388939
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_vc_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_vc_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_vendor_specific_dllp_req == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_vf_bar0_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_vf_bar1_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_vf_bar2_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_vf_bar3_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_vf_bar4_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_vf_bar5_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_vsecras_cap_rasdp_ext_hdr_off_addr_byte2 == 24'd8389546
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_vsecras_cap_rasdp_ext_hdr_off_addr_byte3 == 24'd8389547
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_vsecras_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_vsecras_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pld_aib_loopback_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pld_clk_dis == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pld_crs_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pld_tx_fifo_dyn_empty_dis == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pldif_fifo_clk_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.rstctl_timer_a == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.rstctl_timer_b == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.rx_lane_flip_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.rxbuf_limit_bypass == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.rxbuf_limit_init == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.rxbuf_pfull_th == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.shadow_select == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.sriov_clk_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.sris_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.test_in_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.tx_cdts_rst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.tx_fifo_empty_threshold_1 == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.tx_fifo_empty_threshold_2 == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.tx_fifo_empty_threshold_3 == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.tx_fifo_empty_threshold_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.tx_fifo_full_threshold == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.tx_lane_flip_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.user_mode_del_count == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.vf == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.vf_select == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_drop_vendor0_msg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_drop_vendor1_msg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_ep_native == NATIVE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_ip_port_num == PCIE_PORT3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_link_rate == GEN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_link_width == X1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_maxpayload_size == MAX_PAYLOAD_128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_num_of_lanes == NUM_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf0_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf0_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf0_bar1_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf0_bar3_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf0_bar5_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf0_dlink_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf0_io_decode == IO32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf0_ltr_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf0_margin_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf0_msi_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf0_msix_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf0_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf0_pb_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf0_pl16g_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf0_prefetch_decode == PREF64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf0_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf0_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf0_sn_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf0_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf0_sriov_num_vf_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf0_sriov_num_vf_non_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf0_sriov_vf_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf0_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf0_sriov_vf_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf0_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf0_sriov_vf_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf0_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf0_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf0_user_vsec_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf0_vsecras_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf1_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf1_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf1_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf1_pb_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf1_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf1_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf1_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf2_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf2_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf2_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf2_pb_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf2_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf2_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf2_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf3_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf3_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf3_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf3_pb_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf3_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf3_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf3_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf4_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf4_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf4_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf4_pb_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf4_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf4_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf4_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf5_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf5_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf5_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf5_pb_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf5_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf5_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf5_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf6_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf6_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf6_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf6_pb_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf6_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf6_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf6_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf7_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf7_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf7_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf7_pb_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf7_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf7_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pf7_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_phase23_txpreset == PRESET0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_phase23_txpreset_atg4 == GEN4_PRESET0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_pldclk_rate == SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_rp_ep_mode == EP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_tlp_bypass_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.virtual_txeq_mode == EQ_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.vsec_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.vsec_select == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.wait_pld_warm_rst_rdy == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cfg_bad_dllp_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cfg_bad_tlp_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cfg_blk_crs_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cfg_corrected_internal_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cfg_dbi_pf0_table_size == 12'd347
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cfg_dbi_pf1_start_addr == 12'd384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cfg_dbi_pf1_table_size == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cfg_dbi_pf2_start_addr == 12'd640
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cfg_dbi_pf2_table_size == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cfg_dbi_pf3_start_addr == 12'd896
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cfg_dbi_pf3_table_size == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cfg_dbi_pf4_start_addr == 12'd1152
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cfg_dbi_pf4_table_size == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cfg_dbi_pf5_start_addr == 12'd1408
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cfg_dbi_pf5_table_size == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cfg_dbi_pf6_start_addr == 12'd1664
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cfg_dbi_pf6_table_size == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cfg_dbi_pf7_start_addr == 12'd1920
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cfg_dbi_pf7_table_size == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cfg_dl_protocol_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cfg_ecrc_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cfg_fc_protocol_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cfg_mlf_tlp_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cfg_ptm_auto_update_signal == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cfg_ptm_local_clock_adj_lsb == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cfg_ptm_local_clock_adj_msb == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cfg_ram_ecc_chk_val == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cfg_ram_ecc_gen_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cfg_rcvr_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cfg_rcvr_overflow_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cfg_replay_number_rollover_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cfg_replay_timer_timeout_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cfg_surprise_down_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cfg_uncor_internal_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.clrhip_not_rst_sticky == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.crs_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.crs_override_value == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cvp_blocking_dis == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cvp_data_compressed == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cvp_data_encrypted == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cvp_hard_reset_bypass == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cvp_hip_clk_sel_default == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cvp_irq_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cvp_jtag0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cvp_jtag1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cvp_jtag2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cvp_jtag3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cvp_mode_default == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cvp_mode_gating_dis == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cvp_update_no_reset == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cvp_user_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cvp_vsec_id == 16'd4466
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cvp_vsec_rev == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cvp_warm_rst_ready_force_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cvp_warm_rst_ready_force_bit1 == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cvp_warm_rst_req_ena == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.cvp_write_mask_ctl == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.dbg_clk_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.dbi_ro_wr_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.device_type == DEV_NEP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.device_width == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.disable_ct_ur == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.disable_msg_ur == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.disable_ur_nf == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.dyngate_sriov_clk_dis == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.dyngate_vfspfnum_core_clk_dis == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.ecrc_strip == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.enable_poison_nf == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.ep_signal_mask == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.err_tlp_bypass == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_acs_nxtptr_pf0 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_acs_nxtptr_pf1 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_acs_nxtptr_pf2 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_acs_nxtptr_pf3 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_acs_nxtptr_pf4 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_acs_nxtptr_pf5 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_acs_nxtptr_pf6 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_acs_nxtptr_pf7 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_acscap_enable_pf0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_acscap_enable_pf1 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_acscap_enable_pf2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_acscap_enable_pf3 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_acscap_enable_pf4 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_acscap_enable_pf5 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_acscap_enable_pf6 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_acscap_enable_pf7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_aricap_enable == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_aricap_nxtptr_pf0 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_aricap_nxtptr_pf1 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_aricap_nxtptr_pf2 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_aricap_nxtptr_pf3 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_aricap_nxtptr_pf4 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_aricap_nxtptr_pf5 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_aricap_nxtptr_pf6 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_aricap_nxtptr_pf7 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_ats_globalinvalidate_pf0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_ats_globalinvalidate_pf1 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_ats_globalinvalidate_pf2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_ats_globalinvalidate_pf3 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_ats_globalinvalidate_pf4 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_ats_globalinvalidate_pf5 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_ats_globalinvalidate_pf6 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_ats_globalinvalidate_pf7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_ats_invalidateqdepth_pf0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_ats_invalidateqdepth_pf1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_ats_invalidateqdepth_pf2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_ats_invalidateqdepth_pf3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_ats_invalidateqdepth_pf4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_ats_invalidateqdepth_pf5 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_ats_invalidateqdepth_pf6 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_ats_invalidateqdepth_pf7 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_ats_nxtptr_pf0 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_ats_nxtptr_pf1 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_ats_nxtptr_pf2 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_ats_nxtptr_pf3 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_ats_nxtptr_pf4 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_ats_nxtptr_pf5 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_ats_nxtptr_pf6 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_ats_nxtptr_pf7 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_ats_pagealignreq_pf0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_ats_pagealignreq_pf1 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_ats_pagealignreq_pf2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_ats_pagealignreq_pf3 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_ats_pagealignreq_pf4 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_ats_pagealignreq_pf5 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_ats_pagealignreq_pf6 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_ats_pagealignreq_pf7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_atscap_enable == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msix_nxtptr_pf0 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msix_nxtptr_pf1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msix_nxtptr_pf2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msix_nxtptr_pf3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msix_nxtptr_pf4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msix_nxtptr_pf5 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msix_nxtptr_pf6 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msix_nxtptr_pf7 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msix_tablesize_pf0 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msix_tablesize_pf1 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msix_tablesize_pf2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msix_tablesize_pf3 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msix_tablesize_pf4 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msix_tablesize_pf5 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msix_tablesize_pf6 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msix_tablesize_pf7 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msixcap_enable == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msixpba_bir_pf0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msixpba_bir_pf1 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msixpba_bir_pf2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msixpba_bir_pf3 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msixpba_bir_pf4 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msixpba_bir_pf5 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msixpba_bir_pf6 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msixpba_bir_pf7 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msixpba_offset_pf0 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msixpba_offset_pf1 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msixpba_offset_pf2 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msixpba_offset_pf3 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msixpba_offset_pf4 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msixpba_offset_pf5 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msixpba_offset_pf6 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msixpba_offset_pf7 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msixtable_bir_pf0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msixtable_bir_pf1 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msixtable_bir_pf2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msixtable_bir_pf3 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msixtable_bir_pf4 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msixtable_bir_pf5 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msixtable_bir_pf6 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msixtable_bir_pf7 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msixtable_offset_pf0 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msixtable_offset_pf1 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msixtable_offset_pf2 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msixtable_offset_pf3 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msixtable_offset_pf4 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msixtable_offset_pf5 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msixtable_offset_pf6 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_msixtable_offset_pf7 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_pciecap_nxtptr_pf0 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_pciecap_nxtptr_pf1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_pciecap_nxtptr_pf2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_pciecap_nxtptr_pf3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_pciecap_nxtptr_pf4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_pciecap_nxtptr_pf5 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_pciecap_nxtptr_pf6 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_pciecap_nxtptr_pf7 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_revisionid_pf0 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_revisionid_pf1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_revisionid_pf2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_revisionid_pf3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_revisionid_pf4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_revisionid_pf5 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_revisionid_pf6 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_revisionid_pf7 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_subsysid_pf0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_subsysid_pf1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_subsysid_pf2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_subsysid_pf3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_subsysid_pf4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_subsysid_pf5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_subsysid_pf6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_subsysid_pf7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_devspecificmode_pf0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_devspecificmode_pf1 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_devspecificmode_pf2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_devspecificmode_pf3 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_devspecificmode_pf4 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_devspecificmode_pf5 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_devspecificmode_pf6 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_devspecificmode_pf7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_exttphrequester_pf0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_exttphrequester_pf1 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_exttphrequester_pf2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_exttphrequester_pf3 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_exttphrequester_pf4 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_exttphrequester_pf5 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_exttphrequester_pf6 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_exttphrequester_pf7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_intvecmode_pf0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_intvecmode_pf1 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_intvecmode_pf2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_intvecmode_pf3 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_intvecmode_pf4 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_intvecmode_pf5 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_intvecmode_pf6 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_intvecmode_pf7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_nxtptr_pf0 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_nxtptr_pf1 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_nxtptr_pf2 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_nxtptr_pf3 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_nxtptr_pf4 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_nxtptr_pf5 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_nxtptr_pf6 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_nxtptr_pf7 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_sttablelocation_pf0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_sttablelocation_pf1 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_sttablelocation_pf2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_sttablelocation_pf3 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_sttablelocation_pf4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_sttablelocation_pf5 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_sttablelocation_pf6 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_sttablelocation_pf7 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_sttablesize_pf0 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_sttablesize_pf1 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_sttablesize_pf2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_sttablesize_pf3 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_sttablesize_pf4 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_sttablesize_pf5 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_sttablesize_pf6 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tph_sttablesize_pf7 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_tphcap_enable == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_type0cap_nxtptr_pf0 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_type0cap_nxtptr_pf1 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_type0cap_nxtptr_pf2 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_type0cap_nxtptr_pf3 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_type0cap_nxtptr_pf4 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_type0cap_nxtptr_pf5 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_type0cap_nxtptr_pf6 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.exvf_type0cap_nxtptr_pf7 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.func_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.gate_clk_in_reset_dis == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.gate_radm_clk_dis == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.gpio_irq == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.intel_marker == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.irq_misc_ctrl == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.margining_ready == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.margining_software_ready == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.nonsriov_mode == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pcie_parity_bypass == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ack_n_fts == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_acs_cap_acs_at_block == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_acs_cap_acs_cap_hdr_reg_addr_byte2 == 24'd8389330
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_acs_cap_acs_cap_hdr_reg_addr_byte3 == 24'd8389331
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_acs_cap_acs_capalities_ctrl_reg_addr_byte0 == 24'd8389332
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_acs_cap_acs_capalities_ctrl_reg_addr_byte1 == 24'd725
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_acs_cap_acs_direct_translated_p2p == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_acs_cap_acs_egress_ctrl_size == 8'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_acs_cap_acs_p2p_cpl_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_acs_cap_acs_p2p_egress_control == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_acs_cap_acs_p2p_req_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_acs_cap_acs_src_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_acs_cap_acs_usp_forwarding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_acs_cap_rsvdp_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_acs_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_acs_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_adv_err_int_msg_num == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_aer_cap_aer_ext_cap_hdr_off_addr_byte2 == 24'd8388866
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_aer_cap_aer_ext_cap_hdr_off_addr_byte3 == 24'd8388867
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_aer_cap_root_err_status_off_addr_byte0 == 24'd304
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_aer_cap_version == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_aer_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ari_acs_fun_grp_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ari_cap_ari_base_addr_byte2 == 24'd8388982
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ari_cap_ari_base_addr_byte3 == 24'd8388983
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ari_cap_cap_reg_addr_byte0 == 24'd8388984
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ari_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ari_device_number == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ari_mfvc_fun_grp_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ari_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ats_cap_ats_cap_hdr_reg_addr_byte2 == 24'd8389314
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ats_cap_ats_cap_hdr_reg_addr_byte3 == 24'd8389315
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ats_cap_ats_capabilities_ctrl_reg_addr_byte0 == 24'd8389316
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ats_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ats_capabilities_ctrl_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ats_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_auto_eq_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_auto_eq_disable_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_auto_lane_flip_ctrl_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_aux_clk_freq == 10'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_aux_clk_freq_off_rsvdp_10 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_aux_curr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_bar0_mem_io == PF0_BAR0_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_bar0_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_bar0_type == PF0_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_bar1_mem_io == PF0_BAR1_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_bar1_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_bar1_type == PF0_BAR1_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_bar2_mem_io == PF0_BAR2_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_bar2_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_bar2_type == PF0_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_bar3_mem_io == PF0_BAR3_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_bar3_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_bar3_type == PF0_BAR3_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_bar4_mem_io == PF0_BAR4_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_bar4_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_bar4_type == PF0_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_bar5_mem_io == PF0_BAR5_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_bar5_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_bar5_type == PF0_BAR5_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_base_class_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_cap_id_nxt_ptr_reg_rsvdp_20 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_cap_pointer == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_cardbus_cis_pointer == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_common_clk_n_fts == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_con_status_reg_rsvdp_2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_con_status_reg_rsvdp_4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_config_limit == 10'd831
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_config_phy_tx_change == PF0_FULL_SWING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_config_tx_comp_rx == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_cross_link_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_cross_link_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_d1_support == PF0_D1_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_d2_support == PF0_D2_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_10 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_11 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_12 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_13 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_14 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_15 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_16 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_17 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_18 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_19 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_20 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_21 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_22 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_23 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_24 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_25 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_26 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_27 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_28 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_29 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_30 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_31 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_32 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_33 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_34 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_35 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_36 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_37 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_38 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_39 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_40 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_41 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_42 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_43 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_44 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_7 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_8 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_reserved_9 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dbi_ro_wr_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_default_target == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_device_capabilities_reg_rsvdp_12 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_device_capabilities_reg_rsvdp_16 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_device_capabilities_reg_rsvdp_29 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_direct_speed_change == PF0_AUTO_SPEED_CHG
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_disable_auto_ltr_clr_msg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_disable_fc_wd_timer == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_disable_scrambler_gen_3 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_disable_scrambler_gen_3_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dlink_cap_dlink_fea_ext_hdr_off_addr_byte2 == 24'd8389686
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dlink_cap_dlink_fea_ext_hdr_off_addr_byte3 == 24'd8389687
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dlink_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dlink_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dll_link_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsi == PF0_NOT_REQUIRED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_16g_tx_preset0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_16g_tx_preset1 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_16g_tx_preset10 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_16g_tx_preset11 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_16g_tx_preset12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_16g_tx_preset13 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_16g_tx_preset14 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_16g_tx_preset15 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_16g_tx_preset2 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_16g_tx_preset3 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_16g_tx_preset4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_16g_tx_preset5 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_16g_tx_preset6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_16g_tx_preset7 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_16g_tx_preset8 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_16g_tx_preset9 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_rx_preset_hint0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_rx_preset_hint1 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_rx_preset_hint10 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_rx_preset_hint11 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_rx_preset_hint12 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_rx_preset_hint13 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_rx_preset_hint14 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_rx_preset_hint15 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_rx_preset_hint2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_rx_preset_hint3 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_rx_preset_hint4 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_rx_preset_hint5 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_rx_preset_hint6 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_rx_preset_hint7 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_rx_preset_hint8 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_rx_preset_hint9 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_tx_preset0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_tx_preset1 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_tx_preset10 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_tx_preset11 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_tx_preset12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_tx_preset13 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_tx_preset14 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_tx_preset15 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_tx_preset2 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_tx_preset3 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_tx_preset4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_tx_preset5 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_tx_preset6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_tx_preset7 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_tx_preset8 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_dsp_tx_preset9 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_eidle_timer == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_eq_eieos_cnt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_eq_eieos_cnt_atg4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_eq_phase_2_3 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_eq_phase_2_3_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_eq_redo == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_eq_redo_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_exp_rom_bar_mask_reg_rsvdp_1 == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_exp_rom_base_addr_reg_rsvdp_1 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_fast_link_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_fast_training_seq == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen1_ei_inference == PF0_USE_RX_EIDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen2_ctrl_off_rsvdp_22 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_dc_balance_disable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_dc_balance_disable_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_dllp_xmt_delay_disable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_dllp_xmt_delay_disable_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_eq_control_off_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_eq_control_off_rsvdp_27_atg4 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_eq_control_off_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_eq_control_off_rsvdp_7_atg4 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_eq_eval_2ms_disable == PF0_CONTINUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_eq_eval_2ms_disable_atg4 == PF0_CONTINUE_ATG4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_eq_fb_mode == PF0_FOM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_eq_fb_mode_atg4 == PF0_FOM_ATG4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_eq_fom_inc_initial_eval == PF0_IGNORE_INIT_FOM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_eq_fom_inc_initial_eval_atg4 == PF0_IGNORE_INIT_FOM_ATG4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_eq_invreq_eva_diff_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_eq_invreq_eva_diff_disable_atg4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_eq_phase23_exit_mode == PF0_NEXT_REC_SPEED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_eq_phase23_exit_mode_atg4 == PF0_NEXT_REC_SPEED_ATG4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_eq_pset_req_as_coef == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_eq_pset_req_as_coef_atg4 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_eq_pset_req_vec == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_eq_pset_req_vec_atg4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_equalization_disable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_equalization_disable_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_lower_rate_eq_redo_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_lower_rate_eq_redo_enable_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_related_off_rsvdp_1 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_related_off_rsvdp_14 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_related_off_rsvdp_14_atg4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_related_off_rsvdp_19 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_related_off_rsvdp_19_atg4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_related_off_rsvdp_1_atg4 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_related_off_rsvdp_26 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_related_off_rsvdp_26_atg4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_req_send_consec_eieos_for_pset_map == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_req_send_consec_eieos_for_pset_map_atg4 == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_zrxdc_noncompl == PF0_COMPLIANT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_gen3_zrxdc_noncompl_atg4 == PF0_COMPLIANT_ATG4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_global_inval_spprtd == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_header_type == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_int_pin == PF0_NO_INT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_invalidate_q_depth == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_lane_equalization_control01_reg_rsvdp_15 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_lane_equalization_control01_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_lane_equalization_control01_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_lane_equalization_control01_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_lane_equalization_control1011_reg_rsvdp_15 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_lane_equalization_control1011_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_lane_equalization_control1011_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_lane_equalization_control1011_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_lane_equalization_control1213_reg_rsvdp_15 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_lane_equalization_control1213_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_lane_equalization_control1213_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_lane_equalization_control1213_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_lane_equalization_control1415_reg_rsvdp_15 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_lane_equalization_control1415_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_lane_equalization_control1415_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_lane_equalization_control1415_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_lane_equalization_control23_reg_rsvdp_15 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_lane_equalization_control23_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_lane_equalization_control23_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_lane_equalization_control23_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_lane_equalization_control45_reg_rsvdp_15 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_lane_equalization_control45_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_lane_equalization_control45_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_lane_equalization_control45_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_lane_equalization_control67_reg_rsvdp_15 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_lane_equalization_control67_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_lane_equalization_control67_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_lane_equalization_control67_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_lane_equalization_control89_reg_rsvdp_15 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_lane_equalization_control89_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_lane_equalization_control89_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_lane_equalization_control89_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_link_capabilities_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_link_capable == PF0_CONN_X1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_link_control_link_status_reg_rsvdp_12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_link_control_link_status_reg_rsvdp_2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_link_control_link_status_reg_rsvdp_26 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_link_control_link_status_reg_rsvdp_9 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_link_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_link_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_loopback_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ltr_cap_ltr_cap_hdr_reg_addr_byte2 == 24'd8389358
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ltr_cap_ltr_cap_hdr_reg_addr_byte3 == 24'd8389359
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ltr_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ltr_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_margin_cap_margin_ext_cap_hdr_reg_addr_byte2 == 24'd8389070
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_margin_cap_margin_ext_cap_hdr_reg_addr_byte3 == 24'd8389071
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_margin_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_margin_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_mask_radm_1 == 16'd8200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_mask_radm_2 == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_mask_ur_ca_4_trgt1 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_max_func_num == PF0_ONE_FUNCTION
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_misc_control_1_off_rsvdp_6 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_misc_control_1_rsvdp_21 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte1 == 24'd8388689
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte2 == 24'd8388690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte3 == 24'd8388691
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_msi_cap_pci_msi_cap_id_next_ctrl_reg_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_msix_cap_msix_pba_offset_reg_addr_byte0 == 24'd8388792
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_msix_cap_msix_pba_offset_reg_addr_byte1 == 24'd8388793
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_msix_cap_msix_pba_offset_reg_addr_byte2 == 24'd8388794
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_msix_cap_msix_pba_offset_reg_addr_byte3 == 24'd8388795
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_msix_cap_msix_table_offset_reg_addr_byte0 == 24'd8388788
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_msix_cap_msix_table_offset_reg_addr_byte1 == 24'd8388789
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_msix_cap_msix_table_offset_reg_addr_byte2 == 24'd8388790
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_msix_cap_msix_table_offset_reg_addr_byte3 == 24'd8388791
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte1 == 24'd8388785
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte2 == 24'd8388786
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte3 == 24'd8388787
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte2 == 24'd10485938
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte3 == 24'd10485939
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_multi_func == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_no_soft_rst == PF0_INTERNALLY_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_num_of_lanes == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_p2p_err_rpt_ctrl == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_p2p_track_cpl_to_reg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_page_aligned_req == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pasid_cap_execute_permission_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pasid_cap_max_pasid_width == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pasid_cap_pasid_cap_cntrl_reg_addr_byte0 == 24'd8389368
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pasid_cap_pasid_cap_cntrl_reg_addr_byte1 == 24'd8389369
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pasid_cap_pasid_ext_hdr_reg_addr_byte2 == 24'd8389366
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pasid_cap_pasid_ext_hdr_reg_addr_byte3 == 24'd8389367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pasid_cap_privileged_mode_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pasid_cap_rsvdp_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pasid_cap_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pasid_cap_rsvpd_13 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pasid_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pasid_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_msi_64_bit_addr_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_msi_cap_next_offset == 8'd112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_msi_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_msi_ext_data_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_msi_ext_data_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_msi_multiple_msg_cap == PF0_MSI_VEC_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_msi_multiple_msg_en == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_msix_bir == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_msix_cap_id_next_ctrl_reg_rsvdp_27 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_msix_cap_next_offset == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_msix_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_msix_enable_vfcomm_cs2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_msix_function_mask == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_msix_function_mask_vfcomm_cs2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_msix_pba == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_msix_pba_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_msix_table_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_msix_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_msix_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_pvm_support == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_type0_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_type0_bar0_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_type0_bar1_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_type0_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_type0_bar1_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_type0_bar1_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_type0_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_type0_bar2_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_type0_bar3_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_type0_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_type0_bar3_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_type0_bar3_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_type0_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_type0_bar4_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_type0_bar5_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_type0_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_type0_bar5_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_type0_bar5_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_type0_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pci_type0_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_active_state_link_pm_control == PF0_ASPM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_active_state_link_pm_support == PF0_NO_ASPM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_aspm_opt_compliance == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_attention_indicator == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_attention_indicator_button == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_aux_power_pm_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_clock_power_man == PF0_REFCLK_REMOVE_NOT_OK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_common_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_crs_sw_visibility == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_device_capabilities_reg_addr_byte0 == 24'd8388724
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_device_capabilities_reg_addr_byte1 == 24'd8388725
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_device_capabilities_reg_addr_byte3 == 24'd8388727
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_device_control_device_status_addr_byte1 == 24'd8388729
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_dll_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_dll_active_rep_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_electromech_interlock == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_en_clk_power_man == PF0_CLKREQ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_en_no_snoop == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_enter_compliance == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_ep_l0s_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_ep_l1_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_ext_tag_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_ext_tag_supp == PF0_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_extended_synch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_flr_cap == PF0_NOT_CAPABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_hot_plug_capable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_hot_plug_surprise == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_hw_auto_speed_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvd == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_initiate_flr == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_l0s_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_l1_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_link_auto_bw_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_link_auto_bw_status == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_link_bw_man_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_link_bw_man_status == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_link_bw_not_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_link_capabilities_reg_addr_byte0 == 24'd8388732
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_link_capabilities_reg_addr_byte1 == 24'd8388733
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_link_capabilities_reg_addr_byte2 == 24'd8388734
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_link_capabilities_reg_addr_byte3 == 24'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_link_control2_link_status2_reg_addr_byte0 == 24'd12583072
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_link_control_link_status_reg_addr_byte0 == 24'd4194432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_link_control_link_status_reg_addr_byte1 == 24'd12583041
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_link_control_link_status_reg_addr_byte3 == 24'd4194435
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_link_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_link_training == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_max_link_speed == PF0_MAX_2P5GTS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_max_link_width == PF0_X1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_max_payload_size == PF0_PAYLOAD_128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_max_read_req_size == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_mrl_sensor == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_nego_link_width == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_next_ptr == 8'd176
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_no_cmd_cpl_support == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte1 == 24'd8388721
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte3 == 24'd8388723
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_phantom_func_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_phantom_func_support == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_phy_slot_num == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_port_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_power_controller == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_power_indicator == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_rcb == PF0_RCB_64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_retrain_link == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_role_based_err_report == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_root_control_root_capabilities_reg_addr_byte2 == 24'd142
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_sel_deemphasis == PF0_MINUS_6DB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_slot_capabilities_reg_addr_byte0 == 24'd132
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_slot_capabilities_reg_addr_byte1 == 24'd133
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_slot_capabilities_reg_addr_byte2 == 24'd134
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_slot_capabilities_reg_addr_byte3 == 24'd135
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_slot_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_slot_power_limit_scale == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_slot_power_limit_value == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_surprise_down_err_rep_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_target_link_speed == PF0_TRGT_GEN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_cap_tx_margin == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_int_msg_num == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pcie_slot_imp == PF0_NOT_IMPLEMENTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pipe_loopback == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pipe_loopback_control_off_rsvdp_27 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pl16g_cap_pl16g_cap_off_20h_reg_addr_byte0 == 24'd452
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pl16g_cap_pl16g_cap_off_20h_reg_addr_byte1 == 24'd453
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pl16g_cap_pl16g_cap_off_20h_reg_addr_byte2 == 24'd454
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pl16g_cap_pl16g_cap_off_20h_reg_addr_byte3 == 24'd455
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pl16g_cap_pl16g_cap_off_24h_reg_addr_byte0 == 24'd456
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pl16g_cap_pl16g_cap_off_24h_reg_addr_byte1 == 24'd457
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pl16g_cap_pl16g_cap_off_24h_reg_addr_byte2 == 24'd458
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pl16g_cap_pl16g_cap_off_24h_reg_addr_byte3 == 24'd459
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pl16g_cap_pl16g_cap_off_28h_reg_addr_byte0 == 24'd456
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pl16g_cap_pl16g_cap_off_28h_reg_addr_byte1 == 24'd457
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pl16g_cap_pl16g_cap_off_28h_reg_addr_byte2 == 24'd458
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pl16g_cap_pl16g_cap_off_28h_reg_addr_byte3 == 24'd459
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pl16g_cap_pl16g_cap_off_2ch_reg_addr_byte0 == 24'd456
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pl16g_cap_pl16g_cap_off_2ch_reg_addr_byte1 == 24'd457
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pl16g_cap_pl16g_cap_off_2ch_reg_addr_byte2 == 24'd458
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pl16g_cap_pl16g_cap_off_2ch_reg_addr_byte3 == 24'd459
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pl16g_cap_pl16g_ext_cap_hdr_reg_addr_byte2 == 24'd8389030
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pl16g_cap_pl16g_ext_cap_hdr_reg_addr_byte3 == 24'd8389031
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pl16g_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pl16g_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pm_cap_cap_id_nxt_ptr_reg_addr_byte1 == 24'd8388673
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pm_cap_cap_id_nxt_ptr_reg_addr_byte2 == 24'd8388674
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pm_cap_cap_id_nxt_ptr_reg_addr_byte3 == 24'd8388675
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pm_cap_con_status_reg_addr_byte0 == 24'd8388676
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pm_next_pointer == 8'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pm_spec_ver == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pme_clk == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pme_support == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_link_ctrl_off_rsvdp_4 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_ack_f_aspm_ctrl_off_addr_byte1 == 24'd8390413
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_ack_f_aspm_ctrl_off_addr_byte2 == 24'd1806
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_aux_clk_freq_off_addr_byte0 == 24'd8391488
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_aux_clk_freq_off_addr_byte1 == 24'd8391489
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_filter_mask_2_off_addr_byte0 == 24'd8390432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_filter_mask_2_off_addr_byte1 == 24'd8390433
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_filter_mask_2_off_addr_byte2 == 24'd8390434
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_filter_mask_2_off_addr_byte3 == 24'd8390435
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_gen2_ctrl_off_addr_byte0 == 24'd8390668
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_gen2_ctrl_off_addr_byte1 == 24'd8390669
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_gen2_ctrl_off_addr_byte2 == 24'd12584974
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_gen3_eq_control_off_addr_byte0 == 24'd8390824
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_gen3_eq_control_off_addr_byte1 == 24'd8390825
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_gen3_eq_control_off_addr_byte2 == 24'd8390826
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_gen3_eq_control_off_addr_byte3 == 24'd8390827
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_gen3_eq_control_off_atg4_addr_byte0 == 24'd8390824
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_gen3_eq_control_off_atg4_addr_byte1 == 24'd8390825
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_gen3_eq_control_off_atg4_addr_byte2 == 24'd8390826
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_gen3_eq_control_off_atg4_addr_byte3 == 24'd8390827
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_gen3_eq_local_fs_lf_off_addr_byte1 == 24'd2217
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_gen3_related_off_addr_byte0 == 24'd8390800
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_gen3_related_off_addr_byte1 == 24'd8390801
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_gen3_related_off_addr_byte2 == 24'd8390802
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_gen3_related_off_addr_byte3 == 24'd8390803
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_gen3_related_off_atg4_addr_byte0 == 24'd8390800
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_gen3_related_off_atg4_addr_byte1 == 24'd8390801
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_gen3_related_off_atg4_addr_byte2 == 24'd8390802
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_gen3_related_off_atg4_addr_byte3 == 24'd8390803
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_misc_control_1_off_addr_byte0 == 24'd2236
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_misc_control_1_off_addr_byte1 == 24'd2237
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_misc_control_1_off_addr_byte2 == 24'd2238
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_pipe_loopback_control_off_addr_byte3 == 24'd8390843
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_port_force_off_addr_byte0 == 24'd8390408
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_port_link_ctrl_off_addr_byte0 == 24'd8390416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_port_link_ctrl_off_addr_byte2 == 24'd8390418
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_queue_status_off_addr_byte2 == 24'd8390462
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_queue_status_off_addr_byte3 == 24'd8390463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_symbol_timer_filter_1_off_addr_byte0 == 24'd8390428
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_symbol_timer_filter_1_off_addr_byte1 == 24'd8390429
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_symbol_timer_filter_1_off_addr_byte2 == 24'd8390430
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_symbol_timer_filter_1_off_addr_byte3 == 24'd8390431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_timer_ctrl_max_func_num_off_addr_byte0 == 24'd8390424
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_vc0_cpl_rx_q_ctrl_off_addr_byte0 == 24'd8390480
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_vc0_cpl_rx_q_ctrl_off_addr_byte1 == 24'd8390481
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_vc0_cpl_rx_q_ctrl_off_addr_byte2 == 24'd8390482
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_vc0_cpl_rx_q_ctrl_off_addr_byte3 == 24'd8390483
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_vc0_np_rx_q_ctrl_off_addr_byte0 == 24'd8390476
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_vc0_np_rx_q_ctrl_off_addr_byte1 == 24'd8390477
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_vc0_np_rx_q_ctrl_off_addr_byte2 == 24'd8390478
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_vc0_p_rx_q_ctrl_off_addr_byte0 == 24'd8390472
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_vc0_p_rx_q_ctrl_off_addr_byte1 == 24'd8390473
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_port_logic_vc0_p_rx_q_ctrl_off_addr_byte2 == 24'd8390474
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_power_state == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_pre_det_lane == PF0_DET_ALL_LANES
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_program_interface == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte2 == 24'd8389342
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte3 == 24'd8389343
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_prs_ext_cap_prs_req_capacity_reg_addr_byte0 == 24'd8389348
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_prs_ext_cap_prs_req_capacity_reg_addr_byte1 == 24'd8389349
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_prs_ext_cap_prs_req_capacity_reg_addr_byte2 == 24'd8389350
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_prs_ext_cap_prs_req_capacity_reg_addr_byte3 == 24'd8389351
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_prs_ext_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_prs_ext_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_prs_outstanding_capacity == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_cap_off_reserved3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_cap_off_reserved3_dup == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_cap_ptm_cap_off_addr_byte0 == 24'd8389700
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_cap_ptm_cap_off_addr_byte0_dup == 24'd8389700
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_cap_ptm_ext_cap_hdr_off_addr_byte2 == 24'd8389698
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_cap_ptm_ext_cap_hdr_off_addr_byte3 == 24'd8389699
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_capable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_capable_dup == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_capi_ptm_req_cap_hdr_off_dbi_addr_byte2 == 24'd8389710
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_capi_ptm_req_cap_hdr_off_dbi_addr_byte3 == 24'd8389711
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_capi_ptm_req_control_off_dbi_addr_byte0 == 24'd8389716
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_capi_ptm_req_control_off_dbi_addr_byte1 == 24'd8389717
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_capi_ptm_req_latency_reg_sel_off_gen1_dbi_addr_byte0 == 24'd8389808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_capi_ptm_req_latency_reg_sel_off_gen2_dbi_addr_byte0 == 24'd8389808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_capi_ptm_req_latency_reg_sel_off_gen3_dbi_addr_byte0 == 24'd8389808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_capi_ptm_req_latency_reg_sel_off_gen4_dbi_addr_byte0 == 24'd8389808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_capi_ptm_req_rx_latency_off_gen1_dbi_addr_byte0 == 24'd8389788
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_capi_ptm_req_rx_latency_off_gen1_dbi_addr_byte1 == 24'd8389789
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_capi_ptm_req_rx_latency_off_gen2_dbi_addr_byte0 == 24'd8389788
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_capi_ptm_req_rx_latency_off_gen2_dbi_addr_byte1 == 24'd8389789
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_capi_ptm_req_rx_latency_off_gen3_dbi_addr_byte0 == 24'd8389788
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_capi_ptm_req_rx_latency_off_gen3_dbi_addr_byte1 == 24'd8389789
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_capi_ptm_req_rx_latency_off_gen4_dbi_addr_byte0 == 24'd8389788
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_capi_ptm_req_rx_latency_off_gen4_dbi_addr_byte1 == 24'd8389789
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_capi_ptm_req_tx_latency_off_gen1_dbi_addr_byte0 == 24'd8389784
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_capi_ptm_req_tx_latency_off_gen1_dbi_addr_byte1 == 24'd8389785
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_capi_ptm_req_tx_latency_off_gen2_dbi_addr_byte0 == 24'd8389784
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_capi_ptm_req_tx_latency_off_gen2_dbi_addr_byte1 == 24'd8389785
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_capi_ptm_req_tx_latency_off_gen3_dbi_addr_byte0 == 24'd8389784
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_capi_ptm_req_tx_latency_off_gen3_dbi_addr_byte1 == 24'd8389785
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_capi_ptm_req_tx_latency_off_gen4_dbi_addr_byte0 == 24'd8389784
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_capi_ptm_req_tx_latency_off_gen4_dbi_addr_byte1 == 24'd8389785
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_control_off_ptm_req_auto_update_enabled == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_control_off_ptm_req_fast_timers == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_control_off_ptm_req_long_timer == 8'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_control_off_ptm_req_start_update == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_control_off_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_ext_cap_next_offs == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_ext_cap_ver == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_latency_reg_sel_gen1 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_latency_reg_sel_gen2 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_latency_reg_sel_gen3 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_latency_reg_sel_gen4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_latency_reg_sel_off_gen1_reserved4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_latency_reg_sel_off_gen2_reserved4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_latency_reg_sel_off_gen3_reserved4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_latency_reg_sel_off_gen4_reserved4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_rx_latency_gen1 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_rx_latency_gen2 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_rx_latency_gen3 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_rx_latency_gen4 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_rx_latency_off_gen1_reserved12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_rx_latency_off_gen2_reserved12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_rx_latency_off_gen3_reserved12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_rx_latency_off_gen4_reserved12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_tx_latency_gen1 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_tx_latency_gen2 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_tx_latency_gen3 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_tx_latency_gen4 == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_tx_latency_off_gen1_reserved12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_tx_latency_off_gen2_reserved12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_tx_latency_off_gen3_reserved12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_req_tx_latency_off_gen4_reserved12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_res_capable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_res_capable_dup == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_root_capable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ptm_root_capable_dup == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_queue_status_off_rsvdp_29 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ras_des_cap_event_counter_ctrl_reg_addr_byte0 == 24'd772
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ras_des_cap_event_counter_ctrl_reg_g5_addr_byte3 == 24'd8389383
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ras_des_cap_event_counter_ctrl_reg_g6_addr_byte3 == 24'd8389383
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ras_des_cap_event_counter_ctrl_reg_g7_addr_byte3 == 24'd8389383
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ras_des_cap_force_detect_lane == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ras_des_cap_force_detect_lane_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ras_des_cap_ras_des_hdr_reg_addr_byte2 == 24'd8389374
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ras_des_cap_ras_des_hdr_reg_addr_byte3 == 24'd8389375
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ras_des_cap_sd_control1_reg_addr_byte0 == 24'd8389532
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ras_des_cap_sd_control1_reg_addr_byte1 == 24'd8389533
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ras_des_cap_sd_control1_reg_addr_byte2 == 24'd8389534
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ras_des_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ras_des_event_counter_en == 8'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ras_des_event_counter_event_select_g5 == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ras_des_event_counter_event_select_g6 == 8'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ras_des_event_counter_event_select_g7 == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_ras_des_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_rate_shadow_sel == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_rate_shadow_sel_atg4 == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved10 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved250 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved4 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved6 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved8 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved9 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_10_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_11_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_12_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_13_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_14_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_15_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_16_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_17_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_18_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_19_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_20_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_21_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_22_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_23_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_24_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_25_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_26_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_27_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_28_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_29_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_30_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_31_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_32_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_33_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_34_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_35_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_36_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_37_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_38_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_39_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_40_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_41_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_42_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_43_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_44_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_8_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reserved_9_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_reset_assert == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_revision_id == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_rom_bar_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_rom_bar_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_root_control_root_capabilities_reg_rsvdp_17 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_root_err_status_off_rsvdp_7 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_rp_exp_rom_bar_mask_reg_rp_rom_rsvdp_1 == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_rp_rom_bar_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_rp_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_rxeq_ph01_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_rxeq_ph01_en_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_rxeq_rgrdless_rxts == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_rxeq_rgrdless_rxts_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_rxstatus_value == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_scramble_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sel_deemphasis == PF0_MINUS_6DB_CTL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_shadow_sriov_vf_stride_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_simplified_replay_timer == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_skp_int_val == 11'd640
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sn_cap_ser_num_reg_dw_1_addr_byte0 == 24'd8388968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sn_cap_ser_num_reg_dw_1_addr_byte1 == 24'd8388969
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sn_cap_ser_num_reg_dw_1_addr_byte2 == 24'd8388970
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sn_cap_ser_num_reg_dw_1_addr_byte3 == 24'd8388971
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sn_cap_ser_num_reg_dw_2_addr_byte0 == 24'd8388972
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sn_cap_ser_num_reg_dw_2_addr_byte1 == 24'd8388973
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sn_cap_ser_num_reg_dw_2_addr_byte2 == 24'd8388974
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sn_cap_ser_num_reg_dw_2_addr_byte3 == 24'd8388975
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sn_cap_sn_base_addr_byte2 == 24'd8388966
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sn_cap_sn_base_addr_byte3 == 24'd8388967
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sn_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sn_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sn_ser_num_reg_1_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sn_ser_num_reg_2_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_spcie_cap_lane_equalization_control01_reg_addr_byte0 == 24'd8389008
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_spcie_cap_lane_equalization_control01_reg_addr_byte1 == 24'd8389009
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_spcie_cap_lane_equalization_control01_reg_addr_byte2 == 24'd8389010
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_spcie_cap_lane_equalization_control01_reg_addr_byte3 == 24'd8389011
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_spcie_cap_lane_equalization_control1011_reg_addr_byte0 == 24'd412
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_spcie_cap_lane_equalization_control1011_reg_addr_byte1 == 24'd8389021
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_spcie_cap_lane_equalization_control1011_reg_addr_byte2 == 24'd414
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_spcie_cap_lane_equalization_control1011_reg_addr_byte3 == 24'd8389023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_spcie_cap_lane_equalization_control1213_reg_addr_byte0 == 24'd412
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_spcie_cap_lane_equalization_control1213_reg_addr_byte1 == 24'd8389021
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_spcie_cap_lane_equalization_control1213_reg_addr_byte2 == 24'd414
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_spcie_cap_lane_equalization_control1213_reg_addr_byte3 == 24'd8389023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_spcie_cap_lane_equalization_control1415_reg_addr_byte0 == 24'd412
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_spcie_cap_lane_equalization_control1415_reg_addr_byte1 == 24'd8389021
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_spcie_cap_lane_equalization_control1415_reg_addr_byte2 == 24'd414
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_spcie_cap_lane_equalization_control1415_reg_addr_byte3 == 24'd8389023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_spcie_cap_lane_equalization_control23_reg_addr_byte0 == 24'd404
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_spcie_cap_lane_equalization_control23_reg_addr_byte1 == 24'd8389013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_spcie_cap_lane_equalization_control23_reg_addr_byte2 == 24'd406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_spcie_cap_lane_equalization_control23_reg_addr_byte3 == 24'd8389015
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_spcie_cap_lane_equalization_control45_reg_addr_byte0 == 24'd408
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_spcie_cap_lane_equalization_control45_reg_addr_byte1 == 24'd8389017
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_spcie_cap_lane_equalization_control45_reg_addr_byte2 == 24'd410
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_spcie_cap_lane_equalization_control45_reg_addr_byte3 == 24'd8389019
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_spcie_cap_lane_equalization_control67_reg_addr_byte0 == 24'd412
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_spcie_cap_lane_equalization_control67_reg_addr_byte1 == 24'd8389021
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_spcie_cap_lane_equalization_control67_reg_addr_byte2 == 24'd414
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_spcie_cap_lane_equalization_control67_reg_addr_byte3 == 24'd8389023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_spcie_cap_lane_equalization_control89_reg_addr_byte0 == 24'd412
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_spcie_cap_lane_equalization_control89_reg_addr_byte1 == 24'd8389021
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_spcie_cap_lane_equalization_control89_reg_addr_byte2 == 24'd414
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_spcie_cap_lane_equalization_control89_reg_addr_byte3 == 24'd8389023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_spcie_cap_spcie_cap_header_reg_addr_byte2 == 24'd8388998
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_spcie_cap_spcie_cap_header_reg_addr_byte3 == 24'd8388999
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_spcie_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_spcie_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_shadow_sriov_initial_vfs_addr_byte0 == 24'd10486272
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_shadow_sriov_initial_vfs_addr_byte1 == 24'd10486273
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_shadow_sriov_vf_offset_position_addr_byte0 == 24'd10486280
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_shadow_sriov_vf_offset_position_addr_byte1 == 24'd10486281
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_shadow_sriov_vf_offset_position_addr_byte2 == 24'd10486282
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_shadow_sriov_vf_offset_position_addr_byte3 == 24'd10486283
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_shadow_vf_bar0_reg_addr_byte0 == 24'd2097688
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_shadow_vf_bar0_reg_addr_byte1 == 24'd2097689
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_shadow_vf_bar0_reg_addr_byte2 == 24'd2097690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_shadow_vf_bar0_reg_addr_byte3 == 24'd2097691
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_shadow_vf_bar1_reg_addr_byte0 == 24'd2097692
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_shadow_vf_bar1_reg_addr_byte1 == 24'd2097693
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_shadow_vf_bar1_reg_addr_byte2 == 24'd2097694
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_shadow_vf_bar1_reg_addr_byte3 == 24'd2097695
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_shadow_vf_bar2_reg_addr_byte0 == 24'd2097696
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_shadow_vf_bar2_reg_addr_byte1 == 24'd2097697
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_shadow_vf_bar2_reg_addr_byte2 == 24'd2097698
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_shadow_vf_bar2_reg_addr_byte3 == 24'd2097699
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_shadow_vf_bar3_reg_addr_byte0 == 24'd2097700
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_shadow_vf_bar3_reg_addr_byte1 == 24'd2097701
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_shadow_vf_bar3_reg_addr_byte2 == 24'd2097702
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_shadow_vf_bar3_reg_addr_byte3 == 24'd2097703
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_shadow_vf_bar4_reg_addr_byte0 == 24'd2097704
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_shadow_vf_bar4_reg_addr_byte1 == 24'd2097705
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_shadow_vf_bar4_reg_addr_byte2 == 24'd2097706
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_shadow_vf_bar4_reg_addr_byte3 == 24'd2097707
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_shadow_vf_bar5_reg_addr_byte0 == 24'd2097708
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_shadow_vf_bar5_reg_addr_byte1 == 24'd2097709
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_shadow_vf_bar5_reg_addr_byte2 == 24'd2097710
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_shadow_vf_bar5_reg_addr_byte3 == 24'd2097711
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_sriov_bar1_enable_reg_addr_byte0 == 24'd2097692
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_sriov_bar3_enable_reg_addr_byte0 == 24'd2097700
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_sriov_bar5_enable_reg_addr_byte0 == 24'd2097708
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_sriov_base_reg_addr_byte2 == 24'd8389110
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_sriov_base_reg_addr_byte3 == 24'd8389111
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_sriov_initial_vfs_addr_byte0 == 24'd8389120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_sriov_initial_vfs_addr_byte1 == 24'd8389121
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_sriov_vf_offset_position_addr_byte0 == 24'd8389128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_sriov_vf_offset_position_addr_byte1 == 24'd8389129
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_sriov_vf_offset_position_addr_byte2 == 24'd8389130
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_sriov_vf_offset_position_addr_byte3 == 24'd8389131
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_sup_page_sizes_reg_addr_byte0 == 24'd8389136
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_sup_page_sizes_reg_addr_byte1 == 24'd8389137
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_sup_page_sizes_reg_addr_byte2 == 24'd8389138
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_sup_page_sizes_reg_addr_byte3 == 24'd8389139
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_vf_bar0_reg_addr_byte0 == 24'd536
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_vf_bar1_reg_addr_byte0 == 24'd540
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_vf_bar2_reg_addr_byte0 == 24'd544
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_vf_bar3_reg_addr_byte0 == 24'd548
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_vf_bar4_reg_addr_byte0 == 24'd552
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_vf_bar5_reg_addr_byte0 == 24'd556
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_vf_device_id_reg_addr_byte2 == 24'd8389134
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_cap_vf_device_id_reg_addr_byte3 == 24'd8389135
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_initial_vfs_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_initial_vfs_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_sup_page_size == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_vf_bar0_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_vf_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_vf_bar0_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_vf_bar0_type == PF0_SRIOV_VF_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_vf_bar1_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_vf_bar1_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_vf_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_vf_bar1_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_vf_bar1_type == PF0_SRIOV_VF_BAR1_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_vf_bar2_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_vf_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_vf_bar2_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_vf_bar2_type == PF0_SRIOV_VF_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_vf_bar3_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_vf_bar3_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_vf_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_vf_bar3_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_vf_bar3_type == PF0_SRIOV_VF_BAR3_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_vf_bar4_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_vf_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_vf_bar4_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_vf_bar4_type == PF0_SRIOV_VF_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_vf_bar5_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_vf_bar5_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_vf_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_vf_bar5_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_vf_bar5_type == PF0_SRIOV_VF_BAR5_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_vf_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_vf_offset_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_vf_offset_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_sriov_vf_stride_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_subclass_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_subsys_dev_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_subsys_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_target_above_config_limit == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_timer_mod_flow_control == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_timer_mod_flow_control_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_tlp_bypass_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_tph_cap_tph_ext_cap_hdr_reg_addr_byte2 == 24'd8389174
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_tph_cap_tph_ext_cap_hdr_reg_addr_byte3 == 24'd8389175
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_tph_cap_tph_req_cap_reg_addr_byte0 == 24'd8389176
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_tph_cap_tph_req_cap_reg_addr_byte1 == 24'd8389177
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_tph_cap_tph_req_cap_reg_addr_byte2 == 24'd8389178
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_tph_cap_tph_req_cap_reg_addr_byte3 == 24'd8389179
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte0 == 24'd10486328
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte1 == 24'd10486329
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte2 == 24'd10486330
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte3 == 24'd10486331
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_tph_req_cap_int_vec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_tph_req_cap_int_vec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_tph_req_cap_reg_rsvdp_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_tph_req_cap_reg_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_tph_req_cap_reg_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_tph_req_cap_reg_vfcomm_cs2_rsvdp_11_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_tph_req_cap_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_tph_req_cap_reg_vfcomm_cs2_rsvdp_3_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_tph_req_cap_st_table_loc_0 == PF0_NOT_IN_TPH_STRUCT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_tph_req_cap_st_table_loc_0_vfcomm_cs2 == PF0_NOT_IN_TPH_STRUCT_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_tph_req_cap_st_table_loc_1 == PF0_NOT_IN_MSIX_TABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_tph_req_cap_st_table_loc_1_vfcomm_cs2 == PF0_NOT_IN_MSIX_TABLE_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_tph_req_cap_st_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_tph_req_cap_st_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_tph_req_cap_ver == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_tph_req_device_spec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_tph_req_device_spec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_tph_req_extended_tph == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_tph_req_extended_tph_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_tph_req_next_ptr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_tph_req_no_st_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_tph_req_no_st_mode_vfcomm_cs2 == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_bar0_mask_reg_addr_byte0 == 24'd2097168
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_bar0_mask_reg_addr_byte1 == 24'd2097169
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_bar0_mask_reg_addr_byte2 == 24'd2097170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_bar0_mask_reg_addr_byte3 == 24'd2097171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_bar0_reg_addr_byte0 == 24'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_bar1_enable_reg_addr_byte0 == 24'd2097172
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_bar1_mask_reg_addr_byte0 == 24'd2097172
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_bar1_mask_reg_addr_byte1 == 24'd2097173
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_bar1_mask_reg_addr_byte2 == 24'd2097174
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_bar1_mask_reg_addr_byte3 == 24'd2097175
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_bar1_reg_addr_byte0 == 24'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_bar2_mask_reg_addr_byte0 == 24'd2097176
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_bar2_mask_reg_addr_byte1 == 24'd2097177
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_bar2_mask_reg_addr_byte2 == 24'd2097178
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_bar2_mask_reg_addr_byte3 == 24'd2097179
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_bar2_reg_addr_byte0 == 24'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_bar3_enable_reg_addr_byte0 == 24'd2097180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_bar3_mask_reg_addr_byte0 == 24'd2097180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_bar3_mask_reg_addr_byte1 == 24'd2097181
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_bar3_mask_reg_addr_byte2 == 24'd2097182
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_bar3_mask_reg_addr_byte3 == 24'd2097183
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_bar3_reg_addr_byte0 == 24'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_bar4_mask_reg_addr_byte0 == 24'd2097184
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_bar4_mask_reg_addr_byte1 == 24'd2097185
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_bar4_mask_reg_addr_byte2 == 24'd2097186
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_bar4_mask_reg_addr_byte3 == 24'd2097187
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_bar4_reg_addr_byte0 == 24'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_bar5_enable_reg_addr_byte0 == 24'd2097188
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_bar5_mask_reg_addr_byte0 == 24'd2097188
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_bar5_mask_reg_addr_byte1 == 24'd2097189
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_bar5_mask_reg_addr_byte2 == 24'd2097190
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_bar5_mask_reg_addr_byte3 == 24'd2097191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_bar5_reg_addr_byte0 == 24'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_bist_header_type_latency_cache_line_size_reg_addr_byte2 == 24'd8388622
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_cardbus_cis_ptr_reg_addr_byte0 == 24'd8388648
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_cardbus_cis_ptr_reg_addr_byte1 == 24'd8388649
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_cardbus_cis_ptr_reg_addr_byte2 == 24'd8388650
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_cardbus_cis_ptr_reg_addr_byte3 == 24'd8388651
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_class_code_revision_id_addr_byte0 == 24'd8388616
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_class_code_revision_id_addr_byte1 == 24'd8388617
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_class_code_revision_id_addr_byte2 == 24'd8388618
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_class_code_revision_id_addr_byte3 == 24'd8388619
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_device_id_vendor_id_reg_addr_byte0 == 24'd8388608
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_device_id_vendor_id_reg_addr_byte1 == 24'd8388609
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_device_id_vendor_id_reg_addr_byte2 == 24'd8388610
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_device_id_vendor_id_reg_addr_byte3 == 24'd8388611
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_exp_rom_bar_mask_reg_addr_byte0 == 24'd2097200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_exp_rom_bar_mask_reg_addr_byte1 == 24'd2097201
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_exp_rom_bar_mask_reg_addr_byte2 == 24'd2097202
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_exp_rom_bar_mask_reg_addr_byte3 == 24'd2097203
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_exp_rom_base_addr_reg_addr_byte0 == 24'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_max_latency_min_grant_interrupt_pin_interrupt_line_reg_addr_byte1 == 24'd8388669
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_pci_cap_ptr_reg_addr_byte0 == 24'd8388660
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_rp_exp_rom_bar_mask_reg_addr_byte0 == 24'd2097208
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_rp_exp_rom_bar_mask_reg_addr_byte1 == 24'd2097209
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_rp_exp_rom_bar_mask_reg_addr_byte2 == 24'd2097210
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_rp_exp_rom_bar_mask_reg_addr_byte3 == 24'd2097211
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte0 == 24'd8388652
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte1 == 24'd8388653
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte2 == 24'd8388654
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte3 == 24'd8388655
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_16g_tx_preset0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_16g_tx_preset1 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_16g_tx_preset10 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_16g_tx_preset11 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_16g_tx_preset12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_16g_tx_preset13 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_16g_tx_preset14 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_16g_tx_preset15 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_16g_tx_preset2 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_16g_tx_preset3 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_16g_tx_preset4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_16g_tx_preset5 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_16g_tx_preset6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_16g_tx_preset7 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_16g_tx_preset8 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_16g_tx_preset9 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_rx_preset_hint0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_rx_preset_hint1 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_rx_preset_hint10 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_rx_preset_hint11 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_rx_preset_hint12 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_rx_preset_hint13 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_rx_preset_hint14 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_rx_preset_hint15 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_rx_preset_hint2 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_rx_preset_hint3 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_rx_preset_hint4 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_rx_preset_hint5 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_rx_preset_hint6 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_rx_preset_hint7 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_rx_preset_hint8 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_rx_preset_hint9 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_send_8gt_eq_ts2_disable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_send_8gt_eq_ts2_disable_atg4 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_tx_preset0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_tx_preset1 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_tx_preset10 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_tx_preset11 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_tx_preset12 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_tx_preset13 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_tx_preset14 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_tx_preset15 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_tx_preset2 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_tx_preset3 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_tx_preset4 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_tx_preset5 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_tx_preset6 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_tx_preset7 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_tx_preset8 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_tx_preset9 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_vc0_cpl_data_credit == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_vc0_cpl_data_scale == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_vc0_cpl_hdr_scale == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_vc0_cpl_header_credit == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_vc0_cpl_tlp_q_mode == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_vc0_np_data_credit == 12'd196
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_vc0_np_header_credit == 8'd98
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_vc0_np_tlp_q_mode == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_vc0_p_data_credit == 12'd760
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_vc0_p_header_credit == 8'd98
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_vc0_p_tlp_q_mode == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_vc_cap_vc_base_addr_byte2 == 24'd8388938
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_vc_cap_vc_base_addr_byte3 == 24'd8388939
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_vc_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_vc_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_vendor_specific_dllp_req == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_vf_bar0_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_vf_bar1_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_vf_bar2_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_vf_bar3_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_vf_bar4_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_vf_bar5_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_vsecras_cap_rasdp_ext_hdr_off_addr_byte2 == 24'd8389630
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_vsecras_cap_rasdp_ext_hdr_off_addr_byte3 == 24'd8389631
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_vsecras_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_vsecras_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_acs_cap_acs_at_block == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_acs_cap_acs_cap_hdr_reg_addr_byte2 == 24'd8393426
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_acs_cap_acs_cap_hdr_reg_addr_byte3 == 24'd8393427
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_acs_cap_acs_capalities_ctrl_reg_addr_byte0 == 24'd8393428
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_acs_cap_acs_capalities_ctrl_reg_addr_byte1 == 24'd4821
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_acs_cap_acs_direct_translated_p2p == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_acs_cap_acs_egress_ctrl_size == 8'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_acs_cap_acs_p2p_cpl_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_acs_cap_acs_p2p_egress_control == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_acs_cap_acs_p2p_req_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_acs_cap_acs_src_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_acs_cap_acs_usp_forwarding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_acs_cap_rsvdp_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_acs_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_acs_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_aer_cap_aer_ext_cap_hdr_off_addr_byte2 == 24'd8392962
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_aer_cap_aer_ext_cap_hdr_off_addr_byte3 == 24'd8392963
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_aer_cap_version == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_aer_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_ari_cap_ari_base_addr_byte2 == 24'd8393078
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_ari_cap_ari_base_addr_byte3 == 24'd8393079
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_ari_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_ari_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_ats_cap_ats_cap_hdr_reg_addr_byte2 == 24'd8393410
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_ats_cap_ats_cap_hdr_reg_addr_byte3 == 24'd8393411
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_ats_cap_ats_capabilities_ctrl_reg_addr_byte0 == 24'd8393412
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_ats_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_ats_capabilities_ctrl_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_ats_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_aux_curr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_bar0_mem_io == PF1_BAR0_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_bar0_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_bar0_type == PF1_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_bar1_mem_io == PF1_BAR1_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_bar1_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_bar1_type == PF1_BAR1_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_bar2_mem_io == PF1_BAR2_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_bar2_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_bar2_type == PF1_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_bar3_mem_io == PF1_BAR3_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_bar3_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_bar3_type == PF1_BAR3_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_bar4_mem_io == PF1_BAR4_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_bar4_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_bar4_type == PF1_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_bar5_mem_io == PF1_BAR5_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_bar5_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_bar5_type == PF1_BAR5_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_base_class_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_cap_id_nxt_ptr_reg_rsvdp_20 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_cap_pointer == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_cardbus_cis_pointer == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_con_status_reg_rsvdp_2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_con_status_reg_rsvdp_4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_d1_support == PF1_D1_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_d2_support == PF1_D2_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_10 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_11 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_12 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_13 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_14 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_15 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_16 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_17 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_18 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_19 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_20 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_21 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_22 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_23 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_24 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_25 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_26 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_27 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_28 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_29 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_30 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_31 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_32 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_33 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_34 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_35 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_36 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_37 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_38 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_39 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_40 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_41 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_42 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_43 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_44 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_45 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_46 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_47 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_48 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_49 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_50 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_51 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_52 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_53 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_54 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_55 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_56 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_57 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_58 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_59 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_6 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_60 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_61 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_62 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_63 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_64 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_65 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_7 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_8 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dbi_reserved_9 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_device_capabilities_reg_rsvdp_12 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_device_capabilities_reg_rsvdp_16 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_device_capabilities_reg_rsvdp_29 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_dsi == PF1_NOT_REQUIRED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_exp_rom_bar_mask_reg_rsvdp_1 == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_exp_rom_base_addr_reg_rsvdp_1 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_global_inval_spprtd == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_header_type == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_int_pin == PF1_NO_INT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_invalidate_q_depth == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_link_capabilities_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_link_control_link_status_reg_rsvdp_12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_link_control_link_status_reg_rsvdp_2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_link_control_link_status_reg_rsvdp_26 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_link_control_link_status_reg_rsvdp_9 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte1 == 24'd8392785
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte2 == 24'd8392786
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte3 == 24'd8392787
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_msi_cap_pci_msi_cap_id_next_ctrl_reg_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_msix_cap_msix_pba_offset_reg_addr_byte0 == 24'd8392888
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_msix_cap_msix_pba_offset_reg_addr_byte1 == 24'd8392889
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_msix_cap_msix_pba_offset_reg_addr_byte2 == 24'd8392890
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_msix_cap_msix_pba_offset_reg_addr_byte3 == 24'd8392891
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_msix_cap_msix_table_offset_reg_addr_byte0 == 24'd8392884
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_msix_cap_msix_table_offset_reg_addr_byte1 == 24'd8392885
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_msix_cap_msix_table_offset_reg_addr_byte2 == 24'd8392886
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_msix_cap_msix_table_offset_reg_addr_byte3 == 24'd8392887
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte1 == 24'd8392881
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte2 == 24'd8392882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte3 == 24'd8392883
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte2 == 24'd10490034
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte3 == 24'd10490035
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_multi_func == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_no_soft_rst == PF1_INTERNALLY_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_page_aligned_req == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pasid_cap_execute_permission_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pasid_cap_max_pasid_width == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pasid_cap_pasid_cap_cntrl_reg_addr_byte0 == 24'd8393464
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pasid_cap_pasid_cap_cntrl_reg_addr_byte1 == 24'd8393465
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pasid_cap_pasid_ext_hdr_reg_addr_byte2 == 24'd8393462
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pasid_cap_pasid_ext_hdr_reg_addr_byte3 == 24'd8393463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pasid_cap_privileged_mode_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pasid_cap_rsvdp_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pasid_cap_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pasid_cap_rsvpd_13 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pasid_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pasid_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_msi_64_bit_addr_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_msi_cap_next_offset == 8'd112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_msi_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_msi_ext_data_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_msi_ext_data_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_msi_multiple_msg_cap == PF1_MSI_VEC_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_msi_multiple_msg_en == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_msix_bir == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_msix_cap_id_next_ctrl_reg_rsvdp_27 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_msix_cap_next_offset == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_msix_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_msix_enable_vfcomm_cs2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_msix_function_mask == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_msix_function_mask_vfcomm_cs2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_msix_pba == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_msix_pba_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_msix_table_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_msix_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_msix_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_pvm_support == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_type0_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_type0_bar0_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_type0_bar1_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_type0_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_type0_bar1_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_type0_bar1_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_type0_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_type0_bar2_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_type0_bar3_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_type0_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_type0_bar3_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_type0_bar3_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_type0_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_type0_bar4_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_type0_bar5_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_type0_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_type0_bar5_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_type0_bar5_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_type0_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pci_type0_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_active_state_link_pm_control == PF1_ASPM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_active_state_link_pm_support == PF1_NO_ASPM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_aspm_opt_compliance == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_aux_power_pm_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_clock_power_man == PF1_REFCLK_REMOVE_NOT_OK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_common_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_device_capabilities_reg_addr_byte0 == 24'd8392820
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_device_capabilities_reg_addr_byte1 == 24'd8392821
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_device_capabilities_reg_addr_byte3 == 24'd8392823
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_device_control_device_status_addr_byte1 == 24'd8392825
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_dll_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_dll_active_rep_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_en_clk_power_man == PF1_CLKREQ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_en_no_snoop == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_enter_compliance == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_ep_l0s_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_ep_l1_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_ext_tag_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_ext_tag_supp == PF1_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_extended_synch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_flr_cap == PF1_NOT_CAPABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_hw_auto_speed_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvd == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_initiate_flr == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_l0s_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_l1_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_link_auto_bw_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_link_auto_bw_status == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_link_bw_man_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_link_bw_man_status == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_link_bw_not_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_link_capabilities_reg_addr_byte0 == 24'd8392828
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_link_capabilities_reg_addr_byte1 == 24'd8392829
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_link_capabilities_reg_addr_byte2 == 24'd8392830
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_link_capabilities_reg_addr_byte3 == 24'd4223
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_link_control2_link_status2_reg_addr_byte0 == 24'd12587168
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_link_control_link_status_reg_addr_byte0 == 24'd4198528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_link_control_link_status_reg_addr_byte1 == 24'd12587137
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_link_control_link_status_reg_addr_byte3 == 24'd4198531
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_link_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_link_training == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_max_link_speed == PF1_MAX_2P5GTS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_max_link_width == PF1_X1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_max_payload_size == PF1_PAYLOAD_128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_max_read_req_size == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_nego_link_width == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_next_ptr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte1 == 24'd8392817
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte3 == 24'd8392819
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_phantom_func_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_phantom_func_support == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_port_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_rcb == PF1_RCB_64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_retrain_link == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_role_based_err_report == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_sel_deemphasis == PF1_MINUS_6DB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_slot_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_surprise_down_err_rep_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_target_link_speed == PF1_TRGT_GEN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_cap_tx_margin == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_int_msg_num == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pcie_slot_imp == PF1_NOT_IMPLEMENTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pf0_ari_device_number == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pf0_dbi_ro_wr_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pf0_default_target == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pf0_disable_auto_ltr_clr_msg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pf0_mask_ur_ca_4_trgt1 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pf0_misc_control_1_off_rsvdp_6 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pf0_port_logic_misc_control_1_off_addr_byte0 == 24'd2236
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pf0_simplified_replay_timer == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pf0_tlp_bypass_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pm_cap_cap_id_nxt_ptr_reg_addr_byte1 == 24'd8392769
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pm_cap_cap_id_nxt_ptr_reg_addr_byte2 == 24'd8392770
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pm_cap_cap_id_nxt_ptr_reg_addr_byte3 == 24'd8392771
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pm_cap_con_status_reg_addr_byte0 == 24'd8392772
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pm_next_pointer == 8'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pm_spec_ver == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pme_clk == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_pme_support == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_power_state == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_program_interface == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte2 == 24'd8393438
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte3 == 24'd8393439
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_prs_ext_cap_prs_req_capacity_reg_addr_byte0 == 24'd8393444
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_prs_ext_cap_prs_req_capacity_reg_addr_byte1 == 24'd8393445
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_prs_ext_cap_prs_req_capacity_reg_addr_byte2 == 24'd8393446
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_prs_ext_cap_prs_req_capacity_reg_addr_byte3 == 24'd8393447
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_prs_ext_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_prs_ext_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_prs_outstanding_capacity == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_ras_des_cap_event_counter_ctrl_reg_addr_byte0 == 24'd4868
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_ras_des_cap_event_counter_ctrl_reg_g5_addr_byte3 == 24'd8393479
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_ras_des_cap_event_counter_ctrl_reg_g6_addr_byte3 == 24'd8393479
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_ras_des_cap_event_counter_ctrl_reg_g7_addr_byte3 == 24'd8393479
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_ras_des_cap_force_detect_lane == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_ras_des_cap_force_detect_lane_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_ras_des_cap_ras_des_hdr_reg_addr_byte2 == 24'd8393470
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_ras_des_cap_ras_des_hdr_reg_addr_byte3 == 24'd8393471
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_ras_des_cap_sd_control1_reg_addr_byte0 == 24'd8393628
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_ras_des_cap_sd_control1_reg_addr_byte1 == 24'd8393629
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_ras_des_cap_sd_control1_reg_addr_byte2 == 24'd8393630
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_ras_des_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_ras_des_event_counter_en == 8'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_ras_des_event_counter_event_select_g5 == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_ras_des_event_counter_event_select_g6 == 8'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_ras_des_event_counter_event_select_g7 == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_ras_des_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_10_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_11_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_12_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_13_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_14_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_15_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_16_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_17_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_18_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_19_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_20_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_21_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_22_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_23_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_24_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_25_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_26_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_27_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_28_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_29_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_30_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_31_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_32_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_33_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_34_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_35_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_36_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_37_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_38_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_39_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_40_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_41_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_42_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_43_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_44_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_45_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_46_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_47_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_48_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_49_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_50_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_51_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_52_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_53_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_54_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_55_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_56_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_57_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_58_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_59_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_60_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_61_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_62_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_63_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_64_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_65_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_7_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_8_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_reserved_9_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_revision_id == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_rom_bar_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_rom_bar_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_shadow_sriov_vf_stride_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sn_cap_ser_num_reg_dw_1_addr_byte0 == 24'd8393064
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sn_cap_ser_num_reg_dw_1_addr_byte1 == 24'd8393065
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sn_cap_ser_num_reg_dw_1_addr_byte2 == 24'd8393066
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sn_cap_ser_num_reg_dw_1_addr_byte3 == 24'd8393067
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sn_cap_ser_num_reg_dw_2_addr_byte0 == 24'd8393068
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sn_cap_ser_num_reg_dw_2_addr_byte1 == 24'd8393069
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sn_cap_ser_num_reg_dw_2_addr_byte2 == 24'd8393070
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sn_cap_ser_num_reg_dw_2_addr_byte3 == 24'd8393071
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sn_cap_sn_base_addr_byte2 == 24'd8393062
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sn_cap_sn_base_addr_byte3 == 24'd8393063
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sn_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sn_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sn_ser_num_reg_1_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sn_ser_num_reg_2_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_shadow_sriov_initial_vfs_addr_byte0 == 24'd10490368
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_shadow_sriov_initial_vfs_addr_byte1 == 24'd10490369
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_shadow_sriov_vf_offset_position_addr_byte0 == 24'd10490376
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_shadow_sriov_vf_offset_position_addr_byte1 == 24'd10490377
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_shadow_sriov_vf_offset_position_addr_byte2 == 24'd10490378
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_shadow_sriov_vf_offset_position_addr_byte3 == 24'd10490379
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_shadow_vf_bar0_reg_addr_byte0 == 24'd2101784
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_shadow_vf_bar0_reg_addr_byte1 == 24'd2101785
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_shadow_vf_bar0_reg_addr_byte2 == 24'd2101786
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_shadow_vf_bar0_reg_addr_byte3 == 24'd2101787
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_shadow_vf_bar1_reg_addr_byte0 == 24'd2101788
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_shadow_vf_bar1_reg_addr_byte1 == 24'd2101789
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_shadow_vf_bar1_reg_addr_byte2 == 24'd2101790
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_shadow_vf_bar1_reg_addr_byte3 == 24'd2101791
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_shadow_vf_bar2_reg_addr_byte0 == 24'd2101792
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_shadow_vf_bar2_reg_addr_byte1 == 24'd2101793
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_shadow_vf_bar2_reg_addr_byte2 == 24'd2101794
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_shadow_vf_bar2_reg_addr_byte3 == 24'd2101795
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_shadow_vf_bar3_reg_addr_byte0 == 24'd2101796
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_shadow_vf_bar3_reg_addr_byte1 == 24'd2101797
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_shadow_vf_bar3_reg_addr_byte2 == 24'd2101798
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_shadow_vf_bar3_reg_addr_byte3 == 24'd2101799
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_shadow_vf_bar4_reg_addr_byte0 == 24'd2101800
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_shadow_vf_bar4_reg_addr_byte1 == 24'd2101801
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_shadow_vf_bar4_reg_addr_byte2 == 24'd2101802
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_shadow_vf_bar4_reg_addr_byte3 == 24'd2101803
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_shadow_vf_bar5_reg_addr_byte0 == 24'd2101804
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_shadow_vf_bar5_reg_addr_byte1 == 24'd2101805
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_shadow_vf_bar5_reg_addr_byte2 == 24'd2101806
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_shadow_vf_bar5_reg_addr_byte3 == 24'd2101807
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_sriov_bar1_enable_reg_addr_byte0 == 24'd2101788
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_sriov_bar3_enable_reg_addr_byte0 == 24'd2101796
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_sriov_bar5_enable_reg_addr_byte0 == 24'd2101804
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_sriov_base_reg_addr_byte2 == 24'd8393206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_sriov_base_reg_addr_byte3 == 24'd8393207
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_sriov_initial_vfs_addr_byte0 == 24'd8393216
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_sriov_initial_vfs_addr_byte1 == 24'd8393217
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_sriov_vf_offset_position_addr_byte0 == 24'd8393224
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_sriov_vf_offset_position_addr_byte1 == 24'd8393225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_sriov_vf_offset_position_addr_byte2 == 24'd8393226
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_sriov_vf_offset_position_addr_byte3 == 24'd8393227
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_sup_page_sizes_reg_addr_byte0 == 24'd8393232
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_sup_page_sizes_reg_addr_byte1 == 24'd8393233
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_sup_page_sizes_reg_addr_byte2 == 24'd8393234
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_sup_page_sizes_reg_addr_byte3 == 24'd8393235
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_vf_bar0_reg_addr_byte0 == 24'd4632
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_vf_bar1_reg_addr_byte0 == 24'd4636
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_vf_bar2_reg_addr_byte0 == 24'd4640
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_vf_bar3_reg_addr_byte0 == 24'd4644
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_vf_bar4_reg_addr_byte0 == 24'd4648
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_vf_bar5_reg_addr_byte0 == 24'd4652
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_vf_device_id_reg_addr_byte2 == 24'd8393230
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_cap_vf_device_id_reg_addr_byte3 == 24'd8393231
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_initial_vfs_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_initial_vfs_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_sup_page_size == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_vf_bar0_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_vf_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_vf_bar0_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_vf_bar0_type == PF1_SRIOV_VF_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_vf_bar1_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_vf_bar1_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_vf_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_vf_bar1_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_vf_bar1_type == PF1_SRIOV_VF_BAR1_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_vf_bar2_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_vf_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_vf_bar2_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_vf_bar2_type == PF1_SRIOV_VF_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_vf_bar3_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_vf_bar3_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_vf_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_vf_bar3_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_vf_bar3_type == PF1_SRIOV_VF_BAR3_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_vf_bar4_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_vf_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_vf_bar4_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_vf_bar4_type == PF1_SRIOV_VF_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_vf_bar5_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_vf_bar5_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_vf_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_vf_bar5_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_vf_bar5_type == PF1_SRIOV_VF_BAR5_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_vf_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_vf_offset_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_vf_offset_position_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_sriov_vf_stride_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_subclass_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_subsys_dev_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_subsys_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_tph_cap_tph_ext_cap_hdr_reg_addr_byte2 == 24'd8393270
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_tph_cap_tph_ext_cap_hdr_reg_addr_byte3 == 24'd8393271
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_tph_cap_tph_req_cap_reg_addr_byte0 == 24'd8393272
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_tph_cap_tph_req_cap_reg_addr_byte1 == 24'd8393273
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_tph_cap_tph_req_cap_reg_addr_byte2 == 24'd8393274
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_tph_cap_tph_req_cap_reg_addr_byte3 == 24'd8393275
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte0 == 24'd10490424
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte1 == 24'd10490425
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte2 == 24'd10490426
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte3 == 24'd10490427
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_tph_req_cap_int_vec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_tph_req_cap_int_vec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_tph_req_cap_reg_rsvdp_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_tph_req_cap_reg_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_tph_req_cap_reg_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_tph_req_cap_reg_vfcomm_cs2_rsvdp_11_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_tph_req_cap_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_tph_req_cap_reg_vfcomm_cs2_rsvdp_3_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_tph_req_cap_st_table_loc_0 == PF1_NOT_IN_TPH_STRUCT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_tph_req_cap_st_table_loc_0_vfcomm_cs2 == PF1_NOT_IN_TPH_STRUCT_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_tph_req_cap_st_table_loc_1 == PF1_NOT_IN_MSIX_TABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_tph_req_cap_st_table_loc_1_vfcomm_cs2 == PF1_NOT_IN_MSIX_TABLE_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_tph_req_cap_st_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_tph_req_cap_st_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_tph_req_cap_ver == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_tph_req_device_spec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_tph_req_device_spec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_tph_req_extended_tph == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_tph_req_extended_tph_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_tph_req_next_ptr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_tph_req_no_st_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_tph_req_no_st_mode_vfcomm_cs2 == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_bar0_mask_reg_addr_byte0 == 24'd2101264
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_bar0_mask_reg_addr_byte1 == 24'd2101265
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_bar0_mask_reg_addr_byte2 == 24'd2101266
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_bar0_mask_reg_addr_byte3 == 24'd2101267
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_bar0_reg_addr_byte0 == 24'd4112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_bar1_enable_reg_addr_byte0 == 24'd2101268
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_bar1_mask_reg_addr_byte0 == 24'd2101268
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_bar1_mask_reg_addr_byte1 == 24'd2101269
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_bar1_mask_reg_addr_byte2 == 24'd2101270
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_bar1_mask_reg_addr_byte3 == 24'd2101271
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_bar1_reg_addr_byte0 == 24'd4116
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_bar2_mask_reg_addr_byte0 == 24'd2101272
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_bar2_mask_reg_addr_byte1 == 24'd2101273
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_bar2_mask_reg_addr_byte2 == 24'd2101274
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_bar2_mask_reg_addr_byte3 == 24'd2101275
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_bar2_reg_addr_byte0 == 24'd4120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_bar3_enable_reg_addr_byte0 == 24'd2101276
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_bar3_mask_reg_addr_byte0 == 24'd2101276
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_bar3_mask_reg_addr_byte1 == 24'd2101277
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_bar3_mask_reg_addr_byte2 == 24'd2101278
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_bar3_mask_reg_addr_byte3 == 24'd2101279
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_bar3_reg_addr_byte0 == 24'd4124
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_bar4_mask_reg_addr_byte0 == 24'd2101280
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_bar4_mask_reg_addr_byte1 == 24'd2101281
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_bar4_mask_reg_addr_byte2 == 24'd2101282
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_bar4_mask_reg_addr_byte3 == 24'd2101283
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_bar4_reg_addr_byte0 == 24'd4128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_bar5_enable_reg_addr_byte0 == 24'd2101284
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_bar5_mask_reg_addr_byte0 == 24'd2101284
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_bar5_mask_reg_addr_byte1 == 24'd2101285
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_bar5_mask_reg_addr_byte2 == 24'd2101286
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_bar5_mask_reg_addr_byte3 == 24'd2101287
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_bar5_reg_addr_byte0 == 24'd4132
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_bist_header_type_latency_cache_line_size_reg_addr_byte2 == 24'd8392718
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_cardbus_cis_ptr_reg_addr_byte0 == 24'd8392744
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_cardbus_cis_ptr_reg_addr_byte1 == 24'd8392745
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_cardbus_cis_ptr_reg_addr_byte2 == 24'd8392746
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_cardbus_cis_ptr_reg_addr_byte3 == 24'd8392747
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_class_code_revision_id_addr_byte0 == 24'd8392712
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_class_code_revision_id_addr_byte1 == 24'd8392713
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_class_code_revision_id_addr_byte2 == 24'd8392714
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_class_code_revision_id_addr_byte3 == 24'd8392715
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_device_id_vendor_id_reg_addr_byte0 == 24'd8392704
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_device_id_vendor_id_reg_addr_byte1 == 24'd8392705
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_device_id_vendor_id_reg_addr_byte2 == 24'd8392706
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_device_id_vendor_id_reg_addr_byte3 == 24'd8392707
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_exp_rom_bar_mask_reg_addr_byte0 == 24'd2101296
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_exp_rom_bar_mask_reg_addr_byte1 == 24'd2101297
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_exp_rom_bar_mask_reg_addr_byte2 == 24'd2101298
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_exp_rom_bar_mask_reg_addr_byte3 == 24'd2101299
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_exp_rom_base_addr_reg_addr_byte0 == 24'd4144
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_max_latency_min_grant_interrupt_pin_interrupt_line_reg_addr_byte1 == 24'd8392765
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_pci_cap_ptr_reg_addr_byte0 == 24'd8392756
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte0 == 24'd8392748
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte1 == 24'd8392749
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte2 == 24'd8392750
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte3 == 24'd8392751
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_vf_bar0_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_vf_bar1_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_vf_bar2_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_vf_bar3_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_vf_bar4_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_vf_bar5_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_vsecras_cap_rasdp_ext_hdr_off_addr_byte2 == 24'd8393726
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_vsecras_cap_rasdp_ext_hdr_off_addr_byte3 == 24'd8393727
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_vsecras_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf1_vsecras_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_acs_cap_acs_at_block == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_acs_cap_acs_cap_hdr_reg_addr_byte2 == 24'd8397522
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_acs_cap_acs_cap_hdr_reg_addr_byte3 == 24'd8397523
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_acs_cap_acs_capalities_ctrl_reg_addr_byte0 == 24'd8397524
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_acs_cap_acs_capalities_ctrl_reg_addr_byte1 == 24'd8917
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_acs_cap_acs_direct_translated_p2p == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_acs_cap_acs_egress_ctrl_size == 8'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_acs_cap_acs_p2p_cpl_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_acs_cap_acs_p2p_egress_control == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_acs_cap_acs_p2p_req_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_acs_cap_acs_src_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_acs_cap_acs_usp_forwarding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_acs_cap_rsvdp_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_acs_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_acs_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_aer_cap_aer_ext_cap_hdr_off_addr_byte2 == 24'd8397058
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_aer_cap_aer_ext_cap_hdr_off_addr_byte3 == 24'd8397059
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_aer_cap_version == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_aer_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_ari_cap_ari_base_addr_byte2 == 24'd8397174
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_ari_cap_ari_base_addr_byte3 == 24'd8397175
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_ari_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_ari_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_ats_cap_ats_cap_hdr_reg_addr_byte2 == 24'd8397506
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_ats_cap_ats_cap_hdr_reg_addr_byte3 == 24'd8397507
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_ats_cap_ats_capabilities_ctrl_reg_addr_byte0 == 24'd8397508
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_ats_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_ats_capabilities_ctrl_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_ats_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_aux_curr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_bar0_mem_io == PF2_BAR0_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_bar0_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_bar0_type == PF2_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_bar1_mem_io == PF2_BAR1_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_bar1_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_bar1_type == PF2_BAR1_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_bar2_mem_io == PF2_BAR2_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_bar2_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_bar2_type == PF2_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_bar3_mem_io == PF2_BAR3_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_bar3_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_bar3_type == PF2_BAR3_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_bar4_mem_io == PF2_BAR4_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_bar4_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_bar4_type == PF2_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_bar5_mem_io == PF2_BAR5_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_bar5_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_bar5_type == PF2_BAR5_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_base_class_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_cap_id_nxt_ptr_reg_rsvdp_20 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_cap_pointer == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_cardbus_cis_pointer == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_con_status_reg_rsvdp_2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_con_status_reg_rsvdp_4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_d1_support == PF2_D1_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_d2_support == PF2_D2_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_10 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_11 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_12 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_13 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_14 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_15 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_16 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_17 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_18 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_19 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_20 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_21 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_22 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_23 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_24 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_25 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_26 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_27 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_28 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_29 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_30 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_31 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_32 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_33 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_34 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_35 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_36 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_37 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_38 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_39 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_40 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_41 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_42 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_43 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_44 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_45 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_46 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_47 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_48 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_49 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_50 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_51 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_52 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_53 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_54 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_55 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_56 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_57 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_58 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_59 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_6 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_60 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_61 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_62 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_63 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_64 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_65 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_7 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_8 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dbi_reserved_9 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_device_capabilities_reg_rsvdp_12 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_device_capabilities_reg_rsvdp_16 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_device_capabilities_reg_rsvdp_29 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_dsi == PF2_NOT_REQUIRED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_exp_rom_bar_mask_reg_rsvdp_1 == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_exp_rom_base_addr_reg_rsvdp_1 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_global_inval_spprtd == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_header_type == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_int_pin == PF2_NO_INT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_invalidate_q_depth == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_link_capabilities_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_link_control_link_status_reg_rsvdp_12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_link_control_link_status_reg_rsvdp_2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_link_control_link_status_reg_rsvdp_26 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_link_control_link_status_reg_rsvdp_9 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte1 == 24'd8396881
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte2 == 24'd8396882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte3 == 24'd8396883
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_msi_cap_pci_msi_cap_id_next_ctrl_reg_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_msix_cap_msix_pba_offset_reg_addr_byte0 == 24'd8396984
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_msix_cap_msix_pba_offset_reg_addr_byte1 == 24'd8396985
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_msix_cap_msix_pba_offset_reg_addr_byte2 == 24'd8396986
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_msix_cap_msix_pba_offset_reg_addr_byte3 == 24'd8396987
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_msix_cap_msix_table_offset_reg_addr_byte0 == 24'd8396980
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_msix_cap_msix_table_offset_reg_addr_byte1 == 24'd8396981
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_msix_cap_msix_table_offset_reg_addr_byte2 == 24'd8396982
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_msix_cap_msix_table_offset_reg_addr_byte3 == 24'd8396983
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte1 == 24'd8396977
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte2 == 24'd8396978
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte3 == 24'd8396979
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte2 == 24'd10494130
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte3 == 24'd10494131
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_multi_func == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_no_soft_rst == PF2_INTERNALLY_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_page_aligned_req == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pasid_cap_execute_permission_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pasid_cap_max_pasid_width == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pasid_cap_pasid_cap_cntrl_reg_addr_byte0 == 24'd8397560
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pasid_cap_pasid_cap_cntrl_reg_addr_byte1 == 24'd8397561
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pasid_cap_pasid_ext_hdr_reg_addr_byte2 == 24'd8397558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pasid_cap_pasid_ext_hdr_reg_addr_byte3 == 24'd8397559
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pasid_cap_privileged_mode_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pasid_cap_rsvdp_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pasid_cap_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pasid_cap_rsvpd_13 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pasid_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pasid_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_msi_64_bit_addr_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_msi_cap_next_offset == 8'd112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_msi_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_msi_ext_data_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_msi_ext_data_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_msi_multiple_msg_cap == PF2_MSI_VEC_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_msi_multiple_msg_en == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_msix_bir == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_msix_cap_id_next_ctrl_reg_rsvdp_27 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_msix_cap_next_offset == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_msix_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_msix_enable_vfcomm_cs2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_msix_function_mask == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_msix_function_mask_vfcomm_cs2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_msix_pba == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_msix_pba_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_msix_table_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_msix_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_msix_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_pvm_support == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_type0_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_type0_bar0_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_type0_bar1_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_type0_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_type0_bar1_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_type0_bar1_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_type0_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_type0_bar2_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_type0_bar3_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_type0_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_type0_bar3_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_type0_bar3_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_type0_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_type0_bar4_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_type0_bar5_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_type0_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_type0_bar5_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_type0_bar5_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_type0_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pci_type0_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_active_state_link_pm_control == PF2_ASPM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_active_state_link_pm_support == PF2_NO_ASPM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_aspm_opt_compliance == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_aux_power_pm_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_clock_power_man == PF2_REFCLK_REMOVE_NOT_OK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_common_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_device_capabilities_reg_addr_byte0 == 24'd8396916
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_device_capabilities_reg_addr_byte1 == 24'd8396917
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_device_capabilities_reg_addr_byte3 == 24'd8396919
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_device_control_device_status_addr_byte1 == 24'd8396921
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_dll_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_dll_active_rep_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_en_clk_power_man == PF2_CLKREQ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_en_no_snoop == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_enter_compliance == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_ep_l0s_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_ep_l1_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_ext_tag_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_ext_tag_supp == PF2_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_extended_synch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_flr_cap == PF2_NOT_CAPABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_hw_auto_speed_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvd == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_initiate_flr == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_l0s_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_l1_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_link_auto_bw_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_link_auto_bw_status == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_link_bw_man_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_link_bw_man_status == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_link_bw_not_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_link_capabilities_reg_addr_byte0 == 24'd8396924
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_link_capabilities_reg_addr_byte1 == 24'd8396925
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_link_capabilities_reg_addr_byte2 == 24'd8396926
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_link_capabilities_reg_addr_byte3 == 24'd8319
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_link_control2_link_status2_reg_addr_byte0 == 24'd12591264
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_link_control_link_status_reg_addr_byte0 == 24'd4202624
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_link_control_link_status_reg_addr_byte1 == 24'd12591233
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_link_control_link_status_reg_addr_byte3 == 24'd4202627
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_link_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_link_training == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_max_link_speed == PF2_MAX_2P5GTS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_max_link_width == PF2_X1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_max_payload_size == PF2_PAYLOAD_128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_max_read_req_size == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_nego_link_width == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_next_ptr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte1 == 24'd8396913
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte3 == 24'd8396915
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_phantom_func_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_phantom_func_support == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_port_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_rcb == PF2_RCB_64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_retrain_link == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_role_based_err_report == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_sel_deemphasis == PF2_MINUS_6DB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_slot_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_surprise_down_err_rep_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_target_link_speed == PF2_TRGT_GEN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_cap_tx_margin == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_int_msg_num == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pcie_slot_imp == PF2_NOT_IMPLEMENTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pf0_ari_device_number == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pf0_dbi_ro_wr_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pf0_default_target == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pf0_disable_auto_ltr_clr_msg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pf0_mask_ur_ca_4_trgt1 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pf0_misc_control_1_off_rsvdp_6 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pf0_port_logic_misc_control_1_off_addr_byte0 == 24'd2236
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pf0_simplified_replay_timer == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pf0_tlp_bypass_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pm_cap_cap_id_nxt_ptr_reg_addr_byte1 == 24'd8396865
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pm_cap_cap_id_nxt_ptr_reg_addr_byte2 == 24'd8396866
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pm_cap_cap_id_nxt_ptr_reg_addr_byte3 == 24'd8396867
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pm_cap_con_status_reg_addr_byte0 == 24'd8396868
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pm_next_pointer == 8'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pm_spec_ver == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pme_clk == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_pme_support == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_power_state == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_program_interface == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte2 == 24'd8397534
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte3 == 24'd8397535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_prs_ext_cap_prs_req_capacity_reg_addr_byte0 == 24'd8397540
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_prs_ext_cap_prs_req_capacity_reg_addr_byte1 == 24'd8397541
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_prs_ext_cap_prs_req_capacity_reg_addr_byte2 == 24'd8397542
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_prs_ext_cap_prs_req_capacity_reg_addr_byte3 == 24'd8397543
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_prs_ext_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_prs_ext_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_prs_outstanding_capacity == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_ras_des_cap_event_counter_ctrl_reg_addr_byte0 == 24'd8964
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_ras_des_cap_event_counter_ctrl_reg_g5_addr_byte3 == 24'd8397575
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_ras_des_cap_event_counter_ctrl_reg_g6_addr_byte3 == 24'd8397575
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_ras_des_cap_event_counter_ctrl_reg_g7_addr_byte3 == 24'd8397575
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_ras_des_cap_force_detect_lane == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_ras_des_cap_force_detect_lane_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_ras_des_cap_ras_des_hdr_reg_addr_byte2 == 24'd8397566
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_ras_des_cap_ras_des_hdr_reg_addr_byte3 == 24'd8397567
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_ras_des_cap_sd_control1_reg_addr_byte0 == 24'd8397724
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_ras_des_cap_sd_control1_reg_addr_byte1 == 24'd8397725
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_ras_des_cap_sd_control1_reg_addr_byte2 == 24'd8397726
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_ras_des_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_ras_des_event_counter_en == 8'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_ras_des_event_counter_event_select_g5 == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_ras_des_event_counter_event_select_g6 == 8'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_ras_des_event_counter_event_select_g7 == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_ras_des_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_10_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_11_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_12_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_13_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_14_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_15_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_16_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_17_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_18_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_19_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_20_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_21_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_22_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_23_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_24_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_25_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_26_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_27_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_28_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_29_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_30_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_31_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_32_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_33_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_34_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_35_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_36_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_37_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_38_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_39_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_40_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_41_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_42_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_43_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_44_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_45_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_46_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_47_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_48_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_49_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_50_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_51_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_52_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_53_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_54_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_55_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_56_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_57_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_58_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_59_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_60_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_61_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_62_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_63_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_64_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_65_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_7_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_8_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_reserved_9_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_revision_id == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_rom_bar_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_rom_bar_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_shadow_sriov_vf_stride_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sn_cap_ser_num_reg_dw_1_addr_byte0 == 24'd8397160
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sn_cap_ser_num_reg_dw_1_addr_byte1 == 24'd8397161
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sn_cap_ser_num_reg_dw_1_addr_byte2 == 24'd8397162
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sn_cap_ser_num_reg_dw_1_addr_byte3 == 24'd8397163
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sn_cap_ser_num_reg_dw_2_addr_byte0 == 24'd8397164
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sn_cap_ser_num_reg_dw_2_addr_byte1 == 24'd8397165
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sn_cap_ser_num_reg_dw_2_addr_byte2 == 24'd8397166
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sn_cap_ser_num_reg_dw_2_addr_byte3 == 24'd8397167
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sn_cap_sn_base_addr_byte2 == 24'd8397158
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sn_cap_sn_base_addr_byte3 == 24'd8397159
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sn_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sn_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sn_ser_num_reg_1_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sn_ser_num_reg_2_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_shadow_sriov_initial_vfs_addr_byte0 == 24'd10494464
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_shadow_sriov_initial_vfs_addr_byte1 == 24'd10494465
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_shadow_sriov_vf_offset_position_addr_byte0 == 24'd10494472
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_shadow_sriov_vf_offset_position_addr_byte1 == 24'd10494473
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_shadow_sriov_vf_offset_position_addr_byte2 == 24'd10494474
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_shadow_sriov_vf_offset_position_addr_byte3 == 24'd10494475
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_shadow_vf_bar0_reg_addr_byte0 == 24'd2105880
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_shadow_vf_bar0_reg_addr_byte1 == 24'd2105881
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_shadow_vf_bar0_reg_addr_byte2 == 24'd2105882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_shadow_vf_bar0_reg_addr_byte3 == 24'd2105883
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_shadow_vf_bar1_reg_addr_byte0 == 24'd2105884
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_shadow_vf_bar1_reg_addr_byte1 == 24'd2105885
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_shadow_vf_bar1_reg_addr_byte2 == 24'd2105886
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_shadow_vf_bar1_reg_addr_byte3 == 24'd2105887
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_shadow_vf_bar2_reg_addr_byte0 == 24'd2105888
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_shadow_vf_bar2_reg_addr_byte1 == 24'd2105889
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_shadow_vf_bar2_reg_addr_byte2 == 24'd2105890
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_shadow_vf_bar2_reg_addr_byte3 == 24'd2105891
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_shadow_vf_bar3_reg_addr_byte0 == 24'd2105892
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_shadow_vf_bar3_reg_addr_byte1 == 24'd2105893
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_shadow_vf_bar3_reg_addr_byte2 == 24'd2105894
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_shadow_vf_bar3_reg_addr_byte3 == 24'd2105895
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_shadow_vf_bar4_reg_addr_byte0 == 24'd2105896
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_shadow_vf_bar4_reg_addr_byte1 == 24'd2105897
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_shadow_vf_bar4_reg_addr_byte2 == 24'd2105898
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_shadow_vf_bar4_reg_addr_byte3 == 24'd2105899
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_shadow_vf_bar5_reg_addr_byte0 == 24'd2105900
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_shadow_vf_bar5_reg_addr_byte1 == 24'd2105901
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_shadow_vf_bar5_reg_addr_byte2 == 24'd2105902
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_shadow_vf_bar5_reg_addr_byte3 == 24'd2105903
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_sriov_bar1_enable_reg_addr_byte0 == 24'd2105884
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_sriov_bar3_enable_reg_addr_byte0 == 24'd2105892
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_sriov_bar5_enable_reg_addr_byte0 == 24'd2105900
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_sriov_base_reg_addr_byte2 == 24'd8397302
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_sriov_base_reg_addr_byte3 == 24'd8397303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_sriov_initial_vfs_addr_byte0 == 24'd8397312
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_sriov_initial_vfs_addr_byte1 == 24'd8397313
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_sriov_vf_offset_position_addr_byte0 == 24'd8397320
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_sriov_vf_offset_position_addr_byte1 == 24'd8397321
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_sriov_vf_offset_position_addr_byte2 == 24'd8397322
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_sriov_vf_offset_position_addr_byte3 == 24'd8397323
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_sup_page_sizes_reg_addr_byte0 == 24'd8397328
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_sup_page_sizes_reg_addr_byte1 == 24'd8397329
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_sup_page_sizes_reg_addr_byte2 == 24'd8397330
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_sup_page_sizes_reg_addr_byte3 == 24'd8397331
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_vf_bar0_reg_addr_byte0 == 24'd8728
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_vf_bar1_reg_addr_byte0 == 24'd8732
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_vf_bar2_reg_addr_byte0 == 24'd8736
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_vf_bar3_reg_addr_byte0 == 24'd8740
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_vf_bar4_reg_addr_byte0 == 24'd8744
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_vf_bar5_reg_addr_byte0 == 24'd8748
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_vf_device_id_reg_addr_byte2 == 24'd8397326
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_cap_vf_device_id_reg_addr_byte3 == 24'd8397327
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_initial_vfs_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_initial_vfs_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_sup_page_size == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_vf_bar0_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_vf_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_vf_bar0_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_vf_bar0_type == PF2_SRIOV_VF_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_vf_bar1_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_vf_bar1_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_vf_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_vf_bar1_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_vf_bar1_type == PF2_SRIOV_VF_BAR1_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_vf_bar2_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_vf_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_vf_bar2_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_vf_bar2_type == PF2_SRIOV_VF_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_vf_bar3_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_vf_bar3_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_vf_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_vf_bar3_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_vf_bar3_type == PF2_SRIOV_VF_BAR3_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_vf_bar4_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_vf_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_vf_bar4_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_vf_bar4_type == PF2_SRIOV_VF_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_vf_bar5_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_vf_bar5_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_vf_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_vf_bar5_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_vf_bar5_type == PF2_SRIOV_VF_BAR5_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_vf_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_vf_offset_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_vf_offset_position_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_sriov_vf_stride_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_subclass_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_subsys_dev_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_subsys_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_tph_cap_tph_ext_cap_hdr_reg_addr_byte2 == 24'd8397366
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_tph_cap_tph_ext_cap_hdr_reg_addr_byte3 == 24'd8397367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_tph_cap_tph_req_cap_reg_addr_byte0 == 24'd8397368
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_tph_cap_tph_req_cap_reg_addr_byte1 == 24'd8397369
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_tph_cap_tph_req_cap_reg_addr_byte2 == 24'd8397370
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_tph_cap_tph_req_cap_reg_addr_byte3 == 24'd8397371
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte0 == 24'd10494520
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte1 == 24'd10494521
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte2 == 24'd10494522
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte3 == 24'd10494523
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_tph_req_cap_int_vec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_tph_req_cap_int_vec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_tph_req_cap_reg_rsvdp_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_tph_req_cap_reg_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_tph_req_cap_reg_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_tph_req_cap_reg_vfcomm_cs2_rsvdp_11_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_tph_req_cap_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_tph_req_cap_reg_vfcomm_cs2_rsvdp_3_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_tph_req_cap_st_table_loc_0 == PF2_NOT_IN_TPH_STRUCT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_tph_req_cap_st_table_loc_0_vfcomm_cs2 == PF2_NOT_IN_TPH_STRUCT_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_tph_req_cap_st_table_loc_1 == PF2_NOT_IN_MSIX_TABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_tph_req_cap_st_table_loc_1_vfcomm_cs2 == PF2_NOT_IN_MSIX_TABLE_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_tph_req_cap_st_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_tph_req_cap_st_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_tph_req_cap_ver == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_tph_req_device_spec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_tph_req_device_spec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_tph_req_extended_tph == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_tph_req_extended_tph_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_tph_req_next_ptr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_tph_req_no_st_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_tph_req_no_st_mode_vfcomm_cs2 == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_bar0_mask_reg_addr_byte0 == 24'd2105360
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_bar0_mask_reg_addr_byte1 == 24'd2105361
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_bar0_mask_reg_addr_byte2 == 24'd2105362
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_bar0_mask_reg_addr_byte3 == 24'd2105363
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_bar0_reg_addr_byte0 == 24'd8208
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_bar1_enable_reg_addr_byte0 == 24'd2105364
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_bar1_mask_reg_addr_byte0 == 24'd2105364
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_bar1_mask_reg_addr_byte1 == 24'd2105365
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_bar1_mask_reg_addr_byte2 == 24'd2105366
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_bar1_mask_reg_addr_byte3 == 24'd2105367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_bar1_reg_addr_byte0 == 24'd8212
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_bar2_mask_reg_addr_byte0 == 24'd2105368
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_bar2_mask_reg_addr_byte1 == 24'd2105369
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_bar2_mask_reg_addr_byte2 == 24'd2105370
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_bar2_mask_reg_addr_byte3 == 24'd2105371
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_bar2_reg_addr_byte0 == 24'd8216
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_bar3_enable_reg_addr_byte0 == 24'd2105372
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_bar3_mask_reg_addr_byte0 == 24'd2105372
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_bar3_mask_reg_addr_byte1 == 24'd2105373
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_bar3_mask_reg_addr_byte2 == 24'd2105374
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_bar3_mask_reg_addr_byte3 == 24'd2105375
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_bar3_reg_addr_byte0 == 24'd8220
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_bar4_mask_reg_addr_byte0 == 24'd2105376
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_bar4_mask_reg_addr_byte1 == 24'd2105377
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_bar4_mask_reg_addr_byte2 == 24'd2105378
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_bar4_mask_reg_addr_byte3 == 24'd2105379
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_bar4_reg_addr_byte0 == 24'd8224
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_bar5_enable_reg_addr_byte0 == 24'd2105380
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_bar5_mask_reg_addr_byte0 == 24'd2105380
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_bar5_mask_reg_addr_byte1 == 24'd2105381
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_bar5_mask_reg_addr_byte2 == 24'd2105382
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_bar5_mask_reg_addr_byte3 == 24'd2105383
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_bar5_reg_addr_byte0 == 24'd8228
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_bist_header_type_latency_cache_line_size_reg_addr_byte2 == 24'd8396814
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_cardbus_cis_ptr_reg_addr_byte0 == 24'd8396840
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_cardbus_cis_ptr_reg_addr_byte1 == 24'd8396841
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_cardbus_cis_ptr_reg_addr_byte2 == 24'd8396842
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_cardbus_cis_ptr_reg_addr_byte3 == 24'd8396843
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_class_code_revision_id_addr_byte0 == 24'd8396808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_class_code_revision_id_addr_byte1 == 24'd8396809
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_class_code_revision_id_addr_byte2 == 24'd8396810
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_class_code_revision_id_addr_byte3 == 24'd8396811
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_device_id_vendor_id_reg_addr_byte0 == 24'd8396800
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_device_id_vendor_id_reg_addr_byte1 == 24'd8396801
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_device_id_vendor_id_reg_addr_byte2 == 24'd8396802
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_device_id_vendor_id_reg_addr_byte3 == 24'd8396803
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_exp_rom_bar_mask_reg_addr_byte0 == 24'd2105392
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_exp_rom_bar_mask_reg_addr_byte1 == 24'd2105393
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_exp_rom_bar_mask_reg_addr_byte2 == 24'd2105394
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_exp_rom_bar_mask_reg_addr_byte3 == 24'd2105395
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_exp_rom_base_addr_reg_addr_byte0 == 24'd8240
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_max_latency_min_grant_interrupt_pin_interrupt_line_reg_addr_byte1 == 24'd8396861
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_pci_cap_ptr_reg_addr_byte0 == 24'd8396852
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte0 == 24'd8396844
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte1 == 24'd8396845
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte2 == 24'd8396846
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte3 == 24'd8396847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_vf_bar0_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_vf_bar1_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_vf_bar2_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_vf_bar3_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_vf_bar4_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_vf_bar5_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_vsecras_cap_rasdp_ext_hdr_off_addr_byte2 == 24'd8397822
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_vsecras_cap_rasdp_ext_hdr_off_addr_byte3 == 24'd8397823
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_vsecras_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf2_vsecras_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_acs_cap_acs_at_block == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_acs_cap_acs_cap_hdr_reg_addr_byte2 == 24'd8401618
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_acs_cap_acs_cap_hdr_reg_addr_byte3 == 24'd8401619
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_acs_cap_acs_capalities_ctrl_reg_addr_byte0 == 24'd8401620
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_acs_cap_acs_capalities_ctrl_reg_addr_byte1 == 24'd13013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_acs_cap_acs_direct_translated_p2p == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_acs_cap_acs_egress_ctrl_size == 8'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_acs_cap_acs_p2p_cpl_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_acs_cap_acs_p2p_egress_control == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_acs_cap_acs_p2p_req_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_acs_cap_acs_src_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_acs_cap_acs_usp_forwarding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_acs_cap_rsvdp_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_acs_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_acs_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_aer_cap_aer_ext_cap_hdr_off_addr_byte2 == 24'd8401154
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_aer_cap_aer_ext_cap_hdr_off_addr_byte3 == 24'd8401155
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_aer_cap_version == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_aer_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_ari_cap_ari_base_addr_byte2 == 24'd8401270
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_ari_cap_ari_base_addr_byte3 == 24'd8401271
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_ari_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_ari_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_ats_cap_ats_cap_hdr_reg_addr_byte2 == 24'd8401602
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_ats_cap_ats_cap_hdr_reg_addr_byte3 == 24'd8401603
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_ats_cap_ats_capabilities_ctrl_reg_addr_byte0 == 24'd8401604
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_ats_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_ats_capabilities_ctrl_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_ats_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_aux_curr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_bar0_mem_io == PF3_BAR0_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_bar0_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_bar0_type == PF3_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_bar1_mem_io == PF3_BAR1_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_bar1_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_bar1_type == PF3_BAR1_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_bar2_mem_io == PF3_BAR2_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_bar2_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_bar2_type == PF3_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_bar3_mem_io == PF3_BAR3_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_bar3_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_bar3_type == PF3_BAR3_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_bar4_mem_io == PF3_BAR4_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_bar4_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_bar4_type == PF3_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_bar5_mem_io == PF3_BAR5_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_bar5_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_bar5_type == PF3_BAR5_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_base_class_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_cap_id_nxt_ptr_reg_rsvdp_20 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_cap_pointer == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_cardbus_cis_pointer == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_con_status_reg_rsvdp_2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_con_status_reg_rsvdp_4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_d1_support == PF3_D1_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_d2_support == PF3_D2_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_10 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_11 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_12 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_13 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_14 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_15 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_16 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_17 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_18 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_19 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_20 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_21 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_22 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_23 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_24 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_25 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_26 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_27 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_28 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_29 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_30 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_31 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_32 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_33 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_34 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_35 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_36 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_37 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_38 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_39 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_40 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_41 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_42 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_43 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_44 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_45 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_46 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_47 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_48 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_49 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_50 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_51 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_52 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_53 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_54 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_55 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_56 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_57 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_58 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_59 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_6 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_60 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_61 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_62 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_63 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_64 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_65 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_7 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_8 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dbi_reserved_9 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_device_capabilities_reg_rsvdp_12 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_device_capabilities_reg_rsvdp_16 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_device_capabilities_reg_rsvdp_29 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_dsi == PF3_NOT_REQUIRED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_exp_rom_bar_mask_reg_rsvdp_1 == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_exp_rom_base_addr_reg_rsvdp_1 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_global_inval_spprtd == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_header_type == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_int_pin == PF3_NO_INT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_invalidate_q_depth == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_link_capabilities_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_link_control_link_status_reg_rsvdp_12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_link_control_link_status_reg_rsvdp_2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_link_control_link_status_reg_rsvdp_26 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_link_control_link_status_reg_rsvdp_9 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte1 == 24'd8400977
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte2 == 24'd8400978
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte3 == 24'd8400979
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_msi_cap_pci_msi_cap_id_next_ctrl_reg_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_msix_cap_msix_pba_offset_reg_addr_byte0 == 24'd8401080
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_msix_cap_msix_pba_offset_reg_addr_byte1 == 24'd8401081
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_msix_cap_msix_pba_offset_reg_addr_byte2 == 24'd8401082
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_msix_cap_msix_pba_offset_reg_addr_byte3 == 24'd8401083
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_msix_cap_msix_table_offset_reg_addr_byte0 == 24'd8401076
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_msix_cap_msix_table_offset_reg_addr_byte1 == 24'd8401077
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_msix_cap_msix_table_offset_reg_addr_byte2 == 24'd8401078
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_msix_cap_msix_table_offset_reg_addr_byte3 == 24'd8401079
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte1 == 24'd8401073
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte2 == 24'd8401074
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte3 == 24'd8401075
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte2 == 24'd10498226
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte3 == 24'd10498227
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_multi_func == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_no_soft_rst == PF3_INTERNALLY_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_page_aligned_req == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pasid_cap_execute_permission_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pasid_cap_max_pasid_width == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pasid_cap_pasid_cap_cntrl_reg_addr_byte0 == 24'd8401656
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pasid_cap_pasid_cap_cntrl_reg_addr_byte1 == 24'd8401657
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pasid_cap_pasid_ext_hdr_reg_addr_byte2 == 24'd8401654
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pasid_cap_pasid_ext_hdr_reg_addr_byte3 == 24'd8401655
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pasid_cap_privileged_mode_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pasid_cap_rsvdp_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pasid_cap_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pasid_cap_rsvpd_13 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pasid_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pasid_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_msi_64_bit_addr_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_msi_cap_next_offset == 8'd112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_msi_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_msi_ext_data_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_msi_ext_data_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_msi_multiple_msg_cap == PF3_MSI_VEC_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_msi_multiple_msg_en == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_msix_bir == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_msix_cap_id_next_ctrl_reg_rsvdp_27 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_msix_cap_next_offset == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_msix_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_msix_enable_vfcomm_cs2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_msix_function_mask == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_msix_function_mask_vfcomm_cs2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_msix_pba == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_msix_pba_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_msix_table_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_msix_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_msix_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_pvm_support == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_type0_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_type0_bar0_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_type0_bar1_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_type0_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_type0_bar1_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_type0_bar1_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_type0_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_type0_bar2_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_type0_bar3_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_type0_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_type0_bar3_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_type0_bar3_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_type0_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_type0_bar4_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_type0_bar5_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_type0_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_type0_bar5_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_type0_bar5_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_type0_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pci_type0_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_active_state_link_pm_control == PF3_ASPM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_active_state_link_pm_support == PF3_NO_ASPM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_aspm_opt_compliance == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_aux_power_pm_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_clock_power_man == PF3_REFCLK_REMOVE_NOT_OK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_common_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_device_capabilities_reg_addr_byte0 == 24'd8401012
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_device_capabilities_reg_addr_byte1 == 24'd8401013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_device_capabilities_reg_addr_byte3 == 24'd8401015
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_device_control_device_status_addr_byte1 == 24'd8401017
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_dll_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_dll_active_rep_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_en_clk_power_man == PF3_CLKREQ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_en_no_snoop == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_enter_compliance == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_ep_l0s_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_ep_l1_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_ext_tag_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_ext_tag_supp == PF3_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_extended_synch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_flr_cap == PF3_NOT_CAPABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_hw_auto_speed_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvd == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_initiate_flr == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_l0s_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_l1_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_link_auto_bw_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_link_auto_bw_status == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_link_bw_man_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_link_bw_man_status == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_link_bw_not_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_link_capabilities_reg_addr_byte0 == 24'd8401020
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_link_capabilities_reg_addr_byte1 == 24'd8401021
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_link_capabilities_reg_addr_byte2 == 24'd8401022
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_link_capabilities_reg_addr_byte3 == 24'd12415
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_link_control2_link_status2_reg_addr_byte0 == 24'd12595360
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_link_control_link_status_reg_addr_byte0 == 24'd4206720
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_link_control_link_status_reg_addr_byte1 == 24'd12595329
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_link_control_link_status_reg_addr_byte3 == 24'd4206723
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_link_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_link_training == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_max_link_speed == PF3_MAX_2P5GTS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_max_link_width == PF3_X1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_max_payload_size == PF3_PAYLOAD_128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_max_read_req_size == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_nego_link_width == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_next_ptr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte1 == 24'd8401009
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte3 == 24'd8401011
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_phantom_func_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_phantom_func_support == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_port_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_rcb == PF3_RCB_64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_retrain_link == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_role_based_err_report == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_sel_deemphasis == PF3_MINUS_6DB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_slot_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_surprise_down_err_rep_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_target_link_speed == PF3_TRGT_GEN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_cap_tx_margin == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_int_msg_num == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pcie_slot_imp == PF3_NOT_IMPLEMENTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pf0_ari_device_number == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pf0_dbi_ro_wr_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pf0_default_target == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pf0_disable_auto_ltr_clr_msg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pf0_mask_ur_ca_4_trgt1 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pf0_misc_control_1_off_rsvdp_6 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pf0_port_logic_misc_control_1_off_addr_byte0 == 24'd2236
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pf0_simplified_replay_timer == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pf0_tlp_bypass_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pm_cap_cap_id_nxt_ptr_reg_addr_byte1 == 24'd8400961
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pm_cap_cap_id_nxt_ptr_reg_addr_byte2 == 24'd8400962
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pm_cap_cap_id_nxt_ptr_reg_addr_byte3 == 24'd8400963
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pm_cap_con_status_reg_addr_byte0 == 24'd8400964
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pm_next_pointer == 8'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pm_spec_ver == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pme_clk == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_pme_support == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_power_state == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_program_interface == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte2 == 24'd8401630
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte3 == 24'd8401631
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_prs_ext_cap_prs_req_capacity_reg_addr_byte0 == 24'd8401636
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_prs_ext_cap_prs_req_capacity_reg_addr_byte1 == 24'd8401637
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_prs_ext_cap_prs_req_capacity_reg_addr_byte2 == 24'd8401638
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_prs_ext_cap_prs_req_capacity_reg_addr_byte3 == 24'd8401639
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_prs_ext_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_prs_ext_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_prs_outstanding_capacity == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_ras_des_cap_event_counter_ctrl_reg_addr_byte0 == 24'd13060
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_ras_des_cap_event_counter_ctrl_reg_g5_addr_byte3 == 24'd8401671
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_ras_des_cap_event_counter_ctrl_reg_g6_addr_byte3 == 24'd8401671
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_ras_des_cap_event_counter_ctrl_reg_g7_addr_byte3 == 24'd8401671
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_ras_des_cap_force_detect_lane == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_ras_des_cap_force_detect_lane_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_ras_des_cap_ras_des_hdr_reg_addr_byte2 == 24'd8401662
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_ras_des_cap_ras_des_hdr_reg_addr_byte3 == 24'd8401663
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_ras_des_cap_sd_control1_reg_addr_byte0 == 24'd8401820
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_ras_des_cap_sd_control1_reg_addr_byte1 == 24'd8401821
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_ras_des_cap_sd_control1_reg_addr_byte2 == 24'd8401822
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_ras_des_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_ras_des_event_counter_en == 8'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_ras_des_event_counter_event_select_g5 == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_ras_des_event_counter_event_select_g6 == 8'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_ras_des_event_counter_event_select_g7 == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_ras_des_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_10_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_11_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_12_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_13_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_14_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_15_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_16_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_17_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_18_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_19_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_20_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_21_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_22_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_23_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_24_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_25_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_26_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_27_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_28_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_29_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_30_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_31_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_32_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_33_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_34_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_35_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_36_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_37_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_38_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_39_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_40_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_41_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_42_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_43_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_44_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_45_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_46_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_47_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_48_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_49_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_50_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_51_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_52_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_53_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_54_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_55_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_56_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_57_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_58_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_59_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_60_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_61_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_62_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_63_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_64_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_65_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_7_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_8_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_reserved_9_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_revision_id == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_rom_bar_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_rom_bar_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_shadow_sriov_vf_stride_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sn_cap_ser_num_reg_dw_1_addr_byte0 == 24'd8401256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sn_cap_ser_num_reg_dw_1_addr_byte1 == 24'd8401257
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sn_cap_ser_num_reg_dw_1_addr_byte2 == 24'd8401258
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sn_cap_ser_num_reg_dw_1_addr_byte3 == 24'd8401259
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sn_cap_ser_num_reg_dw_2_addr_byte0 == 24'd8401260
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sn_cap_ser_num_reg_dw_2_addr_byte1 == 24'd8401261
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sn_cap_ser_num_reg_dw_2_addr_byte2 == 24'd8401262
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sn_cap_ser_num_reg_dw_2_addr_byte3 == 24'd8401263
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sn_cap_sn_base_addr_byte2 == 24'd8401254
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sn_cap_sn_base_addr_byte3 == 24'd8401255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sn_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sn_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sn_ser_num_reg_1_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sn_ser_num_reg_2_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_shadow_sriov_initial_vfs_addr_byte0 == 24'd10498560
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_shadow_sriov_initial_vfs_addr_byte1 == 24'd10498561
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_shadow_sriov_vf_offset_position_addr_byte0 == 24'd10498568
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_shadow_sriov_vf_offset_position_addr_byte1 == 24'd10498569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_shadow_sriov_vf_offset_position_addr_byte2 == 24'd10498570
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_shadow_sriov_vf_offset_position_addr_byte3 == 24'd10498571
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_shadow_vf_bar0_reg_addr_byte0 == 24'd2109976
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_shadow_vf_bar0_reg_addr_byte1 == 24'd2109977
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_shadow_vf_bar0_reg_addr_byte2 == 24'd2109978
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_shadow_vf_bar0_reg_addr_byte3 == 24'd2109979
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_shadow_vf_bar1_reg_addr_byte0 == 24'd2109980
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_shadow_vf_bar1_reg_addr_byte1 == 24'd2109981
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_shadow_vf_bar1_reg_addr_byte2 == 24'd2109982
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_shadow_vf_bar1_reg_addr_byte3 == 24'd2109983
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_shadow_vf_bar2_reg_addr_byte0 == 24'd2109984
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_shadow_vf_bar2_reg_addr_byte1 == 24'd2109985
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_shadow_vf_bar2_reg_addr_byte2 == 24'd2109986
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_shadow_vf_bar2_reg_addr_byte3 == 24'd2109987
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_shadow_vf_bar3_reg_addr_byte0 == 24'd2109988
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_shadow_vf_bar3_reg_addr_byte1 == 24'd2109989
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_shadow_vf_bar3_reg_addr_byte2 == 24'd2109990
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_shadow_vf_bar3_reg_addr_byte3 == 24'd2109991
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_shadow_vf_bar4_reg_addr_byte0 == 24'd2109992
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_shadow_vf_bar4_reg_addr_byte1 == 24'd2109993
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_shadow_vf_bar4_reg_addr_byte2 == 24'd2109994
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_shadow_vf_bar4_reg_addr_byte3 == 24'd2109995
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_shadow_vf_bar5_reg_addr_byte0 == 24'd2109996
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_shadow_vf_bar5_reg_addr_byte1 == 24'd2109997
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_shadow_vf_bar5_reg_addr_byte2 == 24'd2109998
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_shadow_vf_bar5_reg_addr_byte3 == 24'd2109999
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_sriov_bar1_enable_reg_addr_byte0 == 24'd2109980
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_sriov_bar3_enable_reg_addr_byte0 == 24'd2109988
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_sriov_bar5_enable_reg_addr_byte0 == 24'd2109996
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_sriov_base_reg_addr_byte2 == 24'd8401398
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_sriov_base_reg_addr_byte3 == 24'd8401399
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_sriov_initial_vfs_addr_byte0 == 24'd8401408
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_sriov_initial_vfs_addr_byte1 == 24'd8401409
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_sriov_vf_offset_position_addr_byte0 == 24'd8401416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_sriov_vf_offset_position_addr_byte1 == 24'd8401417
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_sriov_vf_offset_position_addr_byte2 == 24'd8401418
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_sriov_vf_offset_position_addr_byte3 == 24'd8401419
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_sup_page_sizes_reg_addr_byte0 == 24'd8401424
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_sup_page_sizes_reg_addr_byte1 == 24'd8401425
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_sup_page_sizes_reg_addr_byte2 == 24'd8401426
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_sup_page_sizes_reg_addr_byte3 == 24'd8401427
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_vf_bar0_reg_addr_byte0 == 24'd12824
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_vf_bar1_reg_addr_byte0 == 24'd12828
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_vf_bar2_reg_addr_byte0 == 24'd12832
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_vf_bar3_reg_addr_byte0 == 24'd12836
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_vf_bar4_reg_addr_byte0 == 24'd12840
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_vf_bar5_reg_addr_byte0 == 24'd12844
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_vf_device_id_reg_addr_byte2 == 24'd8401422
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_cap_vf_device_id_reg_addr_byte3 == 24'd8401423
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_initial_vfs_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_initial_vfs_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_sup_page_size == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_vf_bar0_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_vf_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_vf_bar0_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_vf_bar0_type == PF3_SRIOV_VF_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_vf_bar1_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_vf_bar1_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_vf_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_vf_bar1_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_vf_bar1_type == PF3_SRIOV_VF_BAR1_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_vf_bar2_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_vf_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_vf_bar2_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_vf_bar2_type == PF3_SRIOV_VF_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_vf_bar3_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_vf_bar3_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_vf_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_vf_bar3_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_vf_bar3_type == PF3_SRIOV_VF_BAR3_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_vf_bar4_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_vf_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_vf_bar4_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_vf_bar4_type == PF3_SRIOV_VF_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_vf_bar5_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_vf_bar5_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_vf_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_vf_bar5_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_vf_bar5_type == PF3_SRIOV_VF_BAR5_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_vf_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_vf_offset_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_vf_offset_position_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_sriov_vf_stride_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_subclass_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_subsys_dev_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_subsys_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_tph_cap_tph_ext_cap_hdr_reg_addr_byte2 == 24'd8401462
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_tph_cap_tph_ext_cap_hdr_reg_addr_byte3 == 24'd8401463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_tph_cap_tph_req_cap_reg_addr_byte0 == 24'd8401464
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_tph_cap_tph_req_cap_reg_addr_byte1 == 24'd8401465
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_tph_cap_tph_req_cap_reg_addr_byte2 == 24'd8401466
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_tph_cap_tph_req_cap_reg_addr_byte3 == 24'd8401467
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte0 == 24'd10498616
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte1 == 24'd10498617
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte2 == 24'd10498618
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte3 == 24'd10498619
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_tph_req_cap_int_vec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_tph_req_cap_int_vec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_tph_req_cap_reg_rsvdp_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_tph_req_cap_reg_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_tph_req_cap_reg_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_tph_req_cap_reg_vfcomm_cs2_rsvdp_11_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_tph_req_cap_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_tph_req_cap_reg_vfcomm_cs2_rsvdp_3_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_tph_req_cap_st_table_loc_0 == PF3_NOT_IN_TPH_STRUCT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_tph_req_cap_st_table_loc_0_vfcomm_cs2 == PF3_NOT_IN_TPH_STRUCT_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_tph_req_cap_st_table_loc_1 == PF3_NOT_IN_MSIX_TABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_tph_req_cap_st_table_loc_1_vfcomm_cs2 == PF3_NOT_IN_MSIX_TABLE_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_tph_req_cap_st_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_tph_req_cap_st_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_tph_req_cap_ver == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_tph_req_device_spec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_tph_req_device_spec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_tph_req_extended_tph == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_tph_req_extended_tph_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_tph_req_next_ptr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_tph_req_no_st_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_tph_req_no_st_mode_vfcomm_cs2 == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_bar0_mask_reg_addr_byte0 == 24'd2109456
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_bar0_mask_reg_addr_byte1 == 24'd2109457
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_bar0_mask_reg_addr_byte2 == 24'd2109458
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_bar0_mask_reg_addr_byte3 == 24'd2109459
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_bar0_reg_addr_byte0 == 24'd12304
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_bar1_enable_reg_addr_byte0 == 24'd2109460
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_bar1_mask_reg_addr_byte0 == 24'd2109460
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_bar1_mask_reg_addr_byte1 == 24'd2109461
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_bar1_mask_reg_addr_byte2 == 24'd2109462
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_bar1_mask_reg_addr_byte3 == 24'd2109463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_bar1_reg_addr_byte0 == 24'd12308
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_bar2_mask_reg_addr_byte0 == 24'd2109464
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_bar2_mask_reg_addr_byte1 == 24'd2109465
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_bar2_mask_reg_addr_byte2 == 24'd2109466
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_bar2_mask_reg_addr_byte3 == 24'd2109467
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_bar2_reg_addr_byte0 == 24'd12312
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_bar3_enable_reg_addr_byte0 == 24'd2109468
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_bar3_mask_reg_addr_byte0 == 24'd2109468
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_bar3_mask_reg_addr_byte1 == 24'd2109469
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_bar3_mask_reg_addr_byte2 == 24'd2109470
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_bar3_mask_reg_addr_byte3 == 24'd2109471
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_bar3_reg_addr_byte0 == 24'd12316
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_bar4_mask_reg_addr_byte0 == 24'd2109472
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_bar4_mask_reg_addr_byte1 == 24'd2109473
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_bar4_mask_reg_addr_byte2 == 24'd2109474
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_bar4_mask_reg_addr_byte3 == 24'd2109475
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_bar4_reg_addr_byte0 == 24'd12320
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_bar5_enable_reg_addr_byte0 == 24'd2109476
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_bar5_mask_reg_addr_byte0 == 24'd2109476
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_bar5_mask_reg_addr_byte1 == 24'd2109477
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_bar5_mask_reg_addr_byte2 == 24'd2109478
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_bar5_mask_reg_addr_byte3 == 24'd2109479
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_bar5_reg_addr_byte0 == 24'd12324
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_bist_header_type_latency_cache_line_size_reg_addr_byte2 == 24'd8400910
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_cardbus_cis_ptr_reg_addr_byte0 == 24'd8400936
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_cardbus_cis_ptr_reg_addr_byte1 == 24'd8400937
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_cardbus_cis_ptr_reg_addr_byte2 == 24'd8400938
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_cardbus_cis_ptr_reg_addr_byte3 == 24'd8400939
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_class_code_revision_id_addr_byte0 == 24'd8400904
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_class_code_revision_id_addr_byte1 == 24'd8400905
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_class_code_revision_id_addr_byte2 == 24'd8400906
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_class_code_revision_id_addr_byte3 == 24'd8400907
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_device_id_vendor_id_reg_addr_byte0 == 24'd8400896
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_device_id_vendor_id_reg_addr_byte1 == 24'd8400897
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_device_id_vendor_id_reg_addr_byte2 == 24'd8400898
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_device_id_vendor_id_reg_addr_byte3 == 24'd8400899
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_exp_rom_bar_mask_reg_addr_byte0 == 24'd2109488
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_exp_rom_bar_mask_reg_addr_byte1 == 24'd2109489
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_exp_rom_bar_mask_reg_addr_byte2 == 24'd2109490
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_exp_rom_bar_mask_reg_addr_byte3 == 24'd2109491
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_exp_rom_base_addr_reg_addr_byte0 == 24'd12336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_max_latency_min_grant_interrupt_pin_interrupt_line_reg_addr_byte1 == 24'd8400957
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_pci_cap_ptr_reg_addr_byte0 == 24'd8400948
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte0 == 24'd8400940
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte1 == 24'd8400941
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte2 == 24'd8400942
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte3 == 24'd8400943
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_vf_bar0_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_vf_bar1_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_vf_bar2_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_vf_bar3_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_vf_bar4_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_vf_bar5_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_vsecras_cap_rasdp_ext_hdr_off_addr_byte2 == 24'd8401918
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_vsecras_cap_rasdp_ext_hdr_off_addr_byte3 == 24'd8401919
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_vsecras_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf3_vsecras_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_acs_cap_acs_at_block == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_acs_cap_acs_cap_hdr_reg_addr_byte2 == 24'd8405714
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_acs_cap_acs_cap_hdr_reg_addr_byte3 == 24'd8405715
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_acs_cap_acs_capalities_ctrl_reg_addr_byte0 == 24'd8405716
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_acs_cap_acs_capalities_ctrl_reg_addr_byte1 == 24'd17109
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_acs_cap_acs_direct_translated_p2p == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_acs_cap_acs_egress_ctrl_size == 8'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_acs_cap_acs_p2p_cpl_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_acs_cap_acs_p2p_egress_control == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_acs_cap_acs_p2p_req_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_acs_cap_acs_src_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_acs_cap_acs_usp_forwarding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_acs_cap_rsvdp_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_acs_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_acs_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_aer_cap_aer_ext_cap_hdr_off_addr_byte2 == 24'd8405250
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_aer_cap_aer_ext_cap_hdr_off_addr_byte3 == 24'd8405251
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_aer_cap_version == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_aer_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_ari_cap_ari_base_addr_byte2 == 24'd8405366
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_ari_cap_ari_base_addr_byte3 == 24'd8405367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_ari_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_ari_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_ats_cap_ats_cap_hdr_reg_addr_byte2 == 24'd8405698
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_ats_cap_ats_cap_hdr_reg_addr_byte3 == 24'd8405699
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_ats_cap_ats_capabilities_ctrl_reg_addr_byte0 == 24'd8405700
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_ats_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_ats_capabilities_ctrl_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_ats_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_aux_curr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_bar0_mem_io == PF4_BAR0_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_bar0_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_bar0_type == PF4_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_bar1_mem_io == PF4_BAR1_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_bar1_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_bar1_type == PF4_BAR1_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_bar2_mem_io == PF4_BAR2_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_bar2_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_bar2_type == PF4_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_bar3_mem_io == PF4_BAR3_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_bar3_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_bar3_type == PF4_BAR3_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_bar4_mem_io == PF4_BAR4_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_bar4_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_bar4_type == PF4_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_bar5_mem_io == PF4_BAR5_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_bar5_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_bar5_type == PF4_BAR5_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_base_class_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_cap_id_nxt_ptr_reg_rsvdp_20 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_cap_pointer == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_cardbus_cis_pointer == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_con_status_reg_rsvdp_2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_con_status_reg_rsvdp_4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_d1_support == PF4_D1_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_d2_support == PF4_D2_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_10 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_11 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_12 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_13 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_14 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_15 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_16 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_17 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_18 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_19 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_20 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_21 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_22 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_23 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_24 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_25 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_26 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_27 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_28 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_29 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_30 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_31 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_32 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_33 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_34 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_35 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_36 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_37 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_38 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_39 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_40 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_41 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_42 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_43 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_44 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_45 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_46 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_47 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_48 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_49 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_50 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_51 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_52 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_53 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_54 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_55 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_56 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_57 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_58 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_59 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_6 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_60 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_61 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_62 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_63 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_64 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_65 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_7 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_8 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dbi_reserved_9 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_device_capabilities_reg_rsvdp_12 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_device_capabilities_reg_rsvdp_16 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_device_capabilities_reg_rsvdp_29 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_dsi == PF4_NOT_REQUIRED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_exp_rom_bar_mask_reg_rsvdp_1 == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_exp_rom_base_addr_reg_rsvdp_1 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_global_inval_spprtd == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_header_type == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_int_pin == PF4_NO_INT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_invalidate_q_depth == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_link_capabilities_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_link_control_link_status_reg_rsvdp_12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_link_control_link_status_reg_rsvdp_2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_link_control_link_status_reg_rsvdp_26 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_link_control_link_status_reg_rsvdp_9 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte1 == 24'd8405073
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte2 == 24'd8405074
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte3 == 24'd8405075
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_msi_cap_pci_msi_cap_id_next_ctrl_reg_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_msix_cap_msix_pba_offset_reg_addr_byte0 == 24'd8405176
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_msix_cap_msix_pba_offset_reg_addr_byte1 == 24'd8405177
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_msix_cap_msix_pba_offset_reg_addr_byte2 == 24'd8405178
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_msix_cap_msix_pba_offset_reg_addr_byte3 == 24'd8405179
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_msix_cap_msix_table_offset_reg_addr_byte0 == 24'd8405172
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_msix_cap_msix_table_offset_reg_addr_byte1 == 24'd8405173
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_msix_cap_msix_table_offset_reg_addr_byte2 == 24'd8405174
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_msix_cap_msix_table_offset_reg_addr_byte3 == 24'd8405175
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte1 == 24'd8405169
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte2 == 24'd8405170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte3 == 24'd8405171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte2 == 24'd10502322
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte3 == 24'd10502323
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_multi_func == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_no_soft_rst == PF4_INTERNALLY_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_page_aligned_req == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pasid_cap_execute_permission_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pasid_cap_max_pasid_width == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pasid_cap_pasid_cap_cntrl_reg_addr_byte0 == 24'd8405752
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pasid_cap_pasid_cap_cntrl_reg_addr_byte1 == 24'd8405753
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pasid_cap_pasid_ext_hdr_reg_addr_byte2 == 24'd8405750
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pasid_cap_pasid_ext_hdr_reg_addr_byte3 == 24'd8405751
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pasid_cap_privileged_mode_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pasid_cap_rsvdp_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pasid_cap_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pasid_cap_rsvpd_13 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pasid_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pasid_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_msi_64_bit_addr_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_msi_cap_next_offset == 8'd112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_msi_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_msi_ext_data_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_msi_ext_data_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_msi_multiple_msg_cap == PF4_MSI_VEC_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_msi_multiple_msg_en == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_msix_bir == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_msix_cap_id_next_ctrl_reg_rsvdp_27 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_msix_cap_next_offset == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_msix_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_msix_enable_vfcomm_cs2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_msix_function_mask == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_msix_function_mask_vfcomm_cs2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_msix_pba == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_msix_pba_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_msix_table_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_msix_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_msix_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_pvm_support == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_type0_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_type0_bar0_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_type0_bar1_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_type0_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_type0_bar1_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_type0_bar1_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_type0_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_type0_bar2_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_type0_bar3_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_type0_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_type0_bar3_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_type0_bar3_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_type0_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_type0_bar4_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_type0_bar5_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_type0_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_type0_bar5_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_type0_bar5_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_type0_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pci_type0_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_active_state_link_pm_control == PF4_ASPM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_active_state_link_pm_support == PF4_NO_ASPM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_aspm_opt_compliance == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_aux_power_pm_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_clock_power_man == PF4_REFCLK_REMOVE_NOT_OK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_common_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_device_capabilities_reg_addr_byte0 == 24'd8405108
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_device_capabilities_reg_addr_byte1 == 24'd8405109
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_device_capabilities_reg_addr_byte3 == 24'd8405111
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_device_control_device_status_addr_byte1 == 24'd8405113
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_dll_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_dll_active_rep_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_en_clk_power_man == PF4_CLKREQ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_en_no_snoop == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_enter_compliance == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_ep_l0s_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_ep_l1_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_ext_tag_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_ext_tag_supp == PF4_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_extended_synch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_flr_cap == PF4_NOT_CAPABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_hw_auto_speed_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvd == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_initiate_flr == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_l0s_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_l1_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_link_auto_bw_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_link_auto_bw_status == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_link_bw_man_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_link_bw_man_status == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_link_bw_not_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_link_capabilities_reg_addr_byte0 == 24'd8405116
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_link_capabilities_reg_addr_byte1 == 24'd8405117
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_link_capabilities_reg_addr_byte2 == 24'd8405118
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_link_capabilities_reg_addr_byte3 == 24'd16511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_link_control2_link_status2_reg_addr_byte0 == 24'd12599456
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_link_control_link_status_reg_addr_byte0 == 24'd4210816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_link_control_link_status_reg_addr_byte1 == 24'd12599425
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_link_control_link_status_reg_addr_byte3 == 24'd4210819
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_link_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_link_training == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_max_link_speed == PF4_MAX_2P5GTS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_max_link_width == PF4_X1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_max_payload_size == PF4_PAYLOAD_128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_max_read_req_size == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_nego_link_width == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_next_ptr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte1 == 24'd8405105
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte3 == 24'd8405107
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_phantom_func_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_phantom_func_support == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_port_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_rcb == PF4_RCB_64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_retrain_link == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_role_based_err_report == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_sel_deemphasis == PF4_MINUS_6DB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_slot_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_surprise_down_err_rep_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_target_link_speed == PF4_TRGT_GEN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_cap_tx_margin == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_int_msg_num == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pcie_slot_imp == PF4_NOT_IMPLEMENTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pf0_ari_device_number == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pf0_dbi_ro_wr_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pf0_default_target == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pf0_disable_auto_ltr_clr_msg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pf0_mask_ur_ca_4_trgt1 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pf0_misc_control_1_off_rsvdp_6 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pf0_port_logic_misc_control_1_off_addr_byte0 == 24'd2236
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pf0_simplified_replay_timer == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pf0_tlp_bypass_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pm_cap_cap_id_nxt_ptr_reg_addr_byte1 == 24'd8405057
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pm_cap_cap_id_nxt_ptr_reg_addr_byte2 == 24'd8405058
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pm_cap_cap_id_nxt_ptr_reg_addr_byte3 == 24'd8405059
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pm_cap_con_status_reg_addr_byte0 == 24'd8405060
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pm_next_pointer == 8'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pm_spec_ver == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pme_clk == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_pme_support == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_power_state == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_program_interface == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte2 == 24'd8405726
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte3 == 24'd8405727
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_prs_ext_cap_prs_req_capacity_reg_addr_byte0 == 24'd8405732
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_prs_ext_cap_prs_req_capacity_reg_addr_byte1 == 24'd8405733
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_prs_ext_cap_prs_req_capacity_reg_addr_byte2 == 24'd8405734
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_prs_ext_cap_prs_req_capacity_reg_addr_byte3 == 24'd8405735
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_prs_ext_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_prs_ext_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_prs_outstanding_capacity == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_ras_des_cap_event_counter_ctrl_reg_addr_byte0 == 24'd17156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_ras_des_cap_event_counter_ctrl_reg_g5_addr_byte3 == 24'd8405767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_ras_des_cap_event_counter_ctrl_reg_g6_addr_byte3 == 24'd8405767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_ras_des_cap_event_counter_ctrl_reg_g7_addr_byte3 == 24'd8405767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_ras_des_cap_force_detect_lane == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_ras_des_cap_force_detect_lane_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_ras_des_cap_ras_des_hdr_reg_addr_byte2 == 24'd8405758
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_ras_des_cap_ras_des_hdr_reg_addr_byte3 == 24'd8405759
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_ras_des_cap_sd_control1_reg_addr_byte0 == 24'd8405916
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_ras_des_cap_sd_control1_reg_addr_byte1 == 24'd8405917
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_ras_des_cap_sd_control1_reg_addr_byte2 == 24'd8405918
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_ras_des_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_ras_des_event_counter_en == 8'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_ras_des_event_counter_event_select_g5 == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_ras_des_event_counter_event_select_g6 == 8'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_ras_des_event_counter_event_select_g7 == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_ras_des_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_10_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_11_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_12_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_13_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_14_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_15_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_16_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_17_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_18_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_19_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_20_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_21_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_22_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_23_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_24_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_25_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_26_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_27_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_28_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_29_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_30_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_31_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_32_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_33_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_34_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_35_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_36_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_37_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_38_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_39_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_40_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_41_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_42_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_43_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_44_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_45_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_46_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_47_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_48_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_49_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_50_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_51_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_52_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_53_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_54_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_55_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_56_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_57_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_58_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_59_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_60_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_61_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_62_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_63_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_64_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_65_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_7_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_8_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_reserved_9_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_revision_id == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_rom_bar_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_rom_bar_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_shadow_sriov_vf_stride_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sn_cap_ser_num_reg_dw_1_addr_byte0 == 24'd8405352
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sn_cap_ser_num_reg_dw_1_addr_byte1 == 24'd8405353
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sn_cap_ser_num_reg_dw_1_addr_byte2 == 24'd8405354
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sn_cap_ser_num_reg_dw_1_addr_byte3 == 24'd8405355
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sn_cap_ser_num_reg_dw_2_addr_byte0 == 24'd8405356
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sn_cap_ser_num_reg_dw_2_addr_byte1 == 24'd8405357
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sn_cap_ser_num_reg_dw_2_addr_byte2 == 24'd8405358
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sn_cap_ser_num_reg_dw_2_addr_byte3 == 24'd8405359
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sn_cap_sn_base_addr_byte2 == 24'd8405350
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sn_cap_sn_base_addr_byte3 == 24'd8405351
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sn_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sn_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sn_ser_num_reg_1_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sn_ser_num_reg_2_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_shadow_sriov_initial_vfs_addr_byte0 == 24'd10502656
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_shadow_sriov_initial_vfs_addr_byte1 == 24'd10502657
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_shadow_sriov_vf_offset_position_addr_byte0 == 24'd10502664
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_shadow_sriov_vf_offset_position_addr_byte1 == 24'd10502665
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_shadow_sriov_vf_offset_position_addr_byte2 == 24'd10502666
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_shadow_sriov_vf_offset_position_addr_byte3 == 24'd10502667
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_shadow_vf_bar0_reg_addr_byte0 == 24'd2114072
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_shadow_vf_bar0_reg_addr_byte1 == 24'd2114073
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_shadow_vf_bar0_reg_addr_byte2 == 24'd2114074
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_shadow_vf_bar0_reg_addr_byte3 == 24'd2114075
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_shadow_vf_bar1_reg_addr_byte0 == 24'd2114076
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_shadow_vf_bar1_reg_addr_byte1 == 24'd2114077
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_shadow_vf_bar1_reg_addr_byte2 == 24'd2114078
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_shadow_vf_bar1_reg_addr_byte3 == 24'd2114079
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_shadow_vf_bar2_reg_addr_byte0 == 24'd2114080
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_shadow_vf_bar2_reg_addr_byte1 == 24'd2114081
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_shadow_vf_bar2_reg_addr_byte2 == 24'd2114082
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_shadow_vf_bar2_reg_addr_byte3 == 24'd2114083
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_shadow_vf_bar3_reg_addr_byte0 == 24'd2114084
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_shadow_vf_bar3_reg_addr_byte1 == 24'd2114085
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_shadow_vf_bar3_reg_addr_byte2 == 24'd2114086
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_shadow_vf_bar3_reg_addr_byte3 == 24'd2114087
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_shadow_vf_bar4_reg_addr_byte0 == 24'd2114088
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_shadow_vf_bar4_reg_addr_byte1 == 24'd2114089
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_shadow_vf_bar4_reg_addr_byte2 == 24'd2114090
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_shadow_vf_bar4_reg_addr_byte3 == 24'd2114091
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_shadow_vf_bar5_reg_addr_byte0 == 24'd2114092
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_shadow_vf_bar5_reg_addr_byte1 == 24'd2114093
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_shadow_vf_bar5_reg_addr_byte2 == 24'd2114094
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_shadow_vf_bar5_reg_addr_byte3 == 24'd2114095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_sriov_bar1_enable_reg_addr_byte0 == 24'd2114076
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_sriov_bar3_enable_reg_addr_byte0 == 24'd2114084
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_sriov_bar5_enable_reg_addr_byte0 == 24'd2114092
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_sriov_base_reg_addr_byte2 == 24'd8405494
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_sriov_base_reg_addr_byte3 == 24'd8405495
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_sriov_initial_vfs_addr_byte0 == 24'd8405504
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_sriov_initial_vfs_addr_byte1 == 24'd8405505
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_sriov_vf_offset_position_addr_byte0 == 24'd8405512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_sriov_vf_offset_position_addr_byte1 == 24'd8405513
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_sriov_vf_offset_position_addr_byte2 == 24'd8405514
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_sriov_vf_offset_position_addr_byte3 == 24'd8405515
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_sup_page_sizes_reg_addr_byte0 == 24'd8405520
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_sup_page_sizes_reg_addr_byte1 == 24'd8405521
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_sup_page_sizes_reg_addr_byte2 == 24'd8405522
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_sup_page_sizes_reg_addr_byte3 == 24'd8405523
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_vf_bar0_reg_addr_byte0 == 24'd16920
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_vf_bar1_reg_addr_byte0 == 24'd16924
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_vf_bar2_reg_addr_byte0 == 24'd16928
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_vf_bar3_reg_addr_byte0 == 24'd16932
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_vf_bar4_reg_addr_byte0 == 24'd16936
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_vf_bar5_reg_addr_byte0 == 24'd16940
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_vf_device_id_reg_addr_byte2 == 24'd8405518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_cap_vf_device_id_reg_addr_byte3 == 24'd8405519
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_initial_vfs_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_initial_vfs_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_sup_page_size == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_vf_bar0_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_vf_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_vf_bar0_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_vf_bar0_type == PF4_SRIOV_VF_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_vf_bar1_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_vf_bar1_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_vf_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_vf_bar1_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_vf_bar1_type == PF4_SRIOV_VF_BAR1_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_vf_bar2_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_vf_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_vf_bar2_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_vf_bar2_type == PF4_SRIOV_VF_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_vf_bar3_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_vf_bar3_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_vf_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_vf_bar3_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_vf_bar3_type == PF4_SRIOV_VF_BAR3_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_vf_bar4_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_vf_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_vf_bar4_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_vf_bar4_type == PF4_SRIOV_VF_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_vf_bar5_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_vf_bar5_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_vf_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_vf_bar5_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_vf_bar5_type == PF4_SRIOV_VF_BAR5_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_vf_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_vf_offset_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_vf_offset_position_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_sriov_vf_stride_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_subclass_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_subsys_dev_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_subsys_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_tph_cap_tph_ext_cap_hdr_reg_addr_byte2 == 24'd8405558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_tph_cap_tph_ext_cap_hdr_reg_addr_byte3 == 24'd8405559
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_tph_cap_tph_req_cap_reg_addr_byte0 == 24'd8405560
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_tph_cap_tph_req_cap_reg_addr_byte1 == 24'd8405561
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_tph_cap_tph_req_cap_reg_addr_byte2 == 24'd8405562
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_tph_cap_tph_req_cap_reg_addr_byte3 == 24'd8405563
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte0 == 24'd10502712
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte1 == 24'd10502713
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte2 == 24'd10502714
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte3 == 24'd10502715
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_tph_req_cap_int_vec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_tph_req_cap_int_vec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_tph_req_cap_reg_rsvdp_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_tph_req_cap_reg_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_tph_req_cap_reg_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_tph_req_cap_reg_vfcomm_cs2_rsvdp_11_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_tph_req_cap_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_tph_req_cap_reg_vfcomm_cs2_rsvdp_3_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_tph_req_cap_st_table_loc_0 == PF4_NOT_IN_TPH_STRUCT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_tph_req_cap_st_table_loc_0_vfcomm_cs2 == PF4_NOT_IN_TPH_STRUCT_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_tph_req_cap_st_table_loc_1 == PF4_NOT_IN_MSIX_TABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_tph_req_cap_st_table_loc_1_vfcomm_cs2 == PF4_NOT_IN_MSIX_TABLE_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_tph_req_cap_st_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_tph_req_cap_st_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_tph_req_cap_ver == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_tph_req_device_spec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_tph_req_device_spec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_tph_req_extended_tph == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_tph_req_extended_tph_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_tph_req_next_ptr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_tph_req_no_st_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_tph_req_no_st_mode_vfcomm_cs2 == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_bar0_mask_reg_addr_byte0 == 24'd2113552
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_bar0_mask_reg_addr_byte1 == 24'd2113553
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_bar0_mask_reg_addr_byte2 == 24'd2113554
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_bar0_mask_reg_addr_byte3 == 24'd2113555
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_bar0_reg_addr_byte0 == 24'd16400
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_bar1_enable_reg_addr_byte0 == 24'd2113556
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_bar1_mask_reg_addr_byte0 == 24'd2113556
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_bar1_mask_reg_addr_byte1 == 24'd2113557
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_bar1_mask_reg_addr_byte2 == 24'd2113558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_bar1_mask_reg_addr_byte3 == 24'd2113559
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_bar1_reg_addr_byte0 == 24'd16404
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_bar2_mask_reg_addr_byte0 == 24'd2113560
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_bar2_mask_reg_addr_byte1 == 24'd2113561
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_bar2_mask_reg_addr_byte2 == 24'd2113562
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_bar2_mask_reg_addr_byte3 == 24'd2113563
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_bar2_reg_addr_byte0 == 24'd16408
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_bar3_enable_reg_addr_byte0 == 24'd2113564
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_bar3_mask_reg_addr_byte0 == 24'd2113564
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_bar3_mask_reg_addr_byte1 == 24'd2113565
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_bar3_mask_reg_addr_byte2 == 24'd2113566
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_bar3_mask_reg_addr_byte3 == 24'd2113567
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_bar3_reg_addr_byte0 == 24'd16412
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_bar4_mask_reg_addr_byte0 == 24'd2113568
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_bar4_mask_reg_addr_byte1 == 24'd2113569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_bar4_mask_reg_addr_byte2 == 24'd2113570
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_bar4_mask_reg_addr_byte3 == 24'd2113571
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_bar4_reg_addr_byte0 == 24'd16416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_bar5_enable_reg_addr_byte0 == 24'd2113572
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_bar5_mask_reg_addr_byte0 == 24'd2113572
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_bar5_mask_reg_addr_byte1 == 24'd2113573
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_bar5_mask_reg_addr_byte2 == 24'd2113574
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_bar5_mask_reg_addr_byte3 == 24'd2113575
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_bar5_reg_addr_byte0 == 24'd16420
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_bist_header_type_latency_cache_line_size_reg_addr_byte2 == 24'd8405006
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_cardbus_cis_ptr_reg_addr_byte0 == 24'd8405032
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_cardbus_cis_ptr_reg_addr_byte1 == 24'd8405033
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_cardbus_cis_ptr_reg_addr_byte2 == 24'd8405034
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_cardbus_cis_ptr_reg_addr_byte3 == 24'd8405035
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_class_code_revision_id_addr_byte0 == 24'd8405000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_class_code_revision_id_addr_byte1 == 24'd8405001
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_class_code_revision_id_addr_byte2 == 24'd8405002
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_class_code_revision_id_addr_byte3 == 24'd8405003
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_device_id_vendor_id_reg_addr_byte0 == 24'd8404992
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_device_id_vendor_id_reg_addr_byte1 == 24'd8404993
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_device_id_vendor_id_reg_addr_byte2 == 24'd8404994
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_device_id_vendor_id_reg_addr_byte3 == 24'd8404995
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_exp_rom_bar_mask_reg_addr_byte0 == 24'd2113584
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_exp_rom_bar_mask_reg_addr_byte1 == 24'd2113585
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_exp_rom_bar_mask_reg_addr_byte2 == 24'd2113586
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_exp_rom_bar_mask_reg_addr_byte3 == 24'd2113587
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_exp_rom_base_addr_reg_addr_byte0 == 24'd16432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_max_latency_min_grant_interrupt_pin_interrupt_line_reg_addr_byte1 == 24'd8405053
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_pci_cap_ptr_reg_addr_byte0 == 24'd8405044
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte0 == 24'd8405036
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte1 == 24'd8405037
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte2 == 24'd8405038
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte3 == 24'd8405039
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_vf_bar0_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_vf_bar1_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_vf_bar2_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_vf_bar3_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_vf_bar4_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_vf_bar5_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_vsecras_cap_rasdp_ext_hdr_off_addr_byte2 == 24'd8406014
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_vsecras_cap_rasdp_ext_hdr_off_addr_byte3 == 24'd8406015
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_vsecras_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf4_vsecras_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_acs_cap_acs_at_block == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_acs_cap_acs_cap_hdr_reg_addr_byte2 == 24'd8409810
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_acs_cap_acs_cap_hdr_reg_addr_byte3 == 24'd8409811
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_acs_cap_acs_capalities_ctrl_reg_addr_byte0 == 24'd8409812
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_acs_cap_acs_capalities_ctrl_reg_addr_byte1 == 24'd21205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_acs_cap_acs_direct_translated_p2p == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_acs_cap_acs_egress_ctrl_size == 8'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_acs_cap_acs_p2p_cpl_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_acs_cap_acs_p2p_egress_control == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_acs_cap_acs_p2p_req_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_acs_cap_acs_src_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_acs_cap_acs_usp_forwarding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_acs_cap_rsvdp_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_acs_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_acs_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_aer_cap_aer_ext_cap_hdr_off_addr_byte2 == 24'd8409346
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_aer_cap_aer_ext_cap_hdr_off_addr_byte3 == 24'd8409347
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_aer_cap_version == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_aer_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_ari_cap_ari_base_addr_byte2 == 24'd8409462
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_ari_cap_ari_base_addr_byte3 == 24'd8409463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_ari_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_ari_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_ats_cap_ats_cap_hdr_reg_addr_byte2 == 24'd8409794
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_ats_cap_ats_cap_hdr_reg_addr_byte3 == 24'd8409795
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_ats_cap_ats_capabilities_ctrl_reg_addr_byte0 == 24'd8409796
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_ats_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_ats_capabilities_ctrl_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_ats_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_aux_curr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_bar0_mem_io == PF5_BAR0_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_bar0_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_bar0_type == PF5_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_bar1_mem_io == PF5_BAR1_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_bar1_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_bar1_type == PF5_BAR1_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_bar2_mem_io == PF5_BAR2_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_bar2_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_bar2_type == PF5_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_bar3_mem_io == PF5_BAR3_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_bar3_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_bar3_type == PF5_BAR3_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_bar4_mem_io == PF5_BAR4_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_bar4_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_bar4_type == PF5_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_bar5_mem_io == PF5_BAR5_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_bar5_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_bar5_type == PF5_BAR5_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_base_class_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_cap_id_nxt_ptr_reg_rsvdp_20 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_cap_pointer == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_cardbus_cis_pointer == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_con_status_reg_rsvdp_2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_con_status_reg_rsvdp_4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_d1_support == PF5_D1_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_d2_support == PF5_D2_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_10 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_11 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_12 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_13 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_14 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_15 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_16 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_17 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_18 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_19 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_20 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_21 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_22 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_23 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_24 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_25 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_26 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_27 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_28 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_29 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_30 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_31 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_32 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_33 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_34 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_35 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_36 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_37 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_38 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_39 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_40 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_41 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_42 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_43 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_44 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_45 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_46 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_47 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_48 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_49 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_50 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_51 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_52 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_53 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_54 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_55 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_56 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_57 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_58 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_59 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_6 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_60 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_61 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_62 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_63 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_64 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_65 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_7 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_8 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dbi_reserved_9 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_device_capabilities_reg_rsvdp_12 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_device_capabilities_reg_rsvdp_16 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_device_capabilities_reg_rsvdp_29 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_dsi == PF5_NOT_REQUIRED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_exp_rom_bar_mask_reg_rsvdp_1 == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_exp_rom_base_addr_reg_rsvdp_1 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_global_inval_spprtd == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_header_type == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_int_pin == PF5_NO_INT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_invalidate_q_depth == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_link_capabilities_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_link_control_link_status_reg_rsvdp_12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_link_control_link_status_reg_rsvdp_2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_link_control_link_status_reg_rsvdp_26 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_link_control_link_status_reg_rsvdp_9 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte1 == 24'd8409169
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte2 == 24'd8409170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte3 == 24'd8409171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_msi_cap_pci_msi_cap_id_next_ctrl_reg_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_msix_cap_msix_pba_offset_reg_addr_byte0 == 24'd8409272
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_msix_cap_msix_pba_offset_reg_addr_byte1 == 24'd8409273
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_msix_cap_msix_pba_offset_reg_addr_byte2 == 24'd8409274
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_msix_cap_msix_pba_offset_reg_addr_byte3 == 24'd8409275
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_msix_cap_msix_table_offset_reg_addr_byte0 == 24'd8409268
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_msix_cap_msix_table_offset_reg_addr_byte1 == 24'd8409269
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_msix_cap_msix_table_offset_reg_addr_byte2 == 24'd8409270
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_msix_cap_msix_table_offset_reg_addr_byte3 == 24'd8409271
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte1 == 24'd8409265
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte2 == 24'd8409266
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte3 == 24'd8409267
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte2 == 24'd10506418
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte3 == 24'd10506419
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_multi_func == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_no_soft_rst == PF5_INTERNALLY_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_page_aligned_req == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pasid_cap_execute_permission_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pasid_cap_max_pasid_width == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pasid_cap_pasid_cap_cntrl_reg_addr_byte0 == 24'd8409848
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pasid_cap_pasid_cap_cntrl_reg_addr_byte1 == 24'd8409849
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pasid_cap_pasid_ext_hdr_reg_addr_byte2 == 24'd8409846
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pasid_cap_pasid_ext_hdr_reg_addr_byte3 == 24'd8409847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pasid_cap_privileged_mode_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pasid_cap_rsvdp_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pasid_cap_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pasid_cap_rsvpd_13 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pasid_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pasid_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_msi_64_bit_addr_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_msi_cap_next_offset == 8'd112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_msi_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_msi_ext_data_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_msi_ext_data_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_msi_multiple_msg_cap == PF5_MSI_VEC_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_msi_multiple_msg_en == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_msix_bir == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_msix_cap_id_next_ctrl_reg_rsvdp_27 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_msix_cap_next_offset == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_msix_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_msix_enable_vfcomm_cs2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_msix_function_mask == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_msix_function_mask_vfcomm_cs2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_msix_pba == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_msix_pba_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_msix_table_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_msix_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_msix_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_pvm_support == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_type0_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_type0_bar0_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_type0_bar1_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_type0_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_type0_bar1_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_type0_bar1_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_type0_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_type0_bar2_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_type0_bar3_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_type0_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_type0_bar3_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_type0_bar3_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_type0_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_type0_bar4_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_type0_bar5_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_type0_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_type0_bar5_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_type0_bar5_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_type0_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pci_type0_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_active_state_link_pm_control == PF5_ASPM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_active_state_link_pm_support == PF5_NO_ASPM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_aspm_opt_compliance == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_aux_power_pm_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_clock_power_man == PF5_REFCLK_REMOVE_NOT_OK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_common_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_device_capabilities_reg_addr_byte0 == 24'd8409204
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_device_capabilities_reg_addr_byte1 == 24'd8409205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_device_capabilities_reg_addr_byte3 == 24'd8409207
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_device_control_device_status_addr_byte1 == 24'd8409209
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_dll_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_dll_active_rep_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_en_clk_power_man == PF5_CLKREQ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_en_no_snoop == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_enter_compliance == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_ep_l0s_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_ep_l1_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_ext_tag_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_ext_tag_supp == PF5_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_extended_synch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_flr_cap == PF5_NOT_CAPABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_hw_auto_speed_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvd == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_initiate_flr == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_l0s_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_l1_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_link_auto_bw_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_link_auto_bw_status == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_link_bw_man_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_link_bw_man_status == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_link_bw_not_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_link_capabilities_reg_addr_byte0 == 24'd8409212
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_link_capabilities_reg_addr_byte1 == 24'd8409213
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_link_capabilities_reg_addr_byte2 == 24'd8409214
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_link_capabilities_reg_addr_byte3 == 24'd20607
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_link_control2_link_status2_reg_addr_byte0 == 24'd12603552
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_link_control_link_status_reg_addr_byte0 == 24'd4214912
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_link_control_link_status_reg_addr_byte1 == 24'd12603521
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_link_control_link_status_reg_addr_byte3 == 24'd4214915
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_link_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_link_training == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_max_link_speed == PF5_MAX_2P5GTS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_max_link_width == PF5_X1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_max_payload_size == PF5_PAYLOAD_128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_max_read_req_size == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_nego_link_width == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_next_ptr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte1 == 24'd8409201
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte3 == 24'd8409203
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_phantom_func_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_phantom_func_support == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_port_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_rcb == PF5_RCB_64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_retrain_link == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_role_based_err_report == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_sel_deemphasis == PF5_MINUS_6DB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_slot_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_surprise_down_err_rep_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_target_link_speed == PF5_TRGT_GEN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_cap_tx_margin == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_int_msg_num == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pcie_slot_imp == PF5_NOT_IMPLEMENTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pf0_ari_device_number == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pf0_dbi_ro_wr_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pf0_default_target == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pf0_disable_auto_ltr_clr_msg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pf0_mask_ur_ca_4_trgt1 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pf0_misc_control_1_off_rsvdp_6 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pf0_port_logic_misc_control_1_off_addr_byte0 == 24'd2236
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pf0_simplified_replay_timer == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pf0_tlp_bypass_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pm_cap_cap_id_nxt_ptr_reg_addr_byte1 == 24'd8409153
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pm_cap_cap_id_nxt_ptr_reg_addr_byte2 == 24'd8409154
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pm_cap_cap_id_nxt_ptr_reg_addr_byte3 == 24'd8409155
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pm_cap_con_status_reg_addr_byte0 == 24'd8409156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pm_next_pointer == 8'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pm_spec_ver == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pme_clk == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_pme_support == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_power_state == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_program_interface == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte2 == 24'd8409822
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte3 == 24'd8409823
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_prs_ext_cap_prs_req_capacity_reg_addr_byte0 == 24'd8409828
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_prs_ext_cap_prs_req_capacity_reg_addr_byte1 == 24'd8409829
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_prs_ext_cap_prs_req_capacity_reg_addr_byte2 == 24'd8409830
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_prs_ext_cap_prs_req_capacity_reg_addr_byte3 == 24'd8409831
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_prs_ext_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_prs_ext_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_prs_outstanding_capacity == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_ras_des_cap_event_counter_ctrl_reg_addr_byte0 == 24'd21252
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_ras_des_cap_event_counter_ctrl_reg_g5_addr_byte3 == 24'd8409863
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_ras_des_cap_event_counter_ctrl_reg_g6_addr_byte3 == 24'd8409863
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_ras_des_cap_event_counter_ctrl_reg_g7_addr_byte3 == 24'd8409863
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_ras_des_cap_force_detect_lane == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_ras_des_cap_force_detect_lane_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_ras_des_cap_ras_des_hdr_reg_addr_byte2 == 24'd8409854
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_ras_des_cap_ras_des_hdr_reg_addr_byte3 == 24'd8409855
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_ras_des_cap_sd_control1_reg_addr_byte0 == 24'd8410012
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_ras_des_cap_sd_control1_reg_addr_byte1 == 24'd8410013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_ras_des_cap_sd_control1_reg_addr_byte2 == 24'd8410014
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_ras_des_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_ras_des_event_counter_en == 8'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_ras_des_event_counter_event_select_g5 == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_ras_des_event_counter_event_select_g6 == 8'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_ras_des_event_counter_event_select_g7 == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_ras_des_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_10_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_11_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_12_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_13_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_14_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_15_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_16_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_17_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_18_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_19_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_20_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_21_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_22_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_23_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_24_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_25_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_26_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_27_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_28_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_29_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_30_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_31_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_32_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_33_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_34_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_35_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_36_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_37_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_38_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_39_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_40_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_41_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_42_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_43_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_44_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_45_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_46_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_47_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_48_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_49_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_50_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_51_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_52_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_53_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_54_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_55_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_56_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_57_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_58_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_59_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_60_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_61_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_62_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_63_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_64_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_65_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_7_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_8_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_reserved_9_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_revision_id == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_rom_bar_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_rom_bar_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_shadow_sriov_vf_stride_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sn_cap_ser_num_reg_dw_1_addr_byte0 == 24'd8409448
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sn_cap_ser_num_reg_dw_1_addr_byte1 == 24'd8409449
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sn_cap_ser_num_reg_dw_1_addr_byte2 == 24'd8409450
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sn_cap_ser_num_reg_dw_1_addr_byte3 == 24'd8409451
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sn_cap_ser_num_reg_dw_2_addr_byte0 == 24'd8409452
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sn_cap_ser_num_reg_dw_2_addr_byte1 == 24'd8409453
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sn_cap_ser_num_reg_dw_2_addr_byte2 == 24'd8409454
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sn_cap_ser_num_reg_dw_2_addr_byte3 == 24'd8409455
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sn_cap_sn_base_addr_byte2 == 24'd8409446
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sn_cap_sn_base_addr_byte3 == 24'd8409447
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sn_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sn_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sn_ser_num_reg_1_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sn_ser_num_reg_2_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_shadow_sriov_initial_vfs_addr_byte0 == 24'd10506752
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_shadow_sriov_initial_vfs_addr_byte1 == 24'd10506753
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_shadow_sriov_vf_offset_position_addr_byte0 == 24'd10506760
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_shadow_sriov_vf_offset_position_addr_byte1 == 24'd10506761
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_shadow_sriov_vf_offset_position_addr_byte2 == 24'd10506762
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_shadow_sriov_vf_offset_position_addr_byte3 == 24'd10506763
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_shadow_vf_bar0_reg_addr_byte0 == 24'd2118168
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_shadow_vf_bar0_reg_addr_byte1 == 24'd2118169
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_shadow_vf_bar0_reg_addr_byte2 == 24'd2118170
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_shadow_vf_bar0_reg_addr_byte3 == 24'd2118171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_shadow_vf_bar1_reg_addr_byte0 == 24'd2118172
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_shadow_vf_bar1_reg_addr_byte1 == 24'd2118173
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_shadow_vf_bar1_reg_addr_byte2 == 24'd2118174
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_shadow_vf_bar1_reg_addr_byte3 == 24'd2118175
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_shadow_vf_bar2_reg_addr_byte0 == 24'd2118176
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_shadow_vf_bar2_reg_addr_byte1 == 24'd2118177
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_shadow_vf_bar2_reg_addr_byte2 == 24'd2118178
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_shadow_vf_bar2_reg_addr_byte3 == 24'd2118179
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_shadow_vf_bar3_reg_addr_byte0 == 24'd2118180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_shadow_vf_bar3_reg_addr_byte1 == 24'd2118181
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_shadow_vf_bar3_reg_addr_byte2 == 24'd2118182
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_shadow_vf_bar3_reg_addr_byte3 == 24'd2118183
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_shadow_vf_bar4_reg_addr_byte0 == 24'd2118184
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_shadow_vf_bar4_reg_addr_byte1 == 24'd2118185
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_shadow_vf_bar4_reg_addr_byte2 == 24'd2118186
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_shadow_vf_bar4_reg_addr_byte3 == 24'd2118187
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_shadow_vf_bar5_reg_addr_byte0 == 24'd2118188
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_shadow_vf_bar5_reg_addr_byte1 == 24'd2118189
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_shadow_vf_bar5_reg_addr_byte2 == 24'd2118190
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_shadow_vf_bar5_reg_addr_byte3 == 24'd2118191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_sriov_bar1_enable_reg_addr_byte0 == 24'd2118172
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_sriov_bar3_enable_reg_addr_byte0 == 24'd2118180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_sriov_bar5_enable_reg_addr_byte0 == 24'd2118188
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_sriov_base_reg_addr_byte2 == 24'd8409590
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_sriov_base_reg_addr_byte3 == 24'd8409591
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_sriov_initial_vfs_addr_byte0 == 24'd8409600
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_sriov_initial_vfs_addr_byte1 == 24'd8409601
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_sriov_vf_offset_position_addr_byte0 == 24'd8409608
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_sriov_vf_offset_position_addr_byte1 == 24'd8409609
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_sriov_vf_offset_position_addr_byte2 == 24'd8409610
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_sriov_vf_offset_position_addr_byte3 == 24'd8409611
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_sup_page_sizes_reg_addr_byte0 == 24'd8409616
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_sup_page_sizes_reg_addr_byte1 == 24'd8409617
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_sup_page_sizes_reg_addr_byte2 == 24'd8409618
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_sup_page_sizes_reg_addr_byte3 == 24'd8409619
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_vf_bar0_reg_addr_byte0 == 24'd21016
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_vf_bar1_reg_addr_byte0 == 24'd21020
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_vf_bar2_reg_addr_byte0 == 24'd21024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_vf_bar3_reg_addr_byte0 == 24'd21028
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_vf_bar4_reg_addr_byte0 == 24'd21032
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_vf_bar5_reg_addr_byte0 == 24'd21036
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_vf_device_id_reg_addr_byte2 == 24'd8409614
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_cap_vf_device_id_reg_addr_byte3 == 24'd8409615
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_initial_vfs_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_initial_vfs_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_sup_page_size == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_vf_bar0_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_vf_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_vf_bar0_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_vf_bar0_type == PF5_SRIOV_VF_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_vf_bar1_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_vf_bar1_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_vf_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_vf_bar1_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_vf_bar1_type == PF5_SRIOV_VF_BAR1_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_vf_bar2_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_vf_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_vf_bar2_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_vf_bar2_type == PF5_SRIOV_VF_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_vf_bar3_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_vf_bar3_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_vf_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_vf_bar3_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_vf_bar3_type == PF5_SRIOV_VF_BAR3_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_vf_bar4_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_vf_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_vf_bar4_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_vf_bar4_type == PF5_SRIOV_VF_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_vf_bar5_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_vf_bar5_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_vf_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_vf_bar5_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_vf_bar5_type == PF5_SRIOV_VF_BAR5_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_vf_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_vf_offset_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_vf_offset_position_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_sriov_vf_stride_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_subclass_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_subsys_dev_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_subsys_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_tph_cap_tph_ext_cap_hdr_reg_addr_byte2 == 24'd8409654
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_tph_cap_tph_ext_cap_hdr_reg_addr_byte3 == 24'd8409655
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_tph_cap_tph_req_cap_reg_addr_byte0 == 24'd8409656
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_tph_cap_tph_req_cap_reg_addr_byte1 == 24'd8409657
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_tph_cap_tph_req_cap_reg_addr_byte2 == 24'd8409658
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_tph_cap_tph_req_cap_reg_addr_byte3 == 24'd8409659
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte0 == 24'd10506808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte1 == 24'd10506809
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte2 == 24'd10506810
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte3 == 24'd10506811
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_tph_req_cap_int_vec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_tph_req_cap_int_vec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_tph_req_cap_reg_rsvdp_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_tph_req_cap_reg_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_tph_req_cap_reg_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_tph_req_cap_reg_vfcomm_cs2_rsvdp_11_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_tph_req_cap_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_tph_req_cap_reg_vfcomm_cs2_rsvdp_3_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_tph_req_cap_st_table_loc_0 == PF5_NOT_IN_TPH_STRUCT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_tph_req_cap_st_table_loc_0_vfcomm_cs2 == PF5_NOT_IN_TPH_STRUCT_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_tph_req_cap_st_table_loc_1 == PF5_NOT_IN_MSIX_TABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_tph_req_cap_st_table_loc_1_vfcomm_cs2 == PF5_NOT_IN_MSIX_TABLE_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_tph_req_cap_st_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_tph_req_cap_st_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_tph_req_cap_ver == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_tph_req_device_spec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_tph_req_device_spec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_tph_req_extended_tph == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_tph_req_extended_tph_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_tph_req_next_ptr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_tph_req_no_st_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_tph_req_no_st_mode_vfcomm_cs2 == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_bar0_mask_reg_addr_byte0 == 24'd2117648
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_bar0_mask_reg_addr_byte1 == 24'd2117649
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_bar0_mask_reg_addr_byte2 == 24'd2117650
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_bar0_mask_reg_addr_byte3 == 24'd2117651
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_bar0_reg_addr_byte0 == 24'd20496
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_bar1_enable_reg_addr_byte0 == 24'd2117652
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_bar1_mask_reg_addr_byte0 == 24'd2117652
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_bar1_mask_reg_addr_byte1 == 24'd2117653
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_bar1_mask_reg_addr_byte2 == 24'd2117654
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_bar1_mask_reg_addr_byte3 == 24'd2117655
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_bar1_reg_addr_byte0 == 24'd20500
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_bar2_mask_reg_addr_byte0 == 24'd2117656
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_bar2_mask_reg_addr_byte1 == 24'd2117657
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_bar2_mask_reg_addr_byte2 == 24'd2117658
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_bar2_mask_reg_addr_byte3 == 24'd2117659
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_bar2_reg_addr_byte0 == 24'd20504
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_bar3_enable_reg_addr_byte0 == 24'd2117660
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_bar3_mask_reg_addr_byte0 == 24'd2117660
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_bar3_mask_reg_addr_byte1 == 24'd2117661
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_bar3_mask_reg_addr_byte2 == 24'd2117662
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_bar3_mask_reg_addr_byte3 == 24'd2117663
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_bar3_reg_addr_byte0 == 24'd20508
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_bar4_mask_reg_addr_byte0 == 24'd2117664
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_bar4_mask_reg_addr_byte1 == 24'd2117665
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_bar4_mask_reg_addr_byte2 == 24'd2117666
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_bar4_mask_reg_addr_byte3 == 24'd2117667
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_bar4_reg_addr_byte0 == 24'd20512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_bar5_enable_reg_addr_byte0 == 24'd2117668
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_bar5_mask_reg_addr_byte0 == 24'd2117668
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_bar5_mask_reg_addr_byte1 == 24'd2117669
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_bar5_mask_reg_addr_byte2 == 24'd2117670
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_bar5_mask_reg_addr_byte3 == 24'd2117671
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_bar5_reg_addr_byte0 == 24'd20516
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_bist_header_type_latency_cache_line_size_reg_addr_byte2 == 24'd8409102
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_cardbus_cis_ptr_reg_addr_byte0 == 24'd8409128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_cardbus_cis_ptr_reg_addr_byte1 == 24'd8409129
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_cardbus_cis_ptr_reg_addr_byte2 == 24'd8409130
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_cardbus_cis_ptr_reg_addr_byte3 == 24'd8409131
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_class_code_revision_id_addr_byte0 == 24'd8409096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_class_code_revision_id_addr_byte1 == 24'd8409097
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_class_code_revision_id_addr_byte2 == 24'd8409098
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_class_code_revision_id_addr_byte3 == 24'd8409099
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_device_id_vendor_id_reg_addr_byte0 == 24'd8409088
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_device_id_vendor_id_reg_addr_byte1 == 24'd8409089
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_device_id_vendor_id_reg_addr_byte2 == 24'd8409090
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_device_id_vendor_id_reg_addr_byte3 == 24'd8409091
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_exp_rom_bar_mask_reg_addr_byte0 == 24'd2117680
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_exp_rom_bar_mask_reg_addr_byte1 == 24'd2117681
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_exp_rom_bar_mask_reg_addr_byte2 == 24'd2117682
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_exp_rom_bar_mask_reg_addr_byte3 == 24'd2117683
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_exp_rom_base_addr_reg_addr_byte0 == 24'd20528
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_max_latency_min_grant_interrupt_pin_interrupt_line_reg_addr_byte1 == 24'd8409149
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_pci_cap_ptr_reg_addr_byte0 == 24'd8409140
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte0 == 24'd8409132
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte1 == 24'd8409133
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte2 == 24'd8409134
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte3 == 24'd8409135
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_vf_bar0_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_vf_bar1_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_vf_bar2_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_vf_bar3_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_vf_bar4_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_vf_bar5_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_vsecras_cap_rasdp_ext_hdr_off_addr_byte2 == 24'd8410110
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_vsecras_cap_rasdp_ext_hdr_off_addr_byte3 == 24'd8410111
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_vsecras_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf5_vsecras_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_acs_cap_acs_at_block == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_acs_cap_acs_cap_hdr_reg_addr_byte2 == 24'd8413906
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_acs_cap_acs_cap_hdr_reg_addr_byte3 == 24'd8413907
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_acs_cap_acs_capalities_ctrl_reg_addr_byte0 == 24'd8413908
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_acs_cap_acs_capalities_ctrl_reg_addr_byte1 == 24'd25301
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_acs_cap_acs_direct_translated_p2p == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_acs_cap_acs_egress_ctrl_size == 8'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_acs_cap_acs_p2p_cpl_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_acs_cap_acs_p2p_egress_control == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_acs_cap_acs_p2p_req_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_acs_cap_acs_src_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_acs_cap_acs_usp_forwarding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_acs_cap_rsvdp_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_acs_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_acs_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_aer_cap_aer_ext_cap_hdr_off_addr_byte2 == 24'd8413442
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_aer_cap_aer_ext_cap_hdr_off_addr_byte3 == 24'd8413443
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_aer_cap_version == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_aer_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_ari_cap_ari_base_addr_byte2 == 24'd8413558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_ari_cap_ari_base_addr_byte3 == 24'd8413559
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_ari_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_ari_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_ats_cap_ats_cap_hdr_reg_addr_byte2 == 24'd8413890
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_ats_cap_ats_cap_hdr_reg_addr_byte3 == 24'd8413891
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_ats_cap_ats_capabilities_ctrl_reg_addr_byte0 == 24'd8413892
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_ats_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_ats_capabilities_ctrl_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_ats_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_aux_curr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_bar0_mem_io == PF6_BAR0_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_bar0_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_bar0_type == PF6_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_bar1_mem_io == PF6_BAR1_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_bar1_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_bar1_type == PF6_BAR1_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_bar2_mem_io == PF6_BAR2_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_bar2_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_bar2_type == PF6_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_bar3_mem_io == PF6_BAR3_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_bar3_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_bar3_type == PF6_BAR3_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_bar4_mem_io == PF6_BAR4_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_bar4_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_bar4_type == PF6_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_bar5_mem_io == PF6_BAR5_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_bar5_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_bar5_type == PF6_BAR5_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_base_class_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_cap_id_nxt_ptr_reg_rsvdp_20 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_cap_pointer == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_cardbus_cis_pointer == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_con_status_reg_rsvdp_2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_con_status_reg_rsvdp_4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_d1_support == PF6_D1_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_d2_support == PF6_D2_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_10 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_11 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_12 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_13 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_14 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_15 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_16 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_17 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_18 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_19 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_20 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_21 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_22 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_23 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_24 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_25 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_26 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_27 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_28 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_29 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_30 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_31 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_32 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_33 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_34 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_35 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_36 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_37 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_38 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_39 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_40 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_41 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_42 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_43 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_44 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_45 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_46 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_47 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_48 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_49 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_50 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_51 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_52 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_53 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_54 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_55 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_56 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_57 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_58 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_59 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_6 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_60 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_61 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_62 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_63 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_64 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_65 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_7 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_8 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dbi_reserved_9 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_device_capabilities_reg_rsvdp_12 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_device_capabilities_reg_rsvdp_16 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_device_capabilities_reg_rsvdp_29 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_dsi == PF6_NOT_REQUIRED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_exp_rom_bar_mask_reg_rsvdp_1 == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_exp_rom_base_addr_reg_rsvdp_1 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_global_inval_spprtd == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_header_type == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_int_pin == PF6_NO_INT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_invalidate_q_depth == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_link_capabilities_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_link_control_link_status_reg_rsvdp_12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_link_control_link_status_reg_rsvdp_2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_link_control_link_status_reg_rsvdp_26 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_link_control_link_status_reg_rsvdp_9 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte1 == 24'd8413265
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte2 == 24'd8413266
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte3 == 24'd8413267
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_msi_cap_pci_msi_cap_id_next_ctrl_reg_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_msix_cap_msix_pba_offset_reg_addr_byte0 == 24'd8413368
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_msix_cap_msix_pba_offset_reg_addr_byte1 == 24'd8413369
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_msix_cap_msix_pba_offset_reg_addr_byte2 == 24'd8413370
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_msix_cap_msix_pba_offset_reg_addr_byte3 == 24'd8413371
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_msix_cap_msix_table_offset_reg_addr_byte0 == 24'd8413364
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_msix_cap_msix_table_offset_reg_addr_byte1 == 24'd8413365
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_msix_cap_msix_table_offset_reg_addr_byte2 == 24'd8413366
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_msix_cap_msix_table_offset_reg_addr_byte3 == 24'd8413367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte1 == 24'd8413361
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte2 == 24'd8413362
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte3 == 24'd8413363
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte2 == 24'd10510514
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte3 == 24'd10510515
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_multi_func == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_no_soft_rst == PF6_INTERNALLY_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_page_aligned_req == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pasid_cap_execute_permission_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pasid_cap_max_pasid_width == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pasid_cap_pasid_cap_cntrl_reg_addr_byte0 == 24'd8413944
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pasid_cap_pasid_cap_cntrl_reg_addr_byte1 == 24'd8413945
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pasid_cap_pasid_ext_hdr_reg_addr_byte2 == 24'd8413942
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pasid_cap_pasid_ext_hdr_reg_addr_byte3 == 24'd8413943
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pasid_cap_privileged_mode_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pasid_cap_rsvdp_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pasid_cap_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pasid_cap_rsvpd_13 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pasid_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pasid_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_msi_64_bit_addr_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_msi_cap_next_offset == 8'd112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_msi_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_msi_ext_data_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_msi_ext_data_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_msi_multiple_msg_cap == PF6_MSI_VEC_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_msi_multiple_msg_en == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_msix_bir == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_msix_cap_id_next_ctrl_reg_rsvdp_27 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_msix_cap_next_offset == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_msix_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_msix_enable_vfcomm_cs2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_msix_function_mask == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_msix_function_mask_vfcomm_cs2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_msix_pba == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_msix_pba_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_msix_table_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_msix_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_msix_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_pvm_support == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_type0_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_type0_bar0_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_type0_bar1_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_type0_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_type0_bar1_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_type0_bar1_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_type0_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_type0_bar2_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_type0_bar3_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_type0_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_type0_bar3_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_type0_bar3_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_type0_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_type0_bar4_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_type0_bar5_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_type0_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_type0_bar5_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_type0_bar5_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_type0_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pci_type0_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_active_state_link_pm_control == PF6_ASPM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_active_state_link_pm_support == PF6_NO_ASPM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_aspm_opt_compliance == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_aux_power_pm_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_clock_power_man == PF6_REFCLK_REMOVE_NOT_OK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_common_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_device_capabilities_reg_addr_byte0 == 24'd8413300
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_device_capabilities_reg_addr_byte1 == 24'd8413301
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_device_capabilities_reg_addr_byte3 == 24'd8413303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_device_control_device_status_addr_byte1 == 24'd8413305
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_dll_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_dll_active_rep_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_en_clk_power_man == PF6_CLKREQ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_en_no_snoop == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_enter_compliance == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_ep_l0s_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_ep_l1_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_ext_tag_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_ext_tag_supp == PF6_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_extended_synch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_flr_cap == PF6_NOT_CAPABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_hw_auto_speed_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvd == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_initiate_flr == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_l0s_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_l1_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_link_auto_bw_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_link_auto_bw_status == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_link_bw_man_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_link_bw_man_status == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_link_bw_not_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_link_capabilities_reg_addr_byte0 == 24'd8413308
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_link_capabilities_reg_addr_byte1 == 24'd8413309
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_link_capabilities_reg_addr_byte2 == 24'd8413310
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_link_capabilities_reg_addr_byte3 == 24'd24703
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_link_control2_link_status2_reg_addr_byte0 == 24'd12607648
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_link_control_link_status_reg_addr_byte0 == 24'd4219008
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_link_control_link_status_reg_addr_byte1 == 24'd12607617
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_link_control_link_status_reg_addr_byte3 == 24'd4219011
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_link_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_link_training == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_max_link_speed == PF6_MAX_2P5GTS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_max_link_width == PF6_X1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_max_payload_size == PF6_PAYLOAD_128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_max_read_req_size == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_nego_link_width == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_next_ptr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte1 == 24'd8413297
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte3 == 24'd8413299
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_phantom_func_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_phantom_func_support == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_port_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_rcb == PF6_RCB_64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_retrain_link == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_role_based_err_report == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_sel_deemphasis == PF6_MINUS_6DB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_slot_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_surprise_down_err_rep_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_target_link_speed == PF6_TRGT_GEN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_cap_tx_margin == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_int_msg_num == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pcie_slot_imp == PF6_NOT_IMPLEMENTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pf0_ari_device_number == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pf0_dbi_ro_wr_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pf0_default_target == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pf0_disable_auto_ltr_clr_msg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pf0_mask_ur_ca_4_trgt1 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pf0_misc_control_1_off_rsvdp_6 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pf0_port_logic_misc_control_1_off_addr_byte0 == 24'd2236
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pf0_simplified_replay_timer == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pf0_tlp_bypass_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pm_cap_cap_id_nxt_ptr_reg_addr_byte1 == 24'd8413249
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pm_cap_cap_id_nxt_ptr_reg_addr_byte2 == 24'd8413250
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pm_cap_cap_id_nxt_ptr_reg_addr_byte3 == 24'd8413251
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pm_cap_con_status_reg_addr_byte0 == 24'd8413252
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pm_next_pointer == 8'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pm_spec_ver == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pme_clk == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_pme_support == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_power_state == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_program_interface == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte2 == 24'd8413918
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte3 == 24'd8413919
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_prs_ext_cap_prs_req_capacity_reg_addr_byte0 == 24'd8413924
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_prs_ext_cap_prs_req_capacity_reg_addr_byte1 == 24'd8413925
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_prs_ext_cap_prs_req_capacity_reg_addr_byte2 == 24'd8413926
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_prs_ext_cap_prs_req_capacity_reg_addr_byte3 == 24'd8413927
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_prs_ext_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_prs_ext_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_prs_outstanding_capacity == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_ras_des_cap_event_counter_ctrl_reg_addr_byte0 == 24'd25348
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_ras_des_cap_event_counter_ctrl_reg_g5_addr_byte3 == 24'd8413959
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_ras_des_cap_event_counter_ctrl_reg_g6_addr_byte3 == 24'd8413959
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_ras_des_cap_event_counter_ctrl_reg_g7_addr_byte3 == 24'd8413959
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_ras_des_cap_force_detect_lane == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_ras_des_cap_force_detect_lane_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_ras_des_cap_ras_des_hdr_reg_addr_byte2 == 24'd8413950
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_ras_des_cap_ras_des_hdr_reg_addr_byte3 == 24'd8413951
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_ras_des_cap_sd_control1_reg_addr_byte0 == 24'd8414108
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_ras_des_cap_sd_control1_reg_addr_byte1 == 24'd8414109
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_ras_des_cap_sd_control1_reg_addr_byte2 == 24'd8414110
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_ras_des_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_ras_des_event_counter_en == 8'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_ras_des_event_counter_event_select_g5 == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_ras_des_event_counter_event_select_g6 == 8'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_ras_des_event_counter_event_select_g7 == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_ras_des_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_10_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_11_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_12_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_13_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_14_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_15_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_16_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_17_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_18_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_19_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_20_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_21_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_22_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_23_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_24_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_25_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_26_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_27_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_28_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_29_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_30_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_31_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_32_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_33_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_34_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_35_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_36_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_37_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_38_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_39_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_40_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_41_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_42_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_43_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_44_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_45_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_46_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_47_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_48_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_49_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_50_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_51_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_52_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_53_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_54_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_55_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_56_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_57_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_58_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_59_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_60_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_61_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_62_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_63_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_64_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_65_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_7_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_8_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_reserved_9_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_revision_id == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_rom_bar_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_rom_bar_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_shadow_sriov_vf_stride_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sn_cap_ser_num_reg_dw_1_addr_byte0 == 24'd8413544
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sn_cap_ser_num_reg_dw_1_addr_byte1 == 24'd8413545
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sn_cap_ser_num_reg_dw_1_addr_byte2 == 24'd8413546
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sn_cap_ser_num_reg_dw_1_addr_byte3 == 24'd8413547
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sn_cap_ser_num_reg_dw_2_addr_byte0 == 24'd8413548
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sn_cap_ser_num_reg_dw_2_addr_byte1 == 24'd8413549
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sn_cap_ser_num_reg_dw_2_addr_byte2 == 24'd8413550
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sn_cap_ser_num_reg_dw_2_addr_byte3 == 24'd8413551
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sn_cap_sn_base_addr_byte2 == 24'd8413542
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sn_cap_sn_base_addr_byte3 == 24'd8413543
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sn_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sn_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sn_ser_num_reg_1_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sn_ser_num_reg_2_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_shadow_sriov_initial_vfs_addr_byte0 == 24'd10510848
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_shadow_sriov_initial_vfs_addr_byte1 == 24'd10510849
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_shadow_sriov_vf_offset_position_addr_byte0 == 24'd10510856
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_shadow_sriov_vf_offset_position_addr_byte1 == 24'd10510857
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_shadow_sriov_vf_offset_position_addr_byte2 == 24'd10510858
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_shadow_sriov_vf_offset_position_addr_byte3 == 24'd10510859
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_shadow_vf_bar0_reg_addr_byte0 == 24'd2122264
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_shadow_vf_bar0_reg_addr_byte1 == 24'd2122265
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_shadow_vf_bar0_reg_addr_byte2 == 24'd2122266
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_shadow_vf_bar0_reg_addr_byte3 == 24'd2122267
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_shadow_vf_bar1_reg_addr_byte0 == 24'd2122268
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_shadow_vf_bar1_reg_addr_byte1 == 24'd2122269
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_shadow_vf_bar1_reg_addr_byte2 == 24'd2122270
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_shadow_vf_bar1_reg_addr_byte3 == 24'd2122271
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_shadow_vf_bar2_reg_addr_byte0 == 24'd2122272
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_shadow_vf_bar2_reg_addr_byte1 == 24'd2122273
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_shadow_vf_bar2_reg_addr_byte2 == 24'd2122274
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_shadow_vf_bar2_reg_addr_byte3 == 24'd2122275
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_shadow_vf_bar3_reg_addr_byte0 == 24'd2122276
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_shadow_vf_bar3_reg_addr_byte1 == 24'd2122277
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_shadow_vf_bar3_reg_addr_byte2 == 24'd2122278
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_shadow_vf_bar3_reg_addr_byte3 == 24'd2122279
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_shadow_vf_bar4_reg_addr_byte0 == 24'd2122280
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_shadow_vf_bar4_reg_addr_byte1 == 24'd2122281
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_shadow_vf_bar4_reg_addr_byte2 == 24'd2122282
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_shadow_vf_bar4_reg_addr_byte3 == 24'd2122283
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_shadow_vf_bar5_reg_addr_byte0 == 24'd2122284
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_shadow_vf_bar5_reg_addr_byte1 == 24'd2122285
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_shadow_vf_bar5_reg_addr_byte2 == 24'd2122286
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_shadow_vf_bar5_reg_addr_byte3 == 24'd2122287
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_sriov_bar1_enable_reg_addr_byte0 == 24'd2122268
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_sriov_bar3_enable_reg_addr_byte0 == 24'd2122276
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_sriov_bar5_enable_reg_addr_byte0 == 24'd2122284
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_sriov_base_reg_addr_byte2 == 24'd8413686
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_sriov_base_reg_addr_byte3 == 24'd8413687
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_sriov_initial_vfs_addr_byte0 == 24'd8413696
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_sriov_initial_vfs_addr_byte1 == 24'd8413697
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_sriov_vf_offset_position_addr_byte0 == 24'd8413704
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_sriov_vf_offset_position_addr_byte1 == 24'd8413705
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_sriov_vf_offset_position_addr_byte2 == 24'd8413706
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_sriov_vf_offset_position_addr_byte3 == 24'd8413707
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_sup_page_sizes_reg_addr_byte0 == 24'd8413712
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_sup_page_sizes_reg_addr_byte1 == 24'd8413713
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_sup_page_sizes_reg_addr_byte2 == 24'd8413714
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_sup_page_sizes_reg_addr_byte3 == 24'd8413715
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_vf_bar0_reg_addr_byte0 == 24'd25112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_vf_bar1_reg_addr_byte0 == 24'd25116
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_vf_bar2_reg_addr_byte0 == 24'd25120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_vf_bar3_reg_addr_byte0 == 24'd25124
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_vf_bar4_reg_addr_byte0 == 24'd25128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_vf_bar5_reg_addr_byte0 == 24'd25132
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_vf_device_id_reg_addr_byte2 == 24'd8413710
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_cap_vf_device_id_reg_addr_byte3 == 24'd8413711
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_initial_vfs_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_initial_vfs_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_sup_page_size == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_vf_bar0_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_vf_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_vf_bar0_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_vf_bar0_type == PF6_SRIOV_VF_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_vf_bar1_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_vf_bar1_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_vf_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_vf_bar1_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_vf_bar1_type == PF6_SRIOV_VF_BAR1_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_vf_bar2_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_vf_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_vf_bar2_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_vf_bar2_type == PF6_SRIOV_VF_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_vf_bar3_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_vf_bar3_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_vf_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_vf_bar3_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_vf_bar3_type == PF6_SRIOV_VF_BAR3_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_vf_bar4_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_vf_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_vf_bar4_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_vf_bar4_type == PF6_SRIOV_VF_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_vf_bar5_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_vf_bar5_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_vf_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_vf_bar5_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_vf_bar5_type == PF6_SRIOV_VF_BAR5_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_vf_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_vf_offset_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_vf_offset_position_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_sriov_vf_stride_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_subclass_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_subsys_dev_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_subsys_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_tph_cap_tph_ext_cap_hdr_reg_addr_byte2 == 24'd8413750
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_tph_cap_tph_ext_cap_hdr_reg_addr_byte3 == 24'd8413751
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_tph_cap_tph_req_cap_reg_addr_byte0 == 24'd8413752
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_tph_cap_tph_req_cap_reg_addr_byte1 == 24'd8413753
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_tph_cap_tph_req_cap_reg_addr_byte2 == 24'd8413754
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_tph_cap_tph_req_cap_reg_addr_byte3 == 24'd8413755
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte0 == 24'd10510904
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte1 == 24'd10510905
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte2 == 24'd10510906
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte3 == 24'd10510907
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_tph_req_cap_int_vec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_tph_req_cap_int_vec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_tph_req_cap_reg_rsvdp_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_tph_req_cap_reg_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_tph_req_cap_reg_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_tph_req_cap_reg_vfcomm_cs2_rsvdp_11_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_tph_req_cap_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_tph_req_cap_reg_vfcomm_cs2_rsvdp_3_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_tph_req_cap_st_table_loc_0 == PF6_NOT_IN_TPH_STRUCT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_tph_req_cap_st_table_loc_0_vfcomm_cs2 == PF6_NOT_IN_TPH_STRUCT_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_tph_req_cap_st_table_loc_1 == PF6_NOT_IN_MSIX_TABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_tph_req_cap_st_table_loc_1_vfcomm_cs2 == PF6_NOT_IN_MSIX_TABLE_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_tph_req_cap_st_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_tph_req_cap_st_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_tph_req_cap_ver == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_tph_req_device_spec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_tph_req_device_spec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_tph_req_extended_tph == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_tph_req_extended_tph_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_tph_req_next_ptr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_tph_req_no_st_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_tph_req_no_st_mode_vfcomm_cs2 == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_bar0_mask_reg_addr_byte0 == 24'd2121744
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_bar0_mask_reg_addr_byte1 == 24'd2121745
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_bar0_mask_reg_addr_byte2 == 24'd2121746
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_bar0_mask_reg_addr_byte3 == 24'd2121747
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_bar0_reg_addr_byte0 == 24'd24592
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_bar1_enable_reg_addr_byte0 == 24'd2121748
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_bar1_mask_reg_addr_byte0 == 24'd2121748
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_bar1_mask_reg_addr_byte1 == 24'd2121749
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_bar1_mask_reg_addr_byte2 == 24'd2121750
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_bar1_mask_reg_addr_byte3 == 24'd2121751
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_bar1_reg_addr_byte0 == 24'd24596
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_bar2_mask_reg_addr_byte0 == 24'd2121752
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_bar2_mask_reg_addr_byte1 == 24'd2121753
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_bar2_mask_reg_addr_byte2 == 24'd2121754
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_bar2_mask_reg_addr_byte3 == 24'd2121755
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_bar2_reg_addr_byte0 == 24'd24600
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_bar3_enable_reg_addr_byte0 == 24'd2121756
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_bar3_mask_reg_addr_byte0 == 24'd2121756
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_bar3_mask_reg_addr_byte1 == 24'd2121757
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_bar3_mask_reg_addr_byte2 == 24'd2121758
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_bar3_mask_reg_addr_byte3 == 24'd2121759
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_bar3_reg_addr_byte0 == 24'd24604
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_bar4_mask_reg_addr_byte0 == 24'd2121760
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_bar4_mask_reg_addr_byte1 == 24'd2121761
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_bar4_mask_reg_addr_byte2 == 24'd2121762
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_bar4_mask_reg_addr_byte3 == 24'd2121763
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_bar4_reg_addr_byte0 == 24'd24608
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_bar5_enable_reg_addr_byte0 == 24'd2121764
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_bar5_mask_reg_addr_byte0 == 24'd2121764
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_bar5_mask_reg_addr_byte1 == 24'd2121765
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_bar5_mask_reg_addr_byte2 == 24'd2121766
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_bar5_mask_reg_addr_byte3 == 24'd2121767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_bar5_reg_addr_byte0 == 24'd24612
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_bist_header_type_latency_cache_line_size_reg_addr_byte2 == 24'd8413198
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_cardbus_cis_ptr_reg_addr_byte0 == 24'd8413224
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_cardbus_cis_ptr_reg_addr_byte1 == 24'd8413225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_cardbus_cis_ptr_reg_addr_byte2 == 24'd8413226
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_cardbus_cis_ptr_reg_addr_byte3 == 24'd8413227
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_class_code_revision_id_addr_byte0 == 24'd8413192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_class_code_revision_id_addr_byte1 == 24'd8413193
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_class_code_revision_id_addr_byte2 == 24'd8413194
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_class_code_revision_id_addr_byte3 == 24'd8413195
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_device_id_vendor_id_reg_addr_byte0 == 24'd8413184
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_device_id_vendor_id_reg_addr_byte1 == 24'd8413185
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_device_id_vendor_id_reg_addr_byte2 == 24'd8413186
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_device_id_vendor_id_reg_addr_byte3 == 24'd8413187
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_exp_rom_bar_mask_reg_addr_byte0 == 24'd2121776
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_exp_rom_bar_mask_reg_addr_byte1 == 24'd2121777
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_exp_rom_bar_mask_reg_addr_byte2 == 24'd2121778
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_exp_rom_bar_mask_reg_addr_byte3 == 24'd2121779
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_exp_rom_base_addr_reg_addr_byte0 == 24'd24624
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_max_latency_min_grant_interrupt_pin_interrupt_line_reg_addr_byte1 == 24'd8413245
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_pci_cap_ptr_reg_addr_byte0 == 24'd8413236
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte0 == 24'd8413228
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte1 == 24'd8413229
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte2 == 24'd8413230
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte3 == 24'd8413231
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_vf_bar0_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_vf_bar1_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_vf_bar2_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_vf_bar3_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_vf_bar4_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_vf_bar5_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_vsecras_cap_rasdp_ext_hdr_off_addr_byte2 == 24'd8414206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_vsecras_cap_rasdp_ext_hdr_off_addr_byte3 == 24'd8414207
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_vsecras_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf6_vsecras_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_acs_cap_acs_at_block == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_acs_cap_acs_cap_hdr_reg_addr_byte2 == 24'd8418002
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_acs_cap_acs_cap_hdr_reg_addr_byte3 == 24'd8418003
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_acs_cap_acs_capalities_ctrl_reg_addr_byte0 == 24'd8418004
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_acs_cap_acs_capalities_ctrl_reg_addr_byte1 == 24'd29397
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_acs_cap_acs_direct_translated_p2p == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_acs_cap_acs_egress_ctrl_size == 8'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_acs_cap_acs_p2p_cpl_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_acs_cap_acs_p2p_egress_control == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_acs_cap_acs_p2p_req_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_acs_cap_acs_src_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_acs_cap_acs_usp_forwarding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_acs_cap_rsvdp_7 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_acs_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_acs_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_aer_cap_aer_ext_cap_hdr_off_addr_byte2 == 24'd8417538
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_aer_cap_aer_ext_cap_hdr_off_addr_byte3 == 24'd8417539
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_aer_cap_version == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_aer_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_ari_cap_ari_base_addr_byte2 == 24'd8417654
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_ari_cap_ari_base_addr_byte3 == 24'd8417655
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_ari_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_ari_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_ats_cap_ats_cap_hdr_reg_addr_byte2 == 24'd8417986
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_ats_cap_ats_cap_hdr_reg_addr_byte3 == 24'd8417987
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_ats_cap_ats_capabilities_ctrl_reg_addr_byte0 == 24'd8417988
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_ats_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_ats_capabilities_ctrl_reg_rsvdp_7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_ats_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_aux_curr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_bar0_mem_io == PF7_BAR0_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_bar0_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_bar0_type == PF7_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_bar1_mem_io == PF7_BAR1_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_bar1_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_bar1_type == PF7_BAR1_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_bar2_mem_io == PF7_BAR2_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_bar2_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_bar2_type == PF7_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_bar3_mem_io == PF7_BAR3_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_bar3_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_bar3_type == PF7_BAR3_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_bar4_mem_io == PF7_BAR4_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_bar4_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_bar4_type == PF7_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_bar5_mem_io == PF7_BAR5_MEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_bar5_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_bar5_type == PF7_BAR5_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_base_class_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_cap_id_nxt_ptr_reg_rsvdp_20 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_cap_pointer == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_cardbus_cis_pointer == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_con_status_reg_rsvdp_2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_con_status_reg_rsvdp_4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_d1_support == PF7_D1_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_d2_support == PF7_D2_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_10 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_11 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_12 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_13 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_14 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_15 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_16 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_17 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_18 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_19 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_20 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_21 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_22 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_23 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_24 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_25 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_26 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_27 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_28 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_29 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_30 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_31 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_32 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_33 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_34 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_35 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_36 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_37 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_38 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_39 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_40 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_41 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_42 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_43 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_44 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_45 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_46 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_47 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_48 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_49 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_50 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_51 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_52 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_53 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_54 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_55 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_56 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_57 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_58 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_59 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_6 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_60 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_61 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_62 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_63 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_64 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_65 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_7 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_8 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dbi_reserved_9 == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_device_capabilities_reg_rsvdp_12 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_device_capabilities_reg_rsvdp_16 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_device_capabilities_reg_rsvdp_29 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_dsi == PF7_NOT_REQUIRED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_exp_rom_bar_mask_reg_rsvdp_1 == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_exp_rom_base_addr_reg_rsvdp_1 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_global_inval_spprtd == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_header_type == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_int_pin == PF7_NO_INT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_invalidate_q_depth == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_link_capabilities_reg_rsvdp_23 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_link_control_link_status_reg_rsvdp_12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_link_control_link_status_reg_rsvdp_2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_link_control_link_status_reg_rsvdp_26 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_link_control_link_status_reg_rsvdp_9 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte1 == 24'd8417361
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte2 == 24'd8417362
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte3 == 24'd8417363
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_msi_cap_pci_msi_cap_id_next_ctrl_reg_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_msix_cap_msix_pba_offset_reg_addr_byte0 == 24'd8417464
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_msix_cap_msix_pba_offset_reg_addr_byte1 == 24'd8417465
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_msix_cap_msix_pba_offset_reg_addr_byte2 == 24'd8417466
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_msix_cap_msix_pba_offset_reg_addr_byte3 == 24'd8417467
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_msix_cap_msix_table_offset_reg_addr_byte0 == 24'd8417460
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_msix_cap_msix_table_offset_reg_addr_byte1 == 24'd8417461
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_msix_cap_msix_table_offset_reg_addr_byte2 == 24'd8417462
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_msix_cap_msix_table_offset_reg_addr_byte3 == 24'd8417463
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte1 == 24'd8417457
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte2 == 24'd8417458
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte3 == 24'd8417459
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte2 == 24'd10514610
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte3 == 24'd10514611
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_multi_func == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_no_soft_rst == PF7_INTERNALLY_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_page_aligned_req == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pasid_cap_execute_permission_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pasid_cap_max_pasid_width == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pasid_cap_pasid_cap_cntrl_reg_addr_byte0 == 24'd8418040
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pasid_cap_pasid_cap_cntrl_reg_addr_byte1 == 24'd8418041
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pasid_cap_pasid_ext_hdr_reg_addr_byte2 == 24'd8418038
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pasid_cap_pasid_ext_hdr_reg_addr_byte3 == 24'd8418039
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pasid_cap_privileged_mode_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pasid_cap_rsvdp_0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pasid_cap_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pasid_cap_rsvpd_13 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pasid_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pasid_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_msi_64_bit_addr_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_msi_cap_next_offset == 8'd112
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_msi_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_msi_ext_data_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_msi_ext_data_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_msi_multiple_msg_cap == PF7_MSI_VEC_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_msi_multiple_msg_en == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_msix_bir == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_msix_cap_id_next_ctrl_reg_rsvdp_27 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_msix_cap_next_offset == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_msix_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_msix_enable_vfcomm_cs2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_msix_function_mask == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_msix_function_mask_vfcomm_cs2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_msix_pba == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_msix_pba_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_msix_table_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_msix_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_msix_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_pvm_support == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_type0_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_type0_bar0_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_type0_bar1_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_type0_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_type0_bar1_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_type0_bar1_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_type0_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_type0_bar2_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_type0_bar3_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_type0_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_type0_bar3_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_type0_bar3_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_type0_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_type0_bar4_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_type0_bar5_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_type0_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_type0_bar5_enabled_or_mask64lsb == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_type0_bar5_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_type0_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pci_type0_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_active_state_link_pm_control == PF7_ASPM_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_active_state_link_pm_support == PF7_NO_ASPM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_aspm_opt_compliance == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_aux_power_pm_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_clock_power_man == PF7_REFCLK_REMOVE_NOT_OK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_common_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_device_capabilities_reg_addr_byte0 == 24'd8417396
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_device_capabilities_reg_addr_byte1 == 24'd8417397
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_device_capabilities_reg_addr_byte3 == 24'd8417399
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_device_control_device_status_addr_byte1 == 24'd8417401
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_dll_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_dll_active_rep_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_en_clk_power_man == PF7_CLKREQ_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_en_no_snoop == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_enter_compliance == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_ep_l0s_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_ep_l1_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_ext_tag_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_ext_tag_supp == PF7_NOT_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_extended_synch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_flr_cap == PF7_NOT_CAPABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_hw_auto_speed_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvd == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvdp_31 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_initiate_flr == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_l0s_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_l1_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_link_auto_bw_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_link_auto_bw_status == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_link_bw_man_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_link_bw_man_status == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_link_bw_not_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_link_capabilities_reg_addr_byte0 == 24'd8417404
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_link_capabilities_reg_addr_byte1 == 24'd8417405
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_link_capabilities_reg_addr_byte2 == 24'd8417406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_link_capabilities_reg_addr_byte3 == 24'd28799
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_link_control2_link_status2_reg_addr_byte0 == 24'd12611744
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_link_control_link_status_reg_addr_byte0 == 24'd4223104
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_link_control_link_status_reg_addr_byte1 == 24'd12611713
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_link_control_link_status_reg_addr_byte3 == 24'd4223107
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_link_disable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_link_training == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_max_link_speed == PF7_MAX_2P5GTS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_max_link_width == PF7_X1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_max_payload_size == PF7_PAYLOAD_128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_max_read_req_size == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_nego_link_width == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_next_ptr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte1 == 24'd8417393
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte3 == 24'd8417395
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_phantom_func_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_phantom_func_support == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_port_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_rcb == PF7_RCB_64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_retrain_link == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_role_based_err_report == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_sel_deemphasis == PF7_MINUS_6DB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_slot_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_surprise_down_err_rep_cap == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_target_link_speed == PF7_TRGT_GEN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_cap_tx_margin == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_int_msg_num == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pcie_slot_imp == PF7_NOT_IMPLEMENTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pf0_ari_device_number == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pf0_dbi_ro_wr_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pf0_default_target == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pf0_disable_auto_ltr_clr_msg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pf0_mask_ur_ca_4_trgt1 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pf0_misc_control_1_off_rsvdp_6 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pf0_port_logic_misc_control_1_off_addr_byte0 == 24'd2236
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pf0_simplified_replay_timer == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pf0_tlp_bypass_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pm_cap_cap_id_nxt_ptr_reg_addr_byte1 == 24'd8417345
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pm_cap_cap_id_nxt_ptr_reg_addr_byte2 == 24'd8417346
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pm_cap_cap_id_nxt_ptr_reg_addr_byte3 == 24'd8417347
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pm_cap_con_status_reg_addr_byte0 == 24'd8417348
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pm_next_pointer == 8'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pm_spec_ver == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pme_clk == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_pme_support == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_power_state == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_program_interface == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte2 == 24'd8418014
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte3 == 24'd8418015
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_prs_ext_cap_prs_req_capacity_reg_addr_byte0 == 24'd8418020
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_prs_ext_cap_prs_req_capacity_reg_addr_byte1 == 24'd8418021
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_prs_ext_cap_prs_req_capacity_reg_addr_byte2 == 24'd8418022
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_prs_ext_cap_prs_req_capacity_reg_addr_byte3 == 24'd8418023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_prs_ext_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_prs_ext_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_prs_outstanding_capacity == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_ras_des_cap_event_counter_ctrl_reg_addr_byte0 == 24'd29444
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_ras_des_cap_event_counter_ctrl_reg_g5_addr_byte3 == 24'd8418055
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_ras_des_cap_event_counter_ctrl_reg_g6_addr_byte3 == 24'd8418055
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_ras_des_cap_event_counter_ctrl_reg_g7_addr_byte3 == 24'd8418055
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_ras_des_cap_force_detect_lane == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_ras_des_cap_force_detect_lane_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_ras_des_cap_ras_des_hdr_reg_addr_byte2 == 24'd8418046
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_ras_des_cap_ras_des_hdr_reg_addr_byte3 == 24'd8418047
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_ras_des_cap_sd_control1_reg_addr_byte0 == 24'd8418204
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_ras_des_cap_sd_control1_reg_addr_byte1 == 24'd8418205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_ras_des_cap_sd_control1_reg_addr_byte2 == 24'd8418206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_ras_des_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_ras_des_event_counter_en == 8'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_ras_des_event_counter_event_select_g5 == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_ras_des_event_counter_event_select_g6 == 8'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_ras_des_event_counter_event_select_g7 == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_ras_des_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_10_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_11_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_12_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_13_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_14_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_15_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_16_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_17_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_18_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_19_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_20_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_21_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_22_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_23_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_24_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_25_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_26_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_27_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_28_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_29_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_30_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_31_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_32_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_33_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_34_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_35_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_36_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_37_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_38_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_39_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_40_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_41_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_42_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_43_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_44_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_45_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_46_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_47_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_48_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_49_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_50_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_51_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_52_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_53_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_54_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_55_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_56_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_57_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_58_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_59_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_60_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_61_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_62_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_63_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_64_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_65_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_7_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_8_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_reserved_9_addr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_revision_id == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_rom_bar_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_rom_bar_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_shadow_sriov_vf_stride_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sn_cap_ser_num_reg_dw_1_addr_byte0 == 24'd8417640
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sn_cap_ser_num_reg_dw_1_addr_byte1 == 24'd8417641
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sn_cap_ser_num_reg_dw_1_addr_byte2 == 24'd8417642
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sn_cap_ser_num_reg_dw_1_addr_byte3 == 24'd8417643
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sn_cap_ser_num_reg_dw_2_addr_byte0 == 24'd8417644
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sn_cap_ser_num_reg_dw_2_addr_byte1 == 24'd8417645
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sn_cap_ser_num_reg_dw_2_addr_byte2 == 24'd8417646
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sn_cap_ser_num_reg_dw_2_addr_byte3 == 24'd8417647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sn_cap_sn_base_addr_byte2 == 24'd8417638
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sn_cap_sn_base_addr_byte3 == 24'd8417639
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sn_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sn_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sn_ser_num_reg_1_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sn_ser_num_reg_2_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_shadow_sriov_initial_vfs_addr_byte0 == 24'd10514944
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_shadow_sriov_initial_vfs_addr_byte1 == 24'd10514945
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_shadow_sriov_vf_offset_position_addr_byte0 == 24'd10514952
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_shadow_sriov_vf_offset_position_addr_byte1 == 24'd10514953
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_shadow_sriov_vf_offset_position_addr_byte2 == 24'd10514954
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_shadow_sriov_vf_offset_position_addr_byte3 == 24'd10514955
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_shadow_vf_bar0_reg_addr_byte0 == 24'd2126360
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_shadow_vf_bar0_reg_addr_byte1 == 24'd2126361
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_shadow_vf_bar0_reg_addr_byte2 == 24'd2126362
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_shadow_vf_bar0_reg_addr_byte3 == 24'd2126363
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_shadow_vf_bar1_reg_addr_byte0 == 24'd2126364
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_shadow_vf_bar1_reg_addr_byte1 == 24'd2126365
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_shadow_vf_bar1_reg_addr_byte2 == 24'd2126366
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_shadow_vf_bar1_reg_addr_byte3 == 24'd2126367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_shadow_vf_bar2_reg_addr_byte0 == 24'd2126368
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_shadow_vf_bar2_reg_addr_byte1 == 24'd2126369
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_shadow_vf_bar2_reg_addr_byte2 == 24'd2126370
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_shadow_vf_bar2_reg_addr_byte3 == 24'd2126371
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_shadow_vf_bar3_reg_addr_byte0 == 24'd2126372
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_shadow_vf_bar3_reg_addr_byte1 == 24'd2126373
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_shadow_vf_bar3_reg_addr_byte2 == 24'd2126374
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_shadow_vf_bar3_reg_addr_byte3 == 24'd2126375
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_shadow_vf_bar4_reg_addr_byte0 == 24'd2126376
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_shadow_vf_bar4_reg_addr_byte1 == 24'd2126377
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_shadow_vf_bar4_reg_addr_byte2 == 24'd2126378
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_shadow_vf_bar4_reg_addr_byte3 == 24'd2126379
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_shadow_vf_bar5_reg_addr_byte0 == 24'd2126380
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_shadow_vf_bar5_reg_addr_byte1 == 24'd2126381
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_shadow_vf_bar5_reg_addr_byte2 == 24'd2126382
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_shadow_vf_bar5_reg_addr_byte3 == 24'd2126383
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_sriov_bar1_enable_reg_addr_byte0 == 24'd2126364
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_sriov_bar3_enable_reg_addr_byte0 == 24'd2126372
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_sriov_bar5_enable_reg_addr_byte0 == 24'd2126380
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_sriov_base_reg_addr_byte2 == 24'd8417782
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_sriov_base_reg_addr_byte3 == 24'd8417783
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_sriov_initial_vfs_addr_byte0 == 24'd8417792
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_sriov_initial_vfs_addr_byte1 == 24'd8417793
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_sriov_vf_offset_position_addr_byte0 == 24'd8417800
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_sriov_vf_offset_position_addr_byte1 == 24'd8417801
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_sriov_vf_offset_position_addr_byte2 == 24'd8417802
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_sriov_vf_offset_position_addr_byte3 == 24'd8417803
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_sup_page_sizes_reg_addr_byte0 == 24'd8417808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_sup_page_sizes_reg_addr_byte1 == 24'd8417809
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_sup_page_sizes_reg_addr_byte2 == 24'd8417810
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_sup_page_sizes_reg_addr_byte3 == 24'd8417811
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_vf_bar0_reg_addr_byte0 == 24'd29208
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_vf_bar1_reg_addr_byte0 == 24'd29212
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_vf_bar2_reg_addr_byte0 == 24'd29216
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_vf_bar3_reg_addr_byte0 == 24'd29220
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_vf_bar4_reg_addr_byte0 == 24'd29224
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_vf_bar5_reg_addr_byte0 == 24'd29228
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_vf_device_id_reg_addr_byte2 == 24'd8417806
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_cap_vf_device_id_reg_addr_byte3 == 24'd8417807
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_initial_vfs_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_initial_vfs_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_sup_page_size == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_vf_bar0_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_vf_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_vf_bar0_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_vf_bar0_type == PF7_SRIOV_VF_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_vf_bar1_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_vf_bar1_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_vf_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_vf_bar1_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_vf_bar1_type == PF7_SRIOV_VF_BAR1_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_vf_bar2_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_vf_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_vf_bar2_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_vf_bar2_type == PF7_SRIOV_VF_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_vf_bar3_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_vf_bar3_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_vf_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_vf_bar3_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_vf_bar3_type == PF7_SRIOV_VF_BAR3_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_vf_bar4_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_vf_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_vf_bar4_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_vf_bar4_type == PF7_SRIOV_VF_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_vf_bar5_dummy_mask_7_1 == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_vf_bar5_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_vf_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_vf_bar5_start == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_vf_bar5_type == PF7_SRIOV_VF_BAR5_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_vf_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_vf_offset_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_vf_offset_position_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_sriov_vf_stride_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_subclass_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_subsys_dev_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_subsys_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_tph_cap_tph_ext_cap_hdr_reg_addr_byte2 == 24'd8417846
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_tph_cap_tph_ext_cap_hdr_reg_addr_byte3 == 24'd8417847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_tph_cap_tph_req_cap_reg_addr_byte0 == 24'd8417848
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_tph_cap_tph_req_cap_reg_addr_byte1 == 24'd8417849
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_tph_cap_tph_req_cap_reg_addr_byte2 == 24'd8417850
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_tph_cap_tph_req_cap_reg_addr_byte3 == 24'd8417851
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte0 == 24'd10515000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte1 == 24'd10515001
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte2 == 24'd10515002
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte3 == 24'd10515003
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_tph_req_cap_int_vec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_tph_req_cap_int_vec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_tph_req_cap_reg_rsvdp_11 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_tph_req_cap_reg_rsvdp_27 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_tph_req_cap_reg_rsvdp_3 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_tph_req_cap_reg_vfcomm_cs2_rsvdp_11_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_tph_req_cap_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_tph_req_cap_reg_vfcomm_cs2_rsvdp_3_vfcomm_cs2 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_tph_req_cap_st_table_loc_0 == PF7_NOT_IN_TPH_STRUCT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_tph_req_cap_st_table_loc_0_vfcomm_cs2 == PF7_NOT_IN_TPH_STRUCT_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_tph_req_cap_st_table_loc_1 == PF7_NOT_IN_MSIX_TABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_tph_req_cap_st_table_loc_1_vfcomm_cs2 == PF7_NOT_IN_MSIX_TABLE_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_tph_req_cap_st_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_tph_req_cap_st_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_tph_req_cap_ver == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_tph_req_device_spec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_tph_req_device_spec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_tph_req_extended_tph == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_tph_req_extended_tph_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_tph_req_next_ptr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_tph_req_no_st_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_tph_req_no_st_mode_vfcomm_cs2 == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_bar0_mask_reg_addr_byte0 == 24'd2125840
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_bar0_mask_reg_addr_byte1 == 24'd2125841
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_bar0_mask_reg_addr_byte2 == 24'd2125842
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_bar0_mask_reg_addr_byte3 == 24'd2125843
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_bar0_reg_addr_byte0 == 24'd28688
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_bar1_enable_reg_addr_byte0 == 24'd2125844
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_bar1_mask_reg_addr_byte0 == 24'd2125844
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_bar1_mask_reg_addr_byte1 == 24'd2125845
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_bar1_mask_reg_addr_byte2 == 24'd2125846
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_bar1_mask_reg_addr_byte3 == 24'd2125847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_bar1_reg_addr_byte0 == 24'd28692
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_bar2_mask_reg_addr_byte0 == 24'd2125848
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_bar2_mask_reg_addr_byte1 == 24'd2125849
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_bar2_mask_reg_addr_byte2 == 24'd2125850
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_bar2_mask_reg_addr_byte3 == 24'd2125851
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_bar2_reg_addr_byte0 == 24'd28696
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_bar3_enable_reg_addr_byte0 == 24'd2125852
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_bar3_mask_reg_addr_byte0 == 24'd2125852
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_bar3_mask_reg_addr_byte1 == 24'd2125853
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_bar3_mask_reg_addr_byte2 == 24'd2125854
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_bar3_mask_reg_addr_byte3 == 24'd2125855
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_bar3_reg_addr_byte0 == 24'd28700
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_bar4_mask_reg_addr_byte0 == 24'd2125856
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_bar4_mask_reg_addr_byte1 == 24'd2125857
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_bar4_mask_reg_addr_byte2 == 24'd2125858
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_bar4_mask_reg_addr_byte3 == 24'd2125859
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_bar4_reg_addr_byte0 == 24'd28704
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_bar5_enable_reg_addr_byte0 == 24'd2125860
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_bar5_mask_reg_addr_byte0 == 24'd2125860
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_bar5_mask_reg_addr_byte1 == 24'd2125861
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_bar5_mask_reg_addr_byte2 == 24'd2125862
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_bar5_mask_reg_addr_byte3 == 24'd2125863
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_bar5_reg_addr_byte0 == 24'd28708
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_bist_header_type_latency_cache_line_size_reg_addr_byte2 == 24'd8417294
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_cardbus_cis_ptr_reg_addr_byte0 == 24'd8417320
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_cardbus_cis_ptr_reg_addr_byte1 == 24'd8417321
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_cardbus_cis_ptr_reg_addr_byte2 == 24'd8417322
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_cardbus_cis_ptr_reg_addr_byte3 == 24'd8417323
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_class_code_revision_id_addr_byte0 == 24'd8417288
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_class_code_revision_id_addr_byte1 == 24'd8417289
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_class_code_revision_id_addr_byte2 == 24'd8417290
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_class_code_revision_id_addr_byte3 == 24'd8417291
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_device_id_vendor_id_reg_addr_byte0 == 24'd8417280
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_device_id_vendor_id_reg_addr_byte1 == 24'd8417281
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_device_id_vendor_id_reg_addr_byte2 == 24'd8417282
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_device_id_vendor_id_reg_addr_byte3 == 24'd8417283
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_exp_rom_bar_mask_reg_addr_byte0 == 24'd2125872
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_exp_rom_bar_mask_reg_addr_byte1 == 24'd2125873
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_exp_rom_bar_mask_reg_addr_byte2 == 24'd2125874
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_exp_rom_bar_mask_reg_addr_byte3 == 24'd2125875
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_exp_rom_base_addr_reg_addr_byte0 == 24'd28720
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_max_latency_min_grant_interrupt_pin_interrupt_line_reg_addr_byte1 == 24'd8417341
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_pci_cap_ptr_reg_addr_byte0 == 24'd8417332
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte0 == 24'd8417324
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte1 == 24'd8417325
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte2 == 24'd8417326
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte3 == 24'd8417327
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_vf_bar0_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_vf_bar1_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_vf_bar2_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_vf_bar3_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_vf_bar4_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_vf_bar5_reg_rsvdp_0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_vsecras_cap_rasdp_ext_hdr_off_addr_byte2 == 24'd8418302
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_vsecras_cap_rasdp_ext_hdr_off_addr_byte3 == 24'd8418303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_vsecras_cap_version == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf7_vsecras_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pld_aib_loopback_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pld_clk_dis == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pld_crs_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pld_tx_fifo_dyn_empty_dis == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pldif_fifo_clk_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.rstctl_timer_a == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.rstctl_timer_b == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.rx_lane_flip_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.rxbuf_limit_bypass == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.rxbuf_limit_init == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.rxbuf_pfull_th == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.shadow_select == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.sriov_clk_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.sris_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.test_in_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.tx_cdts_rst == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.tx_fifo_empty_threshold_1 == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.tx_fifo_empty_threshold_2 == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.tx_fifo_empty_threshold_3 == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.tx_fifo_empty_threshold_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.tx_fifo_full_threshold == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.tx_lane_flip_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.user_mode_del_count == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.vf == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.vf_select == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_drop_vendor0_msg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_drop_vendor1_msg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_ep_native == NATIVE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_ip_port_num == PCIE_PORT1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_link_rate == GEN1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_link_width == X1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_maxpayload_size == MAX_PAYLOAD_128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_num_of_lanes == NUM_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_bar1_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_bar3_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_bar5_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_dlink_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_exvf_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_exvf_aricap_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_exvf_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_exvf_msix_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_exvf_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_exvf_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_io_decode == IO32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_ltr_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_margin_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_msi_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_msix_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_pb_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_pl16g_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_prefetch_decode == PREF64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_sn_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_sriov_num_vf_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_sriov_num_vf_non_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_sriov_vf_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_sriov_vf_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_sriov_vf_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_user_vsec_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf0_vsecras_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf1_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf1_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf1_bar1_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf1_bar3_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf1_bar5_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf1_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf1_exvf_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf1_exvf_aricap_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf1_exvf_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf1_exvf_msix_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf1_exvf_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf1_exvf_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf1_msi_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf1_msix_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf1_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf1_pb_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf1_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf1_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf1_sn_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf1_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf1_sriov_num_vf_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf1_sriov_num_vf_non_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf1_sriov_vf_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf1_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf1_sriov_vf_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf1_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf1_sriov_vf_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf1_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf1_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf1_user_vsec_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf1_user_vsec_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf1_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf1_vsecras_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf2_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf2_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf2_bar1_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf2_bar3_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf2_bar5_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf2_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf2_exvf_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf2_exvf_aricap_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf2_exvf_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf2_exvf_msix_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf2_exvf_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf2_exvf_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf2_msi_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf2_msix_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf2_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf2_pb_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf2_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf2_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf2_sn_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf2_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf2_sriov_num_vf_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf2_sriov_num_vf_non_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf2_sriov_vf_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf2_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf2_sriov_vf_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf2_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf2_sriov_vf_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf2_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf2_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf2_user_vsec_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf2_user_vsec_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf2_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf2_vsecras_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf3_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf3_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf3_bar1_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf3_bar3_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf3_bar5_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf3_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf3_exvf_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf3_exvf_aricap_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf3_exvf_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf3_exvf_msix_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf3_exvf_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf3_exvf_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf3_msi_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf3_msix_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf3_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf3_pb_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf3_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf3_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf3_sn_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf3_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf3_sriov_num_vf_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf3_sriov_num_vf_non_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf3_sriov_vf_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf3_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf3_sriov_vf_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf3_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf3_sriov_vf_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf3_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf3_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf3_user_vsec_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf3_user_vsec_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf3_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf3_vsecras_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf4_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf4_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf4_bar1_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf4_bar3_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf4_bar5_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf4_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf4_exvf_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf4_exvf_aricap_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf4_exvf_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf4_exvf_msix_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf4_exvf_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf4_exvf_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf4_msi_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf4_msix_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf4_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf4_pb_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf4_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf4_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf4_sn_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf4_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf4_sriov_num_vf_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf4_sriov_num_vf_non_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf4_sriov_vf_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf4_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf4_sriov_vf_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf4_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf4_sriov_vf_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf4_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf4_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf4_user_vsec_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf4_user_vsec_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf4_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf4_vsecras_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf5_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf5_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf5_bar1_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf5_bar3_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf5_bar5_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf5_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf5_exvf_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf5_exvf_aricap_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf5_exvf_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf5_exvf_msix_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf5_exvf_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf5_exvf_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf5_msi_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf5_msix_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf5_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf5_pb_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf5_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf5_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf5_sn_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf5_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf5_sriov_num_vf_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf5_sriov_num_vf_non_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf5_sriov_vf_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf5_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf5_sriov_vf_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf5_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf5_sriov_vf_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf5_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf5_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf5_user_vsec_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf5_user_vsec_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf5_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf5_vsecras_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf6_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf6_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf6_bar1_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf6_bar3_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf6_bar5_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf6_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf6_exvf_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf6_exvf_aricap_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf6_exvf_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf6_exvf_msix_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf6_exvf_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf6_exvf_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf6_msi_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf6_msix_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf6_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf6_pb_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf6_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf6_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf6_sn_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf6_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf6_sriov_num_vf_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf6_sriov_num_vf_non_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf6_sriov_vf_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf6_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf6_sriov_vf_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf6_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf6_sriov_vf_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf6_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf6_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf6_user_vsec_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf6_user_vsec_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf6_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf6_vsecras_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf7_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf7_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf7_bar1_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf7_bar3_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf7_bar5_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf7_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf7_exvf_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf7_exvf_aricap_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf7_exvf_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf7_exvf_msix_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf7_exvf_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf7_exvf_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf7_msi_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf7_msix_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf7_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf7_pb_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf7_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf7_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf7_sn_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf7_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf7_sriov_num_vf_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf7_sriov_num_vf_non_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf7_sriov_vf_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf7_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf7_sriov_vf_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf7_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf7_sriov_vf_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf7_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf7_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf7_user_vsec_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf7_user_vsec_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf7_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pf7_vsecras_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_phase23_txpreset == PRESET0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_phase23_txpreset_atg4 == GEN4_PRESET0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_pldclk_rate == SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_ptm_autoupdate == AUTOUPDATE_10MS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_ptm_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_rp_ep_mode == EP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_tlp_bypass_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.virtual_txeq_mode == EQ_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.vsec_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.vsec_select == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.wait_pld_warm_rst_rdy == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.dfd_ctrl_ctop_bitsync_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.dfd_ctrl_ctop_clk_gate_en_attr == DFD_CTRL_CTOP_CLK_GATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.dfd_ctrl_ctop_clock_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.dfd_ctrl_ctop_data_sel_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.dfd_ctrl_ctop_rst_n_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.dfd_ctrl_ctop_stream0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.dfd_ctrl_ctop_stream1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.dfd_ctrl_ctop_stream2_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.dfd_ctrl_ctop_stream3_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.dfd_ctrl_ctop_trig_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.dfd_status_ctop_e_ctrl_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.ecc_ctrl_bypass_ecc_all_aib_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.ecc_ctrl_clr_stat_n_attr == ECC_CTRL_CLR_STAT_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.ecc_ctrl_ecc_mask_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.ecc_ctrl_ecc_spare_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.mailbox_in_msg_attr == 30'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.mailbox_in_send_msg_attr == MAILBOX_IN_SEND_MSG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.mailbox_out_msg_attr == 30'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.mailbox_out_new_msg_attr == MAILBOX_OUT_NEW_MSG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.pctrl_lane_x16_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.pctrl_lane_x4_0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.pctrl_lane_x4_1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.pctrl_lane_x8_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.pctrl_port_x16_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.pctrl_port_x4_0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.pctrl_port_x4_1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.pctrl_port_x8_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.pctrl_rate_x16_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.pctrl_rate_x4_0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.pctrl_rate_x4_1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.pctrl_rate_x8_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.pctrl_spare_x16_attr == PCTRL_SPARE_X16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.pctrl_spare_x4_0_attr == PCTRL_SPARE_X4_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.pctrl_spare_x4_1_attr == PCTRL_SPARE_X4_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.pctrl_spare_x8_attr == PCTRL_SPARE_X8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_arb_ctrl_k_hrc_arb_disable_attr == R_HRC_ARB_CTRL_K_HRC_ARB_DISABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_arb_ctrl_k_hrc_arb_num_active_ip_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_arb_ctrl_k_hrc_arb_timeslot_interval_attr == 16'd243
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_arb_sel_k_hrc_arb_sel_ip0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_arb_sel_k_hrc_arb_sel_ip1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_arb_sel_k_hrc_arb_sel_ip2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_arb_sel_k_hrc_arb_sel_ip3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_arb_sel_k_hrc_arb_sel_ip4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_bp_ctrl_x16_bypass_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_bp_ctrl_x16_platform_rst_req_attr == R_HRC_BP_CTRL_X16_PLATFORM_RST_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_bp_ctrl_x16_rst_cold_n_attr == R_HRC_BP_CTRL_X16_RST_COLD_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_bp_ctrl_x16_rst_n_attr == R_HRC_BP_CTRL_X16_RST_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_bp_ctrl_x16_rst_perst_n_attr == R_HRC_BP_CTRL_X16_RST_PERST_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_bp_ctrl_x16_rst_pldclrhip_n_attr == R_HRC_BP_CTRL_X16_RST_PLDCLRHIP_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_bp_ctrl_x4_0_bypass_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_bp_ctrl_x4_0_platform_rst_req_attr == R_HRC_BP_CTRL_X4_0_PLATFORM_RST_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_bp_ctrl_x4_0_rst_cold_n_attr == R_HRC_BP_CTRL_X4_0_RST_COLD_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_bp_ctrl_x4_0_rst_n_attr == R_HRC_BP_CTRL_X4_0_RST_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_bp_ctrl_x4_0_rst_perst_n_attr == R_HRC_BP_CTRL_X4_0_RST_PERST_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_bp_ctrl_x4_0_rst_pldclrhip_n_attr == R_HRC_BP_CTRL_X4_0_RST_PLDCLRHIP_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_bp_ctrl_x4_1_bypass_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_bp_ctrl_x4_1_platform_rst_req_attr == R_HRC_BP_CTRL_X4_1_PLATFORM_RST_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_bp_ctrl_x4_1_rst_cold_n_attr == R_HRC_BP_CTRL_X4_1_RST_COLD_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_bp_ctrl_x4_1_rst_n_attr == R_HRC_BP_CTRL_X4_1_RST_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_bp_ctrl_x4_1_rst_perst_n_attr == R_HRC_BP_CTRL_X4_1_RST_PERST_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_bp_ctrl_x4_1_rst_pldclrhip_n_attr == R_HRC_BP_CTRL_X4_1_RST_PLDCLRHIP_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_bp_ctrl_x8_bypass_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_bp_ctrl_x8_platform_rst_req_attr == R_HRC_BP_CTRL_X8_PLATFORM_RST_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_bp_ctrl_x8_rst_cold_n_attr == R_HRC_BP_CTRL_X8_RST_COLD_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_bp_ctrl_x8_rst_n_attr == R_HRC_BP_CTRL_X8_RST_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_bp_ctrl_x8_rst_perst_n_attr == R_HRC_BP_CTRL_X8_RST_PERST_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_bp_ctrl_x8_rst_pldclrhip_n_attr == R_HRC_BP_CTRL_X8_RST_PLDCLRHIP_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_bp_pcs_ctrl_pipeb_a_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_bp_pcs_ctrl_por_b_a_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_bypass_irq_status_attr == R_HRC_BYPASS_IRQ_STATUS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_dfd_sel_k_hrc_dfd_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_irq_mask_k_hrc_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_perst_ctrl_k_hrc_perst_hi_filt_time_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_perst_ctrl_k_hrc_perst_lo_filt_time_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_phy_rst_ctrl_k_hrc_cold_reset_time_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_phy_rst_ctrl_k_hrc_phy_warm_rst_width_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_phy_rst_time_k_hrc_phy_lane_rst_width_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_phy_rst_time_k_hrc_phy_post_phy_rst_quiet_time_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_phy_time_ctrl_k_hrc_phy_post_creg_quiet_time_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_phy_time_ctrl_k_hrc_phy_post_lane_rst_quiet_time_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_pll_ctrl_k_hrc_cpll_lock_time_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_pll_ctrl_k_hrc_cpll_reset_time_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_pll_time_ctrl_k_hrc_cpll_post_rls_quiet_time_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_pll_time_ctrl_k_hrc_cpll_post_rst_quiet_time_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_rst_ctrl_k_hrc_core_rst_width_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_rst_ctrl_k_hrc_cpll_ena_warm_reset_attr == R_HRC_RST_CTRL_K_HRC_CPLL_ENA_WARM_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_rst_ctrl_k_hrc_dis_chk_cpll_lock_attr == R_HRC_RST_CTRL_K_HRC_DIS_CHK_CPLL_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_rst_ctrl_k_hrc_dis_phystat_chk_4_partial_rst_attr == R_HRC_RST_CTRL_K_HRC_DIS_PHYSTAT_CHK_4_PARTIAL_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_rst_ctrl_k_hrc_link_req_is_full_rst_attr == R_HRC_RST_CTRL_K_HRC_LINK_REQ_IS_FULL_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_rst_ctrl_k_hrc_link_req_is_partial_rst_attr == R_HRC_RST_CTRL_K_HRC_LINK_REQ_IS_PARTIAL_RST_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_rst_ctrl_k_hrc_pin_perst_is_full_rst_attr == R_HRC_RST_CTRL_K_HRC_PIN_PERST_IS_FULL_RST_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_rst_time_ctrl_k_hrc_post_core_rst_quiet_time_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_rst_time_ctrl_k_hrc_warm_rst_timeout_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_stagger_ctrl_k_hrc_lane_stagger_disable_attr == R_HRC_STAGGER_CTRL_K_HRC_LANE_STAGGER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_stagger_ctrl_k_hrc_lane_stagger_interval_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_stagger_ctrl_k_hrc_phy_stagger_disable_attr == R_HRC_STAGGER_CTRL_K_HRC_PHY_STAGGER_DISABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_stagger_ctrl_k_hrc_phy_stagger_interval_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_top_ctrl_k_hotrst_act_mute_perstn_attr == R_HRC_TOP_CTRL_K_HOTRST_ACT_MUTE_PERSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_top_ctrl_k_hrc_byp_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_top_ctrl_k_hrc_dw16_perstn_disable_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_top_ctrl_k_hrc_dw16_perstn_overwrite_attr == R_HRC_TOP_CTRL_K_HRC_DW16_PERSTN_OVERWRITE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_top_ctrl_k_hrc_dw16_perstn_overwrite_shadow_attr == R_HRC_TOP_CTRL_K_HRC_DW16_PERSTN_OVERWRITE_SHADOW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_top_ctrl_k_hrc_dw40_perstn_disable_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_top_ctrl_k_hrc_dw40_perstn_overwrite_attr == R_HRC_TOP_CTRL_K_HRC_DW40_PERSTN_OVERWRITE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_top_ctrl_k_hrc_dw40_perstn_overwrite_shadow_attr == R_HRC_TOP_CTRL_K_HRC_DW40_PERSTN_OVERWRITE_SHADOW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_top_ctrl_k_hrc_dw41_perstn_disable_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_top_ctrl_k_hrc_dw41_perstn_overwrite_attr == R_HRC_TOP_CTRL_K_HRC_DW41_PERSTN_OVERWRITE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_top_ctrl_k_hrc_dw41_perstn_overwrite_shadow_attr == R_HRC_TOP_CTRL_K_HRC_DW41_PERSTN_OVERWRITE_SHADOW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_top_ctrl_k_hrc_dw8_perstn_disable_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_top_ctrl_k_hrc_dw8_perstn_overwrite_attr == R_HRC_TOP_CTRL_K_HRC_DW8_PERSTN_OVERWRITE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_top_ctrl_k_hrc_dw8_perstn_overwrite_shadow_attr == R_HRC_TOP_CTRL_K_HRC_DW8_PERSTN_OVERWRITE_SHADOW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_top_ctrl_k_hrc_extended_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_top_ctrl_k_hrc_ip_ena_vec_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.r_hrc_top_ctrl_k_hrc_topology_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.sctrl_clk_gate_en_attr == SCTRL_CLK_GATE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.sctrl_pll_mux_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.sctrl_spare_attr == SCTRL_SPARE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.sctrl_x16_attr == 8'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.sctrl_x4_0_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.sctrl_x4_1_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.sctrl_x8_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ctop.ub_ctrltop.topology == DISABLED_SYSTEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_d0_sclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_d1_sclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_d2_sclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_d3_sclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_d4_sclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_d5_sclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_d6_sclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_d7_sclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u0_pma_internal_clk1_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u0_pma_internal_clk2_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u0_standalonecoreclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u0_xcvr_quad_refclk1_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u0_xcvr_quad_refclk2_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u1_pma_internal_clk1_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u1_pma_internal_clk2_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u1_standalonecoreclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u1_xcvr_quad_refclk1_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u1_xcvr_quad_refclk2_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u2_pma_internal_clk1_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u2_pma_internal_clk2_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u2_standalonecoreclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u2_xcvr_quad_refclk1_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u2_xcvr_quad_refclk2_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u3_pma_internal_clk1_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u3_pma_internal_clk2_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u3_standalonecoreclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u3_xcvr_quad_refclk1_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u3_xcvr_quad_refclk2_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u4_pma_internal_clk1_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u4_pma_internal_clk2_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u4_standalonecoreclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u4_xcvr_quad_refclk1_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u4_xcvr_quad_refclk2_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u5_pma_internal_clk1_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u5_pma_internal_clk2_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u5_standalonecoreclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u5_xcvr_quad_refclk1_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u5_xcvr_quad_refclk2_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u6_pma_internal_clk1_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u6_pma_internal_clk2_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u6_standalonecoreclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u6_xcvr_quad_refclk1_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u6_xcvr_quad_refclk2_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u7_pma_internal_clk1_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u7_pma_internal_clk2_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u7_standalonecoreclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u7_xcvr_quad_refclk1_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.i_ft_u7_xcvr_quad_refclk2_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d0_pma_internal_clk1_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d0_pma_internal_clk2_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d0_standalonecoreclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d0_xcvr_quad_refclk1_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d0_xcvr_quad_refclk2_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d1_pma_internal_clk1_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d1_pma_internal_clk2_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d1_standalonecoreclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d1_xcvr_quad_refclk1_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d1_xcvr_quad_refclk2_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d2_pma_internal_clk1_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d2_pma_internal_clk2_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d2_standalonecoreclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d2_xcvr_quad_refclk1_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d2_xcvr_quad_refclk2_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d3_pma_internal_clk1_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d3_pma_internal_clk2_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d3_standalonecoreclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d3_xcvr_quad_refclk1_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d3_xcvr_quad_refclk2_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d4_pma_internal_clk1_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d4_pma_internal_clk2_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d4_standalonecoreclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d4_xcvr_quad_refclk1_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d4_xcvr_quad_refclk2_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d5_pma_internal_clk1_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d5_pma_internal_clk2_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d5_standalonecoreclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d5_xcvr_quad_refclk1_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d5_xcvr_quad_refclk2_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d6_pma_internal_clk1_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d6_pma_internal_clk2_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d6_standalonecoreclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d6_xcvr_quad_refclk1_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d6_xcvr_quad_refclk2_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d7_pma_internal_clk1_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d7_pma_internal_clk2_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d7_standalonecoreclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d7_xcvr_quad_refclk1_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_d7_xcvr_quad_refclk2_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_u0_sclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_u1_sclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_u2_sclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_u3_sclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_u4_sclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_u5_sclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_u6_sclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.o_ft_u7_sclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_cfg_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_core_x16_l0_pclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_core_x4_l12_pclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_core_x4_l4_pclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_core_x8_l8_pclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma0_pclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma0_ref_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma0_rxclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma0_syntha_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma0_synthb_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma10_pclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma10_ref_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma10_rxclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma10_syntha_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma10_synthb_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma11_pclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma11_ref_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma11_rxclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma11_syntha_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma11_synthb_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma12_pclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma12_ref_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma12_rxclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma12_syntha_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma12_synthb_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma13_pclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma13_ref_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma13_rxclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma13_syntha_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma13_synthb_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma14_pclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma14_ref_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma14_rxclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma14_syntha_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma14_synthb_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma15_pclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma15_ref_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma15_rxclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma15_syntha_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma15_synthb_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma1_pclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma1_ref_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma1_rxclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma1_syntha_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma1_synthb_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma2_pclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma2_ref_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma2_rxclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma2_syntha_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma2_synthb_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma3_pclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma3_ref_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma3_rxclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma3_syntha_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma3_synthb_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma4_pclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma4_ref_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma4_rxclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma4_syntha_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma4_synthb_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma5_pclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma5_ref_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma5_rxclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma5_syntha_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma5_synthb_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma6_pclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma6_ref_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma6_rxclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma6_syntha_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma6_synthb_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma7_pclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma7_ref_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma7_rxclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma7_syntha_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma7_synthb_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma8_pclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma8_ref_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma8_rxclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma8_syntha_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma8_synthb_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma9_pclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma9_ref_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma9_rxclk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma9_syntha_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.pcie_ptop_pma9_synthb_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.powermode_ac == PCIEMODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.powermode_ac_global_avmm == GLOBAL_AVMM_ON
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.powermode_dc == POWERUP_DC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.powermode_freq_hz_pcie_ptop_global_avmm == 37'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.powermode_freq_hz_pcie_ptop_pipe0_pclk == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.powermode_freq_hz_pcie_ptop_pipe10_pclk == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.powermode_freq_hz_pcie_ptop_pipe11_pclk == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.powermode_freq_hz_pcie_ptop_pipe12_pclk == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.powermode_freq_hz_pcie_ptop_pipe13_pclk == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.powermode_freq_hz_pcie_ptop_pipe14_pclk == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.powermode_freq_hz_pcie_ptop_pipe15_pclk == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.powermode_freq_hz_pcie_ptop_pipe1_pclk == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.powermode_freq_hz_pcie_ptop_pipe2_pclk == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.powermode_freq_hz_pcie_ptop_pipe3_pclk == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.powermode_freq_hz_pcie_ptop_pipe4_pclk == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.powermode_freq_hz_pcie_ptop_pipe5_pclk == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.powermode_freq_hz_pcie_ptop_pipe6_pclk == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.powermode_freq_hz_pcie_ptop_pipe7_pclk == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.powermode_freq_hz_pcie_ptop_pipe8_pclk == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.powermode_freq_hz_pcie_ptop_pipe9_pclk == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.topology == DISABLED_SYSTEM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.virtual_dwip_x16_negociated_speed == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.virtual_dwip_x4_0_negociated_speed == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.virtual_dwip_x4_1_negociated_speed == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.virtual_dwip_x8_negociated_speed == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.virtual_port_type == EP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.virtual_sris_enable == DISABLE_SRIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.virtual_tlp_bypass_en == DISABLE_TLBP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane0.dctrl_dfd_bsync_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane0.dctrl_dfd_datasel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane0.dctrl_dfd_power_off_attr == DCTRL_DFD_POWER_OFF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane0.dctrl_dfd_primary_attr == DCTRL_DFD_PRIMARY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane0.dctrl_dfd_secondary_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane0.lctrl_lane_mode_ctrl_attr == LCTRL_LANE_MODE_PCIE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane0.lctrl_lane_mode_sel_attr == LCTRL_LANE_MODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane0.pctrl_lowpin_nt_attr == PCTRL_LOWPIN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane0.pctrl_pclkchangeack_attr == PCTRL_PCLKCHANGEACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane0.pctrl_phy_mode_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane0.pctrl_rxelecidle_disable_a_attr == PCTRL_RXELECIDLE_DISABLE_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane0.pctrl_rxeqclr_attr == PCTRL_RXEQCLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane0.pctrl_rxeqtraining_attr == PCTRL_RXEQTRAINING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane0.pctrl_rxtermination_attr == PCTRL_RXTERMINATION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane0.pctrl_srisenable_attr == PCTRL_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane0.pctrl_txcmnmode_disable_a_attr == PCTRL_TXCMNMODE_DISABLE_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane0.pctrl_txoneszeros_attr == PCTRL_TXONESZEROS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane1.dctrl_dfd_bsync_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane1.dctrl_dfd_datasel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane1.dctrl_dfd_power_off_attr == DCTRL_DFD_POWER_OFF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane1.dctrl_dfd_primary_attr == DCTRL_DFD_PRIMARY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane1.dctrl_dfd_secondary_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane1.lctrl_lane_mode_ctrl_attr == LCTRL_LANE_MODE_PCIE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane1.lctrl_lane_mode_sel_attr == LCTRL_LANE_MODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane1.pctrl_lowpin_nt_attr == PCTRL_LOWPIN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane1.pctrl_pclkchangeack_attr == PCTRL_PCLKCHANGEACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane1.pctrl_phy_mode_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane1.pctrl_rxelecidle_disable_a_attr == PCTRL_RXELECIDLE_DISABLE_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane1.pctrl_rxeqclr_attr == PCTRL_RXEQCLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane1.pctrl_rxeqtraining_attr == PCTRL_RXEQTRAINING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane1.pctrl_rxtermination_attr == PCTRL_RXTERMINATION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane1.pctrl_srisenable_attr == PCTRL_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane1.pctrl_txcmnmode_disable_a_attr == PCTRL_TXCMNMODE_DISABLE_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane1.pctrl_txoneszeros_attr == PCTRL_TXONESZEROS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane10.dctrl_dfd_bsync_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane10.dctrl_dfd_datasel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane10.dctrl_dfd_power_off_attr == DCTRL_DFD_POWER_OFF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane10.dctrl_dfd_primary_attr == DCTRL_DFD_PRIMARY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane10.dctrl_dfd_secondary_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane10.lctrl_lane_mode_ctrl_attr == LCTRL_LANE_MODE_PCIE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane10.lctrl_lane_mode_sel_attr == LCTRL_LANE_MODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane10.pctrl_lowpin_nt_attr == PCTRL_LOWPIN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane10.pctrl_pclkchangeack_attr == PCTRL_PCLKCHANGEACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane10.pctrl_phy_mode_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane10.pctrl_rxelecidle_disable_a_attr == PCTRL_RXELECIDLE_DISABLE_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane10.pctrl_rxeqclr_attr == PCTRL_RXEQCLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane10.pctrl_rxeqtraining_attr == PCTRL_RXEQTRAINING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane10.pctrl_rxtermination_attr == PCTRL_RXTERMINATION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane10.pctrl_srisenable_attr == PCTRL_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane10.pctrl_txcmnmode_disable_a_attr == PCTRL_TXCMNMODE_DISABLE_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane10.pctrl_txoneszeros_attr == PCTRL_TXONESZEROS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane11.dctrl_dfd_bsync_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane11.dctrl_dfd_datasel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane11.dctrl_dfd_power_off_attr == DCTRL_DFD_POWER_OFF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane11.dctrl_dfd_primary_attr == DCTRL_DFD_PRIMARY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane11.dctrl_dfd_secondary_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane11.lctrl_lane_mode_ctrl_attr == LCTRL_LANE_MODE_PCIE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane11.lctrl_lane_mode_sel_attr == LCTRL_LANE_MODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane11.pctrl_lowpin_nt_attr == PCTRL_LOWPIN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane11.pctrl_pclkchangeack_attr == PCTRL_PCLKCHANGEACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane11.pctrl_phy_mode_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane11.pctrl_rxelecidle_disable_a_attr == PCTRL_RXELECIDLE_DISABLE_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane11.pctrl_rxeqclr_attr == PCTRL_RXEQCLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane11.pctrl_rxeqtraining_attr == PCTRL_RXEQTRAINING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane11.pctrl_rxtermination_attr == PCTRL_RXTERMINATION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane11.pctrl_srisenable_attr == PCTRL_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane11.pctrl_txcmnmode_disable_a_attr == PCTRL_TXCMNMODE_DISABLE_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane11.pctrl_txoneszeros_attr == PCTRL_TXONESZEROS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane12.dctrl_dfd_bsync_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane12.dctrl_dfd_datasel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane12.dctrl_dfd_power_off_attr == DCTRL_DFD_POWER_OFF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane12.dctrl_dfd_primary_attr == DCTRL_DFD_PRIMARY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane12.dctrl_dfd_secondary_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane12.lctrl_lane_mode_ctrl_attr == LCTRL_LANE_MODE_PCIE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane12.lctrl_lane_mode_sel_attr == LCTRL_LANE_MODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane12.pctrl_lowpin_nt_attr == PCTRL_LOWPIN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane12.pctrl_pclkchangeack_attr == PCTRL_PCLKCHANGEACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane12.pctrl_phy_mode_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane12.pctrl_rxelecidle_disable_a_attr == PCTRL_RXELECIDLE_DISABLE_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane12.pctrl_rxeqclr_attr == PCTRL_RXEQCLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane12.pctrl_rxeqtraining_attr == PCTRL_RXEQTRAINING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane12.pctrl_rxtermination_attr == PCTRL_RXTERMINATION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane12.pctrl_srisenable_attr == PCTRL_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane12.pctrl_txcmnmode_disable_a_attr == PCTRL_TXCMNMODE_DISABLE_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane12.pctrl_txoneszeros_attr == PCTRL_TXONESZEROS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane13.dctrl_dfd_bsync_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane13.dctrl_dfd_datasel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane13.dctrl_dfd_power_off_attr == DCTRL_DFD_POWER_OFF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane13.dctrl_dfd_primary_attr == DCTRL_DFD_PRIMARY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane13.dctrl_dfd_secondary_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane13.lctrl_lane_mode_ctrl_attr == LCTRL_LANE_MODE_PCIE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane13.lctrl_lane_mode_sel_attr == LCTRL_LANE_MODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane13.pctrl_lowpin_nt_attr == PCTRL_LOWPIN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane13.pctrl_pclkchangeack_attr == PCTRL_PCLKCHANGEACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane13.pctrl_phy_mode_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane13.pctrl_rxelecidle_disable_a_attr == PCTRL_RXELECIDLE_DISABLE_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane13.pctrl_rxeqclr_attr == PCTRL_RXEQCLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane13.pctrl_rxeqtraining_attr == PCTRL_RXEQTRAINING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane13.pctrl_rxtermination_attr == PCTRL_RXTERMINATION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane13.pctrl_srisenable_attr == PCTRL_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane13.pctrl_txcmnmode_disable_a_attr == PCTRL_TXCMNMODE_DISABLE_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane13.pctrl_txoneszeros_attr == PCTRL_TXONESZEROS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane14.dctrl_dfd_bsync_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane14.dctrl_dfd_datasel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane14.dctrl_dfd_power_off_attr == DCTRL_DFD_POWER_OFF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane14.dctrl_dfd_primary_attr == DCTRL_DFD_PRIMARY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane14.dctrl_dfd_secondary_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane14.lctrl_lane_mode_ctrl_attr == LCTRL_LANE_MODE_PCIE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane14.lctrl_lane_mode_sel_attr == LCTRL_LANE_MODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane14.pctrl_lowpin_nt_attr == PCTRL_LOWPIN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane14.pctrl_pclkchangeack_attr == PCTRL_PCLKCHANGEACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane14.pctrl_phy_mode_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane14.pctrl_rxelecidle_disable_a_attr == PCTRL_RXELECIDLE_DISABLE_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane14.pctrl_rxeqclr_attr == PCTRL_RXEQCLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane14.pctrl_rxeqtraining_attr == PCTRL_RXEQTRAINING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane14.pctrl_rxtermination_attr == PCTRL_RXTERMINATION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane14.pctrl_srisenable_attr == PCTRL_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane14.pctrl_txcmnmode_disable_a_attr == PCTRL_TXCMNMODE_DISABLE_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane14.pctrl_txoneszeros_attr == PCTRL_TXONESZEROS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane15.dctrl_dfd_bsync_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane15.dctrl_dfd_datasel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane15.dctrl_dfd_power_off_attr == DCTRL_DFD_POWER_OFF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane15.dctrl_dfd_primary_attr == DCTRL_DFD_PRIMARY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane15.dctrl_dfd_secondary_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane15.lctrl_lane_mode_ctrl_attr == LCTRL_LANE_MODE_PCIE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane15.lctrl_lane_mode_sel_attr == LCTRL_LANE_MODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane15.pctrl_lowpin_nt_attr == PCTRL_LOWPIN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane15.pctrl_pclkchangeack_attr == PCTRL_PCLKCHANGEACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane15.pctrl_phy_mode_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane15.pctrl_rxelecidle_disable_a_attr == PCTRL_RXELECIDLE_DISABLE_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane15.pctrl_rxeqclr_attr == PCTRL_RXEQCLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane15.pctrl_rxeqtraining_attr == PCTRL_RXEQTRAINING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane15.pctrl_rxtermination_attr == PCTRL_RXTERMINATION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane15.pctrl_srisenable_attr == PCTRL_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane15.pctrl_txcmnmode_disable_a_attr == PCTRL_TXCMNMODE_DISABLE_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane15.pctrl_txoneszeros_attr == PCTRL_TXONESZEROS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane2.dctrl_dfd_bsync_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane2.dctrl_dfd_datasel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane2.dctrl_dfd_power_off_attr == DCTRL_DFD_POWER_OFF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane2.dctrl_dfd_primary_attr == DCTRL_DFD_PRIMARY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane2.dctrl_dfd_secondary_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane2.lctrl_lane_mode_ctrl_attr == LCTRL_LANE_MODE_PCIE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane2.lctrl_lane_mode_sel_attr == LCTRL_LANE_MODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane2.pctrl_lowpin_nt_attr == PCTRL_LOWPIN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane2.pctrl_pclkchangeack_attr == PCTRL_PCLKCHANGEACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane2.pctrl_phy_mode_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane2.pctrl_rxelecidle_disable_a_attr == PCTRL_RXELECIDLE_DISABLE_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane2.pctrl_rxeqclr_attr == PCTRL_RXEQCLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane2.pctrl_rxeqtraining_attr == PCTRL_RXEQTRAINING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane2.pctrl_rxtermination_attr == PCTRL_RXTERMINATION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane2.pctrl_srisenable_attr == PCTRL_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane2.pctrl_txcmnmode_disable_a_attr == PCTRL_TXCMNMODE_DISABLE_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane2.pctrl_txoneszeros_attr == PCTRL_TXONESZEROS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane3.dctrl_dfd_bsync_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane3.dctrl_dfd_datasel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane3.dctrl_dfd_power_off_attr == DCTRL_DFD_POWER_OFF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane3.dctrl_dfd_primary_attr == DCTRL_DFD_PRIMARY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane3.dctrl_dfd_secondary_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane3.lctrl_lane_mode_ctrl_attr == LCTRL_LANE_MODE_PCIE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane3.lctrl_lane_mode_sel_attr == LCTRL_LANE_MODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane3.pctrl_lowpin_nt_attr == PCTRL_LOWPIN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane3.pctrl_pclkchangeack_attr == PCTRL_PCLKCHANGEACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane3.pctrl_phy_mode_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane3.pctrl_rxelecidle_disable_a_attr == PCTRL_RXELECIDLE_DISABLE_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane3.pctrl_rxeqclr_attr == PCTRL_RXEQCLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane3.pctrl_rxeqtraining_attr == PCTRL_RXEQTRAINING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane3.pctrl_rxtermination_attr == PCTRL_RXTERMINATION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane3.pctrl_srisenable_attr == PCTRL_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane3.pctrl_txcmnmode_disable_a_attr == PCTRL_TXCMNMODE_DISABLE_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane3.pctrl_txoneszeros_attr == PCTRL_TXONESZEROS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane4.dctrl_dfd_bsync_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane4.dctrl_dfd_datasel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane4.dctrl_dfd_power_off_attr == DCTRL_DFD_POWER_OFF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane4.dctrl_dfd_primary_attr == DCTRL_DFD_PRIMARY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane4.dctrl_dfd_secondary_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane4.lctrl_lane_mode_ctrl_attr == LCTRL_LANE_MODE_PCIE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane4.lctrl_lane_mode_sel_attr == LCTRL_LANE_MODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane4.pctrl_lowpin_nt_attr == PCTRL_LOWPIN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane4.pctrl_pclkchangeack_attr == PCTRL_PCLKCHANGEACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane4.pctrl_phy_mode_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane4.pctrl_rxelecidle_disable_a_attr == PCTRL_RXELECIDLE_DISABLE_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane4.pctrl_rxeqclr_attr == PCTRL_RXEQCLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane4.pctrl_rxeqtraining_attr == PCTRL_RXEQTRAINING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane4.pctrl_rxtermination_attr == PCTRL_RXTERMINATION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane4.pctrl_srisenable_attr == PCTRL_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane4.pctrl_txcmnmode_disable_a_attr == PCTRL_TXCMNMODE_DISABLE_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane4.pctrl_txoneszeros_attr == PCTRL_TXONESZEROS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane5.dctrl_dfd_bsync_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane5.dctrl_dfd_datasel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane5.dctrl_dfd_power_off_attr == DCTRL_DFD_POWER_OFF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane5.dctrl_dfd_primary_attr == DCTRL_DFD_PRIMARY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane5.dctrl_dfd_secondary_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane5.lctrl_lane_mode_ctrl_attr == LCTRL_LANE_MODE_PCIE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane5.lctrl_lane_mode_sel_attr == LCTRL_LANE_MODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane5.pctrl_lowpin_nt_attr == PCTRL_LOWPIN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane5.pctrl_pclkchangeack_attr == PCTRL_PCLKCHANGEACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane5.pctrl_phy_mode_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane5.pctrl_rxelecidle_disable_a_attr == PCTRL_RXELECIDLE_DISABLE_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane5.pctrl_rxeqclr_attr == PCTRL_RXEQCLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane5.pctrl_rxeqtraining_attr == PCTRL_RXEQTRAINING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane5.pctrl_rxtermination_attr == PCTRL_RXTERMINATION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane5.pctrl_srisenable_attr == PCTRL_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane5.pctrl_txcmnmode_disable_a_attr == PCTRL_TXCMNMODE_DISABLE_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane5.pctrl_txoneszeros_attr == PCTRL_TXONESZEROS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane6.dctrl_dfd_bsync_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane6.dctrl_dfd_datasel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane6.dctrl_dfd_power_off_attr == DCTRL_DFD_POWER_OFF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane6.dctrl_dfd_primary_attr == DCTRL_DFD_PRIMARY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane6.dctrl_dfd_secondary_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane6.lctrl_lane_mode_ctrl_attr == LCTRL_LANE_MODE_PCIE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane6.lctrl_lane_mode_sel_attr == LCTRL_LANE_MODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane6.pctrl_lowpin_nt_attr == PCTRL_LOWPIN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane6.pctrl_pclkchangeack_attr == PCTRL_PCLKCHANGEACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane6.pctrl_phy_mode_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane6.pctrl_rxelecidle_disable_a_attr == PCTRL_RXELECIDLE_DISABLE_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane6.pctrl_rxeqclr_attr == PCTRL_RXEQCLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane6.pctrl_rxeqtraining_attr == PCTRL_RXEQTRAINING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane6.pctrl_rxtermination_attr == PCTRL_RXTERMINATION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane6.pctrl_srisenable_attr == PCTRL_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane6.pctrl_txcmnmode_disable_a_attr == PCTRL_TXCMNMODE_DISABLE_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane6.pctrl_txoneszeros_attr == PCTRL_TXONESZEROS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane7.dctrl_dfd_bsync_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane7.dctrl_dfd_datasel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane7.dctrl_dfd_power_off_attr == DCTRL_DFD_POWER_OFF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane7.dctrl_dfd_primary_attr == DCTRL_DFD_PRIMARY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane7.dctrl_dfd_secondary_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane7.lctrl_lane_mode_ctrl_attr == LCTRL_LANE_MODE_PCIE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane7.lctrl_lane_mode_sel_attr == LCTRL_LANE_MODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane7.pctrl_lowpin_nt_attr == PCTRL_LOWPIN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane7.pctrl_pclkchangeack_attr == PCTRL_PCLKCHANGEACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane7.pctrl_phy_mode_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane7.pctrl_rxelecidle_disable_a_attr == PCTRL_RXELECIDLE_DISABLE_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane7.pctrl_rxeqclr_attr == PCTRL_RXEQCLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane7.pctrl_rxeqtraining_attr == PCTRL_RXEQTRAINING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane7.pctrl_rxtermination_attr == PCTRL_RXTERMINATION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane7.pctrl_srisenable_attr == PCTRL_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane7.pctrl_txcmnmode_disable_a_attr == PCTRL_TXCMNMODE_DISABLE_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane7.pctrl_txoneszeros_attr == PCTRL_TXONESZEROS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane8.dctrl_dfd_bsync_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane8.dctrl_dfd_datasel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane8.dctrl_dfd_power_off_attr == DCTRL_DFD_POWER_OFF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane8.dctrl_dfd_primary_attr == DCTRL_DFD_PRIMARY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane8.dctrl_dfd_secondary_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane8.lctrl_lane_mode_ctrl_attr == LCTRL_LANE_MODE_PCIE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane8.lctrl_lane_mode_sel_attr == LCTRL_LANE_MODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane8.pctrl_lowpin_nt_attr == PCTRL_LOWPIN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane8.pctrl_pclkchangeack_attr == PCTRL_PCLKCHANGEACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane8.pctrl_phy_mode_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane8.pctrl_rxelecidle_disable_a_attr == PCTRL_RXELECIDLE_DISABLE_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane8.pctrl_rxeqclr_attr == PCTRL_RXEQCLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane8.pctrl_rxeqtraining_attr == PCTRL_RXEQTRAINING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane8.pctrl_rxtermination_attr == PCTRL_RXTERMINATION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane8.pctrl_srisenable_attr == PCTRL_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane8.pctrl_txcmnmode_disable_a_attr == PCTRL_TXCMNMODE_DISABLE_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane8.pctrl_txoneszeros_attr == PCTRL_TXONESZEROS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane9.dctrl_dfd_bsync_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane9.dctrl_dfd_datasel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane9.dctrl_dfd_power_off_attr == DCTRL_DFD_POWER_OFF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane9.dctrl_dfd_primary_attr == DCTRL_DFD_PRIMARY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane9.dctrl_dfd_secondary_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane9.lctrl_lane_mode_ctrl_attr == LCTRL_LANE_MODE_PCIE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane9.lctrl_lane_mode_sel_attr == LCTRL_LANE_MODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane9.pctrl_lowpin_nt_attr == PCTRL_LOWPIN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane9.pctrl_pclkchangeack_attr == PCTRL_PCLKCHANGEACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane9.pctrl_phy_mode_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane9.pctrl_rxelecidle_disable_a_attr == PCTRL_RXELECIDLE_DISABLE_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane9.pctrl_rxeqclr_attr == PCTRL_RXEQCLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane9.pctrl_rxeqtraining_attr == PCTRL_RXEQTRAINING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane9.pctrl_rxtermination_attr == PCTRL_RXTERMINATION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane9.pctrl_srisenable_attr == PCTRL_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane9.pctrl_txcmnmode_disable_a_attr == PCTRL_TXCMNMODE_DISABLE_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_pcslane9.pctrl_txoneszeros_attr == PCTRL_TXONESZEROS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_m2p_bus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclk_rate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclk_rate_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLK_RATE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclkchangeack_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLKCHANGEACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclkchangeack_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLKCHANGEACK_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_phy_mode_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_phy_mode_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PHY_MODE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_powerdown_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_powerdown_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_POWERDOWN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rate_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RATE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rst_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rst_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RST_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rxelecidle_disable_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RXELECIDLE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rxelecidle_disable_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RXELECIDLE_DISABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxeqeval_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXEQEVAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxeqeval_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXEQEVAL_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpolarity_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpolarity_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPOLARITY_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpresethint_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpresethint_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPRESETHINT_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxstandby_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXSTANDBY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxstandby_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXSTANDBY_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxtermination_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXTERMINATION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxtermination_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXTERMINATION_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_srisenable_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_srisenable_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_SRISENABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcmnmode_disable_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCMNMODE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcmnmode_disable_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCMNMODE_DISABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcompliance_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCOMPLIANCE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcompliance_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCOMPLIANCE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdeemph_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDEEMPH_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdtctrx_lb_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDTCTRX_LB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdtctrx_lb_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDTCTRX_LB_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txelecidle_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txelecidle_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXELECIDLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txmargin_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txmargin_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXMARGIN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txoneszeros_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXONESZEROS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txoneszeros_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXONESZEROS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txdeemph_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txswing_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_TXSWING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txswing_ena_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_TXSWING_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_width_ena_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_WIDTH_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p1subentry_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P1SUBENTRY_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p1subexit_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P1SUBEXIT_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p2entry_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P2ENTRY_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p2exit_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P2EXIT_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatusgen_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUSGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxdetect_inpciep2_en_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXDETECT_INPCIEP2_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxpstate_p0s_en_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXPSTATE_P0S_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxstandby0en_in_rxeq_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXSTANDBY0EN_IN_RXEQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie5_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_usb1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_usb2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_tx_pcie1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie5_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_usb1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_usb2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_14_cfg_vpcslb_fe_attr == UX_PCS_LANE_Q0_REG_14_CFG_VPCSLB_FE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_14_cfg_vpcsmbusconv_illegal_rd_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_14_CFG_VPCSMBUSCONV_ILLEGAL_RD_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_15_cfg_vpcslfps_ctrl_p3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_illegal_wr_c_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_ILLEGAL_WR_C_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_illegal_wr_uc_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_ILLEGAL_WR_UC_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_ack_gen_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_ACK_GEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timeout_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_COMPL_TIMEOUT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timer_en_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_COMPL_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timer_max_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_gen_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_GEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timeout_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_TIMEOUT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timer_en_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timer_max_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_15_cfg_vpcsonezero_one_cntr_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_15_cfg_vpcstxdrv_usb_gen1_txdeemph_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSTXDRV_USB_GEN1_TXDEEMPH_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_16_cfg_vpcsonezero_zero_cntr_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_16_cfg_vpcstbus_addr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_16_cfg_vpcstx_gen4_preset0_attr == 18'd60032
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_16_cfg_vpcstxdrv_usb_gen1_txswing_attr == UX_PCS_LANE_Q0_REG_16_CFG_VPCSTXDRV_USB_GEN1_TXSWING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_17_cfg_vpcsspare0_attr == 32'd4294901760
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_18_cfg_vpcstx_gen4_preset1_attr == 18'd39872
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_18_cfg_vpcstx_localfs_attr == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_18_cfg_vpcstx_localg4fs_attr == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_19_cfg_vpcstx_gen4_preset10_attr == 18'd80192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_19_cfg_vpcstx_localg4lf_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_19_cfg_vpcstx_locallf_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_1_cfg_vcpsckgate_disable_attr == UX_PCS_LANE_Q0_REG_1_CFG_VCPSCKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_1_cfg_vpcs_if_clk_sel_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCS_IF_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_1_cfg_vpcsalign10b_lock_cnt_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_1_cfg_vpcsalign10b_unlock_cnt_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_1_cfg_vpcsalign128b_g3g4_skp_os_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSALIGN128B_G3G4_SKP_OS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_1_cfg_vpcsalign128b_usb2_ctrl_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_clr_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_en_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_hold_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_data_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_en_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_init_ctrl_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_INIT_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_init_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_insert_err_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_INSERT_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_skp_cnt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_1_cfg_vpcsebuf_reset_on_err_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSEBUF_RESET_ON_ERR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_20_cfg_vpcstx_gen4_preset2_attr == 18'd47936
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_20_cfg_vpcstxdrv_levn_gen1_0_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_20_cfg_vpcstxdrv_levn_gen1_1_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_21_cfg_vpcstx_gen4_preset3_attr == 18'd31808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_21_cfg_vpcstxdrv_levn_gen1_10_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_21_cfg_vpcstxdrv_levn_gen1_11_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_22_cfg_vpcstx_gen4_preset4_attr == 18'd3584
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_22_cfg_vpcstxdrv_levn_gen1_12_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_22_cfg_vpcstxdrv_levn_gen1_13_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_23_cfg_vpcstx_gen4_preset5_attr == 18'd3206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_23_cfg_vpcstxdrv_levn_gen1_14_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_23_cfg_vpcstxdrv_levn_gen1_15_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_24_cfg_vpcstx_gen4_preset6_attr == 18'd3143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_24_cfg_vpcstxdrv_levn_gen1_2_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_24_cfg_vpcstxdrv_levn_gen1_3_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_25_cfg_vpcstx_gen4_preset7_attr == 18'd47558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_25_cfg_vpcstxdrv_levn_gen1_4_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_25_cfg_vpcstxdrv_levn_gen1_5_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_26_cfg_vpcstx_gen4_preset8_attr == 18'd31367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_26_cfg_vpcstxdrv_levn_gen1_6_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_26_cfg_vpcstxdrv_levn_gen1_7_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_27_cfg_vpcstx_gen4_preset9_attr == 18'd3017
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_27_cfg_vpcstxdrv_levn_gen1_8_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_27_cfg_vpcstxdrv_levn_gen1_9_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_28_cfg_vpcstx_preset0_attr == 18'd60032
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_28_cfg_vpcstxdrv_levn_gen2_0_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_28_cfg_vpcstxdrv_levn_gen2_1_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_29_cfg_vpcstx_preset1_attr == 18'd39872
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_29_cfg_vpcstxdrv_levn_gen2_10_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_29_cfg_vpcstxdrv_levn_gen2_11_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_2_cfg_vpcs_misc_attr == 32'd305419896
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_30_cfg_vpcstx_preset10_attr == 18'd80192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_30_cfg_vpcstxdrv_levn_gen2_12_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_30_cfg_vpcstxdrv_levn_gen2_13_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_31_cfg_vpcstx_preset2_attr == 18'd47936
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_31_cfg_vpcstxdrv_levn_gen2_14_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_31_cfg_vpcstxdrv_levn_gen2_15_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_32_cfg_vpcstx_preset3_attr == 18'd31808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_32_cfg_vpcstxdrv_levn_gen2_2_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_32_cfg_vpcstxdrv_levn_gen2_3_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_33_cfg_vpcstx_preset4_attr == 18'd3584
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_33_cfg_vpcstxdrv_levn_gen2_4_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_33_cfg_vpcstxdrv_levn_gen2_5_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_34_cfg_vpcstx_preset5_attr == 18'd3206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_34_cfg_vpcstxdrv_levn_gen2_6_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_34_cfg_vpcstxdrv_levn_gen2_7_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_35_cfg_vpcstx_preset6_attr == 18'd3143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_35_cfg_vpcstxdrv_levn_gen2_8_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_35_cfg_vpcstxdrv_levn_gen2_9_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_36_cfg_vpcstx_preset7_attr == 18'd47558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_levnm1_gen1_0_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_levnm1_gen1_1_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_txdrvslew_gen1_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_37_cfg_vpcstx_preset8_attr == 18'd31367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_levnm1_gen1_10_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_levnm1_gen1_11_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_txdrvslew_gen2_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_38_cfg_vpcstx_preset9_attr == 18'd3017
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_levnm1_gen1_12_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_levnm1_gen1_13_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_txdrvslew_gen3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_14_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_15_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_2_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_3_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_5_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_3_cfg_vpcsbist_gen_skp_delay_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_3_cfg_vpcsebuf_fifo_full_thr_attr == 7'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_3_cfg_vpcsebuf_fifo_full_thr_sris_attr == 7'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_3_cfg_vpcseios_det_en_attr == UX_PCS_LANE_Q0_REG_3_CFG_VPCSEIOS_DET_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_3_cfg_vpcsif_blockaligncontrolpolarity_attr == UX_PCS_LANE_Q0_REG_3_CFG_VPCSIF_BLOCKALIGNCONTROLPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_6_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_7_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_8_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_9_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen2_0_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen2_1_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_10_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_11_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_12_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_13_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_14_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_15_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_2_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_3_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_5_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_6_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_7_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_levnm1_gen2_8_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_levnm1_gen2_9_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_txdrvslew_gen4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_good_syncheader_align_dis_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSALIGN128B_GOOD_SYNCHEADER_ALIGN_DIS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_unalign_lb_en_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSALIGN128B_UNALIGN_LB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_unalign_lb_wait_cnt_thr_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_data_en_falling_dly_ovr_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_DATA_EN_FALLING_DLY_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_data_en_falling_dly_thr_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_enb_skp_add_when_skpos_is_24_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_ENB_SKP_ADD_WHEN_SKPOS_IS_24_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_clr_cnt_thr_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_mid_offset_thr_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_mid_offset_thr_ow_en_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_FIFO_RD_MID_OFFSET_THR_OW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_fifo_wr_mid_offset_thr_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_fifo_wr_mid_offset_thr_ow_en_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_FIFO_WR_MID_OFFSET_THR_OW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_det_en_rd_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_DET_EN_RD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_det_en_wr_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_DET_EN_WR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_force_en_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_FORCE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_5_cfg_vpcsif_txflow_force_on_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSIF_TXFLOW_FORCE_ON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_5_cfg_vpcsif_txflow_nodatavld_force_on_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSIF_TXFLOW_NODATAVLD_FORCE_ON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_5_cfg_vpcsroreg_ckgate_dsbl_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSROREG_CKGATE_DSBL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_5_cfg_vpcstbus_ckgate_dsbl_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSTBUS_CKGATE_DSBL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_6_cfg_vpcsbist_udp_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_7_cfg_vpcsbist_udp_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_8_cfg_vpcsebuf_fifo_mid_thr_attr == 7'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_8_cfg_vpcsebuf_fifo_mid_thr_sris_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_force_neg_disp_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_force_pos_disp_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_tx_force_err_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_8_cfg_vpcsif_idle_cntr_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_8_cfg_vpcsif_ovr_blockaligncontrol_attr == UX_PCS_LANE_Q0_REG_8_CFG_VPCSIF_OVR_BLOCKALIGNCONTROL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_8_cfg_vpcsif_ovr_blockaligncontrol_ena_attr == UX_PCS_LANE_Q0_REG_8_CFG_VPCSIF_OVR_BLOCKALIGNCONTROL_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_9_cfg_vpcsif_min_reset_cntr_max_attr == 11'd1000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_9_cfg_vpcsif_min_txidle_cntr_max_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_chng_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_CHNG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_ebuf_mode_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_EBUF_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_ebuf_mode_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_EBUF_MODE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_encodedecodebypass_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_ENCODEDECODEBYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_encodedecodebypass_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_ENCODEDECODEBYPASS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_getlocalpresetcoefficients_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_GETLOCALPRESETCOEFFICIENTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_getlocalpresetcoefficients_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_GETLOCALPRESETCOEFFICIENTS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_localpresetindex_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_localpresetindex_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOCALPRESETINDEX_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_lowpin_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOWPIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_lowpin_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOWPIN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_m2p_bus_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_M2P_BUS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_pclk_as_input_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_PCLK_AS_INPUT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane0.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_pclk_as_input_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_PCLK_AS_INPUT_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_m2p_bus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclk_rate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclk_rate_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLK_RATE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclkchangeack_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLKCHANGEACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclkchangeack_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLKCHANGEACK_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_phy_mode_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_phy_mode_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PHY_MODE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_powerdown_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_powerdown_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_POWERDOWN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rate_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RATE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rst_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rst_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RST_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rxelecidle_disable_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RXELECIDLE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rxelecidle_disable_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RXELECIDLE_DISABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxeqeval_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXEQEVAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxeqeval_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXEQEVAL_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpolarity_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpolarity_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPOLARITY_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpresethint_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpresethint_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPRESETHINT_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxstandby_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXSTANDBY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxstandby_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXSTANDBY_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxtermination_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXTERMINATION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxtermination_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXTERMINATION_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_srisenable_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_srisenable_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_SRISENABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcmnmode_disable_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCMNMODE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcmnmode_disable_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCMNMODE_DISABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcompliance_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCOMPLIANCE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcompliance_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCOMPLIANCE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdeemph_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDEEMPH_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdtctrx_lb_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDTCTRX_LB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdtctrx_lb_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDTCTRX_LB_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txelecidle_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txelecidle_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXELECIDLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txmargin_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txmargin_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXMARGIN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txoneszeros_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXONESZEROS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txoneszeros_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXONESZEROS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txdeemph_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txswing_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_TXSWING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txswing_ena_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_TXSWING_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_width_ena_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_WIDTH_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p1subentry_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P1SUBENTRY_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p1subexit_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P1SUBEXIT_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p2entry_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P2ENTRY_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p2exit_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P2EXIT_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatusgen_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUSGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxdetect_inpciep2_en_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXDETECT_INPCIEP2_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxpstate_p0s_en_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXPSTATE_P0S_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxstandby0en_in_rxeq_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXSTANDBY0EN_IN_RXEQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie5_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_usb1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_usb2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_tx_pcie1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie5_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_usb1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_usb2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_14_cfg_vpcslb_fe_attr == UX_PCS_LANE_Q0_REG_14_CFG_VPCSLB_FE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_14_cfg_vpcsmbusconv_illegal_rd_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_14_CFG_VPCSMBUSCONV_ILLEGAL_RD_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_15_cfg_vpcslfps_ctrl_p3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_illegal_wr_c_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_ILLEGAL_WR_C_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_illegal_wr_uc_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_ILLEGAL_WR_UC_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_ack_gen_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_ACK_GEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timeout_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_COMPL_TIMEOUT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timer_en_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_COMPL_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timer_max_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_gen_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_GEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timeout_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_TIMEOUT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timer_en_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timer_max_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_15_cfg_vpcsonezero_one_cntr_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_15_cfg_vpcstxdrv_usb_gen1_txdeemph_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSTXDRV_USB_GEN1_TXDEEMPH_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_16_cfg_vpcsonezero_zero_cntr_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_16_cfg_vpcstbus_addr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_16_cfg_vpcstx_gen4_preset0_attr == 18'd60032
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_16_cfg_vpcstxdrv_usb_gen1_txswing_attr == UX_PCS_LANE_Q0_REG_16_CFG_VPCSTXDRV_USB_GEN1_TXSWING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_17_cfg_vpcsspare0_attr == 32'd4294901760
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_18_cfg_vpcstx_gen4_preset1_attr == 18'd39872
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_18_cfg_vpcstx_localfs_attr == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_18_cfg_vpcstx_localg4fs_attr == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_19_cfg_vpcstx_gen4_preset10_attr == 18'd80192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_19_cfg_vpcstx_localg4lf_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_19_cfg_vpcstx_locallf_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_1_cfg_vcpsckgate_disable_attr == UX_PCS_LANE_Q0_REG_1_CFG_VCPSCKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_1_cfg_vpcs_if_clk_sel_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCS_IF_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_1_cfg_vpcsalign10b_lock_cnt_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_1_cfg_vpcsalign10b_unlock_cnt_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_1_cfg_vpcsalign128b_g3g4_skp_os_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSALIGN128B_G3G4_SKP_OS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_1_cfg_vpcsalign128b_usb2_ctrl_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_clr_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_en_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_hold_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_data_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_en_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_init_ctrl_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_INIT_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_init_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_insert_err_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_INSERT_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_skp_cnt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_1_cfg_vpcsebuf_reset_on_err_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSEBUF_RESET_ON_ERR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_20_cfg_vpcstx_gen4_preset2_attr == 18'd47936
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_20_cfg_vpcstxdrv_levn_gen1_0_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_20_cfg_vpcstxdrv_levn_gen1_1_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_21_cfg_vpcstx_gen4_preset3_attr == 18'd31808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_21_cfg_vpcstxdrv_levn_gen1_10_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_21_cfg_vpcstxdrv_levn_gen1_11_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_22_cfg_vpcstx_gen4_preset4_attr == 18'd3584
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_22_cfg_vpcstxdrv_levn_gen1_12_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_22_cfg_vpcstxdrv_levn_gen1_13_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_23_cfg_vpcstx_gen4_preset5_attr == 18'd3206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_23_cfg_vpcstxdrv_levn_gen1_14_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_23_cfg_vpcstxdrv_levn_gen1_15_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_24_cfg_vpcstx_gen4_preset6_attr == 18'd3143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_24_cfg_vpcstxdrv_levn_gen1_2_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_24_cfg_vpcstxdrv_levn_gen1_3_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_25_cfg_vpcstx_gen4_preset7_attr == 18'd47558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_25_cfg_vpcstxdrv_levn_gen1_4_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_25_cfg_vpcstxdrv_levn_gen1_5_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_26_cfg_vpcstx_gen4_preset8_attr == 18'd31367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_26_cfg_vpcstxdrv_levn_gen1_6_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_26_cfg_vpcstxdrv_levn_gen1_7_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_27_cfg_vpcstx_gen4_preset9_attr == 18'd3017
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_27_cfg_vpcstxdrv_levn_gen1_8_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_27_cfg_vpcstxdrv_levn_gen1_9_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_28_cfg_vpcstx_preset0_attr == 18'd60032
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_28_cfg_vpcstxdrv_levn_gen2_0_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_28_cfg_vpcstxdrv_levn_gen2_1_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_29_cfg_vpcstx_preset1_attr == 18'd39872
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_29_cfg_vpcstxdrv_levn_gen2_10_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_29_cfg_vpcstxdrv_levn_gen2_11_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_2_cfg_vpcs_misc_attr == 32'd305419896
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_30_cfg_vpcstx_preset10_attr == 18'd80192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_30_cfg_vpcstxdrv_levn_gen2_12_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_30_cfg_vpcstxdrv_levn_gen2_13_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_31_cfg_vpcstx_preset2_attr == 18'd47936
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_31_cfg_vpcstxdrv_levn_gen2_14_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_31_cfg_vpcstxdrv_levn_gen2_15_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_32_cfg_vpcstx_preset3_attr == 18'd31808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_32_cfg_vpcstxdrv_levn_gen2_2_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_32_cfg_vpcstxdrv_levn_gen2_3_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_33_cfg_vpcstx_preset4_attr == 18'd3584
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_33_cfg_vpcstxdrv_levn_gen2_4_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_33_cfg_vpcstxdrv_levn_gen2_5_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_34_cfg_vpcstx_preset5_attr == 18'd3206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_34_cfg_vpcstxdrv_levn_gen2_6_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_34_cfg_vpcstxdrv_levn_gen2_7_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_35_cfg_vpcstx_preset6_attr == 18'd3143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_35_cfg_vpcstxdrv_levn_gen2_8_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_35_cfg_vpcstxdrv_levn_gen2_9_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_36_cfg_vpcstx_preset7_attr == 18'd47558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_levnm1_gen1_0_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_levnm1_gen1_1_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_txdrvslew_gen1_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_37_cfg_vpcstx_preset8_attr == 18'd31367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_levnm1_gen1_10_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_levnm1_gen1_11_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_txdrvslew_gen2_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_38_cfg_vpcstx_preset9_attr == 18'd3017
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_levnm1_gen1_12_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_levnm1_gen1_13_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_txdrvslew_gen3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_14_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_15_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_2_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_3_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_5_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_3_cfg_vpcsbist_gen_skp_delay_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_3_cfg_vpcsebuf_fifo_full_thr_attr == 7'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_3_cfg_vpcsebuf_fifo_full_thr_sris_attr == 7'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_3_cfg_vpcseios_det_en_attr == UX_PCS_LANE_Q0_REG_3_CFG_VPCSEIOS_DET_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_3_cfg_vpcsif_blockaligncontrolpolarity_attr == UX_PCS_LANE_Q0_REG_3_CFG_VPCSIF_BLOCKALIGNCONTROLPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_6_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_7_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_8_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_9_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen2_0_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen2_1_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_10_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_11_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_12_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_13_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_14_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_15_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_2_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_3_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_5_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_6_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_7_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_levnm1_gen2_8_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_levnm1_gen2_9_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_txdrvslew_gen4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_good_syncheader_align_dis_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSALIGN128B_GOOD_SYNCHEADER_ALIGN_DIS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_unalign_lb_en_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSALIGN128B_UNALIGN_LB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_unalign_lb_wait_cnt_thr_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_data_en_falling_dly_ovr_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_DATA_EN_FALLING_DLY_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_data_en_falling_dly_thr_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_enb_skp_add_when_skpos_is_24_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_ENB_SKP_ADD_WHEN_SKPOS_IS_24_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_clr_cnt_thr_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_mid_offset_thr_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_mid_offset_thr_ow_en_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_FIFO_RD_MID_OFFSET_THR_OW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_fifo_wr_mid_offset_thr_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_fifo_wr_mid_offset_thr_ow_en_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_FIFO_WR_MID_OFFSET_THR_OW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_det_en_rd_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_DET_EN_RD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_det_en_wr_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_DET_EN_WR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_force_en_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_FORCE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_5_cfg_vpcsif_txflow_force_on_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSIF_TXFLOW_FORCE_ON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_5_cfg_vpcsif_txflow_nodatavld_force_on_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSIF_TXFLOW_NODATAVLD_FORCE_ON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_5_cfg_vpcsroreg_ckgate_dsbl_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSROREG_CKGATE_DSBL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_5_cfg_vpcstbus_ckgate_dsbl_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSTBUS_CKGATE_DSBL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_6_cfg_vpcsbist_udp_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_7_cfg_vpcsbist_udp_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_8_cfg_vpcsebuf_fifo_mid_thr_attr == 7'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_8_cfg_vpcsebuf_fifo_mid_thr_sris_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_force_neg_disp_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_force_pos_disp_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_tx_force_err_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_8_cfg_vpcsif_idle_cntr_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_8_cfg_vpcsif_ovr_blockaligncontrol_attr == UX_PCS_LANE_Q0_REG_8_CFG_VPCSIF_OVR_BLOCKALIGNCONTROL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_8_cfg_vpcsif_ovr_blockaligncontrol_ena_attr == UX_PCS_LANE_Q0_REG_8_CFG_VPCSIF_OVR_BLOCKALIGNCONTROL_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_9_cfg_vpcsif_min_reset_cntr_max_attr == 11'd1000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_9_cfg_vpcsif_min_txidle_cntr_max_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_chng_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_CHNG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_ebuf_mode_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_EBUF_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_ebuf_mode_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_EBUF_MODE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_encodedecodebypass_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_ENCODEDECODEBYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_encodedecodebypass_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_ENCODEDECODEBYPASS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_getlocalpresetcoefficients_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_GETLOCALPRESETCOEFFICIENTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_getlocalpresetcoefficients_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_GETLOCALPRESETCOEFFICIENTS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_localpresetindex_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_localpresetindex_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOCALPRESETINDEX_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_lowpin_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOWPIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_lowpin_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOWPIN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_m2p_bus_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_M2P_BUS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_pclk_as_input_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_PCLK_AS_INPUT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane1.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_pclk_as_input_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_PCLK_AS_INPUT_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_m2p_bus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclk_rate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclk_rate_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLK_RATE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclkchangeack_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLKCHANGEACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclkchangeack_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLKCHANGEACK_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_phy_mode_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_phy_mode_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PHY_MODE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_powerdown_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_powerdown_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_POWERDOWN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rate_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RATE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rst_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rst_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RST_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rxelecidle_disable_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RXELECIDLE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rxelecidle_disable_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RXELECIDLE_DISABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxeqeval_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXEQEVAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxeqeval_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXEQEVAL_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpolarity_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpolarity_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPOLARITY_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpresethint_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpresethint_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPRESETHINT_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxstandby_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXSTANDBY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxstandby_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXSTANDBY_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxtermination_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXTERMINATION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxtermination_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXTERMINATION_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_srisenable_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_srisenable_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_SRISENABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcmnmode_disable_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCMNMODE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcmnmode_disable_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCMNMODE_DISABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcompliance_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCOMPLIANCE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcompliance_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCOMPLIANCE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdeemph_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDEEMPH_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdtctrx_lb_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDTCTRX_LB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdtctrx_lb_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDTCTRX_LB_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txelecidle_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txelecidle_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXELECIDLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txmargin_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txmargin_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXMARGIN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txoneszeros_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXONESZEROS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txoneszeros_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXONESZEROS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txdeemph_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txswing_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_TXSWING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txswing_ena_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_TXSWING_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_width_ena_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_WIDTH_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p1subentry_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P1SUBENTRY_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p1subexit_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P1SUBEXIT_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p2entry_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P2ENTRY_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p2exit_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P2EXIT_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatusgen_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUSGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxdetect_inpciep2_en_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXDETECT_INPCIEP2_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxpstate_p0s_en_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXPSTATE_P0S_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxstandby0en_in_rxeq_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXSTANDBY0EN_IN_RXEQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie5_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_usb1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_usb2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_tx_pcie1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie5_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_usb1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_usb2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_14_cfg_vpcslb_fe_attr == UX_PCS_LANE_Q0_REG_14_CFG_VPCSLB_FE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_14_cfg_vpcsmbusconv_illegal_rd_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_14_CFG_VPCSMBUSCONV_ILLEGAL_RD_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_15_cfg_vpcslfps_ctrl_p3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_illegal_wr_c_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_ILLEGAL_WR_C_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_illegal_wr_uc_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_ILLEGAL_WR_UC_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_ack_gen_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_ACK_GEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timeout_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_COMPL_TIMEOUT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timer_en_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_COMPL_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timer_max_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_gen_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_GEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timeout_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_TIMEOUT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timer_en_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timer_max_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_15_cfg_vpcsonezero_one_cntr_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_15_cfg_vpcstxdrv_usb_gen1_txdeemph_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSTXDRV_USB_GEN1_TXDEEMPH_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_16_cfg_vpcsonezero_zero_cntr_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_16_cfg_vpcstbus_addr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_16_cfg_vpcstx_gen4_preset0_attr == 18'd60032
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_16_cfg_vpcstxdrv_usb_gen1_txswing_attr == UX_PCS_LANE_Q0_REG_16_CFG_VPCSTXDRV_USB_GEN1_TXSWING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_17_cfg_vpcsspare0_attr == 32'd4294901760
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_18_cfg_vpcstx_gen4_preset1_attr == 18'd39872
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_18_cfg_vpcstx_localfs_attr == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_18_cfg_vpcstx_localg4fs_attr == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_19_cfg_vpcstx_gen4_preset10_attr == 18'd80192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_19_cfg_vpcstx_localg4lf_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_19_cfg_vpcstx_locallf_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_1_cfg_vcpsckgate_disable_attr == UX_PCS_LANE_Q0_REG_1_CFG_VCPSCKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_1_cfg_vpcs_if_clk_sel_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCS_IF_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_1_cfg_vpcsalign10b_lock_cnt_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_1_cfg_vpcsalign10b_unlock_cnt_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_1_cfg_vpcsalign128b_g3g4_skp_os_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSALIGN128B_G3G4_SKP_OS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_1_cfg_vpcsalign128b_usb2_ctrl_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_clr_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_en_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_hold_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_data_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_en_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_init_ctrl_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_INIT_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_init_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_insert_err_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_INSERT_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_skp_cnt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_1_cfg_vpcsebuf_reset_on_err_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSEBUF_RESET_ON_ERR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_20_cfg_vpcstx_gen4_preset2_attr == 18'd47936
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_20_cfg_vpcstxdrv_levn_gen1_0_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_20_cfg_vpcstxdrv_levn_gen1_1_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_21_cfg_vpcstx_gen4_preset3_attr == 18'd31808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_21_cfg_vpcstxdrv_levn_gen1_10_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_21_cfg_vpcstxdrv_levn_gen1_11_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_22_cfg_vpcstx_gen4_preset4_attr == 18'd3584
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_22_cfg_vpcstxdrv_levn_gen1_12_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_22_cfg_vpcstxdrv_levn_gen1_13_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_23_cfg_vpcstx_gen4_preset5_attr == 18'd3206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_23_cfg_vpcstxdrv_levn_gen1_14_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_23_cfg_vpcstxdrv_levn_gen1_15_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_24_cfg_vpcstx_gen4_preset6_attr == 18'd3143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_24_cfg_vpcstxdrv_levn_gen1_2_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_24_cfg_vpcstxdrv_levn_gen1_3_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_25_cfg_vpcstx_gen4_preset7_attr == 18'd47558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_25_cfg_vpcstxdrv_levn_gen1_4_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_25_cfg_vpcstxdrv_levn_gen1_5_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_26_cfg_vpcstx_gen4_preset8_attr == 18'd31367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_26_cfg_vpcstxdrv_levn_gen1_6_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_26_cfg_vpcstxdrv_levn_gen1_7_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_27_cfg_vpcstx_gen4_preset9_attr == 18'd3017
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_27_cfg_vpcstxdrv_levn_gen1_8_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_27_cfg_vpcstxdrv_levn_gen1_9_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_28_cfg_vpcstx_preset0_attr == 18'd60032
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_28_cfg_vpcstxdrv_levn_gen2_0_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_28_cfg_vpcstxdrv_levn_gen2_1_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_29_cfg_vpcstx_preset1_attr == 18'd39872
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_29_cfg_vpcstxdrv_levn_gen2_10_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_29_cfg_vpcstxdrv_levn_gen2_11_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_2_cfg_vpcs_misc_attr == 32'd305419896
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_30_cfg_vpcstx_preset10_attr == 18'd80192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_30_cfg_vpcstxdrv_levn_gen2_12_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_30_cfg_vpcstxdrv_levn_gen2_13_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_31_cfg_vpcstx_preset2_attr == 18'd47936
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_31_cfg_vpcstxdrv_levn_gen2_14_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_31_cfg_vpcstxdrv_levn_gen2_15_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_32_cfg_vpcstx_preset3_attr == 18'd31808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_32_cfg_vpcstxdrv_levn_gen2_2_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_32_cfg_vpcstxdrv_levn_gen2_3_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_33_cfg_vpcstx_preset4_attr == 18'd3584
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_33_cfg_vpcstxdrv_levn_gen2_4_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_33_cfg_vpcstxdrv_levn_gen2_5_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_34_cfg_vpcstx_preset5_attr == 18'd3206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_34_cfg_vpcstxdrv_levn_gen2_6_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_34_cfg_vpcstxdrv_levn_gen2_7_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_35_cfg_vpcstx_preset6_attr == 18'd3143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_35_cfg_vpcstxdrv_levn_gen2_8_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_35_cfg_vpcstxdrv_levn_gen2_9_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_36_cfg_vpcstx_preset7_attr == 18'd47558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_levnm1_gen1_0_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_levnm1_gen1_1_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_txdrvslew_gen1_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_37_cfg_vpcstx_preset8_attr == 18'd31367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_levnm1_gen1_10_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_levnm1_gen1_11_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_txdrvslew_gen2_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_38_cfg_vpcstx_preset9_attr == 18'd3017
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_levnm1_gen1_12_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_levnm1_gen1_13_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_txdrvslew_gen3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_14_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_15_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_2_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_3_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_5_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_3_cfg_vpcsbist_gen_skp_delay_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_3_cfg_vpcsebuf_fifo_full_thr_attr == 7'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_3_cfg_vpcsebuf_fifo_full_thr_sris_attr == 7'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_3_cfg_vpcseios_det_en_attr == UX_PCS_LANE_Q0_REG_3_CFG_VPCSEIOS_DET_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_3_cfg_vpcsif_blockaligncontrolpolarity_attr == UX_PCS_LANE_Q0_REG_3_CFG_VPCSIF_BLOCKALIGNCONTROLPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_6_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_7_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_8_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_9_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen2_0_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen2_1_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_10_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_11_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_12_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_13_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_14_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_15_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_2_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_3_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_5_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_6_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_7_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_levnm1_gen2_8_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_levnm1_gen2_9_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_txdrvslew_gen4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_good_syncheader_align_dis_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSALIGN128B_GOOD_SYNCHEADER_ALIGN_DIS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_unalign_lb_en_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSALIGN128B_UNALIGN_LB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_unalign_lb_wait_cnt_thr_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_data_en_falling_dly_ovr_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_DATA_EN_FALLING_DLY_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_data_en_falling_dly_thr_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_enb_skp_add_when_skpos_is_24_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_ENB_SKP_ADD_WHEN_SKPOS_IS_24_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_clr_cnt_thr_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_mid_offset_thr_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_mid_offset_thr_ow_en_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_FIFO_RD_MID_OFFSET_THR_OW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_fifo_wr_mid_offset_thr_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_fifo_wr_mid_offset_thr_ow_en_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_FIFO_WR_MID_OFFSET_THR_OW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_det_en_rd_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_DET_EN_RD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_det_en_wr_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_DET_EN_WR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_force_en_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_FORCE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_5_cfg_vpcsif_txflow_force_on_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSIF_TXFLOW_FORCE_ON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_5_cfg_vpcsif_txflow_nodatavld_force_on_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSIF_TXFLOW_NODATAVLD_FORCE_ON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_5_cfg_vpcsroreg_ckgate_dsbl_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSROREG_CKGATE_DSBL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_5_cfg_vpcstbus_ckgate_dsbl_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSTBUS_CKGATE_DSBL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_6_cfg_vpcsbist_udp_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_7_cfg_vpcsbist_udp_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_8_cfg_vpcsebuf_fifo_mid_thr_attr == 7'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_8_cfg_vpcsebuf_fifo_mid_thr_sris_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_force_neg_disp_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_force_pos_disp_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_tx_force_err_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_8_cfg_vpcsif_idle_cntr_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_8_cfg_vpcsif_ovr_blockaligncontrol_attr == UX_PCS_LANE_Q0_REG_8_CFG_VPCSIF_OVR_BLOCKALIGNCONTROL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_8_cfg_vpcsif_ovr_blockaligncontrol_ena_attr == UX_PCS_LANE_Q0_REG_8_CFG_VPCSIF_OVR_BLOCKALIGNCONTROL_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_9_cfg_vpcsif_min_reset_cntr_max_attr == 11'd1000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_9_cfg_vpcsif_min_txidle_cntr_max_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_chng_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_CHNG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_ebuf_mode_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_EBUF_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_ebuf_mode_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_EBUF_MODE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_encodedecodebypass_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_ENCODEDECODEBYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_encodedecodebypass_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_ENCODEDECODEBYPASS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_getlocalpresetcoefficients_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_GETLOCALPRESETCOEFFICIENTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_getlocalpresetcoefficients_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_GETLOCALPRESETCOEFFICIENTS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_localpresetindex_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_localpresetindex_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOCALPRESETINDEX_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_lowpin_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOWPIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_lowpin_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOWPIN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_m2p_bus_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_M2P_BUS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_pclk_as_input_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_PCLK_AS_INPUT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane10.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_pclk_as_input_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_PCLK_AS_INPUT_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_m2p_bus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclk_rate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclk_rate_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLK_RATE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclkchangeack_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLKCHANGEACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclkchangeack_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLKCHANGEACK_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_phy_mode_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_phy_mode_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PHY_MODE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_powerdown_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_powerdown_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_POWERDOWN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rate_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RATE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rst_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rst_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RST_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rxelecidle_disable_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RXELECIDLE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rxelecidle_disable_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RXELECIDLE_DISABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxeqeval_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXEQEVAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxeqeval_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXEQEVAL_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpolarity_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpolarity_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPOLARITY_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpresethint_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpresethint_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPRESETHINT_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxstandby_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXSTANDBY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxstandby_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXSTANDBY_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxtermination_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXTERMINATION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxtermination_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXTERMINATION_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_srisenable_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_srisenable_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_SRISENABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcmnmode_disable_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCMNMODE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcmnmode_disable_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCMNMODE_DISABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcompliance_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCOMPLIANCE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcompliance_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCOMPLIANCE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdeemph_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDEEMPH_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdtctrx_lb_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDTCTRX_LB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdtctrx_lb_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDTCTRX_LB_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txelecidle_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txelecidle_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXELECIDLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txmargin_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txmargin_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXMARGIN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txoneszeros_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXONESZEROS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txoneszeros_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXONESZEROS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txdeemph_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txswing_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_TXSWING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txswing_ena_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_TXSWING_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_width_ena_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_WIDTH_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p1subentry_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P1SUBENTRY_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p1subexit_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P1SUBEXIT_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p2entry_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P2ENTRY_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p2exit_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P2EXIT_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatusgen_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUSGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxdetect_inpciep2_en_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXDETECT_INPCIEP2_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxpstate_p0s_en_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXPSTATE_P0S_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxstandby0en_in_rxeq_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXSTANDBY0EN_IN_RXEQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie5_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_usb1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_usb2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_tx_pcie1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie5_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_usb1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_usb2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_14_cfg_vpcslb_fe_attr == UX_PCS_LANE_Q0_REG_14_CFG_VPCSLB_FE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_14_cfg_vpcsmbusconv_illegal_rd_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_14_CFG_VPCSMBUSCONV_ILLEGAL_RD_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_15_cfg_vpcslfps_ctrl_p3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_illegal_wr_c_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_ILLEGAL_WR_C_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_illegal_wr_uc_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_ILLEGAL_WR_UC_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_ack_gen_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_ACK_GEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timeout_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_COMPL_TIMEOUT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timer_en_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_COMPL_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timer_max_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_gen_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_GEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timeout_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_TIMEOUT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timer_en_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timer_max_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_15_cfg_vpcsonezero_one_cntr_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_15_cfg_vpcstxdrv_usb_gen1_txdeemph_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSTXDRV_USB_GEN1_TXDEEMPH_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_16_cfg_vpcsonezero_zero_cntr_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_16_cfg_vpcstbus_addr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_16_cfg_vpcstx_gen4_preset0_attr == 18'd60032
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_16_cfg_vpcstxdrv_usb_gen1_txswing_attr == UX_PCS_LANE_Q0_REG_16_CFG_VPCSTXDRV_USB_GEN1_TXSWING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_17_cfg_vpcsspare0_attr == 32'd4294901760
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_18_cfg_vpcstx_gen4_preset1_attr == 18'd39872
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_18_cfg_vpcstx_localfs_attr == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_18_cfg_vpcstx_localg4fs_attr == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_19_cfg_vpcstx_gen4_preset10_attr == 18'd80192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_19_cfg_vpcstx_localg4lf_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_19_cfg_vpcstx_locallf_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_1_cfg_vcpsckgate_disable_attr == UX_PCS_LANE_Q0_REG_1_CFG_VCPSCKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_1_cfg_vpcs_if_clk_sel_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCS_IF_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_1_cfg_vpcsalign10b_lock_cnt_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_1_cfg_vpcsalign10b_unlock_cnt_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_1_cfg_vpcsalign128b_g3g4_skp_os_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSALIGN128B_G3G4_SKP_OS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_1_cfg_vpcsalign128b_usb2_ctrl_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_clr_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_en_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_hold_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_data_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_en_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_init_ctrl_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_INIT_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_init_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_insert_err_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_INSERT_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_skp_cnt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_1_cfg_vpcsebuf_reset_on_err_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSEBUF_RESET_ON_ERR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_20_cfg_vpcstx_gen4_preset2_attr == 18'd47936
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_20_cfg_vpcstxdrv_levn_gen1_0_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_20_cfg_vpcstxdrv_levn_gen1_1_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_21_cfg_vpcstx_gen4_preset3_attr == 18'd31808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_21_cfg_vpcstxdrv_levn_gen1_10_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_21_cfg_vpcstxdrv_levn_gen1_11_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_22_cfg_vpcstx_gen4_preset4_attr == 18'd3584
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_22_cfg_vpcstxdrv_levn_gen1_12_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_22_cfg_vpcstxdrv_levn_gen1_13_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_23_cfg_vpcstx_gen4_preset5_attr == 18'd3206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_23_cfg_vpcstxdrv_levn_gen1_14_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_23_cfg_vpcstxdrv_levn_gen1_15_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_24_cfg_vpcstx_gen4_preset6_attr == 18'd3143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_24_cfg_vpcstxdrv_levn_gen1_2_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_24_cfg_vpcstxdrv_levn_gen1_3_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_25_cfg_vpcstx_gen4_preset7_attr == 18'd47558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_25_cfg_vpcstxdrv_levn_gen1_4_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_25_cfg_vpcstxdrv_levn_gen1_5_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_26_cfg_vpcstx_gen4_preset8_attr == 18'd31367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_26_cfg_vpcstxdrv_levn_gen1_6_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_26_cfg_vpcstxdrv_levn_gen1_7_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_27_cfg_vpcstx_gen4_preset9_attr == 18'd3017
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_27_cfg_vpcstxdrv_levn_gen1_8_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_27_cfg_vpcstxdrv_levn_gen1_9_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_28_cfg_vpcstx_preset0_attr == 18'd60032
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_28_cfg_vpcstxdrv_levn_gen2_0_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_28_cfg_vpcstxdrv_levn_gen2_1_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_29_cfg_vpcstx_preset1_attr == 18'd39872
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_29_cfg_vpcstxdrv_levn_gen2_10_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_29_cfg_vpcstxdrv_levn_gen2_11_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_2_cfg_vpcs_misc_attr == 32'd305419896
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_30_cfg_vpcstx_preset10_attr == 18'd80192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_30_cfg_vpcstxdrv_levn_gen2_12_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_30_cfg_vpcstxdrv_levn_gen2_13_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_31_cfg_vpcstx_preset2_attr == 18'd47936
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_31_cfg_vpcstxdrv_levn_gen2_14_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_31_cfg_vpcstxdrv_levn_gen2_15_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_32_cfg_vpcstx_preset3_attr == 18'd31808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_32_cfg_vpcstxdrv_levn_gen2_2_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_32_cfg_vpcstxdrv_levn_gen2_3_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_33_cfg_vpcstx_preset4_attr == 18'd3584
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_33_cfg_vpcstxdrv_levn_gen2_4_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_33_cfg_vpcstxdrv_levn_gen2_5_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_34_cfg_vpcstx_preset5_attr == 18'd3206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_34_cfg_vpcstxdrv_levn_gen2_6_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_34_cfg_vpcstxdrv_levn_gen2_7_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_35_cfg_vpcstx_preset6_attr == 18'd3143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_35_cfg_vpcstxdrv_levn_gen2_8_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_35_cfg_vpcstxdrv_levn_gen2_9_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_36_cfg_vpcstx_preset7_attr == 18'd47558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_levnm1_gen1_0_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_levnm1_gen1_1_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_txdrvslew_gen1_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_37_cfg_vpcstx_preset8_attr == 18'd31367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_levnm1_gen1_10_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_levnm1_gen1_11_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_txdrvslew_gen2_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_38_cfg_vpcstx_preset9_attr == 18'd3017
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_levnm1_gen1_12_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_levnm1_gen1_13_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_txdrvslew_gen3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_14_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_15_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_2_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_3_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_5_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_3_cfg_vpcsbist_gen_skp_delay_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_3_cfg_vpcsebuf_fifo_full_thr_attr == 7'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_3_cfg_vpcsebuf_fifo_full_thr_sris_attr == 7'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_3_cfg_vpcseios_det_en_attr == UX_PCS_LANE_Q0_REG_3_CFG_VPCSEIOS_DET_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_3_cfg_vpcsif_blockaligncontrolpolarity_attr == UX_PCS_LANE_Q0_REG_3_CFG_VPCSIF_BLOCKALIGNCONTROLPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_6_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_7_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_8_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_9_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen2_0_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen2_1_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_10_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_11_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_12_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_13_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_14_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_15_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_2_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_3_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_5_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_6_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_7_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_levnm1_gen2_8_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_levnm1_gen2_9_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_txdrvslew_gen4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_good_syncheader_align_dis_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSALIGN128B_GOOD_SYNCHEADER_ALIGN_DIS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_unalign_lb_en_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSALIGN128B_UNALIGN_LB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_unalign_lb_wait_cnt_thr_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_data_en_falling_dly_ovr_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_DATA_EN_FALLING_DLY_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_data_en_falling_dly_thr_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_enb_skp_add_when_skpos_is_24_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_ENB_SKP_ADD_WHEN_SKPOS_IS_24_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_clr_cnt_thr_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_mid_offset_thr_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_mid_offset_thr_ow_en_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_FIFO_RD_MID_OFFSET_THR_OW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_fifo_wr_mid_offset_thr_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_fifo_wr_mid_offset_thr_ow_en_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_FIFO_WR_MID_OFFSET_THR_OW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_det_en_rd_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_DET_EN_RD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_det_en_wr_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_DET_EN_WR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_force_en_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_FORCE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_5_cfg_vpcsif_txflow_force_on_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSIF_TXFLOW_FORCE_ON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_5_cfg_vpcsif_txflow_nodatavld_force_on_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSIF_TXFLOW_NODATAVLD_FORCE_ON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_5_cfg_vpcsroreg_ckgate_dsbl_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSROREG_CKGATE_DSBL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_5_cfg_vpcstbus_ckgate_dsbl_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSTBUS_CKGATE_DSBL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_6_cfg_vpcsbist_udp_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_7_cfg_vpcsbist_udp_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_8_cfg_vpcsebuf_fifo_mid_thr_attr == 7'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_8_cfg_vpcsebuf_fifo_mid_thr_sris_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_force_neg_disp_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_force_pos_disp_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_tx_force_err_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_8_cfg_vpcsif_idle_cntr_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_8_cfg_vpcsif_ovr_blockaligncontrol_attr == UX_PCS_LANE_Q0_REG_8_CFG_VPCSIF_OVR_BLOCKALIGNCONTROL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_8_cfg_vpcsif_ovr_blockaligncontrol_ena_attr == UX_PCS_LANE_Q0_REG_8_CFG_VPCSIF_OVR_BLOCKALIGNCONTROL_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_9_cfg_vpcsif_min_reset_cntr_max_attr == 11'd1000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_9_cfg_vpcsif_min_txidle_cntr_max_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_chng_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_CHNG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_ebuf_mode_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_EBUF_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_ebuf_mode_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_EBUF_MODE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_encodedecodebypass_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_ENCODEDECODEBYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_encodedecodebypass_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_ENCODEDECODEBYPASS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_getlocalpresetcoefficients_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_GETLOCALPRESETCOEFFICIENTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_getlocalpresetcoefficients_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_GETLOCALPRESETCOEFFICIENTS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_localpresetindex_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_localpresetindex_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOCALPRESETINDEX_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_lowpin_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOWPIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_lowpin_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOWPIN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_m2p_bus_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_M2P_BUS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_pclk_as_input_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_PCLK_AS_INPUT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane11.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_pclk_as_input_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_PCLK_AS_INPUT_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_m2p_bus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclk_rate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclk_rate_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLK_RATE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclkchangeack_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLKCHANGEACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclkchangeack_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLKCHANGEACK_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_phy_mode_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_phy_mode_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PHY_MODE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_powerdown_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_powerdown_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_POWERDOWN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rate_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RATE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rst_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rst_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RST_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rxelecidle_disable_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RXELECIDLE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rxelecidle_disable_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RXELECIDLE_DISABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxeqeval_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXEQEVAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxeqeval_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXEQEVAL_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpolarity_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpolarity_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPOLARITY_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpresethint_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpresethint_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPRESETHINT_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxstandby_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXSTANDBY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxstandby_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXSTANDBY_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxtermination_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXTERMINATION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxtermination_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXTERMINATION_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_srisenable_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_srisenable_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_SRISENABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcmnmode_disable_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCMNMODE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcmnmode_disable_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCMNMODE_DISABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcompliance_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCOMPLIANCE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcompliance_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCOMPLIANCE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdeemph_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDEEMPH_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdtctrx_lb_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDTCTRX_LB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdtctrx_lb_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDTCTRX_LB_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txelecidle_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txelecidle_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXELECIDLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txmargin_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txmargin_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXMARGIN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txoneszeros_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXONESZEROS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txoneszeros_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXONESZEROS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txdeemph_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txswing_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_TXSWING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txswing_ena_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_TXSWING_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_width_ena_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_WIDTH_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p1subentry_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P1SUBENTRY_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p1subexit_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P1SUBEXIT_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p2entry_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P2ENTRY_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p2exit_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P2EXIT_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatusgen_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUSGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxdetect_inpciep2_en_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXDETECT_INPCIEP2_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxpstate_p0s_en_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXPSTATE_P0S_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxstandby0en_in_rxeq_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXSTANDBY0EN_IN_RXEQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie5_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_usb1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_usb2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_tx_pcie1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie5_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_usb1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_usb2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_14_cfg_vpcslb_fe_attr == UX_PCS_LANE_Q0_REG_14_CFG_VPCSLB_FE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_14_cfg_vpcsmbusconv_illegal_rd_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_14_CFG_VPCSMBUSCONV_ILLEGAL_RD_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_15_cfg_vpcslfps_ctrl_p3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_illegal_wr_c_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_ILLEGAL_WR_C_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_illegal_wr_uc_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_ILLEGAL_WR_UC_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_ack_gen_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_ACK_GEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timeout_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_COMPL_TIMEOUT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timer_en_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_COMPL_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timer_max_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_gen_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_GEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timeout_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_TIMEOUT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timer_en_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timer_max_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_15_cfg_vpcsonezero_one_cntr_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_15_cfg_vpcstxdrv_usb_gen1_txdeemph_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSTXDRV_USB_GEN1_TXDEEMPH_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_16_cfg_vpcsonezero_zero_cntr_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_16_cfg_vpcstbus_addr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_16_cfg_vpcstx_gen4_preset0_attr == 18'd60032
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_16_cfg_vpcstxdrv_usb_gen1_txswing_attr == UX_PCS_LANE_Q0_REG_16_CFG_VPCSTXDRV_USB_GEN1_TXSWING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_17_cfg_vpcsspare0_attr == 32'd4294901760
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_18_cfg_vpcstx_gen4_preset1_attr == 18'd39872
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_18_cfg_vpcstx_localfs_attr == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_18_cfg_vpcstx_localg4fs_attr == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_19_cfg_vpcstx_gen4_preset10_attr == 18'd80192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_19_cfg_vpcstx_localg4lf_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_19_cfg_vpcstx_locallf_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_1_cfg_vcpsckgate_disable_attr == UX_PCS_LANE_Q0_REG_1_CFG_VCPSCKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_1_cfg_vpcs_if_clk_sel_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCS_IF_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_1_cfg_vpcsalign10b_lock_cnt_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_1_cfg_vpcsalign10b_unlock_cnt_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_1_cfg_vpcsalign128b_g3g4_skp_os_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSALIGN128B_G3G4_SKP_OS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_1_cfg_vpcsalign128b_usb2_ctrl_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_clr_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_en_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_hold_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_data_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_en_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_init_ctrl_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_INIT_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_init_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_insert_err_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_INSERT_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_skp_cnt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_1_cfg_vpcsebuf_reset_on_err_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSEBUF_RESET_ON_ERR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_20_cfg_vpcstx_gen4_preset2_attr == 18'd47936
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_20_cfg_vpcstxdrv_levn_gen1_0_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_20_cfg_vpcstxdrv_levn_gen1_1_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_21_cfg_vpcstx_gen4_preset3_attr == 18'd31808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_21_cfg_vpcstxdrv_levn_gen1_10_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_21_cfg_vpcstxdrv_levn_gen1_11_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_22_cfg_vpcstx_gen4_preset4_attr == 18'd3584
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_22_cfg_vpcstxdrv_levn_gen1_12_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_22_cfg_vpcstxdrv_levn_gen1_13_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_23_cfg_vpcstx_gen4_preset5_attr == 18'd3206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_23_cfg_vpcstxdrv_levn_gen1_14_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_23_cfg_vpcstxdrv_levn_gen1_15_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_24_cfg_vpcstx_gen4_preset6_attr == 18'd3143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_24_cfg_vpcstxdrv_levn_gen1_2_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_24_cfg_vpcstxdrv_levn_gen1_3_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_25_cfg_vpcstx_gen4_preset7_attr == 18'd47558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_25_cfg_vpcstxdrv_levn_gen1_4_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_25_cfg_vpcstxdrv_levn_gen1_5_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_26_cfg_vpcstx_gen4_preset8_attr == 18'd31367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_26_cfg_vpcstxdrv_levn_gen1_6_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_26_cfg_vpcstxdrv_levn_gen1_7_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_27_cfg_vpcstx_gen4_preset9_attr == 18'd3017
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_27_cfg_vpcstxdrv_levn_gen1_8_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_27_cfg_vpcstxdrv_levn_gen1_9_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_28_cfg_vpcstx_preset0_attr == 18'd60032
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_28_cfg_vpcstxdrv_levn_gen2_0_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_28_cfg_vpcstxdrv_levn_gen2_1_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_29_cfg_vpcstx_preset1_attr == 18'd39872
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_29_cfg_vpcstxdrv_levn_gen2_10_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_29_cfg_vpcstxdrv_levn_gen2_11_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_2_cfg_vpcs_misc_attr == 32'd305419896
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_30_cfg_vpcstx_preset10_attr == 18'd80192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_30_cfg_vpcstxdrv_levn_gen2_12_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_30_cfg_vpcstxdrv_levn_gen2_13_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_31_cfg_vpcstx_preset2_attr == 18'd47936
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_31_cfg_vpcstxdrv_levn_gen2_14_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_31_cfg_vpcstxdrv_levn_gen2_15_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_32_cfg_vpcstx_preset3_attr == 18'd31808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_32_cfg_vpcstxdrv_levn_gen2_2_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_32_cfg_vpcstxdrv_levn_gen2_3_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_33_cfg_vpcstx_preset4_attr == 18'd3584
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_33_cfg_vpcstxdrv_levn_gen2_4_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_33_cfg_vpcstxdrv_levn_gen2_5_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_34_cfg_vpcstx_preset5_attr == 18'd3206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_34_cfg_vpcstxdrv_levn_gen2_6_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_34_cfg_vpcstxdrv_levn_gen2_7_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_35_cfg_vpcstx_preset6_attr == 18'd3143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_35_cfg_vpcstxdrv_levn_gen2_8_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_35_cfg_vpcstxdrv_levn_gen2_9_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_36_cfg_vpcstx_preset7_attr == 18'd47558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_levnm1_gen1_0_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_levnm1_gen1_1_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_txdrvslew_gen1_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_37_cfg_vpcstx_preset8_attr == 18'd31367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_levnm1_gen1_10_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_levnm1_gen1_11_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_txdrvslew_gen2_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_38_cfg_vpcstx_preset9_attr == 18'd3017
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_levnm1_gen1_12_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_levnm1_gen1_13_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_txdrvslew_gen3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_14_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_15_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_2_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_3_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_5_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_3_cfg_vpcsbist_gen_skp_delay_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_3_cfg_vpcsebuf_fifo_full_thr_attr == 7'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_3_cfg_vpcsebuf_fifo_full_thr_sris_attr == 7'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_3_cfg_vpcseios_det_en_attr == UX_PCS_LANE_Q0_REG_3_CFG_VPCSEIOS_DET_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_3_cfg_vpcsif_blockaligncontrolpolarity_attr == UX_PCS_LANE_Q0_REG_3_CFG_VPCSIF_BLOCKALIGNCONTROLPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_6_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_7_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_8_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_9_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen2_0_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen2_1_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_10_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_11_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_12_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_13_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_14_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_15_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_2_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_3_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_5_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_6_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_7_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_levnm1_gen2_8_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_levnm1_gen2_9_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_txdrvslew_gen4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_good_syncheader_align_dis_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSALIGN128B_GOOD_SYNCHEADER_ALIGN_DIS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_unalign_lb_en_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSALIGN128B_UNALIGN_LB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_unalign_lb_wait_cnt_thr_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_data_en_falling_dly_ovr_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_DATA_EN_FALLING_DLY_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_data_en_falling_dly_thr_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_enb_skp_add_when_skpos_is_24_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_ENB_SKP_ADD_WHEN_SKPOS_IS_24_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_clr_cnt_thr_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_mid_offset_thr_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_mid_offset_thr_ow_en_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_FIFO_RD_MID_OFFSET_THR_OW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_fifo_wr_mid_offset_thr_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_fifo_wr_mid_offset_thr_ow_en_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_FIFO_WR_MID_OFFSET_THR_OW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_det_en_rd_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_DET_EN_RD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_det_en_wr_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_DET_EN_WR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_force_en_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_FORCE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_5_cfg_vpcsif_txflow_force_on_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSIF_TXFLOW_FORCE_ON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_5_cfg_vpcsif_txflow_nodatavld_force_on_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSIF_TXFLOW_NODATAVLD_FORCE_ON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_5_cfg_vpcsroreg_ckgate_dsbl_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSROREG_CKGATE_DSBL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_5_cfg_vpcstbus_ckgate_dsbl_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSTBUS_CKGATE_DSBL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_6_cfg_vpcsbist_udp_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_7_cfg_vpcsbist_udp_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_8_cfg_vpcsebuf_fifo_mid_thr_attr == 7'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_8_cfg_vpcsebuf_fifo_mid_thr_sris_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_force_neg_disp_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_force_pos_disp_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_tx_force_err_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_8_cfg_vpcsif_idle_cntr_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_8_cfg_vpcsif_ovr_blockaligncontrol_attr == UX_PCS_LANE_Q0_REG_8_CFG_VPCSIF_OVR_BLOCKALIGNCONTROL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_8_cfg_vpcsif_ovr_blockaligncontrol_ena_attr == UX_PCS_LANE_Q0_REG_8_CFG_VPCSIF_OVR_BLOCKALIGNCONTROL_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_9_cfg_vpcsif_min_reset_cntr_max_attr == 11'd1000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_9_cfg_vpcsif_min_txidle_cntr_max_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_chng_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_CHNG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_ebuf_mode_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_EBUF_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_ebuf_mode_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_EBUF_MODE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_encodedecodebypass_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_ENCODEDECODEBYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_encodedecodebypass_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_ENCODEDECODEBYPASS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_getlocalpresetcoefficients_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_GETLOCALPRESETCOEFFICIENTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_getlocalpresetcoefficients_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_GETLOCALPRESETCOEFFICIENTS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_localpresetindex_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_localpresetindex_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOCALPRESETINDEX_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_lowpin_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOWPIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_lowpin_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOWPIN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_m2p_bus_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_M2P_BUS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_pclk_as_input_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_PCLK_AS_INPUT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane12.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_pclk_as_input_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_PCLK_AS_INPUT_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_m2p_bus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclk_rate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclk_rate_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLK_RATE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclkchangeack_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLKCHANGEACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclkchangeack_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLKCHANGEACK_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_phy_mode_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_phy_mode_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PHY_MODE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_powerdown_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_powerdown_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_POWERDOWN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rate_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RATE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rst_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rst_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RST_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rxelecidle_disable_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RXELECIDLE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rxelecidle_disable_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RXELECIDLE_DISABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxeqeval_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXEQEVAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxeqeval_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXEQEVAL_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpolarity_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpolarity_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPOLARITY_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpresethint_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpresethint_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPRESETHINT_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxstandby_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXSTANDBY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxstandby_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXSTANDBY_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxtermination_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXTERMINATION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxtermination_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXTERMINATION_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_srisenable_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_srisenable_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_SRISENABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcmnmode_disable_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCMNMODE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcmnmode_disable_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCMNMODE_DISABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcompliance_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCOMPLIANCE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcompliance_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCOMPLIANCE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdeemph_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDEEMPH_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdtctrx_lb_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDTCTRX_LB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdtctrx_lb_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDTCTRX_LB_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txelecidle_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txelecidle_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXELECIDLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txmargin_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txmargin_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXMARGIN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txoneszeros_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXONESZEROS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txoneszeros_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXONESZEROS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txdeemph_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txswing_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_TXSWING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txswing_ena_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_TXSWING_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_width_ena_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_WIDTH_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p1subentry_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P1SUBENTRY_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p1subexit_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P1SUBEXIT_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p2entry_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P2ENTRY_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p2exit_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P2EXIT_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatusgen_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUSGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxdetect_inpciep2_en_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXDETECT_INPCIEP2_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxpstate_p0s_en_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXPSTATE_P0S_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxstandby0en_in_rxeq_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXSTANDBY0EN_IN_RXEQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie5_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_usb1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_usb2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_tx_pcie1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie5_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_usb1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_usb2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_14_cfg_vpcslb_fe_attr == UX_PCS_LANE_Q0_REG_14_CFG_VPCSLB_FE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_14_cfg_vpcsmbusconv_illegal_rd_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_14_CFG_VPCSMBUSCONV_ILLEGAL_RD_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_15_cfg_vpcslfps_ctrl_p3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_illegal_wr_c_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_ILLEGAL_WR_C_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_illegal_wr_uc_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_ILLEGAL_WR_UC_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_ack_gen_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_ACK_GEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timeout_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_COMPL_TIMEOUT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timer_en_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_COMPL_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timer_max_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_gen_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_GEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timeout_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_TIMEOUT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timer_en_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timer_max_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_15_cfg_vpcsonezero_one_cntr_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_15_cfg_vpcstxdrv_usb_gen1_txdeemph_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSTXDRV_USB_GEN1_TXDEEMPH_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_16_cfg_vpcsonezero_zero_cntr_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_16_cfg_vpcstbus_addr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_16_cfg_vpcstx_gen4_preset0_attr == 18'd60032
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_16_cfg_vpcstxdrv_usb_gen1_txswing_attr == UX_PCS_LANE_Q0_REG_16_CFG_VPCSTXDRV_USB_GEN1_TXSWING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_17_cfg_vpcsspare0_attr == 32'd4294901760
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_18_cfg_vpcstx_gen4_preset1_attr == 18'd39872
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_18_cfg_vpcstx_localfs_attr == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_18_cfg_vpcstx_localg4fs_attr == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_19_cfg_vpcstx_gen4_preset10_attr == 18'd80192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_19_cfg_vpcstx_localg4lf_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_19_cfg_vpcstx_locallf_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_1_cfg_vcpsckgate_disable_attr == UX_PCS_LANE_Q0_REG_1_CFG_VCPSCKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_1_cfg_vpcs_if_clk_sel_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCS_IF_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_1_cfg_vpcsalign10b_lock_cnt_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_1_cfg_vpcsalign10b_unlock_cnt_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_1_cfg_vpcsalign128b_g3g4_skp_os_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSALIGN128B_G3G4_SKP_OS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_1_cfg_vpcsalign128b_usb2_ctrl_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_clr_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_en_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_hold_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_data_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_en_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_init_ctrl_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_INIT_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_init_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_insert_err_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_INSERT_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_skp_cnt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_1_cfg_vpcsebuf_reset_on_err_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSEBUF_RESET_ON_ERR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_20_cfg_vpcstx_gen4_preset2_attr == 18'd47936
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_20_cfg_vpcstxdrv_levn_gen1_0_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_20_cfg_vpcstxdrv_levn_gen1_1_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_21_cfg_vpcstx_gen4_preset3_attr == 18'd31808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_21_cfg_vpcstxdrv_levn_gen1_10_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_21_cfg_vpcstxdrv_levn_gen1_11_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_22_cfg_vpcstx_gen4_preset4_attr == 18'd3584
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_22_cfg_vpcstxdrv_levn_gen1_12_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_22_cfg_vpcstxdrv_levn_gen1_13_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_23_cfg_vpcstx_gen4_preset5_attr == 18'd3206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_23_cfg_vpcstxdrv_levn_gen1_14_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_23_cfg_vpcstxdrv_levn_gen1_15_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_24_cfg_vpcstx_gen4_preset6_attr == 18'd3143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_24_cfg_vpcstxdrv_levn_gen1_2_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_24_cfg_vpcstxdrv_levn_gen1_3_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_25_cfg_vpcstx_gen4_preset7_attr == 18'd47558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_25_cfg_vpcstxdrv_levn_gen1_4_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_25_cfg_vpcstxdrv_levn_gen1_5_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_26_cfg_vpcstx_gen4_preset8_attr == 18'd31367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_26_cfg_vpcstxdrv_levn_gen1_6_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_26_cfg_vpcstxdrv_levn_gen1_7_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_27_cfg_vpcstx_gen4_preset9_attr == 18'd3017
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_27_cfg_vpcstxdrv_levn_gen1_8_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_27_cfg_vpcstxdrv_levn_gen1_9_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_28_cfg_vpcstx_preset0_attr == 18'd60032
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_28_cfg_vpcstxdrv_levn_gen2_0_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_28_cfg_vpcstxdrv_levn_gen2_1_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_29_cfg_vpcstx_preset1_attr == 18'd39872
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_29_cfg_vpcstxdrv_levn_gen2_10_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_29_cfg_vpcstxdrv_levn_gen2_11_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_2_cfg_vpcs_misc_attr == 32'd305419896
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_30_cfg_vpcstx_preset10_attr == 18'd80192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_30_cfg_vpcstxdrv_levn_gen2_12_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_30_cfg_vpcstxdrv_levn_gen2_13_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_31_cfg_vpcstx_preset2_attr == 18'd47936
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_31_cfg_vpcstxdrv_levn_gen2_14_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_31_cfg_vpcstxdrv_levn_gen2_15_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_32_cfg_vpcstx_preset3_attr == 18'd31808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_32_cfg_vpcstxdrv_levn_gen2_2_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_32_cfg_vpcstxdrv_levn_gen2_3_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_33_cfg_vpcstx_preset4_attr == 18'd3584
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_33_cfg_vpcstxdrv_levn_gen2_4_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_33_cfg_vpcstxdrv_levn_gen2_5_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_34_cfg_vpcstx_preset5_attr == 18'd3206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_34_cfg_vpcstxdrv_levn_gen2_6_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_34_cfg_vpcstxdrv_levn_gen2_7_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_35_cfg_vpcstx_preset6_attr == 18'd3143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_35_cfg_vpcstxdrv_levn_gen2_8_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_35_cfg_vpcstxdrv_levn_gen2_9_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_36_cfg_vpcstx_preset7_attr == 18'd47558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_levnm1_gen1_0_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_levnm1_gen1_1_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_txdrvslew_gen1_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_37_cfg_vpcstx_preset8_attr == 18'd31367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_levnm1_gen1_10_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_levnm1_gen1_11_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_txdrvslew_gen2_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_38_cfg_vpcstx_preset9_attr == 18'd3017
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_levnm1_gen1_12_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_levnm1_gen1_13_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_txdrvslew_gen3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_14_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_15_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_2_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_3_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_5_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_3_cfg_vpcsbist_gen_skp_delay_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_3_cfg_vpcsebuf_fifo_full_thr_attr == 7'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_3_cfg_vpcsebuf_fifo_full_thr_sris_attr == 7'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_3_cfg_vpcseios_det_en_attr == UX_PCS_LANE_Q0_REG_3_CFG_VPCSEIOS_DET_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_3_cfg_vpcsif_blockaligncontrolpolarity_attr == UX_PCS_LANE_Q0_REG_3_CFG_VPCSIF_BLOCKALIGNCONTROLPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_6_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_7_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_8_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_9_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen2_0_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen2_1_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_10_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_11_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_12_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_13_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_14_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_15_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_2_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_3_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_5_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_6_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_7_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_levnm1_gen2_8_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_levnm1_gen2_9_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_txdrvslew_gen4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_good_syncheader_align_dis_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSALIGN128B_GOOD_SYNCHEADER_ALIGN_DIS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_unalign_lb_en_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSALIGN128B_UNALIGN_LB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_unalign_lb_wait_cnt_thr_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_data_en_falling_dly_ovr_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_DATA_EN_FALLING_DLY_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_data_en_falling_dly_thr_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_enb_skp_add_when_skpos_is_24_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_ENB_SKP_ADD_WHEN_SKPOS_IS_24_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_clr_cnt_thr_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_mid_offset_thr_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_mid_offset_thr_ow_en_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_FIFO_RD_MID_OFFSET_THR_OW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_fifo_wr_mid_offset_thr_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_fifo_wr_mid_offset_thr_ow_en_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_FIFO_WR_MID_OFFSET_THR_OW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_det_en_rd_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_DET_EN_RD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_det_en_wr_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_DET_EN_WR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_force_en_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_FORCE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_5_cfg_vpcsif_txflow_force_on_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSIF_TXFLOW_FORCE_ON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_5_cfg_vpcsif_txflow_nodatavld_force_on_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSIF_TXFLOW_NODATAVLD_FORCE_ON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_5_cfg_vpcsroreg_ckgate_dsbl_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSROREG_CKGATE_DSBL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_5_cfg_vpcstbus_ckgate_dsbl_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSTBUS_CKGATE_DSBL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_6_cfg_vpcsbist_udp_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_7_cfg_vpcsbist_udp_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_8_cfg_vpcsebuf_fifo_mid_thr_attr == 7'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_8_cfg_vpcsebuf_fifo_mid_thr_sris_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_force_neg_disp_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_force_pos_disp_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_tx_force_err_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_8_cfg_vpcsif_idle_cntr_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_8_cfg_vpcsif_ovr_blockaligncontrol_attr == UX_PCS_LANE_Q0_REG_8_CFG_VPCSIF_OVR_BLOCKALIGNCONTROL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_8_cfg_vpcsif_ovr_blockaligncontrol_ena_attr == UX_PCS_LANE_Q0_REG_8_CFG_VPCSIF_OVR_BLOCKALIGNCONTROL_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_9_cfg_vpcsif_min_reset_cntr_max_attr == 11'd1000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_9_cfg_vpcsif_min_txidle_cntr_max_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_chng_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_CHNG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_ebuf_mode_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_EBUF_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_ebuf_mode_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_EBUF_MODE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_encodedecodebypass_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_ENCODEDECODEBYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_encodedecodebypass_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_ENCODEDECODEBYPASS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_getlocalpresetcoefficients_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_GETLOCALPRESETCOEFFICIENTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_getlocalpresetcoefficients_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_GETLOCALPRESETCOEFFICIENTS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_localpresetindex_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_localpresetindex_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOCALPRESETINDEX_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_lowpin_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOWPIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_lowpin_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOWPIN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_m2p_bus_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_M2P_BUS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_pclk_as_input_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_PCLK_AS_INPUT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane13.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_pclk_as_input_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_PCLK_AS_INPUT_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_m2p_bus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclk_rate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclk_rate_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLK_RATE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclkchangeack_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLKCHANGEACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclkchangeack_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLKCHANGEACK_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_phy_mode_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_phy_mode_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PHY_MODE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_powerdown_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_powerdown_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_POWERDOWN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rate_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RATE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rst_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rst_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RST_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rxelecidle_disable_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RXELECIDLE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rxelecidle_disable_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RXELECIDLE_DISABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxeqeval_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXEQEVAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxeqeval_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXEQEVAL_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpolarity_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpolarity_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPOLARITY_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpresethint_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpresethint_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPRESETHINT_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxstandby_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXSTANDBY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxstandby_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXSTANDBY_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxtermination_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXTERMINATION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxtermination_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXTERMINATION_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_srisenable_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_srisenable_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_SRISENABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcmnmode_disable_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCMNMODE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcmnmode_disable_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCMNMODE_DISABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcompliance_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCOMPLIANCE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcompliance_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCOMPLIANCE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdeemph_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDEEMPH_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdtctrx_lb_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDTCTRX_LB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdtctrx_lb_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDTCTRX_LB_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txelecidle_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txelecidle_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXELECIDLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txmargin_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txmargin_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXMARGIN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txoneszeros_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXONESZEROS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txoneszeros_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXONESZEROS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txdeemph_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txswing_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_TXSWING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txswing_ena_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_TXSWING_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_width_ena_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_WIDTH_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p1subentry_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P1SUBENTRY_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p1subexit_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P1SUBEXIT_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p2entry_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P2ENTRY_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p2exit_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P2EXIT_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatusgen_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUSGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxdetect_inpciep2_en_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXDETECT_INPCIEP2_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxpstate_p0s_en_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXPSTATE_P0S_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxstandby0en_in_rxeq_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXSTANDBY0EN_IN_RXEQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie5_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_usb1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_usb2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_tx_pcie1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie5_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_usb1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_usb2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_14_cfg_vpcslb_fe_attr == UX_PCS_LANE_Q0_REG_14_CFG_VPCSLB_FE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_14_cfg_vpcsmbusconv_illegal_rd_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_14_CFG_VPCSMBUSCONV_ILLEGAL_RD_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_15_cfg_vpcslfps_ctrl_p3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_illegal_wr_c_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_ILLEGAL_WR_C_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_illegal_wr_uc_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_ILLEGAL_WR_UC_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_ack_gen_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_ACK_GEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timeout_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_COMPL_TIMEOUT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timer_en_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_COMPL_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timer_max_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_gen_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_GEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timeout_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_TIMEOUT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timer_en_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timer_max_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_15_cfg_vpcsonezero_one_cntr_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_15_cfg_vpcstxdrv_usb_gen1_txdeemph_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSTXDRV_USB_GEN1_TXDEEMPH_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_16_cfg_vpcsonezero_zero_cntr_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_16_cfg_vpcstbus_addr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_16_cfg_vpcstx_gen4_preset0_attr == 18'd60032
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_16_cfg_vpcstxdrv_usb_gen1_txswing_attr == UX_PCS_LANE_Q0_REG_16_CFG_VPCSTXDRV_USB_GEN1_TXSWING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_17_cfg_vpcsspare0_attr == 32'd4294901760
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_18_cfg_vpcstx_gen4_preset1_attr == 18'd39872
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_18_cfg_vpcstx_localfs_attr == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_18_cfg_vpcstx_localg4fs_attr == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_19_cfg_vpcstx_gen4_preset10_attr == 18'd80192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_19_cfg_vpcstx_localg4lf_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_19_cfg_vpcstx_locallf_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_1_cfg_vcpsckgate_disable_attr == UX_PCS_LANE_Q0_REG_1_CFG_VCPSCKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_1_cfg_vpcs_if_clk_sel_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCS_IF_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_1_cfg_vpcsalign10b_lock_cnt_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_1_cfg_vpcsalign10b_unlock_cnt_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_1_cfg_vpcsalign128b_g3g4_skp_os_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSALIGN128B_G3G4_SKP_OS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_1_cfg_vpcsalign128b_usb2_ctrl_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_clr_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_en_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_hold_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_data_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_en_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_init_ctrl_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_INIT_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_init_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_insert_err_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_INSERT_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_skp_cnt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_1_cfg_vpcsebuf_reset_on_err_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSEBUF_RESET_ON_ERR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_20_cfg_vpcstx_gen4_preset2_attr == 18'd47936
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_20_cfg_vpcstxdrv_levn_gen1_0_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_20_cfg_vpcstxdrv_levn_gen1_1_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_21_cfg_vpcstx_gen4_preset3_attr == 18'd31808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_21_cfg_vpcstxdrv_levn_gen1_10_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_21_cfg_vpcstxdrv_levn_gen1_11_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_22_cfg_vpcstx_gen4_preset4_attr == 18'd3584
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_22_cfg_vpcstxdrv_levn_gen1_12_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_22_cfg_vpcstxdrv_levn_gen1_13_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_23_cfg_vpcstx_gen4_preset5_attr == 18'd3206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_23_cfg_vpcstxdrv_levn_gen1_14_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_23_cfg_vpcstxdrv_levn_gen1_15_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_24_cfg_vpcstx_gen4_preset6_attr == 18'd3143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_24_cfg_vpcstxdrv_levn_gen1_2_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_24_cfg_vpcstxdrv_levn_gen1_3_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_25_cfg_vpcstx_gen4_preset7_attr == 18'd47558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_25_cfg_vpcstxdrv_levn_gen1_4_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_25_cfg_vpcstxdrv_levn_gen1_5_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_26_cfg_vpcstx_gen4_preset8_attr == 18'd31367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_26_cfg_vpcstxdrv_levn_gen1_6_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_26_cfg_vpcstxdrv_levn_gen1_7_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_27_cfg_vpcstx_gen4_preset9_attr == 18'd3017
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_27_cfg_vpcstxdrv_levn_gen1_8_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_27_cfg_vpcstxdrv_levn_gen1_9_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_28_cfg_vpcstx_preset0_attr == 18'd60032
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_28_cfg_vpcstxdrv_levn_gen2_0_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_28_cfg_vpcstxdrv_levn_gen2_1_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_29_cfg_vpcstx_preset1_attr == 18'd39872
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_29_cfg_vpcstxdrv_levn_gen2_10_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_29_cfg_vpcstxdrv_levn_gen2_11_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_2_cfg_vpcs_misc_attr == 32'd305419896
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_30_cfg_vpcstx_preset10_attr == 18'd80192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_30_cfg_vpcstxdrv_levn_gen2_12_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_30_cfg_vpcstxdrv_levn_gen2_13_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_31_cfg_vpcstx_preset2_attr == 18'd47936
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_31_cfg_vpcstxdrv_levn_gen2_14_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_31_cfg_vpcstxdrv_levn_gen2_15_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_32_cfg_vpcstx_preset3_attr == 18'd31808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_32_cfg_vpcstxdrv_levn_gen2_2_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_32_cfg_vpcstxdrv_levn_gen2_3_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_33_cfg_vpcstx_preset4_attr == 18'd3584
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_33_cfg_vpcstxdrv_levn_gen2_4_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_33_cfg_vpcstxdrv_levn_gen2_5_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_34_cfg_vpcstx_preset5_attr == 18'd3206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_34_cfg_vpcstxdrv_levn_gen2_6_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_34_cfg_vpcstxdrv_levn_gen2_7_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_35_cfg_vpcstx_preset6_attr == 18'd3143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_35_cfg_vpcstxdrv_levn_gen2_8_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_35_cfg_vpcstxdrv_levn_gen2_9_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_36_cfg_vpcstx_preset7_attr == 18'd47558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_levnm1_gen1_0_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_levnm1_gen1_1_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_txdrvslew_gen1_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_37_cfg_vpcstx_preset8_attr == 18'd31367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_levnm1_gen1_10_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_levnm1_gen1_11_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_txdrvslew_gen2_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_38_cfg_vpcstx_preset9_attr == 18'd3017
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_levnm1_gen1_12_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_levnm1_gen1_13_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_txdrvslew_gen3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_14_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_15_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_2_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_3_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_5_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_3_cfg_vpcsbist_gen_skp_delay_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_3_cfg_vpcsebuf_fifo_full_thr_attr == 7'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_3_cfg_vpcsebuf_fifo_full_thr_sris_attr == 7'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_3_cfg_vpcseios_det_en_attr == UX_PCS_LANE_Q0_REG_3_CFG_VPCSEIOS_DET_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_3_cfg_vpcsif_blockaligncontrolpolarity_attr == UX_PCS_LANE_Q0_REG_3_CFG_VPCSIF_BLOCKALIGNCONTROLPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_6_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_7_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_8_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_9_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen2_0_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen2_1_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_10_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_11_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_12_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_13_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_14_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_15_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_2_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_3_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_5_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_6_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_7_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_levnm1_gen2_8_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_levnm1_gen2_9_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_txdrvslew_gen4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_good_syncheader_align_dis_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSALIGN128B_GOOD_SYNCHEADER_ALIGN_DIS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_unalign_lb_en_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSALIGN128B_UNALIGN_LB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_unalign_lb_wait_cnt_thr_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_data_en_falling_dly_ovr_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_DATA_EN_FALLING_DLY_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_data_en_falling_dly_thr_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_enb_skp_add_when_skpos_is_24_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_ENB_SKP_ADD_WHEN_SKPOS_IS_24_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_clr_cnt_thr_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_mid_offset_thr_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_mid_offset_thr_ow_en_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_FIFO_RD_MID_OFFSET_THR_OW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_fifo_wr_mid_offset_thr_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_fifo_wr_mid_offset_thr_ow_en_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_FIFO_WR_MID_OFFSET_THR_OW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_det_en_rd_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_DET_EN_RD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_det_en_wr_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_DET_EN_WR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_force_en_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_FORCE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_5_cfg_vpcsif_txflow_force_on_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSIF_TXFLOW_FORCE_ON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_5_cfg_vpcsif_txflow_nodatavld_force_on_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSIF_TXFLOW_NODATAVLD_FORCE_ON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_5_cfg_vpcsroreg_ckgate_dsbl_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSROREG_CKGATE_DSBL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_5_cfg_vpcstbus_ckgate_dsbl_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSTBUS_CKGATE_DSBL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_6_cfg_vpcsbist_udp_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_7_cfg_vpcsbist_udp_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_8_cfg_vpcsebuf_fifo_mid_thr_attr == 7'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_8_cfg_vpcsebuf_fifo_mid_thr_sris_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_force_neg_disp_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_force_pos_disp_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_tx_force_err_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_8_cfg_vpcsif_idle_cntr_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_8_cfg_vpcsif_ovr_blockaligncontrol_attr == UX_PCS_LANE_Q0_REG_8_CFG_VPCSIF_OVR_BLOCKALIGNCONTROL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_8_cfg_vpcsif_ovr_blockaligncontrol_ena_attr == UX_PCS_LANE_Q0_REG_8_CFG_VPCSIF_OVR_BLOCKALIGNCONTROL_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_9_cfg_vpcsif_min_reset_cntr_max_attr == 11'd1000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_9_cfg_vpcsif_min_txidle_cntr_max_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_chng_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_CHNG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_ebuf_mode_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_EBUF_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_ebuf_mode_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_EBUF_MODE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_encodedecodebypass_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_ENCODEDECODEBYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_encodedecodebypass_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_ENCODEDECODEBYPASS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_getlocalpresetcoefficients_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_GETLOCALPRESETCOEFFICIENTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_getlocalpresetcoefficients_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_GETLOCALPRESETCOEFFICIENTS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_localpresetindex_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_localpresetindex_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOCALPRESETINDEX_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_lowpin_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOWPIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_lowpin_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOWPIN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_m2p_bus_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_M2P_BUS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_pclk_as_input_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_PCLK_AS_INPUT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane14.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_pclk_as_input_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_PCLK_AS_INPUT_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_m2p_bus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclk_rate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclk_rate_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLK_RATE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclkchangeack_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLKCHANGEACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclkchangeack_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLKCHANGEACK_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_phy_mode_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_phy_mode_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PHY_MODE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_powerdown_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_powerdown_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_POWERDOWN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rate_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RATE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rst_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rst_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RST_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rxelecidle_disable_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RXELECIDLE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rxelecidle_disable_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RXELECIDLE_DISABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxeqeval_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXEQEVAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxeqeval_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXEQEVAL_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpolarity_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpolarity_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPOLARITY_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpresethint_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpresethint_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPRESETHINT_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxstandby_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXSTANDBY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxstandby_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXSTANDBY_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxtermination_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXTERMINATION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxtermination_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXTERMINATION_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_srisenable_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_srisenable_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_SRISENABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcmnmode_disable_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCMNMODE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcmnmode_disable_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCMNMODE_DISABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcompliance_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCOMPLIANCE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcompliance_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCOMPLIANCE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdeemph_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDEEMPH_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdtctrx_lb_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDTCTRX_LB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdtctrx_lb_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDTCTRX_LB_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txelecidle_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txelecidle_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXELECIDLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txmargin_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txmargin_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXMARGIN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txoneszeros_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXONESZEROS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txoneszeros_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXONESZEROS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txdeemph_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txswing_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_TXSWING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txswing_ena_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_TXSWING_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_width_ena_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_WIDTH_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p1subentry_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P1SUBENTRY_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p1subexit_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P1SUBEXIT_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p2entry_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P2ENTRY_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p2exit_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P2EXIT_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatusgen_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUSGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxdetect_inpciep2_en_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXDETECT_INPCIEP2_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxpstate_p0s_en_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXPSTATE_P0S_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxstandby0en_in_rxeq_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXSTANDBY0EN_IN_RXEQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie5_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_usb1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_usb2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_tx_pcie1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie5_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_usb1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_usb2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_14_cfg_vpcslb_fe_attr == UX_PCS_LANE_Q0_REG_14_CFG_VPCSLB_FE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_14_cfg_vpcsmbusconv_illegal_rd_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_14_CFG_VPCSMBUSCONV_ILLEGAL_RD_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_15_cfg_vpcslfps_ctrl_p3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_illegal_wr_c_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_ILLEGAL_WR_C_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_illegal_wr_uc_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_ILLEGAL_WR_UC_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_ack_gen_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_ACK_GEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timeout_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_COMPL_TIMEOUT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timer_en_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_COMPL_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timer_max_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_gen_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_GEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timeout_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_TIMEOUT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timer_en_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timer_max_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_15_cfg_vpcsonezero_one_cntr_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_15_cfg_vpcstxdrv_usb_gen1_txdeemph_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSTXDRV_USB_GEN1_TXDEEMPH_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_16_cfg_vpcsonezero_zero_cntr_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_16_cfg_vpcstbus_addr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_16_cfg_vpcstx_gen4_preset0_attr == 18'd60032
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_16_cfg_vpcstxdrv_usb_gen1_txswing_attr == UX_PCS_LANE_Q0_REG_16_CFG_VPCSTXDRV_USB_GEN1_TXSWING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_17_cfg_vpcsspare0_attr == 32'd4294901760
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_18_cfg_vpcstx_gen4_preset1_attr == 18'd39872
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_18_cfg_vpcstx_localfs_attr == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_18_cfg_vpcstx_localg4fs_attr == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_19_cfg_vpcstx_gen4_preset10_attr == 18'd80192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_19_cfg_vpcstx_localg4lf_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_19_cfg_vpcstx_locallf_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_1_cfg_vcpsckgate_disable_attr == UX_PCS_LANE_Q0_REG_1_CFG_VCPSCKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_1_cfg_vpcs_if_clk_sel_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCS_IF_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_1_cfg_vpcsalign10b_lock_cnt_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_1_cfg_vpcsalign10b_unlock_cnt_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_1_cfg_vpcsalign128b_g3g4_skp_os_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSALIGN128B_G3G4_SKP_OS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_1_cfg_vpcsalign128b_usb2_ctrl_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_clr_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_en_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_hold_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_data_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_en_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_init_ctrl_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_INIT_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_init_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_insert_err_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_INSERT_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_skp_cnt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_1_cfg_vpcsebuf_reset_on_err_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSEBUF_RESET_ON_ERR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_20_cfg_vpcstx_gen4_preset2_attr == 18'd47936
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_20_cfg_vpcstxdrv_levn_gen1_0_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_20_cfg_vpcstxdrv_levn_gen1_1_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_21_cfg_vpcstx_gen4_preset3_attr == 18'd31808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_21_cfg_vpcstxdrv_levn_gen1_10_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_21_cfg_vpcstxdrv_levn_gen1_11_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_22_cfg_vpcstx_gen4_preset4_attr == 18'd3584
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_22_cfg_vpcstxdrv_levn_gen1_12_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_22_cfg_vpcstxdrv_levn_gen1_13_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_23_cfg_vpcstx_gen4_preset5_attr == 18'd3206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_23_cfg_vpcstxdrv_levn_gen1_14_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_23_cfg_vpcstxdrv_levn_gen1_15_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_24_cfg_vpcstx_gen4_preset6_attr == 18'd3143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_24_cfg_vpcstxdrv_levn_gen1_2_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_24_cfg_vpcstxdrv_levn_gen1_3_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_25_cfg_vpcstx_gen4_preset7_attr == 18'd47558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_25_cfg_vpcstxdrv_levn_gen1_4_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_25_cfg_vpcstxdrv_levn_gen1_5_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_26_cfg_vpcstx_gen4_preset8_attr == 18'd31367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_26_cfg_vpcstxdrv_levn_gen1_6_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_26_cfg_vpcstxdrv_levn_gen1_7_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_27_cfg_vpcstx_gen4_preset9_attr == 18'd3017
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_27_cfg_vpcstxdrv_levn_gen1_8_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_27_cfg_vpcstxdrv_levn_gen1_9_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_28_cfg_vpcstx_preset0_attr == 18'd60032
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_28_cfg_vpcstxdrv_levn_gen2_0_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_28_cfg_vpcstxdrv_levn_gen2_1_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_29_cfg_vpcstx_preset1_attr == 18'd39872
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_29_cfg_vpcstxdrv_levn_gen2_10_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_29_cfg_vpcstxdrv_levn_gen2_11_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_2_cfg_vpcs_misc_attr == 32'd305419896
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_30_cfg_vpcstx_preset10_attr == 18'd80192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_30_cfg_vpcstxdrv_levn_gen2_12_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_30_cfg_vpcstxdrv_levn_gen2_13_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_31_cfg_vpcstx_preset2_attr == 18'd47936
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_31_cfg_vpcstxdrv_levn_gen2_14_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_31_cfg_vpcstxdrv_levn_gen2_15_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_32_cfg_vpcstx_preset3_attr == 18'd31808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_32_cfg_vpcstxdrv_levn_gen2_2_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_32_cfg_vpcstxdrv_levn_gen2_3_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_33_cfg_vpcstx_preset4_attr == 18'd3584
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_33_cfg_vpcstxdrv_levn_gen2_4_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_33_cfg_vpcstxdrv_levn_gen2_5_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_34_cfg_vpcstx_preset5_attr == 18'd3206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_34_cfg_vpcstxdrv_levn_gen2_6_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_34_cfg_vpcstxdrv_levn_gen2_7_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_35_cfg_vpcstx_preset6_attr == 18'd3143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_35_cfg_vpcstxdrv_levn_gen2_8_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_35_cfg_vpcstxdrv_levn_gen2_9_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_36_cfg_vpcstx_preset7_attr == 18'd47558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_levnm1_gen1_0_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_levnm1_gen1_1_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_txdrvslew_gen1_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_37_cfg_vpcstx_preset8_attr == 18'd31367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_levnm1_gen1_10_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_levnm1_gen1_11_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_txdrvslew_gen2_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_38_cfg_vpcstx_preset9_attr == 18'd3017
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_levnm1_gen1_12_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_levnm1_gen1_13_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_txdrvslew_gen3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_14_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_15_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_2_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_3_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_5_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_3_cfg_vpcsbist_gen_skp_delay_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_3_cfg_vpcsebuf_fifo_full_thr_attr == 7'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_3_cfg_vpcsebuf_fifo_full_thr_sris_attr == 7'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_3_cfg_vpcseios_det_en_attr == UX_PCS_LANE_Q0_REG_3_CFG_VPCSEIOS_DET_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_3_cfg_vpcsif_blockaligncontrolpolarity_attr == UX_PCS_LANE_Q0_REG_3_CFG_VPCSIF_BLOCKALIGNCONTROLPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_6_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_7_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_8_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_9_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen2_0_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen2_1_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_10_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_11_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_12_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_13_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_14_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_15_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_2_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_3_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_5_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_6_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_7_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_levnm1_gen2_8_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_levnm1_gen2_9_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_txdrvslew_gen4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_good_syncheader_align_dis_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSALIGN128B_GOOD_SYNCHEADER_ALIGN_DIS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_unalign_lb_en_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSALIGN128B_UNALIGN_LB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_unalign_lb_wait_cnt_thr_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_data_en_falling_dly_ovr_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_DATA_EN_FALLING_DLY_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_data_en_falling_dly_thr_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_enb_skp_add_when_skpos_is_24_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_ENB_SKP_ADD_WHEN_SKPOS_IS_24_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_clr_cnt_thr_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_mid_offset_thr_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_mid_offset_thr_ow_en_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_FIFO_RD_MID_OFFSET_THR_OW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_fifo_wr_mid_offset_thr_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_fifo_wr_mid_offset_thr_ow_en_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_FIFO_WR_MID_OFFSET_THR_OW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_det_en_rd_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_DET_EN_RD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_det_en_wr_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_DET_EN_WR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_force_en_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_FORCE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_5_cfg_vpcsif_txflow_force_on_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSIF_TXFLOW_FORCE_ON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_5_cfg_vpcsif_txflow_nodatavld_force_on_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSIF_TXFLOW_NODATAVLD_FORCE_ON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_5_cfg_vpcsroreg_ckgate_dsbl_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSROREG_CKGATE_DSBL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_5_cfg_vpcstbus_ckgate_dsbl_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSTBUS_CKGATE_DSBL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_6_cfg_vpcsbist_udp_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_7_cfg_vpcsbist_udp_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_8_cfg_vpcsebuf_fifo_mid_thr_attr == 7'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_8_cfg_vpcsebuf_fifo_mid_thr_sris_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_force_neg_disp_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_force_pos_disp_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_tx_force_err_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_8_cfg_vpcsif_idle_cntr_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_8_cfg_vpcsif_ovr_blockaligncontrol_attr == UX_PCS_LANE_Q0_REG_8_CFG_VPCSIF_OVR_BLOCKALIGNCONTROL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_8_cfg_vpcsif_ovr_blockaligncontrol_ena_attr == UX_PCS_LANE_Q0_REG_8_CFG_VPCSIF_OVR_BLOCKALIGNCONTROL_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_9_cfg_vpcsif_min_reset_cntr_max_attr == 11'd1000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_9_cfg_vpcsif_min_txidle_cntr_max_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_chng_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_CHNG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_ebuf_mode_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_EBUF_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_ebuf_mode_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_EBUF_MODE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_encodedecodebypass_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_ENCODEDECODEBYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_encodedecodebypass_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_ENCODEDECODEBYPASS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_getlocalpresetcoefficients_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_GETLOCALPRESETCOEFFICIENTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_getlocalpresetcoefficients_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_GETLOCALPRESETCOEFFICIENTS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_localpresetindex_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_localpresetindex_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOCALPRESETINDEX_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_lowpin_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOWPIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_lowpin_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOWPIN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_m2p_bus_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_M2P_BUS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_pclk_as_input_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_PCLK_AS_INPUT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane15.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_pclk_as_input_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_PCLK_AS_INPUT_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_m2p_bus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclk_rate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclk_rate_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLK_RATE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclkchangeack_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLKCHANGEACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclkchangeack_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLKCHANGEACK_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_phy_mode_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_phy_mode_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PHY_MODE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_powerdown_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_powerdown_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_POWERDOWN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rate_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RATE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rst_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rst_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RST_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rxelecidle_disable_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RXELECIDLE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rxelecidle_disable_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RXELECIDLE_DISABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxeqeval_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXEQEVAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxeqeval_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXEQEVAL_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpolarity_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpolarity_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPOLARITY_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpresethint_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpresethint_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPRESETHINT_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxstandby_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXSTANDBY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxstandby_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXSTANDBY_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxtermination_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXTERMINATION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxtermination_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXTERMINATION_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_srisenable_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_srisenable_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_SRISENABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcmnmode_disable_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCMNMODE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcmnmode_disable_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCMNMODE_DISABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcompliance_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCOMPLIANCE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcompliance_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCOMPLIANCE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdeemph_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDEEMPH_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdtctrx_lb_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDTCTRX_LB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdtctrx_lb_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDTCTRX_LB_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txelecidle_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txelecidle_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXELECIDLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txmargin_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txmargin_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXMARGIN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txoneszeros_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXONESZEROS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txoneszeros_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXONESZEROS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txdeemph_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txswing_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_TXSWING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txswing_ena_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_TXSWING_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_width_ena_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_WIDTH_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p1subentry_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P1SUBENTRY_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p1subexit_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P1SUBEXIT_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p2entry_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P2ENTRY_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p2exit_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P2EXIT_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatusgen_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUSGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxdetect_inpciep2_en_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXDETECT_INPCIEP2_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxpstate_p0s_en_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXPSTATE_P0S_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxstandby0en_in_rxeq_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXSTANDBY0EN_IN_RXEQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie5_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_usb1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_usb2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_tx_pcie1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie5_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_usb1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_usb2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_14_cfg_vpcslb_fe_attr == UX_PCS_LANE_Q0_REG_14_CFG_VPCSLB_FE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_14_cfg_vpcsmbusconv_illegal_rd_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_14_CFG_VPCSMBUSCONV_ILLEGAL_RD_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_15_cfg_vpcslfps_ctrl_p3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_illegal_wr_c_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_ILLEGAL_WR_C_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_illegal_wr_uc_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_ILLEGAL_WR_UC_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_ack_gen_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_ACK_GEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timeout_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_COMPL_TIMEOUT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timer_en_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_COMPL_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timer_max_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_gen_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_GEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timeout_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_TIMEOUT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timer_en_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timer_max_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_15_cfg_vpcsonezero_one_cntr_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_15_cfg_vpcstxdrv_usb_gen1_txdeemph_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSTXDRV_USB_GEN1_TXDEEMPH_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_16_cfg_vpcsonezero_zero_cntr_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_16_cfg_vpcstbus_addr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_16_cfg_vpcstx_gen4_preset0_attr == 18'd60032
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_16_cfg_vpcstxdrv_usb_gen1_txswing_attr == UX_PCS_LANE_Q0_REG_16_CFG_VPCSTXDRV_USB_GEN1_TXSWING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_17_cfg_vpcsspare0_attr == 32'd4294901760
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_18_cfg_vpcstx_gen4_preset1_attr == 18'd39872
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_18_cfg_vpcstx_localfs_attr == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_18_cfg_vpcstx_localg4fs_attr == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_19_cfg_vpcstx_gen4_preset10_attr == 18'd80192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_19_cfg_vpcstx_localg4lf_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_19_cfg_vpcstx_locallf_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_1_cfg_vcpsckgate_disable_attr == UX_PCS_LANE_Q0_REG_1_CFG_VCPSCKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_1_cfg_vpcs_if_clk_sel_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCS_IF_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_1_cfg_vpcsalign10b_lock_cnt_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_1_cfg_vpcsalign10b_unlock_cnt_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_1_cfg_vpcsalign128b_g3g4_skp_os_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSALIGN128B_G3G4_SKP_OS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_1_cfg_vpcsalign128b_usb2_ctrl_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_clr_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_en_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_hold_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_data_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_en_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_init_ctrl_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_INIT_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_init_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_insert_err_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_INSERT_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_skp_cnt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_1_cfg_vpcsebuf_reset_on_err_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSEBUF_RESET_ON_ERR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_20_cfg_vpcstx_gen4_preset2_attr == 18'd47936
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_20_cfg_vpcstxdrv_levn_gen1_0_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_20_cfg_vpcstxdrv_levn_gen1_1_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_21_cfg_vpcstx_gen4_preset3_attr == 18'd31808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_21_cfg_vpcstxdrv_levn_gen1_10_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_21_cfg_vpcstxdrv_levn_gen1_11_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_22_cfg_vpcstx_gen4_preset4_attr == 18'd3584
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_22_cfg_vpcstxdrv_levn_gen1_12_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_22_cfg_vpcstxdrv_levn_gen1_13_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_23_cfg_vpcstx_gen4_preset5_attr == 18'd3206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_23_cfg_vpcstxdrv_levn_gen1_14_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_23_cfg_vpcstxdrv_levn_gen1_15_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_24_cfg_vpcstx_gen4_preset6_attr == 18'd3143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_24_cfg_vpcstxdrv_levn_gen1_2_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_24_cfg_vpcstxdrv_levn_gen1_3_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_25_cfg_vpcstx_gen4_preset7_attr == 18'd47558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_25_cfg_vpcstxdrv_levn_gen1_4_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_25_cfg_vpcstxdrv_levn_gen1_5_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_26_cfg_vpcstx_gen4_preset8_attr == 18'd31367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_26_cfg_vpcstxdrv_levn_gen1_6_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_26_cfg_vpcstxdrv_levn_gen1_7_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_27_cfg_vpcstx_gen4_preset9_attr == 18'd3017
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_27_cfg_vpcstxdrv_levn_gen1_8_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_27_cfg_vpcstxdrv_levn_gen1_9_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_28_cfg_vpcstx_preset0_attr == 18'd60032
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_28_cfg_vpcstxdrv_levn_gen2_0_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_28_cfg_vpcstxdrv_levn_gen2_1_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_29_cfg_vpcstx_preset1_attr == 18'd39872
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_29_cfg_vpcstxdrv_levn_gen2_10_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_29_cfg_vpcstxdrv_levn_gen2_11_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_2_cfg_vpcs_misc_attr == 32'd305419896
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_30_cfg_vpcstx_preset10_attr == 18'd80192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_30_cfg_vpcstxdrv_levn_gen2_12_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_30_cfg_vpcstxdrv_levn_gen2_13_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_31_cfg_vpcstx_preset2_attr == 18'd47936
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_31_cfg_vpcstxdrv_levn_gen2_14_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_31_cfg_vpcstxdrv_levn_gen2_15_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_32_cfg_vpcstx_preset3_attr == 18'd31808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_32_cfg_vpcstxdrv_levn_gen2_2_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_32_cfg_vpcstxdrv_levn_gen2_3_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_33_cfg_vpcstx_preset4_attr == 18'd3584
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_33_cfg_vpcstxdrv_levn_gen2_4_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_33_cfg_vpcstxdrv_levn_gen2_5_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_34_cfg_vpcstx_preset5_attr == 18'd3206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_34_cfg_vpcstxdrv_levn_gen2_6_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_34_cfg_vpcstxdrv_levn_gen2_7_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_35_cfg_vpcstx_preset6_attr == 18'd3143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_35_cfg_vpcstxdrv_levn_gen2_8_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_35_cfg_vpcstxdrv_levn_gen2_9_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_36_cfg_vpcstx_preset7_attr == 18'd47558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_levnm1_gen1_0_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_levnm1_gen1_1_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_txdrvslew_gen1_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_37_cfg_vpcstx_preset8_attr == 18'd31367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_levnm1_gen1_10_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_levnm1_gen1_11_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_txdrvslew_gen2_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_38_cfg_vpcstx_preset9_attr == 18'd3017
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_levnm1_gen1_12_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_levnm1_gen1_13_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_txdrvslew_gen3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_14_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_15_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_2_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_3_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_5_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_3_cfg_vpcsbist_gen_skp_delay_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_3_cfg_vpcsebuf_fifo_full_thr_attr == 7'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_3_cfg_vpcsebuf_fifo_full_thr_sris_attr == 7'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_3_cfg_vpcseios_det_en_attr == UX_PCS_LANE_Q0_REG_3_CFG_VPCSEIOS_DET_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_3_cfg_vpcsif_blockaligncontrolpolarity_attr == UX_PCS_LANE_Q0_REG_3_CFG_VPCSIF_BLOCKALIGNCONTROLPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_6_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_7_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_8_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_9_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen2_0_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen2_1_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_10_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_11_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_12_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_13_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_14_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_15_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_2_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_3_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_5_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_6_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_7_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_levnm1_gen2_8_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_levnm1_gen2_9_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_txdrvslew_gen4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_good_syncheader_align_dis_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSALIGN128B_GOOD_SYNCHEADER_ALIGN_DIS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_unalign_lb_en_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSALIGN128B_UNALIGN_LB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_unalign_lb_wait_cnt_thr_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_data_en_falling_dly_ovr_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_DATA_EN_FALLING_DLY_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_data_en_falling_dly_thr_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_enb_skp_add_when_skpos_is_24_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_ENB_SKP_ADD_WHEN_SKPOS_IS_24_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_clr_cnt_thr_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_mid_offset_thr_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_mid_offset_thr_ow_en_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_FIFO_RD_MID_OFFSET_THR_OW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_fifo_wr_mid_offset_thr_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_fifo_wr_mid_offset_thr_ow_en_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_FIFO_WR_MID_OFFSET_THR_OW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_det_en_rd_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_DET_EN_RD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_det_en_wr_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_DET_EN_WR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_force_en_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_FORCE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_5_cfg_vpcsif_txflow_force_on_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSIF_TXFLOW_FORCE_ON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_5_cfg_vpcsif_txflow_nodatavld_force_on_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSIF_TXFLOW_NODATAVLD_FORCE_ON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_5_cfg_vpcsroreg_ckgate_dsbl_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSROREG_CKGATE_DSBL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_5_cfg_vpcstbus_ckgate_dsbl_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSTBUS_CKGATE_DSBL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_6_cfg_vpcsbist_udp_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_7_cfg_vpcsbist_udp_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_8_cfg_vpcsebuf_fifo_mid_thr_attr == 7'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_8_cfg_vpcsebuf_fifo_mid_thr_sris_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_force_neg_disp_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_force_pos_disp_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_tx_force_err_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_8_cfg_vpcsif_idle_cntr_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_8_cfg_vpcsif_ovr_blockaligncontrol_attr == UX_PCS_LANE_Q0_REG_8_CFG_VPCSIF_OVR_BLOCKALIGNCONTROL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_8_cfg_vpcsif_ovr_blockaligncontrol_ena_attr == UX_PCS_LANE_Q0_REG_8_CFG_VPCSIF_OVR_BLOCKALIGNCONTROL_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_9_cfg_vpcsif_min_reset_cntr_max_attr == 11'd1000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_9_cfg_vpcsif_min_txidle_cntr_max_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_chng_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_CHNG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_ebuf_mode_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_EBUF_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_ebuf_mode_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_EBUF_MODE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_encodedecodebypass_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_ENCODEDECODEBYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_encodedecodebypass_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_ENCODEDECODEBYPASS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_getlocalpresetcoefficients_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_GETLOCALPRESETCOEFFICIENTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_getlocalpresetcoefficients_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_GETLOCALPRESETCOEFFICIENTS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_localpresetindex_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_localpresetindex_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOCALPRESETINDEX_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_lowpin_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOWPIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_lowpin_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOWPIN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_m2p_bus_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_M2P_BUS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_pclk_as_input_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_PCLK_AS_INPUT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane2.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_pclk_as_input_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_PCLK_AS_INPUT_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_m2p_bus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclk_rate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclk_rate_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLK_RATE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclkchangeack_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLKCHANGEACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclkchangeack_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLKCHANGEACK_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_phy_mode_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_phy_mode_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PHY_MODE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_powerdown_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_powerdown_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_POWERDOWN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rate_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RATE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rst_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rst_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RST_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rxelecidle_disable_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RXELECIDLE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rxelecidle_disable_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RXELECIDLE_DISABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxeqeval_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXEQEVAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxeqeval_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXEQEVAL_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpolarity_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpolarity_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPOLARITY_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpresethint_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpresethint_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPRESETHINT_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxstandby_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXSTANDBY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxstandby_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXSTANDBY_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxtermination_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXTERMINATION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxtermination_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXTERMINATION_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_srisenable_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_srisenable_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_SRISENABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcmnmode_disable_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCMNMODE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcmnmode_disable_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCMNMODE_DISABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcompliance_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCOMPLIANCE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcompliance_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCOMPLIANCE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdeemph_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDEEMPH_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdtctrx_lb_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDTCTRX_LB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdtctrx_lb_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDTCTRX_LB_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txelecidle_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txelecidle_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXELECIDLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txmargin_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txmargin_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXMARGIN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txoneszeros_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXONESZEROS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txoneszeros_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXONESZEROS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txdeemph_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txswing_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_TXSWING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txswing_ena_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_TXSWING_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_width_ena_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_WIDTH_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p1subentry_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P1SUBENTRY_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p1subexit_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P1SUBEXIT_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p2entry_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P2ENTRY_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p2exit_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P2EXIT_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatusgen_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUSGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxdetect_inpciep2_en_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXDETECT_INPCIEP2_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxpstate_p0s_en_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXPSTATE_P0S_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxstandby0en_in_rxeq_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXSTANDBY0EN_IN_RXEQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie5_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_usb1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_usb2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_tx_pcie1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie5_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_usb1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_usb2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_14_cfg_vpcslb_fe_attr == UX_PCS_LANE_Q0_REG_14_CFG_VPCSLB_FE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_14_cfg_vpcsmbusconv_illegal_rd_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_14_CFG_VPCSMBUSCONV_ILLEGAL_RD_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_15_cfg_vpcslfps_ctrl_p3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_illegal_wr_c_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_ILLEGAL_WR_C_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_illegal_wr_uc_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_ILLEGAL_WR_UC_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_ack_gen_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_ACK_GEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timeout_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_COMPL_TIMEOUT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timer_en_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_COMPL_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timer_max_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_gen_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_GEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timeout_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_TIMEOUT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timer_en_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timer_max_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_15_cfg_vpcsonezero_one_cntr_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_15_cfg_vpcstxdrv_usb_gen1_txdeemph_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSTXDRV_USB_GEN1_TXDEEMPH_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_16_cfg_vpcsonezero_zero_cntr_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_16_cfg_vpcstbus_addr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_16_cfg_vpcstx_gen4_preset0_attr == 18'd60032
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_16_cfg_vpcstxdrv_usb_gen1_txswing_attr == UX_PCS_LANE_Q0_REG_16_CFG_VPCSTXDRV_USB_GEN1_TXSWING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_17_cfg_vpcsspare0_attr == 32'd4294901760
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_18_cfg_vpcstx_gen4_preset1_attr == 18'd39872
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_18_cfg_vpcstx_localfs_attr == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_18_cfg_vpcstx_localg4fs_attr == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_19_cfg_vpcstx_gen4_preset10_attr == 18'd80192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_19_cfg_vpcstx_localg4lf_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_19_cfg_vpcstx_locallf_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_1_cfg_vcpsckgate_disable_attr == UX_PCS_LANE_Q0_REG_1_CFG_VCPSCKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_1_cfg_vpcs_if_clk_sel_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCS_IF_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_1_cfg_vpcsalign10b_lock_cnt_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_1_cfg_vpcsalign10b_unlock_cnt_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_1_cfg_vpcsalign128b_g3g4_skp_os_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSALIGN128B_G3G4_SKP_OS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_1_cfg_vpcsalign128b_usb2_ctrl_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_clr_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_en_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_hold_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_data_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_en_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_init_ctrl_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_INIT_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_init_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_insert_err_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_INSERT_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_skp_cnt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_1_cfg_vpcsebuf_reset_on_err_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSEBUF_RESET_ON_ERR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_20_cfg_vpcstx_gen4_preset2_attr == 18'd47936
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_20_cfg_vpcstxdrv_levn_gen1_0_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_20_cfg_vpcstxdrv_levn_gen1_1_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_21_cfg_vpcstx_gen4_preset3_attr == 18'd31808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_21_cfg_vpcstxdrv_levn_gen1_10_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_21_cfg_vpcstxdrv_levn_gen1_11_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_22_cfg_vpcstx_gen4_preset4_attr == 18'd3584
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_22_cfg_vpcstxdrv_levn_gen1_12_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_22_cfg_vpcstxdrv_levn_gen1_13_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_23_cfg_vpcstx_gen4_preset5_attr == 18'd3206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_23_cfg_vpcstxdrv_levn_gen1_14_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_23_cfg_vpcstxdrv_levn_gen1_15_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_24_cfg_vpcstx_gen4_preset6_attr == 18'd3143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_24_cfg_vpcstxdrv_levn_gen1_2_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_24_cfg_vpcstxdrv_levn_gen1_3_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_25_cfg_vpcstx_gen4_preset7_attr == 18'd47558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_25_cfg_vpcstxdrv_levn_gen1_4_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_25_cfg_vpcstxdrv_levn_gen1_5_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_26_cfg_vpcstx_gen4_preset8_attr == 18'd31367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_26_cfg_vpcstxdrv_levn_gen1_6_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_26_cfg_vpcstxdrv_levn_gen1_7_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_27_cfg_vpcstx_gen4_preset9_attr == 18'd3017
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_27_cfg_vpcstxdrv_levn_gen1_8_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_27_cfg_vpcstxdrv_levn_gen1_9_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_28_cfg_vpcstx_preset0_attr == 18'd60032
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_28_cfg_vpcstxdrv_levn_gen2_0_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_28_cfg_vpcstxdrv_levn_gen2_1_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_29_cfg_vpcstx_preset1_attr == 18'd39872
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_29_cfg_vpcstxdrv_levn_gen2_10_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_29_cfg_vpcstxdrv_levn_gen2_11_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_2_cfg_vpcs_misc_attr == 32'd305419896
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_30_cfg_vpcstx_preset10_attr == 18'd80192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_30_cfg_vpcstxdrv_levn_gen2_12_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_30_cfg_vpcstxdrv_levn_gen2_13_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_31_cfg_vpcstx_preset2_attr == 18'd47936
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_31_cfg_vpcstxdrv_levn_gen2_14_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_31_cfg_vpcstxdrv_levn_gen2_15_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_32_cfg_vpcstx_preset3_attr == 18'd31808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_32_cfg_vpcstxdrv_levn_gen2_2_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_32_cfg_vpcstxdrv_levn_gen2_3_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_33_cfg_vpcstx_preset4_attr == 18'd3584
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_33_cfg_vpcstxdrv_levn_gen2_4_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_33_cfg_vpcstxdrv_levn_gen2_5_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_34_cfg_vpcstx_preset5_attr == 18'd3206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_34_cfg_vpcstxdrv_levn_gen2_6_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_34_cfg_vpcstxdrv_levn_gen2_7_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_35_cfg_vpcstx_preset6_attr == 18'd3143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_35_cfg_vpcstxdrv_levn_gen2_8_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_35_cfg_vpcstxdrv_levn_gen2_9_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_36_cfg_vpcstx_preset7_attr == 18'd47558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_levnm1_gen1_0_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_levnm1_gen1_1_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_txdrvslew_gen1_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_37_cfg_vpcstx_preset8_attr == 18'd31367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_levnm1_gen1_10_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_levnm1_gen1_11_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_txdrvslew_gen2_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_38_cfg_vpcstx_preset9_attr == 18'd3017
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_levnm1_gen1_12_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_levnm1_gen1_13_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_txdrvslew_gen3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_14_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_15_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_2_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_3_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_5_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_3_cfg_vpcsbist_gen_skp_delay_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_3_cfg_vpcsebuf_fifo_full_thr_attr == 7'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_3_cfg_vpcsebuf_fifo_full_thr_sris_attr == 7'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_3_cfg_vpcseios_det_en_attr == UX_PCS_LANE_Q0_REG_3_CFG_VPCSEIOS_DET_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_3_cfg_vpcsif_blockaligncontrolpolarity_attr == UX_PCS_LANE_Q0_REG_3_CFG_VPCSIF_BLOCKALIGNCONTROLPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_6_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_7_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_8_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_9_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen2_0_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen2_1_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_10_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_11_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_12_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_13_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_14_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_15_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_2_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_3_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_5_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_6_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_7_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_levnm1_gen2_8_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_levnm1_gen2_9_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_txdrvslew_gen4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_good_syncheader_align_dis_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSALIGN128B_GOOD_SYNCHEADER_ALIGN_DIS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_unalign_lb_en_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSALIGN128B_UNALIGN_LB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_unalign_lb_wait_cnt_thr_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_data_en_falling_dly_ovr_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_DATA_EN_FALLING_DLY_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_data_en_falling_dly_thr_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_enb_skp_add_when_skpos_is_24_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_ENB_SKP_ADD_WHEN_SKPOS_IS_24_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_clr_cnt_thr_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_mid_offset_thr_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_mid_offset_thr_ow_en_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_FIFO_RD_MID_OFFSET_THR_OW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_fifo_wr_mid_offset_thr_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_fifo_wr_mid_offset_thr_ow_en_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_FIFO_WR_MID_OFFSET_THR_OW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_det_en_rd_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_DET_EN_RD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_det_en_wr_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_DET_EN_WR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_force_en_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_FORCE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_5_cfg_vpcsif_txflow_force_on_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSIF_TXFLOW_FORCE_ON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_5_cfg_vpcsif_txflow_nodatavld_force_on_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSIF_TXFLOW_NODATAVLD_FORCE_ON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_5_cfg_vpcsroreg_ckgate_dsbl_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSROREG_CKGATE_DSBL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_5_cfg_vpcstbus_ckgate_dsbl_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSTBUS_CKGATE_DSBL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_6_cfg_vpcsbist_udp_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_7_cfg_vpcsbist_udp_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_8_cfg_vpcsebuf_fifo_mid_thr_attr == 7'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_8_cfg_vpcsebuf_fifo_mid_thr_sris_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_force_neg_disp_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_force_pos_disp_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_tx_force_err_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_8_cfg_vpcsif_idle_cntr_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_8_cfg_vpcsif_ovr_blockaligncontrol_attr == UX_PCS_LANE_Q0_REG_8_CFG_VPCSIF_OVR_BLOCKALIGNCONTROL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_8_cfg_vpcsif_ovr_blockaligncontrol_ena_attr == UX_PCS_LANE_Q0_REG_8_CFG_VPCSIF_OVR_BLOCKALIGNCONTROL_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_9_cfg_vpcsif_min_reset_cntr_max_attr == 11'd1000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_9_cfg_vpcsif_min_txidle_cntr_max_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_chng_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_CHNG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_ebuf_mode_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_EBUF_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_ebuf_mode_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_EBUF_MODE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_encodedecodebypass_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_ENCODEDECODEBYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_encodedecodebypass_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_ENCODEDECODEBYPASS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_getlocalpresetcoefficients_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_GETLOCALPRESETCOEFFICIENTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_getlocalpresetcoefficients_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_GETLOCALPRESETCOEFFICIENTS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_localpresetindex_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_localpresetindex_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOCALPRESETINDEX_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_lowpin_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOWPIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_lowpin_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOWPIN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_m2p_bus_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_M2P_BUS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_pclk_as_input_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_PCLK_AS_INPUT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane3.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_pclk_as_input_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_PCLK_AS_INPUT_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_m2p_bus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclk_rate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclk_rate_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLK_RATE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclkchangeack_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLKCHANGEACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclkchangeack_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLKCHANGEACK_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_phy_mode_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_phy_mode_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PHY_MODE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_powerdown_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_powerdown_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_POWERDOWN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rate_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RATE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rst_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rst_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RST_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rxelecidle_disable_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RXELECIDLE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rxelecidle_disable_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RXELECIDLE_DISABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxeqeval_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXEQEVAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxeqeval_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXEQEVAL_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpolarity_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpolarity_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPOLARITY_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpresethint_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpresethint_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPRESETHINT_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxstandby_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXSTANDBY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxstandby_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXSTANDBY_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxtermination_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXTERMINATION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxtermination_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXTERMINATION_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_srisenable_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_srisenable_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_SRISENABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcmnmode_disable_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCMNMODE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcmnmode_disable_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCMNMODE_DISABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcompliance_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCOMPLIANCE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcompliance_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCOMPLIANCE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdeemph_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDEEMPH_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdtctrx_lb_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDTCTRX_LB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdtctrx_lb_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDTCTRX_LB_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txelecidle_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txelecidle_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXELECIDLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txmargin_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txmargin_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXMARGIN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txoneszeros_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXONESZEROS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txoneszeros_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXONESZEROS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txdeemph_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txswing_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_TXSWING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txswing_ena_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_TXSWING_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_width_ena_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_WIDTH_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p1subentry_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P1SUBENTRY_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p1subexit_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P1SUBEXIT_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p2entry_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P2ENTRY_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p2exit_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P2EXIT_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatusgen_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUSGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxdetect_inpciep2_en_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXDETECT_INPCIEP2_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxpstate_p0s_en_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXPSTATE_P0S_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxstandby0en_in_rxeq_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXSTANDBY0EN_IN_RXEQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie5_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_usb1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_usb2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_tx_pcie1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie5_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_usb1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_usb2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_14_cfg_vpcslb_fe_attr == UX_PCS_LANE_Q0_REG_14_CFG_VPCSLB_FE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_14_cfg_vpcsmbusconv_illegal_rd_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_14_CFG_VPCSMBUSCONV_ILLEGAL_RD_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_15_cfg_vpcslfps_ctrl_p3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_illegal_wr_c_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_ILLEGAL_WR_C_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_illegal_wr_uc_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_ILLEGAL_WR_UC_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_ack_gen_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_ACK_GEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timeout_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_COMPL_TIMEOUT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timer_en_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_COMPL_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timer_max_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_gen_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_GEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timeout_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_TIMEOUT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timer_en_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timer_max_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_15_cfg_vpcsonezero_one_cntr_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_15_cfg_vpcstxdrv_usb_gen1_txdeemph_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSTXDRV_USB_GEN1_TXDEEMPH_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_16_cfg_vpcsonezero_zero_cntr_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_16_cfg_vpcstbus_addr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_16_cfg_vpcstx_gen4_preset0_attr == 18'd60032
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_16_cfg_vpcstxdrv_usb_gen1_txswing_attr == UX_PCS_LANE_Q0_REG_16_CFG_VPCSTXDRV_USB_GEN1_TXSWING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_17_cfg_vpcsspare0_attr == 32'd4294901760
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_18_cfg_vpcstx_gen4_preset1_attr == 18'd39872
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_18_cfg_vpcstx_localfs_attr == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_18_cfg_vpcstx_localg4fs_attr == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_19_cfg_vpcstx_gen4_preset10_attr == 18'd80192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_19_cfg_vpcstx_localg4lf_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_19_cfg_vpcstx_locallf_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_1_cfg_vcpsckgate_disable_attr == UX_PCS_LANE_Q0_REG_1_CFG_VCPSCKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_1_cfg_vpcs_if_clk_sel_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCS_IF_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_1_cfg_vpcsalign10b_lock_cnt_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_1_cfg_vpcsalign10b_unlock_cnt_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_1_cfg_vpcsalign128b_g3g4_skp_os_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSALIGN128B_G3G4_SKP_OS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_1_cfg_vpcsalign128b_usb2_ctrl_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_clr_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_en_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_hold_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_data_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_en_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_init_ctrl_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_INIT_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_init_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_insert_err_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_INSERT_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_skp_cnt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_1_cfg_vpcsebuf_reset_on_err_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSEBUF_RESET_ON_ERR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_20_cfg_vpcstx_gen4_preset2_attr == 18'd47936
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_20_cfg_vpcstxdrv_levn_gen1_0_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_20_cfg_vpcstxdrv_levn_gen1_1_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_21_cfg_vpcstx_gen4_preset3_attr == 18'd31808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_21_cfg_vpcstxdrv_levn_gen1_10_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_21_cfg_vpcstxdrv_levn_gen1_11_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_22_cfg_vpcstx_gen4_preset4_attr == 18'd3584
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_22_cfg_vpcstxdrv_levn_gen1_12_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_22_cfg_vpcstxdrv_levn_gen1_13_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_23_cfg_vpcstx_gen4_preset5_attr == 18'd3206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_23_cfg_vpcstxdrv_levn_gen1_14_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_23_cfg_vpcstxdrv_levn_gen1_15_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_24_cfg_vpcstx_gen4_preset6_attr == 18'd3143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_24_cfg_vpcstxdrv_levn_gen1_2_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_24_cfg_vpcstxdrv_levn_gen1_3_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_25_cfg_vpcstx_gen4_preset7_attr == 18'd47558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_25_cfg_vpcstxdrv_levn_gen1_4_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_25_cfg_vpcstxdrv_levn_gen1_5_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_26_cfg_vpcstx_gen4_preset8_attr == 18'd31367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_26_cfg_vpcstxdrv_levn_gen1_6_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_26_cfg_vpcstxdrv_levn_gen1_7_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_27_cfg_vpcstx_gen4_preset9_attr == 18'd3017
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_27_cfg_vpcstxdrv_levn_gen1_8_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_27_cfg_vpcstxdrv_levn_gen1_9_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_28_cfg_vpcstx_preset0_attr == 18'd60032
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_28_cfg_vpcstxdrv_levn_gen2_0_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_28_cfg_vpcstxdrv_levn_gen2_1_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_29_cfg_vpcstx_preset1_attr == 18'd39872
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_29_cfg_vpcstxdrv_levn_gen2_10_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_29_cfg_vpcstxdrv_levn_gen2_11_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_2_cfg_vpcs_misc_attr == 32'd305419896
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_30_cfg_vpcstx_preset10_attr == 18'd80192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_30_cfg_vpcstxdrv_levn_gen2_12_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_30_cfg_vpcstxdrv_levn_gen2_13_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_31_cfg_vpcstx_preset2_attr == 18'd47936
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_31_cfg_vpcstxdrv_levn_gen2_14_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_31_cfg_vpcstxdrv_levn_gen2_15_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_32_cfg_vpcstx_preset3_attr == 18'd31808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_32_cfg_vpcstxdrv_levn_gen2_2_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_32_cfg_vpcstxdrv_levn_gen2_3_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_33_cfg_vpcstx_preset4_attr == 18'd3584
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_33_cfg_vpcstxdrv_levn_gen2_4_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_33_cfg_vpcstxdrv_levn_gen2_5_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_34_cfg_vpcstx_preset5_attr == 18'd3206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_34_cfg_vpcstxdrv_levn_gen2_6_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_34_cfg_vpcstxdrv_levn_gen2_7_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_35_cfg_vpcstx_preset6_attr == 18'd3143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_35_cfg_vpcstxdrv_levn_gen2_8_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_35_cfg_vpcstxdrv_levn_gen2_9_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_36_cfg_vpcstx_preset7_attr == 18'd47558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_levnm1_gen1_0_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_levnm1_gen1_1_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_txdrvslew_gen1_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_37_cfg_vpcstx_preset8_attr == 18'd31367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_levnm1_gen1_10_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_levnm1_gen1_11_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_txdrvslew_gen2_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_38_cfg_vpcstx_preset9_attr == 18'd3017
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_levnm1_gen1_12_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_levnm1_gen1_13_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_txdrvslew_gen3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_14_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_15_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_2_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_3_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_5_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_3_cfg_vpcsbist_gen_skp_delay_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_3_cfg_vpcsebuf_fifo_full_thr_attr == 7'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_3_cfg_vpcsebuf_fifo_full_thr_sris_attr == 7'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_3_cfg_vpcseios_det_en_attr == UX_PCS_LANE_Q0_REG_3_CFG_VPCSEIOS_DET_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_3_cfg_vpcsif_blockaligncontrolpolarity_attr == UX_PCS_LANE_Q0_REG_3_CFG_VPCSIF_BLOCKALIGNCONTROLPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_6_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_7_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_8_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_9_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen2_0_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen2_1_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_10_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_11_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_12_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_13_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_14_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_15_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_2_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_3_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_5_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_6_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_7_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_levnm1_gen2_8_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_levnm1_gen2_9_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_txdrvslew_gen4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_good_syncheader_align_dis_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSALIGN128B_GOOD_SYNCHEADER_ALIGN_DIS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_unalign_lb_en_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSALIGN128B_UNALIGN_LB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_unalign_lb_wait_cnt_thr_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_data_en_falling_dly_ovr_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_DATA_EN_FALLING_DLY_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_data_en_falling_dly_thr_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_enb_skp_add_when_skpos_is_24_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_ENB_SKP_ADD_WHEN_SKPOS_IS_24_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_clr_cnt_thr_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_mid_offset_thr_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_mid_offset_thr_ow_en_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_FIFO_RD_MID_OFFSET_THR_OW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_fifo_wr_mid_offset_thr_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_fifo_wr_mid_offset_thr_ow_en_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_FIFO_WR_MID_OFFSET_THR_OW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_det_en_rd_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_DET_EN_RD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_det_en_wr_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_DET_EN_WR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_force_en_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_FORCE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_5_cfg_vpcsif_txflow_force_on_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSIF_TXFLOW_FORCE_ON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_5_cfg_vpcsif_txflow_nodatavld_force_on_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSIF_TXFLOW_NODATAVLD_FORCE_ON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_5_cfg_vpcsroreg_ckgate_dsbl_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSROREG_CKGATE_DSBL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_5_cfg_vpcstbus_ckgate_dsbl_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSTBUS_CKGATE_DSBL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_6_cfg_vpcsbist_udp_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_7_cfg_vpcsbist_udp_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_8_cfg_vpcsebuf_fifo_mid_thr_attr == 7'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_8_cfg_vpcsebuf_fifo_mid_thr_sris_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_force_neg_disp_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_force_pos_disp_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_tx_force_err_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_8_cfg_vpcsif_idle_cntr_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_8_cfg_vpcsif_ovr_blockaligncontrol_attr == UX_PCS_LANE_Q0_REG_8_CFG_VPCSIF_OVR_BLOCKALIGNCONTROL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_8_cfg_vpcsif_ovr_blockaligncontrol_ena_attr == UX_PCS_LANE_Q0_REG_8_CFG_VPCSIF_OVR_BLOCKALIGNCONTROL_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_9_cfg_vpcsif_min_reset_cntr_max_attr == 11'd1000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_9_cfg_vpcsif_min_txidle_cntr_max_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_chng_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_CHNG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_ebuf_mode_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_EBUF_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_ebuf_mode_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_EBUF_MODE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_encodedecodebypass_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_ENCODEDECODEBYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_encodedecodebypass_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_ENCODEDECODEBYPASS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_getlocalpresetcoefficients_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_GETLOCALPRESETCOEFFICIENTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_getlocalpresetcoefficients_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_GETLOCALPRESETCOEFFICIENTS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_localpresetindex_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_localpresetindex_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOCALPRESETINDEX_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_lowpin_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOWPIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_lowpin_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOWPIN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_m2p_bus_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_M2P_BUS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_pclk_as_input_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_PCLK_AS_INPUT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane4.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_pclk_as_input_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_PCLK_AS_INPUT_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_m2p_bus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclk_rate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclk_rate_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLK_RATE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclkchangeack_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLKCHANGEACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclkchangeack_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLKCHANGEACK_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_phy_mode_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_phy_mode_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PHY_MODE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_powerdown_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_powerdown_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_POWERDOWN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rate_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RATE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rst_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rst_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RST_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rxelecidle_disable_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RXELECIDLE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rxelecidle_disable_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RXELECIDLE_DISABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxeqeval_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXEQEVAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxeqeval_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXEQEVAL_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpolarity_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpolarity_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPOLARITY_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpresethint_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpresethint_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPRESETHINT_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxstandby_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXSTANDBY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxstandby_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXSTANDBY_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxtermination_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXTERMINATION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxtermination_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXTERMINATION_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_srisenable_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_srisenable_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_SRISENABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcmnmode_disable_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCMNMODE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcmnmode_disable_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCMNMODE_DISABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcompliance_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCOMPLIANCE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcompliance_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCOMPLIANCE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdeemph_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDEEMPH_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdtctrx_lb_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDTCTRX_LB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdtctrx_lb_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDTCTRX_LB_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txelecidle_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txelecidle_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXELECIDLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txmargin_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txmargin_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXMARGIN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txoneszeros_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXONESZEROS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txoneszeros_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXONESZEROS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txdeemph_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txswing_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_TXSWING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txswing_ena_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_TXSWING_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_width_ena_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_WIDTH_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p1subentry_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P1SUBENTRY_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p1subexit_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P1SUBEXIT_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p2entry_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P2ENTRY_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p2exit_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P2EXIT_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatusgen_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUSGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxdetect_inpciep2_en_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXDETECT_INPCIEP2_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxpstate_p0s_en_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXPSTATE_P0S_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxstandby0en_in_rxeq_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXSTANDBY0EN_IN_RXEQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie5_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_usb1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_usb2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_tx_pcie1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie5_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_usb1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_usb2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_14_cfg_vpcslb_fe_attr == UX_PCS_LANE_Q0_REG_14_CFG_VPCSLB_FE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_14_cfg_vpcsmbusconv_illegal_rd_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_14_CFG_VPCSMBUSCONV_ILLEGAL_RD_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_15_cfg_vpcslfps_ctrl_p3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_illegal_wr_c_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_ILLEGAL_WR_C_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_illegal_wr_uc_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_ILLEGAL_WR_UC_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_ack_gen_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_ACK_GEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timeout_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_COMPL_TIMEOUT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timer_en_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_COMPL_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timer_max_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_gen_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_GEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timeout_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_TIMEOUT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timer_en_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timer_max_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_15_cfg_vpcsonezero_one_cntr_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_15_cfg_vpcstxdrv_usb_gen1_txdeemph_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSTXDRV_USB_GEN1_TXDEEMPH_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_16_cfg_vpcsonezero_zero_cntr_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_16_cfg_vpcstbus_addr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_16_cfg_vpcstx_gen4_preset0_attr == 18'd60032
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_16_cfg_vpcstxdrv_usb_gen1_txswing_attr == UX_PCS_LANE_Q0_REG_16_CFG_VPCSTXDRV_USB_GEN1_TXSWING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_17_cfg_vpcsspare0_attr == 32'd4294901760
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_18_cfg_vpcstx_gen4_preset1_attr == 18'd39872
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_18_cfg_vpcstx_localfs_attr == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_18_cfg_vpcstx_localg4fs_attr == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_19_cfg_vpcstx_gen4_preset10_attr == 18'd80192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_19_cfg_vpcstx_localg4lf_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_19_cfg_vpcstx_locallf_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_1_cfg_vcpsckgate_disable_attr == UX_PCS_LANE_Q0_REG_1_CFG_VCPSCKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_1_cfg_vpcs_if_clk_sel_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCS_IF_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_1_cfg_vpcsalign10b_lock_cnt_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_1_cfg_vpcsalign10b_unlock_cnt_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_1_cfg_vpcsalign128b_g3g4_skp_os_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSALIGN128B_G3G4_SKP_OS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_1_cfg_vpcsalign128b_usb2_ctrl_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_clr_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_en_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_hold_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_data_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_en_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_init_ctrl_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_INIT_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_init_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_insert_err_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_INSERT_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_skp_cnt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_1_cfg_vpcsebuf_reset_on_err_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSEBUF_RESET_ON_ERR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_20_cfg_vpcstx_gen4_preset2_attr == 18'd47936
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_20_cfg_vpcstxdrv_levn_gen1_0_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_20_cfg_vpcstxdrv_levn_gen1_1_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_21_cfg_vpcstx_gen4_preset3_attr == 18'd31808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_21_cfg_vpcstxdrv_levn_gen1_10_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_21_cfg_vpcstxdrv_levn_gen1_11_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_22_cfg_vpcstx_gen4_preset4_attr == 18'd3584
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_22_cfg_vpcstxdrv_levn_gen1_12_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_22_cfg_vpcstxdrv_levn_gen1_13_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_23_cfg_vpcstx_gen4_preset5_attr == 18'd3206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_23_cfg_vpcstxdrv_levn_gen1_14_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_23_cfg_vpcstxdrv_levn_gen1_15_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_24_cfg_vpcstx_gen4_preset6_attr == 18'd3143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_24_cfg_vpcstxdrv_levn_gen1_2_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_24_cfg_vpcstxdrv_levn_gen1_3_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_25_cfg_vpcstx_gen4_preset7_attr == 18'd47558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_25_cfg_vpcstxdrv_levn_gen1_4_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_25_cfg_vpcstxdrv_levn_gen1_5_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_26_cfg_vpcstx_gen4_preset8_attr == 18'd31367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_26_cfg_vpcstxdrv_levn_gen1_6_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_26_cfg_vpcstxdrv_levn_gen1_7_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_27_cfg_vpcstx_gen4_preset9_attr == 18'd3017
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_27_cfg_vpcstxdrv_levn_gen1_8_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_27_cfg_vpcstxdrv_levn_gen1_9_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_28_cfg_vpcstx_preset0_attr == 18'd60032
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_28_cfg_vpcstxdrv_levn_gen2_0_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_28_cfg_vpcstxdrv_levn_gen2_1_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_29_cfg_vpcstx_preset1_attr == 18'd39872
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_29_cfg_vpcstxdrv_levn_gen2_10_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_29_cfg_vpcstxdrv_levn_gen2_11_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_2_cfg_vpcs_misc_attr == 32'd305419896
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_30_cfg_vpcstx_preset10_attr == 18'd80192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_30_cfg_vpcstxdrv_levn_gen2_12_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_30_cfg_vpcstxdrv_levn_gen2_13_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_31_cfg_vpcstx_preset2_attr == 18'd47936
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_31_cfg_vpcstxdrv_levn_gen2_14_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_31_cfg_vpcstxdrv_levn_gen2_15_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_32_cfg_vpcstx_preset3_attr == 18'd31808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_32_cfg_vpcstxdrv_levn_gen2_2_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_32_cfg_vpcstxdrv_levn_gen2_3_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_33_cfg_vpcstx_preset4_attr == 18'd3584
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_33_cfg_vpcstxdrv_levn_gen2_4_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_33_cfg_vpcstxdrv_levn_gen2_5_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_34_cfg_vpcstx_preset5_attr == 18'd3206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_34_cfg_vpcstxdrv_levn_gen2_6_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_34_cfg_vpcstxdrv_levn_gen2_7_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_35_cfg_vpcstx_preset6_attr == 18'd3143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_35_cfg_vpcstxdrv_levn_gen2_8_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_35_cfg_vpcstxdrv_levn_gen2_9_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_36_cfg_vpcstx_preset7_attr == 18'd47558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_levnm1_gen1_0_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_levnm1_gen1_1_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_txdrvslew_gen1_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_37_cfg_vpcstx_preset8_attr == 18'd31367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_levnm1_gen1_10_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_levnm1_gen1_11_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_txdrvslew_gen2_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_38_cfg_vpcstx_preset9_attr == 18'd3017
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_levnm1_gen1_12_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_levnm1_gen1_13_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_txdrvslew_gen3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_14_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_15_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_2_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_3_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_5_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_3_cfg_vpcsbist_gen_skp_delay_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_3_cfg_vpcsebuf_fifo_full_thr_attr == 7'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_3_cfg_vpcsebuf_fifo_full_thr_sris_attr == 7'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_3_cfg_vpcseios_det_en_attr == UX_PCS_LANE_Q0_REG_3_CFG_VPCSEIOS_DET_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_3_cfg_vpcsif_blockaligncontrolpolarity_attr == UX_PCS_LANE_Q0_REG_3_CFG_VPCSIF_BLOCKALIGNCONTROLPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_6_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_7_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_8_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_9_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen2_0_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen2_1_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_10_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_11_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_12_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_13_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_14_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_15_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_2_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_3_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_5_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_6_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_7_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_levnm1_gen2_8_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_levnm1_gen2_9_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_txdrvslew_gen4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_good_syncheader_align_dis_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSALIGN128B_GOOD_SYNCHEADER_ALIGN_DIS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_unalign_lb_en_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSALIGN128B_UNALIGN_LB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_unalign_lb_wait_cnt_thr_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_data_en_falling_dly_ovr_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_DATA_EN_FALLING_DLY_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_data_en_falling_dly_thr_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_enb_skp_add_when_skpos_is_24_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_ENB_SKP_ADD_WHEN_SKPOS_IS_24_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_clr_cnt_thr_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_mid_offset_thr_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_mid_offset_thr_ow_en_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_FIFO_RD_MID_OFFSET_THR_OW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_fifo_wr_mid_offset_thr_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_fifo_wr_mid_offset_thr_ow_en_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_FIFO_WR_MID_OFFSET_THR_OW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_det_en_rd_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_DET_EN_RD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_det_en_wr_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_DET_EN_WR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_force_en_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_FORCE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_5_cfg_vpcsif_txflow_force_on_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSIF_TXFLOW_FORCE_ON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_5_cfg_vpcsif_txflow_nodatavld_force_on_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSIF_TXFLOW_NODATAVLD_FORCE_ON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_5_cfg_vpcsroreg_ckgate_dsbl_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSROREG_CKGATE_DSBL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_5_cfg_vpcstbus_ckgate_dsbl_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSTBUS_CKGATE_DSBL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_6_cfg_vpcsbist_udp_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_7_cfg_vpcsbist_udp_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_8_cfg_vpcsebuf_fifo_mid_thr_attr == 7'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_8_cfg_vpcsebuf_fifo_mid_thr_sris_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_force_neg_disp_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_force_pos_disp_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_tx_force_err_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_8_cfg_vpcsif_idle_cntr_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_8_cfg_vpcsif_ovr_blockaligncontrol_attr == UX_PCS_LANE_Q0_REG_8_CFG_VPCSIF_OVR_BLOCKALIGNCONTROL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_8_cfg_vpcsif_ovr_blockaligncontrol_ena_attr == UX_PCS_LANE_Q0_REG_8_CFG_VPCSIF_OVR_BLOCKALIGNCONTROL_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_9_cfg_vpcsif_min_reset_cntr_max_attr == 11'd1000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_9_cfg_vpcsif_min_txidle_cntr_max_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_chng_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_CHNG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_ebuf_mode_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_EBUF_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_ebuf_mode_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_EBUF_MODE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_encodedecodebypass_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_ENCODEDECODEBYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_encodedecodebypass_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_ENCODEDECODEBYPASS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_getlocalpresetcoefficients_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_GETLOCALPRESETCOEFFICIENTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_getlocalpresetcoefficients_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_GETLOCALPRESETCOEFFICIENTS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_localpresetindex_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_localpresetindex_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOCALPRESETINDEX_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_lowpin_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOWPIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_lowpin_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOWPIN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_m2p_bus_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_M2P_BUS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_pclk_as_input_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_PCLK_AS_INPUT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane5.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_pclk_as_input_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_PCLK_AS_INPUT_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_m2p_bus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclk_rate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclk_rate_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLK_RATE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclkchangeack_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLKCHANGEACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclkchangeack_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLKCHANGEACK_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_phy_mode_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_phy_mode_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PHY_MODE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_powerdown_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_powerdown_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_POWERDOWN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rate_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RATE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rst_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rst_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RST_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rxelecidle_disable_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RXELECIDLE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rxelecidle_disable_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RXELECIDLE_DISABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxeqeval_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXEQEVAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxeqeval_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXEQEVAL_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpolarity_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpolarity_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPOLARITY_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpresethint_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpresethint_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPRESETHINT_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxstandby_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXSTANDBY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxstandby_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXSTANDBY_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxtermination_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXTERMINATION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxtermination_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXTERMINATION_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_srisenable_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_srisenable_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_SRISENABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcmnmode_disable_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCMNMODE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcmnmode_disable_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCMNMODE_DISABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcompliance_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCOMPLIANCE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcompliance_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCOMPLIANCE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdeemph_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDEEMPH_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdtctrx_lb_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDTCTRX_LB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdtctrx_lb_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDTCTRX_LB_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txelecidle_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txelecidle_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXELECIDLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txmargin_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txmargin_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXMARGIN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txoneszeros_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXONESZEROS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txoneszeros_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXONESZEROS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txdeemph_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txswing_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_TXSWING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txswing_ena_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_TXSWING_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_width_ena_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_WIDTH_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p1subentry_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P1SUBENTRY_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p1subexit_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P1SUBEXIT_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p2entry_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P2ENTRY_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p2exit_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P2EXIT_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatusgen_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUSGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxdetect_inpciep2_en_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXDETECT_INPCIEP2_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxpstate_p0s_en_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXPSTATE_P0S_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxstandby0en_in_rxeq_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXSTANDBY0EN_IN_RXEQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie5_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_usb1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_usb2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_tx_pcie1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie5_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_usb1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_usb2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_14_cfg_vpcslb_fe_attr == UX_PCS_LANE_Q0_REG_14_CFG_VPCSLB_FE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_14_cfg_vpcsmbusconv_illegal_rd_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_14_CFG_VPCSMBUSCONV_ILLEGAL_RD_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_15_cfg_vpcslfps_ctrl_p3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_illegal_wr_c_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_ILLEGAL_WR_C_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_illegal_wr_uc_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_ILLEGAL_WR_UC_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_ack_gen_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_ACK_GEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timeout_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_COMPL_TIMEOUT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timer_en_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_COMPL_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timer_max_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_gen_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_GEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timeout_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_TIMEOUT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timer_en_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timer_max_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_15_cfg_vpcsonezero_one_cntr_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_15_cfg_vpcstxdrv_usb_gen1_txdeemph_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSTXDRV_USB_GEN1_TXDEEMPH_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_16_cfg_vpcsonezero_zero_cntr_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_16_cfg_vpcstbus_addr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_16_cfg_vpcstx_gen4_preset0_attr == 18'd60032
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_16_cfg_vpcstxdrv_usb_gen1_txswing_attr == UX_PCS_LANE_Q0_REG_16_CFG_VPCSTXDRV_USB_GEN1_TXSWING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_17_cfg_vpcsspare0_attr == 32'd4294901760
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_18_cfg_vpcstx_gen4_preset1_attr == 18'd39872
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_18_cfg_vpcstx_localfs_attr == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_18_cfg_vpcstx_localg4fs_attr == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_19_cfg_vpcstx_gen4_preset10_attr == 18'd80192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_19_cfg_vpcstx_localg4lf_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_19_cfg_vpcstx_locallf_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_1_cfg_vcpsckgate_disable_attr == UX_PCS_LANE_Q0_REG_1_CFG_VCPSCKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_1_cfg_vpcs_if_clk_sel_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCS_IF_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_1_cfg_vpcsalign10b_lock_cnt_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_1_cfg_vpcsalign10b_unlock_cnt_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_1_cfg_vpcsalign128b_g3g4_skp_os_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSALIGN128B_G3G4_SKP_OS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_1_cfg_vpcsalign128b_usb2_ctrl_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_clr_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_en_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_hold_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_data_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_en_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_init_ctrl_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_INIT_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_init_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_insert_err_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_INSERT_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_skp_cnt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_1_cfg_vpcsebuf_reset_on_err_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSEBUF_RESET_ON_ERR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_20_cfg_vpcstx_gen4_preset2_attr == 18'd47936
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_20_cfg_vpcstxdrv_levn_gen1_0_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_20_cfg_vpcstxdrv_levn_gen1_1_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_21_cfg_vpcstx_gen4_preset3_attr == 18'd31808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_21_cfg_vpcstxdrv_levn_gen1_10_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_21_cfg_vpcstxdrv_levn_gen1_11_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_22_cfg_vpcstx_gen4_preset4_attr == 18'd3584
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_22_cfg_vpcstxdrv_levn_gen1_12_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_22_cfg_vpcstxdrv_levn_gen1_13_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_23_cfg_vpcstx_gen4_preset5_attr == 18'd3206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_23_cfg_vpcstxdrv_levn_gen1_14_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_23_cfg_vpcstxdrv_levn_gen1_15_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_24_cfg_vpcstx_gen4_preset6_attr == 18'd3143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_24_cfg_vpcstxdrv_levn_gen1_2_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_24_cfg_vpcstxdrv_levn_gen1_3_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_25_cfg_vpcstx_gen4_preset7_attr == 18'd47558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_25_cfg_vpcstxdrv_levn_gen1_4_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_25_cfg_vpcstxdrv_levn_gen1_5_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_26_cfg_vpcstx_gen4_preset8_attr == 18'd31367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_26_cfg_vpcstxdrv_levn_gen1_6_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_26_cfg_vpcstxdrv_levn_gen1_7_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_27_cfg_vpcstx_gen4_preset9_attr == 18'd3017
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_27_cfg_vpcstxdrv_levn_gen1_8_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_27_cfg_vpcstxdrv_levn_gen1_9_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_28_cfg_vpcstx_preset0_attr == 18'd60032
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_28_cfg_vpcstxdrv_levn_gen2_0_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_28_cfg_vpcstxdrv_levn_gen2_1_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_29_cfg_vpcstx_preset1_attr == 18'd39872
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_29_cfg_vpcstxdrv_levn_gen2_10_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_29_cfg_vpcstxdrv_levn_gen2_11_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_2_cfg_vpcs_misc_attr == 32'd305419896
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_30_cfg_vpcstx_preset10_attr == 18'd80192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_30_cfg_vpcstxdrv_levn_gen2_12_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_30_cfg_vpcstxdrv_levn_gen2_13_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_31_cfg_vpcstx_preset2_attr == 18'd47936
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_31_cfg_vpcstxdrv_levn_gen2_14_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_31_cfg_vpcstxdrv_levn_gen2_15_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_32_cfg_vpcstx_preset3_attr == 18'd31808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_32_cfg_vpcstxdrv_levn_gen2_2_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_32_cfg_vpcstxdrv_levn_gen2_3_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_33_cfg_vpcstx_preset4_attr == 18'd3584
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_33_cfg_vpcstxdrv_levn_gen2_4_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_33_cfg_vpcstxdrv_levn_gen2_5_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_34_cfg_vpcstx_preset5_attr == 18'd3206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_34_cfg_vpcstxdrv_levn_gen2_6_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_34_cfg_vpcstxdrv_levn_gen2_7_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_35_cfg_vpcstx_preset6_attr == 18'd3143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_35_cfg_vpcstxdrv_levn_gen2_8_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_35_cfg_vpcstxdrv_levn_gen2_9_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_36_cfg_vpcstx_preset7_attr == 18'd47558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_levnm1_gen1_0_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_levnm1_gen1_1_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_txdrvslew_gen1_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_37_cfg_vpcstx_preset8_attr == 18'd31367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_levnm1_gen1_10_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_levnm1_gen1_11_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_txdrvslew_gen2_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_38_cfg_vpcstx_preset9_attr == 18'd3017
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_levnm1_gen1_12_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_levnm1_gen1_13_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_txdrvslew_gen3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_14_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_15_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_2_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_3_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_5_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_3_cfg_vpcsbist_gen_skp_delay_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_3_cfg_vpcsebuf_fifo_full_thr_attr == 7'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_3_cfg_vpcsebuf_fifo_full_thr_sris_attr == 7'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_3_cfg_vpcseios_det_en_attr == UX_PCS_LANE_Q0_REG_3_CFG_VPCSEIOS_DET_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_3_cfg_vpcsif_blockaligncontrolpolarity_attr == UX_PCS_LANE_Q0_REG_3_CFG_VPCSIF_BLOCKALIGNCONTROLPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_6_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_7_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_8_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_9_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen2_0_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen2_1_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_10_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_11_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_12_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_13_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_14_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_15_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_2_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_3_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_5_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_6_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_7_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_levnm1_gen2_8_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_levnm1_gen2_9_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_txdrvslew_gen4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_good_syncheader_align_dis_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSALIGN128B_GOOD_SYNCHEADER_ALIGN_DIS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_unalign_lb_en_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSALIGN128B_UNALIGN_LB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_unalign_lb_wait_cnt_thr_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_data_en_falling_dly_ovr_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_DATA_EN_FALLING_DLY_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_data_en_falling_dly_thr_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_enb_skp_add_when_skpos_is_24_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_ENB_SKP_ADD_WHEN_SKPOS_IS_24_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_clr_cnt_thr_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_mid_offset_thr_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_mid_offset_thr_ow_en_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_FIFO_RD_MID_OFFSET_THR_OW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_fifo_wr_mid_offset_thr_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_fifo_wr_mid_offset_thr_ow_en_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_FIFO_WR_MID_OFFSET_THR_OW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_det_en_rd_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_DET_EN_RD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_det_en_wr_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_DET_EN_WR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_force_en_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_FORCE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_5_cfg_vpcsif_txflow_force_on_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSIF_TXFLOW_FORCE_ON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_5_cfg_vpcsif_txflow_nodatavld_force_on_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSIF_TXFLOW_NODATAVLD_FORCE_ON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_5_cfg_vpcsroreg_ckgate_dsbl_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSROREG_CKGATE_DSBL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_5_cfg_vpcstbus_ckgate_dsbl_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSTBUS_CKGATE_DSBL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_6_cfg_vpcsbist_udp_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_7_cfg_vpcsbist_udp_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_8_cfg_vpcsebuf_fifo_mid_thr_attr == 7'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_8_cfg_vpcsebuf_fifo_mid_thr_sris_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_force_neg_disp_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_force_pos_disp_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_tx_force_err_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_8_cfg_vpcsif_idle_cntr_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_8_cfg_vpcsif_ovr_blockaligncontrol_attr == UX_PCS_LANE_Q0_REG_8_CFG_VPCSIF_OVR_BLOCKALIGNCONTROL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_8_cfg_vpcsif_ovr_blockaligncontrol_ena_attr == UX_PCS_LANE_Q0_REG_8_CFG_VPCSIF_OVR_BLOCKALIGNCONTROL_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_9_cfg_vpcsif_min_reset_cntr_max_attr == 11'd1000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_9_cfg_vpcsif_min_txidle_cntr_max_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_chng_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_CHNG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_ebuf_mode_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_EBUF_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_ebuf_mode_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_EBUF_MODE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_encodedecodebypass_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_ENCODEDECODEBYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_encodedecodebypass_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_ENCODEDECODEBYPASS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_getlocalpresetcoefficients_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_GETLOCALPRESETCOEFFICIENTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_getlocalpresetcoefficients_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_GETLOCALPRESETCOEFFICIENTS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_localpresetindex_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_localpresetindex_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOCALPRESETINDEX_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_lowpin_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOWPIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_lowpin_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOWPIN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_m2p_bus_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_M2P_BUS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_pclk_as_input_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_PCLK_AS_INPUT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane6.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_pclk_as_input_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_PCLK_AS_INPUT_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_m2p_bus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclk_rate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclk_rate_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLK_RATE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclkchangeack_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLKCHANGEACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclkchangeack_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLKCHANGEACK_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_phy_mode_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_phy_mode_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PHY_MODE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_powerdown_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_powerdown_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_POWERDOWN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rate_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RATE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rst_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rst_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RST_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rxelecidle_disable_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RXELECIDLE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rxelecidle_disable_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RXELECIDLE_DISABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxeqeval_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXEQEVAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxeqeval_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXEQEVAL_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpolarity_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpolarity_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPOLARITY_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpresethint_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpresethint_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPRESETHINT_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxstandby_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXSTANDBY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxstandby_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXSTANDBY_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxtermination_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXTERMINATION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxtermination_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXTERMINATION_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_srisenable_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_srisenable_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_SRISENABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcmnmode_disable_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCMNMODE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcmnmode_disable_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCMNMODE_DISABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcompliance_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCOMPLIANCE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcompliance_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCOMPLIANCE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdeemph_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDEEMPH_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdtctrx_lb_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDTCTRX_LB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdtctrx_lb_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDTCTRX_LB_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txelecidle_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txelecidle_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXELECIDLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txmargin_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txmargin_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXMARGIN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txoneszeros_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXONESZEROS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txoneszeros_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXONESZEROS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txdeemph_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txswing_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_TXSWING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txswing_ena_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_TXSWING_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_width_ena_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_WIDTH_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p1subentry_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P1SUBENTRY_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p1subexit_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P1SUBEXIT_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p2entry_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P2ENTRY_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p2exit_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P2EXIT_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatusgen_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUSGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxdetect_inpciep2_en_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXDETECT_INPCIEP2_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxpstate_p0s_en_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXPSTATE_P0S_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxstandby0en_in_rxeq_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXSTANDBY0EN_IN_RXEQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie5_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_usb1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_usb2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_tx_pcie1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie5_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_usb1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_usb2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_14_cfg_vpcslb_fe_attr == UX_PCS_LANE_Q0_REG_14_CFG_VPCSLB_FE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_14_cfg_vpcsmbusconv_illegal_rd_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_14_CFG_VPCSMBUSCONV_ILLEGAL_RD_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_15_cfg_vpcslfps_ctrl_p3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_illegal_wr_c_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_ILLEGAL_WR_C_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_illegal_wr_uc_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_ILLEGAL_WR_UC_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_ack_gen_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_ACK_GEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timeout_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_COMPL_TIMEOUT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timer_en_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_COMPL_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timer_max_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_gen_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_GEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timeout_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_TIMEOUT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timer_en_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timer_max_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_15_cfg_vpcsonezero_one_cntr_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_15_cfg_vpcstxdrv_usb_gen1_txdeemph_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSTXDRV_USB_GEN1_TXDEEMPH_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_16_cfg_vpcsonezero_zero_cntr_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_16_cfg_vpcstbus_addr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_16_cfg_vpcstx_gen4_preset0_attr == 18'd60032
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_16_cfg_vpcstxdrv_usb_gen1_txswing_attr == UX_PCS_LANE_Q0_REG_16_CFG_VPCSTXDRV_USB_GEN1_TXSWING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_17_cfg_vpcsspare0_attr == 32'd4294901760
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_18_cfg_vpcstx_gen4_preset1_attr == 18'd39872
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_18_cfg_vpcstx_localfs_attr == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_18_cfg_vpcstx_localg4fs_attr == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_19_cfg_vpcstx_gen4_preset10_attr == 18'd80192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_19_cfg_vpcstx_localg4lf_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_19_cfg_vpcstx_locallf_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_1_cfg_vcpsckgate_disable_attr == UX_PCS_LANE_Q0_REG_1_CFG_VCPSCKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_1_cfg_vpcs_if_clk_sel_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCS_IF_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_1_cfg_vpcsalign10b_lock_cnt_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_1_cfg_vpcsalign10b_unlock_cnt_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_1_cfg_vpcsalign128b_g3g4_skp_os_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSALIGN128B_G3G4_SKP_OS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_1_cfg_vpcsalign128b_usb2_ctrl_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_clr_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_en_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_hold_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_data_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_en_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_init_ctrl_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_INIT_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_init_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_insert_err_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_INSERT_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_skp_cnt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_1_cfg_vpcsebuf_reset_on_err_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSEBUF_RESET_ON_ERR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_20_cfg_vpcstx_gen4_preset2_attr == 18'd47936
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_20_cfg_vpcstxdrv_levn_gen1_0_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_20_cfg_vpcstxdrv_levn_gen1_1_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_21_cfg_vpcstx_gen4_preset3_attr == 18'd31808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_21_cfg_vpcstxdrv_levn_gen1_10_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_21_cfg_vpcstxdrv_levn_gen1_11_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_22_cfg_vpcstx_gen4_preset4_attr == 18'd3584
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_22_cfg_vpcstxdrv_levn_gen1_12_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_22_cfg_vpcstxdrv_levn_gen1_13_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_23_cfg_vpcstx_gen4_preset5_attr == 18'd3206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_23_cfg_vpcstxdrv_levn_gen1_14_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_23_cfg_vpcstxdrv_levn_gen1_15_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_24_cfg_vpcstx_gen4_preset6_attr == 18'd3143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_24_cfg_vpcstxdrv_levn_gen1_2_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_24_cfg_vpcstxdrv_levn_gen1_3_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_25_cfg_vpcstx_gen4_preset7_attr == 18'd47558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_25_cfg_vpcstxdrv_levn_gen1_4_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_25_cfg_vpcstxdrv_levn_gen1_5_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_26_cfg_vpcstx_gen4_preset8_attr == 18'd31367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_26_cfg_vpcstxdrv_levn_gen1_6_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_26_cfg_vpcstxdrv_levn_gen1_7_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_27_cfg_vpcstx_gen4_preset9_attr == 18'd3017
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_27_cfg_vpcstxdrv_levn_gen1_8_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_27_cfg_vpcstxdrv_levn_gen1_9_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_28_cfg_vpcstx_preset0_attr == 18'd60032
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_28_cfg_vpcstxdrv_levn_gen2_0_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_28_cfg_vpcstxdrv_levn_gen2_1_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_29_cfg_vpcstx_preset1_attr == 18'd39872
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_29_cfg_vpcstxdrv_levn_gen2_10_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_29_cfg_vpcstxdrv_levn_gen2_11_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_2_cfg_vpcs_misc_attr == 32'd305419896
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_30_cfg_vpcstx_preset10_attr == 18'd80192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_30_cfg_vpcstxdrv_levn_gen2_12_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_30_cfg_vpcstxdrv_levn_gen2_13_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_31_cfg_vpcstx_preset2_attr == 18'd47936
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_31_cfg_vpcstxdrv_levn_gen2_14_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_31_cfg_vpcstxdrv_levn_gen2_15_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_32_cfg_vpcstx_preset3_attr == 18'd31808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_32_cfg_vpcstxdrv_levn_gen2_2_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_32_cfg_vpcstxdrv_levn_gen2_3_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_33_cfg_vpcstx_preset4_attr == 18'd3584
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_33_cfg_vpcstxdrv_levn_gen2_4_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_33_cfg_vpcstxdrv_levn_gen2_5_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_34_cfg_vpcstx_preset5_attr == 18'd3206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_34_cfg_vpcstxdrv_levn_gen2_6_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_34_cfg_vpcstxdrv_levn_gen2_7_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_35_cfg_vpcstx_preset6_attr == 18'd3143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_35_cfg_vpcstxdrv_levn_gen2_8_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_35_cfg_vpcstxdrv_levn_gen2_9_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_36_cfg_vpcstx_preset7_attr == 18'd47558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_levnm1_gen1_0_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_levnm1_gen1_1_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_txdrvslew_gen1_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_37_cfg_vpcstx_preset8_attr == 18'd31367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_levnm1_gen1_10_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_levnm1_gen1_11_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_txdrvslew_gen2_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_38_cfg_vpcstx_preset9_attr == 18'd3017
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_levnm1_gen1_12_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_levnm1_gen1_13_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_txdrvslew_gen3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_14_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_15_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_2_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_3_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_5_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_3_cfg_vpcsbist_gen_skp_delay_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_3_cfg_vpcsebuf_fifo_full_thr_attr == 7'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_3_cfg_vpcsebuf_fifo_full_thr_sris_attr == 7'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_3_cfg_vpcseios_det_en_attr == UX_PCS_LANE_Q0_REG_3_CFG_VPCSEIOS_DET_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_3_cfg_vpcsif_blockaligncontrolpolarity_attr == UX_PCS_LANE_Q0_REG_3_CFG_VPCSIF_BLOCKALIGNCONTROLPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_6_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_7_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_8_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_9_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen2_0_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen2_1_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_10_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_11_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_12_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_13_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_14_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_15_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_2_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_3_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_5_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_6_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_7_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_levnm1_gen2_8_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_levnm1_gen2_9_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_txdrvslew_gen4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_good_syncheader_align_dis_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSALIGN128B_GOOD_SYNCHEADER_ALIGN_DIS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_unalign_lb_en_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSALIGN128B_UNALIGN_LB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_unalign_lb_wait_cnt_thr_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_data_en_falling_dly_ovr_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_DATA_EN_FALLING_DLY_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_data_en_falling_dly_thr_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_enb_skp_add_when_skpos_is_24_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_ENB_SKP_ADD_WHEN_SKPOS_IS_24_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_clr_cnt_thr_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_mid_offset_thr_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_mid_offset_thr_ow_en_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_FIFO_RD_MID_OFFSET_THR_OW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_fifo_wr_mid_offset_thr_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_fifo_wr_mid_offset_thr_ow_en_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_FIFO_WR_MID_OFFSET_THR_OW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_det_en_rd_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_DET_EN_RD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_det_en_wr_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_DET_EN_WR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_force_en_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_FORCE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_5_cfg_vpcsif_txflow_force_on_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSIF_TXFLOW_FORCE_ON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_5_cfg_vpcsif_txflow_nodatavld_force_on_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSIF_TXFLOW_NODATAVLD_FORCE_ON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_5_cfg_vpcsroreg_ckgate_dsbl_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSROREG_CKGATE_DSBL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_5_cfg_vpcstbus_ckgate_dsbl_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSTBUS_CKGATE_DSBL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_6_cfg_vpcsbist_udp_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_7_cfg_vpcsbist_udp_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_8_cfg_vpcsebuf_fifo_mid_thr_attr == 7'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_8_cfg_vpcsebuf_fifo_mid_thr_sris_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_force_neg_disp_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_force_pos_disp_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_tx_force_err_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_8_cfg_vpcsif_idle_cntr_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_8_cfg_vpcsif_ovr_blockaligncontrol_attr == UX_PCS_LANE_Q0_REG_8_CFG_VPCSIF_OVR_BLOCKALIGNCONTROL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_8_cfg_vpcsif_ovr_blockaligncontrol_ena_attr == UX_PCS_LANE_Q0_REG_8_CFG_VPCSIF_OVR_BLOCKALIGNCONTROL_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_9_cfg_vpcsif_min_reset_cntr_max_attr == 11'd1000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_9_cfg_vpcsif_min_txidle_cntr_max_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_chng_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_CHNG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_ebuf_mode_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_EBUF_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_ebuf_mode_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_EBUF_MODE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_encodedecodebypass_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_ENCODEDECODEBYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_encodedecodebypass_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_ENCODEDECODEBYPASS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_getlocalpresetcoefficients_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_GETLOCALPRESETCOEFFICIENTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_getlocalpresetcoefficients_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_GETLOCALPRESETCOEFFICIENTS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_localpresetindex_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_localpresetindex_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOCALPRESETINDEX_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_lowpin_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOWPIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_lowpin_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOWPIN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_m2p_bus_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_M2P_BUS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_pclk_as_input_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_PCLK_AS_INPUT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane7.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_pclk_as_input_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_PCLK_AS_INPUT_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_m2p_bus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclk_rate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclk_rate_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLK_RATE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclkchangeack_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLKCHANGEACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclkchangeack_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLKCHANGEACK_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_phy_mode_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_phy_mode_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PHY_MODE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_powerdown_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_powerdown_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_POWERDOWN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rate_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RATE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rst_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rst_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RST_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rxelecidle_disable_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RXELECIDLE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rxelecidle_disable_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RXELECIDLE_DISABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxeqeval_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXEQEVAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxeqeval_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXEQEVAL_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpolarity_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpolarity_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPOLARITY_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpresethint_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpresethint_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPRESETHINT_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxstandby_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXSTANDBY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxstandby_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXSTANDBY_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxtermination_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXTERMINATION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxtermination_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXTERMINATION_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_srisenable_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_srisenable_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_SRISENABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcmnmode_disable_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCMNMODE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcmnmode_disable_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCMNMODE_DISABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcompliance_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCOMPLIANCE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcompliance_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCOMPLIANCE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdeemph_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDEEMPH_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdtctrx_lb_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDTCTRX_LB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdtctrx_lb_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDTCTRX_LB_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txelecidle_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txelecidle_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXELECIDLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txmargin_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txmargin_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXMARGIN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txoneszeros_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXONESZEROS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txoneszeros_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXONESZEROS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txdeemph_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txswing_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_TXSWING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txswing_ena_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_TXSWING_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_width_ena_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_WIDTH_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p1subentry_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P1SUBENTRY_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p1subexit_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P1SUBEXIT_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p2entry_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P2ENTRY_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p2exit_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P2EXIT_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatusgen_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUSGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxdetect_inpciep2_en_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXDETECT_INPCIEP2_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxpstate_p0s_en_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXPSTATE_P0S_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxstandby0en_in_rxeq_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXSTANDBY0EN_IN_RXEQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie5_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_usb1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_usb2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_tx_pcie1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie5_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_usb1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_usb2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_14_cfg_vpcslb_fe_attr == UX_PCS_LANE_Q0_REG_14_CFG_VPCSLB_FE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_14_cfg_vpcsmbusconv_illegal_rd_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_14_CFG_VPCSMBUSCONV_ILLEGAL_RD_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_15_cfg_vpcslfps_ctrl_p3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_illegal_wr_c_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_ILLEGAL_WR_C_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_illegal_wr_uc_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_ILLEGAL_WR_UC_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_ack_gen_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_ACK_GEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timeout_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_COMPL_TIMEOUT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timer_en_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_COMPL_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timer_max_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_gen_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_GEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timeout_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_TIMEOUT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timer_en_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timer_max_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_15_cfg_vpcsonezero_one_cntr_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_15_cfg_vpcstxdrv_usb_gen1_txdeemph_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSTXDRV_USB_GEN1_TXDEEMPH_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_16_cfg_vpcsonezero_zero_cntr_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_16_cfg_vpcstbus_addr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_16_cfg_vpcstx_gen4_preset0_attr == 18'd60032
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_16_cfg_vpcstxdrv_usb_gen1_txswing_attr == UX_PCS_LANE_Q0_REG_16_CFG_VPCSTXDRV_USB_GEN1_TXSWING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_17_cfg_vpcsspare0_attr == 32'd4294901760
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_18_cfg_vpcstx_gen4_preset1_attr == 18'd39872
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_18_cfg_vpcstx_localfs_attr == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_18_cfg_vpcstx_localg4fs_attr == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_19_cfg_vpcstx_gen4_preset10_attr == 18'd80192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_19_cfg_vpcstx_localg4lf_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_19_cfg_vpcstx_locallf_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_1_cfg_vcpsckgate_disable_attr == UX_PCS_LANE_Q0_REG_1_CFG_VCPSCKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_1_cfg_vpcs_if_clk_sel_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCS_IF_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_1_cfg_vpcsalign10b_lock_cnt_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_1_cfg_vpcsalign10b_unlock_cnt_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_1_cfg_vpcsalign128b_g3g4_skp_os_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSALIGN128B_G3G4_SKP_OS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_1_cfg_vpcsalign128b_usb2_ctrl_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_clr_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_en_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_hold_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_data_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_en_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_init_ctrl_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_INIT_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_init_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_insert_err_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_INSERT_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_skp_cnt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_1_cfg_vpcsebuf_reset_on_err_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSEBUF_RESET_ON_ERR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_20_cfg_vpcstx_gen4_preset2_attr == 18'd47936
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_20_cfg_vpcstxdrv_levn_gen1_0_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_20_cfg_vpcstxdrv_levn_gen1_1_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_21_cfg_vpcstx_gen4_preset3_attr == 18'd31808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_21_cfg_vpcstxdrv_levn_gen1_10_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_21_cfg_vpcstxdrv_levn_gen1_11_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_22_cfg_vpcstx_gen4_preset4_attr == 18'd3584
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_22_cfg_vpcstxdrv_levn_gen1_12_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_22_cfg_vpcstxdrv_levn_gen1_13_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_23_cfg_vpcstx_gen4_preset5_attr == 18'd3206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_23_cfg_vpcstxdrv_levn_gen1_14_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_23_cfg_vpcstxdrv_levn_gen1_15_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_24_cfg_vpcstx_gen4_preset6_attr == 18'd3143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_24_cfg_vpcstxdrv_levn_gen1_2_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_24_cfg_vpcstxdrv_levn_gen1_3_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_25_cfg_vpcstx_gen4_preset7_attr == 18'd47558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_25_cfg_vpcstxdrv_levn_gen1_4_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_25_cfg_vpcstxdrv_levn_gen1_5_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_26_cfg_vpcstx_gen4_preset8_attr == 18'd31367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_26_cfg_vpcstxdrv_levn_gen1_6_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_26_cfg_vpcstxdrv_levn_gen1_7_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_27_cfg_vpcstx_gen4_preset9_attr == 18'd3017
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_27_cfg_vpcstxdrv_levn_gen1_8_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_27_cfg_vpcstxdrv_levn_gen1_9_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_28_cfg_vpcstx_preset0_attr == 18'd60032
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_28_cfg_vpcstxdrv_levn_gen2_0_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_28_cfg_vpcstxdrv_levn_gen2_1_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_29_cfg_vpcstx_preset1_attr == 18'd39872
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_29_cfg_vpcstxdrv_levn_gen2_10_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_29_cfg_vpcstxdrv_levn_gen2_11_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_2_cfg_vpcs_misc_attr == 32'd305419896
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_30_cfg_vpcstx_preset10_attr == 18'd80192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_30_cfg_vpcstxdrv_levn_gen2_12_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_30_cfg_vpcstxdrv_levn_gen2_13_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_31_cfg_vpcstx_preset2_attr == 18'd47936
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_31_cfg_vpcstxdrv_levn_gen2_14_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_31_cfg_vpcstxdrv_levn_gen2_15_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_32_cfg_vpcstx_preset3_attr == 18'd31808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_32_cfg_vpcstxdrv_levn_gen2_2_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_32_cfg_vpcstxdrv_levn_gen2_3_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_33_cfg_vpcstx_preset4_attr == 18'd3584
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_33_cfg_vpcstxdrv_levn_gen2_4_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_33_cfg_vpcstxdrv_levn_gen2_5_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_34_cfg_vpcstx_preset5_attr == 18'd3206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_34_cfg_vpcstxdrv_levn_gen2_6_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_34_cfg_vpcstxdrv_levn_gen2_7_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_35_cfg_vpcstx_preset6_attr == 18'd3143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_35_cfg_vpcstxdrv_levn_gen2_8_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_35_cfg_vpcstxdrv_levn_gen2_9_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_36_cfg_vpcstx_preset7_attr == 18'd47558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_levnm1_gen1_0_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_levnm1_gen1_1_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_txdrvslew_gen1_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_37_cfg_vpcstx_preset8_attr == 18'd31367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_levnm1_gen1_10_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_levnm1_gen1_11_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_txdrvslew_gen2_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_38_cfg_vpcstx_preset9_attr == 18'd3017
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_levnm1_gen1_12_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_levnm1_gen1_13_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_txdrvslew_gen3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_14_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_15_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_2_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_3_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_5_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_3_cfg_vpcsbist_gen_skp_delay_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_3_cfg_vpcsebuf_fifo_full_thr_attr == 7'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_3_cfg_vpcsebuf_fifo_full_thr_sris_attr == 7'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_3_cfg_vpcseios_det_en_attr == UX_PCS_LANE_Q0_REG_3_CFG_VPCSEIOS_DET_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_3_cfg_vpcsif_blockaligncontrolpolarity_attr == UX_PCS_LANE_Q0_REG_3_CFG_VPCSIF_BLOCKALIGNCONTROLPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_6_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_7_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_8_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_9_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen2_0_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen2_1_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_10_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_11_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_12_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_13_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_14_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_15_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_2_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_3_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_5_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_6_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_7_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_levnm1_gen2_8_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_levnm1_gen2_9_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_txdrvslew_gen4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_good_syncheader_align_dis_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSALIGN128B_GOOD_SYNCHEADER_ALIGN_DIS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_unalign_lb_en_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSALIGN128B_UNALIGN_LB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_unalign_lb_wait_cnt_thr_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_data_en_falling_dly_ovr_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_DATA_EN_FALLING_DLY_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_data_en_falling_dly_thr_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_enb_skp_add_when_skpos_is_24_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_ENB_SKP_ADD_WHEN_SKPOS_IS_24_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_clr_cnt_thr_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_mid_offset_thr_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_mid_offset_thr_ow_en_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_FIFO_RD_MID_OFFSET_THR_OW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_fifo_wr_mid_offset_thr_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_fifo_wr_mid_offset_thr_ow_en_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_FIFO_WR_MID_OFFSET_THR_OW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_det_en_rd_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_DET_EN_RD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_det_en_wr_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_DET_EN_WR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_force_en_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_FORCE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_5_cfg_vpcsif_txflow_force_on_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSIF_TXFLOW_FORCE_ON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_5_cfg_vpcsif_txflow_nodatavld_force_on_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSIF_TXFLOW_NODATAVLD_FORCE_ON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_5_cfg_vpcsroreg_ckgate_dsbl_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSROREG_CKGATE_DSBL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_5_cfg_vpcstbus_ckgate_dsbl_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSTBUS_CKGATE_DSBL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_6_cfg_vpcsbist_udp_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_7_cfg_vpcsbist_udp_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_8_cfg_vpcsebuf_fifo_mid_thr_attr == 7'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_8_cfg_vpcsebuf_fifo_mid_thr_sris_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_force_neg_disp_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_force_pos_disp_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_tx_force_err_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_8_cfg_vpcsif_idle_cntr_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_8_cfg_vpcsif_ovr_blockaligncontrol_attr == UX_PCS_LANE_Q0_REG_8_CFG_VPCSIF_OVR_BLOCKALIGNCONTROL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_8_cfg_vpcsif_ovr_blockaligncontrol_ena_attr == UX_PCS_LANE_Q0_REG_8_CFG_VPCSIF_OVR_BLOCKALIGNCONTROL_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_9_cfg_vpcsif_min_reset_cntr_max_attr == 11'd1000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_9_cfg_vpcsif_min_txidle_cntr_max_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_chng_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_CHNG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_ebuf_mode_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_EBUF_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_ebuf_mode_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_EBUF_MODE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_encodedecodebypass_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_ENCODEDECODEBYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_encodedecodebypass_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_ENCODEDECODEBYPASS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_getlocalpresetcoefficients_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_GETLOCALPRESETCOEFFICIENTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_getlocalpresetcoefficients_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_GETLOCALPRESETCOEFFICIENTS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_localpresetindex_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_localpresetindex_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOCALPRESETINDEX_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_lowpin_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOWPIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_lowpin_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOWPIN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_m2p_bus_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_M2P_BUS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_pclk_as_input_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_PCLK_AS_INPUT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane8.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_pclk_as_input_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_PCLK_AS_INPUT_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_m2p_bus_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclk_rate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclk_rate_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLK_RATE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclkchangeack_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLKCHANGEACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_pclkchangeack_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PCLKCHANGEACK_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_phy_mode_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_phy_mode_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_PHY_MODE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_powerdown_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_powerdown_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_POWERDOWN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rate_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RATE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rst_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rst_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RST_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rxelecidle_disable_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RXELECIDLE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_10_cfg_vpcsif_ovr_rxelecidle_disable_ena_attr == UX_PCS_LANE_Q0_REG_10_CFG_VPCSIF_OVR_RXELECIDLE_DISABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxeqeval_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXEQEVAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxeqeval_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXEQEVAL_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpolarity_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpolarity_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPOLARITY_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpresethint_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxpresethint_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXPRESETHINT_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxstandby_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXSTANDBY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxstandby_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXSTANDBY_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxtermination_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXTERMINATION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_rxtermination_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_RXTERMINATION_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_srisenable_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_srisenable_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_SRISENABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcmnmode_disable_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCMNMODE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcmnmode_disable_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCMNMODE_DISABLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcompliance_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCOMPLIANCE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txcompliance_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXCOMPLIANCE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdeemph_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDEEMPH_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdtctrx_lb_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDTCTRX_LB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txdtctrx_lb_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXDTCTRX_LB_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txelecidle_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txelecidle_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXELECIDLE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txmargin_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txmargin_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXMARGIN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txoneszeros_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXONESZEROS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_11_cfg_vpcsif_ovr_txoneszeros_ena_attr == UX_PCS_LANE_Q0_REG_11_CFG_VPCSIF_OVR_TXONESZEROS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txdeemph_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txswing_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_TXSWING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_txswing_ena_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_TXSWING_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_12_cfg_vpcsif_ovr_width_ena_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_OVR_WIDTH_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p1subentry_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P1SUBENTRY_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p1subexit_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P1SUBEXIT_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p2entry_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P2ENTRY_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatus_p2exit_1cycle_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUS_P2EXIT_1CYCLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_12_cfg_vpcsif_phystatusgen_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_PHYSTATUSGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxdetect_inpciep2_en_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXDETECT_INPCIEP2_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxpstate_p0s_en_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXPSTATE_P0S_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_12_cfg_vpcsif_rxstandby0en_in_rxeq_attr == UX_PCS_LANE_Q0_REG_12_CFG_VPCSIF_RXSTANDBY0EN_IN_RXEQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_pcie5_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_usb1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_rx_usb2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_13_cfg_vpcsif_pma_tx_pcie1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_pcie5_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_usb1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_14_cfg_vpcsif_pma_tx_usb2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_14_cfg_vpcslb_fe_attr == UX_PCS_LANE_Q0_REG_14_CFG_VPCSLB_FE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_14_cfg_vpcslfps_ctrl_p2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_14_cfg_vpcsmbusconv_illegal_rd_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_14_CFG_VPCSMBUSCONV_ILLEGAL_RD_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_15_cfg_vpcslfps_ctrl_p3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_illegal_wr_c_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_ILLEGAL_WR_C_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_illegal_wr_uc_addr_det_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_ILLEGAL_WR_UC_ADDR_DET_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_ack_gen_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_ACK_GEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timeout_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_COMPL_TIMEOUT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timer_en_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_RD_COMPL_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_rd_compl_timer_max_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_gen_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_GEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timeout_clr_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_TIMEOUT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timer_en_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSMBUSCONV_WR_ACK_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_15_cfg_vpcsmbusconv_wr_ack_timer_max_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_15_cfg_vpcsonezero_one_cntr_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_15_cfg_vpcstxdrv_usb_gen1_txdeemph_attr == UX_PCS_LANE_Q0_REG_15_CFG_VPCSTXDRV_USB_GEN1_TXDEEMPH_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_16_cfg_vpcsonezero_zero_cntr_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_16_cfg_vpcstbus_addr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_16_cfg_vpcstx_gen4_preset0_attr == 18'd60032
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_16_cfg_vpcstxdrv_usb_gen1_txswing_attr == UX_PCS_LANE_Q0_REG_16_CFG_VPCSTXDRV_USB_GEN1_TXSWING_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_17_cfg_vpcsspare0_attr == 32'd4294901760
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_18_cfg_vpcstx_gen4_preset1_attr == 18'd39872
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_18_cfg_vpcstx_localfs_attr == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_18_cfg_vpcstx_localg4fs_attr == 6'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_19_cfg_vpcstx_gen4_preset10_attr == 18'd80192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_19_cfg_vpcstx_localg4lf_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_19_cfg_vpcstx_locallf_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_1_cfg_vcpsckgate_disable_attr == UX_PCS_LANE_Q0_REG_1_CFG_VCPSCKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_1_cfg_vpcs_if_clk_sel_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCS_IF_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_1_cfg_vpcsalign10b_lock_cnt_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_1_cfg_vpcsalign10b_unlock_cnt_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_1_cfg_vpcsalign128b_g3g4_skp_os_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSALIGN128B_G3G4_SKP_OS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_1_cfg_vpcsalign128b_usb2_ctrl_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_clr_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_en_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_chk_hold_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_CHK_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_data_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_en_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_init_ctrl_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_INIT_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_init_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_insert_err_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSBIST_GEN_INSERT_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_1_cfg_vpcsbist_gen_skp_cnt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_1_cfg_vpcsebuf_reset_on_err_attr == UX_PCS_LANE_Q0_REG_1_CFG_VPCSEBUF_RESET_ON_ERR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_20_cfg_vpcstx_gen4_preset2_attr == 18'd47936
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_20_cfg_vpcstxdrv_levn_gen1_0_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_20_cfg_vpcstxdrv_levn_gen1_1_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_21_cfg_vpcstx_gen4_preset3_attr == 18'd31808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_21_cfg_vpcstxdrv_levn_gen1_10_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_21_cfg_vpcstxdrv_levn_gen1_11_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_22_cfg_vpcstx_gen4_preset4_attr == 18'd3584
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_22_cfg_vpcstxdrv_levn_gen1_12_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_22_cfg_vpcstxdrv_levn_gen1_13_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_23_cfg_vpcstx_gen4_preset5_attr == 18'd3206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_23_cfg_vpcstxdrv_levn_gen1_14_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_23_cfg_vpcstxdrv_levn_gen1_15_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_24_cfg_vpcstx_gen4_preset6_attr == 18'd3143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_24_cfg_vpcstxdrv_levn_gen1_2_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_24_cfg_vpcstxdrv_levn_gen1_3_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_25_cfg_vpcstx_gen4_preset7_attr == 18'd47558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_25_cfg_vpcstxdrv_levn_gen1_4_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_25_cfg_vpcstxdrv_levn_gen1_5_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_26_cfg_vpcstx_gen4_preset8_attr == 18'd31367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_26_cfg_vpcstxdrv_levn_gen1_6_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_26_cfg_vpcstxdrv_levn_gen1_7_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_27_cfg_vpcstx_gen4_preset9_attr == 18'd3017
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_27_cfg_vpcstxdrv_levn_gen1_8_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_27_cfg_vpcstxdrv_levn_gen1_9_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_28_cfg_vpcstx_preset0_attr == 18'd60032
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_28_cfg_vpcstxdrv_levn_gen2_0_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_28_cfg_vpcstxdrv_levn_gen2_1_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_29_cfg_vpcstx_preset1_attr == 18'd39872
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_29_cfg_vpcstxdrv_levn_gen2_10_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_29_cfg_vpcstxdrv_levn_gen2_11_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_2_cfg_vpcs_misc_attr == 32'd305419896
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_30_cfg_vpcstx_preset10_attr == 18'd80192
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_30_cfg_vpcstxdrv_levn_gen2_12_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_30_cfg_vpcstxdrv_levn_gen2_13_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_31_cfg_vpcstx_preset2_attr == 18'd47936
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_31_cfg_vpcstxdrv_levn_gen2_14_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_31_cfg_vpcstxdrv_levn_gen2_15_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_32_cfg_vpcstx_preset3_attr == 18'd31808
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_32_cfg_vpcstxdrv_levn_gen2_2_attr == 6'd42
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_32_cfg_vpcstxdrv_levn_gen2_3_attr == 6'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_33_cfg_vpcstx_preset4_attr == 18'd3584
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_33_cfg_vpcstxdrv_levn_gen2_4_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_33_cfg_vpcstxdrv_levn_gen2_5_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_34_cfg_vpcstx_preset5_attr == 18'd3206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_34_cfg_vpcstxdrv_levn_gen2_6_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_34_cfg_vpcstxdrv_levn_gen2_7_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_35_cfg_vpcstx_preset6_attr == 18'd3143
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_35_cfg_vpcstxdrv_levn_gen2_8_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_35_cfg_vpcstxdrv_levn_gen2_9_attr == 6'd55
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_36_cfg_vpcstx_preset7_attr == 18'd47558
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_levnm1_gen1_0_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_levnm1_gen1_1_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_36_cfg_vpcstxdrv_txdrvslew_gen1_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_37_cfg_vpcstx_preset8_attr == 18'd31367
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_levnm1_gen1_10_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_levnm1_gen1_11_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_37_cfg_vpcstxdrv_txdrvslew_gen2_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_38_cfg_vpcstx_preset9_attr == 18'd3017
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_levnm1_gen1_12_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_levnm1_gen1_13_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_38_cfg_vpcstxdrv_txdrvslew_gen3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_14_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_15_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_2_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_3_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_39_cfg_vpcstxdrv_levnm1_gen1_5_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_3_cfg_vpcsbist_gen_skp_delay_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_3_cfg_vpcsebuf_fifo_full_thr_attr == 7'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_3_cfg_vpcsebuf_fifo_full_thr_sris_attr == 7'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_3_cfg_vpcseios_det_en_attr == UX_PCS_LANE_Q0_REG_3_CFG_VPCSEIOS_DET_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_3_cfg_vpcsif_blockaligncontrolpolarity_attr == UX_PCS_LANE_Q0_REG_3_CFG_VPCSIF_BLOCKALIGNCONTROLPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_6_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_7_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_8_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen1_9_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen2_0_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_40_cfg_vpcstxdrv_levnm1_gen2_1_attr == 5'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_10_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_11_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_12_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_13_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_14_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_41_cfg_vpcstxdrv_levnm1_gen2_15_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_2_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_3_attr == 5'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_5_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_6_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_42_cfg_vpcstxdrv_levnm1_gen2_7_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_levnm1_gen2_8_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_levnm1_gen2_9_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_43_cfg_vpcstxdrv_txdrvslew_gen4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_good_syncheader_align_dis_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSALIGN128B_GOOD_SYNCHEADER_ALIGN_DIS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_unalign_lb_en_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSALIGN128B_UNALIGN_LB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_4_cfg_vpcsalign128b_unalign_lb_wait_cnt_thr_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_data_en_falling_dly_ovr_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_DATA_EN_FALLING_DLY_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_data_en_falling_dly_thr_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_enb_skp_add_when_skpos_is_24_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_ENB_SKP_ADD_WHEN_SKPOS_IS_24_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_clr_cnt_thr_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_mid_offset_thr_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_4_cfg_vpcsebuf_fifo_rd_mid_offset_thr_ow_en_attr == UX_PCS_LANE_Q0_REG_4_CFG_VPCSEBUF_FIFO_RD_MID_OFFSET_THR_OW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_fifo_wr_mid_offset_thr_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_fifo_wr_mid_offset_thr_ow_en_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_FIFO_WR_MID_OFFSET_THR_OW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_det_en_rd_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_DET_EN_RD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_det_en_wr_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_DET_EN_WR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_5_cfg_vpcsebuf_g3g4_skp_err_force_en_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSEBUF_G3G4_SKP_ERR_FORCE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_5_cfg_vpcsif_txflow_force_on_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSIF_TXFLOW_FORCE_ON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_5_cfg_vpcsif_txflow_nodatavld_force_on_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSIF_TXFLOW_NODATAVLD_FORCE_ON_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_5_cfg_vpcsroreg_ckgate_dsbl_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSROREG_CKGATE_DSBL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_5_cfg_vpcstbus_ckgate_dsbl_attr == UX_PCS_LANE_Q0_REG_5_CFG_VPCSTBUS_CKGATE_DSBL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_6_cfg_vpcsbist_udp_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_7_cfg_vpcsbist_udp_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_8_cfg_vpcsebuf_fifo_mid_thr_attr == 7'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_8_cfg_vpcsebuf_fifo_mid_thr_sris_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_force_neg_disp_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_force_pos_disp_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_8_cfg_vpcsenc_tx_force_err_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_8_cfg_vpcsif_idle_cntr_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_8_cfg_vpcsif_ovr_blockaligncontrol_attr == UX_PCS_LANE_Q0_REG_8_CFG_VPCSIF_OVR_BLOCKALIGNCONTROL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_8_cfg_vpcsif_ovr_blockaligncontrol_ena_attr == UX_PCS_LANE_Q0_REG_8_CFG_VPCSIF_OVR_BLOCKALIGNCONTROL_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_9_cfg_vpcsif_min_reset_cntr_max_attr == 11'd1000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_9_cfg_vpcsif_min_txidle_cntr_max_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_chng_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_CHNG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_ebuf_mode_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_EBUF_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_ebuf_mode_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_EBUF_MODE_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_encodedecodebypass_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_ENCODEDECODEBYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_encodedecodebypass_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_ENCODEDECODEBYPASS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_getlocalpresetcoefficients_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_GETLOCALPRESETCOEFFICIENTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_getlocalpresetcoefficients_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_GETLOCALPRESETCOEFFICIENTS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_localpresetindex_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_localpresetindex_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOCALPRESETINDEX_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_lowpin_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOWPIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_lowpin_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_LOWPIN_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_m2p_bus_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_M2P_BUS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_pclk_as_input_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_PCLK_AS_INPUT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_pcie_ss.u_ptop.ub_uxlane9.ux_pcs_lane_q0_reg_9_cfg_vpcsif_ovr_pclk_as_input_ena_attr == UX_PCS_LANE_Q0_REG_9_CFG_VPCSIF_OVR_PCLK_AS_INPUT_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.all_enabled_refclks_always_running == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.all_ux_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.bot_f_fastest_reconfig_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.bot_refclk_reconfig_span == BOT_REFCLK_RECONFIG_SPAN_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.bot_syspll_refclk_output_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ch1_ch0_master_pll_pair_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ch3_ch2_master_pll_pair_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.clkrx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.f_avmm_clk_hz == 40'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.f_bot_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.f_bot_syspll_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.f_fastest_reconfig_refclk_global_refclk_0_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.f_fastest_reconfig_refclk_global_refclk_1_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.f_fastest_reconfig_refclk_global_refclk_2_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.f_fastest_reconfig_refclk_global_refclk_3_hz == 40'd800000001
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.f_fastest_reconfig_refclk_regional_refclk_0_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.f_fastest_reconfig_refclk_regional_refclk_1_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.f_global_refclk_0_bot_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.f_global_refclk_0_bot_right_top_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.f_global_refclk_1_bot_right_top_left_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.f_global_refclk_1_top_right_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.f_global_refclk_2_bot_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.f_global_refclk_2_bot_right_top_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.f_global_refclk_3_bot_right_top_left_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.f_global_refclk_3_top_right_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.f_local_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.f_regional_refclk_0_bot_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.f_regional_refclk_0_bot_right_top_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.f_regional_refclk_1_bot_right_top_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.f_regional_refclk_1_top_right_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.f_top_refclk_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.f_top_syspll_refclk_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.global_refclk_0_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.global_refclk_0_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.global_refclk_1_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.global_refclk_1_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.global_refclk_2_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.global_refclk_2_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.global_refclk_3_left_adjacent_active == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.global_refclk_3_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.hard_all_ux_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_avmm == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_bot_clkrx_base == POWERMODE_AC_MODE_BOT_CLKRX_BASE_NON_PIN_PRIMARY_DRIVER_HIGH_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_bot_cmos_driver == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_flux == POWERMODE_AC_MODE_FLUX_FLUX_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_global_refclk_0_bot == POWERMODE_AC_MODE_GLOBAL_REFCLK_0_BOT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_global_refclk_0_top == POWERMODE_AC_MODE_GLOBAL_REFCLK_0_TOP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_global_refclk_1_bot == POWERMODE_AC_MODE_GLOBAL_REFCLK_1_BOT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_global_refclk_1_top == POWERMODE_AC_MODE_GLOBAL_REFCLK_1_TOP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_global_refclk_2_bot == POWERMODE_AC_MODE_GLOBAL_REFCLK_2_BOT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_global_refclk_2_top == POWERMODE_AC_MODE_GLOBAL_REFCLK_2_TOP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_global_refclk_3_bot == POWERMODE_AC_MODE_GLOBAL_REFCLK_3_BOT_HIGH_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_global_refclk_3_top == POWERMODE_AC_MODE_GLOBAL_REFCLK_3_TOP_HIGH_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_regional_refclk_0_bot == POWERMODE_AC_MODE_REGIONAL_REFCLK_0_BOT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_regional_refclk_0_top == POWERMODE_AC_MODE_REGIONAL_REFCLK_0_TOP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_regional_refclk_1_bot == POWERMODE_AC_MODE_REGIONAL_REFCLK_1_BOT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_regional_refclk_1_top == POWERMODE_AC_MODE_REGIONAL_REFCLK_1_TOP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_rx_ux0 == UX0_POWERMODE_AC_MODE_RX_NRZ_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_rx_ux1 == UX1_POWERMODE_AC_MODE_RX_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_rx_ux2 == UX2_POWERMODE_AC_MODE_RX_NRZ_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_rx_ux3 == UX3_POWERMODE_AC_MODE_RX_NRZ_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_synth_lc_fast_ux0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_synth_lc_fast_ux1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_synth_lc_fast_ux2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_synth_lc_fast_ux3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_synth_lc_med_ux0 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_synth_lc_med_ux1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_synth_lc_med_ux2 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_synth_lc_med_ux3 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_synth_lc_slow_ux0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_synth_lc_slow_ux1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_synth_lc_slow_ux2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_synth_lc_slow_ux3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_top_clkrx_base == POWERMODE_AC_MODE_TOP_CLKRX_BASE_NON_PIN_PRIMARY_DRIVER_HIGH_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_top_cmos_driver == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_tx_ux0 == UX0_POWERMODE_AC_MODE_TX_NRZ_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_tx_ux1 == UX1_POWERMODE_AC_MODE_TX_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_tx_ux2 == UX2_POWERMODE_AC_MODE_TX_NRZ_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_ac_mode_tx_ux3 == UX3_POWERMODE_AC_MODE_TX_NRZ_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_avmm == 40'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_bot_clkrx_base == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_bot_cmos_driver == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_flux == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_global_refclk_0_bot == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_global_refclk_0_top == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_global_refclk_1_bot == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_global_refclk_1_top == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_global_refclk_2_bot == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_global_refclk_2_top == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_global_refclk_3_bot == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_global_refclk_3_top == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_regional_refclk_0_bot == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_regional_refclk_0_top == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_regional_refclk_1_bot == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_regional_refclk_1_top == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_rx_parallel_ux0 == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_rx_parallel_ux1 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_rx_parallel_ux2 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_rx_parallel_ux3 == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_rx_ux0 == 36'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_rx_ux1 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_rx_ux2 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_rx_ux3 == 36'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_synth_lc_fast_ux0 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_synth_lc_fast_ux1 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_synth_lc_fast_ux2 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_synth_lc_fast_ux3 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_synth_lc_med_ux0 == 40'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_synth_lc_med_ux1 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_synth_lc_med_ux2 == 40'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_synth_lc_med_ux3 == 40'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_synth_lc_slow_ux0 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_synth_lc_slow_ux1 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_synth_lc_slow_ux2 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_synth_lc_slow_ux3 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_top_clkrx_base == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_top_cmos_driver == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_tx_parallel_ux0 == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_tx_parallel_ux1 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_tx_parallel_ux2 == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_tx_parallel_ux3 == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_tx_ux0 == 36'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_tx_ux1 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_tx_ux2 == 36'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.powermode_freq_hz_tx_ux3 == 36'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.refclk0_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.refclk1_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.refclk2_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.refclk3_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.refclk4_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.refclk5_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.refclk6_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.refclk7_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.refclk8_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.refclk9_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.regional_refclk_0_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.regional_refclk_0_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.regional_refclk_1_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.regional_refclk_1_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.top_f_fastest_reconfig_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.top_refclk_reconfig_span == TOP_REFCLK_RECONFIG_SPAN_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.top_syspll_refclk_output_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_cdr_bw_sel == UX0_CDR_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_cdr_f_mod_hz == 40'd990000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_cdr_f_out_hz == 40'd5940000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_cdr_f_pfd_hz == 40'd29700000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_cdr_f_postdiv_hz == 40'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_cdr_f_ref_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_cdr_f_vco_hz == 40'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_cdr_is_cascaded == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_cdr_l_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_cdr_m_counter == 9'd200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_cdr_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_cdr_postdiv_counter == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_cdr_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_cdr_ppm_driftcount == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_cdr_refclk_mux_select == UX0_CDR_REFCLK_MUX_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_cdr_refclk_select == UX0_CDR_REFCLK_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_cmn_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_core_pll == UX0_CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_core_pll_refclk_select == UX0_CORE_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_dpma_refclk_source == UX0_DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_duplex_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_enable_port_control_of_cdr_ltr_ltd == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ethernet_source == UX0_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_expose_pcie_gen1_gen6_critical_signals == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_external_dpma_refclk_source == UX0_EXTERNAL_DPMA_REFCLK_SOURCE_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_fec_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_flux_mode == UX0_FLUX_MODE_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_lane_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_loopback_mode == UX0_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_master_sup_mode == UX0_MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_primary_use == UX0_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ref_clk_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_rx_ac_couple_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_rx_adapt_mode == UX0_RX_ADAPT_MODE_STATIC_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_rx_bond_size == UX0_RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_rx_datarate == 40'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_rx_line_rate_bps == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_rx_master_bond_chnl == UX0_RX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_rx_o_clk_e2_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_rx_o_clk_e4_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_rx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_rx_o_usr_clk_e2_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_rx_o_usr_clk_e4_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_rx_onchip_termination == UX0_RX_ONCHIP_TERMINATION_R_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_rx_protocol == UX0_RX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_rx_term_mode_select == UX0_RX_TERM_MODE_SELECT_DIFFERENTIAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_rx_tuning_hint == UX0_RX_TUNING_HINT_SDI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_rx_user_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_rx_width == UX0_RX_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_rxeq_vga_gain == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_standalone_core_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_standalone_core_clk_mux == UX0_STANDALONE_CORE_CLK_MUX_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sup_mode == UX0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sv_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sv_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sv_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sv_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sv_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sv_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sv_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sv_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sv_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sv_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sv_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sv_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sv_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sv_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sv_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sv_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_sv_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_0_feed_forward_gain == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_0_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_fast_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_fast_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_fast_primary_use == UX0_SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_fb_div_emb_mult_counter == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_fb_div_n_frac_mode == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_med_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_med_f_out_hz == 40'd5940000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_med_f_ref_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_med_f_tx_postdiv_hz == 40'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_med_f_vco_hz == 40'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_med_l_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_med_m_counter == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_med_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_med_primary_use == UX0_SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_med_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_med_tx_postdiv_counter == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_slow_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_slow_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_slow_primary_use == UX0_SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_syspll0_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_syspll1_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_syspll2_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_tx_bond_size == UX0_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_tx_datarate == 40'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_tx_i_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_tx_i_clk_e4_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_tx_i_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_tx_line_rate_bps == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_tx_master_bond_chnl == UX0_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_tx_o_clk_e2_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_tx_o_clk_e4_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_tx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_tx_o_usr_clk_1_e2_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_tx_o_usr_clk_1_e4_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_tx_o_usr_clk_2_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_tx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_tx_pll == UX0_TX_PLL_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_tx_pll_bw_sel == UX0_TX_PLL_BW_SEL_MEDIUM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_tx_pll_refclk_mux_select == UX0_TX_PLL_REFCLK_MUX_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_tx_pll_refclk_select == UX0_TX_PLL_REFCLK_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_tx_protocol == UX0_TX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_tx_tuning_hint == UX0_TX_TUNING_HINT_SDI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_tx_user_clk1_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_tx_user_clk1_mux == UX0_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_tx_user_clk2_mux == UX0_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_tx_user_clk_slow_med_mux == UX0_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_tx_width == UX0_TX_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_txeq_main_tap == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_txrx_channel_operation == UX0_TXRX_CHANNEL_OPERATION_DUAL_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_txrx_line_encoding_type == UX0_TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_txrx_xcvr_speed_bucket == UX0_TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_en_rxbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_en_rxeiosdetectstat_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_en_rxeq_clr_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_en_rxeq_precal_code_sel_lx_nt_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_en_rxeq_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_en_rxeq_static_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_en_rxeyediag_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_en_rxovrcdrlock2dataen_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_en_rxpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_en_rxrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_en_rxterm_hiz_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_en_rxwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_en_txbeacon_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_en_txbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_en_txclkdivrate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_en_txdetectrx_req_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_en_txdrv_levn_lx_5to0 == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_en_txdrv_levnm1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_en_txdrv_levnp1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_en_txdrv_levnp2_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_en_txdrv_spare_l0_1to0 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_en_txdrv_spare_l0_3to2 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_en_txdrv_spare_l0_5to4 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_en_txdrv_spare_l0_9to6 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_en_txelecidle_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_en_txpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_en_txrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_en_txwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_ovr_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_ovr_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_ovr_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_ovr_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_ovr_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_ovr_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_ovr_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_ovr_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_ovr_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_ovr_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_ovr_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_ovr_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_ovr_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_ovr_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_ovr_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_ovr_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_ur_ovr_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux0_vsr_mode == UX0_VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_cdr_bw_sel == UX1_CDR_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_cdr_f_mod_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_cdr_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_cdr_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_cdr_f_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_cdr_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_cdr_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_cdr_is_cascaded == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_cdr_l_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_cdr_m_counter == 9'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_cdr_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_cdr_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_cdr_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_cdr_ppm_driftcount == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_cdr_refclk_mux_select == UX1_CDR_REFCLK_MUX_SELECT_REGIONAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_cdr_refclk_select == UX1_CDR_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_cmn_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_core_pll == UX1_CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_core_pll_refclk_select == UX1_CORE_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_dpma_refclk_source == UX1_DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_duplex_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_enable_port_control_of_cdr_ltr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ethernet_source == UX1_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_expose_pcie_gen1_gen6_critical_signals == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_external_dpma_refclk_source == UX1_EXTERNAL_DPMA_REFCLK_SOURCE_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_flux_mode == UX1_FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_lane_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_loopback_mode == UX1_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_master_sup_mode == UX1_MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_primary_use == UX1_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ref_clk_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_rx_adapt_mode == UX1_RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_rx_bond_size == UX1_RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_rx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_rx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_rx_master_bond_chnl == UX1_RX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_rx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_rx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_rx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_rx_o_usr_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_rx_o_usr_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_rx_onchip_termination == UX1_RX_ONCHIP_TERMINATION_R_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_rx_protocol == UX1_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_rx_term_mode_select == UX1_RX_TERM_MODE_SELECT_GROUNDED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_rx_tuning_hint == UX1_RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_rx_width == UX1_RX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_rxeq_vga_gain == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_standalone_core_clk_mux == UX1_STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sup_mode == UX1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sv_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sv_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sv_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sv_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sv_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sv_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sv_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sv_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sv_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sv_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sv_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sv_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sv_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sv_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sv_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sv_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_sv_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_0_feed_forward_gain == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_0_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_fast_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_fast_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_fast_primary_use == UX1_SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_fb_div_emb_mult_counter == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_med_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_med_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_med_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_med_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_med_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_med_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_med_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_med_primary_use == UX1_SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_slow_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_slow_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_slow_primary_use == UX1_SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_syspll0_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_syspll1_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_syspll2_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_tx_bond_size == UX1_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_tx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_tx_i_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_tx_i_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_tx_i_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_tx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_tx_master_bond_chnl == UX1_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_tx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_tx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_tx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_tx_o_usr_clk_1_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_tx_o_usr_clk_1_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_tx_o_usr_clk_2_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_tx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_tx_pll == UX1_TX_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_tx_pll_bw_sel == UX1_TX_PLL_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_tx_pll_refclk_mux_select == UX1_TX_PLL_REFCLK_MUX_SELECT_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_tx_pll_refclk_select == UX1_TX_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_tx_protocol == UX1_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_tx_tuning_hint == UX1_TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_tx_user_clk1_mux == UX1_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_tx_user_clk2_mux == UX1_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_tx_user_clk_slow_med_mux == UX1_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_tx_width == UX1_TX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_txeq_main_tap == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_txrx_channel_operation == UX1_TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_txrx_line_encoding_type == UX1_TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_txrx_xcvr_speed_bucket == UX1_TXRX_XCVR_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_en_rxbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_en_rxeiosdetectstat_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_en_rxeq_clr_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_en_rxeq_precal_code_sel_lx_nt_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_en_rxeq_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_en_rxeq_static_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_en_rxeyediag_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_en_rxovrcdrlock2dataen_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_en_rxpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_en_rxrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_en_rxterm_hiz_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_en_rxwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_en_txbeacon_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_en_txbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_en_txclkdivrate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_en_txdetectrx_req_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_en_txdrv_levn_lx_5to0 == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_en_txdrv_levnm1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_en_txdrv_levnp1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_en_txdrv_levnp2_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_en_txdrv_spare_l0_1to0 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_en_txdrv_spare_l0_3to2 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_en_txdrv_spare_l0_5to4 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_en_txdrv_spare_l0_9to6 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_en_txelecidle_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_en_txpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_en_txrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_en_txwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_ovr_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_ovr_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_ovr_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_ovr_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_ovr_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_ovr_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_ovr_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_ovr_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_ovr_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_ovr_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_ovr_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_ovr_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_ovr_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_ovr_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_ovr_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_ovr_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_ur_ovr_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux1_vsr_mode == UX1_VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_cdr_bw_sel == UX2_CDR_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_cdr_f_mod_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_cdr_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_cdr_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_cdr_f_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_cdr_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_cdr_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_cdr_is_cascaded == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_cdr_l_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_cdr_m_counter == 9'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_cdr_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_cdr_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_cdr_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_cdr_ppm_driftcount == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_cdr_refclk_mux_select == UX2_CDR_REFCLK_MUX_SELECT_REGIONAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_cdr_refclk_select == UX2_CDR_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_cmn_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_core_pll == UX2_CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_core_pll_refclk_select == UX2_CORE_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_dpma_refclk_source == UX2_DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_duplex_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_enable_port_control_of_cdr_ltr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ethernet_source == UX2_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_expose_pcie_gen1_gen6_critical_signals == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_external_dpma_refclk_source == UX2_EXTERNAL_DPMA_REFCLK_SOURCE_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_fec_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_flux_mode == UX2_FLUX_MODE_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_lane_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_loopback_mode == UX2_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_master_sup_mode == UX2_MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_prbs_mon_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_primary_use == UX2_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ref_clk_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_rx_adapt_mode == UX2_RX_ADAPT_MODE_STATIC_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_rx_bond_size == UX2_RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_rx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_rx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_rx_master_bond_chnl == UX2_RX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_rx_o_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_rx_o_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_rx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_rx_o_usr_clk_e2_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_rx_o_usr_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_rx_onchip_termination == UX2_RX_ONCHIP_TERMINATION_R_4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_rx_protocol == UX2_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_rx_protocol_hard_pcie_lowloss == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_rx_term_mode_select == UX2_RX_TERM_MODE_SELECT_GROUNDED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_rx_tuning_hint == UX2_RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_rx_user_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_rx_width == UX2_RX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_rxeq_vga_gain == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_squelch_detect == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_standalone_core_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_standalone_core_clk_mux == UX2_STANDALONE_CORE_CLK_MUX_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sup_mode == UX2_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sv_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sv_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sv_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sv_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sv_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sv_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sv_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sv_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sv_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sv_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sv_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sv_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sv_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sv_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sv_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sv_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_sv_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_0_feed_forward_gain == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_0_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_fast_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_fast_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_fast_primary_use == UX2_SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_fb_div_emb_mult_counter == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_fb_div_n_frac_mode == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_med_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_med_f_out_hz == 40'd5940000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_med_f_ref_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_med_f_tx_postdiv_hz == 40'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_med_f_vco_hz == 40'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_med_l_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_med_m_counter == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_med_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_med_primary_use == UX2_SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_med_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_med_tx_postdiv_counter == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_slow_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_slow_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_slow_primary_use == UX2_SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_syspll0_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_syspll1_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_syspll2_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_tx_bond_size == UX2_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_tx_datarate == 40'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_tx_i_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_tx_i_clk_e4_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_tx_i_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_tx_line_rate_bps == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_tx_master_bond_chnl == UX2_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_tx_o_clk_e2_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_tx_o_clk_e4_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_tx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_tx_o_usr_clk_1_e2_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_tx_o_usr_clk_1_e4_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_tx_o_usr_clk_2_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_tx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_tx_pll == UX2_TX_PLL_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_tx_pll_bw_sel == UX2_TX_PLL_BW_SEL_MEDIUM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_tx_pll_refclk_mux_select == UX2_TX_PLL_REFCLK_MUX_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_tx_pll_refclk_select == UX2_TX_PLL_REFCLK_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_tx_protocol == UX2_TX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_tx_tuning_hint == UX2_TX_TUNING_HINT_SDI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_tx_user_clk1_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_tx_user_clk1_mux == UX2_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_tx_user_clk2_mux == UX2_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_tx_user_clk_slow_med_mux == UX2_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_tx_width == UX2_TX_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_txeq_main_tap == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_txrx_channel_operation == UX2_TXRX_CHANNEL_OPERATION_DUAL_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_txrx_line_encoding_type == UX2_TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_txrx_xcvr_speed_bucket == UX2_TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_en_rxbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_en_rxeiosdetectstat_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_en_rxeq_clr_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_en_rxeq_precal_code_sel_lx_nt_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_en_rxeq_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_en_rxeq_static_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_en_rxeyediag_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_en_rxovrcdrlock2dataen_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_en_rxpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_en_rxrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_en_rxterm_hiz_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_en_rxwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_en_txbeacon_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_en_txbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_en_txclkdivrate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_en_txdetectrx_req_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_en_txdrv_levn_lx_5to0 == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_en_txdrv_levnm1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_en_txdrv_levnp1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_en_txdrv_levnp2_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_en_txdrv_spare_l0_1to0 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_en_txdrv_spare_l0_3to2 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_en_txdrv_spare_l0_5to4 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_en_txdrv_spare_l0_9to6 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_en_txelecidle_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_en_txpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_en_txrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_en_txwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_ovr_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_ovr_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_ovr_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_ovr_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_ovr_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_ovr_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_ovr_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_ovr_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_ovr_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_ovr_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_ovr_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_ovr_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_ovr_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_ovr_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_ovr_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_ovr_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_ur_ovr_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux2_vsr_mode == UX2_VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_cdr_bw_sel == UX3_CDR_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_cdr_f_mod_hz == 40'd990000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_cdr_f_out_hz == 40'd5940000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_cdr_f_pfd_hz == 40'd29700000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_cdr_f_postdiv_hz == 40'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_cdr_f_ref_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_cdr_f_vco_hz == 40'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_cdr_is_cascaded == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_cdr_l_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_cdr_m_counter == 9'd200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_cdr_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_cdr_postdiv_counter == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_cdr_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_cdr_ppm_driftcount == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_cdr_refclk_mux_select == UX3_CDR_REFCLK_MUX_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_cdr_refclk_select == UX3_CDR_REFCLK_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_cmn_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_core_pll == UX3_CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_core_pll_refclk_select == UX3_CORE_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_dpma_refclk_source == UX3_DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_duplex_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_enable_port_control_of_cdr_ltr_ltd == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ethernet_source == UX3_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_expose_pcie_gen1_gen6_critical_signals == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_external_dpma_refclk_source == UX3_EXTERNAL_DPMA_REFCLK_SOURCE_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_fec_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_flux_mode == UX3_FLUX_MODE_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_lane_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_loopback_mode == UX3_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_master_sup_mode == UX3_MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_primary_use == UX3_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ref_clk_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_rx_ac_couple_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_rx_adapt_mode == UX3_RX_ADAPT_MODE_STATIC_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_rx_bond_size == UX3_RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_rx_datarate == 40'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_rx_line_rate_bps == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_rx_master_bond_chnl == UX3_RX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_rx_o_clk_e2_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_rx_o_clk_e4_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_rx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_rx_o_usr_clk_e2_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_rx_o_usr_clk_e4_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_rx_onchip_termination == UX3_RX_ONCHIP_TERMINATION_R_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_rx_protocol == UX3_RX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_rx_term_mode_select == UX3_RX_TERM_MODE_SELECT_DIFFERENTIAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_rx_tuning_hint == UX3_RX_TUNING_HINT_SDI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_rx_user_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_rx_width == UX3_RX_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_rxeq_vga_gain == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_standalone_core_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_standalone_core_clk_mux == UX3_STANDALONE_CORE_CLK_MUX_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sup_mode == UX3_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sv_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sv_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sv_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sv_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sv_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sv_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sv_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sv_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sv_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sv_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sv_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sv_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sv_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sv_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sv_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sv_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_sv_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_0_feed_forward_gain == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_0_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_fast_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_fast_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_fast_primary_use == UX3_SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_fb_div_emb_mult_counter == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_fb_div_n_frac_mode == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_med_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_med_f_out_hz == 40'd5940000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_med_f_ref_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_med_f_tx_postdiv_hz == 40'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_med_f_vco_hz == 40'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_med_l_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_med_m_counter == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_med_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_med_primary_use == UX3_SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_med_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_med_tx_postdiv_counter == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_slow_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_slow_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_slow_primary_use == UX3_SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_syspll0_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_syspll1_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_syspll2_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_tx_bond_size == UX3_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_tx_datarate == 40'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_tx_i_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_tx_i_clk_e4_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_tx_i_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_tx_line_rate_bps == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_tx_master_bond_chnl == UX3_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_tx_o_clk_e2_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_tx_o_clk_e4_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_tx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_tx_o_usr_clk_1_e2_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_tx_o_usr_clk_1_e4_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_tx_o_usr_clk_2_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_tx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_tx_pll == UX3_TX_PLL_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_tx_pll_bw_sel == UX3_TX_PLL_BW_SEL_MEDIUM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_tx_pll_refclk_mux_select == UX3_TX_PLL_REFCLK_MUX_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_tx_pll_refclk_select == UX3_TX_PLL_REFCLK_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_tx_protocol == UX3_TX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_tx_tuning_hint == UX3_TX_TUNING_HINT_SDI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_tx_user_clk1_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_tx_user_clk1_mux == UX3_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_tx_user_clk2_mux == UX3_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_tx_user_clk_slow_med_mux == UX3_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_tx_width == UX3_TX_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_txeq_main_tap == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_txrx_channel_operation == UX3_TXRX_CHANNEL_OPERATION_DUAL_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_txrx_line_encoding_type == UX3_TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_txrx_xcvr_speed_bucket == UX3_TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_en_rxbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_en_rxeiosdetectstat_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_en_rxeq_clr_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_en_rxeq_precal_code_sel_lx_nt_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_en_rxeq_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_en_rxeq_static_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_en_rxeyediag_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_en_rxovrcdrlock2dataen_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_en_rxpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_en_rxrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_en_rxterm_hiz_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_en_rxwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_en_txbeacon_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_en_txbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_en_txclkdivrate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_en_txdetectrx_req_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_en_txdrv_levn_lx_5to0 == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_en_txdrv_levnm1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_en_txdrv_levnp1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_en_txdrv_levnp2_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_en_txdrv_spare_l0_1to0 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_en_txdrv_spare_l0_3to2 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_en_txdrv_spare_l0_5to4 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_en_txdrv_spare_l0_9to6 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_en_txelecidle_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_en_txpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_en_txrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_en_txwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_ovr_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_ovr_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_ovr_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_ovr_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_ovr_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_ovr_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_ovr_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_ovr_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_ovr_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_ovr_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_ovr_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_ovr_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_ovr_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_ovr_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_ovr_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_ovr_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_ur_ovr_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux3_vsr_mode == UX3_VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK1_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux_q_ckmux_cpu_attr == CKMUX_CPU_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux_q_i_pll0_hz == 36'd250000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux_q_i_pll1_hz == 36'd250000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux_q_i_pll2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux_quad_instance == UX_QUAD_INSTANCE_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.ux_speed_grade == UX_SPEED_GRADE_DASH2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.all_ux_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.bot_f_fastest_reconfig_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.bot_refclk_reconfig_span == BOT_REFCLK_RECONFIG_SPAN_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.bot_syspll_refclk_output_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.cdrdiv_offchip_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ch1_ch0_master_pll_pair_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ch3_ch2_master_pll_pair_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.clkrx_bot_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.clkrx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.clkrx_top_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_bot_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_bot_syspll_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_ch1_ch0_master_pll_pair_cascade_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_ch3_ch2_master_pll_pair_cascade_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_fastest_reconfig_refclk_global_refclk_0_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_fastest_reconfig_refclk_global_refclk_1_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_fastest_reconfig_refclk_global_refclk_2_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_fastest_reconfig_refclk_global_refclk_3_hz == 40'd800000001
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_fastest_reconfig_refclk_regional_refclk_0_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_fastest_reconfig_refclk_regional_refclk_1_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_full_quad_master_pll_cascade_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_global_refclk_0_bot_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_global_refclk_0_bot_right_top_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_global_refclk_0_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_global_refclk_0_top_right_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_global_refclk_1_bot_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_global_refclk_1_bot_right_top_left_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_global_refclk_1_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_global_refclk_1_top_right_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_global_refclk_2_bot_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_global_refclk_2_bot_right_top_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_global_refclk_2_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_global_refclk_2_top_right_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_global_refclk_3_bot_left_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_global_refclk_3_bot_right_top_left_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_global_refclk_3_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_global_refclk_3_top_right_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_local_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_regional_refclk_0_bot_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_regional_refclk_0_bot_right_top_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_regional_refclk_0_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_regional_refclk_0_top_right_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_regional_refclk_1_bot_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_regional_refclk_1_bot_right_top_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_regional_refclk_1_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_regional_refclk_1_top_right_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_regional_refclk_2_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_regional_refclk_3_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_top_refclk_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.f_top_syspll_refclk_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.fabric_iram_fabric_iram_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.global_refclk_0_bot_control == GLOBAL_REFCLK_0_BOT_CONTROL_ENABLE_T2R_B2L_NO_PASS_THRU
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.global_refclk_0_bot_power_mode == GLOBAL_REFCLK_0_BOT_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.global_refclk_0_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.global_refclk_0_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.global_refclk_0_top_control == GLOBAL_REFCLK_0_TOP_CONTROL_ENABLE_T2R_B2L_NO_PASS_THRU
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.global_refclk_0_top_power_mode == GLOBAL_REFCLK_0_TOP_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.global_refclk_1_bot_control == GLOBAL_REFCLK_1_BOT_CONTROL_ENABLE_T2R_B2L_NO_PASS_THRU
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.global_refclk_1_bot_power_mode == GLOBAL_REFCLK_1_BOT_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.global_refclk_1_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.global_refclk_1_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.global_refclk_1_top_control == GLOBAL_REFCLK_1_TOP_CONTROL_ENABLE_T2R_B2L_NO_PASS_THRU
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.global_refclk_1_top_power_mode == GLOBAL_REFCLK_1_TOP_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.global_refclk_2_bot_control == GLOBAL_REFCLK_2_BOT_CONTROL_ENABLE_T2R_B2L_NO_PASS_THRU
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.global_refclk_2_bot_power_mode == GLOBAL_REFCLK_2_BOT_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.global_refclk_2_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.global_refclk_2_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.global_refclk_2_top_control == GLOBAL_REFCLK_2_TOP_CONTROL_ENABLE_T2R_B2L_NO_PASS_THRU
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.global_refclk_2_top_power_mode == GLOBAL_REFCLK_2_TOP_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.global_refclk_3_bot_control == GLOBAL_REFCLK_3_BOT_CONTROL_ENABLE_R2L_L2B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.global_refclk_3_bot_power_mode == GLOBAL_REFCLK_3_BOT_POWER_MODE_HIGH_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.global_refclk_3_left_adjacent_active == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.global_refclk_3_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.global_refclk_3_top_control == GLOBAL_REFCLK_3_TOP_CONTROL_ENABLE_L2R_R2T
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.global_refclk_3_top_power_mode == GLOBAL_REFCLK_3_TOP_POWER_MODE_HIGH_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.hard_all_ux_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.local_clock_line_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.quad_global_refclk_0_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.quad_global_refclk_1_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.quad_global_refclk_2_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.quad_global_refclk_3_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.quad_regional_refclk_0_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.quad_regional_refclk_1_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.regional_refclk_0_bot_control == REGIONAL_REFCLK_0_BOT_CONTROL_ENABLE_T2R_B2L_NO_PASS_THRU
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.regional_refclk_0_bot_power_mode == REGIONAL_REFCLK_0_BOT_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.regional_refclk_0_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.regional_refclk_0_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.regional_refclk_0_top_control == REGIONAL_REFCLK_0_TOP_CONTROL_ENABLE_T2R_B2L_NO_PASS_THRU
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.regional_refclk_0_top_power_mode == REGIONAL_REFCLK_0_TOP_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.regional_refclk_1_bot_control == REGIONAL_REFCLK_1_BOT_CONTROL_ENABLE_T2R_B2L_NO_PASS_THRU
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.regional_refclk_1_bot_power_mode == REGIONAL_REFCLK_1_BOT_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.regional_refclk_1_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.regional_refclk_1_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.regional_refclk_1_top_control == REGIONAL_REFCLK_1_TOP_CONTROL_ENABLE_T2R_B2L_NO_PASS_THRU
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.regional_refclk_1_top_power_mode == REGIONAL_REFCLK_1_TOP_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_fw_loader_cfg_data_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_fw_loader_cfg_fw_loader_en_attr == SCMNG_FW_LOADER_CFG_FW_LOADER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_fw_loader_cfg_offset_addr_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_fw_loader_cfg_single_mode_en_attr == SCMNG_FW_LOADER_CFG_SINGLE_MODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_ahb_non_posted_write_attr == SCMNG_PM_CFG_AHB_NON_POSTED_WRITE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_an_done_lane0_attr == SCMNG_PM_CFG_AN_DONE_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_an_done_lane1_attr == SCMNG_PM_CFG_AN_DONE_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_an_done_lane2_attr == SCMNG_PM_CFG_AN_DONE_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_an_done_lane3_attr == SCMNG_PM_CFG_AN_DONE_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_apb_broadcast_feature_en_attr == SCMNG_PM_CFG_APB_BROADCAST_FEATURE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_apb_broadcast_type_attr == SCMNG_PM_CFG_APB_BROADCAST_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_apb_security_check_en_attr == SCMNG_PM_CFG_APB_SECURITY_CHECK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_cfg_top_head_visactl0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_cfg_top_head_visactl1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_cfg_top_head_visactl2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_cfg_top_head_visactl3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_cfg_top_head_visaenable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_cpi_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_cpi_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_cpi_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_ecc_double_attr == SCMNG_PM_CFG_ECC_DOUBLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_error_l0_attr == SCMNG_PM_CFG_ERROR_L0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_error_l1_attr == SCMNG_PM_CFG_ERROR_L1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_error_l2_attr == SCMNG_PM_CFG_ERROR_L2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_error_l3_attr == SCMNG_PM_CFG_ERROR_L3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_fabric_wd_counter_max_attr == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_link_mng_cpi_cmd_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_link_mng_cpi_data_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_one_bit_error_corrected_attr == SCMNG_PM_CFG_ONE_BIT_ERROR_CORRECTED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_phy_cpi_cmd_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_phy_cpi_data_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_phy_owner_cpi_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_probe_addr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_rx_ready_lane0_attr == SCMNG_PM_CFG_RX_READY_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_rx_ready_lane1_attr == SCMNG_PM_CFG_RX_READY_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_rx_ready_lane2_attr == SCMNG_PM_CFG_RX_READY_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_rx_ready_lane3_attr == SCMNG_PM_CFG_RX_READY_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_sw_reserved_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_trn_done_lane0_attr == SCMNG_PM_CFG_TRN_DONE_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_trn_done_lane1_attr == SCMNG_PM_CFG_TRN_DONE_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_trn_done_lane2_attr == SCMNG_PM_CFG_TRN_DONE_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_trn_done_lane3_attr == SCMNG_PM_CFG_TRN_DONE_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_tx_ready_lane0_attr == SCMNG_PM_CFG_TX_READY_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_tx_ready_lane1_attr == SCMNG_PM_CFG_TX_READY_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_tx_ready_lane2_attr == SCMNG_PM_CFG_TX_READY_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_tx_ready_lane3_attr == SCMNG_PM_CFG_TX_READY_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_visa_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_visa_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.scmng_pm_cfg_visa_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_aon_cfg_ckgate_disable_attr == SERDES_IP_CLKRX_BOT_AON_CFG_CKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_aon_cfg_cmn_powerup_attr == SERDES_IP_CLKRX_BOT_AON_CFG_CMN_POWERUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_aon_cfg_cmn_powerup_override_en_attr == SERDES_IP_CLKRX_BOT_AON_CFG_CMN_POWERUP_OVERRIDE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_aon_cfg_cmntstbus_addr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_aon_cfg_synth_force_pup_attr == SERDES_IP_CLKRX_BOT_AON_CFG_SYNTH_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_aon_cfg_synth_force_pup_en_attr == SERDES_IP_CLKRX_BOT_AON_CFG_SYNTH_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_aprobe_bot_en_attr == SERDES_IP_CLKRX_BOT_CFG_APROBE_BOT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_aprobe_left_en_attr == SERDES_IP_CLKRX_BOT_CFG_APROBE_LEFT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_aprobe_right_en_attr == SERDES_IP_CLKRX_BOT_CFG_APROBE_RIGHT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_aprobe_top_en_attr == SERDES_IP_CLKRX_BOT_CFG_APROBE_TOP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmn_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmn_pg_disable_attr == SERDES_IP_CLKRX_BOT_CFG_CMN_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmn_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnaprobeclkrx_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnbs_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnbshihyst_attr == SERDES_IP_CLKRX_BOT_CFG_CMNBSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalptr_pstate_refckregopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalptr_pstate_swfabricregopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalptr_quad_refckregopampoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalptr_quad_swfabricregopampoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffset_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREFCKREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffsetfsm_clear_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREFCKREGOPAMPOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffsetfsm_init_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREFCKREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffsetfsm_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREFCKREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffsetfsm_req_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREFCKREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREFCKREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffsetfsmout_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREFCKREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffsetmeas_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREFCKREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffsetmeas_req_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREFCKREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_finish_side_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_invert_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_round_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_runcount_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_signmagen_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetmeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetmeas_validdlycount_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffset_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALSWFABRICREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffsetfsm_clear_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffsetfsm_init_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffsetfsm_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffsetfsm_req_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffsetfsmout_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffsetmeas_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALSWFABRICREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffsetmeas_req_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALSWFABRICREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrx_bypass_en_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRX_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxcdrdiv_bot_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXCDRDIV_BOT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxcdrdiv_input_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxcdrdiv_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXCDRDIV_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxcdrdiv_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXCDRDIV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxcdrdiv_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXCDRDIV_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxcdrdiv_top_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXCDRDIV_TOP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbuf_buf2dpma_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXREFCKBUF_BUF2DPMA_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbuf_cml_ena_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXREFCKBUF_CML_ENA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbuf_core_cmos_ena_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXREFCKBUF_CORE_CMOS_ENA_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbuf_hs_cmos_ena_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXREFCKBUF_HS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbuf_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXREFCKBUF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbuf_powersave_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXREFCKBUF_POWERSAVE_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbuf_termcal_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbuf_termhiz_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXREFCKBUF_TERMHIZ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbufsel_hs_ls_b_path_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXREFCKBUFSEL_HS_LS_B_PATH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbufsel_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXREFCKBUFSEL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxspare_attr == 16'd61440
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxsynthdiv_bot_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXSYNTHDIV_BOT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxsynthdiv_input_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxsynthdiv_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXSYNTHDIV_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxsynthdiv_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXSYNTHDIV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxsynthdiv_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXSYNTHDIV_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxsynthdiv_top_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXSYNTHDIV_TOP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmndprobe_addr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnfsm_cken_ovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnfsm_cken_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_changeref_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_REFCK_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_changeref_val_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_REFCK_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_en_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_REFCK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_smpltime_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refckm_charge_up_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_REFCKM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refckm_pull_dn_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_REFCKM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refckm_sense_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_REFCKM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refckp_charge_up_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_REFCKP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refckp_pull_dn_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_REFCKP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refckp_sense_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_REFCKP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_cdrdivsel_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_hsrefsel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_hsrefsel_powersave_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_HSREFSEL_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_lcrefsel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_lcrefsel_powersave_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_LCREFSEL_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_pad2cmos_ana_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_PAD2CMOS_ANA_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_pad2cmos_dig_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_PAD2CMOS_DIG_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel0_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel0_powersave_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_REFSEL0_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel1_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel1_powersave_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_REFSEL1_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel2_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel2_powersave_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_REFSEL2_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel3_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel3_powersave_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_REFSEL3_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel4_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel4_powersave_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_REFSEL4_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel5_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel5_powersave_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_REFSEL5_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_synthdivsel_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_termhiz_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_TERMHIZ_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrefckctrl_auto_powerdown_en_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREFCKCTRL_AUTO_POWERDOWN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrefckctrl_cml_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREFCKCTRL_CML_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrefckctrl_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREFCKCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrefckreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s0q0_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s0q1_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s0q2_attr == 10'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s0q3_attr == 10'd250
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s0q4_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s0q5_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s0q6_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s0q7_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s1q0_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s1q1_attr == 10'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s1q2_attr == 10'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s1q3_attr == 10'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s1q4_attr == 10'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s1q5_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s1q6_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s1q7_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s2q0_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s2q1_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s2q2_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s2q3_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s2q4_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s2q5_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s2q6_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s2q7_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_en_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_dn_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_up_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_up_ptr1_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_dn_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_up_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_up_ptr1_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_aetrcmn_refckregpwrupacc_ovr_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_AETRCMN_REFCKREGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_aetrcmn_refckregpwrupacc_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_AETRCMN_REFCKREGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_aetrcmn_swfabricregpwrupacc_ovr_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_AETRCMN_SWFABRICREGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_aetrcmn_swfabricregpwrupacc_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_AETRCMN_SWFABRICREGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdcmn_refckbuf_ovr_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdcmn_refckbuf_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdcmn_refckreg_ovr_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDCMN_REFCKREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdcmn_refckreg_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDCMN_REFCKREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdcmn_swfabric_ovr_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDCMN_SWFABRIC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdcmn_swfabric_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDCMN_SWFABRIC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdcmn_swfabricreg_ovr_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDCMN_SWFABRICREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdcmn_swfabricreg_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDCMN_SWFABRICREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdrefck_ntl_b_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDREFCK_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdrefck_ntl_ovr_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDREFCK_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_arstcmn_refckregreset_ovr_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_ARSTCMN_REFCKREGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_arstcmn_refckregreset_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_ARSTCMN_REFCKREGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_arstcmn_swfabricregreset_ovr_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_ARSTCMN_SWFABRICREGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_arstcmn_swfabricregreset_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_ARSTCMN_SWFABRICREGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref0_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF0_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref0_powersave_b_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF0_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref0_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF0_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref0_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref1_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF1_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref1_powersave_b_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF1_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref1_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF1_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref1_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref2_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF2_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref2_powersave_b_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF2_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref2_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF2_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref2_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref3_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF3_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref3_powersave_b_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF3_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref3_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF3_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref3_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref4_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF4_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref4_powersave_b_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF4_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref4_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF4_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref4_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref5_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF5_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref5_powersave_b_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF5_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref5_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF5_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref5_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref6_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF6_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref6_powersave_b_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF6_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref6_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF6_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref6_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref7_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF7_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref7_powersave_b_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF7_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref7_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF7_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref7_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabricreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_egress_override_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_EGRESS_OVERRIDE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_egress_override_val_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_p_vdd_pwrgood_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_P_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_p_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_P_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_pa_vdd_ehv_pwrgood_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_pa_vdd_ehv_pwrgood_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_pa_vdd_pwrgood_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_PA_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_pa_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_PA_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_burnin_mode_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_BURNIN_MODE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_burnin_mode_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_BURNIN_MODE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_cdrdivsel_nt_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_cdrdivsel_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_CDRDIVSEL_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_cmnclkrxrefckbufsel_hs_ls_b_path_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_CMNCLKRXREFCKBUFSEL_HS_LS_B_PATH_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_cmnclkrxrefckbufsel_hs_ls_b_path_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_CMNCLKRXREFCKBUFSEL_HS_LS_B_PATH_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_hsrefsel_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_hsrefsel_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_HSREFSEL_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_hsrefsel_powersave_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_HSREFSEL_POWERSAVE_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_hsrefsel_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_HSREFSEL_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_jtagid_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_JTAGID_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_jtagslvid_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_JTAGSLVID_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_pad2cmos_ana_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_PAD2CMOS_ANA_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_pad2cmos_ana_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_PAD2CMOS_ANA_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_pad2cmos_dig_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_PAD2CMOS_DIG_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_pad2cmos_dig_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_PAD2CMOS_DIG_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_powerup_a_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_POWERUP_A_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_powerup_a_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_POWERUP_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel0_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel0_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel0_powersave_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL0_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel0_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL0_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel1_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel1_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL1_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel1_powersave_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL1_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel1_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL1_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel2_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel2_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL2_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel2_powersave_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL2_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel2_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL2_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel3_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel3_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL3_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel3_powersave_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL3_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel3_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL3_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel4_nt_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel4_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL4_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel4_powersave_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL4_POWERSAVE_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel4_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL4_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel5_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel5_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL5_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel5_powersave_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL5_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel5_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL5_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_synthdivsel_nt_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_synthdivsel_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_SYNTHDIVSEL_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_termhiz_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_TERMHIZ_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_termhiz_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_TERMHIZ_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_vdd_ehv_sel_nt_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_vdd_ehv_sel_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_VDD_EHV_SEL_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_spare_nt_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_spare_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_SPARE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_idat_txbscan_n_attr == SERDES_IP_CLKRX_BOT_IF_CFG_IDAT_TXBSCAN_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_idat_txbscan_n_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_IDAT_TXBSCAN_N_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_idat_txbscan_p_attr == SERDES_IP_CLKRX_BOT_IF_CFG_IDAT_TXBSCAN_P_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_idat_txbscan_p_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_IDAT_TXBSCAN_P_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_irst_ref_por_b_a_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_IRST_REF_POR_B_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_irst_ref_tstbus_b_a_attr == SERDES_IP_CLKRX_BOT_IF_CFG_IRST_REF_TSTBUS_B_A_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_bot_if_cfg_irst_ref_tstbus_b_a_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_IRST_REF_TSTBUS_B_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_aon_cfg_ckgate_disable_attr == SERDES_IP_CLKRX_TOP_AON_CFG_CKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_aon_cfg_cmn_powerup_attr == SERDES_IP_CLKRX_TOP_AON_CFG_CMN_POWERUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_aon_cfg_cmn_powerup_override_en_attr == SERDES_IP_CLKRX_TOP_AON_CFG_CMN_POWERUP_OVERRIDE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_aon_cfg_cmntstbus_addr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_aon_cfg_synth_force_pup_attr == SERDES_IP_CLKRX_TOP_AON_CFG_SYNTH_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_aon_cfg_synth_force_pup_en_attr == SERDES_IP_CLKRX_TOP_AON_CFG_SYNTH_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_aprobe_bot_en_attr == SERDES_IP_CLKRX_TOP_CFG_APROBE_BOT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_aprobe_left_en_attr == SERDES_IP_CLKRX_TOP_CFG_APROBE_LEFT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_aprobe_right_en_attr == SERDES_IP_CLKRX_TOP_CFG_APROBE_RIGHT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_aprobe_top_en_attr == SERDES_IP_CLKRX_TOP_CFG_APROBE_TOP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmn_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmn_pg_disable_attr == SERDES_IP_CLKRX_TOP_CFG_CMN_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmn_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnaprobeclkrx_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnbs_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnbshihyst_attr == SERDES_IP_CLKRX_TOP_CFG_CMNBSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalptr_pstate_refckregopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalptr_pstate_swfabricregopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalptr_quad_refckregopampoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalptr_quad_swfabricregopampoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffset_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREFCKREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffsetfsm_clear_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREFCKREGOPAMPOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffsetfsm_init_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREFCKREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffsetfsm_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREFCKREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffsetfsm_req_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREFCKREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREFCKREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffsetfsmout_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREFCKREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffsetmeas_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREFCKREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffsetmeas_req_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREFCKREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_finish_side_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_invert_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_round_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_runcount_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_signmagen_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetmeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetmeas_validdlycount_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffset_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALSWFABRICREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffsetfsm_clear_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffsetfsm_init_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffsetfsm_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffsetfsm_req_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffsetfsmout_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffsetmeas_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALSWFABRICREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffsetmeas_req_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALSWFABRICREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrx_bypass_en_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRX_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxcdrdiv_bot_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXCDRDIV_BOT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxcdrdiv_input_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxcdrdiv_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXCDRDIV_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxcdrdiv_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXCDRDIV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxcdrdiv_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXCDRDIV_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxcdrdiv_top_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXCDRDIV_TOP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbuf_buf2dpma_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXREFCKBUF_BUF2DPMA_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbuf_cml_ena_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXREFCKBUF_CML_ENA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbuf_core_cmos_ena_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXREFCKBUF_CORE_CMOS_ENA_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbuf_hs_cmos_ena_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXREFCKBUF_HS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbuf_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXREFCKBUF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbuf_powersave_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXREFCKBUF_POWERSAVE_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbuf_termcal_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbuf_termhiz_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXREFCKBUF_TERMHIZ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbufsel_hs_ls_b_path_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXREFCKBUFSEL_HS_LS_B_PATH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbufsel_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXREFCKBUFSEL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxspare_attr == 16'd61440
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxsynthdiv_bot_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXSYNTHDIV_BOT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxsynthdiv_input_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxsynthdiv_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXSYNTHDIV_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxsynthdiv_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXSYNTHDIV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxsynthdiv_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXSYNTHDIV_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxsynthdiv_top_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXSYNTHDIV_TOP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmndprobe_addr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnfsm_cken_ovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnfsm_cken_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_changeref_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_REFCK_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_changeref_val_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_REFCK_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_en_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_REFCK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_smpltime_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refckm_charge_up_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_REFCKM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refckm_pull_dn_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_REFCKM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refckm_sense_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_REFCKM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refckp_charge_up_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_REFCKP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refckp_pull_dn_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_REFCKP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refckp_sense_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_REFCKP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnref_cdrdivsel_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnref_hsrefsel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnref_hsrefsel_powersave_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_HSREFSEL_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnref_lcrefsel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnref_lcrefsel_powersave_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_LCREFSEL_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnref_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnref_pad2cmos_ana_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_PAD2CMOS_ANA_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnref_pad2cmos_dig_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_PAD2CMOS_DIG_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel0_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel0_powersave_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_REFSEL0_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel1_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel1_powersave_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_REFSEL1_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel2_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel2_powersave_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_REFSEL2_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel3_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel3_powersave_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_REFSEL3_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel4_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel4_powersave_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_REFSEL4_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel5_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel5_powersave_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_REFSEL5_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnref_synthdivsel_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnref_termhiz_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_TERMHIZ_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrefckctrl_auto_powerdown_en_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREFCKCTRL_AUTO_POWERDOWN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrefckctrl_cml_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREFCKCTRL_CML_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrefckctrl_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREFCKCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrefckreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s0q0_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s0q1_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s0q2_attr == 10'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s0q3_attr == 10'd250
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s0q4_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s0q5_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s0q6_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s0q7_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s1q0_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s1q1_attr == 10'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s1q2_attr == 10'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s1q3_attr == 10'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s1q4_attr == 10'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s1q5_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s1q6_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s1q7_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s2q0_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s2q1_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s2q2_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s2q3_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s2q4_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s2q5_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s2q6_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s2q7_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_en_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_dn_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_up_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_up_ptr1_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_dn_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_up_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_up_ptr1_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_aetrcmn_refckregpwrupacc_ovr_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_AETRCMN_REFCKREGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_aetrcmn_refckregpwrupacc_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_AETRCMN_REFCKREGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_aetrcmn_swfabricregpwrupacc_ovr_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_AETRCMN_SWFABRICREGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_aetrcmn_swfabricregpwrupacc_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_AETRCMN_SWFABRICREGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdcmn_refckbuf_ovr_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdcmn_refckbuf_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdcmn_refckreg_ovr_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDCMN_REFCKREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdcmn_refckreg_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDCMN_REFCKREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdcmn_swfabric_ovr_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDCMN_SWFABRIC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdcmn_swfabric_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDCMN_SWFABRIC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdcmn_swfabricreg_ovr_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDCMN_SWFABRICREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdcmn_swfabricreg_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDCMN_SWFABRICREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdrefck_ntl_b_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDREFCK_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdrefck_ntl_ovr_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDREFCK_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_arstcmn_refckregreset_ovr_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_ARSTCMN_REFCKREGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_arstcmn_refckregreset_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_ARSTCMN_REFCKREGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_arstcmn_swfabricregreset_ovr_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_ARSTCMN_SWFABRICREGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_arstcmn_swfabricregreset_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_ARSTCMN_SWFABRICREGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref0_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF0_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref0_powersave_b_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF0_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref0_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF0_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref0_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref1_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF1_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref1_powersave_b_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF1_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref1_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF1_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref1_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref2_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF2_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref2_powersave_b_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF2_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref2_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF2_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref2_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref3_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF3_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref3_powersave_b_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF3_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref3_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF3_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref3_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref4_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF4_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref4_powersave_b_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF4_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref4_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF4_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref4_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref5_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF5_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref5_powersave_b_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF5_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref5_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF5_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref5_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref6_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF6_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref6_powersave_b_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF6_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref6_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF6_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref6_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref7_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF7_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref7_powersave_b_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF7_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref7_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF7_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref7_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabricreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_egress_override_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_EGRESS_OVERRIDE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_egress_override_val_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_p_vdd_pwrgood_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_P_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_p_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_P_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_pa_vdd_ehv_pwrgood_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_pa_vdd_ehv_pwrgood_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_pa_vdd_pwrgood_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_PA_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_pa_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_PA_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_burnin_mode_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_BURNIN_MODE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_burnin_mode_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_BURNIN_MODE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_cdrdivsel_nt_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_cdrdivsel_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_CDRDIVSEL_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_cmnclkrxrefckbufsel_hs_ls_b_path_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_CMNCLKRXREFCKBUFSEL_HS_LS_B_PATH_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_cmnclkrxrefckbufsel_hs_ls_b_path_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_CMNCLKRXREFCKBUFSEL_HS_LS_B_PATH_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_hsrefsel_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_hsrefsel_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_HSREFSEL_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_hsrefsel_powersave_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_HSREFSEL_POWERSAVE_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_hsrefsel_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_HSREFSEL_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_jtagid_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_JTAGID_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_jtagslvid_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_JTAGSLVID_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_pad2cmos_ana_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_PAD2CMOS_ANA_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_pad2cmos_ana_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_PAD2CMOS_ANA_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_pad2cmos_dig_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_PAD2CMOS_DIG_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_pad2cmos_dig_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_PAD2CMOS_DIG_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_powerup_a_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_POWERUP_A_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_powerup_a_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_POWERUP_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel0_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel0_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel0_powersave_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL0_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel0_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL0_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel1_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel1_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL1_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel1_powersave_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL1_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel1_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL1_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel2_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel2_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL2_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel2_powersave_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL2_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel2_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL2_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel3_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel3_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL3_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel3_powersave_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL3_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel3_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL3_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel4_nt_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel4_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL4_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel4_powersave_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL4_POWERSAVE_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel4_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL4_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel5_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel5_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL5_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel5_powersave_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL5_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel5_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL5_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_synthdivsel_nt_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_synthdivsel_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_SYNTHDIVSEL_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_termhiz_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_TERMHIZ_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_termhiz_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_TERMHIZ_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_vdd_ehv_sel_nt_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_vdd_ehv_sel_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_VDD_EHV_SEL_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_spare_nt_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_spare_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_SPARE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_idat_txbscan_n_attr == SERDES_IP_CLKRX_TOP_IF_CFG_IDAT_TXBSCAN_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_idat_txbscan_n_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_IDAT_TXBSCAN_N_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_idat_txbscan_p_attr == SERDES_IP_CLKRX_TOP_IF_CFG_IDAT_TXBSCAN_P_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_idat_txbscan_p_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_IDAT_TXBSCAN_P_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_irst_ref_por_b_a_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_IRST_REF_POR_B_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_irst_ref_tstbus_b_a_attr == SERDES_IP_CLKRX_TOP_IF_CFG_IRST_REF_TSTBUS_B_A_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_clkrx_top_if_cfg_irst_ref_tstbus_b_a_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_IRST_REF_TSTBUS_B_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l0_cfg_ckgate_disable_attr == SERDES_IP_CMN_AON_L0_CFG_CKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l0_cfg_cmn_force_pup_attr == SERDES_IP_CMN_AON_L0_CFG_CMN_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l0_cfg_cmn_force_pup_en_attr == SERDES_IP_CMN_AON_L0_CFG_CMN_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l0_cfg_cmn_rst_b_attr == SERDES_IP_CMN_AON_L0_CFG_CMN_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l0_cfg_cmn_rst_en_attr == SERDES_IP_CMN_AON_L0_CFG_CMN_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l0_cfg_cmnclk_ctrl_attr == SERDES_IP_CMN_AON_L0_CFG_CMNCLK_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l0_cfg_cmnclkdiv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l0_cfg_cmnfsm_pmu_req_attr == SERDES_IP_CMN_AON_L0_CFG_CMNFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l0_cfg_cmnfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L0_CFG_CMNFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l0_cfg_cmntstbus_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcfast_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcfast_force_pup_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCFAST_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcfast_force_pup_en_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCFAST_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcfast_ignore_mode_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCFAST_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcfast_rst_b_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCFAST_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcfast_rst_en_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCFAST_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcfastfsm_pmu_req_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCFASTFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcfastfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCFASTFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcmed_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcmed_force_pup_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCMED_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcmed_force_pup_en_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCMED_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcmed_ignore_mode_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCMED_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcmed_rst_b_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCMED_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcmed_rst_en_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCMED_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcmedfsm_pmu_req_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCMEDFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcmedfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCMEDFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcslow_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcslow_force_pup_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCSLOW_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcslow_force_pup_en_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCSLOW_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcslow_ignore_mode_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCSLOW_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcslow_rst_b_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCSLOW_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcslow_rst_en_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCSLOW_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcslowfsm_pmu_req_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCSLOWFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcslowfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCSLOWFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l0_cfg_tstbus_rst_bypass_attr == SERDES_IP_CMN_AON_L0_CFG_TSTBUS_RST_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l0_cfg_tstbus_rst_bypass_en_attr == SERDES_IP_CMN_AON_L0_CFG_TSTBUS_RST_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l1_cfg_ckgate_disable_attr == SERDES_IP_CMN_AON_L1_CFG_CKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l1_cfg_cmn_force_pup_attr == SERDES_IP_CMN_AON_L1_CFG_CMN_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l1_cfg_cmn_force_pup_en_attr == SERDES_IP_CMN_AON_L1_CFG_CMN_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l1_cfg_cmn_rst_b_attr == SERDES_IP_CMN_AON_L1_CFG_CMN_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l1_cfg_cmn_rst_en_attr == SERDES_IP_CMN_AON_L1_CFG_CMN_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l1_cfg_cmnclk_ctrl_attr == SERDES_IP_CMN_AON_L1_CFG_CMNCLK_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l1_cfg_cmnclkdiv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l1_cfg_cmnfsm_pmu_req_attr == SERDES_IP_CMN_AON_L1_CFG_CMNFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l1_cfg_cmnfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L1_CFG_CMNFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l1_cfg_cmntstbus_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcfast_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcfast_force_pup_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCFAST_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcfast_force_pup_en_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCFAST_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcfast_ignore_mode_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCFAST_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcfast_rst_b_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCFAST_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcfast_rst_en_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCFAST_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcfastfsm_pmu_req_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCFASTFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcfastfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCFASTFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcmed_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcmed_force_pup_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCMED_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcmed_force_pup_en_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCMED_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcmed_ignore_mode_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCMED_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcmed_rst_b_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCMED_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcmed_rst_en_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCMED_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcmedfsm_pmu_req_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCMEDFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcmedfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCMEDFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcslow_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcslow_force_pup_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCSLOW_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcslow_force_pup_en_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCSLOW_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcslow_ignore_mode_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCSLOW_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcslow_rst_b_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCSLOW_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcslow_rst_en_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCSLOW_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcslowfsm_pmu_req_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCSLOWFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcslowfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCSLOWFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l1_cfg_tstbus_rst_bypass_attr == SERDES_IP_CMN_AON_L1_CFG_TSTBUS_RST_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l1_cfg_tstbus_rst_bypass_en_attr == SERDES_IP_CMN_AON_L1_CFG_TSTBUS_RST_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l2_cfg_ckgate_disable_attr == SERDES_IP_CMN_AON_L2_CFG_CKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l2_cfg_cmn_force_pup_attr == SERDES_IP_CMN_AON_L2_CFG_CMN_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l2_cfg_cmn_force_pup_en_attr == SERDES_IP_CMN_AON_L2_CFG_CMN_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l2_cfg_cmn_rst_b_attr == SERDES_IP_CMN_AON_L2_CFG_CMN_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l2_cfg_cmn_rst_en_attr == SERDES_IP_CMN_AON_L2_CFG_CMN_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l2_cfg_cmnclk_ctrl_attr == SERDES_IP_CMN_AON_L2_CFG_CMNCLK_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l2_cfg_cmnclkdiv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l2_cfg_cmnfsm_pmu_req_attr == SERDES_IP_CMN_AON_L2_CFG_CMNFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l2_cfg_cmnfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L2_CFG_CMNFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l2_cfg_cmntstbus_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcfast_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcfast_force_pup_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCFAST_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcfast_force_pup_en_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCFAST_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcfast_ignore_mode_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCFAST_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcfast_rst_b_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCFAST_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcfast_rst_en_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCFAST_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcfastfsm_pmu_req_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCFASTFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcfastfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCFASTFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcmed_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcmed_force_pup_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCMED_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcmed_force_pup_en_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCMED_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcmed_ignore_mode_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCMED_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcmed_rst_b_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCMED_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcmed_rst_en_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCMED_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcmedfsm_pmu_req_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCMEDFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcmedfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCMEDFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcslow_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcslow_force_pup_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCSLOW_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcslow_force_pup_en_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCSLOW_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcslow_ignore_mode_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCSLOW_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcslow_rst_b_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCSLOW_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcslow_rst_en_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCSLOW_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcslowfsm_pmu_req_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCSLOWFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcslowfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCSLOWFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l2_cfg_tstbus_rst_bypass_attr == SERDES_IP_CMN_AON_L2_CFG_TSTBUS_RST_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l2_cfg_tstbus_rst_bypass_en_attr == SERDES_IP_CMN_AON_L2_CFG_TSTBUS_RST_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l3_cfg_ckgate_disable_attr == SERDES_IP_CMN_AON_L3_CFG_CKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l3_cfg_cmn_force_pup_attr == SERDES_IP_CMN_AON_L3_CFG_CMN_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l3_cfg_cmn_force_pup_en_attr == SERDES_IP_CMN_AON_L3_CFG_CMN_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l3_cfg_cmn_rst_b_attr == SERDES_IP_CMN_AON_L3_CFG_CMN_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l3_cfg_cmn_rst_en_attr == SERDES_IP_CMN_AON_L3_CFG_CMN_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l3_cfg_cmnclk_ctrl_attr == SERDES_IP_CMN_AON_L3_CFG_CMNCLK_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l3_cfg_cmnclkdiv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l3_cfg_cmnfsm_pmu_req_attr == SERDES_IP_CMN_AON_L3_CFG_CMNFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l3_cfg_cmnfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L3_CFG_CMNFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l3_cfg_cmntstbus_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcfast_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcfast_force_pup_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCFAST_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcfast_force_pup_en_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCFAST_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcfast_ignore_mode_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCFAST_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcfast_rst_b_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCFAST_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcfast_rst_en_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCFAST_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcfastfsm_pmu_req_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCFASTFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcfastfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCFASTFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcmed_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcmed_force_pup_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCMED_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcmed_force_pup_en_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCMED_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcmed_ignore_mode_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCMED_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcmed_rst_b_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCMED_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcmed_rst_en_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCMED_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcmedfsm_pmu_req_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCMEDFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcmedfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCMEDFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcslow_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcslow_force_pup_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCSLOW_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcslow_force_pup_en_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCSLOW_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcslow_ignore_mode_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCSLOW_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcslow_rst_b_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCSLOW_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcslow_rst_en_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCSLOW_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcslowfsm_pmu_req_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCSLOWFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcslowfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCSLOWFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l3_cfg_tstbus_rst_bypass_attr == SERDES_IP_CMN_AON_L3_CFG_TSTBUS_RST_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_aon_l3_cfg_tstbus_rst_bypass_en_attr == SERDES_IP_CMN_AON_L3_CFG_TSTBUS_RST_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_bti_div_attr == 7'd54
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_bti_div_rst_attr == SERDES_IP_CMN_L0_CFG_BTI_DIV_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_bti_en_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_bti_static_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmn_pg_disable_attr == SERDES_IP_CMN_L0_CFG_CMN_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmn_scratch_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnadc_req_attr == SERDES_IP_CMN_L0_CFG_CMNADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnapb2strbbridgecfg_acc_ctrl_field_mask_write_en_attr == SERDES_IP_CMN_L0_CFG_CMNAPB2STRBBRIDGECFG_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnapb2strbbridgecfg_force_state_en_attr == SERDES_IP_CMN_L0_CFG_CMNAPB2STRBBRIDGECFG_FORCE_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnapb2strbbridgecfg_force_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnapb2strbbridgecfg_stbl_time_aftr_strb_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnapb2strbbridgecfg_stbl_time_bfr_strb_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnapb2strbbridgecfg_strb_pulse_width_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnapbmaster_timeout_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobe_addr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobe_lastmux_isolate_attr == SERDES_IP_CMN_L0_CFG_CMNAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobeadc_current_direction_attr == SERDES_IP_CMN_L0_CFG_CMNAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobeadc_resistor_enable_attr == SERDES_IP_CMN_L0_CFG_CMNAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobedac_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobedac_en_attr == SERDES_IP_CMN_L0_CFG_CMNAPROBEDAC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobedacctrl_block_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobedacctrl_en_attr == SERDES_IP_CMN_L0_CFG_CMNAPROBEDACCTRL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobedacctrl_mask_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobedacctrl_rotate_left_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobedacctrl_tstbus_clkdiv_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnbias_icc20uadj_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnbias_icc80uadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnbias_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnbias_termcal_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnbscan_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnbshihyst_attr == SERDES_IP_CMN_L0_CFG_CMNBSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_bg_en_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_bg_one_step_cal_en_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_fg_inc_cal_en_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_fg_one_step_cal_en_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_finish_side_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_initval_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_invert_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_restore_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_round_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_runcount_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_signmagen_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetmeas_req_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_SYNTHDUTYOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncaldacbg_abort_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncaldacbg_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncaldacbg_ready_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncaldacfsm_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncaldacfsm_synthdutyoffsetfsm_clear_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncaldacfsm_synthdutyoffsetfsm_init_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncaldacfsm_synthdutyoffsetfsm_req_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncaldacsynthdutyoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALDACSYNTHDUTYOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncaldacsynthdutyoffsetfsmout_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALDACSYNTHDUTYOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalptr_pstate_rcomp_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalptr_pstate_synthdutyoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalptr_quad_rcomp_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalptr_quad_regopampoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalptr_quad_synthdutyoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_biastrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_cap_tune_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_divrate_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_mode_select_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_ref_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMP_REF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_rx_term_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMP_RX_TERM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_tfr_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMP_TFR_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_tx_term_pd_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMP_TX_TERM_PD_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_tx_term_pu_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMP_TX_TERM_PU_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_txterm_nmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_txterm_pmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_clear_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_code_delay_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_init_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rcomp_tfr_init_cal_value_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rcomp_tfr_max_value_attr == 4'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rcomp_tfr_min_value_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rcomp_txpd_valid_code_lut_vf00_attr == 32'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rcomp_txpd_valid_code_lut_vf01_attr == 32'd4246868100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rcomp_txpu_valid_code_lut_vf00_attr == 32'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rcomp_txpu_valid_code_lut_vf01_attr == 32'd4246868100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_req_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rx_comp_inv_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_RX_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rx_init_cal_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rx_initval_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rx_step_sign_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_RX_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rx_termcode_delta_lut_attr == 31'd24084352
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tfr_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tfr_comp_inv_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_TFR_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tfr_initval_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tfr_step_sign_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_TFR_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tfr_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_time_comp_config_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_time_lpfsetup_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_time_mode_setup_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_time_reset_release_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_time_sample_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tx_pd_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tx_pd_init_cal_value_attr == 6'd49
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tx_pd_max_value_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tx_pd_min_value_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tx_pu_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tx_pu_init_cal_value_attr == 6'd49
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tx_pu_max_value_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tx_pu_min_value_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_txpd_comp_inv_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_TXPD_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_txpd_initval_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_txpd_step_sign_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_TXPD_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_txpd_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_txpu_comp_inv_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_TXPU_COMP_INV_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_txpu_initval_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_txpu_step_sign_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_TXPU_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_txpu_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_txterm_pmos_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmaster_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPMASTER_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmaster_rx_locovr_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmaster_tfr_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmaster_txpd_locovr_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmaster_txpu_locovr_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmaster_valid_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPMASTER_VALID_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmeas_dlycount_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffset_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_clear_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_finish_side_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_init_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_invert_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_req_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_runcount_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsmout_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetmeas_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetmeas_req_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_avg_en_attr == SERDES_IP_CMN_L0_CFG_CMNCKM_AVG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_clk_en_attr == SERDES_IP_CMN_L0_CFG_CMNCKM_CLK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_continuous_attr == SERDES_IP_CMN_L0_CFG_CMNCKM_CONTINUOUS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_dig_meas_en_attr == SERDES_IP_CMN_L0_CFG_CMNCKM_DIG_MEAS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_dig_meas_err_clr_attr == SERDES_IP_CMN_L0_CFG_CMNCKM_DIG_MEAS_ERR_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_en_attr == SERDES_IP_CMN_L0_CFG_CMNCKM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_max_thr_attr == 25'd33554431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_meas_ck_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_ref_ck_div_ratio_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_result_clr_attr == SERDES_IP_CMN_L0_CFG_CMNCKM_RESULT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_start_attr == SERDES_IP_CMN_L0_CFG_CMNCKM_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_wdt_interval_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_win_thr_ref_attr == 25'd16777215
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnclk_keepalive_en_b_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnclk_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmndmondac_en_attr == SERDES_IP_CMN_L0_CFG_CMNDMONDAC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnfsm_cken_ovr_attr == SERDES_IP_CMN_L0_CFG_CMNFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnfsm_cken_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_aprobe1_charge_up_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_APROBE1_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_aprobe1_pull_dn_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_APROBE1_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_aprobe1_sense_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_APROBE1_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_aprobe2_charge_up_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_APROBE2_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_aprobe2_pull_dn_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_APROBE2_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_aprobe2_sense_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_APROBE2_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_changeref_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_changeref_val_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_en_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_CMN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_ntl_sel_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_CMN_NTL_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_refckm_charge_up_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_REFCKM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_refckm_pull_dn_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_REFCKM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_refckm_sense_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_REFCKM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_refckp_charge_up_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_REFCKP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_refckp_pull_dn_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_REFCKP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_refckp_sense_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_REFCKP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnpcs_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnpcs_ref_sel_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnpcs_ref_sel_tx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnperfmon_compare_val_start_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnperfmon_compare_val_stop_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnperfmon_en_attr == SERDES_IP_CMN_L0_CFG_CMNPERFMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnperfmon_mask_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprefckbufprelut_delta_attr == 15'd32767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprefckbufprelut_init_termcal_rx_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprefckbufprelut_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNRCOMPREFCKBUFPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprefckbufprelut_termcal_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprefcktxdrvprelut_delta_attr == 15'd4672
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprefcktxdrvprelut_init_termcal_rx_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprefcktxdrvprelut_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNRCOMPREFCKTXDRVPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprefcktxdrvprelut_termcal_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprxdfeprelut_delta_attr == 15'd32767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprxdfeprelut_init_termcal_tfr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprxdfeprelut_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNRCOMPRXDFEPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprxdfeprelut_termcal_tfr_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckbuf_cml_ena_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKBUF_CML_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckbuf_hs_cmos_ena_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKBUF_HS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckbuf_hs_ls_b_path_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKBUF_HS_LS_B_PATH_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckbuf_hs_ref_to_cdrdiv_ena_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKBUF_HS_REF_TO_CDRDIV_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckbuf_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKBUF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckbuf_ls_cmos_ena_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKBUF_LS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckbuf_powersave_b_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKBUF_POWERSAVE_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckbuf_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckbuf_termhiz_b_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKBUF_TERMHIZ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckdrv_powersave_en_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKDRV_POWERSAVE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrefcktxdrv_cdrdiv_en_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKTXDRV_CDRDIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrefcktxdrv_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKTXDRV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrefcktxdrv_termcal_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_en_b_attr == SERDES_IP_CMN_L0_CFG_CMNRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_entry3_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s0q2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s0q3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s1q4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s1q5_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s1q6_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s1q7_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s2q0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_entry2_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_entry3_attr == 13'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_entry4_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_entry5_attr == 13'd62
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_entry6_attr == 13'd390
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_entry7_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s0q2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s0q3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s1q1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s1q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s1q5_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s1q7_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s2q0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_term_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_term_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_term_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_term_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_term_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_term_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_term_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_term_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_keepalive_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_keepalive_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_bias_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_bias_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_refckbuf_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_refckbuf_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_refckbuf_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_refckbuf_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_rxref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_rxref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_rxref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_rxref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_synthdutycomp_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_synthdutycomp_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_synthdutycomp_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_synthdutycomp_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_synthlcslowref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_synthlcslowref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_synthlcslowref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_synthlcslowref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_txref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_txref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_txref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_txref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpurst_regreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpurst_regreset_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpurst_regreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrpurst_regreset_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_aetrcmn_regpwrupacc_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_AETRCMN_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_aetrcmn_regpwrupacc_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_AETRCMN_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_adc_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_adc_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_ADC_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_biasicc_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_biasicc_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_ntl_b_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_ntl_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_refckbuf_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_refckbuf_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_reg_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_reg_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_rxref_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_RXREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_rxref_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_RXREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_synthlcslowref_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_SYNTHLCSLOWREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_synthlcslowref_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_SYNTHLCSLOWREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_txref_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_TXREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_txref_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_TXREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_arstcmn_adc_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_ARSTCMN_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_arstcmn_adc_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_ARSTCMN_ADC_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_arstcmn_aprobedac_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_ARSTCMN_APROBEDAC_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_arstcmn_refcktxdrv_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_ARSTCMN_REFCKTXDRV_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_arstcmn_refcktxdrv_hiz_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_ARSTCMN_REFCKTXDRV_HIZ_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_arstcmn_regreset_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_ARSTCMN_REGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_arstcmn_regreset_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_ARSTCMN_REGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_synthdutycomp_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_SYNTHDUTYCOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_synthdutycomp_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_SYNTHDUTYCOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrxref_dpma_en_attr == SERDES_IP_CMN_L0_CFG_CMNRXREF_DPMA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrxref_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNRXREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnrxref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnspare0_attr == 32'd163
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnspare_attr == 9'd384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_rxlane0_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_rxlane1_timer_attr == 12'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_rxlane2_timer_attr == 12'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_rxlane3_timer_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_synthlcfast_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_synthlcmed_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_synthlcslow_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_txlane0_timer_attr == 12'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_txlane1_timer_attr == 12'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_txlane2_timer_attr == 12'd70
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_txlane3_timer_attr == 12'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthdiv_cdrdiv_en_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHDIV_CDRDIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthdiv_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHDIV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthdiv_slowmed_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHDIV_SLOWMED_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthdutyoffsetcal_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHDUTYOFFSETCAL_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthdutyoffsetcal_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHDUTYOFFSETCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthdutysel_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHDUTYSEL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthdutysel_mux_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlccaldac_currentdacdcdmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlccaldac_currentdacdcdmeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlccaldac_currentdacdcdmeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlccaldac_currentdacdcdmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlccaldac_synthdutyoffsetmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlccaldac_tx_disable_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHLCCALDAC_TX_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlccaldacerr_calsynthdutyerr_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHLCCALDACERR_CALSYNTHDUTYERR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlccaldacerr_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHLCCALDACERR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlcslowref_dpma_en_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHLCSLOWREF_DPMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlcslowref_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHLCSLOWREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlcslowref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmntxref_dpma_en_attr == SERDES_IP_CMN_L0_CFG_CMNTXREF_DPMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmntxref_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNTXREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmntxref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_cmnynthdutyselpolarity_attr == SERDES_IP_CMN_L0_CFG_CMNYNTHDUTYSELPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_lbcmn_locovren_attr == SERDES_IP_CMN_L0_CFG_LBCMN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_lbcmn_synthlcslowmedpostdivclk2cdrrefclken_locovr_attr == SERDES_IP_CMN_L0_CFG_LBCMN_SYNTHLCSLOWMEDPOSTDIVCLK2CDRREFCLKEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_rcompmaster_en_locovr_attr == SERDES_IP_CMN_L0_CFG_RCOMPMASTER_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_rcompmaster_locovren_attr == SERDES_IP_CMN_L0_CFG_RCOMPMASTER_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_rcompslave_locovr_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_rcompslave_locovren_attr == SERDES_IP_CMN_L0_CFG_RCOMPSLAVE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_rcompslave_valid_locovr_attr == SERDES_IP_CMN_L0_CFG_RCOMPSLAVE_VALID_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_rcompterm_rx_termcode_base_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_rcompterm_tfr_termcode_base_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_rcompterm_txpd_termcode_base_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_rcompterm_txpu_termcode_base_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmed_locovren_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMED_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmed_txbitclkselect_locovr_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMED_TXBITCLKSELECT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedcaldac_locovren_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMEDCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedcalregopampoffset_locovren_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedcalregopampoffsetfsmout_locovren_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedpcs_locovren_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMEDPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedpcs_postdiv2clk0_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedpcs_postdiv2clk0en_locovr_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMEDPCS_POSTDIV2CLK0EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedpcs_postdivclk0en_locovr_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMEDPCS_POSTDIVCLK0EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedreg_lev_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedreg_locovren_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMEDREG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_bti_div_attr == 7'd54
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_bti_div_rst_attr == SERDES_IP_CMN_L1_CFG_BTI_DIV_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_bti_en_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_bti_static_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmn_pg_disable_attr == SERDES_IP_CMN_L1_CFG_CMN_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmn_scratch_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnadc_req_attr == SERDES_IP_CMN_L1_CFG_CMNADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnapb2strbbridgecfg_acc_ctrl_field_mask_write_en_attr == SERDES_IP_CMN_L1_CFG_CMNAPB2STRBBRIDGECFG_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnapb2strbbridgecfg_force_state_en_attr == SERDES_IP_CMN_L1_CFG_CMNAPB2STRBBRIDGECFG_FORCE_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnapb2strbbridgecfg_force_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnapb2strbbridgecfg_stbl_time_aftr_strb_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnapb2strbbridgecfg_stbl_time_bfr_strb_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnapb2strbbridgecfg_strb_pulse_width_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnapbmaster_timeout_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobe_addr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobe_lastmux_isolate_attr == SERDES_IP_CMN_L1_CFG_CMNAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobeadc_current_direction_attr == SERDES_IP_CMN_L1_CFG_CMNAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobeadc_resistor_enable_attr == SERDES_IP_CMN_L1_CFG_CMNAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobedac_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobedac_en_attr == SERDES_IP_CMN_L1_CFG_CMNAPROBEDAC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobedacctrl_block_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobedacctrl_en_attr == SERDES_IP_CMN_L1_CFG_CMNAPROBEDACCTRL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobedacctrl_mask_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobedacctrl_rotate_left_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobedacctrl_tstbus_clkdiv_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnbias_icc20uadj_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnbias_icc80uadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnbias_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnbias_termcal_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnbscan_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnbshihyst_attr == SERDES_IP_CMN_L1_CFG_CMNBSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_bg_en_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_bg_one_step_cal_en_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_fg_inc_cal_en_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_fg_one_step_cal_en_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_finish_side_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_initval_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_invert_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_restore_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_round_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_runcount_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_signmagen_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetmeas_req_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_SYNTHDUTYOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncaldacbg_abort_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncaldacbg_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncaldacbg_ready_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncaldacfsm_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncaldacfsm_synthdutyoffsetfsm_clear_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncaldacfsm_synthdutyoffsetfsm_init_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncaldacfsm_synthdutyoffsetfsm_req_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncaldacsynthdutyoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALDACSYNTHDUTYOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncaldacsynthdutyoffsetfsmout_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALDACSYNTHDUTYOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalptr_pstate_rcomp_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalptr_pstate_synthdutyoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalptr_quad_rcomp_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalptr_quad_regopampoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalptr_quad_synthdutyoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_biastrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_cap_tune_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_divrate_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_mode_select_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_ref_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMP_REF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_rx_term_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMP_RX_TERM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_tfr_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMP_TFR_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_tx_term_pd_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMP_TX_TERM_PD_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_tx_term_pu_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMP_TX_TERM_PU_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_txterm_nmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_txterm_pmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_clear_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_code_delay_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_init_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rcomp_tfr_init_cal_value_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rcomp_tfr_max_value_attr == 4'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rcomp_tfr_min_value_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rcomp_txpd_valid_code_lut_vf00_attr == 32'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rcomp_txpd_valid_code_lut_vf01_attr == 32'd4246868100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rcomp_txpu_valid_code_lut_vf00_attr == 32'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rcomp_txpu_valid_code_lut_vf01_attr == 32'd4246868100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_req_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rx_comp_inv_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_RX_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rx_init_cal_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rx_initval_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rx_step_sign_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_RX_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rx_termcode_delta_lut_attr == 31'd24084352
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tfr_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tfr_comp_inv_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_TFR_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tfr_initval_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tfr_step_sign_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_TFR_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tfr_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_time_comp_config_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_time_lpfsetup_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_time_mode_setup_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_time_reset_release_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_time_sample_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tx_pd_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tx_pd_init_cal_value_attr == 6'd49
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tx_pd_max_value_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tx_pd_min_value_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tx_pu_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tx_pu_init_cal_value_attr == 6'd49
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tx_pu_max_value_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tx_pu_min_value_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_txpd_comp_inv_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_TXPD_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_txpd_initval_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_txpd_step_sign_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_TXPD_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_txpd_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_txpu_comp_inv_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_TXPU_COMP_INV_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_txpu_initval_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_txpu_step_sign_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_TXPU_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_txpu_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_txterm_pmos_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmaster_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPMASTER_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmaster_rx_locovr_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmaster_tfr_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmaster_txpd_locovr_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmaster_txpu_locovr_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmaster_valid_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPMASTER_VALID_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmeas_dlycount_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffset_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_clear_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_finish_side_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_init_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_invert_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_req_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_runcount_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsmout_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetmeas_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetmeas_req_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_avg_en_attr == SERDES_IP_CMN_L1_CFG_CMNCKM_AVG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_clk_en_attr == SERDES_IP_CMN_L1_CFG_CMNCKM_CLK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_continuous_attr == SERDES_IP_CMN_L1_CFG_CMNCKM_CONTINUOUS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_dig_meas_en_attr == SERDES_IP_CMN_L1_CFG_CMNCKM_DIG_MEAS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_dig_meas_err_clr_attr == SERDES_IP_CMN_L1_CFG_CMNCKM_DIG_MEAS_ERR_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_en_attr == SERDES_IP_CMN_L1_CFG_CMNCKM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_max_thr_attr == 25'd33554431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_meas_ck_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_ref_ck_div_ratio_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_result_clr_attr == SERDES_IP_CMN_L1_CFG_CMNCKM_RESULT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_start_attr == SERDES_IP_CMN_L1_CFG_CMNCKM_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_wdt_interval_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_win_thr_ref_attr == 25'd16777215
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnclk_keepalive_en_b_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnclk_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmndmondac_en_attr == SERDES_IP_CMN_L1_CFG_CMNDMONDAC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnfsm_cken_ovr_attr == SERDES_IP_CMN_L1_CFG_CMNFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnfsm_cken_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_aprobe1_charge_up_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_APROBE1_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_aprobe1_pull_dn_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_APROBE1_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_aprobe1_sense_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_APROBE1_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_aprobe2_charge_up_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_APROBE2_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_aprobe2_pull_dn_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_APROBE2_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_aprobe2_sense_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_APROBE2_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_changeref_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_changeref_val_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_en_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_CMN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_ntl_sel_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_CMN_NTL_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_refckm_charge_up_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_REFCKM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_refckm_pull_dn_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_REFCKM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_refckm_sense_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_REFCKM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_refckp_charge_up_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_REFCKP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_refckp_pull_dn_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_REFCKP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_refckp_sense_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_REFCKP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnpcs_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnpcs_ref_sel_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnpcs_ref_sel_tx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnperfmon_compare_val_start_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnperfmon_compare_val_stop_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnperfmon_en_attr == SERDES_IP_CMN_L1_CFG_CMNPERFMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnperfmon_mask_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprefckbufprelut_delta_attr == 15'd32767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprefckbufprelut_init_termcal_rx_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprefckbufprelut_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNRCOMPREFCKBUFPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprefckbufprelut_termcal_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprefcktxdrvprelut_delta_attr == 15'd4672
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprefcktxdrvprelut_init_termcal_rx_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprefcktxdrvprelut_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNRCOMPREFCKTXDRVPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprefcktxdrvprelut_termcal_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprxdfeprelut_delta_attr == 15'd32767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprxdfeprelut_init_termcal_tfr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprxdfeprelut_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNRCOMPRXDFEPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprxdfeprelut_termcal_tfr_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckbuf_cml_ena_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKBUF_CML_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckbuf_hs_cmos_ena_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKBUF_HS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckbuf_hs_ls_b_path_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKBUF_HS_LS_B_PATH_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckbuf_hs_ref_to_cdrdiv_ena_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKBUF_HS_REF_TO_CDRDIV_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckbuf_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKBUF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckbuf_ls_cmos_ena_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKBUF_LS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckbuf_powersave_b_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKBUF_POWERSAVE_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckbuf_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckbuf_termhiz_b_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKBUF_TERMHIZ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckdrv_powersave_en_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKDRV_POWERSAVE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrefcktxdrv_cdrdiv_en_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKTXDRV_CDRDIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrefcktxdrv_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKTXDRV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrefcktxdrv_termcal_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_en_b_attr == SERDES_IP_CMN_L1_CFG_CMNRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_entry3_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s0q2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s0q3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s1q4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s1q5_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s1q6_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s1q7_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s2q0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_entry2_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_entry3_attr == 13'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_entry4_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_entry5_attr == 13'd62
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_entry6_attr == 13'd390
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_entry7_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s0q2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s0q3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s1q1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s1q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s1q5_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s1q7_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s2q0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_term_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_term_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_term_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_term_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_term_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_term_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_term_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_term_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_keepalive_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_keepalive_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_bias_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_bias_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_refckbuf_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_refckbuf_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_refckbuf_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_refckbuf_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_rxref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_rxref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_rxref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_rxref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_synthdutycomp_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_synthdutycomp_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_synthdutycomp_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_synthdutycomp_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_synthlcslowref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_synthlcslowref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_synthlcslowref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_synthlcslowref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_txref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_txref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_txref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_txref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpurst_regreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpurst_regreset_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpurst_regreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrpurst_regreset_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_aetrcmn_regpwrupacc_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_AETRCMN_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_aetrcmn_regpwrupacc_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_AETRCMN_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_adc_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_adc_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_ADC_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_biasicc_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_biasicc_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_ntl_b_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_ntl_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_refckbuf_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_refckbuf_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_reg_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_reg_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_rxref_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_RXREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_rxref_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_RXREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_synthlcslowref_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_SYNTHLCSLOWREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_synthlcslowref_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_SYNTHLCSLOWREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_txref_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_TXREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_txref_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_TXREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_arstcmn_adc_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_ARSTCMN_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_arstcmn_adc_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_ARSTCMN_ADC_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_arstcmn_aprobedac_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_ARSTCMN_APROBEDAC_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_arstcmn_refcktxdrv_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_ARSTCMN_REFCKTXDRV_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_arstcmn_refcktxdrv_hiz_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_ARSTCMN_REFCKTXDRV_HIZ_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_arstcmn_regreset_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_ARSTCMN_REGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_arstcmn_regreset_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_ARSTCMN_REGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_synthdutycomp_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_SYNTHDUTYCOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_synthdutycomp_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_SYNTHDUTYCOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrxref_dpma_en_attr == SERDES_IP_CMN_L1_CFG_CMNRXREF_DPMA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrxref_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNRXREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnrxref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnspare0_attr == 32'd163
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnspare_attr == 9'd384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_rxlane0_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_rxlane1_timer_attr == 12'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_rxlane2_timer_attr == 12'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_rxlane3_timer_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_synthlcfast_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_synthlcmed_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_synthlcslow_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_txlane0_timer_attr == 12'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_txlane1_timer_attr == 12'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_txlane2_timer_attr == 12'd70
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_txlane3_timer_attr == 12'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthdiv_cdrdiv_en_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHDIV_CDRDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthdiv_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHDIV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthdiv_slowmed_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHDIV_SLOWMED_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthdutyoffsetcal_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHDUTYOFFSETCAL_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthdutyoffsetcal_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHDUTYOFFSETCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthdutysel_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHDUTYSEL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthdutysel_mux_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlccaldac_currentdacdcdmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlccaldac_currentdacdcdmeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlccaldac_currentdacdcdmeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlccaldac_currentdacdcdmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlccaldac_synthdutyoffsetmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlccaldac_tx_disable_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHLCCALDAC_TX_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlccaldacerr_calsynthdutyerr_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHLCCALDACERR_CALSYNTHDUTYERR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlccaldacerr_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHLCCALDACERR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlcslowref_dpma_en_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHLCSLOWREF_DPMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlcslowref_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHLCSLOWREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlcslowref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmntxref_dpma_en_attr == SERDES_IP_CMN_L1_CFG_CMNTXREF_DPMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmntxref_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNTXREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmntxref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_cmnynthdutyselpolarity_attr == SERDES_IP_CMN_L1_CFG_CMNYNTHDUTYSELPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_lbcmn_locovren_attr == SERDES_IP_CMN_L1_CFG_LBCMN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_lbcmn_synthlcslowmedpostdivclk2cdrrefclken_locovr_attr == SERDES_IP_CMN_L1_CFG_LBCMN_SYNTHLCSLOWMEDPOSTDIVCLK2CDRREFCLKEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_rcompmaster_en_locovr_attr == SERDES_IP_CMN_L1_CFG_RCOMPMASTER_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_rcompmaster_locovren_attr == SERDES_IP_CMN_L1_CFG_RCOMPMASTER_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_rcompslave_locovr_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_rcompslave_locovren_attr == SERDES_IP_CMN_L1_CFG_RCOMPSLAVE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_rcompslave_valid_locovr_attr == SERDES_IP_CMN_L1_CFG_RCOMPSLAVE_VALID_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_rcompterm_rx_termcode_base_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_rcompterm_tfr_termcode_base_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_rcompterm_txpd_termcode_base_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_rcompterm_txpu_termcode_base_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmed_locovren_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMED_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmed_txbitclkselect_locovr_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMED_TXBITCLKSELECT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedcaldac_locovren_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMEDCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedcalregopampoffset_locovren_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedcalregopampoffsetfsmout_locovren_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedpcs_locovren_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMEDPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedpcs_postdiv2clk0_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedpcs_postdiv2clk0en_locovr_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMEDPCS_POSTDIV2CLK0EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedpcs_postdivclk0en_locovr_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMEDPCS_POSTDIVCLK0EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedreg_lev_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedreg_locovren_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMEDREG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_bti_div_attr == 7'd54
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_bti_div_rst_attr == SERDES_IP_CMN_L2_CFG_BTI_DIV_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_bti_en_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_bti_static_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmn_pg_disable_attr == SERDES_IP_CMN_L2_CFG_CMN_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmn_scratch_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnadc_req_attr == SERDES_IP_CMN_L2_CFG_CMNADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnapb2strbbridgecfg_acc_ctrl_field_mask_write_en_attr == SERDES_IP_CMN_L2_CFG_CMNAPB2STRBBRIDGECFG_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnapb2strbbridgecfg_force_state_en_attr == SERDES_IP_CMN_L2_CFG_CMNAPB2STRBBRIDGECFG_FORCE_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnapb2strbbridgecfg_force_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnapb2strbbridgecfg_stbl_time_aftr_strb_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnapb2strbbridgecfg_stbl_time_bfr_strb_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnapb2strbbridgecfg_strb_pulse_width_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnapbmaster_timeout_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobe_addr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobe_lastmux_isolate_attr == SERDES_IP_CMN_L2_CFG_CMNAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobeadc_current_direction_attr == SERDES_IP_CMN_L2_CFG_CMNAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobeadc_resistor_enable_attr == SERDES_IP_CMN_L2_CFG_CMNAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobedac_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobedac_en_attr == SERDES_IP_CMN_L2_CFG_CMNAPROBEDAC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobedacctrl_block_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobedacctrl_en_attr == SERDES_IP_CMN_L2_CFG_CMNAPROBEDACCTRL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobedacctrl_mask_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobedacctrl_rotate_left_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobedacctrl_tstbus_clkdiv_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnbias_icc20uadj_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnbias_icc80uadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnbias_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnbias_termcal_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnbscan_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnbshihyst_attr == SERDES_IP_CMN_L2_CFG_CMNBSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_bg_en_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_bg_one_step_cal_en_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_fg_inc_cal_en_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_fg_one_step_cal_en_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_finish_side_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_initval_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_invert_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_restore_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_round_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_runcount_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_signmagen_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetmeas_req_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_SYNTHDUTYOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncaldacbg_abort_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncaldacbg_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncaldacbg_ready_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncaldacfsm_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncaldacfsm_synthdutyoffsetfsm_clear_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncaldacfsm_synthdutyoffsetfsm_init_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncaldacfsm_synthdutyoffsetfsm_req_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncaldacsynthdutyoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALDACSYNTHDUTYOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncaldacsynthdutyoffsetfsmout_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALDACSYNTHDUTYOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalptr_pstate_rcomp_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalptr_pstate_synthdutyoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalptr_quad_rcomp_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalptr_quad_regopampoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalptr_quad_synthdutyoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_biastrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_cap_tune_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_divrate_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_mode_select_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_ref_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMP_REF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_rx_term_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMP_RX_TERM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_tfr_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMP_TFR_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_tx_term_pd_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMP_TX_TERM_PD_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_tx_term_pu_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMP_TX_TERM_PU_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_txterm_nmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_txterm_pmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_clear_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_code_delay_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_init_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rcomp_tfr_init_cal_value_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rcomp_tfr_max_value_attr == 4'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rcomp_tfr_min_value_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rcomp_txpd_valid_code_lut_vf00_attr == 32'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rcomp_txpd_valid_code_lut_vf01_attr == 32'd4246868100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rcomp_txpu_valid_code_lut_vf00_attr == 32'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rcomp_txpu_valid_code_lut_vf01_attr == 32'd4246868100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_req_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rx_comp_inv_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_RX_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rx_init_cal_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rx_initval_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rx_step_sign_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_RX_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rx_termcode_delta_lut_attr == 31'd24084352
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tfr_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tfr_comp_inv_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_TFR_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tfr_initval_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tfr_step_sign_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_TFR_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tfr_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_time_comp_config_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_time_lpfsetup_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_time_mode_setup_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_time_reset_release_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_time_sample_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tx_pd_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tx_pd_init_cal_value_attr == 6'd49
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tx_pd_max_value_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tx_pd_min_value_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tx_pu_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tx_pu_init_cal_value_attr == 6'd49
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tx_pu_max_value_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tx_pu_min_value_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_txpd_comp_inv_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_TXPD_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_txpd_initval_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_txpd_step_sign_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_TXPD_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_txpd_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_txpu_comp_inv_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_TXPU_COMP_INV_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_txpu_initval_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_txpu_step_sign_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_TXPU_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_txpu_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_txterm_pmos_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmaster_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPMASTER_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmaster_rx_locovr_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmaster_tfr_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmaster_txpd_locovr_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmaster_txpu_locovr_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmaster_valid_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPMASTER_VALID_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmeas_dlycount_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffset_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_clear_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_finish_side_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_init_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_invert_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_req_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_runcount_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsmout_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetmeas_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetmeas_req_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_avg_en_attr == SERDES_IP_CMN_L2_CFG_CMNCKM_AVG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_clk_en_attr == SERDES_IP_CMN_L2_CFG_CMNCKM_CLK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_continuous_attr == SERDES_IP_CMN_L2_CFG_CMNCKM_CONTINUOUS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_dig_meas_en_attr == SERDES_IP_CMN_L2_CFG_CMNCKM_DIG_MEAS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_dig_meas_err_clr_attr == SERDES_IP_CMN_L2_CFG_CMNCKM_DIG_MEAS_ERR_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_en_attr == SERDES_IP_CMN_L2_CFG_CMNCKM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_max_thr_attr == 25'd33554431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_meas_ck_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_ref_ck_div_ratio_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_result_clr_attr == SERDES_IP_CMN_L2_CFG_CMNCKM_RESULT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_start_attr == SERDES_IP_CMN_L2_CFG_CMNCKM_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_wdt_interval_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_win_thr_ref_attr == 25'd16777215
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnclk_keepalive_en_b_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnclk_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmndmondac_en_attr == SERDES_IP_CMN_L2_CFG_CMNDMONDAC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnfsm_cken_ovr_attr == SERDES_IP_CMN_L2_CFG_CMNFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnfsm_cken_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_aprobe1_charge_up_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_APROBE1_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_aprobe1_pull_dn_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_APROBE1_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_aprobe1_sense_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_APROBE1_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_aprobe2_charge_up_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_APROBE2_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_aprobe2_pull_dn_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_APROBE2_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_aprobe2_sense_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_APROBE2_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_changeref_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_changeref_val_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_en_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_CMN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_ntl_sel_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_CMN_NTL_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_refckm_charge_up_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_REFCKM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_refckm_pull_dn_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_REFCKM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_refckm_sense_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_REFCKM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_refckp_charge_up_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_REFCKP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_refckp_pull_dn_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_REFCKP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_refckp_sense_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_REFCKP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnpcs_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnpcs_ref_sel_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnpcs_ref_sel_tx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnperfmon_compare_val_start_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnperfmon_compare_val_stop_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnperfmon_en_attr == SERDES_IP_CMN_L2_CFG_CMNPERFMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnperfmon_mask_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprefckbufprelut_delta_attr == 15'd32767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprefckbufprelut_init_termcal_rx_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprefckbufprelut_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNRCOMPREFCKBUFPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprefckbufprelut_termcal_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprefcktxdrvprelut_delta_attr == 15'd4672
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprefcktxdrvprelut_init_termcal_rx_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprefcktxdrvprelut_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNRCOMPREFCKTXDRVPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprefcktxdrvprelut_termcal_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprxdfeprelut_delta_attr == 15'd32767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprxdfeprelut_init_termcal_tfr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprxdfeprelut_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNRCOMPRXDFEPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprxdfeprelut_termcal_tfr_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckbuf_cml_ena_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKBUF_CML_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckbuf_hs_cmos_ena_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKBUF_HS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckbuf_hs_ls_b_path_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKBUF_HS_LS_B_PATH_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckbuf_hs_ref_to_cdrdiv_ena_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKBUF_HS_REF_TO_CDRDIV_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckbuf_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKBUF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckbuf_ls_cmos_ena_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKBUF_LS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckbuf_powersave_b_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKBUF_POWERSAVE_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckbuf_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckbuf_termhiz_b_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKBUF_TERMHIZ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckdrv_powersave_en_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKDRV_POWERSAVE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrefcktxdrv_cdrdiv_en_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKTXDRV_CDRDIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrefcktxdrv_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKTXDRV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrefcktxdrv_termcal_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_en_b_attr == SERDES_IP_CMN_L2_CFG_CMNRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_entry3_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s0q2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s0q3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s1q4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s1q5_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s1q6_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s1q7_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s2q0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_entry2_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_entry3_attr == 13'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_entry4_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_entry5_attr == 13'd62
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_entry6_attr == 13'd390
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_entry7_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s0q2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s0q3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s1q1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s1q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s1q5_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s1q7_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s2q0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_term_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_term_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_term_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_term_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_term_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_term_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_term_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_term_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_keepalive_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_keepalive_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_bias_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_bias_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_refckbuf_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_refckbuf_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_refckbuf_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_refckbuf_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_rxref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_rxref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_rxref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_rxref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_synthdutycomp_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_synthdutycomp_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_synthdutycomp_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_synthdutycomp_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_synthlcslowref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_synthlcslowref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_synthlcslowref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_synthlcslowref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_txref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_txref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_txref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_txref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpurst_regreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpurst_regreset_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpurst_regreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrpurst_regreset_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_aetrcmn_regpwrupacc_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_AETRCMN_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_aetrcmn_regpwrupacc_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_AETRCMN_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_adc_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_adc_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_ADC_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_biasicc_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_biasicc_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_ntl_b_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_ntl_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_refckbuf_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_refckbuf_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_reg_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_reg_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_rxref_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_RXREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_rxref_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_RXREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_synthlcslowref_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_SYNTHLCSLOWREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_synthlcslowref_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_SYNTHLCSLOWREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_txref_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_TXREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_txref_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_TXREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_arstcmn_adc_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_ARSTCMN_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_arstcmn_adc_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_ARSTCMN_ADC_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_arstcmn_aprobedac_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_ARSTCMN_APROBEDAC_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_arstcmn_refcktxdrv_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_ARSTCMN_REFCKTXDRV_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_arstcmn_refcktxdrv_hiz_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_ARSTCMN_REFCKTXDRV_HIZ_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_arstcmn_regreset_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_ARSTCMN_REGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_arstcmn_regreset_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_ARSTCMN_REGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_synthdutycomp_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_SYNTHDUTYCOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_synthdutycomp_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_SYNTHDUTYCOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrxref_dpma_en_attr == SERDES_IP_CMN_L2_CFG_CMNRXREF_DPMA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrxref_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNRXREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnrxref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnspare0_attr == 32'd163
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnspare_attr == 9'd384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_rxlane0_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_rxlane1_timer_attr == 12'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_rxlane2_timer_attr == 12'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_rxlane3_timer_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_synthlcfast_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_synthlcmed_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_synthlcslow_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_txlane0_timer_attr == 12'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_txlane1_timer_attr == 12'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_txlane2_timer_attr == 12'd70
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_txlane3_timer_attr == 12'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthdiv_cdrdiv_en_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHDIV_CDRDIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthdiv_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHDIV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthdiv_slowmed_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHDIV_SLOWMED_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthdutyoffsetcal_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHDUTYOFFSETCAL_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthdutyoffsetcal_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHDUTYOFFSETCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthdutysel_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHDUTYSEL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthdutysel_mux_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlccaldac_currentdacdcdmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlccaldac_currentdacdcdmeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlccaldac_currentdacdcdmeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlccaldac_currentdacdcdmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlccaldac_synthdutyoffsetmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlccaldac_tx_disable_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHLCCALDAC_TX_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlccaldacerr_calsynthdutyerr_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHLCCALDACERR_CALSYNTHDUTYERR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlccaldacerr_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHLCCALDACERR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlcslowref_dpma_en_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHLCSLOWREF_DPMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlcslowref_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHLCSLOWREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlcslowref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmntxref_dpma_en_attr == SERDES_IP_CMN_L2_CFG_CMNTXREF_DPMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmntxref_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNTXREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmntxref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_cmnynthdutyselpolarity_attr == SERDES_IP_CMN_L2_CFG_CMNYNTHDUTYSELPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_lbcmn_locovren_attr == SERDES_IP_CMN_L2_CFG_LBCMN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_lbcmn_synthlcslowmedpostdivclk2cdrrefclken_locovr_attr == SERDES_IP_CMN_L2_CFG_LBCMN_SYNTHLCSLOWMEDPOSTDIVCLK2CDRREFCLKEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_rcompmaster_en_locovr_attr == SERDES_IP_CMN_L2_CFG_RCOMPMASTER_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_rcompmaster_locovren_attr == SERDES_IP_CMN_L2_CFG_RCOMPMASTER_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_rcompslave_locovr_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_rcompslave_locovren_attr == SERDES_IP_CMN_L2_CFG_RCOMPSLAVE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_rcompslave_valid_locovr_attr == SERDES_IP_CMN_L2_CFG_RCOMPSLAVE_VALID_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_rcompterm_rx_termcode_base_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_rcompterm_tfr_termcode_base_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_rcompterm_txpd_termcode_base_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_rcompterm_txpu_termcode_base_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmed_locovren_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMED_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmed_txbitclkselect_locovr_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMED_TXBITCLKSELECT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedcaldac_locovren_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMEDCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedcalregopampoffset_locovren_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedcalregopampoffsetfsmout_locovren_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedpcs_locovren_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMEDPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedpcs_postdiv2clk0_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedpcs_postdiv2clk0en_locovr_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMEDPCS_POSTDIV2CLK0EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedpcs_postdivclk0en_locovr_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMEDPCS_POSTDIVCLK0EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedreg_lev_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedreg_locovren_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMEDREG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_bti_div_attr == 7'd54
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_bti_div_rst_attr == SERDES_IP_CMN_L3_CFG_BTI_DIV_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_bti_en_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_bti_static_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmn_pg_disable_attr == SERDES_IP_CMN_L3_CFG_CMN_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmn_scratch_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnadc_req_attr == SERDES_IP_CMN_L3_CFG_CMNADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnapb2strbbridgecfg_acc_ctrl_field_mask_write_en_attr == SERDES_IP_CMN_L3_CFG_CMNAPB2STRBBRIDGECFG_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnapb2strbbridgecfg_force_state_en_attr == SERDES_IP_CMN_L3_CFG_CMNAPB2STRBBRIDGECFG_FORCE_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnapb2strbbridgecfg_force_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnapb2strbbridgecfg_stbl_time_aftr_strb_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnapb2strbbridgecfg_stbl_time_bfr_strb_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnapb2strbbridgecfg_strb_pulse_width_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnapbmaster_timeout_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobe_addr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobe_lastmux_isolate_attr == SERDES_IP_CMN_L3_CFG_CMNAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobeadc_current_direction_attr == SERDES_IP_CMN_L3_CFG_CMNAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobeadc_resistor_enable_attr == SERDES_IP_CMN_L3_CFG_CMNAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobedac_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobedac_en_attr == SERDES_IP_CMN_L3_CFG_CMNAPROBEDAC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobedacctrl_block_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobedacctrl_en_attr == SERDES_IP_CMN_L3_CFG_CMNAPROBEDACCTRL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobedacctrl_mask_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobedacctrl_rotate_left_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobedacctrl_tstbus_clkdiv_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnbias_icc20uadj_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnbias_icc80uadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnbias_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnbias_termcal_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnbscan_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnbshihyst_attr == SERDES_IP_CMN_L3_CFG_CMNBSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_bg_en_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_bg_one_step_cal_en_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_fg_inc_cal_en_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_fg_one_step_cal_en_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_finish_side_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_initval_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_invert_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_restore_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_round_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_runcount_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_signmagen_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetmeas_req_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_SYNTHDUTYOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncaldacbg_abort_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncaldacbg_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncaldacbg_ready_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncaldacfsm_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncaldacfsm_synthdutyoffsetfsm_clear_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncaldacfsm_synthdutyoffsetfsm_init_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncaldacfsm_synthdutyoffsetfsm_req_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncaldacsynthdutyoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALDACSYNTHDUTYOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncaldacsynthdutyoffsetfsmout_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALDACSYNTHDUTYOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalptr_pstate_rcomp_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalptr_pstate_synthdutyoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalptr_quad_rcomp_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalptr_quad_regopampoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalptr_quad_synthdutyoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_biastrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_cap_tune_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_divrate_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_mode_select_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_ref_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMP_REF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_rx_term_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMP_RX_TERM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_tfr_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMP_TFR_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_tx_term_pd_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMP_TX_TERM_PD_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_tx_term_pu_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMP_TX_TERM_PU_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_txterm_nmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_txterm_pmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_clear_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_code_delay_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_init_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rcomp_tfr_init_cal_value_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rcomp_tfr_max_value_attr == 4'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rcomp_tfr_min_value_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rcomp_txpd_valid_code_lut_vf00_attr == 32'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rcomp_txpd_valid_code_lut_vf01_attr == 32'd4246868100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rcomp_txpu_valid_code_lut_vf00_attr == 32'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rcomp_txpu_valid_code_lut_vf01_attr == 32'd4246868100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_req_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rx_comp_inv_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_RX_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rx_init_cal_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rx_initval_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rx_step_sign_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_RX_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rx_termcode_delta_lut_attr == 31'd24084352
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tfr_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tfr_comp_inv_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_TFR_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tfr_initval_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tfr_step_sign_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_TFR_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tfr_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_time_comp_config_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_time_lpfsetup_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_time_mode_setup_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_time_reset_release_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_time_sample_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tx_pd_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tx_pd_init_cal_value_attr == 6'd49
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tx_pd_max_value_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tx_pd_min_value_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tx_pu_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tx_pu_init_cal_value_attr == 6'd49
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tx_pu_max_value_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tx_pu_min_value_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_txpd_comp_inv_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_TXPD_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_txpd_initval_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_txpd_step_sign_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_TXPD_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_txpd_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_txpu_comp_inv_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_TXPU_COMP_INV_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_txpu_initval_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_txpu_step_sign_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_TXPU_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_txpu_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_txterm_pmos_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmaster_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPMASTER_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmaster_rx_locovr_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmaster_tfr_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmaster_txpd_locovr_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmaster_txpu_locovr_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmaster_valid_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPMASTER_VALID_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmeas_dlycount_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffset_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_clear_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_finish_side_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_init_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_invert_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_req_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_runcount_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsmout_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetmeas_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetmeas_req_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_avg_en_attr == SERDES_IP_CMN_L3_CFG_CMNCKM_AVG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_clk_en_attr == SERDES_IP_CMN_L3_CFG_CMNCKM_CLK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_continuous_attr == SERDES_IP_CMN_L3_CFG_CMNCKM_CONTINUOUS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_dig_meas_en_attr == SERDES_IP_CMN_L3_CFG_CMNCKM_DIG_MEAS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_dig_meas_err_clr_attr == SERDES_IP_CMN_L3_CFG_CMNCKM_DIG_MEAS_ERR_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_en_attr == SERDES_IP_CMN_L3_CFG_CMNCKM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_max_thr_attr == 25'd33554431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_meas_ck_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_ref_ck_div_ratio_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_result_clr_attr == SERDES_IP_CMN_L3_CFG_CMNCKM_RESULT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_start_attr == SERDES_IP_CMN_L3_CFG_CMNCKM_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_wdt_interval_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_win_thr_ref_attr == 25'd16777215
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnclk_keepalive_en_b_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnclk_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmndmondac_en_attr == SERDES_IP_CMN_L3_CFG_CMNDMONDAC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnfsm_cken_ovr_attr == SERDES_IP_CMN_L3_CFG_CMNFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnfsm_cken_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_aprobe1_charge_up_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_APROBE1_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_aprobe1_pull_dn_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_APROBE1_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_aprobe1_sense_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_APROBE1_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_aprobe2_charge_up_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_APROBE2_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_aprobe2_pull_dn_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_APROBE2_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_aprobe2_sense_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_APROBE2_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_changeref_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_changeref_val_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_en_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_CMN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_ntl_sel_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_CMN_NTL_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_refckm_charge_up_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_REFCKM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_refckm_pull_dn_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_REFCKM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_refckm_sense_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_REFCKM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_refckp_charge_up_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_REFCKP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_refckp_pull_dn_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_REFCKP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_refckp_sense_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_REFCKP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnpcs_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnpcs_ref_sel_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnpcs_ref_sel_tx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnperfmon_compare_val_start_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnperfmon_compare_val_stop_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnperfmon_en_attr == SERDES_IP_CMN_L3_CFG_CMNPERFMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnperfmon_mask_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprefckbufprelut_delta_attr == 15'd32767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprefckbufprelut_init_termcal_rx_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprefckbufprelut_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNRCOMPREFCKBUFPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprefckbufprelut_termcal_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprefcktxdrvprelut_delta_attr == 15'd4672
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprefcktxdrvprelut_init_termcal_rx_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprefcktxdrvprelut_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNRCOMPREFCKTXDRVPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprefcktxdrvprelut_termcal_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprxdfeprelut_delta_attr == 15'd32767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprxdfeprelut_init_termcal_tfr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprxdfeprelut_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNRCOMPRXDFEPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprxdfeprelut_termcal_tfr_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckbuf_cml_ena_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKBUF_CML_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckbuf_hs_cmos_ena_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKBUF_HS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckbuf_hs_ls_b_path_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKBUF_HS_LS_B_PATH_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckbuf_hs_ref_to_cdrdiv_ena_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKBUF_HS_REF_TO_CDRDIV_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckbuf_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKBUF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckbuf_ls_cmos_ena_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKBUF_LS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckbuf_powersave_b_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKBUF_POWERSAVE_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckbuf_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckbuf_termhiz_b_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKBUF_TERMHIZ_B_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckdrv_powersave_en_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKDRV_POWERSAVE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrefcktxdrv_cdrdiv_en_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKTXDRV_CDRDIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrefcktxdrv_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKTXDRV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrefcktxdrv_termcal_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_en_b_attr == SERDES_IP_CMN_L3_CFG_CMNRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_entry3_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s0q2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s0q3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s1q4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s1q5_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s1q6_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s1q7_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s2q0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_entry2_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_entry3_attr == 13'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_entry4_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_entry5_attr == 13'd62
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_entry6_attr == 13'd390
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_entry7_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s0q2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s0q3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s1q1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s1q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s1q5_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s1q7_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s2q0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_term_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_term_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_term_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_term_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_term_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_term_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_term_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_term_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_keepalive_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_keepalive_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_bias_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_bias_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_refckbuf_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_refckbuf_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_refckbuf_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_refckbuf_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_rxref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_rxref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_rxref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_rxref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_synthdutycomp_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_synthdutycomp_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_synthdutycomp_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_synthdutycomp_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_synthlcslowref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_synthlcslowref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_synthlcslowref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_synthlcslowref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_txref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_txref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_txref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_txref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpurst_regreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpurst_regreset_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpurst_regreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrpurst_regreset_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_aetrcmn_regpwrupacc_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_AETRCMN_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_aetrcmn_regpwrupacc_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_AETRCMN_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_adc_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_adc_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_ADC_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_biasicc_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_biasicc_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_ntl_b_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_ntl_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_refckbuf_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_refckbuf_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_reg_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_reg_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_rxref_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_RXREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_rxref_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_RXREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_synthlcslowref_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_SYNTHLCSLOWREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_synthlcslowref_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_SYNTHLCSLOWREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_txref_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_TXREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_txref_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_TXREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_arstcmn_adc_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_ARSTCMN_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_arstcmn_adc_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_ARSTCMN_ADC_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_arstcmn_aprobedac_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_ARSTCMN_APROBEDAC_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_arstcmn_refcktxdrv_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_ARSTCMN_REFCKTXDRV_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_arstcmn_refcktxdrv_hiz_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_ARSTCMN_REFCKTXDRV_HIZ_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_arstcmn_regreset_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_ARSTCMN_REGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_arstcmn_regreset_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_ARSTCMN_REGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_synthdutycomp_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_SYNTHDUTYCOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_synthdutycomp_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_SYNTHDUTYCOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrxref_dpma_en_attr == SERDES_IP_CMN_L3_CFG_CMNRXREF_DPMA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrxref_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNRXREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnrxref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnspare0_attr == 32'd163
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnspare_attr == 9'd384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_rxlane0_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_rxlane1_timer_attr == 12'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_rxlane2_timer_attr == 12'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_rxlane3_timer_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_synthlcfast_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_synthlcmed_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_synthlcslow_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_txlane0_timer_attr == 12'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_txlane1_timer_attr == 12'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_txlane2_timer_attr == 12'd70
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_txlane3_timer_attr == 12'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthdiv_cdrdiv_en_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHDIV_CDRDIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthdiv_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHDIV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthdiv_slowmed_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHDIV_SLOWMED_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthdutyoffsetcal_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHDUTYOFFSETCAL_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthdutyoffsetcal_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHDUTYOFFSETCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthdutysel_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHDUTYSEL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthdutysel_mux_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlccaldac_currentdacdcdmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlccaldac_currentdacdcdmeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlccaldac_currentdacdcdmeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlccaldac_currentdacdcdmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlccaldac_synthdutyoffsetmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlccaldac_tx_disable_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHLCCALDAC_TX_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlccaldacerr_calsynthdutyerr_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHLCCALDACERR_CALSYNTHDUTYERR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlccaldacerr_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHLCCALDACERR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlcslowref_dpma_en_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHLCSLOWREF_DPMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlcslowref_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHLCSLOWREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlcslowref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmntxref_dpma_en_attr == SERDES_IP_CMN_L3_CFG_CMNTXREF_DPMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmntxref_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNTXREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmntxref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_cmnynthdutyselpolarity_attr == SERDES_IP_CMN_L3_CFG_CMNYNTHDUTYSELPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_lbcmn_locovren_attr == SERDES_IP_CMN_L3_CFG_LBCMN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_lbcmn_synthlcslowmedpostdivclk2cdrrefclken_locovr_attr == SERDES_IP_CMN_L3_CFG_LBCMN_SYNTHLCSLOWMEDPOSTDIVCLK2CDRREFCLKEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_rcompmaster_en_locovr_attr == SERDES_IP_CMN_L3_CFG_RCOMPMASTER_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_rcompmaster_locovren_attr == SERDES_IP_CMN_L3_CFG_RCOMPMASTER_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_rcompslave_locovr_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_rcompslave_locovren_attr == SERDES_IP_CMN_L3_CFG_RCOMPSLAVE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_rcompslave_valid_locovr_attr == SERDES_IP_CMN_L3_CFG_RCOMPSLAVE_VALID_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_rcompterm_rx_termcode_base_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_rcompterm_tfr_termcode_base_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_rcompterm_txpd_termcode_base_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_rcompterm_txpu_termcode_base_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmed_locovren_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMED_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmed_txbitclkselect_locovr_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMED_TXBITCLKSELECT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedcaldac_locovren_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMEDCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedcalregopampoffset_locovren_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedcalregopampoffsetfsmout_locovren_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedpcs_locovren_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMEDPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedpcs_postdiv2clk0_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedpcs_postdiv2clk0en_locovr_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMEDPCS_POSTDIV2CLK0EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedpcs_postdivclk0en_locovr_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMEDPCS_POSTDIVCLK0EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedreg_lev_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedreg_locovren_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMEDREG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_clock_ratio_cnt_max_timer_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_clock_ratio_cnt_min_timer_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_enable_flex_override_en_attr == SERDES_IP_FLEX_FW_LOADER_L0_CFG_CFG_ENABLE_FLEX_OVERRIDE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_enable_flex_override_value_attr == SERDES_IP_FLEX_FW_LOADER_L0_CFG_CFG_ENABLE_FLEX_OVERRIDE_VALUE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_flex_gpi_attr == 17'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_gp_lvl_attr == SERDES_IP_FLEX_FW_LOADER_L0_CFG_CFG_GP_LVL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_gp_pls_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_lms_cont_dis_attr == SERDES_IP_FLEX_FW_LOADER_L0_CFG_CFG_LMS_CONT_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_local_tp_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_periodical_rst_dis_attr == SERDES_IP_FLEX_FW_LOADER_L0_CFG_CFG_PERIODICAL_RST_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_spa_sat_dir_attr == SERDES_IP_FLEX_FW_LOADER_L0_CFG_CFG_SPA_SAT_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_vg_inv_cb_attr == SERDES_IP_FLEX_FW_LOADER_L0_CFG_CFG_VG_INV_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l0_cfg_data_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l0_cfg_fw_loader_en_attr == SERDES_IP_FLEX_FW_LOADER_L0_CFG_FW_LOADER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l0_cfg_offset_addr_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l0_cfg_single_mode_en_attr == SERDES_IP_FLEX_FW_LOADER_L0_CFG_SINGLE_MODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_clock_ratio_cnt_max_timer_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_clock_ratio_cnt_min_timer_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_enable_flex_override_en_attr == SERDES_IP_FLEX_FW_LOADER_L1_CFG_CFG_ENABLE_FLEX_OVERRIDE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_enable_flex_override_value_attr == SERDES_IP_FLEX_FW_LOADER_L1_CFG_CFG_ENABLE_FLEX_OVERRIDE_VALUE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_flex_gpi_attr == 17'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_gp_lvl_attr == SERDES_IP_FLEX_FW_LOADER_L1_CFG_CFG_GP_LVL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_gp_pls_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_lms_cont_dis_attr == SERDES_IP_FLEX_FW_LOADER_L1_CFG_CFG_LMS_CONT_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_local_tp_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_periodical_rst_dis_attr == SERDES_IP_FLEX_FW_LOADER_L1_CFG_CFG_PERIODICAL_RST_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_spa_sat_dir_attr == SERDES_IP_FLEX_FW_LOADER_L1_CFG_CFG_SPA_SAT_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_vg_inv_cb_attr == SERDES_IP_FLEX_FW_LOADER_L1_CFG_CFG_VG_INV_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l1_cfg_data_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l1_cfg_fw_loader_en_attr == SERDES_IP_FLEX_FW_LOADER_L1_CFG_FW_LOADER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l1_cfg_offset_addr_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l1_cfg_single_mode_en_attr == SERDES_IP_FLEX_FW_LOADER_L1_CFG_SINGLE_MODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_clock_ratio_cnt_max_timer_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_clock_ratio_cnt_min_timer_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_enable_flex_override_en_attr == SERDES_IP_FLEX_FW_LOADER_L2_CFG_CFG_ENABLE_FLEX_OVERRIDE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_enable_flex_override_value_attr == SERDES_IP_FLEX_FW_LOADER_L2_CFG_CFG_ENABLE_FLEX_OVERRIDE_VALUE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_flex_gpi_attr == 17'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_gp_lvl_attr == SERDES_IP_FLEX_FW_LOADER_L2_CFG_CFG_GP_LVL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_gp_pls_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_lms_cont_dis_attr == SERDES_IP_FLEX_FW_LOADER_L2_CFG_CFG_LMS_CONT_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_local_tp_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_periodical_rst_dis_attr == SERDES_IP_FLEX_FW_LOADER_L2_CFG_CFG_PERIODICAL_RST_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_spa_sat_dir_attr == SERDES_IP_FLEX_FW_LOADER_L2_CFG_CFG_SPA_SAT_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_vg_inv_cb_attr == SERDES_IP_FLEX_FW_LOADER_L2_CFG_CFG_VG_INV_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l2_cfg_data_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l2_cfg_fw_loader_en_attr == SERDES_IP_FLEX_FW_LOADER_L2_CFG_FW_LOADER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l2_cfg_offset_addr_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l2_cfg_single_mode_en_attr == SERDES_IP_FLEX_FW_LOADER_L2_CFG_SINGLE_MODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_clock_ratio_cnt_max_timer_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_clock_ratio_cnt_min_timer_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_enable_flex_override_en_attr == SERDES_IP_FLEX_FW_LOADER_L3_CFG_CFG_ENABLE_FLEX_OVERRIDE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_enable_flex_override_value_attr == SERDES_IP_FLEX_FW_LOADER_L3_CFG_CFG_ENABLE_FLEX_OVERRIDE_VALUE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_flex_gpi_attr == 17'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_gp_lvl_attr == SERDES_IP_FLEX_FW_LOADER_L3_CFG_CFG_GP_LVL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_gp_pls_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_lms_cont_dis_attr == SERDES_IP_FLEX_FW_LOADER_L3_CFG_CFG_LMS_CONT_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_local_tp_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_periodical_rst_dis_attr == SERDES_IP_FLEX_FW_LOADER_L3_CFG_CFG_PERIODICAL_RST_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_spa_sat_dir_attr == SERDES_IP_FLEX_FW_LOADER_L3_CFG_CFG_SPA_SAT_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_vg_inv_cb_attr == SERDES_IP_FLEX_FW_LOADER_L3_CFG_CFG_VG_INV_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l3_cfg_data_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l3_cfg_fw_loader_en_attr == SERDES_IP_FLEX_FW_LOADER_L3_CFG_FW_LOADER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l3_cfg_offset_addr_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_flex_fw_loader_l3_cfg_single_mode_en_attr == SERDES_IP_FLEX_FW_LOADER_L3_CFG_SINGLE_MODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_cpi_port_mode_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_dfx_secure_visa_nt_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_dfx_secure_visa_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_DFX_SECURE_VISA_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_p_vdd_pwrgood_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_P_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_p_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_P_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pa_vdd_ehv_pwrgood_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pa_vdd_ehv_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pa_vdd_pwrgood_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PA_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pa_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PA_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_andme_en_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_ANDME_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_andme_en_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_ANDME_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bist_modesel_l0_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bist_modesel_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BIST_MODESEL_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_capturedr_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_CAPTUREDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_clamp_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_CLAMP_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_exit1dr_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_EXIT1DR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_exit2dr_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_EXIT2DR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_extest_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_EXTEST_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_extestpulse_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_EXTESTPULSE_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_extesttrain_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_EXTESTTRAIN_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_highz_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_HIGHZ_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_mode_en_nt_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_MODE_EN_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_preload_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_PRELOAD_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_runtestidle_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_RUNTESTIDLE_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_shiftdr_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_SHIFTDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_txinvert_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_TXINVERT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_updatedr_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_UPDATEDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_cmn_force_pup_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_CMN_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_cmn_force_pup_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_CMN_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_disconnect_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_DISCONNECT_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_disconnect_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_DISCONNECT_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_isolate_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_ISOLATE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_isolate_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_ISOLATE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_jtagid_nt_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_JTAGID_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_jtagslvid_nt_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_JTAGSLVID_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_lb_cdrclk2txen_l0_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_LB_CDRCLK2TXEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_lb_cdrclk2txen_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_LB_CDRCLK2TXEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_lb_parrx2txtimeden_l0_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_LB_PARRX2TXTIMEDEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_lb_parrx2txtimeden_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_LB_PARRX2TXTIMEDEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_lb_tx2rxbuftimeden_l0_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_LB_TX2RXBUFTIMEDEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_lb_tx2rxbuftimeden_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_LB_TX2RXBUFTIMEDEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_lfps_en_l0_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_LFPS_EN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_lfps_en_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_LFPS_EN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_mode_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_MODE_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_mode_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_MODE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_pcie_l1d1_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_PCIE_L1D1_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_pcie_l1d1_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_PCIE_L1D1_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_pcie_l1d2_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_PCIE_L1D2_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_pcie_l1d2_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_PCIE_L1D2_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rcomp_slave_en_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RCOMP_SLAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rcomp_slave_en_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RCOMP_SLAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rcomp_slave_nt_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rcomp_slave_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RCOMP_SLAVE_NT_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rcomp_slave_valid_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RCOMP_SLAVE_VALID_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rcomp_slave_valid_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RCOMP_SLAVE_VALID_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_ref_sel_rx_nt_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_ref_sel_rx_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_REF_SEL_RX_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_ref_sel_tx_nt_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_ref_sel_tx_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_REF_SEL_TX_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_ref_term_hiz_en_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_REF_TERM_HIZ_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_ref_term_hiz_en_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_REF_TERM_HIZ_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxbist_en_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXBIST_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxbist_en_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXBIST_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxbitslip_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXBITSLIP_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxbitslip_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXBITSLIP_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeiosdetectstat_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEIOSDETECTSTAT_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeiosdetectstat_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEIOSDETECTSTAT_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeq_clr_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEQ_CLR_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeq_clr_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEQ_CLR_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeq_precal_code_sel_l0_nt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeq_precal_code_sel_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEQ_PRECAL_CODE_SEL_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeq_start_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEQ_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeq_start_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEQ_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeq_static_en_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEQ_STATIC_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeq_static_en_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEQ_STATIC_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeyediag_start_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEYEDIAG_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeyediag_start_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEYEDIAG_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_direction_l0_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXMARGIN_DIRECTION_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_direction_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXMARGIN_DIRECTION_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_mode_l0_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXMARGIN_MODE_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_mode_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXMARGIN_MODE_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_offset_change_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXMARGIN_OFFSET_CHANGE_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_offset_change_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXMARGIN_OFFSET_CHANGE_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_offset_l0_nt_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_offset_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXMARGIN_OFFSET_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_start_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXMARGIN_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_start_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXMARGIN_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxpam_gray_en_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXPAM_GRAY_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxpam_gray_en_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXPAM_GRAY_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxpam_precode_en_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXPAM_PRECODE_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxpam_precode_en_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXPAM_PRECODE_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxrate_l0_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxrate_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxterm_hiz_en_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXTERM_HIZ_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxterm_hiz_en_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXTERM_HIZ_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxwidth_l0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxwidth_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXWIDTH_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_spare_nt_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_spare_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SPARE_NT_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcfast_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcfast_divrate_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SYNTHLCFAST_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcfast_force_pup_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SYNTHLCFAST_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcfast_force_pup_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SYNTHLCFAST_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcmed_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcmed_divrate_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SYNTHLCMED_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcmed_force_pup_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SYNTHLCMED_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcmed_force_pup_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SYNTHLCMED_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcslow_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcslow_divrate_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SYNTHLCSLOW_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcslow_force_pup_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SYNTHLCSLOW_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcslow_force_pup_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SYNTHLCSLOW_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txbeacon_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXBEACON_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txbeacon_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXBEACON_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txbist_en_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXBIST_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txbist_en_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXBIST_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txclkdivrate_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txclkdivrate_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXCLKDIVRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdetectrx_req_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXDETECTRX_REQ_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdetectrx_req_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXDETECTRX_REQ_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_levn_l0_attr == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_levn_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXDRV_LEVN_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_levnm1_l0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_levnm1_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXDRV_LEVNM1_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_levnm2_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_levnm2_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXDRV_LEVNM2_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_levnp1_l0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_levnp1_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXDRV_LEVNP1_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_slew_l0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_slew_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXDRV_SLEW_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_spare_l0_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_spare_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXDRV_SPARE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txenable_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXENABLE_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txenable_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXENABLE_L0_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txpam_gray_en_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXPAM_GRAY_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txpam_gray_en_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXPAM_GRAY_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txpam_precode_en_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXPAM_PRECODE_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txpam_precode_en_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXPAM_PRECODE_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txrate_l0_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txrate_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txwidth_l0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txwidth_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXWIDTH_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_visa_unit_id_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_ictl_visa_unit_id_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_VISA_UNIT_ID_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_idat_dfx_obs_dig_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_idat_visa_serial_cfg_in_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_irst_apb_mem_b_attr == SERDES_IP_IF_L0_CFG_IRST_APB_MEM_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_irst_apb_mem_b_reg_en_attr == SERDES_IP_IF_L0_CFG_IRST_APB_MEM_B_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_irst_pcs_rx_l0_b_a_attr == SERDES_IP_IF_L0_CFG_IRST_PCS_RX_L0_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_irst_pcs_rx_l0_b_a_reg_en_attr == SERDES_IP_IF_L0_CFG_IRST_PCS_RX_L0_B_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_irst_pcs_tstbus_b_a_attr == SERDES_IP_IF_L0_CFG_IRST_PCS_TSTBUS_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_irst_pcs_tx_l0_b_a_attr == SERDES_IP_IF_L0_CFG_IRST_PCS_TX_L0_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_irst_pcs_tx_l0_b_a_reg_en_attr == SERDES_IP_IF_L0_CFG_IRST_PCS_TX_L0_B_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l0_cfg_irst_visa_reset_b_a_attr == SERDES_IP_IF_L0_CFG_IRST_VISA_RESET_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_cpi_port_mode_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_dfx_secure_visa_nt_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_dfx_secure_visa_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_DFX_SECURE_VISA_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_p_vdd_pwrgood_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_P_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_p_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_P_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pa_vdd_ehv_pwrgood_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pa_vdd_ehv_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pa_vdd_pwrgood_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PA_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pa_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PA_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_andme_en_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_ANDME_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_andme_en_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_ANDME_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bist_modesel_l0_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bist_modesel_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BIST_MODESEL_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_capturedr_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_CAPTUREDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_clamp_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_CLAMP_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_exit1dr_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_EXIT1DR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_exit2dr_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_EXIT2DR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_extest_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_EXTEST_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_extestpulse_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_EXTESTPULSE_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_extesttrain_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_EXTESTTRAIN_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_highz_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_HIGHZ_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_mode_en_nt_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_MODE_EN_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_preload_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_PRELOAD_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_runtestidle_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_RUNTESTIDLE_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_shiftdr_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_SHIFTDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_txinvert_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_TXINVERT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_updatedr_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_UPDATEDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_cmn_force_pup_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_CMN_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_cmn_force_pup_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_CMN_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_disconnect_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_DISCONNECT_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_disconnect_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_DISCONNECT_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_isolate_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_ISOLATE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_isolate_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_ISOLATE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_jtagid_nt_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_JTAGID_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_jtagslvid_nt_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_JTAGSLVID_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_lb_cdrclk2txen_l0_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_LB_CDRCLK2TXEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_lb_cdrclk2txen_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_LB_CDRCLK2TXEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_lb_parrx2txtimeden_l0_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_LB_PARRX2TXTIMEDEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_lb_parrx2txtimeden_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_LB_PARRX2TXTIMEDEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_lb_tx2rxbuftimeden_l0_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_LB_TX2RXBUFTIMEDEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_lb_tx2rxbuftimeden_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_LB_TX2RXBUFTIMEDEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_lfps_en_l0_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_LFPS_EN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_lfps_en_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_LFPS_EN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_mode_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_MODE_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_mode_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_MODE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_pcie_l1d1_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_PCIE_L1D1_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_pcie_l1d1_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_PCIE_L1D1_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_pcie_l1d2_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_PCIE_L1D2_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_pcie_l1d2_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_PCIE_L1D2_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rcomp_slave_en_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RCOMP_SLAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rcomp_slave_en_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RCOMP_SLAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rcomp_slave_nt_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rcomp_slave_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RCOMP_SLAVE_NT_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rcomp_slave_valid_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RCOMP_SLAVE_VALID_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rcomp_slave_valid_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RCOMP_SLAVE_VALID_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_ref_sel_rx_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_ref_sel_rx_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_REF_SEL_RX_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_ref_sel_tx_nt_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_ref_sel_tx_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_REF_SEL_TX_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_ref_term_hiz_en_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_REF_TERM_HIZ_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_ref_term_hiz_en_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_REF_TERM_HIZ_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxbist_en_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXBIST_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxbist_en_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXBIST_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxbitslip_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXBITSLIP_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxbitslip_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXBITSLIP_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeiosdetectstat_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEIOSDETECTSTAT_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeiosdetectstat_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEIOSDETECTSTAT_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeq_clr_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEQ_CLR_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeq_clr_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEQ_CLR_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeq_precal_code_sel_l0_nt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeq_precal_code_sel_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEQ_PRECAL_CODE_SEL_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeq_start_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEQ_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeq_start_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEQ_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeq_static_en_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEQ_STATIC_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeq_static_en_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEQ_STATIC_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeyediag_start_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEYEDIAG_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeyediag_start_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEYEDIAG_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_direction_l0_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXMARGIN_DIRECTION_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_direction_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXMARGIN_DIRECTION_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_mode_l0_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXMARGIN_MODE_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_mode_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXMARGIN_MODE_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_offset_change_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXMARGIN_OFFSET_CHANGE_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_offset_change_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXMARGIN_OFFSET_CHANGE_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_offset_l0_nt_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_offset_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXMARGIN_OFFSET_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_start_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXMARGIN_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_start_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXMARGIN_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxpam_gray_en_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXPAM_GRAY_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxpam_gray_en_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXPAM_GRAY_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxpam_precode_en_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXPAM_PRECODE_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxpam_precode_en_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXPAM_PRECODE_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxrate_l0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxrate_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxterm_hiz_en_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXTERM_HIZ_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxterm_hiz_en_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXTERM_HIZ_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxwidth_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxwidth_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXWIDTH_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_spare_nt_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_spare_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SPARE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcfast_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcfast_divrate_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SYNTHLCFAST_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcfast_force_pup_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SYNTHLCFAST_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcfast_force_pup_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SYNTHLCFAST_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcmed_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcmed_divrate_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SYNTHLCMED_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcmed_force_pup_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SYNTHLCMED_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcmed_force_pup_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SYNTHLCMED_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcslow_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcslow_divrate_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SYNTHLCSLOW_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcslow_force_pup_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SYNTHLCSLOW_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcslow_force_pup_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SYNTHLCSLOW_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txbeacon_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXBEACON_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txbeacon_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXBEACON_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txbist_en_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXBIST_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txbist_en_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXBIST_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txclkdivrate_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txclkdivrate_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXCLKDIVRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdetectrx_req_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXDETECTRX_REQ_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdetectrx_req_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXDETECTRX_REQ_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_levn_l0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_levn_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXDRV_LEVN_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_levnm1_l0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_levnm1_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXDRV_LEVNM1_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_levnm2_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_levnm2_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXDRV_LEVNM2_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_levnp1_l0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_levnp1_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXDRV_LEVNP1_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_slew_l0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_slew_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXDRV_SLEW_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_spare_l0_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_spare_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXDRV_SPARE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txenable_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXENABLE_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txenable_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXENABLE_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txpam_gray_en_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXPAM_GRAY_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txpam_gray_en_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXPAM_GRAY_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txpam_precode_en_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXPAM_PRECODE_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txpam_precode_en_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXPAM_PRECODE_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txrate_l0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txrate_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txwidth_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txwidth_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXWIDTH_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_visa_unit_id_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_ictl_visa_unit_id_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_VISA_UNIT_ID_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_idat_dfx_obs_dig_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_idat_visa_serial_cfg_in_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_irst_apb_mem_b_attr == SERDES_IP_IF_L1_CFG_IRST_APB_MEM_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_irst_apb_mem_b_reg_en_attr == SERDES_IP_IF_L1_CFG_IRST_APB_MEM_B_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_irst_pcs_rx_l0_b_a_attr == SERDES_IP_IF_L1_CFG_IRST_PCS_RX_L0_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_irst_pcs_rx_l0_b_a_reg_en_attr == SERDES_IP_IF_L1_CFG_IRST_PCS_RX_L0_B_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_irst_pcs_tstbus_b_a_attr == SERDES_IP_IF_L1_CFG_IRST_PCS_TSTBUS_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_irst_pcs_tx_l0_b_a_attr == SERDES_IP_IF_L1_CFG_IRST_PCS_TX_L0_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_irst_pcs_tx_l0_b_a_reg_en_attr == SERDES_IP_IF_L1_CFG_IRST_PCS_TX_L0_B_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l1_cfg_irst_visa_reset_b_a_attr == SERDES_IP_IF_L1_CFG_IRST_VISA_RESET_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_cpi_port_mode_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_dfx_secure_visa_nt_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_dfx_secure_visa_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_DFX_SECURE_VISA_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_p_vdd_pwrgood_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_P_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_p_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_P_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pa_vdd_ehv_pwrgood_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pa_vdd_ehv_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pa_vdd_pwrgood_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PA_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pa_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PA_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_andme_en_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_ANDME_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_andme_en_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_ANDME_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bist_modesel_l0_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bist_modesel_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BIST_MODESEL_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_capturedr_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_CAPTUREDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_clamp_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_CLAMP_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_exit1dr_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_EXIT1DR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_exit2dr_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_EXIT2DR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_extest_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_EXTEST_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_extestpulse_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_EXTESTPULSE_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_extesttrain_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_EXTESTTRAIN_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_highz_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_HIGHZ_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_mode_en_nt_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_MODE_EN_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_preload_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_PRELOAD_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_runtestidle_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_RUNTESTIDLE_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_shiftdr_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_SHIFTDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_txinvert_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_TXINVERT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_updatedr_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_UPDATEDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_cmn_force_pup_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_CMN_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_cmn_force_pup_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_CMN_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_disconnect_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_DISCONNECT_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_disconnect_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_DISCONNECT_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_isolate_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_ISOLATE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_isolate_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_ISOLATE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_jtagid_nt_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_JTAGID_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_jtagslvid_nt_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_JTAGSLVID_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_lb_cdrclk2txen_l0_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_LB_CDRCLK2TXEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_lb_cdrclk2txen_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_LB_CDRCLK2TXEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_lb_parrx2txtimeden_l0_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_LB_PARRX2TXTIMEDEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_lb_parrx2txtimeden_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_LB_PARRX2TXTIMEDEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_lb_tx2rxbuftimeden_l0_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_LB_TX2RXBUFTIMEDEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_lb_tx2rxbuftimeden_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_LB_TX2RXBUFTIMEDEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_lfps_en_l0_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_LFPS_EN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_lfps_en_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_LFPS_EN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_mode_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_MODE_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_mode_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_MODE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_pcie_l1d1_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_PCIE_L1D1_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_pcie_l1d1_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_PCIE_L1D1_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_pcie_l1d2_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_PCIE_L1D2_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_pcie_l1d2_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_PCIE_L1D2_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rcomp_slave_en_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RCOMP_SLAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rcomp_slave_en_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RCOMP_SLAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rcomp_slave_nt_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rcomp_slave_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RCOMP_SLAVE_NT_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rcomp_slave_valid_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RCOMP_SLAVE_VALID_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rcomp_slave_valid_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RCOMP_SLAVE_VALID_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_ref_sel_rx_nt_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_ref_sel_rx_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_REF_SEL_RX_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_ref_sel_tx_nt_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_ref_sel_tx_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_REF_SEL_TX_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_ref_term_hiz_en_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_REF_TERM_HIZ_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_ref_term_hiz_en_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_REF_TERM_HIZ_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxbist_en_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXBIST_EN_L0_A_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxbist_en_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXBIST_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxbitslip_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXBITSLIP_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxbitslip_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXBITSLIP_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeiosdetectstat_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEIOSDETECTSTAT_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeiosdetectstat_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEIOSDETECTSTAT_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeq_clr_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEQ_CLR_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeq_clr_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEQ_CLR_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeq_precal_code_sel_l0_nt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeq_precal_code_sel_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEQ_PRECAL_CODE_SEL_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeq_start_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEQ_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeq_start_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEQ_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeq_static_en_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEQ_STATIC_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeq_static_en_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEQ_STATIC_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeyediag_start_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEYEDIAG_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeyediag_start_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEYEDIAG_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_direction_l0_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXMARGIN_DIRECTION_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_direction_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXMARGIN_DIRECTION_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_mode_l0_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXMARGIN_MODE_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_mode_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXMARGIN_MODE_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_offset_change_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXMARGIN_OFFSET_CHANGE_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_offset_change_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXMARGIN_OFFSET_CHANGE_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_offset_l0_nt_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_offset_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXMARGIN_OFFSET_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_start_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXMARGIN_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_start_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXMARGIN_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxpam_gray_en_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXPAM_GRAY_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxpam_gray_en_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXPAM_GRAY_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxpam_precode_en_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXPAM_PRECODE_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxpam_precode_en_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXPAM_PRECODE_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxrate_l0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxrate_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxterm_hiz_en_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXTERM_HIZ_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxterm_hiz_en_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXTERM_HIZ_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxwidth_l0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxwidth_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXWIDTH_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_spare_nt_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_spare_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SPARE_NT_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcfast_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcfast_divrate_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SYNTHLCFAST_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcfast_force_pup_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SYNTHLCFAST_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcfast_force_pup_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SYNTHLCFAST_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcmed_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcmed_divrate_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SYNTHLCMED_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcmed_force_pup_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SYNTHLCMED_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcmed_force_pup_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SYNTHLCMED_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcslow_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcslow_divrate_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SYNTHLCSLOW_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcslow_force_pup_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SYNTHLCSLOW_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcslow_force_pup_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SYNTHLCSLOW_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txbeacon_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXBEACON_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txbeacon_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXBEACON_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txbist_en_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXBIST_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txbist_en_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXBIST_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txclkdivrate_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txclkdivrate_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXCLKDIVRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdetectrx_req_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXDETECTRX_REQ_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdetectrx_req_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXDETECTRX_REQ_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_levn_l0_attr == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_levn_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXDRV_LEVN_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_levnm1_l0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_levnm1_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXDRV_LEVNM1_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_levnm2_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_levnm2_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXDRV_LEVNM2_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_levnp1_l0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_levnp1_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXDRV_LEVNP1_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_slew_l0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_slew_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXDRV_SLEW_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_spare_l0_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_spare_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXDRV_SPARE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txenable_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXENABLE_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txenable_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXENABLE_L0_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txpam_gray_en_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXPAM_GRAY_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txpam_gray_en_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXPAM_GRAY_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txpam_precode_en_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXPAM_PRECODE_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txpam_precode_en_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXPAM_PRECODE_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txrate_l0_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txrate_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txwidth_l0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txwidth_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXWIDTH_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_visa_unit_id_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_ictl_visa_unit_id_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_VISA_UNIT_ID_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_idat_dfx_obs_dig_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_idat_visa_serial_cfg_in_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_irst_apb_mem_b_attr == SERDES_IP_IF_L2_CFG_IRST_APB_MEM_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_irst_apb_mem_b_reg_en_attr == SERDES_IP_IF_L2_CFG_IRST_APB_MEM_B_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_irst_pcs_rx_l0_b_a_attr == SERDES_IP_IF_L2_CFG_IRST_PCS_RX_L0_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_irst_pcs_rx_l0_b_a_reg_en_attr == SERDES_IP_IF_L2_CFG_IRST_PCS_RX_L0_B_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_irst_pcs_tstbus_b_a_attr == SERDES_IP_IF_L2_CFG_IRST_PCS_TSTBUS_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_irst_pcs_tx_l0_b_a_attr == SERDES_IP_IF_L2_CFG_IRST_PCS_TX_L0_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_irst_pcs_tx_l0_b_a_reg_en_attr == SERDES_IP_IF_L2_CFG_IRST_PCS_TX_L0_B_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l2_cfg_irst_visa_reset_b_a_attr == SERDES_IP_IF_L2_CFG_IRST_VISA_RESET_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_cpi_port_mode_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_dfx_secure_visa_nt_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_dfx_secure_visa_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_DFX_SECURE_VISA_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_p_vdd_pwrgood_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_P_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_p_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_P_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pa_vdd_ehv_pwrgood_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pa_vdd_ehv_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pa_vdd_pwrgood_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PA_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pa_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PA_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_andme_en_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_ANDME_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_andme_en_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_ANDME_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bist_modesel_l0_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bist_modesel_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BIST_MODESEL_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_capturedr_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_CAPTUREDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_clamp_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_CLAMP_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_exit1dr_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_EXIT1DR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_exit2dr_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_EXIT2DR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_extest_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_EXTEST_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_extestpulse_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_EXTESTPULSE_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_extesttrain_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_EXTESTTRAIN_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_highz_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_HIGHZ_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_mode_en_nt_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_MODE_EN_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_preload_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_PRELOAD_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_runtestidle_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_RUNTESTIDLE_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_shiftdr_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_SHIFTDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_txinvert_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_TXINVERT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_updatedr_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_UPDATEDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_cmn_force_pup_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_CMN_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_cmn_force_pup_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_CMN_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_disconnect_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_DISCONNECT_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_disconnect_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_DISCONNECT_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_isolate_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_ISOLATE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_isolate_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_ISOLATE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_jtagid_nt_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_JTAGID_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_jtagslvid_nt_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_JTAGSLVID_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_lb_cdrclk2txen_l0_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_LB_CDRCLK2TXEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_lb_cdrclk2txen_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_LB_CDRCLK2TXEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_lb_parrx2txtimeden_l0_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_LB_PARRX2TXTIMEDEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_lb_parrx2txtimeden_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_LB_PARRX2TXTIMEDEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_lb_tx2rxbuftimeden_l0_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_LB_TX2RXBUFTIMEDEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_lb_tx2rxbuftimeden_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_LB_TX2RXBUFTIMEDEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_lfps_en_l0_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_LFPS_EN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_lfps_en_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_LFPS_EN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_mode_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_MODE_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_mode_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_MODE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_pcie_l1d1_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_PCIE_L1D1_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_pcie_l1d1_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_PCIE_L1D1_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_pcie_l1d2_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_PCIE_L1D2_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_pcie_l1d2_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_PCIE_L1D2_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rcomp_slave_en_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RCOMP_SLAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rcomp_slave_en_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RCOMP_SLAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rcomp_slave_nt_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rcomp_slave_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RCOMP_SLAVE_NT_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rcomp_slave_valid_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RCOMP_SLAVE_VALID_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rcomp_slave_valid_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RCOMP_SLAVE_VALID_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_ref_sel_rx_nt_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_ref_sel_rx_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_REF_SEL_RX_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_ref_sel_tx_nt_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_ref_sel_tx_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_REF_SEL_TX_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_ref_term_hiz_en_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_REF_TERM_HIZ_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_ref_term_hiz_en_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_REF_TERM_HIZ_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxbist_en_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXBIST_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxbist_en_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXBIST_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxbitslip_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXBITSLIP_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxbitslip_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXBITSLIP_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeiosdetectstat_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEIOSDETECTSTAT_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeiosdetectstat_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEIOSDETECTSTAT_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeq_clr_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEQ_CLR_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeq_clr_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEQ_CLR_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeq_precal_code_sel_l0_nt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeq_precal_code_sel_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEQ_PRECAL_CODE_SEL_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeq_start_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEQ_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeq_start_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEQ_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeq_static_en_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEQ_STATIC_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeq_static_en_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEQ_STATIC_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeyediag_start_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEYEDIAG_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeyediag_start_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEYEDIAG_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_direction_l0_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXMARGIN_DIRECTION_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_direction_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXMARGIN_DIRECTION_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_mode_l0_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXMARGIN_MODE_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_mode_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXMARGIN_MODE_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_offset_change_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXMARGIN_OFFSET_CHANGE_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_offset_change_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXMARGIN_OFFSET_CHANGE_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_offset_l0_nt_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_offset_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXMARGIN_OFFSET_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_start_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXMARGIN_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_start_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXMARGIN_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxpam_gray_en_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXPAM_GRAY_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxpam_gray_en_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXPAM_GRAY_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxpam_precode_en_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXPAM_PRECODE_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxpam_precode_en_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXPAM_PRECODE_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxrate_l0_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxrate_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxterm_hiz_en_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXTERM_HIZ_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxterm_hiz_en_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXTERM_HIZ_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxwidth_l0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxwidth_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXWIDTH_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_spare_nt_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_spare_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SPARE_NT_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcfast_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcfast_divrate_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SYNTHLCFAST_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcfast_force_pup_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SYNTHLCFAST_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcfast_force_pup_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SYNTHLCFAST_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcmed_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcmed_divrate_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SYNTHLCMED_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcmed_force_pup_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SYNTHLCMED_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcmed_force_pup_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SYNTHLCMED_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcslow_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcslow_divrate_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SYNTHLCSLOW_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcslow_force_pup_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SYNTHLCSLOW_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcslow_force_pup_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SYNTHLCSLOW_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txbeacon_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXBEACON_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txbeacon_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXBEACON_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txbist_en_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXBIST_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txbist_en_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXBIST_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txclkdivrate_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txclkdivrate_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXCLKDIVRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdetectrx_req_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXDETECTRX_REQ_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdetectrx_req_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXDETECTRX_REQ_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_levn_l0_attr == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_levn_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXDRV_LEVN_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_levnm1_l0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_levnm1_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXDRV_LEVNM1_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_levnm2_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_levnm2_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXDRV_LEVNM2_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_levnp1_l0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_levnp1_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXDRV_LEVNP1_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_slew_l0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_slew_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXDRV_SLEW_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_spare_l0_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_spare_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXDRV_SPARE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txenable_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXENABLE_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txenable_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXENABLE_L0_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txpam_gray_en_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXPAM_GRAY_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txpam_gray_en_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXPAM_GRAY_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txpam_precode_en_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXPAM_PRECODE_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txpam_precode_en_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXPAM_PRECODE_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txrate_l0_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txrate_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txwidth_l0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txwidth_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXWIDTH_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_visa_unit_id_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_ictl_visa_unit_id_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_VISA_UNIT_ID_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_idat_dfx_obs_dig_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_idat_visa_serial_cfg_in_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_irst_apb_mem_b_attr == SERDES_IP_IF_L3_CFG_IRST_APB_MEM_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_irst_apb_mem_b_reg_en_attr == SERDES_IP_IF_L3_CFG_IRST_APB_MEM_B_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_irst_pcs_rx_l0_b_a_attr == SERDES_IP_IF_L3_CFG_IRST_PCS_RX_L0_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_irst_pcs_rx_l0_b_a_reg_en_attr == SERDES_IP_IF_L3_CFG_IRST_PCS_RX_L0_B_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_irst_pcs_tstbus_b_a_attr == SERDES_IP_IF_L3_CFG_IRST_PCS_TSTBUS_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_irst_pcs_tx_l0_b_a_attr == SERDES_IP_IF_L3_CFG_IRST_PCS_TX_L0_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_irst_pcs_tx_l0_b_a_reg_en_attr == SERDES_IP_IF_L3_CFG_IRST_PCS_TX_L0_B_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_if_l3_cfg_irst_visa_reset_b_a_attr == SERDES_IP_IF_L3_CFG_IRST_VISA_RESET_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l0_cfg_laneclk_ctrl_attr == SERDES_IP_LANE_AON_L0_CFG_LANECLK_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l0_cfg_lanefsm_pmu_req_attr == SERDES_IP_LANE_AON_L0_CFG_LANEFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l0_cfg_lanefsm_pmu_req_en_attr == SERDES_IP_LANE_AON_L0_CFG_LANEFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l0_cfg_lanetstbus_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l0_cfg_rxmem_clr_attr == SERDES_IP_LANE_AON_L0_CFG_RXMEM_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l0_cfg_rxmem_en_attr == SERDES_IP_LANE_AON_L0_CFG_RXMEM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l0_cfg_rxmem_pstate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l0_cfg_rxmem_rate_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l0_cfg_rxmem_req_attr == SERDES_IP_LANE_AON_L0_CFG_RXMEM_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l0_cfg_rxmem_rst_b_attr == SERDES_IP_LANE_AON_L0_CFG_RXMEM_RST_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l0_cfg_rxmem_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l0_cfg_rxrstpdovr_apdrx_sqlch_ovr_b_attr == SERDES_IP_LANE_AON_L0_CFG_RXRSTPDOVR_APDRX_SQLCH_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l0_cfg_rxrstpdovr_apdrx_sqlch_ovren_attr == SERDES_IP_LANE_AON_L0_CFG_RXRSTPDOVR_APDRX_SQLCH_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l0_cfg_rxsussigdetout_ovr_attr == SERDES_IP_LANE_AON_L0_CFG_RXSUSSIGDETOUT_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l0_cfg_rxsussigdetout_ovr_en_attr == SERDES_IP_LANE_AON_L0_CFG_RXSUSSIGDETOUT_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l0_cfg_rxsussqlch_enable_attr == SERDES_IP_LANE_AON_L0_CFG_RXSUSSQLCH_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l0_cfg_txmem_clr_attr == SERDES_IP_LANE_AON_L0_CFG_TXMEM_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l0_cfg_txmem_en_attr == SERDES_IP_LANE_AON_L0_CFG_TXMEM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l0_cfg_txmem_pstate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l0_cfg_txmem_rate_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l0_cfg_txmem_req_attr == SERDES_IP_LANE_AON_L0_CFG_TXMEM_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l0_cfg_txmem_rst_b_attr == SERDES_IP_LANE_AON_L0_CFG_TXMEM_RST_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l0_cfg_txmem_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l0_cfg_txpcs_pciel1d1_ovr_attr == SERDES_IP_LANE_AON_L0_CFG_TXPCS_PCIEL1D1_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l0_cfg_txpcs_pciel1d1_ovren_attr == SERDES_IP_LANE_AON_L0_CFG_TXPCS_PCIEL1D1_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l0_cfg_txpcs_pciel1d2_ovr_attr == SERDES_IP_LANE_AON_L0_CFG_TXPCS_PCIEL1D2_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l0_cfg_txpcs_pciel1d2_ovren_attr == SERDES_IP_LANE_AON_L0_CFG_TXPCS_PCIEL1D2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l0_cfg_txrstpdovr_apdtx_bias_ovr_b_attr == SERDES_IP_LANE_AON_L0_CFG_TXRSTPDOVR_APDTX_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l0_cfg_txrstpdovr_apdtx_bias_ovren_attr == SERDES_IP_LANE_AON_L0_CFG_TXRSTPDOVR_APDTX_BIAS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l0_cfg_txrstpdovr_apdtx_drv_ovr_b_attr == SERDES_IP_LANE_AON_L0_CFG_TXRSTPDOVR_APDTX_DRV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l0_cfg_txrstpdovr_apdtx_drv_ovren_attr == SERDES_IP_LANE_AON_L0_CFG_TXRSTPDOVR_APDTX_DRV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l1_cfg_laneclk_ctrl_attr == SERDES_IP_LANE_AON_L1_CFG_LANECLK_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l1_cfg_lanefsm_pmu_req_attr == SERDES_IP_LANE_AON_L1_CFG_LANEFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l1_cfg_lanefsm_pmu_req_en_attr == SERDES_IP_LANE_AON_L1_CFG_LANEFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l1_cfg_lanetstbus_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l1_cfg_rxmem_clr_attr == SERDES_IP_LANE_AON_L1_CFG_RXMEM_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l1_cfg_rxmem_en_attr == SERDES_IP_LANE_AON_L1_CFG_RXMEM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l1_cfg_rxmem_pstate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l1_cfg_rxmem_rate_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l1_cfg_rxmem_req_attr == SERDES_IP_LANE_AON_L1_CFG_RXMEM_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l1_cfg_rxmem_rst_b_attr == SERDES_IP_LANE_AON_L1_CFG_RXMEM_RST_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l1_cfg_rxmem_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l1_cfg_rxrstpdovr_apdrx_sqlch_ovr_b_attr == SERDES_IP_LANE_AON_L1_CFG_RXRSTPDOVR_APDRX_SQLCH_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l1_cfg_rxrstpdovr_apdrx_sqlch_ovren_attr == SERDES_IP_LANE_AON_L1_CFG_RXRSTPDOVR_APDRX_SQLCH_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l1_cfg_rxsussigdetout_ovr_attr == SERDES_IP_LANE_AON_L1_CFG_RXSUSSIGDETOUT_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l1_cfg_rxsussigdetout_ovr_en_attr == SERDES_IP_LANE_AON_L1_CFG_RXSUSSIGDETOUT_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l1_cfg_rxsussqlch_enable_attr == SERDES_IP_LANE_AON_L1_CFG_RXSUSSQLCH_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l1_cfg_txmem_clr_attr == SERDES_IP_LANE_AON_L1_CFG_TXMEM_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l1_cfg_txmem_en_attr == SERDES_IP_LANE_AON_L1_CFG_TXMEM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l1_cfg_txmem_pstate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l1_cfg_txmem_rate_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l1_cfg_txmem_req_attr == SERDES_IP_LANE_AON_L1_CFG_TXMEM_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l1_cfg_txmem_rst_b_attr == SERDES_IP_LANE_AON_L1_CFG_TXMEM_RST_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l1_cfg_txmem_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l1_cfg_txpcs_pciel1d1_ovr_attr == SERDES_IP_LANE_AON_L1_CFG_TXPCS_PCIEL1D1_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l1_cfg_txpcs_pciel1d1_ovren_attr == SERDES_IP_LANE_AON_L1_CFG_TXPCS_PCIEL1D1_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l1_cfg_txpcs_pciel1d2_ovr_attr == SERDES_IP_LANE_AON_L1_CFG_TXPCS_PCIEL1D2_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l1_cfg_txpcs_pciel1d2_ovren_attr == SERDES_IP_LANE_AON_L1_CFG_TXPCS_PCIEL1D2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l1_cfg_txrstpdovr_apdtx_bias_ovr_b_attr == SERDES_IP_LANE_AON_L1_CFG_TXRSTPDOVR_APDTX_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l1_cfg_txrstpdovr_apdtx_bias_ovren_attr == SERDES_IP_LANE_AON_L1_CFG_TXRSTPDOVR_APDTX_BIAS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l1_cfg_txrstpdovr_apdtx_drv_ovr_b_attr == SERDES_IP_LANE_AON_L1_CFG_TXRSTPDOVR_APDTX_DRV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l1_cfg_txrstpdovr_apdtx_drv_ovren_attr == SERDES_IP_LANE_AON_L1_CFG_TXRSTPDOVR_APDTX_DRV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l2_cfg_laneclk_ctrl_attr == SERDES_IP_LANE_AON_L2_CFG_LANECLK_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l2_cfg_lanefsm_pmu_req_attr == SERDES_IP_LANE_AON_L2_CFG_LANEFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l2_cfg_lanefsm_pmu_req_en_attr == SERDES_IP_LANE_AON_L2_CFG_LANEFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l2_cfg_lanetstbus_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l2_cfg_rxmem_clr_attr == SERDES_IP_LANE_AON_L2_CFG_RXMEM_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l2_cfg_rxmem_en_attr == SERDES_IP_LANE_AON_L2_CFG_RXMEM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l2_cfg_rxmem_pstate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l2_cfg_rxmem_rate_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l2_cfg_rxmem_req_attr == SERDES_IP_LANE_AON_L2_CFG_RXMEM_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l2_cfg_rxmem_rst_b_attr == SERDES_IP_LANE_AON_L2_CFG_RXMEM_RST_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l2_cfg_rxmem_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l2_cfg_rxrstpdovr_apdrx_sqlch_ovr_b_attr == SERDES_IP_LANE_AON_L2_CFG_RXRSTPDOVR_APDRX_SQLCH_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l2_cfg_rxrstpdovr_apdrx_sqlch_ovren_attr == SERDES_IP_LANE_AON_L2_CFG_RXRSTPDOVR_APDRX_SQLCH_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l2_cfg_rxsussigdetout_ovr_attr == SERDES_IP_LANE_AON_L2_CFG_RXSUSSIGDETOUT_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l2_cfg_rxsussigdetout_ovr_en_attr == SERDES_IP_LANE_AON_L2_CFG_RXSUSSIGDETOUT_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l2_cfg_rxsussqlch_enable_attr == SERDES_IP_LANE_AON_L2_CFG_RXSUSSQLCH_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l2_cfg_txmem_clr_attr == SERDES_IP_LANE_AON_L2_CFG_TXMEM_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l2_cfg_txmem_en_attr == SERDES_IP_LANE_AON_L2_CFG_TXMEM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l2_cfg_txmem_pstate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l2_cfg_txmem_rate_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l2_cfg_txmem_req_attr == SERDES_IP_LANE_AON_L2_CFG_TXMEM_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l2_cfg_txmem_rst_b_attr == SERDES_IP_LANE_AON_L2_CFG_TXMEM_RST_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l2_cfg_txmem_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l2_cfg_txpcs_pciel1d1_ovr_attr == SERDES_IP_LANE_AON_L2_CFG_TXPCS_PCIEL1D1_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l2_cfg_txpcs_pciel1d1_ovren_attr == SERDES_IP_LANE_AON_L2_CFG_TXPCS_PCIEL1D1_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l2_cfg_txpcs_pciel1d2_ovr_attr == SERDES_IP_LANE_AON_L2_CFG_TXPCS_PCIEL1D2_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l2_cfg_txpcs_pciel1d2_ovren_attr == SERDES_IP_LANE_AON_L2_CFG_TXPCS_PCIEL1D2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l2_cfg_txrstpdovr_apdtx_bias_ovr_b_attr == SERDES_IP_LANE_AON_L2_CFG_TXRSTPDOVR_APDTX_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l2_cfg_txrstpdovr_apdtx_bias_ovren_attr == SERDES_IP_LANE_AON_L2_CFG_TXRSTPDOVR_APDTX_BIAS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l2_cfg_txrstpdovr_apdtx_drv_ovr_b_attr == SERDES_IP_LANE_AON_L2_CFG_TXRSTPDOVR_APDTX_DRV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l2_cfg_txrstpdovr_apdtx_drv_ovren_attr == SERDES_IP_LANE_AON_L2_CFG_TXRSTPDOVR_APDTX_DRV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l3_cfg_laneclk_ctrl_attr == SERDES_IP_LANE_AON_L3_CFG_LANECLK_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l3_cfg_lanefsm_pmu_req_attr == SERDES_IP_LANE_AON_L3_CFG_LANEFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l3_cfg_lanefsm_pmu_req_en_attr == SERDES_IP_LANE_AON_L3_CFG_LANEFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l3_cfg_lanetstbus_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l3_cfg_rxmem_clr_attr == SERDES_IP_LANE_AON_L3_CFG_RXMEM_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l3_cfg_rxmem_en_attr == SERDES_IP_LANE_AON_L3_CFG_RXMEM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l3_cfg_rxmem_pstate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l3_cfg_rxmem_rate_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l3_cfg_rxmem_req_attr == SERDES_IP_LANE_AON_L3_CFG_RXMEM_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l3_cfg_rxmem_rst_b_attr == SERDES_IP_LANE_AON_L3_CFG_RXMEM_RST_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l3_cfg_rxmem_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l3_cfg_rxrstpdovr_apdrx_sqlch_ovr_b_attr == SERDES_IP_LANE_AON_L3_CFG_RXRSTPDOVR_APDRX_SQLCH_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l3_cfg_rxrstpdovr_apdrx_sqlch_ovren_attr == SERDES_IP_LANE_AON_L3_CFG_RXRSTPDOVR_APDRX_SQLCH_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l3_cfg_rxsussigdetout_ovr_attr == SERDES_IP_LANE_AON_L3_CFG_RXSUSSIGDETOUT_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l3_cfg_rxsussigdetout_ovr_en_attr == SERDES_IP_LANE_AON_L3_CFG_RXSUSSIGDETOUT_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l3_cfg_rxsussqlch_enable_attr == SERDES_IP_LANE_AON_L3_CFG_RXSUSSQLCH_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l3_cfg_txmem_clr_attr == SERDES_IP_LANE_AON_L3_CFG_TXMEM_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l3_cfg_txmem_en_attr == SERDES_IP_LANE_AON_L3_CFG_TXMEM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l3_cfg_txmem_pstate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l3_cfg_txmem_rate_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l3_cfg_txmem_req_attr == SERDES_IP_LANE_AON_L3_CFG_TXMEM_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l3_cfg_txmem_rst_b_attr == SERDES_IP_LANE_AON_L3_CFG_TXMEM_RST_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l3_cfg_txmem_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l3_cfg_txpcs_pciel1d1_ovr_attr == SERDES_IP_LANE_AON_L3_CFG_TXPCS_PCIEL1D1_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l3_cfg_txpcs_pciel1d1_ovren_attr == SERDES_IP_LANE_AON_L3_CFG_TXPCS_PCIEL1D1_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l3_cfg_txpcs_pciel1d2_ovr_attr == SERDES_IP_LANE_AON_L3_CFG_TXPCS_PCIEL1D2_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l3_cfg_txpcs_pciel1d2_ovren_attr == SERDES_IP_LANE_AON_L3_CFG_TXPCS_PCIEL1D2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l3_cfg_txrstpdovr_apdtx_bias_ovr_b_attr == SERDES_IP_LANE_AON_L3_CFG_TXRSTPDOVR_APDTX_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l3_cfg_txrstpdovr_apdtx_bias_ovren_attr == SERDES_IP_LANE_AON_L3_CFG_TXRSTPDOVR_APDTX_BIAS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l3_cfg_txrstpdovr_apdtx_drv_ovr_b_attr == SERDES_IP_LANE_AON_L3_CFG_TXRSTPDOVR_APDTX_DRV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_aon_l3_cfg_txrstpdovr_apdtx_drv_ovren_attr == SERDES_IP_LANE_AON_L3_CFG_TXRSTPDOVR_APDTX_DRV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_bshihyst_attr == SERDES_IP_LANE_L0_CFG_BSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_bstxdrv_levn_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_bstxdrv_levnm1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_bstxdrv_levnp1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_bstxdrv_levnp2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_calsqlchosc_locovren_attr == SERDES_IP_LANE_L0_CFG_CALSQLCHOSC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_calsqlchosc_trimcode_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_cdrclkstat_locovren_attr == SERDES_IP_LANE_L0_CFG_CDRCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_cdrclkstat_ready_locovr_attr == SERDES_IP_LANE_L0_CFG_CDRCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_etrregrxcdrclk_ready_attr == SERDES_IP_LANE_L0_CFG_ETRREGRXCDRCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_laneckm_avg_en_attr == SERDES_IP_LANE_L0_CFG_LANECKM_AVG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_laneckm_clk_en_attr == SERDES_IP_LANE_L0_CFG_LANECKM_CLK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_laneckm_continuous_attr == SERDES_IP_LANE_L0_CFG_LANECKM_CONTINUOUS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_laneckm_dig_meas_en_attr == SERDES_IP_LANE_L0_CFG_LANECKM_DIG_MEAS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_laneckm_dig_meas_err_clr_attr == SERDES_IP_LANE_L0_CFG_LANECKM_DIG_MEAS_ERR_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_laneckm_en_attr == SERDES_IP_LANE_L0_CFG_LANECKM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_laneckm_max_thr_attr == 25'd33554431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_laneckm_meas_ck_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_laneckm_ref_ck_div_ratio_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_laneckm_result_clr_attr == SERDES_IP_LANE_L0_CFG_LANECKM_RESULT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_laneckm_start_attr == SERDES_IP_LANE_L0_CFG_LANECKM_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_laneckm_wdt_interval_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_laneckm_win_thr_ref_attr == 25'd16777215
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_lanepcs_locovren_attr == SERDES_IP_LANE_L0_CFG_LANEPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_lanepcs_mode_locovr_attr == SERDES_IP_LANE_L0_CFG_LANEPCS_MODE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_laneperfmon_compare_val_start_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_laneperfmon_compare_val_stop_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_laneperfmon_en_attr == SERDES_IP_LANE_L0_CFG_LANEPERFMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_laneperfmon_mask_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_lanepmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_lanepmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_lanepmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_lanepmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_lanepmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_lanepmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_lb_cdrclk2txen_locovr_attr == SERDES_IP_LANE_L0_CFG_LB_CDRCLK2TXEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_lb_cdrclkdiven_attr == SERDES_IP_LANE_L0_CFG_LB_CDRCLKDIVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_lb_cdrdivclk2exten_attr == SERDES_IP_LANE_L0_CFG_LB_CDRDIVCLK2EXTEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_lb_cdrdivclk2txen_attr == SERDES_IP_LANE_L0_CFG_LB_CDRDIVCLK2TXEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_lb_hsclk2cdrdiven_attr == SERDES_IP_LANE_L0_CFG_LB_HSCLK2CDRDIVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_lb_locovren_attr == SERDES_IP_LANE_L0_CFG_LB_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_lb_parrx2txtimeden_locovr_attr == SERDES_IP_LANE_L0_CFG_LB_PARRX2TXTIMEDEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_lb_pllfbclk2cdrrefclken_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_lb_pllfbclk2cdrrefclken_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_lb_pllfbclk2cdrrefclken_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_lb_pllfbclk2cdrrefclken_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_lb_pllfbclk2cdrrefclken_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_lb_rx2txuntimeden_attr == SERDES_IP_LANE_L0_CFG_LB_RX2TXUNTIMEDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_lb_rxwordck2pcstxwordcken_attr == SERDES_IP_LANE_L0_CFG_LB_RXWORDCK2PCSTXWORDCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_lb_tx2rxbuftimeden_lsb_locovr_attr == SERDES_IP_LANE_L0_CFG_LB_TX2RXBUFTIMEDEN_LSB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_lb_tx2rxbuftimeden_msb_locovr_attr == SERDES_IP_LANE_L0_CFG_LB_TX2RXBUFTIMEDEN_MSB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_lb_tx2rxiotimeden_attr == SERDES_IP_LANE_L0_CFG_LB_TX2RXIOTIMEDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_lfps_det_locovr_attr == SERDES_IP_LANE_L0_CFG_LFPS_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_lfps_locovren_attr == SERDES_IP_LANE_L0_CFG_LFPS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_lfps_out_en_attr == SERDES_IP_LANE_L0_CFG_LFPS_OUT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_pcslfps_en_locovr_attr == SERDES_IP_LANE_L0_CFG_PCSLFPS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_pcslfps_locovren_attr == SERDES_IP_LANE_L0_CFG_PCSLFPS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_pcsrx_dme_en_locovr_attr == SERDES_IP_LANE_L0_CFG_PCSRX_DME_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_pcsrx_locovren_attr == SERDES_IP_LANE_L0_CFG_PCSRX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_pcsrxbist_locovren_attr == SERDES_IP_LANE_L0_CFG_PCSRXBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_pcsrxbist_modesel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_pcstx_beaconen_locovr_attr == SERDES_IP_LANE_L0_CFG_PCSTX_BEACONEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_pcstx_locovren_attr == SERDES_IP_LANE_L0_CFG_PCSTX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_polarity_rx_attr == SERDES_IP_LANE_L0_CFG_POLARITY_RX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_polarity_tx_attr == SERDES_IP_LANE_L0_CFG_POLARITY_TX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rx_cmn_on_state_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rx_fastregpwrup_en_attr == SERDES_IP_LANE_L0_CFG_RX_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rx_frac_mode_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rx_on_state_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rx_pg_disable_attr == SERDES_IP_LANE_L0_CFG_RX_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rx_synth_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rx_synth_sel_amode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rx_synth_sel_bmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rx_synth_sel_cmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rx_synth_sel_dmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rx_synth_sel_emode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxadc_req_attr == SERDES_IP_LANE_L0_CFG_RXADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxagc_dccoupleen_attr == SERDES_IP_LANE_L0_CFG_RXAGC_DCCOUPLEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxaprobe_addr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxaprobe_lastmux_isolate_attr == SERDES_IP_LANE_L0_CFG_RXAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxaprobeadc_current_direction_attr == SERDES_IP_LANE_L0_CFG_RXAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxaprobeadc_resistor_enable_attr == SERDES_IP_LANE_L0_CFG_RXAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxbias_iccadj_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxbias_icvadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxbias_locovren_attr == SERDES_IP_LANE_L0_CFG_RXBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxbias_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxbist_burst_four_errtype_attr == SERDES_IP_LANE_L0_CFG_RXBIST_BURST_FOUR_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxbist_burst_one_errtype_attr == SERDES_IP_LANE_L0_CFG_RXBIST_BURST_ONE_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxbist_burst_three_errtype_attr == SERDES_IP_LANE_L0_CFG_RXBIST_BURST_THREE_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxbist_burst_two_errtype_attr == SERDES_IP_LANE_L0_CFG_RXBIST_BURST_TWO_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxbist_cdrlock2data_bypass_attr == SERDES_IP_LANE_L0_CFG_RXBIST_CDRLOCK2DATA_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxbist_cdrlock2data_postamble_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxbist_clear_errcount_attr == SERDES_IP_LANE_L0_CFG_RXBIST_CLEAR_ERRCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxbist_err_en_attr == SERDES_IP_LANE_L0_CFG_RXBIST_ERR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxbist_err_trig_type_attr == SERDES_IP_LANE_L0_CFG_RXBIST_ERR_TRIG_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxbist_errmask_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxbist_errtype_attr == SERDES_IP_LANE_L0_CFG_RXBIST_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxbist_firsterr_type_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxbist_lockchk_count_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxbist_maxbitcnt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxbist_mostrecent_err_attr == SERDES_IP_LANE_L0_CFG_RXBIST_MOSTRECENT_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxbist_relock_itercount_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxbist_seed_attr == 31'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxbist_status_hold_attr == SERDES_IP_LANE_L0_CFG_RXBIST_STATUS_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxbitslip_locovr_attr == SERDES_IP_LANE_L0_CFG_RXBITSLIP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxbitslip_locovren_attr == SERDES_IP_LANE_L0_CFG_RXBITSLIP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxbscan_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxbshicm_attr == SERDES_IP_LANE_L0_CFG_RXBSHICM_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalcdrfbdiv_div2_bypass_muxd0_attr == SERDES_IP_LANE_L0_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalcdrfbdiv_div2_bypass_muxd1_attr == SERDES_IP_LANE_L0_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalcdrfbdiv_div2_bypass_muxd2_attr == SERDES_IP_LANE_L0_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalcdrfbdiv_div2_bypass_muxd3_attr == SERDES_IP_LANE_L0_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalcdrfbdiv_div2_bypass_muxd4_attr == SERDES_IP_LANE_L0_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalduty_iclk_gray_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalduty_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTY_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalduty_qclk_gray_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalduty_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutybg_abort_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutybg_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutybg_ready_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycomp_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycomp_offset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_finish_side_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_init_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_initval_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_invert_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_round_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_runcount_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_signmagen_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsmout_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsmout_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_disable_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCTRL_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_i_div1_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_i_div2_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_i_div4_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_i_div8_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_q_div1_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_q_div2_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_q_div4_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_q_div8_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_bg_en_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_bg_one_step_cal_en_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_finish_side_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_i_polarity_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_I_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_i_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_I_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_init_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_q_polarity_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_Q_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_q_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_Q_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_round_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_runcount_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_signmagen_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_comp_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEAS_COMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_comp_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEAS_COMP_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_i_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEAS_I_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_i_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEAS_I_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_q_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEAS_Q_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_q_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEAS_Q_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeasout_comp_ack_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEASOUT_COMP_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeasout_comp_erravg_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEASOUT_COMP_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeasout_i_ack_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEASOUT_I_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeasout_i_erravg_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEASOUT_I_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeasout_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeasout_q_ack_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEASOUT_Q_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeasout_q_erravg_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEASOUT_Q_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutystat_done_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaldutystat_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_centerfreq_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_end_delay_attr == 9'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_hscount_muxd0_attr == 8'd181
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_hscount_muxd1_attr == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_hscount_muxd2_attr == 8'd180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_hscount_muxd3_attr == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_hscount_muxd4_attr == 8'd206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_initval_centerfreq_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_initval_fosc_attr == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_centerfreq_finish_side_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_CENTERFREQ_FINISH_SIDE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_centerfreq_to_fosc_offset_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_centerfreqen_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_CENTERFREQEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_centerfreqoffset_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_fosc_finishside_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_FOSC_FINISHSIDE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_foscen_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_FOSCEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_foscoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_init_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_invert_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_lpfax_calfosccoarse_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_lpfax_calfoscfine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_lpfax_centerfreqcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_lpfax_centerfreqfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_runcount_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_signmagen_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_vcorepen_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_VCOREPEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsmout_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsmout_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_count_muxd0_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_count_muxd1_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_count_muxd2_attr == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_count_muxd3_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_count_muxd4_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_dlycount_attr == 9'd68
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeasout_clear_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCMEASOUT_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeasout_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeasout_start_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCMEASOUT_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscval_int_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscval_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalintsval_int_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalintsval_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALINTSVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaloffsetfsm_init_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaloffsetfsm_init_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaloffsetfsm_init_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALOFFSETFSM_INIT_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaloffsetfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcaloffsetfsmout_input_en_attr == SERDES_IP_LANE_L0_CFG_RXCALOFFSETFSMOUT_INPUT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_duty_i_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_duty_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_dutycomp_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_foscfsm_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_offsetfsm_init_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_regopampoffset_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_rxppm_lockstatus_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_sqlch_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_sqlchosc_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_synthppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_voscregopampoffset_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_duty_i_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_duty_q_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_dutycomp_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_foscfsm_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_offsetfsm_init_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_rxppm_lockstatus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_sqlch_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_sqlchosc_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_synthppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_voscregopampoffset_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffset_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_finish_side_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_round_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_runcount_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_signmagen_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchfsm_clear_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchfsm_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchfsmout_caldone_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHFSMOUT_CALDONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchfsmout_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_codeoffset_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_finish_side_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHOSCFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_init_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHOSCFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_initval_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_invert_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHOSCFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHOSCFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHOSCFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_round_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHOSCFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_runcount_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHOSCFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscmeas_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHOSCMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscmeas_ref_cnt_attr == 10'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscmeas_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHOSCMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscmeas_settle_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscmeas_smpl_cnt_attr == 10'd144
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvbiascap_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALVBIASCAP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvbiascap_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALVBIASCAP_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvcoopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvcoopampoffsetmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvcoopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvcoopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffset_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffset_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_codeoffset_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_finish_side_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_initval_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_invert_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_lpfaxcoarse_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_round_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_runcount_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETFSM_RUNCOUNT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_signmagen_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsmout_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsmout_runcount_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETFSMOUT_RUNCOUNT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetmeas_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffset_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALVOSCREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALVOSCREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L0_CFG_RXCALVOSCREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALVOSCREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALVOSCREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALVOSCREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALVOSCREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALVOSCREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALVOSCREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrdiv_local_en_attr == SERDES_IP_LANE_L0_CFG_RXCDRDIV_LOCAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdiv_moddiv_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdiv_moddiv_muxd1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdiv_moddiv_muxd2_attr == 4'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdiv_moddiv_muxd3_attr == 4'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdiv_moddiv_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdivslip_mdiv_muxd0_attr == 9'd194
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdivslip_mdiv_muxd1_attr == 9'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdivslip_mdiv_muxd2_attr == 9'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdivslip_mdiv_muxd3_attr == 9'd66
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdivslip_mdiv_muxd4_attr == 9'd210
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrpfd_forcedn_attr == SERDES_IP_LANE_L0_CFG_RXCDRPFD_FORCEDN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrpfd_forceen_attr == SERDES_IP_LANE_L0_CFG_RXCDRPFD_FORCEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrpfd_forceup_attr == SERDES_IP_LANE_L0_CFG_RXCDRPFD_FORCEUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrpfd_propgain_attr == SERDES_IP_LANE_L0_CFG_RXCDRPFD_PROPGAIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrpfd_pulsewidth_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrphd_asym_override_ignore_attr == SERDES_IP_LANE_L0_CFG_RXCDRPHD_ASYM_OVERRIDE_IGNORE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrphd_bitshift_en_attr == SERDES_IP_LANE_L0_CFG_RXCDRPHD_BITSHIFT_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrphd_forcedn_attr == SERDES_IP_LANE_L0_CFG_RXCDRPHD_FORCEDN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrphd_forceen_attr == SERDES_IP_LANE_L0_CFG_RXCDRPHD_FORCEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrphd_forceup_attr == SERDES_IP_LANE_L0_CFG_RXCDRPHD_FORCEUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrphdrate_doublerate2s2p_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCDRPHDRATE_DOUBLERATE2S2P_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrphdrate_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCDRPHDRATE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrrefck_refdiv_muxd0_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrrefck_refdiv_muxd1_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrrefck_refdiv_muxd2_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrrefck_refdiv_muxd3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrrefck_refdiv_muxd4_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_biastop_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_biastopbypass_attr == SERDES_IP_LANE_L0_CFG_RXCDRVCO_BIASTOPBYPASS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_datapropgain_high_attr == 5'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_datapropgain_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_datapropgain_low_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_ff_ovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_ff_ovr_en_attr == SERDES_IP_LANE_L0_CFG_RXCDRVCO_FF_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_fil_short_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_flickerdegen_attr == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_gmfoscshort_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCDRVCO_GMFOSCSHORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_intf_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_intf_fil_short_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_intrj_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCDRVCO_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_refpropgain_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_refpropgain_nom_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxclk_cdrfb_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCLK_CDRFB_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxclk_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxclk_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdat_nrz_64b80b_bcword_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdata_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXDATA_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdata_locovren_attr == SERDES_IP_LANE_L0_CFG_RXDATA_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdatapath_locovren_attr == SERDES_IP_LANE_L0_CFG_RXDATAPATH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdatapath_on_state_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdatapath_ready_locovr_attr == SERDES_IP_LANE_L0_CFG_RXDATAPATH_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdfe_datatap_vcasc_attr == 4'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdfe_dfebiasadj_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdfe_nbiasctle_en_attr == SERDES_IP_LANE_L0_CFG_RXDFE_NBIASCTLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdfe_vcasc_sel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdfeterm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXDFETERM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdfeterm_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdfeyadjdac_datamid_edge_coarse_en_attr == SERDES_IP_LANE_L0_CFG_RXDFEYADJDAC_DATAMID_EDGE_COARSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdfeyadjdac_datatopbot_aux_coarse_en_attr == SERDES_IP_LANE_L0_CFG_RXDFEYADJDAC_DATATOPBOT_AUX_COARSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_accum_mon_en_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_ACCUM_MON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_accum_mon_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_bypasscdrpdetupdnsmpl_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_bypassenfosc_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_BYPASSENFOSC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_bypassenints_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_BYPASSENINTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_bypassenupdnsmpl_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_BYPASSENUPDNSMPL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_bypassfosc_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_bypasspllpfdupdnsmpl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_bypassrxints_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_data2pll_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_deltasigmode_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_DELTASIGMODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_fastref_muxd0_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_FASTREF_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_fastref_muxd1_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_FASTREF_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_fastref_muxd2_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_FASTREF_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_fastref_muxd3_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_FASTREF_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_fastref_muxd4_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_FASTREF_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_fosc_mod_bypass_en_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_FOSC_MOD_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_fosc_sample_pedge_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_FOSC_SAMPLE_PEDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gain_step_on_lock_recovery_en_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_GAIN_STEP_ON_LOCK_RECOVERY_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gaindelaycount_init_attr == 9'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gaindelaycount_pow2_muxd0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gaindelaycount_pow2_muxd1_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gaindelaycount_pow2_muxd2_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gaindelaycount_pow2_muxd3_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gaindelaycount_pow2_muxd4_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2ref_pow2_muxd0_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2ref_pow2_muxd1_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2ref_pow2_muxd2_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2ref_pow2_muxd3_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2ref_pow2_muxd4_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainunlocked_pow2_muxd0_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainunlocked_pow2_muxd1_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainunlocked_pow2_muxd2_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainunlocked_pow2_muxd3_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainunlocked_pow2_muxd4_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_initintegrator_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_INITINTEGRATOR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_initmodulator_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_INITMODULATOR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_deltasig_mode_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_INTS_DELTASIG_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_freeze_en_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_INTS_FREEZE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gaindelaycount_pow2_muxd0_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gaindelaycount_pow2_muxd1_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gaindelaycount_pow2_muxd2_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gaindelaycount_pow2_muxd3_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gaindelaycount_pow2_muxd4_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd0_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd1_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd2_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd3_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd4_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd0_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd1_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd2_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd3_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd4_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainunlocked_pow2_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainunlocked_pow2_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainunlocked_pow2_muxd2_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainunlocked_pow2_muxd3_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainunlocked_pow2_muxd4_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_guardband_hi_attr == 8'd200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_guardband_lo_attr == 8'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_loop_sel_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_INTS_LOOP_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_mod_bypass_en_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_INTS_MOD_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_mod_load_pedge_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_INTS_MOD_LOAD_PEDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_step_to_integer_en_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_INTS_STEP_TO_INTEGER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_jit_length_attr == 18'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_jit_mode_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_JIT_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_modck_ctrl_en_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_MODCK_CTRL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_pll2data_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_restore_cntr_attr == 9'd258
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_store_cntr_attr == 16'd258
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpif_trnsfrdelay_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpiffreeze_inten_attr == SERDES_IP_LANE_L0_CFG_RXDPIFFREEZE_INTEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdpiffreeze_moden_attr == SERDES_IP_LANE_L0_CFG_RXDPIFFREEZE_MODEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxdutyselpolarity_attr == SERDES_IP_LANE_L0_CFG_RXDUTYSELPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxflxgate_force_rxeq_gate_locovr_attr == SERDES_IP_LANE_L0_CFG_RXFLXGATE_FORCE_RXEQ_GATE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxflxgate_locovren_attr == SERDES_IP_LANE_L0_CFG_RXFLXGATE_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxfoscstat_done_locovr_attr == SERDES_IP_LANE_L0_CFG_RXFOSCSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxfoscstat_locovren_attr == SERDES_IP_LANE_L0_CFG_RXFOSCSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxfsm_cken_ovr_attr == SERDES_IP_LANE_L0_CFG_RXFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxfsm_cken_ovren_attr == SERDES_IP_LANE_L0_CFG_RXFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxints_prev_votes_hold_en_attr == SERDES_IP_LANE_L0_CFG_RXINTS_PREV_VOTES_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxlanepam_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXLANEPAM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxlanepam_locovren_attr == SERDES_IP_LANE_L0_CFG_RXLANEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxlock2datatmr_attr == 8'd240
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxlock2datatmr_short_attr == 8'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxntl_changeref_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxntl_changeref_val_locovr_attr == SERDES_IP_LANE_L0_CFG_RXNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxntl_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxntl_en_attr == SERDES_IP_LANE_L0_CFG_RXNTL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxntl_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxntl_locovren_attr == SERDES_IP_LANE_L0_CFG_RXNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxntl_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxntl_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxntl_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxntl_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxntl_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxntl_rxm_charge_up_locovr_attr == SERDES_IP_LANE_L0_CFG_RXNTL_RXM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxntl_rxm_pull_dn_locovr_attr == SERDES_IP_LANE_L0_CFG_RXNTL_RXM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxntl_rxm_sense_locovr_attr == SERDES_IP_LANE_L0_CFG_RXNTL_RXM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxntl_rxp_charge_up_locovr_attr == SERDES_IP_LANE_L0_CFG_RXNTL_RXP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxntl_rxp_pull_dn_locovr_attr == SERDES_IP_LANE_L0_CFG_RXNTL_RXP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxntl_rxp_sense_locovr_attr == SERDES_IP_LANE_L0_CFG_RXNTL_RXP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxntl_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_acc_freeze_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_ACC_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_cdrlock2data_gater_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_cdrlock2data_gater_hold_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_cdrlock2data_gater_ovrd_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_cdrlock2datatmr_optcl_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_cdrlock2datatmr_optcl_sel_ovrd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_enter_lock2data_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_ENTER_LOCK2DATA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_enter_lock2data_hold_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_ENTER_LOCK2DATA_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_exit_lock2data_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_EXIT_LOCK2DATA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_exit_lock2data_hold_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_EXIT_LOCK2DATA_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_force_lock2data_ovrd_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_FORCE_LOCK2DATA_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_force_lock2ref_ovrd_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_FORCE_LOCK2REF_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_hold_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_hold_timer_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_intf_ovrd_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_INTF_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_intf_ovrd_type_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_INTF_OVRD_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_mod_freeze_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_MOD_FREEZE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_ovrd_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_ppm_detect_freeze_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_PPM_DETECT_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_ppm_detect_freeze_ovrd_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_PPM_DETECT_FREEZE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_ppm_detect_hold_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_PPM_DETECT_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_prop_freeze_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_PROP_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_prop_freeze_ovrd_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_PROP_FREEZE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_rxdata_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_RXDATA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_skip_init_lock2data_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_SKIP_INIT_LOCK2DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxpam_bitorder_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxpam_gray_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXPAM_GRAY_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxpam_locovren_attr == SERDES_IP_LANE_L0_CFG_RXPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxpam_precode_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXPAM_PRECODE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_muxd0_attr == 7'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_p5_muxd0_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIV_P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_p5_muxd1_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIV_P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_p5_muxd2_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIV_P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_p5_muxd3_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIV_P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_p5_muxd4_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIV_P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdivclken_muxd0_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIVCLKEN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdivclken_muxd1_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIVCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdivclken_muxd2_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIVCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdivclken_muxd3_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIVCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdivclken_muxd4_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIVCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxpcsbist_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXPCSBIST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxpcsbist_locovren_attr == SERDES_IP_LANE_L0_CFG_RXPCSBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxphd_gain_hold_en_attr == SERDES_IP_LANE_L0_CFG_RXPHD_GAIN_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxphd_gain_zero_locovr_attr == SERDES_IP_LANE_L0_CFG_RXPHD_GAIN_ZERO_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxphd_locovren_attr == SERDES_IP_LANE_L0_CFG_RXPHD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxphd_majvote_basegain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxphd_majvote_en_attr == SERDES_IP_LANE_L0_CFG_RXPHD_MAJVOTE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxphd_mute_cntr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxphd_nrz8b10b_pam16b20b_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxphd_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxphd_pam_transition_sel_attr == SERDES_IP_LANE_L0_CFG_RXPHD_PAM_TRANSITION_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxphd_sign_invert_attr == SERDES_IP_LANE_L0_CFG_RXPHD_SIGN_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxpostdiv_wait_for_lock_disable_attr == SERDES_IP_LANE_L0_CFG_RXPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxppm_freq_max_offset_h_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxppm_freq_max_offset_l_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxppm_freq_ref_cnt_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxppm_lockstatus_locovr_attr == SERDES_IP_LANE_L0_CFG_RXPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxppm_lockstatus_synthlcfast_en_attr == SERDES_IP_LANE_L0_CFG_RXPPM_LOCKSTATUS_SYNTHLCFAST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxppm_lockstatus_synthlcmed_en_attr == SERDES_IP_LANE_L0_CFG_RXPPM_LOCKSTATUS_SYNTHLCMED_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxppm_lockstatus_synthlcslow_en_attr == SERDES_IP_LANE_L0_CFG_RXPPM_LOCKSTATUS_SYNTHLCSLOW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxppm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxppm_ppmdriftcount_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxppm_ppmdriftmax_attr == 16'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxppm_status_hold_attr == SERDES_IP_LANE_L0_CFG_RXPPM_STATUS_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxppm_unlock_clear_attr == SERDES_IP_LANE_L0_CFG_RXPPM_UNLOCK_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_fast_muxd0_attr == 16'd1188
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_fast_muxd1_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_fast_muxd2_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_fast_muxd3_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_fast_muxd4_attr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_muxd0_attr == 16'd1188
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_muxd1_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_muxd2_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_muxd3_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_muxd4_attr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxppmctrl_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXPPMCTRL_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxppmctrl_locovren_attr == SERDES_IP_LANE_L0_CFG_RXPPMCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxppmlockstat_locovren_attr == SERDES_IP_LANE_L0_CFG_RXPPMLOCKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxppmlockstat_sticky_locovr_attr == SERDES_IP_LANE_L0_CFG_RXPPMLOCKSTAT_STICKY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxppmtmr_locovren_attr == SERDES_IP_LANE_L0_CFG_RXPPMTMR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxppmtmr_watchdogtmr_sel_locovr_attr == SERDES_IP_LANE_L0_CFG_RXPPMTMR_WATCHDOGTMR_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_cal_clear_delay_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_clk_chk_disable_attr == SERDES_IP_LANE_L0_CFG_RXRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_clk_delay_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_etr_on_delay_attr == 12'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_locovren_attr == SERDES_IP_LANE_L0_CFG_RXRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxreg_lev_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxreg_toggle_reset_on_rate_change_en_attr == SERDES_IP_LANE_L0_CFG_RXREG_TOGGLE_RESET_ON_RATE_CHANGE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxreg_vreg_bypass_attr == SERDES_IP_LANE_L0_CFG_RXREG_VREG_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_en_b_attr == SERDES_IP_LANE_L0_CFG_RXRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s0q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s0q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s2q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s2q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s2q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s2q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s2q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s2q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s2q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s3q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s3q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s3q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s3q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s3q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s3q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s3q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s3q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s4q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s4q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s5q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_entry4_attr == 13'd78
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_entry5_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_entry6_attr == 13'd1406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s0q2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s0q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s1q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s1q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s1q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s1q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s1q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s1q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s2q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s2q2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s2q3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s2q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s2q5_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s2q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s2q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s3q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s3q1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s3q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s3q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s3q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s3q5_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s3q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s3q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s4q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s4q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s5q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_aetrrx_cdrfbdivcken_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_AETRRX_CDRFBDIVCKEN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_aetrrx_cdrfbdivcken_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_AETRRX_CDRFBDIVCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_aetrrx_cdrmoddivcken_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_AETRRX_CDRMODDIVCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_aetrrx_cdrmoddivcken_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_AETRRX_CDRMODDIVCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_aetrrx_termhiz_en_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_AETRRX_TERMHIZ_EN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_aetrrx_termhiz_en_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_AETRRX_TERMHIZ_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_aetrsynth_pcspostdivclksel_ovr_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_AETRSYNTH_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_aetrsynth_pcspostdivclksel_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_AETRSYNTH_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_adc_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_adc_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_auxcomp_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_AUXCOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_auxcomp_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_AUXCOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_bias_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_bias_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_BIAS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_ctlecomp_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_CTLECOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_ctlecomp_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_CTLECOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_datfbdiv_b_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DATFBDIV_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_datfbdiv_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DATFBDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_dfe_bias_b_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DFE_BIAS_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_dfe_bias_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DFE_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_dfe_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DFE_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_dfe_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DFE_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_dfe_yadj_b_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DFE_YADJ_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_dfe_yadj_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DFE_YADJ_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_duty_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DUTY_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_duty_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DUTY_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_hifreqagc_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_HIFREQAGC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_hifreqagc_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_HIFREQAGC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_ntl_b_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_ntl_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_reg_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_reg_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_vco_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_VCO_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_vco_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_VCO_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_voscreg_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_VOSCREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_voscreg_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_VOSCREG_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_adc_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_adc_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_cdrfbdiv_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_CDRFBDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_cdrfbdiv_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_CDRFBDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_pdet_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_PDET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_pdet_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_PDET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_pfd_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_PFD_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_pfd_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_PFD_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_refdiv_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_refdiv_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_reg_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_reg_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_s2pa_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_S2PA_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_s2pa_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_S2PA_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_s2pb_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_S2PB_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_s2pb_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_S2PB_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_vco_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_VCO_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_vco_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_VCO_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_voscreg_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_VOSCREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_voscreg_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_VOSCREG_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstsynth_postdiv_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTSYNTH_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstsynth_postdiv_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTSYNTH_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_drstrx_dpif_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_DRSTRX_DPIF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_drstrx_dpif_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_DRSTRX_DPIF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_drstrx_ppm_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_DRSTRX_PPM_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_drstrx_ppm_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_DRSTRX_PPM_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_cdrlock2data_locovr_attr == SERDES_IP_LANE_L0_CFG_RXSIGDET_CDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_diglfpsdeten_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_diglfpsdeten_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_diglfpsdeten_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_diglfpsdeten_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_diglfpsdeten_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrancnten_muxd0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrancnten_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrancnten_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrancnten_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrancnten_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrancnten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrandeten_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrandeten_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrandeten_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrandeten_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrandeten_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrandeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_eiosdeten_muxd0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_eiosdeten_muxd1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_eiosdeten_muxd2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_eiosdeten_muxd3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_eiosdeten_muxd4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_eiosdeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_enable_attr == SERDES_IP_LANE_L0_CFG_RXSIGDET_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_fastlock_winsize_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_leveldeten_muxd0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_leveldeten_muxd1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_leveldeten_muxd2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_leveldeten_muxd3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_leveldeten_muxd4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_leveldeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_lfpsexit_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_locovren_attr == SERDES_IP_LANE_L0_CFG_RXSIGDET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_ppmdeten_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_ppmdeten_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_ppmdeten_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_ppmdeten_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_ppmdeten_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_ppmdeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_rxeq_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_rxeqen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_rxeqen_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_rxleveldet_debounce_dncount_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_rxleveldet_debounce_flush_en_attr == SERDES_IP_LANE_L0_CFG_RXSIGDET_RXLEVELDET_DEBOUNCE_FLUSH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_rxleveldet_debounce_upcount_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_sigdet_debounce_attr == SERDES_IP_LANE_L0_CFG_RXSIGDET_SIGDET_DEBOUNCE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_tmr_clksel_attr == SERDES_IP_LANE_L0_CFG_RXSIGDET_TMR_CLKSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_toggle_count_en_attr == SERDES_IP_LANE_L0_CFG_RXSIGDET_TOGGLE_COUNT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_toggle_count_pause_attr == SERDES_IP_LANE_L0_CFG_RXSIGDET_TOGGLE_COUNT_PAUSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_toggle_monitor_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdetin_eiosdetectstat_locovr_attr == SERDES_IP_LANE_L0_CFG_RXSIGDETIN_EIOSDETECTSTAT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdetin_locovren_attr == SERDES_IP_LANE_L0_CFG_RXSIGDETIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdetin_ovrcdrlock2data_locovr_attr == SERDES_IP_LANE_L0_CFG_RXSIGDETIN_OVRCDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdetin_ovrencdrlock2data_locovr_attr == SERDES_IP_LANE_L0_CFG_RXSIGDETIN_OVRENCDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdetout_lock2data_noforce_ltr_locovr_attr == SERDES_IP_LANE_L0_CFG_RXSIGDETOUT_LOCK2DATA_NOFORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsigdetout_locovren_attr == SERDES_IP_LANE_L0_CFG_RXSIGDETOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxspare0_attr == 32'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxspare_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsqlchlfps_consec_one_thresh_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsqlchlfps_consec_zero_thresh_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsqlchlfps_cycle_thresh_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsqlchlfps_dat_bitorder_attr == SERDES_IP_LANE_L0_CFG_RXSQLCHLFPS_DAT_BITORDER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsqlchlfps_debounce_type_attr == SERDES_IP_LANE_L0_CFG_RXSQLCHLFPS_DEBOUNCE_TYPE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsqlchlfps_one_run_length_thresh_attr == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsqlchlfps_one_run_length_timeout_attr == 8'd103
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsqlchlfps_zero_run_length_thresh_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsqlchlfps_zero_run_length_timeout_attr == 8'd103
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsynthdiv_slowmed_en_muxd0_attr == SERDES_IP_LANE_L0_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsynthdiv_slowmed_en_muxd1_attr == SERDES_IP_LANE_L0_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsynthdiv_slowmed_en_muxd2_attr == SERDES_IP_LANE_L0_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsynthdiv_slowmed_en_muxd3_attr == SERDES_IP_LANE_L0_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxsynthdiv_slowmed_en_muxd4_attr == SERDES_IP_LANE_L0_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxterm_cal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxterm_coarse_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxterm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXTERM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxterm_modeselect_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxtermhiz_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXTERMHIZ_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxtermhiz_locovren_attr == SERDES_IP_LANE_L0_CFG_RXTERMHIZ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxvoscreg_bypass_vosc_attr == SERDES_IP_LANE_L0_CFG_RXVOSCREG_BYPASS_VOSC_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxvoscregopampoffsetctrl_sel_attr == SERDES_IP_LANE_L0_CFG_RXVOSCREGOPAMPOFFSETCTRL_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxvoscregopampoffseterr_locovren_attr == SERDES_IP_LANE_L0_CFG_RXVOSCREGOPAMPOFFSETERR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxvoscregopampoffseterr_sel_locovr_attr == SERDES_IP_LANE_L0_CFG_RXVOSCREGOPAMPOFFSETERR_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxvoscregvref_locovren_attr == SERDES_IP_LANE_L0_CFG_RXVOSCREGVREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_rxvoscregvref_sel_locovr_attr == SERDES_IP_LANE_L0_CFG_RXVOSCREGVREF_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlch_acqgain_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlch_acqtime_attr == 13'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlch_cal_quiet_locovr_attr == SERDES_IP_LANE_L0_CFG_SQLCH_CAL_QUIET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlch_cal_sel_locovr_attr == SERDES_IP_LANE_L0_CFG_SQLCH_CAL_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlch_calctrl_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlch_calen_locovr_attr == SERDES_IP_LANE_L0_CFG_SQLCH_CALEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlch_caltimer_attr == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlch_clkgate_locovr_attr == SERDES_IP_LANE_L0_CFG_SQLCH_CLKGATE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlch_cmshiften_attr == SERDES_IP_LANE_L0_CFG_SQLCH_CMSHIFTEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_acq_gain_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_acq_pct_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_cal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_clr_errlog_attr == SERDES_IP_LANE_L0_CFG_SQLCH_CONT_CLR_ERRLOG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_controller_mode_attr == SERDES_IP_LANE_L0_CFG_SQLCH_CONT_CONTROLLER_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_dis_attr == SERDES_IP_LANE_L0_CFG_SQLCH_CONT_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_pause_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_postcal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_precal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_quiet_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlch_lfps_en_attr == SERDES_IP_LANE_L0_CFG_SQLCH_LFPS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlch_locovren_attr == SERDES_IP_LANE_L0_CFG_SQLCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlch_ovrd_val_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlch_pkdet_freqsel_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlch_polarity_attr == SERDES_IP_LANE_L0_CFG_SQLCH_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlch_rdacen_attr == SERDES_IP_LANE_L0_CFG_SQLCH_RDACEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlch_thresh_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlch_time_out_attr == 16'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlch_vrefsel0_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlch_vrefsel1_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlch_vrefsel_ovr_en_attr == SERDES_IP_LANE_L0_CFG_SQLCH_VREFSEL_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlchdeb_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlchdeb_deb_cnt_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlchdeb_deb_status_cnt_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlchdeb_en_attr == SERDES_IP_LANE_L0_CFG_SQLCHDEB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlchdeb_ign_cnt_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlchdeb_sigdet_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlchdeb_thresh_cnt_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlchdebout_exit_good_debounced_locovr_attr == SERDES_IP_LANE_L0_CFG_SQLCHDEBOUT_EXIT_GOOD_DEBOUNCED_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlchdebout_exit_good_debounced_status_locovr_attr == SERDES_IP_LANE_L0_CFG_SQLCHDEBOUT_EXIT_GOOD_DEBOUNCED_STATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlchdebout_exit_good_locovr_attr == SERDES_IP_LANE_L0_CFG_SQLCHDEBOUT_EXIT_GOOD_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_sqlchdebout_locovren_attr == SERDES_IP_LANE_L0_CFG_SQLCHDEBOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_trancnt_off_attr == 10'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_trancnt_on_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_trancntout_det_locovr_attr == SERDES_IP_LANE_L0_CFG_TRANCNTOUT_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_trancntout_locovren_attr == SERDES_IP_LANE_L0_CFG_TRANCNTOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_trandet_ax_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_trandet_ay_attr == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_trandet_off_h_attr == 6'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_trandet_off_l_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_trandet_on_h_attr == 6'd39
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_trandet_on_l_attr == 6'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_trandetout_det_locovr_attr == SERDES_IP_LANE_L0_CFG_TRANDETOUT_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_trandetout_locovren_attr == SERDES_IP_LANE_L0_CFG_TRANDETOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_tx2rxlb_en_attr == SERDES_IP_LANE_L0_CFG_TX2RXLB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_tx2rxlb_init_offset_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_tx_cmn_on_state_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_tx_fastregpwrup_en_attr == SERDES_IP_LANE_L0_CFG_TX_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_tx_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_tx_pg_disable_attr == SERDES_IP_LANE_L0_CFG_TX_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_tx_synth_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_tx_synth_sel_amode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_tx_synth_sel_bmode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_tx_synth_sel_cmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_tx_synth_sel_dmode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_tx_synth_sel_emode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_tx_txdetrx_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txadc_req_attr == SERDES_IP_LANE_L0_CFG_TXADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txaprobe_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txaprobe_lastmux_isolate_attr == SERDES_IP_LANE_L0_CFG_TXAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txaprobeadc_current_direction_attr == SERDES_IP_LANE_L0_CFG_TXAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txaprobeadc_resistor_enable_attr == SERDES_IP_LANE_L0_CFG_TXAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txbdvdr_pma2pcstxworden_attr == SERDES_IP_LANE_L0_CFG_TXBDVDR_PMA2PCSTXWORDEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txbeacon_div_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txbeacon_sel_attr == SERDES_IP_LANE_L0_CFG_TXBEACON_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txbias_icc20uadj_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txbias_icc80uadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txbias_locovren_attr == SERDES_IP_LANE_L0_CFG_TXBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txbias_termcal_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txbist_biterror_en_attr == SERDES_IP_LANE_L0_CFG_TXBIST_BITERROR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txbist_locovren_attr == SERDES_IP_LANE_L0_CFG_TXBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txbist_modesel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txbist_oobmode_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txbist_oobtburst_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txbist_oobtcomrstinit_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txbist_oobtcomsas_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txbist_oobtcomwake_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txbist_seed_attr == 31'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_size_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf00_attr == 32'd1985229328
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf01_attr == 32'd4275878552
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf02_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf03_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf04_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf05_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf06_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf07_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf08_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf09_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txbit_select_muxd0_attr == SERDES_IP_LANE_L0_CFG_TXBIT_SELECT_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txbit_select_muxd1_attr == SERDES_IP_LANE_L0_CFG_TXBIT_SELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txbit_select_muxd2_attr == SERDES_IP_LANE_L0_CFG_TXBIT_SELECT_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txbit_select_muxd3_attr == SERDES_IP_LANE_L0_CFG_TXBIT_SELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txbit_select_muxd4_attr == SERDES_IP_LANE_L0_CFG_TXBIT_SELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txbti_data_replication_attr == SERDES_IP_LANE_L0_CFG_TXBTI_DATA_REPLICATION_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txbti_tx_idle_data_en_attr == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcal_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcal_tclkduty_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalduty_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalduty_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTY_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalduty_sel_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutybg_abort_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutybg_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutybg_ready_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutycomp_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutycomp_offset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_finish_side_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_init_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_initval_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_invert_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_req_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_round_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_runcount_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_signmagen_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsmout_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsmout_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompmeas_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompmeas_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompmeas_req_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompmeasout_ack_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPMEASOUT_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompmeasout_erravg_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPMEASOUT_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompmeasout_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_bg_en_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_bg_one_step_cal_en_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_finish_side_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_init_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_invert_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_req_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_round_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_runcount_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_signmagen_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeas_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeas_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeas_req_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeasout_ack_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYMEASOUT_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeasout_erravg_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYMEASOUT_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeasout_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutystat_done_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaldutystat_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalptr_pstate_duty_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalptr_pstate_dutycomp_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalptr_pstate_regopampoffset_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_duty_muxd0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_duty_muxd1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_duty_muxd2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_duty_muxd3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_duty_muxd4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_dutycomp_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_dutycomp_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_dutycomp_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_dutycomp_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_dutycomp_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_regopampoffset_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffset_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_finish_side_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_round_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_runcount_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_signmagen_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcaltclkdutyforce_div1_attr == SERDES_IP_LANE_L0_CFG_TXCALTCLKDUTYFORCE_DIV1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txcdrdiv_local_en_attr == SERDES_IP_LANE_L0_CFG_TXCDRDIV_LOCAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txclk_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txclk_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txclkgenmuxsel_txinternal_attr == SERDES_IP_LANE_L0_CFG_TXCLKGENMUXSEL_TXINTERNAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txdetectrx_thr_attr == 5'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeas_count_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeas_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXDETECTRXMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeas_locovren_attr == SERDES_IP_LANE_L0_CFG_TXDETECTRXMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeas_validdlycount_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeasin_locovren_attr == SERDES_IP_LANE_L0_CFG_TXDETECTRXMEASIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeasin_start_locovr_attr == SERDES_IP_LANE_L0_CFG_TXDETECTRXMEASIN_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeaspcs_locovren_attr == SERDES_IP_LANE_L0_CFG_TXDETECTRXMEASPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeaspcs_req_locovr_attr == SERDES_IP_LANE_L0_CFG_TXDETECTRXMEASPCS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeasval_locovren_attr == SERDES_IP_LANE_L0_CFG_TXDETECTRXMEASVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeasval_stat_locovr_attr == SERDES_IP_LANE_L0_CFG_TXDETECTRXMEASVAL_STAT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txdetrx_levn_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txdetrx_levnm1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txdetrx_levnp1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txdetrx_levnp2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txdrv_hizen_locovr_attr == SERDES_IP_LANE_L0_CFG_TXDRV_HIZEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txdrv_levn_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txdrv_levnm1_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txdrv_levnp1_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txdrv_levnp2_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txdrv_locovren_attr == SERDES_IP_LANE_L0_CFG_TXDRV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txdrv_refcken_attr == SERDES_IP_LANE_L0_CFG_TXDRV_REFCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txdrv_termref_attr == SERDES_IP_LANE_L0_CFG_TXDRV_TERMREF_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txdrvmute_locovr_attr == SERDES_IP_LANE_L0_CFG_TXDRVMUTE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txdrvmute_locovren_attr == SERDES_IP_LANE_L0_CFG_TXDRVMUTE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txduty_ctrl_disable_attr == SERDES_IP_LANE_L0_CFG_TXDUTY_CTRL_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txduty_pad_sense_en_attr == SERDES_IP_LANE_L0_CFG_TXDUTY_PAD_SENSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txdutycal_div16_en_attr == SERDES_IP_LANE_L0_CFG_TXDUTYCAL_DIV16_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txdutycal_div1_en_attr == SERDES_IP_LANE_L0_CFG_TXDUTYCAL_DIV1_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txdutycal_div2_en_attr == SERDES_IP_LANE_L0_CFG_TXDUTYCAL_DIV2_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txdutycal_div4_en_attr == SERDES_IP_LANE_L0_CFG_TXDUTYCAL_DIV4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txdutycal_div8_en_attr == SERDES_IP_LANE_L0_CFG_TXDUTYCAL_DIV8_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txfifo_elecidle_deskew_en_attr == SERDES_IP_LANE_L0_CFG_TXFIFO_ELECIDLE_DESKEW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txfifo_force_txidlebit1_zero_disable_attr == SERDES_IP_LANE_L0_CFG_TXFIFO_FORCE_TXIDLEBIT1_ZERO_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txfifo_kill_dly_10b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txfifo_kill_dly_16b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txfifo_kill_dly_20b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txfifo_kill_dly_32b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txfifo_kill_dly_40b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txfifo_kill_dly_64b_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txfifo_kill_dly_80b_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txfifo_kill_dly_8b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txfifo_kill_en_attr == SERDES_IP_LANE_L0_CFG_TXFIFO_KILL_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txfsm_cken_ovr_attr == SERDES_IP_LANE_L0_CFG_TXFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txfsm_cken_ovren_attr == SERDES_IP_LANE_L0_CFG_TXFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txfsm_main_on_state_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txl1d1_doze_ctrl_attr == SERDES_IP_LANE_L0_CFG_TXL1D1_DOZE_CTRL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txl1d1_txbias_ctrl_attr == SERDES_IP_LANE_L0_CFG_TXL1D1_TXBIAS_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txlanepam_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXLANEPAM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txlanepam_locovren_attr == SERDES_IP_LANE_L0_CFG_TXLANEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txmeaslatovrhd_meas_sel_attr == SERDES_IP_LANE_L0_CFG_TXMEASLATOVRHD_MEAS_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txmute_delay_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txntl_changeref_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txntl_changeref_val_locovr_attr == SERDES_IP_LANE_L0_CFG_TXNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txntl_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txntl_en_attr == SERDES_IP_LANE_L0_CFG_TXNTL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txntl_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txntl_locovren_attr == SERDES_IP_LANE_L0_CFG_TXNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txntl_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txntl_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txntl_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txntl_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txntl_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txntl_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txntl_txm_charge_up_locovr_attr == SERDES_IP_LANE_L0_CFG_TXNTL_TXM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txntl_txm_pull_dn_locovr_attr == SERDES_IP_LANE_L0_CFG_TXNTL_TXM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txntl_txm_sense_locovr_attr == SERDES_IP_LANE_L0_CFG_TXNTL_TXM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txntl_txp_charge_up_locovr_attr == SERDES_IP_LANE_L0_CFG_TXNTL_TXP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txntl_txp_pull_dn_locovr_attr == SERDES_IP_LANE_L0_CFG_TXNTL_TXP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txntl_txp_sense_locovr_attr == SERDES_IP_LANE_L0_CFG_TXNTL_TXP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txp2s_txwordsyncbypen_attr == SERDES_IP_LANE_L0_CFG_TXP2S_TXWORDSYNCBYPEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txpam_bitorder_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txpam_gray_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXPAM_GRAY_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txpam_locovren_attr == SERDES_IP_LANE_L0_CFG_TXPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txpam_precode_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXPAM_PRECODE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txpcs_locovren_attr == SERDES_IP_LANE_L0_CFG_TXPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txpcs_txenable_locovr_attr == SERDES_IP_LANE_L0_CFG_TXPCS_TXENABLE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txpcsbist_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXPCSBIST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txpcsbist_locovren_attr == SERDES_IP_LANE_L0_CFG_TXPCSBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txratewidth_clk_chk_disable_attr == SERDES_IP_LANE_L0_CFG_TXRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txratewidth_etr_on_delay_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txratewidth_locovren_attr == SERDES_IP_LANE_L0_CFG_TXRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txreg_toggle_pwrupacc_on_rate_change_en_attr == SERDES_IP_LANE_L0_CFG_TXREG_TOGGLE_PWRUPACC_ON_RATE_CHANGE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txreg_toggle_reset_on_rate_change_en_attr == SERDES_IP_LANE_L0_CFG_TXREG_TOGGLE_RESET_ON_RATE_CHANGE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txresetdel_sel_attr == SERDES_IP_LANE_L0_CFG_TXRESETDEL_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_en_b_attr == SERDES_IP_LANE_L0_CFG_TXRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s0q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s0q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s1q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s1q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s2q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s2q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s2q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s2q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s2q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s2q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s2q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s3q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s3q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s3q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s3q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s3q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s3q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s3q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s3q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s4q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s4q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s5q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s0q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s0q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s1q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s1q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s1q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s1q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s1q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s1q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s2q0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s2q1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s2q2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s2q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s2q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s2q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s2q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s2q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s3q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s3q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s3q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s3q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s3q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s3q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s3q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s3q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s4q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s4q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s5q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_dn_ptr0_s_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_up_ptr0_s_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_aetrtx_bitckdvdrcken_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_AETRTX_BITCKDVDRCKEN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_aetrtx_bitckdvdrcken_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_AETRTX_BITCKDVDRCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_aetrtx_regpwrupacc_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_AETRTX_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_aetrtx_regpwrupacc_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_AETRTX_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_adc_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_adc_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_drvdoze_b_ovr_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_DRVDOZE_B_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_drvdoze_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_DRVDOZE_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_duty_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_DUTY_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_duty_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_DUTY_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_ntl_b_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_ntl_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_p2s_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_P2S_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_p2s_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_P2S_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_reg_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_reg_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_arsttx_adc_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_ARSTTX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_arsttx_adc_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_ARSTTX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_arsttx_pma2pcstxword_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_ARSTTX_PMA2PCSTXWORD_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_arsttx_pma2pcstxword_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_ARSTTX_PMA2PCSTXWORD_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_arsttx_regreset_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_ARSTTX_REGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_arsttx_regreset_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_ARSTTX_REGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_arsttx_txdetectrx_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_ARSTTX_TXDETECTRX_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_arsttx_txdetectrx_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_ARSTTX_TXDETECTRX_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txrststate_hiz_en_attr == SERDES_IP_LANE_L0_CFG_TXRSTSTATE_HIZ_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txspare0_attr == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txspare_attr == 10'd384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txterm_coarse_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txtermtrim_locovren_attr == SERDES_IP_LANE_L0_CFG_TXTERMTRIM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txtermtrim_nmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txtermtrim_pmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txwclk_div_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txwclk_div_en_attr == SERDES_IP_LANE_L0_CFG_TXWCLK_DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txwclk_div_smpl_attr == SERDES_IP_LANE_L0_CFG_TXWCLK_DIV_SMPL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txwptr_init01_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txwptr_init02_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txwptr_init04_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txwptr_init08_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txwptr_init16_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txwptr_init32_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l0_cfg_txwptr_init_rx2txparlb_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_bshihyst_attr == SERDES_IP_LANE_L1_CFG_BSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_bstxdrv_levn_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_bstxdrv_levnm1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_bstxdrv_levnp1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_bstxdrv_levnp2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_calsqlchosc_locovren_attr == SERDES_IP_LANE_L1_CFG_CALSQLCHOSC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_calsqlchosc_trimcode_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_cdrclkstat_locovren_attr == SERDES_IP_LANE_L1_CFG_CDRCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_cdrclkstat_ready_locovr_attr == SERDES_IP_LANE_L1_CFG_CDRCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_etrregrxcdrclk_ready_attr == SERDES_IP_LANE_L1_CFG_ETRREGRXCDRCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_laneckm_avg_en_attr == SERDES_IP_LANE_L1_CFG_LANECKM_AVG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_laneckm_clk_en_attr == SERDES_IP_LANE_L1_CFG_LANECKM_CLK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_laneckm_continuous_attr == SERDES_IP_LANE_L1_CFG_LANECKM_CONTINUOUS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_laneckm_dig_meas_en_attr == SERDES_IP_LANE_L1_CFG_LANECKM_DIG_MEAS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_laneckm_dig_meas_err_clr_attr == SERDES_IP_LANE_L1_CFG_LANECKM_DIG_MEAS_ERR_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_laneckm_en_attr == SERDES_IP_LANE_L1_CFG_LANECKM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_laneckm_max_thr_attr == 25'd33554431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_laneckm_meas_ck_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_laneckm_ref_ck_div_ratio_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_laneckm_result_clr_attr == SERDES_IP_LANE_L1_CFG_LANECKM_RESULT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_laneckm_start_attr == SERDES_IP_LANE_L1_CFG_LANECKM_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_laneckm_wdt_interval_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_laneckm_win_thr_ref_attr == 25'd16777215
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_lanepcs_locovren_attr == SERDES_IP_LANE_L1_CFG_LANEPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_lanepcs_mode_locovr_attr == SERDES_IP_LANE_L1_CFG_LANEPCS_MODE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_laneperfmon_compare_val_start_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_laneperfmon_compare_val_stop_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_laneperfmon_en_attr == SERDES_IP_LANE_L1_CFG_LANEPERFMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_laneperfmon_mask_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_lanepmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_lanepmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_lanepmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_lanepmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_lanepmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_lanepmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_lb_cdrclk2txen_locovr_attr == SERDES_IP_LANE_L1_CFG_LB_CDRCLK2TXEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_lb_cdrclkdiven_attr == SERDES_IP_LANE_L1_CFG_LB_CDRCLKDIVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_lb_cdrdivclk2exten_attr == SERDES_IP_LANE_L1_CFG_LB_CDRDIVCLK2EXTEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_lb_cdrdivclk2txen_attr == SERDES_IP_LANE_L1_CFG_LB_CDRDIVCLK2TXEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_lb_hsclk2cdrdiven_attr == SERDES_IP_LANE_L1_CFG_LB_HSCLK2CDRDIVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_lb_locovren_attr == SERDES_IP_LANE_L1_CFG_LB_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_lb_parrx2txtimeden_locovr_attr == SERDES_IP_LANE_L1_CFG_LB_PARRX2TXTIMEDEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_lb_pllfbclk2cdrrefclken_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_lb_pllfbclk2cdrrefclken_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_lb_pllfbclk2cdrrefclken_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_lb_pllfbclk2cdrrefclken_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_lb_pllfbclk2cdrrefclken_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_lb_rx2txuntimeden_attr == SERDES_IP_LANE_L1_CFG_LB_RX2TXUNTIMEDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_lb_rxwordck2pcstxwordcken_attr == SERDES_IP_LANE_L1_CFG_LB_RXWORDCK2PCSTXWORDCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_lb_tx2rxbuftimeden_lsb_locovr_attr == SERDES_IP_LANE_L1_CFG_LB_TX2RXBUFTIMEDEN_LSB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_lb_tx2rxbuftimeden_msb_locovr_attr == SERDES_IP_LANE_L1_CFG_LB_TX2RXBUFTIMEDEN_MSB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_lb_tx2rxiotimeden_attr == SERDES_IP_LANE_L1_CFG_LB_TX2RXIOTIMEDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_lfps_det_locovr_attr == SERDES_IP_LANE_L1_CFG_LFPS_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_lfps_locovren_attr == SERDES_IP_LANE_L1_CFG_LFPS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_lfps_out_en_attr == SERDES_IP_LANE_L1_CFG_LFPS_OUT_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_pcslfps_en_locovr_attr == SERDES_IP_LANE_L1_CFG_PCSLFPS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_pcslfps_locovren_attr == SERDES_IP_LANE_L1_CFG_PCSLFPS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_pcsrx_dme_en_locovr_attr == SERDES_IP_LANE_L1_CFG_PCSRX_DME_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_pcsrx_locovren_attr == SERDES_IP_LANE_L1_CFG_PCSRX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_pcsrxbist_locovren_attr == SERDES_IP_LANE_L1_CFG_PCSRXBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_pcsrxbist_modesel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_pcstx_beaconen_locovr_attr == SERDES_IP_LANE_L1_CFG_PCSTX_BEACONEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_pcstx_locovren_attr == SERDES_IP_LANE_L1_CFG_PCSTX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_polarity_rx_attr == SERDES_IP_LANE_L1_CFG_POLARITY_RX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_polarity_tx_attr == SERDES_IP_LANE_L1_CFG_POLARITY_TX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rx_cmn_on_state_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rx_fastregpwrup_en_attr == SERDES_IP_LANE_L1_CFG_RX_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rx_frac_mode_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rx_on_state_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rx_pg_disable_attr == SERDES_IP_LANE_L1_CFG_RX_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rx_synth_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rx_synth_sel_amode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rx_synth_sel_bmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rx_synth_sel_cmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rx_synth_sel_dmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rx_synth_sel_emode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxadc_req_attr == SERDES_IP_LANE_L1_CFG_RXADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxagc_dccoupleen_attr == SERDES_IP_LANE_L1_CFG_RXAGC_DCCOUPLEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxaprobe_addr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxaprobe_lastmux_isolate_attr == SERDES_IP_LANE_L1_CFG_RXAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxaprobeadc_current_direction_attr == SERDES_IP_LANE_L1_CFG_RXAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxaprobeadc_resistor_enable_attr == SERDES_IP_LANE_L1_CFG_RXAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxbias_iccadj_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxbias_icvadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxbias_locovren_attr == SERDES_IP_LANE_L1_CFG_RXBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxbias_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxbist_burst_four_errtype_attr == SERDES_IP_LANE_L1_CFG_RXBIST_BURST_FOUR_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxbist_burst_one_errtype_attr == SERDES_IP_LANE_L1_CFG_RXBIST_BURST_ONE_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxbist_burst_three_errtype_attr == SERDES_IP_LANE_L1_CFG_RXBIST_BURST_THREE_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxbist_burst_two_errtype_attr == SERDES_IP_LANE_L1_CFG_RXBIST_BURST_TWO_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxbist_cdrlock2data_bypass_attr == SERDES_IP_LANE_L1_CFG_RXBIST_CDRLOCK2DATA_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxbist_cdrlock2data_postamble_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxbist_clear_errcount_attr == SERDES_IP_LANE_L1_CFG_RXBIST_CLEAR_ERRCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxbist_err_en_attr == SERDES_IP_LANE_L1_CFG_RXBIST_ERR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxbist_err_trig_type_attr == SERDES_IP_LANE_L1_CFG_RXBIST_ERR_TRIG_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxbist_errmask_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxbist_errtype_attr == SERDES_IP_LANE_L1_CFG_RXBIST_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxbist_firsterr_type_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxbist_lockchk_count_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxbist_maxbitcnt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxbist_mostrecent_err_attr == SERDES_IP_LANE_L1_CFG_RXBIST_MOSTRECENT_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxbist_relock_itercount_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxbist_seed_attr == 31'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxbist_status_hold_attr == SERDES_IP_LANE_L1_CFG_RXBIST_STATUS_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxbitslip_locovr_attr == SERDES_IP_LANE_L1_CFG_RXBITSLIP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxbitslip_locovren_attr == SERDES_IP_LANE_L1_CFG_RXBITSLIP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxbscan_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxbshicm_attr == SERDES_IP_LANE_L1_CFG_RXBSHICM_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalcdrfbdiv_div2_bypass_muxd0_attr == SERDES_IP_LANE_L1_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalcdrfbdiv_div2_bypass_muxd1_attr == SERDES_IP_LANE_L1_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalcdrfbdiv_div2_bypass_muxd2_attr == SERDES_IP_LANE_L1_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalcdrfbdiv_div2_bypass_muxd3_attr == SERDES_IP_LANE_L1_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalcdrfbdiv_div2_bypass_muxd4_attr == SERDES_IP_LANE_L1_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalduty_iclk_gray_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalduty_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTY_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalduty_qclk_gray_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalduty_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutybg_abort_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutybg_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutybg_ready_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycomp_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycomp_offset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_finish_side_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_init_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_initval_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_invert_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_round_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_runcount_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_signmagen_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsmout_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsmout_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_disable_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCTRL_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_i_div1_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_i_div2_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_i_div4_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_i_div8_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_q_div1_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_q_div2_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_q_div4_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_q_div8_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_bg_en_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_bg_one_step_cal_en_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_finish_side_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_i_polarity_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_I_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_i_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_I_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_init_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_q_polarity_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_Q_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_q_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_Q_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_round_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_runcount_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_signmagen_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_comp_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEAS_COMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_comp_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEAS_COMP_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_i_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEAS_I_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_i_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEAS_I_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_q_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEAS_Q_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_q_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEAS_Q_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeasout_comp_ack_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEASOUT_COMP_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeasout_comp_erravg_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEASOUT_COMP_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeasout_i_ack_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEASOUT_I_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeasout_i_erravg_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEASOUT_I_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeasout_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeasout_q_ack_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEASOUT_Q_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeasout_q_erravg_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEASOUT_Q_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutystat_done_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaldutystat_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_centerfreq_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_end_delay_attr == 9'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_hscount_muxd0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_hscount_muxd1_attr == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_hscount_muxd2_attr == 8'd180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_hscount_muxd3_attr == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_hscount_muxd4_attr == 8'd206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_initval_centerfreq_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_initval_fosc_attr == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_centerfreq_finish_side_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_CENTERFREQ_FINISH_SIDE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_centerfreq_to_fosc_offset_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_centerfreqen_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_CENTERFREQEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_centerfreqoffset_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_fosc_finishside_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_FOSC_FINISHSIDE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_foscen_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_FOSCEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_foscoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_init_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_invert_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_lpfax_calfosccoarse_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_lpfax_calfoscfine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_lpfax_centerfreqcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_lpfax_centerfreqfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_runcount_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_signmagen_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_vcorepen_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_VCOREPEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsmout_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsmout_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_count_muxd0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_count_muxd1_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_count_muxd2_attr == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_count_muxd3_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_count_muxd4_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_dlycount_attr == 9'd68
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeasout_clear_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCMEASOUT_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeasout_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeasout_start_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCMEASOUT_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscval_int_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscval_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalintsval_int_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalintsval_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALINTSVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaloffsetfsm_init_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaloffsetfsm_init_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaloffsetfsm_init_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALOFFSETFSM_INIT_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaloffsetfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcaloffsetfsmout_input_en_attr == SERDES_IP_LANE_L1_CFG_RXCALOFFSETFSMOUT_INPUT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_duty_i_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_duty_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_dutycomp_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_foscfsm_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_offsetfsm_init_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_regopampoffset_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_rxppm_lockstatus_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_sqlch_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_sqlchosc_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_synthppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_voscregopampoffset_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_duty_i_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_duty_q_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_dutycomp_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_foscfsm_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_offsetfsm_init_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_rxppm_lockstatus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_sqlch_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_sqlchosc_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_synthppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_voscregopampoffset_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffset_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_finish_side_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_round_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_runcount_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_signmagen_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchfsm_clear_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchfsm_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchfsmout_caldone_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHFSMOUT_CALDONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchfsmout_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_codeoffset_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_finish_side_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHOSCFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_init_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHOSCFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_initval_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_invert_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHOSCFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHOSCFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHOSCFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_round_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHOSCFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_runcount_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHOSCFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscmeas_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHOSCMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscmeas_ref_cnt_attr == 10'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscmeas_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHOSCMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscmeas_settle_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscmeas_smpl_cnt_attr == 10'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvbiascap_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALVBIASCAP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvbiascap_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALVBIASCAP_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvcoopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvcoopampoffsetmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvcoopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvcoopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffset_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffset_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_codeoffset_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_finish_side_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_initval_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_invert_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_lpfaxcoarse_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_round_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_runcount_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETFSM_RUNCOUNT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_signmagen_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsmout_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsmout_runcount_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETFSMOUT_RUNCOUNT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetmeas_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffset_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALVOSCREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALVOSCREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L1_CFG_RXCALVOSCREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALVOSCREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALVOSCREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALVOSCREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALVOSCREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALVOSCREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALVOSCREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrdiv_local_en_attr == SERDES_IP_LANE_L1_CFG_RXCDRDIV_LOCAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdiv_moddiv_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdiv_moddiv_muxd1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdiv_moddiv_muxd2_attr == 4'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdiv_moddiv_muxd3_attr == 4'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdiv_moddiv_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdivslip_mdiv_muxd0_attr == 9'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdivslip_mdiv_muxd1_attr == 9'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdivslip_mdiv_muxd2_attr == 9'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdivslip_mdiv_muxd3_attr == 9'd66
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdivslip_mdiv_muxd4_attr == 9'd210
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrpfd_forcedn_attr == SERDES_IP_LANE_L1_CFG_RXCDRPFD_FORCEDN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrpfd_forceen_attr == SERDES_IP_LANE_L1_CFG_RXCDRPFD_FORCEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrpfd_forceup_attr == SERDES_IP_LANE_L1_CFG_RXCDRPFD_FORCEUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrpfd_propgain_attr == SERDES_IP_LANE_L1_CFG_RXCDRPFD_PROPGAIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrpfd_pulsewidth_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrphd_asym_override_ignore_attr == SERDES_IP_LANE_L1_CFG_RXCDRPHD_ASYM_OVERRIDE_IGNORE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrphd_bitshift_en_attr == SERDES_IP_LANE_L1_CFG_RXCDRPHD_BITSHIFT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrphd_forcedn_attr == SERDES_IP_LANE_L1_CFG_RXCDRPHD_FORCEDN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrphd_forceen_attr == SERDES_IP_LANE_L1_CFG_RXCDRPHD_FORCEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrphd_forceup_attr == SERDES_IP_LANE_L1_CFG_RXCDRPHD_FORCEUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrphdrate_doublerate2s2p_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCDRPHDRATE_DOUBLERATE2S2P_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrphdrate_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCDRPHDRATE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrrefck_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrrefck_refdiv_muxd1_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrrefck_refdiv_muxd2_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrrefck_refdiv_muxd3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrrefck_refdiv_muxd4_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_biastop_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_biastopbypass_attr == SERDES_IP_LANE_L1_CFG_RXCDRVCO_BIASTOPBYPASS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_datapropgain_high_attr == 5'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_datapropgain_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_datapropgain_low_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_ff_ovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_ff_ovr_en_attr == SERDES_IP_LANE_L1_CFG_RXCDRVCO_FF_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_fil_short_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_flickerdegen_attr == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_gmfoscshort_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCDRVCO_GMFOSCSHORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_intf_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_intf_fil_short_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_intrj_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCDRVCO_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_refpropgain_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_refpropgain_nom_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxclk_cdrfb_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCLK_CDRFB_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxclk_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxclk_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdat_nrz_64b80b_bcword_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdata_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXDATA_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdata_locovren_attr == SERDES_IP_LANE_L1_CFG_RXDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdatapath_locovren_attr == SERDES_IP_LANE_L1_CFG_RXDATAPATH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdatapath_on_state_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdatapath_ready_locovr_attr == SERDES_IP_LANE_L1_CFG_RXDATAPATH_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdfe_datatap_vcasc_attr == 4'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdfe_dfebiasadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdfe_nbiasctle_en_attr == SERDES_IP_LANE_L1_CFG_RXDFE_NBIASCTLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdfe_vcasc_sel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdfeterm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXDFETERM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdfeterm_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdfeyadjdac_datamid_edge_coarse_en_attr == SERDES_IP_LANE_L1_CFG_RXDFEYADJDAC_DATAMID_EDGE_COARSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdfeyadjdac_datatopbot_aux_coarse_en_attr == SERDES_IP_LANE_L1_CFG_RXDFEYADJDAC_DATATOPBOT_AUX_COARSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_accum_mon_en_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_ACCUM_MON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_accum_mon_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_bypasscdrpdetupdnsmpl_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_bypassenfosc_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_BYPASSENFOSC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_bypassenints_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_BYPASSENINTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_bypassenupdnsmpl_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_BYPASSENUPDNSMPL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_bypassfosc_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_bypasspllpfdupdnsmpl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_bypassrxints_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_data2pll_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_deltasigmode_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_DELTASIGMODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_fastref_muxd0_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_FASTREF_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_fastref_muxd1_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_FASTREF_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_fastref_muxd2_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_FASTREF_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_fastref_muxd3_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_FASTREF_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_fastref_muxd4_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_FASTREF_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_fosc_mod_bypass_en_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_FOSC_MOD_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_fosc_sample_pedge_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_FOSC_SAMPLE_PEDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gain_step_on_lock_recovery_en_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_GAIN_STEP_ON_LOCK_RECOVERY_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gaindelaycount_init_attr == 9'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gaindelaycount_pow2_muxd0_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gaindelaycount_pow2_muxd1_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gaindelaycount_pow2_muxd2_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gaindelaycount_pow2_muxd3_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gaindelaycount_pow2_muxd4_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2ref_pow2_muxd0_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2ref_pow2_muxd1_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2ref_pow2_muxd2_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2ref_pow2_muxd3_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2ref_pow2_muxd4_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainunlocked_pow2_muxd0_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainunlocked_pow2_muxd1_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainunlocked_pow2_muxd2_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainunlocked_pow2_muxd3_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainunlocked_pow2_muxd4_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_initintegrator_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_INITINTEGRATOR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_initmodulator_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_INITMODULATOR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_deltasig_mode_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_INTS_DELTASIG_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_freeze_en_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_INTS_FREEZE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gaindelaycount_pow2_muxd0_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gaindelaycount_pow2_muxd1_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gaindelaycount_pow2_muxd2_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gaindelaycount_pow2_muxd3_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gaindelaycount_pow2_muxd4_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd0_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd1_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd2_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd3_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd4_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd0_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd1_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd2_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd3_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd4_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainunlocked_pow2_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainunlocked_pow2_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainunlocked_pow2_muxd2_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainunlocked_pow2_muxd3_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainunlocked_pow2_muxd4_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_guardband_hi_attr == 8'd200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_guardband_lo_attr == 8'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_loop_sel_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_INTS_LOOP_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_mod_bypass_en_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_INTS_MOD_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_mod_load_pedge_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_INTS_MOD_LOAD_PEDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_step_to_integer_en_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_INTS_STEP_TO_INTEGER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_jit_length_attr == 18'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_jit_mode_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_JIT_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_modck_ctrl_en_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_MODCK_CTRL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_pll2data_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_restore_cntr_attr == 9'd258
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_store_cntr_attr == 16'd258
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpif_trnsfrdelay_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpiffreeze_inten_attr == SERDES_IP_LANE_L1_CFG_RXDPIFFREEZE_INTEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdpiffreeze_moden_attr == SERDES_IP_LANE_L1_CFG_RXDPIFFREEZE_MODEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxdutyselpolarity_attr == SERDES_IP_LANE_L1_CFG_RXDUTYSELPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxflxgate_force_rxeq_gate_locovr_attr == SERDES_IP_LANE_L1_CFG_RXFLXGATE_FORCE_RXEQ_GATE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxflxgate_locovren_attr == SERDES_IP_LANE_L1_CFG_RXFLXGATE_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxfoscstat_done_locovr_attr == SERDES_IP_LANE_L1_CFG_RXFOSCSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxfoscstat_locovren_attr == SERDES_IP_LANE_L1_CFG_RXFOSCSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxfsm_cken_ovr_attr == SERDES_IP_LANE_L1_CFG_RXFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxfsm_cken_ovren_attr == SERDES_IP_LANE_L1_CFG_RXFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxints_prev_votes_hold_en_attr == SERDES_IP_LANE_L1_CFG_RXINTS_PREV_VOTES_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxlanepam_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXLANEPAM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxlanepam_locovren_attr == SERDES_IP_LANE_L1_CFG_RXLANEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxlock2datatmr_attr == 8'd240
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxlock2datatmr_short_attr == 8'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxntl_changeref_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxntl_changeref_val_locovr_attr == SERDES_IP_LANE_L1_CFG_RXNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxntl_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxntl_en_attr == SERDES_IP_LANE_L1_CFG_RXNTL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxntl_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxntl_locovren_attr == SERDES_IP_LANE_L1_CFG_RXNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxntl_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxntl_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxntl_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxntl_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxntl_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxntl_rxm_charge_up_locovr_attr == SERDES_IP_LANE_L1_CFG_RXNTL_RXM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxntl_rxm_pull_dn_locovr_attr == SERDES_IP_LANE_L1_CFG_RXNTL_RXM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxntl_rxm_sense_locovr_attr == SERDES_IP_LANE_L1_CFG_RXNTL_RXM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxntl_rxp_charge_up_locovr_attr == SERDES_IP_LANE_L1_CFG_RXNTL_RXP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxntl_rxp_pull_dn_locovr_attr == SERDES_IP_LANE_L1_CFG_RXNTL_RXP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxntl_rxp_sense_locovr_attr == SERDES_IP_LANE_L1_CFG_RXNTL_RXP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxntl_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_acc_freeze_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_ACC_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_cdrlock2data_gater_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_cdrlock2data_gater_hold_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_cdrlock2data_gater_ovrd_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_cdrlock2datatmr_optcl_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_cdrlock2datatmr_optcl_sel_ovrd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_enter_lock2data_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_ENTER_LOCK2DATA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_enter_lock2data_hold_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_ENTER_LOCK2DATA_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_exit_lock2data_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_EXIT_LOCK2DATA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_exit_lock2data_hold_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_EXIT_LOCK2DATA_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_force_lock2data_ovrd_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_FORCE_LOCK2DATA_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_force_lock2ref_ovrd_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_FORCE_LOCK2REF_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_hold_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_hold_timer_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_intf_ovrd_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_INTF_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_intf_ovrd_type_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_INTF_OVRD_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_mod_freeze_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_MOD_FREEZE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_ovrd_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_ppm_detect_freeze_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_PPM_DETECT_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_ppm_detect_freeze_ovrd_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_PPM_DETECT_FREEZE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_ppm_detect_hold_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_PPM_DETECT_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_prop_freeze_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_PROP_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_prop_freeze_ovrd_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_PROP_FREEZE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_rxdata_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_RXDATA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_skip_init_lock2data_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_SKIP_INIT_LOCK2DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxpam_bitorder_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxpam_gray_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXPAM_GRAY_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxpam_locovren_attr == SERDES_IP_LANE_L1_CFG_RXPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxpam_precode_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXPAM_PRECODE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_p5_muxd0_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIV_P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_p5_muxd1_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIV_P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_p5_muxd2_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIV_P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_p5_muxd3_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIV_P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_p5_muxd4_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIV_P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdivclken_muxd0_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIVCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdivclken_muxd1_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIVCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdivclken_muxd2_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIVCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdivclken_muxd3_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIVCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdivclken_muxd4_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIVCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxpcsbist_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXPCSBIST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxpcsbist_locovren_attr == SERDES_IP_LANE_L1_CFG_RXPCSBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxphd_gain_hold_en_attr == SERDES_IP_LANE_L1_CFG_RXPHD_GAIN_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxphd_gain_zero_locovr_attr == SERDES_IP_LANE_L1_CFG_RXPHD_GAIN_ZERO_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxphd_locovren_attr == SERDES_IP_LANE_L1_CFG_RXPHD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxphd_majvote_basegain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxphd_majvote_en_attr == SERDES_IP_LANE_L1_CFG_RXPHD_MAJVOTE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxphd_mute_cntr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxphd_nrz8b10b_pam16b20b_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxphd_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxphd_pam_transition_sel_attr == SERDES_IP_LANE_L1_CFG_RXPHD_PAM_TRANSITION_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxphd_sign_invert_attr == SERDES_IP_LANE_L1_CFG_RXPHD_SIGN_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxpostdiv_wait_for_lock_disable_attr == SERDES_IP_LANE_L1_CFG_RXPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxppm_freq_max_offset_h_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxppm_freq_max_offset_l_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxppm_freq_ref_cnt_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxppm_lockstatus_locovr_attr == SERDES_IP_LANE_L1_CFG_RXPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxppm_lockstatus_synthlcfast_en_attr == SERDES_IP_LANE_L1_CFG_RXPPM_LOCKSTATUS_SYNTHLCFAST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxppm_lockstatus_synthlcmed_en_attr == SERDES_IP_LANE_L1_CFG_RXPPM_LOCKSTATUS_SYNTHLCMED_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxppm_lockstatus_synthlcslow_en_attr == SERDES_IP_LANE_L1_CFG_RXPPM_LOCKSTATUS_SYNTHLCSLOW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxppm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxppm_ppmdriftcount_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxppm_ppmdriftmax_attr == 16'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxppm_status_hold_attr == SERDES_IP_LANE_L1_CFG_RXPPM_STATUS_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxppm_unlock_clear_attr == SERDES_IP_LANE_L1_CFG_RXPPM_UNLOCK_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_fast_muxd0_attr == 16'd666
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_fast_muxd1_attr == 16'd4000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_fast_muxd2_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_fast_muxd3_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_fast_muxd4_attr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_muxd0_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_muxd1_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_muxd2_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_muxd3_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_muxd4_attr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxppmctrl_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXPPMCTRL_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxppmctrl_locovren_attr == SERDES_IP_LANE_L1_CFG_RXPPMCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxppmlockstat_locovren_attr == SERDES_IP_LANE_L1_CFG_RXPPMLOCKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxppmlockstat_sticky_locovr_attr == SERDES_IP_LANE_L1_CFG_RXPPMLOCKSTAT_STICKY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxppmtmr_locovren_attr == SERDES_IP_LANE_L1_CFG_RXPPMTMR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxppmtmr_watchdogtmr_sel_locovr_attr == SERDES_IP_LANE_L1_CFG_RXPPMTMR_WATCHDOGTMR_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_cal_clear_delay_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_clk_chk_disable_attr == SERDES_IP_LANE_L1_CFG_RXRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_clk_delay_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_etr_on_delay_attr == 12'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_locovren_attr == SERDES_IP_LANE_L1_CFG_RXRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxreg_lev_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxreg_toggle_reset_on_rate_change_en_attr == SERDES_IP_LANE_L1_CFG_RXREG_TOGGLE_RESET_ON_RATE_CHANGE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxreg_vreg_bypass_attr == SERDES_IP_LANE_L1_CFG_RXREG_VREG_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_en_b_attr == SERDES_IP_LANE_L1_CFG_RXRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s0q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s0q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s2q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s2q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s2q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s2q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s2q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s2q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s2q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s3q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s3q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s3q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s3q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s3q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s3q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s3q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s3q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s4q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s4q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s5q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_entry2_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_entry4_attr == 13'd78
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_entry5_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_entry6_attr == 13'd1406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s0q2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s0q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s1q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s1q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s1q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s1q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s1q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s1q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s2q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s2q2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s2q3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s2q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s2q5_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s2q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s2q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s3q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s3q1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s3q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s3q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s3q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s3q5_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s3q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s3q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s4q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s4q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s5q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_aetrrx_cdrfbdivcken_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_AETRRX_CDRFBDIVCKEN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_aetrrx_cdrfbdivcken_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_AETRRX_CDRFBDIVCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_aetrrx_cdrmoddivcken_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_AETRRX_CDRMODDIVCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_aetrrx_cdrmoddivcken_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_AETRRX_CDRMODDIVCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_aetrrx_termhiz_en_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_AETRRX_TERMHIZ_EN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_aetrrx_termhiz_en_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_AETRRX_TERMHIZ_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_aetrsynth_pcspostdivclksel_ovr_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_AETRSYNTH_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_aetrsynth_pcspostdivclksel_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_AETRSYNTH_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_adc_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_adc_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_auxcomp_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_AUXCOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_auxcomp_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_AUXCOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_bias_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_bias_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_BIAS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_ctlecomp_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_CTLECOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_ctlecomp_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_CTLECOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_datfbdiv_b_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DATFBDIV_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_datfbdiv_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DATFBDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_dfe_bias_b_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DFE_BIAS_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_dfe_bias_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DFE_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_dfe_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DFE_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_dfe_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DFE_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_dfe_yadj_b_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DFE_YADJ_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_dfe_yadj_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DFE_YADJ_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_duty_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DUTY_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_duty_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DUTY_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_hifreqagc_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_HIFREQAGC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_hifreqagc_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_HIFREQAGC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_ntl_b_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_ntl_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_reg_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_reg_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_vco_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_VCO_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_vco_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_VCO_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_voscreg_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_VOSCREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_voscreg_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_VOSCREG_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_adc_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_adc_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_cdrfbdiv_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_CDRFBDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_cdrfbdiv_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_CDRFBDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_pdet_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_PDET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_pdet_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_PDET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_pfd_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_PFD_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_pfd_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_PFD_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_refdiv_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_refdiv_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_reg_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_reg_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_s2pa_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_S2PA_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_s2pa_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_S2PA_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_s2pb_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_S2PB_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_s2pb_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_S2PB_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_vco_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_VCO_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_vco_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_VCO_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_voscreg_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_VOSCREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_voscreg_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_VOSCREG_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstsynth_postdiv_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTSYNTH_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstsynth_postdiv_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTSYNTH_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_drstrx_dpif_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_DRSTRX_DPIF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_drstrx_dpif_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_DRSTRX_DPIF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_drstrx_ppm_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_DRSTRX_PPM_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_drstrx_ppm_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_DRSTRX_PPM_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_cdrlock2data_locovr_attr == SERDES_IP_LANE_L1_CFG_RXSIGDET_CDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_diglfpsdeten_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_diglfpsdeten_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_diglfpsdeten_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_diglfpsdeten_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_diglfpsdeten_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrancnten_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrancnten_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrancnten_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrancnten_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrancnten_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrancnten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrandeten_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrandeten_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrandeten_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrandeten_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrandeten_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrandeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_eiosdeten_muxd0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_eiosdeten_muxd1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_eiosdeten_muxd2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_eiosdeten_muxd3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_eiosdeten_muxd4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_eiosdeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_enable_attr == SERDES_IP_LANE_L1_CFG_RXSIGDET_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_fastlock_winsize_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_leveldeten_muxd0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_leveldeten_muxd1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_leveldeten_muxd2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_leveldeten_muxd3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_leveldeten_muxd4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_leveldeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_lfpsexit_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_locovren_attr == SERDES_IP_LANE_L1_CFG_RXSIGDET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_ppmdeten_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_ppmdeten_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_ppmdeten_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_ppmdeten_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_ppmdeten_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_ppmdeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_rxeq_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_rxeqen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_rxeqen_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_rxleveldet_debounce_dncount_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_rxleveldet_debounce_flush_en_attr == SERDES_IP_LANE_L1_CFG_RXSIGDET_RXLEVELDET_DEBOUNCE_FLUSH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_rxleveldet_debounce_upcount_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_sigdet_debounce_attr == SERDES_IP_LANE_L1_CFG_RXSIGDET_SIGDET_DEBOUNCE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_tmr_clksel_attr == SERDES_IP_LANE_L1_CFG_RXSIGDET_TMR_CLKSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_toggle_count_en_attr == SERDES_IP_LANE_L1_CFG_RXSIGDET_TOGGLE_COUNT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_toggle_count_pause_attr == SERDES_IP_LANE_L1_CFG_RXSIGDET_TOGGLE_COUNT_PAUSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_toggle_monitor_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdetin_eiosdetectstat_locovr_attr == SERDES_IP_LANE_L1_CFG_RXSIGDETIN_EIOSDETECTSTAT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdetin_locovren_attr == SERDES_IP_LANE_L1_CFG_RXSIGDETIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdetin_ovrcdrlock2data_locovr_attr == SERDES_IP_LANE_L1_CFG_RXSIGDETIN_OVRCDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdetin_ovrencdrlock2data_locovr_attr == SERDES_IP_LANE_L1_CFG_RXSIGDETIN_OVRENCDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdetout_lock2data_noforce_ltr_locovr_attr == SERDES_IP_LANE_L1_CFG_RXSIGDETOUT_LOCK2DATA_NOFORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsigdetout_locovren_attr == SERDES_IP_LANE_L1_CFG_RXSIGDETOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxspare0_attr == 32'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxspare_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsqlchlfps_consec_one_thresh_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsqlchlfps_consec_zero_thresh_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsqlchlfps_cycle_thresh_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsqlchlfps_dat_bitorder_attr == SERDES_IP_LANE_L1_CFG_RXSQLCHLFPS_DAT_BITORDER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsqlchlfps_debounce_type_attr == SERDES_IP_LANE_L1_CFG_RXSQLCHLFPS_DEBOUNCE_TYPE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsqlchlfps_one_run_length_thresh_attr == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsqlchlfps_one_run_length_timeout_attr == 8'd103
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsqlchlfps_zero_run_length_thresh_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsqlchlfps_zero_run_length_timeout_attr == 8'd103
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsynthdiv_slowmed_en_muxd0_attr == SERDES_IP_LANE_L1_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsynthdiv_slowmed_en_muxd1_attr == SERDES_IP_LANE_L1_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsynthdiv_slowmed_en_muxd2_attr == SERDES_IP_LANE_L1_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsynthdiv_slowmed_en_muxd3_attr == SERDES_IP_LANE_L1_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxsynthdiv_slowmed_en_muxd4_attr == SERDES_IP_LANE_L1_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxterm_cal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxterm_coarse_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxterm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXTERM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxterm_modeselect_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxtermhiz_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXTERMHIZ_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxtermhiz_locovren_attr == SERDES_IP_LANE_L1_CFG_RXTERMHIZ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxvoscreg_bypass_vosc_attr == SERDES_IP_LANE_L1_CFG_RXVOSCREG_BYPASS_VOSC_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxvoscregopampoffsetctrl_sel_attr == SERDES_IP_LANE_L1_CFG_RXVOSCREGOPAMPOFFSETCTRL_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxvoscregopampoffseterr_locovren_attr == SERDES_IP_LANE_L1_CFG_RXVOSCREGOPAMPOFFSETERR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxvoscregopampoffseterr_sel_locovr_attr == SERDES_IP_LANE_L1_CFG_RXVOSCREGOPAMPOFFSETERR_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxvoscregvref_locovren_attr == SERDES_IP_LANE_L1_CFG_RXVOSCREGVREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_rxvoscregvref_sel_locovr_attr == SERDES_IP_LANE_L1_CFG_RXVOSCREGVREF_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlch_acqgain_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlch_acqtime_attr == 13'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlch_cal_quiet_locovr_attr == SERDES_IP_LANE_L1_CFG_SQLCH_CAL_QUIET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlch_cal_sel_locovr_attr == SERDES_IP_LANE_L1_CFG_SQLCH_CAL_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlch_calctrl_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlch_calen_locovr_attr == SERDES_IP_LANE_L1_CFG_SQLCH_CALEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlch_caltimer_attr == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlch_clkgate_locovr_attr == SERDES_IP_LANE_L1_CFG_SQLCH_CLKGATE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlch_cmshiften_attr == SERDES_IP_LANE_L1_CFG_SQLCH_CMSHIFTEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_acq_gain_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_acq_pct_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_cal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_clr_errlog_attr == SERDES_IP_LANE_L1_CFG_SQLCH_CONT_CLR_ERRLOG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_controller_mode_attr == SERDES_IP_LANE_L1_CFG_SQLCH_CONT_CONTROLLER_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_dis_attr == SERDES_IP_LANE_L1_CFG_SQLCH_CONT_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_pause_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_postcal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_precal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_quiet_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlch_lfps_en_attr == SERDES_IP_LANE_L1_CFG_SQLCH_LFPS_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlch_locovren_attr == SERDES_IP_LANE_L1_CFG_SQLCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlch_ovrd_val_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlch_pkdet_freqsel_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlch_polarity_attr == SERDES_IP_LANE_L1_CFG_SQLCH_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlch_rdacen_attr == SERDES_IP_LANE_L1_CFG_SQLCH_RDACEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlch_thresh_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlch_time_out_attr == 16'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlch_vrefsel0_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlch_vrefsel1_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlch_vrefsel_ovr_en_attr == SERDES_IP_LANE_L1_CFG_SQLCH_VREFSEL_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlchdeb_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlchdeb_deb_cnt_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlchdeb_deb_status_cnt_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlchdeb_en_attr == SERDES_IP_LANE_L1_CFG_SQLCHDEB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlchdeb_ign_cnt_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlchdeb_sigdet_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlchdeb_thresh_cnt_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlchdebout_exit_good_debounced_locovr_attr == SERDES_IP_LANE_L1_CFG_SQLCHDEBOUT_EXIT_GOOD_DEBOUNCED_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlchdebout_exit_good_debounced_status_locovr_attr == SERDES_IP_LANE_L1_CFG_SQLCHDEBOUT_EXIT_GOOD_DEBOUNCED_STATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlchdebout_exit_good_locovr_attr == SERDES_IP_LANE_L1_CFG_SQLCHDEBOUT_EXIT_GOOD_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_sqlchdebout_locovren_attr == SERDES_IP_LANE_L1_CFG_SQLCHDEBOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_trancnt_off_attr == 10'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_trancnt_on_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_trancntout_det_locovr_attr == SERDES_IP_LANE_L1_CFG_TRANCNTOUT_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_trancntout_locovren_attr == SERDES_IP_LANE_L1_CFG_TRANCNTOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_trandet_ax_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_trandet_ay_attr == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_trandet_off_h_attr == 6'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_trandet_off_l_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_trandet_on_h_attr == 6'd39
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_trandet_on_l_attr == 6'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_trandetout_det_locovr_attr == SERDES_IP_LANE_L1_CFG_TRANDETOUT_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_trandetout_locovren_attr == SERDES_IP_LANE_L1_CFG_TRANDETOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_tx2rxlb_en_attr == SERDES_IP_LANE_L1_CFG_TX2RXLB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_tx2rxlb_init_offset_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_tx_cmn_on_state_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_tx_fastregpwrup_en_attr == SERDES_IP_LANE_L1_CFG_TX_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_tx_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_tx_pg_disable_attr == SERDES_IP_LANE_L1_CFG_TX_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_tx_synth_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_tx_synth_sel_amode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_tx_synth_sel_bmode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_tx_synth_sel_cmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_tx_synth_sel_dmode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_tx_synth_sel_emode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_tx_txdetrx_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txadc_req_attr == SERDES_IP_LANE_L1_CFG_TXADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txaprobe_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txaprobe_lastmux_isolate_attr == SERDES_IP_LANE_L1_CFG_TXAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txaprobeadc_current_direction_attr == SERDES_IP_LANE_L1_CFG_TXAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txaprobeadc_resistor_enable_attr == SERDES_IP_LANE_L1_CFG_TXAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txbdvdr_pma2pcstxworden_attr == SERDES_IP_LANE_L1_CFG_TXBDVDR_PMA2PCSTXWORDEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txbeacon_div_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txbeacon_sel_attr == SERDES_IP_LANE_L1_CFG_TXBEACON_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txbias_icc20uadj_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txbias_icc80uadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txbias_locovren_attr == SERDES_IP_LANE_L1_CFG_TXBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txbias_termcal_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txbist_biterror_en_attr == SERDES_IP_LANE_L1_CFG_TXBIST_BITERROR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txbist_locovren_attr == SERDES_IP_LANE_L1_CFG_TXBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txbist_modesel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txbist_oobmode_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txbist_oobtburst_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txbist_oobtcomrstinit_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txbist_oobtcomsas_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txbist_oobtcomwake_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txbist_seed_attr == 31'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_size_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf00_attr == 32'd1985229328
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf01_attr == 32'd4275878552
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf02_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf03_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf04_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf05_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf06_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf07_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf08_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf09_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txbit_select_muxd0_attr == SERDES_IP_LANE_L1_CFG_TXBIT_SELECT_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txbit_select_muxd1_attr == SERDES_IP_LANE_L1_CFG_TXBIT_SELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txbit_select_muxd2_attr == SERDES_IP_LANE_L1_CFG_TXBIT_SELECT_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txbit_select_muxd3_attr == SERDES_IP_LANE_L1_CFG_TXBIT_SELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txbit_select_muxd4_attr == SERDES_IP_LANE_L1_CFG_TXBIT_SELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txbti_data_replication_attr == SERDES_IP_LANE_L1_CFG_TXBTI_DATA_REPLICATION_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txbti_tx_idle_data_en_attr == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcal_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcal_tclkduty_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalduty_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalduty_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTY_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalduty_sel_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutybg_abort_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutybg_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutybg_ready_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutycomp_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutycomp_offset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_finish_side_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_init_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_initval_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_invert_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_req_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_round_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_runcount_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_signmagen_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsmout_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsmout_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompmeas_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompmeas_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompmeas_req_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompmeasout_ack_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPMEASOUT_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompmeasout_erravg_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPMEASOUT_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompmeasout_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_bg_en_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_bg_one_step_cal_en_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_finish_side_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_init_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_invert_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_req_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_round_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_runcount_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_signmagen_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeas_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeas_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeas_req_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeasout_ack_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYMEASOUT_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeasout_erravg_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYMEASOUT_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeasout_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutystat_done_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaldutystat_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalptr_pstate_duty_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalptr_pstate_dutycomp_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalptr_pstate_regopampoffset_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_duty_muxd0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_duty_muxd1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_duty_muxd2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_duty_muxd3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_duty_muxd4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_dutycomp_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_dutycomp_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_dutycomp_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_dutycomp_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_dutycomp_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_regopampoffset_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffset_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_finish_side_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_round_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_runcount_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_signmagen_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcaltclkdutyforce_div1_attr == SERDES_IP_LANE_L1_CFG_TXCALTCLKDUTYFORCE_DIV1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txcdrdiv_local_en_attr == SERDES_IP_LANE_L1_CFG_TXCDRDIV_LOCAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txclk_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txclk_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txclkgenmuxsel_txinternal_attr == SERDES_IP_LANE_L1_CFG_TXCLKGENMUXSEL_TXINTERNAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txdetectrx_thr_attr == 5'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeas_count_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeas_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXDETECTRXMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeas_locovren_attr == SERDES_IP_LANE_L1_CFG_TXDETECTRXMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeas_validdlycount_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeasin_locovren_attr == SERDES_IP_LANE_L1_CFG_TXDETECTRXMEASIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeasin_start_locovr_attr == SERDES_IP_LANE_L1_CFG_TXDETECTRXMEASIN_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeaspcs_locovren_attr == SERDES_IP_LANE_L1_CFG_TXDETECTRXMEASPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeaspcs_req_locovr_attr == SERDES_IP_LANE_L1_CFG_TXDETECTRXMEASPCS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeasval_locovren_attr == SERDES_IP_LANE_L1_CFG_TXDETECTRXMEASVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeasval_stat_locovr_attr == SERDES_IP_LANE_L1_CFG_TXDETECTRXMEASVAL_STAT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txdetrx_levn_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txdetrx_levnm1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txdetrx_levnp1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txdetrx_levnp2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txdrv_hizen_locovr_attr == SERDES_IP_LANE_L1_CFG_TXDRV_HIZEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txdrv_levn_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txdrv_levnm1_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txdrv_levnp1_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txdrv_levnp2_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txdrv_locovren_attr == SERDES_IP_LANE_L1_CFG_TXDRV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txdrv_refcken_attr == SERDES_IP_LANE_L1_CFG_TXDRV_REFCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txdrv_termref_attr == SERDES_IP_LANE_L1_CFG_TXDRV_TERMREF_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txdrvmute_locovr_attr == SERDES_IP_LANE_L1_CFG_TXDRVMUTE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txdrvmute_locovren_attr == SERDES_IP_LANE_L1_CFG_TXDRVMUTE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txduty_ctrl_disable_attr == SERDES_IP_LANE_L1_CFG_TXDUTY_CTRL_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txduty_pad_sense_en_attr == SERDES_IP_LANE_L1_CFG_TXDUTY_PAD_SENSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txdutycal_div16_en_attr == SERDES_IP_LANE_L1_CFG_TXDUTYCAL_DIV16_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txdutycal_div1_en_attr == SERDES_IP_LANE_L1_CFG_TXDUTYCAL_DIV1_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txdutycal_div2_en_attr == SERDES_IP_LANE_L1_CFG_TXDUTYCAL_DIV2_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txdutycal_div4_en_attr == SERDES_IP_LANE_L1_CFG_TXDUTYCAL_DIV4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txdutycal_div8_en_attr == SERDES_IP_LANE_L1_CFG_TXDUTYCAL_DIV8_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txfifo_elecidle_deskew_en_attr == SERDES_IP_LANE_L1_CFG_TXFIFO_ELECIDLE_DESKEW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txfifo_force_txidlebit1_zero_disable_attr == SERDES_IP_LANE_L1_CFG_TXFIFO_FORCE_TXIDLEBIT1_ZERO_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txfifo_kill_dly_10b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txfifo_kill_dly_16b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txfifo_kill_dly_20b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txfifo_kill_dly_32b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txfifo_kill_dly_40b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txfifo_kill_dly_64b_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txfifo_kill_dly_80b_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txfifo_kill_dly_8b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txfifo_kill_en_attr == SERDES_IP_LANE_L1_CFG_TXFIFO_KILL_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txfsm_cken_ovr_attr == SERDES_IP_LANE_L1_CFG_TXFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txfsm_cken_ovren_attr == SERDES_IP_LANE_L1_CFG_TXFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txfsm_main_on_state_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txl1d1_doze_ctrl_attr == SERDES_IP_LANE_L1_CFG_TXL1D1_DOZE_CTRL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txl1d1_txbias_ctrl_attr == SERDES_IP_LANE_L1_CFG_TXL1D1_TXBIAS_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txlanepam_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXLANEPAM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txlanepam_locovren_attr == SERDES_IP_LANE_L1_CFG_TXLANEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txmeaslatovrhd_meas_sel_attr == SERDES_IP_LANE_L1_CFG_TXMEASLATOVRHD_MEAS_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txmute_delay_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txntl_changeref_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txntl_changeref_val_locovr_attr == SERDES_IP_LANE_L1_CFG_TXNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txntl_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txntl_en_attr == SERDES_IP_LANE_L1_CFG_TXNTL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txntl_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txntl_locovren_attr == SERDES_IP_LANE_L1_CFG_TXNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txntl_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txntl_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txntl_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txntl_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txntl_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txntl_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txntl_txm_charge_up_locovr_attr == SERDES_IP_LANE_L1_CFG_TXNTL_TXM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txntl_txm_pull_dn_locovr_attr == SERDES_IP_LANE_L1_CFG_TXNTL_TXM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txntl_txm_sense_locovr_attr == SERDES_IP_LANE_L1_CFG_TXNTL_TXM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txntl_txp_charge_up_locovr_attr == SERDES_IP_LANE_L1_CFG_TXNTL_TXP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txntl_txp_pull_dn_locovr_attr == SERDES_IP_LANE_L1_CFG_TXNTL_TXP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txntl_txp_sense_locovr_attr == SERDES_IP_LANE_L1_CFG_TXNTL_TXP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txp2s_txwordsyncbypen_attr == SERDES_IP_LANE_L1_CFG_TXP2S_TXWORDSYNCBYPEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txpam_bitorder_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txpam_gray_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXPAM_GRAY_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txpam_locovren_attr == SERDES_IP_LANE_L1_CFG_TXPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txpam_precode_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXPAM_PRECODE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txpcs_locovren_attr == SERDES_IP_LANE_L1_CFG_TXPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txpcs_txenable_locovr_attr == SERDES_IP_LANE_L1_CFG_TXPCS_TXENABLE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txpcsbist_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXPCSBIST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txpcsbist_locovren_attr == SERDES_IP_LANE_L1_CFG_TXPCSBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txratewidth_clk_chk_disable_attr == SERDES_IP_LANE_L1_CFG_TXRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txratewidth_etr_on_delay_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txratewidth_locovren_attr == SERDES_IP_LANE_L1_CFG_TXRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txreg_toggle_pwrupacc_on_rate_change_en_attr == SERDES_IP_LANE_L1_CFG_TXREG_TOGGLE_PWRUPACC_ON_RATE_CHANGE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txreg_toggle_reset_on_rate_change_en_attr == SERDES_IP_LANE_L1_CFG_TXREG_TOGGLE_RESET_ON_RATE_CHANGE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txresetdel_sel_attr == SERDES_IP_LANE_L1_CFG_TXRESETDEL_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_en_b_attr == SERDES_IP_LANE_L1_CFG_TXRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s0q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s0q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s1q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s1q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s2q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s2q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s2q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s2q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s2q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s2q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s2q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s3q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s3q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s3q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s3q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s3q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s3q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s3q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s3q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s4q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s4q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s5q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_entry2_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s0q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s0q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s1q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s1q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s1q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s1q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s1q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s1q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s2q0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s2q1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s2q2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s2q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s2q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s2q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s2q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s2q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s3q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s3q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s3q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s3q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s3q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s3q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s3q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s3q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s4q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s4q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s5q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_dn_ptr0_s_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_up_ptr0_s_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_aetrtx_bitckdvdrcken_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_AETRTX_BITCKDVDRCKEN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_aetrtx_bitckdvdrcken_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_AETRTX_BITCKDVDRCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_aetrtx_regpwrupacc_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_AETRTX_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_aetrtx_regpwrupacc_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_AETRTX_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_adc_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_adc_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_drvdoze_b_ovr_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_DRVDOZE_B_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_drvdoze_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_DRVDOZE_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_duty_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_DUTY_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_duty_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_DUTY_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_ntl_b_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_ntl_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_p2s_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_P2S_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_p2s_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_P2S_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_reg_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_reg_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_arsttx_adc_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_ARSTTX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_arsttx_adc_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_ARSTTX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_arsttx_pma2pcstxword_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_ARSTTX_PMA2PCSTXWORD_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_arsttx_pma2pcstxword_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_ARSTTX_PMA2PCSTXWORD_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_arsttx_regreset_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_ARSTTX_REGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_arsttx_regreset_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_ARSTTX_REGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_arsttx_txdetectrx_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_ARSTTX_TXDETECTRX_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_arsttx_txdetectrx_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_ARSTTX_TXDETECTRX_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txrststate_hiz_en_attr == SERDES_IP_LANE_L1_CFG_TXRSTSTATE_HIZ_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txspare0_attr == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txspare_attr == 10'd384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txterm_coarse_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txtermtrim_locovren_attr == SERDES_IP_LANE_L1_CFG_TXTERMTRIM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txtermtrim_nmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txtermtrim_pmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txwclk_div_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txwclk_div_en_attr == SERDES_IP_LANE_L1_CFG_TXWCLK_DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txwclk_div_smpl_attr == SERDES_IP_LANE_L1_CFG_TXWCLK_DIV_SMPL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txwptr_init01_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txwptr_init02_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txwptr_init04_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txwptr_init08_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txwptr_init16_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txwptr_init32_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l1_cfg_txwptr_init_rx2txparlb_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_bshihyst_attr == SERDES_IP_LANE_L2_CFG_BSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_bstxdrv_levn_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_bstxdrv_levnm1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_bstxdrv_levnp1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_bstxdrv_levnp2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_calsqlchosc_locovren_attr == SERDES_IP_LANE_L2_CFG_CALSQLCHOSC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_calsqlchosc_trimcode_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_cdrclkstat_locovren_attr == SERDES_IP_LANE_L2_CFG_CDRCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_cdrclkstat_ready_locovr_attr == SERDES_IP_LANE_L2_CFG_CDRCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_etrregrxcdrclk_ready_attr == SERDES_IP_LANE_L2_CFG_ETRREGRXCDRCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_laneckm_avg_en_attr == SERDES_IP_LANE_L2_CFG_LANECKM_AVG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_laneckm_clk_en_attr == SERDES_IP_LANE_L2_CFG_LANECKM_CLK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_laneckm_continuous_attr == SERDES_IP_LANE_L2_CFG_LANECKM_CONTINUOUS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_laneckm_dig_meas_en_attr == SERDES_IP_LANE_L2_CFG_LANECKM_DIG_MEAS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_laneckm_dig_meas_err_clr_attr == SERDES_IP_LANE_L2_CFG_LANECKM_DIG_MEAS_ERR_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_laneckm_en_attr == SERDES_IP_LANE_L2_CFG_LANECKM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_laneckm_max_thr_attr == 25'd33554431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_laneckm_meas_ck_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_laneckm_ref_ck_div_ratio_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_laneckm_result_clr_attr == SERDES_IP_LANE_L2_CFG_LANECKM_RESULT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_laneckm_start_attr == SERDES_IP_LANE_L2_CFG_LANECKM_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_laneckm_wdt_interval_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_laneckm_win_thr_ref_attr == 25'd16777215
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_lanepcs_locovren_attr == SERDES_IP_LANE_L2_CFG_LANEPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_lanepcs_mode_locovr_attr == SERDES_IP_LANE_L2_CFG_LANEPCS_MODE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_laneperfmon_compare_val_start_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_laneperfmon_compare_val_stop_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_laneperfmon_en_attr == SERDES_IP_LANE_L2_CFG_LANEPERFMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_laneperfmon_mask_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_lanepmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_lanepmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_lanepmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_lanepmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_lanepmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_lanepmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_lb_cdrclk2txen_locovr_attr == SERDES_IP_LANE_L2_CFG_LB_CDRCLK2TXEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_lb_cdrclkdiven_attr == SERDES_IP_LANE_L2_CFG_LB_CDRCLKDIVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_lb_cdrdivclk2exten_attr == SERDES_IP_LANE_L2_CFG_LB_CDRDIVCLK2EXTEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_lb_cdrdivclk2txen_attr == SERDES_IP_LANE_L2_CFG_LB_CDRDIVCLK2TXEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_lb_hsclk2cdrdiven_attr == SERDES_IP_LANE_L2_CFG_LB_HSCLK2CDRDIVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_lb_locovren_attr == SERDES_IP_LANE_L2_CFG_LB_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_lb_parrx2txtimeden_locovr_attr == SERDES_IP_LANE_L2_CFG_LB_PARRX2TXTIMEDEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_lb_pllfbclk2cdrrefclken_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_lb_pllfbclk2cdrrefclken_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_lb_pllfbclk2cdrrefclken_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_lb_pllfbclk2cdrrefclken_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_lb_pllfbclk2cdrrefclken_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_lb_rx2txuntimeden_attr == SERDES_IP_LANE_L2_CFG_LB_RX2TXUNTIMEDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_lb_rxwordck2pcstxwordcken_attr == SERDES_IP_LANE_L2_CFG_LB_RXWORDCK2PCSTXWORDCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_lb_tx2rxbuftimeden_lsb_locovr_attr == SERDES_IP_LANE_L2_CFG_LB_TX2RXBUFTIMEDEN_LSB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_lb_tx2rxbuftimeden_msb_locovr_attr == SERDES_IP_LANE_L2_CFG_LB_TX2RXBUFTIMEDEN_MSB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_lb_tx2rxiotimeden_attr == SERDES_IP_LANE_L2_CFG_LB_TX2RXIOTIMEDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_lfps_det_locovr_attr == SERDES_IP_LANE_L2_CFG_LFPS_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_lfps_locovren_attr == SERDES_IP_LANE_L2_CFG_LFPS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_lfps_out_en_attr == SERDES_IP_LANE_L2_CFG_LFPS_OUT_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_pcslfps_en_locovr_attr == SERDES_IP_LANE_L2_CFG_PCSLFPS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_pcslfps_locovren_attr == SERDES_IP_LANE_L2_CFG_PCSLFPS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_pcsrx_dme_en_locovr_attr == SERDES_IP_LANE_L2_CFG_PCSRX_DME_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_pcsrx_locovren_attr == SERDES_IP_LANE_L2_CFG_PCSRX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_pcsrxbist_locovren_attr == SERDES_IP_LANE_L2_CFG_PCSRXBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_pcsrxbist_modesel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_pcstx_beaconen_locovr_attr == SERDES_IP_LANE_L2_CFG_PCSTX_BEACONEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_pcstx_locovren_attr == SERDES_IP_LANE_L2_CFG_PCSTX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_polarity_rx_attr == SERDES_IP_LANE_L2_CFG_POLARITY_RX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_polarity_tx_attr == SERDES_IP_LANE_L2_CFG_POLARITY_TX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rx_cmn_on_state_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rx_fastregpwrup_en_attr == SERDES_IP_LANE_L2_CFG_RX_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rx_frac_mode_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rx_on_state_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rx_pg_disable_attr == SERDES_IP_LANE_L2_CFG_RX_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rx_synth_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rx_synth_sel_amode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rx_synth_sel_bmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rx_synth_sel_cmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rx_synth_sel_dmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rx_synth_sel_emode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxadc_req_attr == SERDES_IP_LANE_L2_CFG_RXADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxagc_dccoupleen_attr == SERDES_IP_LANE_L2_CFG_RXAGC_DCCOUPLEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxaprobe_addr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxaprobe_lastmux_isolate_attr == SERDES_IP_LANE_L2_CFG_RXAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxaprobeadc_current_direction_attr == SERDES_IP_LANE_L2_CFG_RXAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxaprobeadc_resistor_enable_attr == SERDES_IP_LANE_L2_CFG_RXAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxbias_iccadj_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxbias_icvadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxbias_locovren_attr == SERDES_IP_LANE_L2_CFG_RXBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxbias_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxbist_burst_four_errtype_attr == SERDES_IP_LANE_L2_CFG_RXBIST_BURST_FOUR_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxbist_burst_one_errtype_attr == SERDES_IP_LANE_L2_CFG_RXBIST_BURST_ONE_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxbist_burst_three_errtype_attr == SERDES_IP_LANE_L2_CFG_RXBIST_BURST_THREE_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxbist_burst_two_errtype_attr == SERDES_IP_LANE_L2_CFG_RXBIST_BURST_TWO_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxbist_cdrlock2data_bypass_attr == SERDES_IP_LANE_L2_CFG_RXBIST_CDRLOCK2DATA_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxbist_cdrlock2data_postamble_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxbist_clear_errcount_attr == SERDES_IP_LANE_L2_CFG_RXBIST_CLEAR_ERRCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxbist_err_en_attr == SERDES_IP_LANE_L2_CFG_RXBIST_ERR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxbist_err_trig_type_attr == SERDES_IP_LANE_L2_CFG_RXBIST_ERR_TRIG_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxbist_errmask_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxbist_errtype_attr == SERDES_IP_LANE_L2_CFG_RXBIST_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxbist_firsterr_type_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxbist_lockchk_count_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxbist_maxbitcnt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxbist_mostrecent_err_attr == SERDES_IP_LANE_L2_CFG_RXBIST_MOSTRECENT_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxbist_relock_itercount_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxbist_seed_attr == 31'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxbist_status_hold_attr == SERDES_IP_LANE_L2_CFG_RXBIST_STATUS_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxbitslip_locovr_attr == SERDES_IP_LANE_L2_CFG_RXBITSLIP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxbitslip_locovren_attr == SERDES_IP_LANE_L2_CFG_RXBITSLIP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxbscan_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxbshicm_attr == SERDES_IP_LANE_L2_CFG_RXBSHICM_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalcdrfbdiv_div2_bypass_muxd0_attr == SERDES_IP_LANE_L2_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalcdrfbdiv_div2_bypass_muxd1_attr == SERDES_IP_LANE_L2_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalcdrfbdiv_div2_bypass_muxd2_attr == SERDES_IP_LANE_L2_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalcdrfbdiv_div2_bypass_muxd3_attr == SERDES_IP_LANE_L2_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalcdrfbdiv_div2_bypass_muxd4_attr == SERDES_IP_LANE_L2_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalduty_iclk_gray_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalduty_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTY_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalduty_qclk_gray_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalduty_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutybg_abort_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutybg_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutybg_ready_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycomp_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycomp_offset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_finish_side_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_init_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_initval_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_invert_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_round_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_runcount_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_signmagen_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsmout_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsmout_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_disable_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCTRL_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_i_div1_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_i_div2_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_i_div4_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_i_div8_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_q_div1_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_q_div2_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_q_div4_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_q_div8_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_bg_en_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_bg_one_step_cal_en_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_finish_side_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_i_polarity_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_I_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_i_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_I_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_init_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_q_polarity_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_Q_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_q_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_Q_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_round_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_runcount_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_signmagen_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_comp_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEAS_COMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_comp_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEAS_COMP_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_i_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEAS_I_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_i_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEAS_I_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_q_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEAS_Q_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_q_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEAS_Q_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeasout_comp_ack_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEASOUT_COMP_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeasout_comp_erravg_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEASOUT_COMP_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeasout_i_ack_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEASOUT_I_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeasout_i_erravg_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEASOUT_I_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeasout_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeasout_q_ack_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEASOUT_Q_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeasout_q_erravg_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEASOUT_Q_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutystat_done_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaldutystat_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_centerfreq_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_end_delay_attr == 9'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_hscount_muxd0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_hscount_muxd1_attr == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_hscount_muxd2_attr == 8'd180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_hscount_muxd3_attr == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_hscount_muxd4_attr == 8'd206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_initval_centerfreq_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_initval_fosc_attr == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_centerfreq_finish_side_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_CENTERFREQ_FINISH_SIDE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_centerfreq_to_fosc_offset_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_centerfreqen_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_CENTERFREQEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_centerfreqoffset_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_fosc_finishside_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_FOSC_FINISHSIDE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_foscen_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_FOSCEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_foscoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_init_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_invert_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_lpfax_calfosccoarse_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_lpfax_calfoscfine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_lpfax_centerfreqcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_lpfax_centerfreqfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_runcount_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_signmagen_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_vcorepen_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_VCOREPEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsmout_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsmout_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_count_muxd0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_count_muxd1_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_count_muxd2_attr == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_count_muxd3_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_count_muxd4_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_dlycount_attr == 9'd68
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeasout_clear_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCMEASOUT_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeasout_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeasout_start_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCMEASOUT_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscval_int_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscval_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalintsval_int_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalintsval_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALINTSVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaloffsetfsm_init_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaloffsetfsm_init_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaloffsetfsm_init_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALOFFSETFSM_INIT_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaloffsetfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcaloffsetfsmout_input_en_attr == SERDES_IP_LANE_L2_CFG_RXCALOFFSETFSMOUT_INPUT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_duty_i_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_duty_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_dutycomp_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_foscfsm_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_offsetfsm_init_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_regopampoffset_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_rxppm_lockstatus_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_sqlch_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_sqlchosc_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_synthppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_voscregopampoffset_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_duty_i_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_duty_q_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_dutycomp_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_foscfsm_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_offsetfsm_init_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_rxppm_lockstatus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_sqlch_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_sqlchosc_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_synthppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_voscregopampoffset_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffset_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_finish_side_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_round_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_runcount_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_signmagen_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchfsm_clear_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchfsm_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchfsmout_caldone_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHFSMOUT_CALDONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchfsmout_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_codeoffset_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_finish_side_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHOSCFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_init_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHOSCFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_initval_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_invert_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHOSCFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHOSCFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHOSCFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_round_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHOSCFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_runcount_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHOSCFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscmeas_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHOSCMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscmeas_ref_cnt_attr == 10'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscmeas_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHOSCMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscmeas_settle_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscmeas_smpl_cnt_attr == 10'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvbiascap_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALVBIASCAP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvbiascap_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALVBIASCAP_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvcoopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvcoopampoffsetmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvcoopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvcoopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffset_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffset_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_codeoffset_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_finish_side_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_initval_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_invert_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_lpfaxcoarse_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_round_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_runcount_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETFSM_RUNCOUNT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_signmagen_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsmout_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsmout_runcount_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETFSMOUT_RUNCOUNT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetmeas_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffset_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALVOSCREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALVOSCREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L2_CFG_RXCALVOSCREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALVOSCREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALVOSCREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALVOSCREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALVOSCREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALVOSCREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALVOSCREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrdiv_local_en_attr == SERDES_IP_LANE_L2_CFG_RXCDRDIV_LOCAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdiv_moddiv_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdiv_moddiv_muxd1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdiv_moddiv_muxd2_attr == 4'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdiv_moddiv_muxd3_attr == 4'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdiv_moddiv_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdivslip_mdiv_muxd0_attr == 9'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdivslip_mdiv_muxd1_attr == 9'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdivslip_mdiv_muxd2_attr == 9'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdivslip_mdiv_muxd3_attr == 9'd66
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdivslip_mdiv_muxd4_attr == 9'd210
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrpfd_forcedn_attr == SERDES_IP_LANE_L2_CFG_RXCDRPFD_FORCEDN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrpfd_forceen_attr == SERDES_IP_LANE_L2_CFG_RXCDRPFD_FORCEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrpfd_forceup_attr == SERDES_IP_LANE_L2_CFG_RXCDRPFD_FORCEUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrpfd_propgain_attr == SERDES_IP_LANE_L2_CFG_RXCDRPFD_PROPGAIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrpfd_pulsewidth_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrphd_asym_override_ignore_attr == SERDES_IP_LANE_L2_CFG_RXCDRPHD_ASYM_OVERRIDE_IGNORE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrphd_bitshift_en_attr == SERDES_IP_LANE_L2_CFG_RXCDRPHD_BITSHIFT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrphd_forcedn_attr == SERDES_IP_LANE_L2_CFG_RXCDRPHD_FORCEDN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrphd_forceen_attr == SERDES_IP_LANE_L2_CFG_RXCDRPHD_FORCEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrphd_forceup_attr == SERDES_IP_LANE_L2_CFG_RXCDRPHD_FORCEUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrphdrate_doublerate2s2p_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCDRPHDRATE_DOUBLERATE2S2P_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrphdrate_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCDRPHDRATE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrrefck_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrrefck_refdiv_muxd1_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrrefck_refdiv_muxd2_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrrefck_refdiv_muxd3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrrefck_refdiv_muxd4_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_biastop_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_biastopbypass_attr == SERDES_IP_LANE_L2_CFG_RXCDRVCO_BIASTOPBYPASS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_datapropgain_high_attr == 5'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_datapropgain_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_datapropgain_low_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_ff_ovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_ff_ovr_en_attr == SERDES_IP_LANE_L2_CFG_RXCDRVCO_FF_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_fil_short_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_flickerdegen_attr == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_gmfoscshort_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCDRVCO_GMFOSCSHORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_intf_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_intf_fil_short_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_intrj_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCDRVCO_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_refpropgain_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_refpropgain_nom_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxclk_cdrfb_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCLK_CDRFB_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxclk_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxclk_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdat_nrz_64b80b_bcword_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdata_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXDATA_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdata_locovren_attr == SERDES_IP_LANE_L2_CFG_RXDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdatapath_locovren_attr == SERDES_IP_LANE_L2_CFG_RXDATAPATH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdatapath_on_state_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdatapath_ready_locovr_attr == SERDES_IP_LANE_L2_CFG_RXDATAPATH_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdfe_datatap_vcasc_attr == 4'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdfe_dfebiasadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdfe_nbiasctle_en_attr == SERDES_IP_LANE_L2_CFG_RXDFE_NBIASCTLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdfe_vcasc_sel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdfeterm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXDFETERM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdfeterm_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdfeyadjdac_datamid_edge_coarse_en_attr == SERDES_IP_LANE_L2_CFG_RXDFEYADJDAC_DATAMID_EDGE_COARSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdfeyadjdac_datatopbot_aux_coarse_en_attr == SERDES_IP_LANE_L2_CFG_RXDFEYADJDAC_DATATOPBOT_AUX_COARSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_accum_mon_en_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_ACCUM_MON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_accum_mon_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_bypasscdrpdetupdnsmpl_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_bypassenfosc_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_BYPASSENFOSC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_bypassenints_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_BYPASSENINTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_bypassenupdnsmpl_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_BYPASSENUPDNSMPL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_bypassfosc_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_bypasspllpfdupdnsmpl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_bypassrxints_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_data2pll_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_deltasigmode_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_DELTASIGMODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_fastref_muxd0_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_FASTREF_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_fastref_muxd1_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_FASTREF_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_fastref_muxd2_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_FASTREF_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_fastref_muxd3_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_FASTREF_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_fastref_muxd4_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_FASTREF_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_fosc_mod_bypass_en_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_FOSC_MOD_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_fosc_sample_pedge_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_FOSC_SAMPLE_PEDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gain_step_on_lock_recovery_en_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_GAIN_STEP_ON_LOCK_RECOVERY_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gaindelaycount_init_attr == 9'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gaindelaycount_pow2_muxd0_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gaindelaycount_pow2_muxd1_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gaindelaycount_pow2_muxd2_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gaindelaycount_pow2_muxd3_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gaindelaycount_pow2_muxd4_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2ref_pow2_muxd0_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2ref_pow2_muxd1_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2ref_pow2_muxd2_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2ref_pow2_muxd3_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2ref_pow2_muxd4_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainunlocked_pow2_muxd0_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainunlocked_pow2_muxd1_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainunlocked_pow2_muxd2_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainunlocked_pow2_muxd3_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainunlocked_pow2_muxd4_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_initintegrator_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_INITINTEGRATOR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_initmodulator_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_INITMODULATOR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_deltasig_mode_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_INTS_DELTASIG_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_freeze_en_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_INTS_FREEZE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gaindelaycount_pow2_muxd0_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gaindelaycount_pow2_muxd1_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gaindelaycount_pow2_muxd2_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gaindelaycount_pow2_muxd3_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gaindelaycount_pow2_muxd4_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd0_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd1_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd2_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd3_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd4_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd0_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd1_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd2_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd3_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd4_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainunlocked_pow2_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainunlocked_pow2_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainunlocked_pow2_muxd2_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainunlocked_pow2_muxd3_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainunlocked_pow2_muxd4_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_guardband_hi_attr == 8'd200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_guardband_lo_attr == 8'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_loop_sel_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_INTS_LOOP_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_mod_bypass_en_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_INTS_MOD_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_mod_load_pedge_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_INTS_MOD_LOAD_PEDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_step_to_integer_en_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_INTS_STEP_TO_INTEGER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_jit_length_attr == 18'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_jit_mode_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_JIT_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_modck_ctrl_en_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_MODCK_CTRL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_pll2data_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_restore_cntr_attr == 9'd258
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_store_cntr_attr == 16'd258
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpif_trnsfrdelay_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpiffreeze_inten_attr == SERDES_IP_LANE_L2_CFG_RXDPIFFREEZE_INTEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdpiffreeze_moden_attr == SERDES_IP_LANE_L2_CFG_RXDPIFFREEZE_MODEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxdutyselpolarity_attr == SERDES_IP_LANE_L2_CFG_RXDUTYSELPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxflxgate_force_rxeq_gate_locovr_attr == SERDES_IP_LANE_L2_CFG_RXFLXGATE_FORCE_RXEQ_GATE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxflxgate_locovren_attr == SERDES_IP_LANE_L2_CFG_RXFLXGATE_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxfoscstat_done_locovr_attr == SERDES_IP_LANE_L2_CFG_RXFOSCSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxfoscstat_locovren_attr == SERDES_IP_LANE_L2_CFG_RXFOSCSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxfsm_cken_ovr_attr == SERDES_IP_LANE_L2_CFG_RXFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxfsm_cken_ovren_attr == SERDES_IP_LANE_L2_CFG_RXFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxints_prev_votes_hold_en_attr == SERDES_IP_LANE_L2_CFG_RXINTS_PREV_VOTES_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxlanepam_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXLANEPAM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxlanepam_locovren_attr == SERDES_IP_LANE_L2_CFG_RXLANEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxlock2datatmr_attr == 8'd240
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxlock2datatmr_short_attr == 8'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxntl_changeref_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxntl_changeref_val_locovr_attr == SERDES_IP_LANE_L2_CFG_RXNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxntl_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxntl_en_attr == SERDES_IP_LANE_L2_CFG_RXNTL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxntl_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxntl_locovren_attr == SERDES_IP_LANE_L2_CFG_RXNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxntl_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxntl_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxntl_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxntl_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxntl_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxntl_rxm_charge_up_locovr_attr == SERDES_IP_LANE_L2_CFG_RXNTL_RXM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxntl_rxm_pull_dn_locovr_attr == SERDES_IP_LANE_L2_CFG_RXNTL_RXM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxntl_rxm_sense_locovr_attr == SERDES_IP_LANE_L2_CFG_RXNTL_RXM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxntl_rxp_charge_up_locovr_attr == SERDES_IP_LANE_L2_CFG_RXNTL_RXP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxntl_rxp_pull_dn_locovr_attr == SERDES_IP_LANE_L2_CFG_RXNTL_RXP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxntl_rxp_sense_locovr_attr == SERDES_IP_LANE_L2_CFG_RXNTL_RXP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxntl_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_acc_freeze_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_ACC_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_cdrlock2data_gater_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_cdrlock2data_gater_hold_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_cdrlock2data_gater_ovrd_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_cdrlock2datatmr_optcl_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_cdrlock2datatmr_optcl_sel_ovrd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_enter_lock2data_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_ENTER_LOCK2DATA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_enter_lock2data_hold_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_ENTER_LOCK2DATA_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_exit_lock2data_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_EXIT_LOCK2DATA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_exit_lock2data_hold_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_EXIT_LOCK2DATA_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_force_lock2data_ovrd_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_FORCE_LOCK2DATA_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_force_lock2ref_ovrd_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_FORCE_LOCK2REF_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_hold_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_hold_timer_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_intf_ovrd_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_INTF_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_intf_ovrd_type_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_INTF_OVRD_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_mod_freeze_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_MOD_FREEZE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_ovrd_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_ppm_detect_freeze_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_PPM_DETECT_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_ppm_detect_freeze_ovrd_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_PPM_DETECT_FREEZE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_ppm_detect_hold_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_PPM_DETECT_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_prop_freeze_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_PROP_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_prop_freeze_ovrd_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_PROP_FREEZE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_rxdata_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_RXDATA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_skip_init_lock2data_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_SKIP_INIT_LOCK2DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxpam_bitorder_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxpam_gray_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXPAM_GRAY_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxpam_locovren_attr == SERDES_IP_LANE_L2_CFG_RXPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxpam_precode_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXPAM_PRECODE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_p5_muxd0_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIV_P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_p5_muxd1_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIV_P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_p5_muxd2_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIV_P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_p5_muxd3_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIV_P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_p5_muxd4_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIV_P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdivclken_muxd0_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIVCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdivclken_muxd1_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIVCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdivclken_muxd2_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIVCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdivclken_muxd3_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIVCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdivclken_muxd4_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIVCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxpcsbist_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXPCSBIST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxpcsbist_locovren_attr == SERDES_IP_LANE_L2_CFG_RXPCSBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxphd_gain_hold_en_attr == SERDES_IP_LANE_L2_CFG_RXPHD_GAIN_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxphd_gain_zero_locovr_attr == SERDES_IP_LANE_L2_CFG_RXPHD_GAIN_ZERO_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxphd_locovren_attr == SERDES_IP_LANE_L2_CFG_RXPHD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxphd_majvote_basegain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxphd_majvote_en_attr == SERDES_IP_LANE_L2_CFG_RXPHD_MAJVOTE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxphd_mute_cntr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxphd_nrz8b10b_pam16b20b_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxphd_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxphd_pam_transition_sel_attr == SERDES_IP_LANE_L2_CFG_RXPHD_PAM_TRANSITION_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxphd_sign_invert_attr == SERDES_IP_LANE_L2_CFG_RXPHD_SIGN_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxpostdiv_wait_for_lock_disable_attr == SERDES_IP_LANE_L2_CFG_RXPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxppm_freq_max_offset_h_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxppm_freq_max_offset_l_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxppm_freq_ref_cnt_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxppm_lockstatus_locovr_attr == SERDES_IP_LANE_L2_CFG_RXPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxppm_lockstatus_synthlcfast_en_attr == SERDES_IP_LANE_L2_CFG_RXPPM_LOCKSTATUS_SYNTHLCFAST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxppm_lockstatus_synthlcmed_en_attr == SERDES_IP_LANE_L2_CFG_RXPPM_LOCKSTATUS_SYNTHLCMED_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxppm_lockstatus_synthlcslow_en_attr == SERDES_IP_LANE_L2_CFG_RXPPM_LOCKSTATUS_SYNTHLCSLOW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxppm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxppm_ppmdriftcount_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxppm_ppmdriftmax_attr == 16'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxppm_status_hold_attr == SERDES_IP_LANE_L2_CFG_RXPPM_STATUS_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxppm_unlock_clear_attr == SERDES_IP_LANE_L2_CFG_RXPPM_UNLOCK_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_fast_muxd0_attr == 16'd666
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_fast_muxd1_attr == 16'd4000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_fast_muxd2_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_fast_muxd3_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_fast_muxd4_attr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_muxd0_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_muxd1_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_muxd2_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_muxd3_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_muxd4_attr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxppmctrl_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXPPMCTRL_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxppmctrl_locovren_attr == SERDES_IP_LANE_L2_CFG_RXPPMCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxppmlockstat_locovren_attr == SERDES_IP_LANE_L2_CFG_RXPPMLOCKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxppmlockstat_sticky_locovr_attr == SERDES_IP_LANE_L2_CFG_RXPPMLOCKSTAT_STICKY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxppmtmr_locovren_attr == SERDES_IP_LANE_L2_CFG_RXPPMTMR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxppmtmr_watchdogtmr_sel_locovr_attr == SERDES_IP_LANE_L2_CFG_RXPPMTMR_WATCHDOGTMR_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_cal_clear_delay_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_clk_chk_disable_attr == SERDES_IP_LANE_L2_CFG_RXRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_clk_delay_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_etr_on_delay_attr == 12'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_locovren_attr == SERDES_IP_LANE_L2_CFG_RXRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxreg_lev_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxreg_toggle_reset_on_rate_change_en_attr == SERDES_IP_LANE_L2_CFG_RXREG_TOGGLE_RESET_ON_RATE_CHANGE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxreg_vreg_bypass_attr == SERDES_IP_LANE_L2_CFG_RXREG_VREG_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_en_b_attr == SERDES_IP_LANE_L2_CFG_RXRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s0q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s0q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s2q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s2q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s2q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s2q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s2q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s2q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s2q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s3q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s3q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s3q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s3q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s3q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s3q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s3q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s3q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s4q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s4q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s5q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_entry4_attr == 13'd78
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_entry5_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_entry6_attr == 13'd1406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s0q2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s0q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s1q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s1q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s1q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s1q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s1q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s1q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s2q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s2q2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s2q3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s2q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s2q5_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s2q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s2q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s3q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s3q1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s3q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s3q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s3q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s3q5_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s3q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s3q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s4q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s4q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s5q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_aetrrx_cdrfbdivcken_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_AETRRX_CDRFBDIVCKEN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_aetrrx_cdrfbdivcken_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_AETRRX_CDRFBDIVCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_aetrrx_cdrmoddivcken_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_AETRRX_CDRMODDIVCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_aetrrx_cdrmoddivcken_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_AETRRX_CDRMODDIVCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_aetrrx_termhiz_en_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_AETRRX_TERMHIZ_EN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_aetrrx_termhiz_en_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_AETRRX_TERMHIZ_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_aetrsynth_pcspostdivclksel_ovr_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_AETRSYNTH_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_aetrsynth_pcspostdivclksel_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_AETRSYNTH_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_adc_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_adc_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_auxcomp_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_AUXCOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_auxcomp_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_AUXCOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_bias_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_bias_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_BIAS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_ctlecomp_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_CTLECOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_ctlecomp_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_CTLECOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_datfbdiv_b_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DATFBDIV_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_datfbdiv_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DATFBDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_dfe_bias_b_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DFE_BIAS_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_dfe_bias_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DFE_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_dfe_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DFE_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_dfe_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DFE_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_dfe_yadj_b_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DFE_YADJ_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_dfe_yadj_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DFE_YADJ_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_duty_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DUTY_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_duty_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DUTY_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_hifreqagc_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_HIFREQAGC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_hifreqagc_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_HIFREQAGC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_ntl_b_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_ntl_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_reg_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_reg_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_vco_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_VCO_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_vco_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_VCO_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_voscreg_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_VOSCREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_voscreg_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_VOSCREG_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_adc_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_adc_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_cdrfbdiv_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_CDRFBDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_cdrfbdiv_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_CDRFBDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_pdet_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_PDET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_pdet_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_PDET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_pfd_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_PFD_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_pfd_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_PFD_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_refdiv_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_refdiv_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_reg_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_reg_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_s2pa_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_S2PA_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_s2pa_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_S2PA_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_s2pb_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_S2PB_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_s2pb_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_S2PB_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_vco_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_VCO_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_vco_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_VCO_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_voscreg_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_VOSCREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_voscreg_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_VOSCREG_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstsynth_postdiv_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTSYNTH_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstsynth_postdiv_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTSYNTH_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_drstrx_dpif_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_DRSTRX_DPIF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_drstrx_dpif_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_DRSTRX_DPIF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_drstrx_ppm_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_DRSTRX_PPM_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_drstrx_ppm_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_DRSTRX_PPM_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_cdrlock2data_locovr_attr == SERDES_IP_LANE_L2_CFG_RXSIGDET_CDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_diglfpsdeten_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_diglfpsdeten_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_diglfpsdeten_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_diglfpsdeten_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_diglfpsdeten_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrancnten_muxd0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrancnten_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrancnten_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrancnten_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrancnten_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrancnten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrandeten_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrandeten_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrandeten_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrandeten_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrandeten_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrandeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_eiosdeten_muxd0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_eiosdeten_muxd1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_eiosdeten_muxd2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_eiosdeten_muxd3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_eiosdeten_muxd4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_eiosdeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_enable_attr == SERDES_IP_LANE_L2_CFG_RXSIGDET_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_fastlock_winsize_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_leveldeten_muxd0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_leveldeten_muxd1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_leveldeten_muxd2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_leveldeten_muxd3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_leveldeten_muxd4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_leveldeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_lfpsexit_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_locovren_attr == SERDES_IP_LANE_L2_CFG_RXSIGDET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_ppmdeten_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_ppmdeten_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_ppmdeten_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_ppmdeten_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_ppmdeten_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_ppmdeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_rxeq_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_rxeqen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_rxeqen_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_rxleveldet_debounce_dncount_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_rxleveldet_debounce_flush_en_attr == SERDES_IP_LANE_L2_CFG_RXSIGDET_RXLEVELDET_DEBOUNCE_FLUSH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_rxleveldet_debounce_upcount_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_sigdet_debounce_attr == SERDES_IP_LANE_L2_CFG_RXSIGDET_SIGDET_DEBOUNCE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_tmr_clksel_attr == SERDES_IP_LANE_L2_CFG_RXSIGDET_TMR_CLKSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_toggle_count_en_attr == SERDES_IP_LANE_L2_CFG_RXSIGDET_TOGGLE_COUNT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_toggle_count_pause_attr == SERDES_IP_LANE_L2_CFG_RXSIGDET_TOGGLE_COUNT_PAUSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_toggle_monitor_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdetin_eiosdetectstat_locovr_attr == SERDES_IP_LANE_L2_CFG_RXSIGDETIN_EIOSDETECTSTAT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdetin_locovren_attr == SERDES_IP_LANE_L2_CFG_RXSIGDETIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdetin_ovrcdrlock2data_locovr_attr == SERDES_IP_LANE_L2_CFG_RXSIGDETIN_OVRCDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdetin_ovrencdrlock2data_locovr_attr == SERDES_IP_LANE_L2_CFG_RXSIGDETIN_OVRENCDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdetout_lock2data_noforce_ltr_locovr_attr == SERDES_IP_LANE_L2_CFG_RXSIGDETOUT_LOCK2DATA_NOFORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsigdetout_locovren_attr == SERDES_IP_LANE_L2_CFG_RXSIGDETOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxspare0_attr == 32'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxspare_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsqlchlfps_consec_one_thresh_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsqlchlfps_consec_zero_thresh_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsqlchlfps_cycle_thresh_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsqlchlfps_dat_bitorder_attr == SERDES_IP_LANE_L2_CFG_RXSQLCHLFPS_DAT_BITORDER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsqlchlfps_debounce_type_attr == SERDES_IP_LANE_L2_CFG_RXSQLCHLFPS_DEBOUNCE_TYPE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsqlchlfps_one_run_length_thresh_attr == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsqlchlfps_one_run_length_timeout_attr == 8'd103
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsqlchlfps_zero_run_length_thresh_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsqlchlfps_zero_run_length_timeout_attr == 8'd103
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsynthdiv_slowmed_en_muxd0_attr == SERDES_IP_LANE_L2_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsynthdiv_slowmed_en_muxd1_attr == SERDES_IP_LANE_L2_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsynthdiv_slowmed_en_muxd2_attr == SERDES_IP_LANE_L2_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsynthdiv_slowmed_en_muxd3_attr == SERDES_IP_LANE_L2_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxsynthdiv_slowmed_en_muxd4_attr == SERDES_IP_LANE_L2_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxterm_cal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxterm_coarse_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxterm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXTERM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxterm_modeselect_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxtermhiz_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXTERMHIZ_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxtermhiz_locovren_attr == SERDES_IP_LANE_L2_CFG_RXTERMHIZ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxvoscreg_bypass_vosc_attr == SERDES_IP_LANE_L2_CFG_RXVOSCREG_BYPASS_VOSC_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxvoscregopampoffsetctrl_sel_attr == SERDES_IP_LANE_L2_CFG_RXVOSCREGOPAMPOFFSETCTRL_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxvoscregopampoffseterr_locovren_attr == SERDES_IP_LANE_L2_CFG_RXVOSCREGOPAMPOFFSETERR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxvoscregopampoffseterr_sel_locovr_attr == SERDES_IP_LANE_L2_CFG_RXVOSCREGOPAMPOFFSETERR_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxvoscregvref_locovren_attr == SERDES_IP_LANE_L2_CFG_RXVOSCREGVREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_rxvoscregvref_sel_locovr_attr == SERDES_IP_LANE_L2_CFG_RXVOSCREGVREF_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlch_acqgain_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlch_acqtime_attr == 13'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlch_cal_quiet_locovr_attr == SERDES_IP_LANE_L2_CFG_SQLCH_CAL_QUIET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlch_cal_sel_locovr_attr == SERDES_IP_LANE_L2_CFG_SQLCH_CAL_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlch_calctrl_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlch_calen_locovr_attr == SERDES_IP_LANE_L2_CFG_SQLCH_CALEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlch_caltimer_attr == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlch_clkgate_locovr_attr == SERDES_IP_LANE_L2_CFG_SQLCH_CLKGATE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlch_cmshiften_attr == SERDES_IP_LANE_L2_CFG_SQLCH_CMSHIFTEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_acq_gain_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_acq_pct_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_cal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_clr_errlog_attr == SERDES_IP_LANE_L2_CFG_SQLCH_CONT_CLR_ERRLOG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_controller_mode_attr == SERDES_IP_LANE_L2_CFG_SQLCH_CONT_CONTROLLER_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_dis_attr == SERDES_IP_LANE_L2_CFG_SQLCH_CONT_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_pause_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_postcal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_precal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_quiet_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlch_lfps_en_attr == SERDES_IP_LANE_L2_CFG_SQLCH_LFPS_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlch_locovren_attr == SERDES_IP_LANE_L2_CFG_SQLCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlch_ovrd_val_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlch_pkdet_freqsel_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlch_polarity_attr == SERDES_IP_LANE_L2_CFG_SQLCH_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlch_rdacen_attr == SERDES_IP_LANE_L2_CFG_SQLCH_RDACEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlch_thresh_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlch_time_out_attr == 16'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlch_vrefsel0_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlch_vrefsel1_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlch_vrefsel_ovr_en_attr == SERDES_IP_LANE_L2_CFG_SQLCH_VREFSEL_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlchdeb_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlchdeb_deb_cnt_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlchdeb_deb_status_cnt_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlchdeb_en_attr == SERDES_IP_LANE_L2_CFG_SQLCHDEB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlchdeb_ign_cnt_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlchdeb_sigdet_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlchdeb_thresh_cnt_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlchdebout_exit_good_debounced_locovr_attr == SERDES_IP_LANE_L2_CFG_SQLCHDEBOUT_EXIT_GOOD_DEBOUNCED_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlchdebout_exit_good_debounced_status_locovr_attr == SERDES_IP_LANE_L2_CFG_SQLCHDEBOUT_EXIT_GOOD_DEBOUNCED_STATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlchdebout_exit_good_locovr_attr == SERDES_IP_LANE_L2_CFG_SQLCHDEBOUT_EXIT_GOOD_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_sqlchdebout_locovren_attr == SERDES_IP_LANE_L2_CFG_SQLCHDEBOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_trancnt_off_attr == 10'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_trancnt_on_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_trancntout_det_locovr_attr == SERDES_IP_LANE_L2_CFG_TRANCNTOUT_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_trancntout_locovren_attr == SERDES_IP_LANE_L2_CFG_TRANCNTOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_trandet_ax_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_trandet_ay_attr == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_trandet_off_h_attr == 6'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_trandet_off_l_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_trandet_on_h_attr == 6'd39
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_trandet_on_l_attr == 6'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_trandetout_det_locovr_attr == SERDES_IP_LANE_L2_CFG_TRANDETOUT_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_trandetout_locovren_attr == SERDES_IP_LANE_L2_CFG_TRANDETOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_tx2rxlb_en_attr == SERDES_IP_LANE_L2_CFG_TX2RXLB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_tx2rxlb_init_offset_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_tx_cmn_on_state_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_tx_fastregpwrup_en_attr == SERDES_IP_LANE_L2_CFG_TX_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_tx_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_tx_pg_disable_attr == SERDES_IP_LANE_L2_CFG_TX_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_tx_synth_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_tx_synth_sel_amode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_tx_synth_sel_bmode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_tx_synth_sel_cmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_tx_synth_sel_dmode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_tx_synth_sel_emode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_tx_txdetrx_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txadc_req_attr == SERDES_IP_LANE_L2_CFG_TXADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txaprobe_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txaprobe_lastmux_isolate_attr == SERDES_IP_LANE_L2_CFG_TXAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txaprobeadc_current_direction_attr == SERDES_IP_LANE_L2_CFG_TXAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txaprobeadc_resistor_enable_attr == SERDES_IP_LANE_L2_CFG_TXAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txbdvdr_pma2pcstxworden_attr == SERDES_IP_LANE_L2_CFG_TXBDVDR_PMA2PCSTXWORDEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txbeacon_div_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txbeacon_sel_attr == SERDES_IP_LANE_L2_CFG_TXBEACON_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txbias_icc20uadj_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txbias_icc80uadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txbias_locovren_attr == SERDES_IP_LANE_L2_CFG_TXBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txbias_termcal_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txbist_biterror_en_attr == SERDES_IP_LANE_L2_CFG_TXBIST_BITERROR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txbist_locovren_attr == SERDES_IP_LANE_L2_CFG_TXBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txbist_modesel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txbist_oobmode_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txbist_oobtburst_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txbist_oobtcomrstinit_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txbist_oobtcomsas_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txbist_oobtcomwake_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txbist_seed_attr == 31'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_size_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf00_attr == 32'd1985229328
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf01_attr == 32'd4275878552
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf02_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf03_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf04_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf05_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf06_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf07_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf08_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf09_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txbit_select_muxd0_attr == SERDES_IP_LANE_L2_CFG_TXBIT_SELECT_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txbit_select_muxd1_attr == SERDES_IP_LANE_L2_CFG_TXBIT_SELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txbit_select_muxd2_attr == SERDES_IP_LANE_L2_CFG_TXBIT_SELECT_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txbit_select_muxd3_attr == SERDES_IP_LANE_L2_CFG_TXBIT_SELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txbit_select_muxd4_attr == SERDES_IP_LANE_L2_CFG_TXBIT_SELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txbti_data_replication_attr == SERDES_IP_LANE_L2_CFG_TXBTI_DATA_REPLICATION_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txbti_tx_idle_data_en_attr == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcal_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcal_tclkduty_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalduty_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalduty_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTY_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalduty_sel_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutybg_abort_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutybg_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutybg_ready_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutycomp_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutycomp_offset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_finish_side_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_init_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_initval_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_invert_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_req_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_round_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_runcount_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_signmagen_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsmout_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsmout_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompmeas_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompmeas_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompmeas_req_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompmeasout_ack_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPMEASOUT_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompmeasout_erravg_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPMEASOUT_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompmeasout_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_bg_en_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_bg_one_step_cal_en_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_finish_side_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_init_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_invert_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_req_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_round_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_runcount_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_signmagen_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeas_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeas_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeas_req_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeasout_ack_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYMEASOUT_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeasout_erravg_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYMEASOUT_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeasout_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutystat_done_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaldutystat_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalptr_pstate_duty_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalptr_pstate_dutycomp_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalptr_pstate_regopampoffset_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_duty_muxd0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_duty_muxd1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_duty_muxd2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_duty_muxd3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_duty_muxd4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_dutycomp_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_dutycomp_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_dutycomp_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_dutycomp_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_dutycomp_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_regopampoffset_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffset_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_finish_side_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_round_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_runcount_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_signmagen_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcaltclkdutyforce_div1_attr == SERDES_IP_LANE_L2_CFG_TXCALTCLKDUTYFORCE_DIV1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txcdrdiv_local_en_attr == SERDES_IP_LANE_L2_CFG_TXCDRDIV_LOCAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txclk_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txclk_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txclkgenmuxsel_txinternal_attr == SERDES_IP_LANE_L2_CFG_TXCLKGENMUXSEL_TXINTERNAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txdetectrx_thr_attr == 5'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeas_count_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeas_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXDETECTRXMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeas_locovren_attr == SERDES_IP_LANE_L2_CFG_TXDETECTRXMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeas_validdlycount_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeasin_locovren_attr == SERDES_IP_LANE_L2_CFG_TXDETECTRXMEASIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeasin_start_locovr_attr == SERDES_IP_LANE_L2_CFG_TXDETECTRXMEASIN_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeaspcs_locovren_attr == SERDES_IP_LANE_L2_CFG_TXDETECTRXMEASPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeaspcs_req_locovr_attr == SERDES_IP_LANE_L2_CFG_TXDETECTRXMEASPCS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeasval_locovren_attr == SERDES_IP_LANE_L2_CFG_TXDETECTRXMEASVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeasval_stat_locovr_attr == SERDES_IP_LANE_L2_CFG_TXDETECTRXMEASVAL_STAT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txdetrx_levn_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txdetrx_levnm1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txdetrx_levnp1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txdetrx_levnp2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txdrv_hizen_locovr_attr == SERDES_IP_LANE_L2_CFG_TXDRV_HIZEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txdrv_levn_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txdrv_levnm1_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txdrv_levnp1_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txdrv_levnp2_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txdrv_locovren_attr == SERDES_IP_LANE_L2_CFG_TXDRV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txdrv_refcken_attr == SERDES_IP_LANE_L2_CFG_TXDRV_REFCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txdrv_termref_attr == SERDES_IP_LANE_L2_CFG_TXDRV_TERMREF_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txdrvmute_locovr_attr == SERDES_IP_LANE_L2_CFG_TXDRVMUTE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txdrvmute_locovren_attr == SERDES_IP_LANE_L2_CFG_TXDRVMUTE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txduty_ctrl_disable_attr == SERDES_IP_LANE_L2_CFG_TXDUTY_CTRL_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txduty_pad_sense_en_attr == SERDES_IP_LANE_L2_CFG_TXDUTY_PAD_SENSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txdutycal_div16_en_attr == SERDES_IP_LANE_L2_CFG_TXDUTYCAL_DIV16_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txdutycal_div1_en_attr == SERDES_IP_LANE_L2_CFG_TXDUTYCAL_DIV1_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txdutycal_div2_en_attr == SERDES_IP_LANE_L2_CFG_TXDUTYCAL_DIV2_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txdutycal_div4_en_attr == SERDES_IP_LANE_L2_CFG_TXDUTYCAL_DIV4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txdutycal_div8_en_attr == SERDES_IP_LANE_L2_CFG_TXDUTYCAL_DIV8_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txfifo_elecidle_deskew_en_attr == SERDES_IP_LANE_L2_CFG_TXFIFO_ELECIDLE_DESKEW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txfifo_force_txidlebit1_zero_disable_attr == SERDES_IP_LANE_L2_CFG_TXFIFO_FORCE_TXIDLEBIT1_ZERO_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txfifo_kill_dly_10b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txfifo_kill_dly_16b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txfifo_kill_dly_20b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txfifo_kill_dly_32b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txfifo_kill_dly_40b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txfifo_kill_dly_64b_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txfifo_kill_dly_80b_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txfifo_kill_dly_8b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txfifo_kill_en_attr == SERDES_IP_LANE_L2_CFG_TXFIFO_KILL_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txfsm_cken_ovr_attr == SERDES_IP_LANE_L2_CFG_TXFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txfsm_cken_ovren_attr == SERDES_IP_LANE_L2_CFG_TXFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txfsm_main_on_state_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txl1d1_doze_ctrl_attr == SERDES_IP_LANE_L2_CFG_TXL1D1_DOZE_CTRL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txl1d1_txbias_ctrl_attr == SERDES_IP_LANE_L2_CFG_TXL1D1_TXBIAS_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txlanepam_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXLANEPAM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txlanepam_locovren_attr == SERDES_IP_LANE_L2_CFG_TXLANEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txmeaslatovrhd_meas_sel_attr == SERDES_IP_LANE_L2_CFG_TXMEASLATOVRHD_MEAS_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txmute_delay_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txntl_changeref_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txntl_changeref_val_locovr_attr == SERDES_IP_LANE_L2_CFG_TXNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txntl_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txntl_en_attr == SERDES_IP_LANE_L2_CFG_TXNTL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txntl_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txntl_locovren_attr == SERDES_IP_LANE_L2_CFG_TXNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txntl_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txntl_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txntl_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txntl_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txntl_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txntl_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txntl_txm_charge_up_locovr_attr == SERDES_IP_LANE_L2_CFG_TXNTL_TXM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txntl_txm_pull_dn_locovr_attr == SERDES_IP_LANE_L2_CFG_TXNTL_TXM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txntl_txm_sense_locovr_attr == SERDES_IP_LANE_L2_CFG_TXNTL_TXM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txntl_txp_charge_up_locovr_attr == SERDES_IP_LANE_L2_CFG_TXNTL_TXP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txntl_txp_pull_dn_locovr_attr == SERDES_IP_LANE_L2_CFG_TXNTL_TXP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txntl_txp_sense_locovr_attr == SERDES_IP_LANE_L2_CFG_TXNTL_TXP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txp2s_txwordsyncbypen_attr == SERDES_IP_LANE_L2_CFG_TXP2S_TXWORDSYNCBYPEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txpam_bitorder_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txpam_gray_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXPAM_GRAY_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txpam_locovren_attr == SERDES_IP_LANE_L2_CFG_TXPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txpam_precode_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXPAM_PRECODE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txpcs_locovren_attr == SERDES_IP_LANE_L2_CFG_TXPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txpcs_txenable_locovr_attr == SERDES_IP_LANE_L2_CFG_TXPCS_TXENABLE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txpcsbist_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXPCSBIST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txpcsbist_locovren_attr == SERDES_IP_LANE_L2_CFG_TXPCSBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txratewidth_clk_chk_disable_attr == SERDES_IP_LANE_L2_CFG_TXRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txratewidth_etr_on_delay_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txratewidth_locovren_attr == SERDES_IP_LANE_L2_CFG_TXRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txreg_toggle_pwrupacc_on_rate_change_en_attr == SERDES_IP_LANE_L2_CFG_TXREG_TOGGLE_PWRUPACC_ON_RATE_CHANGE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txreg_toggle_reset_on_rate_change_en_attr == SERDES_IP_LANE_L2_CFG_TXREG_TOGGLE_RESET_ON_RATE_CHANGE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txresetdel_sel_attr == SERDES_IP_LANE_L2_CFG_TXRESETDEL_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_en_b_attr == SERDES_IP_LANE_L2_CFG_TXRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s0q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s0q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s1q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s1q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s2q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s2q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s2q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s2q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s2q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s2q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s2q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s3q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s3q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s3q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s3q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s3q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s3q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s3q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s3q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s4q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s4q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s5q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s0q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s0q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s1q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s1q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s1q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s1q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s1q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s1q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s2q0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s2q1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s2q2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s2q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s2q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s2q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s2q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s2q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s3q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s3q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s3q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s3q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s3q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s3q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s3q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s3q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s4q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s4q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s5q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_dn_ptr0_s_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_up_ptr0_s_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_aetrtx_bitckdvdrcken_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_AETRTX_BITCKDVDRCKEN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_aetrtx_bitckdvdrcken_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_AETRTX_BITCKDVDRCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_aetrtx_regpwrupacc_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_AETRTX_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_aetrtx_regpwrupacc_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_AETRTX_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_adc_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_adc_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_drvdoze_b_ovr_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_DRVDOZE_B_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_drvdoze_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_DRVDOZE_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_duty_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_DUTY_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_duty_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_DUTY_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_ntl_b_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_ntl_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_p2s_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_P2S_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_p2s_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_P2S_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_reg_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_reg_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_arsttx_adc_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_ARSTTX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_arsttx_adc_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_ARSTTX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_arsttx_pma2pcstxword_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_ARSTTX_PMA2PCSTXWORD_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_arsttx_pma2pcstxword_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_ARSTTX_PMA2PCSTXWORD_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_arsttx_regreset_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_ARSTTX_REGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_arsttx_regreset_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_ARSTTX_REGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_arsttx_txdetectrx_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_ARSTTX_TXDETECTRX_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_arsttx_txdetectrx_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_ARSTTX_TXDETECTRX_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txrststate_hiz_en_attr == SERDES_IP_LANE_L2_CFG_TXRSTSTATE_HIZ_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txspare0_attr == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txspare_attr == 10'd384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txterm_coarse_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txtermtrim_locovren_attr == SERDES_IP_LANE_L2_CFG_TXTERMTRIM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txtermtrim_nmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txtermtrim_pmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txwclk_div_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txwclk_div_en_attr == SERDES_IP_LANE_L2_CFG_TXWCLK_DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txwclk_div_smpl_attr == SERDES_IP_LANE_L2_CFG_TXWCLK_DIV_SMPL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txwptr_init01_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txwptr_init02_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txwptr_init04_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txwptr_init08_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txwptr_init16_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txwptr_init32_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l2_cfg_txwptr_init_rx2txparlb_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_bshihyst_attr == SERDES_IP_LANE_L3_CFG_BSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_bstxdrv_levn_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_bstxdrv_levnm1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_bstxdrv_levnp1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_bstxdrv_levnp2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_calsqlchosc_locovren_attr == SERDES_IP_LANE_L3_CFG_CALSQLCHOSC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_calsqlchosc_trimcode_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_cdrclkstat_locovren_attr == SERDES_IP_LANE_L3_CFG_CDRCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_cdrclkstat_ready_locovr_attr == SERDES_IP_LANE_L3_CFG_CDRCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_etrregrxcdrclk_ready_attr == SERDES_IP_LANE_L3_CFG_ETRREGRXCDRCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_laneckm_avg_en_attr == SERDES_IP_LANE_L3_CFG_LANECKM_AVG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_laneckm_clk_en_attr == SERDES_IP_LANE_L3_CFG_LANECKM_CLK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_laneckm_continuous_attr == SERDES_IP_LANE_L3_CFG_LANECKM_CONTINUOUS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_laneckm_dig_meas_en_attr == SERDES_IP_LANE_L3_CFG_LANECKM_DIG_MEAS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_laneckm_dig_meas_err_clr_attr == SERDES_IP_LANE_L3_CFG_LANECKM_DIG_MEAS_ERR_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_laneckm_en_attr == SERDES_IP_LANE_L3_CFG_LANECKM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_laneckm_max_thr_attr == 25'd33554431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_laneckm_meas_ck_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_laneckm_ref_ck_div_ratio_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_laneckm_result_clr_attr == SERDES_IP_LANE_L3_CFG_LANECKM_RESULT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_laneckm_start_attr == SERDES_IP_LANE_L3_CFG_LANECKM_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_laneckm_wdt_interval_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_laneckm_win_thr_ref_attr == 25'd16777215
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_lanepcs_locovren_attr == SERDES_IP_LANE_L3_CFG_LANEPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_lanepcs_mode_locovr_attr == SERDES_IP_LANE_L3_CFG_LANEPCS_MODE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_laneperfmon_compare_val_start_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_laneperfmon_compare_val_stop_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_laneperfmon_en_attr == SERDES_IP_LANE_L3_CFG_LANEPERFMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_laneperfmon_mask_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_lanepmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_lanepmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_lanepmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_lanepmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_lanepmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_lanepmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_lb_cdrclk2txen_locovr_attr == SERDES_IP_LANE_L3_CFG_LB_CDRCLK2TXEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_lb_cdrclkdiven_attr == SERDES_IP_LANE_L3_CFG_LB_CDRCLKDIVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_lb_cdrdivclk2exten_attr == SERDES_IP_LANE_L3_CFG_LB_CDRDIVCLK2EXTEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_lb_cdrdivclk2txen_attr == SERDES_IP_LANE_L3_CFG_LB_CDRDIVCLK2TXEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_lb_hsclk2cdrdiven_attr == SERDES_IP_LANE_L3_CFG_LB_HSCLK2CDRDIVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_lb_locovren_attr == SERDES_IP_LANE_L3_CFG_LB_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_lb_parrx2txtimeden_locovr_attr == SERDES_IP_LANE_L3_CFG_LB_PARRX2TXTIMEDEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_lb_pllfbclk2cdrrefclken_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_lb_pllfbclk2cdrrefclken_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_lb_pllfbclk2cdrrefclken_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_lb_pllfbclk2cdrrefclken_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_lb_pllfbclk2cdrrefclken_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_lb_rx2txuntimeden_attr == SERDES_IP_LANE_L3_CFG_LB_RX2TXUNTIMEDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_lb_rxwordck2pcstxwordcken_attr == SERDES_IP_LANE_L3_CFG_LB_RXWORDCK2PCSTXWORDCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_lb_tx2rxbuftimeden_lsb_locovr_attr == SERDES_IP_LANE_L3_CFG_LB_TX2RXBUFTIMEDEN_LSB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_lb_tx2rxbuftimeden_msb_locovr_attr == SERDES_IP_LANE_L3_CFG_LB_TX2RXBUFTIMEDEN_MSB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_lb_tx2rxiotimeden_attr == SERDES_IP_LANE_L3_CFG_LB_TX2RXIOTIMEDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_lfps_det_locovr_attr == SERDES_IP_LANE_L3_CFG_LFPS_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_lfps_locovren_attr == SERDES_IP_LANE_L3_CFG_LFPS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_lfps_out_en_attr == SERDES_IP_LANE_L3_CFG_LFPS_OUT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_pcslfps_en_locovr_attr == SERDES_IP_LANE_L3_CFG_PCSLFPS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_pcslfps_locovren_attr == SERDES_IP_LANE_L3_CFG_PCSLFPS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_pcsrx_dme_en_locovr_attr == SERDES_IP_LANE_L3_CFG_PCSRX_DME_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_pcsrx_locovren_attr == SERDES_IP_LANE_L3_CFG_PCSRX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_pcsrxbist_locovren_attr == SERDES_IP_LANE_L3_CFG_PCSRXBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_pcsrxbist_modesel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_pcstx_beaconen_locovr_attr == SERDES_IP_LANE_L3_CFG_PCSTX_BEACONEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_pcstx_locovren_attr == SERDES_IP_LANE_L3_CFG_PCSTX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_polarity_rx_attr == SERDES_IP_LANE_L3_CFG_POLARITY_RX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_polarity_tx_attr == SERDES_IP_LANE_L3_CFG_POLARITY_TX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rx_cmn_on_state_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rx_fastregpwrup_en_attr == SERDES_IP_LANE_L3_CFG_RX_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rx_frac_mode_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rx_on_state_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rx_pg_disable_attr == SERDES_IP_LANE_L3_CFG_RX_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rx_synth_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rx_synth_sel_amode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rx_synth_sel_bmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rx_synth_sel_cmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rx_synth_sel_dmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rx_synth_sel_emode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxadc_req_attr == SERDES_IP_LANE_L3_CFG_RXADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxagc_dccoupleen_attr == SERDES_IP_LANE_L3_CFG_RXAGC_DCCOUPLEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxaprobe_addr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxaprobe_lastmux_isolate_attr == SERDES_IP_LANE_L3_CFG_RXAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxaprobeadc_current_direction_attr == SERDES_IP_LANE_L3_CFG_RXAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxaprobeadc_resistor_enable_attr == SERDES_IP_LANE_L3_CFG_RXAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxbias_iccadj_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxbias_icvadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxbias_locovren_attr == SERDES_IP_LANE_L3_CFG_RXBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxbias_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxbist_burst_four_errtype_attr == SERDES_IP_LANE_L3_CFG_RXBIST_BURST_FOUR_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxbist_burst_one_errtype_attr == SERDES_IP_LANE_L3_CFG_RXBIST_BURST_ONE_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxbist_burst_three_errtype_attr == SERDES_IP_LANE_L3_CFG_RXBIST_BURST_THREE_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxbist_burst_two_errtype_attr == SERDES_IP_LANE_L3_CFG_RXBIST_BURST_TWO_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxbist_cdrlock2data_bypass_attr == SERDES_IP_LANE_L3_CFG_RXBIST_CDRLOCK2DATA_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxbist_cdrlock2data_postamble_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxbist_clear_errcount_attr == SERDES_IP_LANE_L3_CFG_RXBIST_CLEAR_ERRCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxbist_err_en_attr == SERDES_IP_LANE_L3_CFG_RXBIST_ERR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxbist_err_trig_type_attr == SERDES_IP_LANE_L3_CFG_RXBIST_ERR_TRIG_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxbist_errmask_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxbist_errtype_attr == SERDES_IP_LANE_L3_CFG_RXBIST_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxbist_firsterr_type_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxbist_lockchk_count_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxbist_maxbitcnt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxbist_mostrecent_err_attr == SERDES_IP_LANE_L3_CFG_RXBIST_MOSTRECENT_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxbist_relock_itercount_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxbist_seed_attr == 31'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxbist_status_hold_attr == SERDES_IP_LANE_L3_CFG_RXBIST_STATUS_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxbitslip_locovr_attr == SERDES_IP_LANE_L3_CFG_RXBITSLIP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxbitslip_locovren_attr == SERDES_IP_LANE_L3_CFG_RXBITSLIP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxbscan_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxbshicm_attr == SERDES_IP_LANE_L3_CFG_RXBSHICM_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalcdrfbdiv_div2_bypass_muxd0_attr == SERDES_IP_LANE_L3_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalcdrfbdiv_div2_bypass_muxd1_attr == SERDES_IP_LANE_L3_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalcdrfbdiv_div2_bypass_muxd2_attr == SERDES_IP_LANE_L3_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalcdrfbdiv_div2_bypass_muxd3_attr == SERDES_IP_LANE_L3_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalcdrfbdiv_div2_bypass_muxd4_attr == SERDES_IP_LANE_L3_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalduty_iclk_gray_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalduty_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTY_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalduty_qclk_gray_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalduty_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutybg_abort_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutybg_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutybg_ready_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycomp_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycomp_offset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_finish_side_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_init_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_initval_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_invert_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_round_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_runcount_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_signmagen_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsmout_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsmout_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_disable_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCTRL_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_i_div1_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_i_div2_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_i_div4_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_i_div8_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_q_div1_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_q_div2_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_q_div4_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_q_div8_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_bg_en_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_bg_one_step_cal_en_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_finish_side_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_i_polarity_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_I_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_i_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_I_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_init_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_q_polarity_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_Q_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_q_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_Q_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_round_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_runcount_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_signmagen_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_comp_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEAS_COMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_comp_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEAS_COMP_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_i_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEAS_I_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_i_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEAS_I_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_q_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEAS_Q_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_q_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEAS_Q_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeasout_comp_ack_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEASOUT_COMP_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeasout_comp_erravg_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEASOUT_COMP_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeasout_i_ack_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEASOUT_I_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeasout_i_erravg_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEASOUT_I_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeasout_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeasout_q_ack_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEASOUT_Q_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeasout_q_erravg_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEASOUT_Q_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutystat_done_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaldutystat_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_centerfreq_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_end_delay_attr == 9'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_hscount_muxd0_attr == 8'd181
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_hscount_muxd1_attr == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_hscount_muxd2_attr == 8'd180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_hscount_muxd3_attr == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_hscount_muxd4_attr == 8'd206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_initval_centerfreq_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_initval_fosc_attr == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_centerfreq_finish_side_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_CENTERFREQ_FINISH_SIDE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_centerfreq_to_fosc_offset_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_centerfreqen_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_CENTERFREQEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_centerfreqoffset_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_fosc_finishside_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_FOSC_FINISHSIDE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_foscen_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_FOSCEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_foscoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_init_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_invert_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_lpfax_calfosccoarse_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_lpfax_calfoscfine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_lpfax_centerfreqcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_lpfax_centerfreqfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_runcount_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_signmagen_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_vcorepen_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_VCOREPEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsmout_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsmout_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_count_muxd0_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_count_muxd1_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_count_muxd2_attr == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_count_muxd3_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_count_muxd4_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_dlycount_attr == 9'd68
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeasout_clear_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCMEASOUT_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeasout_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeasout_start_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCMEASOUT_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscval_int_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscval_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalintsval_int_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalintsval_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALINTSVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaloffsetfsm_init_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaloffsetfsm_init_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaloffsetfsm_init_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALOFFSETFSM_INIT_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaloffsetfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcaloffsetfsmout_input_en_attr == SERDES_IP_LANE_L3_CFG_RXCALOFFSETFSMOUT_INPUT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_duty_i_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_duty_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_dutycomp_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_foscfsm_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_offsetfsm_init_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_regopampoffset_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_rxppm_lockstatus_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_sqlch_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_sqlchosc_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_synthppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_voscregopampoffset_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_duty_i_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_duty_q_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_dutycomp_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_foscfsm_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_offsetfsm_init_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_rxppm_lockstatus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_sqlch_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_sqlchosc_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_synthppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_voscregopampoffset_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffset_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_finish_side_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_round_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_runcount_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_signmagen_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchfsm_clear_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchfsm_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchfsmout_caldone_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHFSMOUT_CALDONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchfsmout_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_codeoffset_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_finish_side_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHOSCFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_init_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHOSCFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_initval_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_invert_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHOSCFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHOSCFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHOSCFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_round_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHOSCFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_runcount_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHOSCFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscmeas_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHOSCMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscmeas_ref_cnt_attr == 10'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscmeas_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHOSCMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscmeas_settle_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscmeas_smpl_cnt_attr == 10'd144
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvbiascap_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALVBIASCAP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvbiascap_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALVBIASCAP_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvcoopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvcoopampoffsetmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvcoopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvcoopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffset_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffset_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_codeoffset_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_finish_side_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_initval_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_invert_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_lpfaxcoarse_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_round_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_runcount_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETFSM_RUNCOUNT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_signmagen_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsmout_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsmout_runcount_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETFSMOUT_RUNCOUNT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetmeas_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffset_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALVOSCREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALVOSCREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L3_CFG_RXCALVOSCREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALVOSCREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALVOSCREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALVOSCREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALVOSCREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALVOSCREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALVOSCREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrdiv_local_en_attr == SERDES_IP_LANE_L3_CFG_RXCDRDIV_LOCAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdiv_moddiv_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdiv_moddiv_muxd1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdiv_moddiv_muxd2_attr == 4'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdiv_moddiv_muxd3_attr == 4'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdiv_moddiv_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdivslip_mdiv_muxd0_attr == 9'd194
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdivslip_mdiv_muxd1_attr == 9'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdivslip_mdiv_muxd2_attr == 9'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdivslip_mdiv_muxd3_attr == 9'd66
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdivslip_mdiv_muxd4_attr == 9'd210
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrpfd_forcedn_attr == SERDES_IP_LANE_L3_CFG_RXCDRPFD_FORCEDN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrpfd_forceen_attr == SERDES_IP_LANE_L3_CFG_RXCDRPFD_FORCEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrpfd_forceup_attr == SERDES_IP_LANE_L3_CFG_RXCDRPFD_FORCEUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrpfd_propgain_attr == SERDES_IP_LANE_L3_CFG_RXCDRPFD_PROPGAIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrpfd_pulsewidth_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrphd_asym_override_ignore_attr == SERDES_IP_LANE_L3_CFG_RXCDRPHD_ASYM_OVERRIDE_IGNORE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrphd_bitshift_en_attr == SERDES_IP_LANE_L3_CFG_RXCDRPHD_BITSHIFT_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrphd_forcedn_attr == SERDES_IP_LANE_L3_CFG_RXCDRPHD_FORCEDN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrphd_forceen_attr == SERDES_IP_LANE_L3_CFG_RXCDRPHD_FORCEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrphd_forceup_attr == SERDES_IP_LANE_L3_CFG_RXCDRPHD_FORCEUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrphdrate_doublerate2s2p_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCDRPHDRATE_DOUBLERATE2S2P_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrphdrate_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCDRPHDRATE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrrefck_refdiv_muxd0_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrrefck_refdiv_muxd1_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrrefck_refdiv_muxd2_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrrefck_refdiv_muxd3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrrefck_refdiv_muxd4_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_biastop_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_biastopbypass_attr == SERDES_IP_LANE_L3_CFG_RXCDRVCO_BIASTOPBYPASS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_datapropgain_high_attr == 5'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_datapropgain_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_datapropgain_low_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_ff_ovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_ff_ovr_en_attr == SERDES_IP_LANE_L3_CFG_RXCDRVCO_FF_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_fil_short_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_flickerdegen_attr == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_gmfoscshort_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCDRVCO_GMFOSCSHORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_intf_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_intf_fil_short_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_intrj_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCDRVCO_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_refpropgain_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_refpropgain_nom_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxclk_cdrfb_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCLK_CDRFB_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxclk_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxclk_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdat_nrz_64b80b_bcword_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdata_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXDATA_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdata_locovren_attr == SERDES_IP_LANE_L3_CFG_RXDATA_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdatapath_locovren_attr == SERDES_IP_LANE_L3_CFG_RXDATAPATH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdatapath_on_state_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdatapath_ready_locovr_attr == SERDES_IP_LANE_L3_CFG_RXDATAPATH_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdfe_datatap_vcasc_attr == 4'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdfe_dfebiasadj_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdfe_nbiasctle_en_attr == SERDES_IP_LANE_L3_CFG_RXDFE_NBIASCTLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdfe_vcasc_sel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdfeterm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXDFETERM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdfeterm_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdfeyadjdac_datamid_edge_coarse_en_attr == SERDES_IP_LANE_L3_CFG_RXDFEYADJDAC_DATAMID_EDGE_COARSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdfeyadjdac_datatopbot_aux_coarse_en_attr == SERDES_IP_LANE_L3_CFG_RXDFEYADJDAC_DATATOPBOT_AUX_COARSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_accum_mon_en_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_ACCUM_MON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_accum_mon_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_bypasscdrpdetupdnsmpl_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_bypassenfosc_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_BYPASSENFOSC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_bypassenints_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_BYPASSENINTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_bypassenupdnsmpl_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_BYPASSENUPDNSMPL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_bypassfosc_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_bypasspllpfdupdnsmpl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_bypassrxints_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_data2pll_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_deltasigmode_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_DELTASIGMODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_fastref_muxd0_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_FASTREF_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_fastref_muxd1_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_FASTREF_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_fastref_muxd2_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_FASTREF_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_fastref_muxd3_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_FASTREF_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_fastref_muxd4_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_FASTREF_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_fosc_mod_bypass_en_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_FOSC_MOD_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_fosc_sample_pedge_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_FOSC_SAMPLE_PEDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gain_step_on_lock_recovery_en_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_GAIN_STEP_ON_LOCK_RECOVERY_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gaindelaycount_init_attr == 9'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gaindelaycount_pow2_muxd0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gaindelaycount_pow2_muxd1_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gaindelaycount_pow2_muxd2_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gaindelaycount_pow2_muxd3_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gaindelaycount_pow2_muxd4_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2ref_pow2_muxd0_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2ref_pow2_muxd1_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2ref_pow2_muxd2_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2ref_pow2_muxd3_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2ref_pow2_muxd4_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainunlocked_pow2_muxd0_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainunlocked_pow2_muxd1_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainunlocked_pow2_muxd2_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainunlocked_pow2_muxd3_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainunlocked_pow2_muxd4_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_initintegrator_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_INITINTEGRATOR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_initmodulator_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_INITMODULATOR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_deltasig_mode_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_INTS_DELTASIG_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_freeze_en_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_INTS_FREEZE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gaindelaycount_pow2_muxd0_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gaindelaycount_pow2_muxd1_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gaindelaycount_pow2_muxd2_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gaindelaycount_pow2_muxd3_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gaindelaycount_pow2_muxd4_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd0_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd1_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd2_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd3_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd4_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd0_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd1_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd2_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd3_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd4_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainunlocked_pow2_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainunlocked_pow2_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainunlocked_pow2_muxd2_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainunlocked_pow2_muxd3_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainunlocked_pow2_muxd4_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_guardband_hi_attr == 8'd200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_guardband_lo_attr == 8'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_loop_sel_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_INTS_LOOP_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_mod_bypass_en_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_INTS_MOD_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_mod_load_pedge_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_INTS_MOD_LOAD_PEDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_step_to_integer_en_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_INTS_STEP_TO_INTEGER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_jit_length_attr == 18'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_jit_mode_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_JIT_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_modck_ctrl_en_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_MODCK_CTRL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_pll2data_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_restore_cntr_attr == 9'd258
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_store_cntr_attr == 16'd258
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpif_trnsfrdelay_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpiffreeze_inten_attr == SERDES_IP_LANE_L3_CFG_RXDPIFFREEZE_INTEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdpiffreeze_moden_attr == SERDES_IP_LANE_L3_CFG_RXDPIFFREEZE_MODEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxdutyselpolarity_attr == SERDES_IP_LANE_L3_CFG_RXDUTYSELPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxflxgate_force_rxeq_gate_locovr_attr == SERDES_IP_LANE_L3_CFG_RXFLXGATE_FORCE_RXEQ_GATE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxflxgate_locovren_attr == SERDES_IP_LANE_L3_CFG_RXFLXGATE_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxfoscstat_done_locovr_attr == SERDES_IP_LANE_L3_CFG_RXFOSCSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxfoscstat_locovren_attr == SERDES_IP_LANE_L3_CFG_RXFOSCSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxfsm_cken_ovr_attr == SERDES_IP_LANE_L3_CFG_RXFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxfsm_cken_ovren_attr == SERDES_IP_LANE_L3_CFG_RXFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxints_prev_votes_hold_en_attr == SERDES_IP_LANE_L3_CFG_RXINTS_PREV_VOTES_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxlanepam_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXLANEPAM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxlanepam_locovren_attr == SERDES_IP_LANE_L3_CFG_RXLANEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxlock2datatmr_attr == 8'd240
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxlock2datatmr_short_attr == 8'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxntl_changeref_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxntl_changeref_val_locovr_attr == SERDES_IP_LANE_L3_CFG_RXNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxntl_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxntl_en_attr == SERDES_IP_LANE_L3_CFG_RXNTL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxntl_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxntl_locovren_attr == SERDES_IP_LANE_L3_CFG_RXNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxntl_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxntl_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxntl_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxntl_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxntl_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxntl_rxm_charge_up_locovr_attr == SERDES_IP_LANE_L3_CFG_RXNTL_RXM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxntl_rxm_pull_dn_locovr_attr == SERDES_IP_LANE_L3_CFG_RXNTL_RXM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxntl_rxm_sense_locovr_attr == SERDES_IP_LANE_L3_CFG_RXNTL_RXM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxntl_rxp_charge_up_locovr_attr == SERDES_IP_LANE_L3_CFG_RXNTL_RXP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxntl_rxp_pull_dn_locovr_attr == SERDES_IP_LANE_L3_CFG_RXNTL_RXP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxntl_rxp_sense_locovr_attr == SERDES_IP_LANE_L3_CFG_RXNTL_RXP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxntl_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_acc_freeze_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_ACC_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_cdrlock2data_gater_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_cdrlock2data_gater_hold_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_cdrlock2data_gater_ovrd_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_cdrlock2datatmr_optcl_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_cdrlock2datatmr_optcl_sel_ovrd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_enter_lock2data_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_ENTER_LOCK2DATA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_enter_lock2data_hold_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_ENTER_LOCK2DATA_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_exit_lock2data_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_EXIT_LOCK2DATA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_exit_lock2data_hold_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_EXIT_LOCK2DATA_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_force_lock2data_ovrd_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_FORCE_LOCK2DATA_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_force_lock2ref_ovrd_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_FORCE_LOCK2REF_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_hold_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_hold_timer_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_intf_ovrd_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_INTF_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_intf_ovrd_type_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_INTF_OVRD_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_mod_freeze_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_MOD_FREEZE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_ovrd_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_ppm_detect_freeze_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_PPM_DETECT_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_ppm_detect_freeze_ovrd_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_PPM_DETECT_FREEZE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_ppm_detect_hold_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_PPM_DETECT_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_prop_freeze_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_PROP_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_prop_freeze_ovrd_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_PROP_FREEZE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_rxdata_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_RXDATA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_skip_init_lock2data_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_SKIP_INIT_LOCK2DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxpam_bitorder_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxpam_gray_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXPAM_GRAY_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxpam_locovren_attr == SERDES_IP_LANE_L3_CFG_RXPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxpam_precode_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXPAM_PRECODE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_muxd0_attr == 7'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_p5_muxd0_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIV_P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_p5_muxd1_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIV_P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_p5_muxd2_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIV_P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_p5_muxd3_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIV_P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_p5_muxd4_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIV_P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdivclken_muxd0_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIVCLKEN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdivclken_muxd1_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIVCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdivclken_muxd2_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIVCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdivclken_muxd3_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIVCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdivclken_muxd4_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIVCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxpcsbist_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXPCSBIST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxpcsbist_locovren_attr == SERDES_IP_LANE_L3_CFG_RXPCSBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxphd_gain_hold_en_attr == SERDES_IP_LANE_L3_CFG_RXPHD_GAIN_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxphd_gain_zero_locovr_attr == SERDES_IP_LANE_L3_CFG_RXPHD_GAIN_ZERO_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxphd_locovren_attr == SERDES_IP_LANE_L3_CFG_RXPHD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxphd_majvote_basegain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxphd_majvote_en_attr == SERDES_IP_LANE_L3_CFG_RXPHD_MAJVOTE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxphd_mute_cntr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxphd_nrz8b10b_pam16b20b_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxphd_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxphd_pam_transition_sel_attr == SERDES_IP_LANE_L3_CFG_RXPHD_PAM_TRANSITION_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxphd_sign_invert_attr == SERDES_IP_LANE_L3_CFG_RXPHD_SIGN_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxpostdiv_wait_for_lock_disable_attr == SERDES_IP_LANE_L3_CFG_RXPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxppm_freq_max_offset_h_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxppm_freq_max_offset_l_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxppm_freq_ref_cnt_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxppm_lockstatus_locovr_attr == SERDES_IP_LANE_L3_CFG_RXPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxppm_lockstatus_synthlcfast_en_attr == SERDES_IP_LANE_L3_CFG_RXPPM_LOCKSTATUS_SYNTHLCFAST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxppm_lockstatus_synthlcmed_en_attr == SERDES_IP_LANE_L3_CFG_RXPPM_LOCKSTATUS_SYNTHLCMED_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxppm_lockstatus_synthlcslow_en_attr == SERDES_IP_LANE_L3_CFG_RXPPM_LOCKSTATUS_SYNTHLCSLOW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxppm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxppm_ppmdriftcount_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxppm_ppmdriftmax_attr == 16'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxppm_status_hold_attr == SERDES_IP_LANE_L3_CFG_RXPPM_STATUS_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxppm_unlock_clear_attr == SERDES_IP_LANE_L3_CFG_RXPPM_UNLOCK_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_fast_muxd0_attr == 16'd1188
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_fast_muxd1_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_fast_muxd2_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_fast_muxd3_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_fast_muxd4_attr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_muxd0_attr == 16'd1188
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_muxd1_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_muxd2_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_muxd3_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_muxd4_attr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxppmctrl_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXPPMCTRL_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxppmctrl_locovren_attr == SERDES_IP_LANE_L3_CFG_RXPPMCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxppmlockstat_locovren_attr == SERDES_IP_LANE_L3_CFG_RXPPMLOCKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxppmlockstat_sticky_locovr_attr == SERDES_IP_LANE_L3_CFG_RXPPMLOCKSTAT_STICKY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxppmtmr_locovren_attr == SERDES_IP_LANE_L3_CFG_RXPPMTMR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxppmtmr_watchdogtmr_sel_locovr_attr == SERDES_IP_LANE_L3_CFG_RXPPMTMR_WATCHDOGTMR_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_cal_clear_delay_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_clk_chk_disable_attr == SERDES_IP_LANE_L3_CFG_RXRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_clk_delay_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_etr_on_delay_attr == 12'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_locovren_attr == SERDES_IP_LANE_L3_CFG_RXRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxreg_lev_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxreg_toggle_reset_on_rate_change_en_attr == SERDES_IP_LANE_L3_CFG_RXREG_TOGGLE_RESET_ON_RATE_CHANGE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxreg_vreg_bypass_attr == SERDES_IP_LANE_L3_CFG_RXREG_VREG_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_en_b_attr == SERDES_IP_LANE_L3_CFG_RXRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s0q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s0q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s2q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s2q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s2q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s2q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s2q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s2q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s2q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s3q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s3q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s3q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s3q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s3q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s3q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s3q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s3q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s4q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s4q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s5q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_entry4_attr == 13'd78
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_entry5_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_entry6_attr == 13'd1406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s0q2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s0q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s1q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s1q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s1q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s1q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s1q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s1q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s2q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s2q2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s2q3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s2q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s2q5_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s2q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s2q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s3q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s3q1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s3q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s3q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s3q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s3q5_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s3q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s3q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s4q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s4q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s5q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_aetrrx_cdrfbdivcken_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_AETRRX_CDRFBDIVCKEN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_aetrrx_cdrfbdivcken_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_AETRRX_CDRFBDIVCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_aetrrx_cdrmoddivcken_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_AETRRX_CDRMODDIVCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_aetrrx_cdrmoddivcken_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_AETRRX_CDRMODDIVCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_aetrrx_termhiz_en_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_AETRRX_TERMHIZ_EN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_aetrrx_termhiz_en_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_AETRRX_TERMHIZ_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_aetrsynth_pcspostdivclksel_ovr_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_AETRSYNTH_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_aetrsynth_pcspostdivclksel_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_AETRSYNTH_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_adc_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_adc_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_auxcomp_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_AUXCOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_auxcomp_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_AUXCOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_bias_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_bias_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_BIAS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_ctlecomp_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_CTLECOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_ctlecomp_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_CTLECOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_datfbdiv_b_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DATFBDIV_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_datfbdiv_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DATFBDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_dfe_bias_b_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DFE_BIAS_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_dfe_bias_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DFE_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_dfe_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DFE_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_dfe_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DFE_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_dfe_yadj_b_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DFE_YADJ_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_dfe_yadj_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DFE_YADJ_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_duty_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DUTY_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_duty_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DUTY_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_hifreqagc_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_HIFREQAGC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_hifreqagc_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_HIFREQAGC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_ntl_b_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_ntl_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_reg_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_reg_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_vco_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_VCO_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_vco_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_VCO_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_voscreg_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_VOSCREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_voscreg_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_VOSCREG_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_adc_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_adc_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_cdrfbdiv_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_CDRFBDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_cdrfbdiv_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_CDRFBDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_pdet_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_PDET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_pdet_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_PDET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_pfd_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_PFD_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_pfd_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_PFD_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_refdiv_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_refdiv_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_reg_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_reg_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_s2pa_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_S2PA_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_s2pa_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_S2PA_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_s2pb_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_S2PB_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_s2pb_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_S2PB_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_vco_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_VCO_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_vco_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_VCO_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_voscreg_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_VOSCREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_voscreg_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_VOSCREG_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstsynth_postdiv_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTSYNTH_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstsynth_postdiv_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTSYNTH_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_drstrx_dpif_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_DRSTRX_DPIF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_drstrx_dpif_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_DRSTRX_DPIF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_drstrx_ppm_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_DRSTRX_PPM_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_drstrx_ppm_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_DRSTRX_PPM_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_cdrlock2data_locovr_attr == SERDES_IP_LANE_L3_CFG_RXSIGDET_CDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_diglfpsdeten_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_diglfpsdeten_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_diglfpsdeten_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_diglfpsdeten_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_diglfpsdeten_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrancnten_muxd0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrancnten_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrancnten_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrancnten_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrancnten_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrancnten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrandeten_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrandeten_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrandeten_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrandeten_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrandeten_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrandeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_eiosdeten_muxd0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_eiosdeten_muxd1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_eiosdeten_muxd2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_eiosdeten_muxd3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_eiosdeten_muxd4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_eiosdeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_enable_attr == SERDES_IP_LANE_L3_CFG_RXSIGDET_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_fastlock_winsize_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_leveldeten_muxd0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_leveldeten_muxd1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_leveldeten_muxd2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_leveldeten_muxd3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_leveldeten_muxd4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_leveldeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_lfpsexit_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_locovren_attr == SERDES_IP_LANE_L3_CFG_RXSIGDET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_ppmdeten_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_ppmdeten_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_ppmdeten_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_ppmdeten_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_ppmdeten_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_ppmdeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_rxeq_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_rxeqen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_rxeqen_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_rxleveldet_debounce_dncount_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_rxleveldet_debounce_flush_en_attr == SERDES_IP_LANE_L3_CFG_RXSIGDET_RXLEVELDET_DEBOUNCE_FLUSH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_rxleveldet_debounce_upcount_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_sigdet_debounce_attr == SERDES_IP_LANE_L3_CFG_RXSIGDET_SIGDET_DEBOUNCE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_tmr_clksel_attr == SERDES_IP_LANE_L3_CFG_RXSIGDET_TMR_CLKSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_toggle_count_en_attr == SERDES_IP_LANE_L3_CFG_RXSIGDET_TOGGLE_COUNT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_toggle_count_pause_attr == SERDES_IP_LANE_L3_CFG_RXSIGDET_TOGGLE_COUNT_PAUSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_toggle_monitor_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdetin_eiosdetectstat_locovr_attr == SERDES_IP_LANE_L3_CFG_RXSIGDETIN_EIOSDETECTSTAT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdetin_locovren_attr == SERDES_IP_LANE_L3_CFG_RXSIGDETIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdetin_ovrcdrlock2data_locovr_attr == SERDES_IP_LANE_L3_CFG_RXSIGDETIN_OVRCDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdetin_ovrencdrlock2data_locovr_attr == SERDES_IP_LANE_L3_CFG_RXSIGDETIN_OVRENCDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdetout_lock2data_noforce_ltr_locovr_attr == SERDES_IP_LANE_L3_CFG_RXSIGDETOUT_LOCK2DATA_NOFORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsigdetout_locovren_attr == SERDES_IP_LANE_L3_CFG_RXSIGDETOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxspare0_attr == 32'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxspare_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsqlchlfps_consec_one_thresh_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsqlchlfps_consec_zero_thresh_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsqlchlfps_cycle_thresh_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsqlchlfps_dat_bitorder_attr == SERDES_IP_LANE_L3_CFG_RXSQLCHLFPS_DAT_BITORDER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsqlchlfps_debounce_type_attr == SERDES_IP_LANE_L3_CFG_RXSQLCHLFPS_DEBOUNCE_TYPE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsqlchlfps_one_run_length_thresh_attr == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsqlchlfps_one_run_length_timeout_attr == 8'd103
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsqlchlfps_zero_run_length_thresh_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsqlchlfps_zero_run_length_timeout_attr == 8'd103
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsynthdiv_slowmed_en_muxd0_attr == SERDES_IP_LANE_L3_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsynthdiv_slowmed_en_muxd1_attr == SERDES_IP_LANE_L3_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsynthdiv_slowmed_en_muxd2_attr == SERDES_IP_LANE_L3_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsynthdiv_slowmed_en_muxd3_attr == SERDES_IP_LANE_L3_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxsynthdiv_slowmed_en_muxd4_attr == SERDES_IP_LANE_L3_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxterm_cal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxterm_coarse_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxterm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXTERM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxterm_modeselect_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxtermhiz_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXTERMHIZ_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxtermhiz_locovren_attr == SERDES_IP_LANE_L3_CFG_RXTERMHIZ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxvoscreg_bypass_vosc_attr == SERDES_IP_LANE_L3_CFG_RXVOSCREG_BYPASS_VOSC_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxvoscregopampoffsetctrl_sel_attr == SERDES_IP_LANE_L3_CFG_RXVOSCREGOPAMPOFFSETCTRL_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxvoscregopampoffseterr_locovren_attr == SERDES_IP_LANE_L3_CFG_RXVOSCREGOPAMPOFFSETERR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxvoscregopampoffseterr_sel_locovr_attr == SERDES_IP_LANE_L3_CFG_RXVOSCREGOPAMPOFFSETERR_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxvoscregvref_locovren_attr == SERDES_IP_LANE_L3_CFG_RXVOSCREGVREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_rxvoscregvref_sel_locovr_attr == SERDES_IP_LANE_L3_CFG_RXVOSCREGVREF_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlch_acqgain_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlch_acqtime_attr == 13'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlch_cal_quiet_locovr_attr == SERDES_IP_LANE_L3_CFG_SQLCH_CAL_QUIET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlch_cal_sel_locovr_attr == SERDES_IP_LANE_L3_CFG_SQLCH_CAL_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlch_calctrl_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlch_calen_locovr_attr == SERDES_IP_LANE_L3_CFG_SQLCH_CALEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlch_caltimer_attr == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlch_clkgate_locovr_attr == SERDES_IP_LANE_L3_CFG_SQLCH_CLKGATE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlch_cmshiften_attr == SERDES_IP_LANE_L3_CFG_SQLCH_CMSHIFTEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_acq_gain_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_acq_pct_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_cal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_clr_errlog_attr == SERDES_IP_LANE_L3_CFG_SQLCH_CONT_CLR_ERRLOG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_controller_mode_attr == SERDES_IP_LANE_L3_CFG_SQLCH_CONT_CONTROLLER_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_dis_attr == SERDES_IP_LANE_L3_CFG_SQLCH_CONT_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_pause_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_postcal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_precal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_quiet_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlch_lfps_en_attr == SERDES_IP_LANE_L3_CFG_SQLCH_LFPS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlch_locovren_attr == SERDES_IP_LANE_L3_CFG_SQLCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlch_ovrd_val_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlch_pkdet_freqsel_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlch_polarity_attr == SERDES_IP_LANE_L3_CFG_SQLCH_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlch_rdacen_attr == SERDES_IP_LANE_L3_CFG_SQLCH_RDACEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlch_thresh_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlch_time_out_attr == 16'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlch_vrefsel0_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlch_vrefsel1_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlch_vrefsel_ovr_en_attr == SERDES_IP_LANE_L3_CFG_SQLCH_VREFSEL_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlchdeb_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlchdeb_deb_cnt_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlchdeb_deb_status_cnt_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlchdeb_en_attr == SERDES_IP_LANE_L3_CFG_SQLCHDEB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlchdeb_ign_cnt_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlchdeb_sigdet_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlchdeb_thresh_cnt_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlchdebout_exit_good_debounced_locovr_attr == SERDES_IP_LANE_L3_CFG_SQLCHDEBOUT_EXIT_GOOD_DEBOUNCED_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlchdebout_exit_good_debounced_status_locovr_attr == SERDES_IP_LANE_L3_CFG_SQLCHDEBOUT_EXIT_GOOD_DEBOUNCED_STATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlchdebout_exit_good_locovr_attr == SERDES_IP_LANE_L3_CFG_SQLCHDEBOUT_EXIT_GOOD_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_sqlchdebout_locovren_attr == SERDES_IP_LANE_L3_CFG_SQLCHDEBOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_trancnt_off_attr == 10'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_trancnt_on_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_trancntout_det_locovr_attr == SERDES_IP_LANE_L3_CFG_TRANCNTOUT_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_trancntout_locovren_attr == SERDES_IP_LANE_L3_CFG_TRANCNTOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_trandet_ax_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_trandet_ay_attr == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_trandet_off_h_attr == 6'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_trandet_off_l_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_trandet_on_h_attr == 6'd39
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_trandet_on_l_attr == 6'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_trandetout_det_locovr_attr == SERDES_IP_LANE_L3_CFG_TRANDETOUT_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_trandetout_locovren_attr == SERDES_IP_LANE_L3_CFG_TRANDETOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_tx2rxlb_en_attr == SERDES_IP_LANE_L3_CFG_TX2RXLB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_tx2rxlb_init_offset_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_tx_cmn_on_state_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_tx_fastregpwrup_en_attr == SERDES_IP_LANE_L3_CFG_TX_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_tx_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_tx_pg_disable_attr == SERDES_IP_LANE_L3_CFG_TX_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_tx_synth_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_tx_synth_sel_amode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_tx_synth_sel_bmode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_tx_synth_sel_cmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_tx_synth_sel_dmode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_tx_synth_sel_emode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_tx_txdetrx_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txadc_req_attr == SERDES_IP_LANE_L3_CFG_TXADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txaprobe_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txaprobe_lastmux_isolate_attr == SERDES_IP_LANE_L3_CFG_TXAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txaprobeadc_current_direction_attr == SERDES_IP_LANE_L3_CFG_TXAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txaprobeadc_resistor_enable_attr == SERDES_IP_LANE_L3_CFG_TXAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txbdvdr_pma2pcstxworden_attr == SERDES_IP_LANE_L3_CFG_TXBDVDR_PMA2PCSTXWORDEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txbeacon_div_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txbeacon_sel_attr == SERDES_IP_LANE_L3_CFG_TXBEACON_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txbias_icc20uadj_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txbias_icc80uadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txbias_locovren_attr == SERDES_IP_LANE_L3_CFG_TXBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txbias_termcal_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txbist_biterror_en_attr == SERDES_IP_LANE_L3_CFG_TXBIST_BITERROR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txbist_locovren_attr == SERDES_IP_LANE_L3_CFG_TXBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txbist_modesel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txbist_oobmode_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txbist_oobtburst_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txbist_oobtcomrstinit_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txbist_oobtcomsas_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txbist_oobtcomwake_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txbist_seed_attr == 31'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_size_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf00_attr == 32'd1985229328
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf01_attr == 32'd4275878552
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf02_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf03_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf04_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf05_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf06_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf07_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf08_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf09_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txbit_select_muxd0_attr == SERDES_IP_LANE_L3_CFG_TXBIT_SELECT_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txbit_select_muxd1_attr == SERDES_IP_LANE_L3_CFG_TXBIT_SELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txbit_select_muxd2_attr == SERDES_IP_LANE_L3_CFG_TXBIT_SELECT_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txbit_select_muxd3_attr == SERDES_IP_LANE_L3_CFG_TXBIT_SELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txbit_select_muxd4_attr == SERDES_IP_LANE_L3_CFG_TXBIT_SELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txbti_data_replication_attr == SERDES_IP_LANE_L3_CFG_TXBTI_DATA_REPLICATION_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txbti_tx_idle_data_en_attr == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcal_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcal_tclkduty_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalduty_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalduty_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTY_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalduty_sel_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutybg_abort_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutybg_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutybg_ready_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutycomp_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutycomp_offset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_finish_side_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_init_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_initval_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_invert_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_req_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_round_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_runcount_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_signmagen_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsmout_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsmout_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompmeas_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompmeas_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompmeas_req_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompmeasout_ack_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPMEASOUT_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompmeasout_erravg_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPMEASOUT_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompmeasout_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_bg_en_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_bg_one_step_cal_en_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_finish_side_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_init_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_invert_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_req_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_round_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_runcount_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_signmagen_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeas_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeas_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeas_req_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeasout_ack_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYMEASOUT_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeasout_erravg_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYMEASOUT_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeasout_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutystat_done_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaldutystat_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalptr_pstate_duty_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalptr_pstate_dutycomp_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalptr_pstate_regopampoffset_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_duty_muxd0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_duty_muxd1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_duty_muxd2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_duty_muxd3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_duty_muxd4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_dutycomp_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_dutycomp_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_dutycomp_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_dutycomp_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_dutycomp_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_regopampoffset_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffset_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_finish_side_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_round_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_runcount_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_signmagen_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcaltclkdutyforce_div1_attr == SERDES_IP_LANE_L3_CFG_TXCALTCLKDUTYFORCE_DIV1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txcdrdiv_local_en_attr == SERDES_IP_LANE_L3_CFG_TXCDRDIV_LOCAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txclk_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txclk_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txclkgenmuxsel_txinternal_attr == SERDES_IP_LANE_L3_CFG_TXCLKGENMUXSEL_TXINTERNAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txdetectrx_thr_attr == 5'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeas_count_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeas_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXDETECTRXMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeas_locovren_attr == SERDES_IP_LANE_L3_CFG_TXDETECTRXMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeas_validdlycount_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeasin_locovren_attr == SERDES_IP_LANE_L3_CFG_TXDETECTRXMEASIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeasin_start_locovr_attr == SERDES_IP_LANE_L3_CFG_TXDETECTRXMEASIN_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeaspcs_locovren_attr == SERDES_IP_LANE_L3_CFG_TXDETECTRXMEASPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeaspcs_req_locovr_attr == SERDES_IP_LANE_L3_CFG_TXDETECTRXMEASPCS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeasval_locovren_attr == SERDES_IP_LANE_L3_CFG_TXDETECTRXMEASVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeasval_stat_locovr_attr == SERDES_IP_LANE_L3_CFG_TXDETECTRXMEASVAL_STAT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txdetrx_levn_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txdetrx_levnm1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txdetrx_levnp1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txdetrx_levnp2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txdrv_hizen_locovr_attr == SERDES_IP_LANE_L3_CFG_TXDRV_HIZEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txdrv_levn_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txdrv_levnm1_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txdrv_levnp1_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txdrv_levnp2_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txdrv_locovren_attr == SERDES_IP_LANE_L3_CFG_TXDRV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txdrv_refcken_attr == SERDES_IP_LANE_L3_CFG_TXDRV_REFCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txdrv_termref_attr == SERDES_IP_LANE_L3_CFG_TXDRV_TERMREF_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txdrvmute_locovr_attr == SERDES_IP_LANE_L3_CFG_TXDRVMUTE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txdrvmute_locovren_attr == SERDES_IP_LANE_L3_CFG_TXDRVMUTE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txduty_ctrl_disable_attr == SERDES_IP_LANE_L3_CFG_TXDUTY_CTRL_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txduty_pad_sense_en_attr == SERDES_IP_LANE_L3_CFG_TXDUTY_PAD_SENSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txdutycal_div16_en_attr == SERDES_IP_LANE_L3_CFG_TXDUTYCAL_DIV16_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txdutycal_div1_en_attr == SERDES_IP_LANE_L3_CFG_TXDUTYCAL_DIV1_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txdutycal_div2_en_attr == SERDES_IP_LANE_L3_CFG_TXDUTYCAL_DIV2_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txdutycal_div4_en_attr == SERDES_IP_LANE_L3_CFG_TXDUTYCAL_DIV4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txdutycal_div8_en_attr == SERDES_IP_LANE_L3_CFG_TXDUTYCAL_DIV8_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txfifo_elecidle_deskew_en_attr == SERDES_IP_LANE_L3_CFG_TXFIFO_ELECIDLE_DESKEW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txfifo_force_txidlebit1_zero_disable_attr == SERDES_IP_LANE_L3_CFG_TXFIFO_FORCE_TXIDLEBIT1_ZERO_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txfifo_kill_dly_10b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txfifo_kill_dly_16b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txfifo_kill_dly_20b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txfifo_kill_dly_32b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txfifo_kill_dly_40b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txfifo_kill_dly_64b_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txfifo_kill_dly_80b_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txfifo_kill_dly_8b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txfifo_kill_en_attr == SERDES_IP_LANE_L3_CFG_TXFIFO_KILL_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txfsm_cken_ovr_attr == SERDES_IP_LANE_L3_CFG_TXFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txfsm_cken_ovren_attr == SERDES_IP_LANE_L3_CFG_TXFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txfsm_main_on_state_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txl1d1_doze_ctrl_attr == SERDES_IP_LANE_L3_CFG_TXL1D1_DOZE_CTRL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txl1d1_txbias_ctrl_attr == SERDES_IP_LANE_L3_CFG_TXL1D1_TXBIAS_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txlanepam_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXLANEPAM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txlanepam_locovren_attr == SERDES_IP_LANE_L3_CFG_TXLANEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txmeaslatovrhd_meas_sel_attr == SERDES_IP_LANE_L3_CFG_TXMEASLATOVRHD_MEAS_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txmute_delay_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txntl_changeref_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txntl_changeref_val_locovr_attr == SERDES_IP_LANE_L3_CFG_TXNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txntl_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txntl_en_attr == SERDES_IP_LANE_L3_CFG_TXNTL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txntl_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txntl_locovren_attr == SERDES_IP_LANE_L3_CFG_TXNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txntl_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txntl_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txntl_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txntl_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txntl_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txntl_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txntl_txm_charge_up_locovr_attr == SERDES_IP_LANE_L3_CFG_TXNTL_TXM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txntl_txm_pull_dn_locovr_attr == SERDES_IP_LANE_L3_CFG_TXNTL_TXM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txntl_txm_sense_locovr_attr == SERDES_IP_LANE_L3_CFG_TXNTL_TXM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txntl_txp_charge_up_locovr_attr == SERDES_IP_LANE_L3_CFG_TXNTL_TXP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txntl_txp_pull_dn_locovr_attr == SERDES_IP_LANE_L3_CFG_TXNTL_TXP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txntl_txp_sense_locovr_attr == SERDES_IP_LANE_L3_CFG_TXNTL_TXP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txp2s_txwordsyncbypen_attr == SERDES_IP_LANE_L3_CFG_TXP2S_TXWORDSYNCBYPEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txpam_bitorder_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txpam_gray_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXPAM_GRAY_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txpam_locovren_attr == SERDES_IP_LANE_L3_CFG_TXPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txpam_precode_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXPAM_PRECODE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txpcs_locovren_attr == SERDES_IP_LANE_L3_CFG_TXPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txpcs_txenable_locovr_attr == SERDES_IP_LANE_L3_CFG_TXPCS_TXENABLE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txpcsbist_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXPCSBIST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txpcsbist_locovren_attr == SERDES_IP_LANE_L3_CFG_TXPCSBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txratewidth_clk_chk_disable_attr == SERDES_IP_LANE_L3_CFG_TXRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txratewidth_etr_on_delay_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txratewidth_locovren_attr == SERDES_IP_LANE_L3_CFG_TXRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txreg_toggle_pwrupacc_on_rate_change_en_attr == SERDES_IP_LANE_L3_CFG_TXREG_TOGGLE_PWRUPACC_ON_RATE_CHANGE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txreg_toggle_reset_on_rate_change_en_attr == SERDES_IP_LANE_L3_CFG_TXREG_TOGGLE_RESET_ON_RATE_CHANGE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txresetdel_sel_attr == SERDES_IP_LANE_L3_CFG_TXRESETDEL_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_en_b_attr == SERDES_IP_LANE_L3_CFG_TXRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s0q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s0q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s1q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s1q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s2q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s2q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s2q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s2q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s2q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s2q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s2q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s3q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s3q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s3q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s3q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s3q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s3q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s3q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s3q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s4q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s4q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s5q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s0q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s0q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s1q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s1q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s1q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s1q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s1q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s1q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s2q0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s2q1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s2q2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s2q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s2q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s2q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s2q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s2q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s3q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s3q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s3q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s3q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s3q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s3q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s3q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s3q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s4q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s4q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s5q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_dn_ptr0_s_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_up_ptr0_s_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_aetrtx_bitckdvdrcken_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_AETRTX_BITCKDVDRCKEN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_aetrtx_bitckdvdrcken_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_AETRTX_BITCKDVDRCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_aetrtx_regpwrupacc_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_AETRTX_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_aetrtx_regpwrupacc_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_AETRTX_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_adc_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_adc_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_drvdoze_b_ovr_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_DRVDOZE_B_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_drvdoze_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_DRVDOZE_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_duty_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_DUTY_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_duty_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_DUTY_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_ntl_b_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_ntl_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_p2s_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_P2S_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_p2s_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_P2S_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_reg_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_reg_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_arsttx_adc_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_ARSTTX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_arsttx_adc_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_ARSTTX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_arsttx_pma2pcstxword_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_ARSTTX_PMA2PCSTXWORD_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_arsttx_pma2pcstxword_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_ARSTTX_PMA2PCSTXWORD_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_arsttx_regreset_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_ARSTTX_REGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_arsttx_regreset_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_ARSTTX_REGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_arsttx_txdetectrx_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_ARSTTX_TXDETECTRX_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_arsttx_txdetectrx_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_ARSTTX_TXDETECTRX_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txrststate_hiz_en_attr == SERDES_IP_LANE_L3_CFG_TXRSTSTATE_HIZ_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txspare0_attr == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txspare_attr == 10'd384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txterm_coarse_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txtermtrim_locovren_attr == SERDES_IP_LANE_L3_CFG_TXTERMTRIM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txtermtrim_nmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txtermtrim_pmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txwclk_div_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txwclk_div_en_attr == SERDES_IP_LANE_L3_CFG_TXWCLK_DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txwclk_div_smpl_attr == SERDES_IP_LANE_L3_CFG_TXWCLK_DIV_SMPL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txwptr_init01_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txwptr_init02_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txwptr_init04_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txwptr_init08_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txwptr_init16_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txwptr_init32_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_l3_cfg_txwptr_init_rx2txparlb_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_dfeyadj_aging_cdrlock2data_loc_ov_attr == SERDES_IP_LANE_RXEQ_L0_CFG_DFEYADJ_AGING_CDRLOCK2DATA_LOC_OV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_dfeyadj_aging_cdrlock2data_loc_ov_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_DFEYADJ_AGING_CDRLOCK2DATA_LOC_OV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_dfeyadj_aging_div_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_dfeyadj_aging_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_DFEYADJ_AGING_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxagc_ctlecomp_filterbypass_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXAGC_CTLECOMP_FILTERBYPASS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxagc_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXAGC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxbgcal_calfsmmeas_dlycount_attr == 10'd392
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxbgcal_clear_mask_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxbgcal_fsmmaxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxbgcal_lpfax_coarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxbgcal_lpfax_fine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxbgcalorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxbgcalorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxbgcalorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_calbiasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_calbiasboost_use_lut_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_CALBIASBOOST_USE_LUT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_callbbiasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_callbbiasboost_use_lut_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_CALLBBIASBOOST_USE_LUT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlecomp_filterbypass_smplrcal_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_CTLECOMP_FILTERBYPASS_SMPLRCAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg1_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg2_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg3_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctleinput_probe_mux_smplrcal_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg1_probe_mux_en_smplrcal_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg1_state_en_smplrcal_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg1_state_en_tfrcal_stg1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg1_state_en_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg1_state_en_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg1_use_stg2code_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_CTLESTG1_USE_STG2CODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg2_probe_mux_en_smplrcal_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg2_state_en_smplrcal_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg2_state_en_tfrcal_stg1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg2_state_en_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg2_state_en_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg3_probe_mux_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg3_state_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg3_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg3_state_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg3_state_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_hifreqagc_n5targin_sel_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_HIFREQAGC_N5TARGIN_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_inputcmadjust_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_inputcmadjust_stg1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_inputcmadjust_stg2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_inputcmadjust_stg3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_sdimode_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_SDIMODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_smplroffset_aux0_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_smplroffset_aux1_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_smplroffset_d0_bot_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_smplroffset_d0_mid_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_smplroffset_d0_top_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_smplroffset_d1_bot_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_smplroffset_d1_mid_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_smplroffset_d1_top_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_tfrtrim_outen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_tfrtrim_outen_tfrcal_stg1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_tfrtrim_outen_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_tfrtrim_outen_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalalign_iqclk_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalalign_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALALIGN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctl_cal_abort_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALCTL_CAL_ABORT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctl_cal_type_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctl_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALCTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctl_post_delay_pow2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctl_pre_delay_pow2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecalctrl_input_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecalctrl_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALCTLECALCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecalctrl_stg1_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecalctrl_stg1_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecalctrl_stg2_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecalctrl_stg2_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecalctrl_stg3_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecalctrl_stg3_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecompoffset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecompoffset_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALCTLECOMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecompoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALCTLECOMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecompoffsetfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALCTLECOMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecompoffsetfsmout_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaldutybkgnd_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALDUTYBKGND_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaldutybkgnd_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALDUTYBKGND_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_biasboost_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_hf1deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_hf1resdcgain_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_hf2cap_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_hf2deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_hf2reszero_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_hf3deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_hf3resdcgain_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_hf4deq_gray_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALEQ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_ctlecmnmode_stg1_finish_side_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALFSM_CTLECMNMODE_STG1_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_ctlecmnmode_stg1_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_ctlecmnmode_stg2_finish_side_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALFSM_CTLECMNMODE_STG2_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_ctlecmnmode_stg2_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_ctlecmnmode_stg3_finish_side_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALFSM_CTLECMNMODE_STG3_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_ctlecmnmode_stg3_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_runcount_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_smplroffset_finish_side_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALFSM_SMPLROFFSET_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_smplroffset_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsmmeas_ctlecmnmode_stg1_invert_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALFSMMEAS_CTLECMNMODE_STG1_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsmmeas_ctlecmnmode_stg2_invert_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALFSMMEAS_CTLECMNMODE_STG2_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsmmeas_ctlecmnmode_stg3_invert_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALFSMMEAS_CTLECMNMODE_STG3_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsmmeas_smplroffset_invert_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALFSMMEAS_SMPLROFFSET_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_ctlecmnmode_stg1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_ctlecmnmode_stg2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_ctlecmnmode_stg3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_aux0_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_aux1_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_d0_bot_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_d0_mid_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_d0_top_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_d1_bot_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_d1_mid_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_d1_top_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_e0_lo_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_e1_lo_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeas_pow2count_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasin_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasin_req_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASIN_REQ_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasin_req_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASIN_REQ_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasin_req_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASIN_REQ_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasout_ack_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASOUT_ACK_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasout_ack_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASOUT_ACK_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasout_ack_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASOUT_ACK_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasout_avg_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASOUT_AVG_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasout_avg_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASOUT_AVG_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasout_avg_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASOUT_AVG_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasout_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaloffsetfsmout_auxdatacomp_offset_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALOFFSETFSMOUT_AUXDATACOMP_OFFSET_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaloffsetfsmout_boost_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALOFFSETFSMOUT_BOOST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaloffsetfsmout_edgecomp_offset_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALOFFSETFSMOUT_EDGECOMP_OFFSET_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaloffsetfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalset_cal_clear_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalset_cal_mode_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALSET_CAL_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalset_cal_req_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALSET_CAL_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalset_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalstat_cal_ack_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALSTAT_CAL_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalstat_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalsummerfsmout_comp_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALSUMMERFSMOUT_COMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalsummerfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALSUMMERFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcdrphd_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCDRPHD_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcdrphd_override_ignore_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCDRPHD_OVERRIDE_IGNORE_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_caloffset_range_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_calstg1offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_calstg1offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_calstg2offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_calstg2offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_calstg3offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_calstg3offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_dccouple_sigpath_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCTLE_DCCOUPLE_SIGPATH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_lbbiasboost_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCTLE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_stg1tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_stg2tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_stg3tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_tfrtrim_outmem_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCTLE_TFRTRIM_OUTMEM_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_tfrtrim_outpen_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCTLE_TFRTRIM_OUTPEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctledc_dccouple_tgate_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCTLEDC_DCCOUPLE_TGATE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctledc_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCTLEDC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxdfe_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXDFE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxdfe_tapgain_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxdfepam_enable_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXDFEPAM_ENABLE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxdfepam_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXDFEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxdpifjit_enb_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXDPIFJIT_ENB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxdpifjit_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXDPIFJIT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxdpifjit_offset_locovr_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqadj_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQADJ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqadj_yadjust_aux0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqadj_yadjust_aux1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqadj_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqadj_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqadj_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqadj_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqadj_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqadj_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqauxxor_amux_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqauxxor_dmux_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqauxxor_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQAUXXOR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcal2flx_pstate_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCAL2FLX_PSTATE_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcal2flx_rate_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCAL2FLX_RATE_MASK_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_16a_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_16b_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_16c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_16d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_16e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_1a_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_1b_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_1c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_1d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_1e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_2a_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_2b_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_2c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_2d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_2e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_4a_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_4b_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_4c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_4d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_4e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_8a_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_8b_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_8c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_8d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_8e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_16a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_16b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_16c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_16d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_16e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_1a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_1b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_1c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_1d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_1e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_2a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_2b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_2c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_2d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_2e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_4a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_4b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_4c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_4d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_4e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_8a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_8b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_8c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_8d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_8e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_16a_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_16b_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_16c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_16d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_16e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_1a_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_1b_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_1c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_1d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_1e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_2a_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_2b_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_2c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_2d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_2e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_4a_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_4b_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_4c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_4d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_4e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_8a_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_8b_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_8c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_8d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_8e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcals_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCALS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcals_offset_datasummer0_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcals_offset_datasummer0_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcals_offset_datasummer1_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcals_offset_datasummer1_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcals_offset_edgesummer0_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcals_offset_edgesummer0_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcals_offset_edgesummer1_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcals_offset_edgesummer1_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcdr_force_ltr_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCDR_FORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcdr_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCDR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqctl_clear_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCTL_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqctl_fg_run_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCTL_FG_RUN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqctlelut_hifreqagcres_ovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCTLELUT_HIFREQAGCRES_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqctlelut_hifreqvgagain_ovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCTLELUT_HIFREQVGAGAIN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqctls_oddeven_tapgain_sel_inv_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCTLS_ODDEVEN_TAPGAIN_SEL_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqctls_static_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCTLS_STATIC_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqdat_aux_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQDAT_AUX_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqdat_edge_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQDAT_EDGE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqdatactl_auxswap_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqdatactl_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQDATACTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqdatarate_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQDATARATE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqdatarate_rx_rate_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqdfeyadj_agingl2r_delay_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqdfeyadj_agingl2r_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQDFEYADJ_AGINGL2R_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqedgeadj_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEDGEADJ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqedgeadj_yadjust_edge0lo_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqedgeadj_yadjust_edge1lo_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm2flx_ehm_done_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHM2FLX_EHM_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm2flx_ehm_done_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHM2FLX_EHM_DONE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm2flx_ehm_err_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHM2FLX_EHM_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm2flx_ehm_err_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHM2FLX_EHM_ERR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm2flx_ehm_fom_locovr_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHM2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_data_extshift_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHM_DATA_EXTSHIFT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_distance_th_50p_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_distance_th_rate_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_err_mask_vf00_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_err_mask_vf01_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_event_rate_vf00_attr == 32'd67108864
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_event_rate_vf01_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_general_in_vf00_attr == 32'd5521424
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_general_in_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_lms_th_50p_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_lms_th_rate_attr == 20'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_mask_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_no_change_th_50p_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_no_change_th_rate_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_reflections_num_50p_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_reflections_num_rate_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_slicer_swap_cb_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHM_SLICER_SWAP_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_sym_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_sym_dly_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_tap_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_test_aux_slicer_val_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_test_hits_th_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjaux_ehm_yadjust_aux0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjaux_ehm_yadjust_aux1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjaux_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJAUX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjauxen_ehm_aux_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJAUXEN_EHM_AUX_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjauxen_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJAUXEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjauxltch_aux_yadj_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJAUXLTCH_AUX_YADJ_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjauxltch_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJAUXLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdata_ehm_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdata_ehm_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdata_ehm_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdata_ehm_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdata_ehm_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdata_ehm_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdata_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdataen_ehm_data_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJDATAEN_EHM_DATA_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdataen_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJDATAEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdataltch_data_yadj_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJDATALTCH_DATA_YADJ_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdataltch_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJDATALTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2ehm_ehm_run_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2EHM_EHM_RUN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2ehm_ehm_run_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2EHM_EHM_RUN_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2lms_coarse_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2LMS_COARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2lms_ctrl_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2LMS_CTRL_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2lms_dfecore_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2LMS_DFECORE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2lms_force_evrefupd_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2LMS_FORCE_EVREFUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2lms_freeze_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2LMS_FREEZE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2lms_incr_decr_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2LMS_INCR_DECR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2lms_mu_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2LMS_MU_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2lms_rst_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2LMS_RST_OVRDEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2ofc_ofc_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2OFC_OFC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2ofc_ofc_en_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2OFC_OFC_EN_OVRDEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx_pcs_rxeq_clr_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX_PCS_RXEQ_CLR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx_pcs_rxeq_start_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX_PCS_RXEQ_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx_pcs_rxeq_static_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX_PCS_RXEQ_STATIC_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx_rxrate2pcie1_map_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx_rxrate2pcie2_map_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx_rxrate2pcie3_map_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx_rxrate2pcie4_map_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxehmdata_ehm_data_slc_sel_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXEHMDATA_EHM_DATA_SLC_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxehmdata_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXEHMDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxfsm_generalpurpose_reg_in_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxfsm_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXFSM_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxfsm_pause_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXFSM_PAUSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxfsm_state_obs_hold_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXFSM_STATE_OBS_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxfsm_state_obs_sel_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXFSM_STATE_OBS_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxltr_force_ltr_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXLTR_FORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxltr_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXLTR_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxpcsrxeyediag_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXPCSRXEYEDIAG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxpcsrxeyediag_start_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXPCSRXEYEDIAG_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxsigdet_sel_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXSIGDET_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqfsm2ofc_ofc_cal_req_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFSM2OFC_OFC_CAL_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqfsm2ofc_ofc_cal_req_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFSM2OFC_OFC_CAL_REQ_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_16a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_16b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_16c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_16d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_16e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_1a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_1b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_1c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_1d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_1e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_2a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_2b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_2c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_2d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_2e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_4a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_4b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_4c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_4d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_4e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_8a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_8b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_8c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_8d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_8e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_done_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmax_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmax_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_SATMAX_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmax_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmax_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmax_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_SATMAX_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmax_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_SATMAX_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmax_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_SATMAX_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmin_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmin_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_SATMIN_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmin_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmin_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmin_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_SATMIN_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmin_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_SATMIN_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmin_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_SATMIN_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_stable_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_stable_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_STABLE_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_stable_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_stable_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_stable_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_STABLE_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_stable_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_STABLE_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_stable_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_STABLE_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsupd_chng_ack_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSUPD_CHNG_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsupd_chng_req_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSUPD_CHNG_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsupd_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSUPD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjaux_lms_vref0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjaux_lms_vref1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjaux_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJAUX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjauxen_lms_aux_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJAUXEN_LMS_AUX_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjauxen_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJAUXEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjauxltch_lms_aux_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJAUXLTCH_LMS_AUX_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjauxltch_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJAUXLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdata_lms_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdata_lms_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdata_lms_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdata_lms_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdata_lms_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdata_lms_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdata_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdataen_lms_data_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJDATAEN_LMS_DATA_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdataen_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJDATAEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdataltch_lms_data_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJDATALTCH_LMS_DATA_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdataltch_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJDATALTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjedge_lms_yadjust_edge0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjedge_lms_yadjust_edge1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjedge_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJEDGE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjedgeen_lms_edge_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJEDGEEN_LMS_EDGE_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjedgeen_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJEDGEEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjedgeltch_lms_edge_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJEDGELTCH_LMS_EDGE_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjedgeltch_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJEDGELTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqltch_dfe_aux_yadj_b_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLTCH_DFE_AUX_YADJ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqltch_dfe_b_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLTCH_DFE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqltch_dfe_data_yadj_b_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLTCH_DFE_DATA_YADJ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqltch_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqltchc_auxswap_b_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLTCHC_AUXSWAP_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqltchc_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLTCHC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofc2flx_ofc_cal_done_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQOFC2FLX_OFC_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofc2flx_ofc_cal_done_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQOFC2FLX_OFC_CAL_DONE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_ctle_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_ctle_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_ctle_rxstg1probemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_ctle_rxstg2_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_ctle_rxstg2probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_ctle_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_ctle_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_summer_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_summer_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_summer_rxstg1probemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_summer_rxstg2_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_summer_rxstg2probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_summer_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_summer_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_time_h_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_time_l_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_ctle_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_ctle_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_ctle_rxstg1probemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_ctle_rxstg2_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_ctle_rxstg2probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_ctle_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_ctle_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_summer_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_summer_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_summer_rxstg1probemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_summer_rxstg2_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_summer_rxstg2probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_summer_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_summer_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_time_l_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_compsel_ctle_st1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_compsel_ctle_st2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_compsel_ctle_st3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_compsel_idle_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_compsel_sa_d0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_compsel_sa_d1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_compsel_sa_e0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_compsel_sa_e1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_invert_comp_fb_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_lpexitcal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_lpexitcal_time_l_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_adapt_en_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_adapt_thr_sel_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_cal_en_attr == 8'd249
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_cal_thr_sel_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_data_disp_sticky_clr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQOFCCFG_OFC_DATA_DISP_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_disparity_disable_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQOFCCFG_OFC_DISPARITY_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_disparity_leak_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_disparity_thr_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_lpexitcal_en_attr == 8'd249
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_lpf_bypass_en_cb_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQOFCCFG_OFC_LPF_BYPASS_EN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_ratechangecal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_pre_timer_setting_pow2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ratechangecal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ratechangecal_time_l_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_rxinpprobemuxen_idle_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_rxstg1_stateen_idle_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_rxstg1probemuxen_idle_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_rxstg2_stateen_idle_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_rxstg2probemuxen_idle_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_rxstg3_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_rxstg3probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqout_init_restore_avail_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQOUT_INIT_RESTORE_AVAIL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqprecal_code_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqprecal_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQPRECAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_hf1deq_dir_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_BOOSTLUT_HF1DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_hf2deq_dir_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_BOOSTLUT_HF2DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_hf2reszero_dir_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_BOOSTLUT_HF2RESZERO_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_hf3deq_dir_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_BOOSTLUT_HF3DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_idx_hf1deq_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_idx_hf1deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_idx_hf2deq_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_idx_hf2deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_idx_hf2reszero_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_idx_hf2reszero_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_idx_hf3deq_vf00_attr == 32'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_idx_hf3deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_init_hf1deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_init_hf2deq_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_init_hf2reszero_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_init_hf3deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_cal_hifreqagcres_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_cal_hifreqvgagain_attr == 7'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_cal_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_cal_yadjust_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_biasboost_dir_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_GAINLUT_BIASBOOST_DIR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_hf1resdcgain_dir_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_GAINLUT_HF1RESDCGAIN_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_hf3resdcgain_dir_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_GAINLUT_HF3RESDCGAIN_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_biasboost_vf00_attr == 32'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_biasboost_vf01_attr == 32'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_biasboost_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_lbbiasboost_vf00_attr == 32'd268435454
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_lbbiasboost_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_lbbiasboost_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_init_biasboost_attr == 5'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_init_hf1resdcgain_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_init_hf3resdcgain_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_init_lbbiasboost_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_lbbiasboost_dir_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_GAINLUT_LBBIASBOOST_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_latch_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref0_initval_attr == 9'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref1_initval_attr == 9'd191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref2_initval_attr == 9'd321
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref3_initval_attr == 9'd451
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_decr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_AUXVREF_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_frac_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_AUXVREF_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_frac_reset_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_incr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_AUXVREF_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_incr_decr_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_pam4adj_swizzle_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_AUXVREF_PAM4ADJ_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_AUXVREF_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_pol_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_single_step_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_AUXVREF_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_stable_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_AUXVREF_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_AUXVREF_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_targ_0_hi_attr == 9'd160
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_targ_0_lo_attr == 9'd140
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_auxvref_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_auxvref_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_dfe_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_dfe_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_edge_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_edge_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_edgevref_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_edgevref_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_iqalign_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_iqalign_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_level_vga_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_vga_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_vga_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_blockcount_fast_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_BLOCKCOUNT_FAST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_coarse_detect_clear_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_COARSE_DETECT_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_coarse_detect_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_COARSE_DETECT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_continuous_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_CONTINUOUS_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_datastats_incr_decr_swizzle_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_DATASTATS_INCR_DECR_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_datastats_pol_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_DATASTATS_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_datastats_thres_attr == 16'd1023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe1_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe2_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe3_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe4p_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_core_sel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_decr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_DFE_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_frac_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_DFE_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_frac_reset_mask_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_incr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_DFE_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_incr_decr_mask_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_inner_lvl_filter_en_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_DFE_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_pol_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_single_step_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_DFE_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_stable_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_DFE_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_DFE_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_targtap1_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_targtap2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_targtap3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_targtap4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_decr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGE_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_frac_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGE_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_frac_reset_mask_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_incr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGE_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_incr_decr_mask_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGE_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_pol_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_single_step_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGE_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_stable_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGE_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGE_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_decr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGEVREF_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_frac_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGEVREF_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGEVREF_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_incr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGEVREF_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_initval_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGEVREF_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_pol_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGEVREF_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_single_step_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGEVREF_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_stable_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGEVREF_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGEVREF_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_fast_blockcnt_attr == 16'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_filter_mode_auxvref_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_filter_mode_dfe_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_filter_mode_edge_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_filter_mode_edgevref_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_filter_mode_iqalign_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_filter_mode_vga_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_freeze_auxvrefupd_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_freeze_dfeupd_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_freeze_edgeupd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_freeze_edgevrefupd_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_FREEZE_EDGEVREFUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_freeze_forcebg_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_FREEZE_FORCEBG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_freeze_hifreqagcupd_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_FREEZE_HIFREQAGCUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_freeze_iqalignupd_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_FREEZE_IQALIGNUPD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_freeze_lofreqagcupd_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_FREEZE_LOFREQAGCUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_freeze_vgaupd_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_FREEZE_VGAUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_gated_update_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_GATED_UPDATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_accum_count_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_accum_level_en_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_decr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_HIFREQAGC_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_frac_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_HIFREQAGC_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_HIFREQAGC_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_incr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_HIFREQAGC_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_n1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_n2_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_n3_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_n4_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_n5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_HIFREQAGC_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_pol_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_HIFREQAGC_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_single_step_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_HIFREQAGC_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_stable_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_HIFREQAGC_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_HIFREQAGC_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_init_adapt_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_INIT_ADAPT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_decr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_IQALIGN_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_frac_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_IQALIGN_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_IQALIGN_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_incr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_IQALIGN_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_IQALIGN_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_pol_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_IQALIGN_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_single_step_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_IQALIGN_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_stable_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_IQALIGN_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_IQALIGN_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_targ_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_itercount_attr == 10'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_latch_delay_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_latch_prepost_delay_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_decr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOFREQAGC_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_frac_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOFREQAGC_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOFREQAGC_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_incr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOFREQAGC_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOFREQAGC_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_pol_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOFREQAGC_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_single_step_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOFREQAGC_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_stable_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOFREQAGC_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOFREQAGC_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_logain_auxvref_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOGAIN_AUXVREF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_logain_dfe_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_logain_edge_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_logain_edgevref_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOGAIN_EDGEVREF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_logain_hifreqagc_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOGAIN_HIFREQAGC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_logain_iqalign_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOGAIN_IQALIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_logain_lofreqagc_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOGAIN_LOFREQAGC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_logain_vga_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOGAIN_VGA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_auxvref_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_dfe1_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_dfe23_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_dfe4p_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_edge2_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_edge3_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_edge4_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_edgevref_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_hifreqagc_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_iqalign_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_lofreqagc_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_vga_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_nrz_to_pam4_mode_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_NRZ_TO_PAM4_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_slow_blockcnt_attr == 16'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_start_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_tsettle_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_accum_count_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_accum_level_en_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_decr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_frac_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_incr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_mode_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_pol_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_single_step_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_stable_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_yadjdata_mid_clamp_zero_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_YADJDATA_MID_CLAMP_ZERO_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lofreqagcgain_sel_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LOFREQAGCGAIN_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_caldfedatatap1gain_attr == 6'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_caldfedatatap2gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_caldfedatatap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_caldfedatatap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_caldfeedgetap2gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_caldfeedgetap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_caldfeedgetap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_hifreqagcres_attr == 6'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_hifreqvgagain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_caldfedatatap1gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_caldfedatatap1gain_attr == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_caldfedatatap1gain_attr == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_shift_auxshft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_shift_capture_trigger_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_SHIFT_CAPTURE_TRIGGER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_shift_clear_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_SHIFT_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_shift_dat_bitsel_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_SHIFT_DAT_BITSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_shift_datashft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_shift_edgeshft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_shift_edgeshft_nrz8b10b_pam16b20b_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_shift_polarity_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_SHIFT_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap10gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap11gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap12gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap13gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap14gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap15gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap16gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap1gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap2gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap5gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap6gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap7gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap8gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap9gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfeedgetap2gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfeedgetap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfeedgetap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_hifreqvgagain_attr == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_auxvref0_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_auxvref1_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_auxvref2_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_auxvref3_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_caldfedatatap1gain_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_caldfeedgetap2gain_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_calhifreqagcres_attr == 6'd38
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_callofreqagcgain_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_edgevref_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_hifreqvgagain_attr == 7'd45
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_iqalign_attr == 6'd45
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_auxvref0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_auxvref1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_auxvref2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_auxvref3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_caldfedatatap1gain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_caldfeedgetap2gain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_calhifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_callofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_edgevref_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_iqalign_attr == 6'd21
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqsetnrztopam4_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSETNRZTOPAM4_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqsetnrztopam4_switch_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSETNRZTOPAM4_SWITCH_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqsigdet_pause_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSIGDET_PAUSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqspare0_attr == 32'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqspare1_attr == 32'd15871
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqspare2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqsync2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSYNC2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqsync2flx_rxdatapath_ready_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSYNC2FLX_RXDATAPATH_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqtapctrl_data_tap13to16_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQTAPCTRL_DATA_TAP13TO16_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqtapctrl_data_tap1to4_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQTAPCTRL_DATA_TAP1TO4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqtapctrl_data_tap5to8_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQTAPCTRL_DATA_TAP5TO8_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqtapctrl_data_tap9to12_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQTAPCTRL_DATA_TAP9TO12_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqtapctrl_edge_tap_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQTAPCTRL_EDGE_TAP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqtapctrl_tap1to4gain_dbl_res_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQTAPCTRL_TAP1TO4GAIN_DBL_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqtapctrl_tap5to16gain_dbl_res_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQTAPCTRL_TAP5TO16GAIN_DBL_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvalc_hifreqagcbiasadjust_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvalc_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQVALC_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvalc_midbandzero_locovr_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvalcl_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQVALCL_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvalcl_lofreqagcgain_locovr_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap01gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap02gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap03gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap04gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap05gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap06gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap07gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap08gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap09gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap10gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap11gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap12gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap13gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap14gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap15gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap16gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQVALD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvale_caldfeedgetap02gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvale_caldfeedgetap03gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvale_caldfeedgetap04gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvale_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQVALE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1cal_clear_mask_attr == 13'd8184
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_aux0_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_aux1_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_d0_bot_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_d0_mid_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_d0_top_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_d1_bot_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_d1_mid_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_d1_top_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_e0_lo_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_e1_lo_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2cal_clear_mask_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_aux0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_aux1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_d0_bot_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_d0_mid_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_d0_top_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_d1_bot_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_d1_mid_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_d1_top_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_e0_lo_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_e1_lo_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfgcal_calfsmmeas_dlycount_attr == 10'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfgcal_fsmmaxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfgcal_lpfax_coarse_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfgcal_lpfax_fine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxhifreqagc_inputcmadjust_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxhifreqagc_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXHIFREQAGC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcal_clear_mask_attr == 13'd8191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_ctlecmnmode_stg3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_aux0_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_aux1_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_d0_bot_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_d0_mid_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_d0_top_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_d1_bot_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_d1_mid_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_d1_top_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_e0_lo_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_e1_lo_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmargin_flx_jit_offset_shift_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmargin_jit_disable_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmargin_jit_enable_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmargin_jit_offset_shift_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmargin_jit_setup_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmargin_volt_comp_mask_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmargin_volt_forcel2d_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXMARGIN_VOLT_FORCEL2D_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmargin_volt_offset_shift_d0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmargin_volt_offset_shift_d1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmarginin_direction_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXMARGININ_DIRECTION_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmarginin_flx_jit_offset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmarginin_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXMARGININ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmarginin_mode_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXMARGININ_MODE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmarginin_offset_change_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXMARGININ_OFFSET_CHANGE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmarginin_offset_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmarginin_start_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXMARGININ_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxsum_cm_vref_attr == 9'd75
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxsum_summer_cmfb_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXSUM_SUMMER_CMFB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxsum_summer_cmfb_ibias_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_dfeyadj_aging_cdrlock2data_loc_ov_attr == SERDES_IP_LANE_RXEQ_L1_CFG_DFEYADJ_AGING_CDRLOCK2DATA_LOC_OV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_dfeyadj_aging_cdrlock2data_loc_ov_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_DFEYADJ_AGING_CDRLOCK2DATA_LOC_OV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_dfeyadj_aging_div_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_dfeyadj_aging_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_DFEYADJ_AGING_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxagc_ctlecomp_filterbypass_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXAGC_CTLECOMP_FILTERBYPASS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxagc_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXAGC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxbgcal_calfsmmeas_dlycount_attr == 10'd392
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxbgcal_clear_mask_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxbgcal_fsmmaxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxbgcal_lpfax_coarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxbgcal_lpfax_fine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxbgcalorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxbgcalorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxbgcalorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_calbiasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_calbiasboost_use_lut_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_CALBIASBOOST_USE_LUT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_callbbiasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_callbbiasboost_use_lut_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_CALLBBIASBOOST_USE_LUT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlecomp_filterbypass_smplrcal_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_CTLECOMP_FILTERBYPASS_SMPLRCAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg1_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg2_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg3_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctleinput_probe_mux_smplrcal_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg1_probe_mux_en_smplrcal_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg1_state_en_smplrcal_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg1_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg1_state_en_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg1_state_en_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg1_use_stg2code_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_CTLESTG1_USE_STG2CODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg2_probe_mux_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg2_state_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg2_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg2_state_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg2_state_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg3_probe_mux_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg3_state_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg3_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg3_state_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg3_state_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_hifreqagc_n5targin_sel_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_HIFREQAGC_N5TARGIN_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_inputcmadjust_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_inputcmadjust_stg1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_inputcmadjust_stg2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_inputcmadjust_stg3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_sdimode_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_SDIMODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_smplroffset_aux0_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_smplroffset_aux1_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_smplroffset_d0_bot_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_smplroffset_d0_mid_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_smplroffset_d0_top_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_smplroffset_d1_bot_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_smplroffset_d1_mid_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_smplroffset_d1_top_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_tfrtrim_outen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_tfrtrim_outen_tfrcal_stg1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_tfrtrim_outen_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_tfrtrim_outen_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalalign_iqclk_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalalign_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALALIGN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctl_cal_abort_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALCTL_CAL_ABORT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctl_cal_type_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctl_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALCTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctl_post_delay_pow2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctl_pre_delay_pow2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecalctrl_input_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecalctrl_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALCTLECALCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecalctrl_stg1_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecalctrl_stg1_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecalctrl_stg2_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecalctrl_stg2_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecalctrl_stg3_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecalctrl_stg3_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecompoffset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecompoffset_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALCTLECOMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecompoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALCTLECOMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecompoffsetfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALCTLECOMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecompoffsetfsmout_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaldutybkgnd_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALDUTYBKGND_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaldutybkgnd_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALDUTYBKGND_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_biasboost_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_hf1deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_hf1resdcgain_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_hf2cap_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_hf2deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_hf2reszero_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_hf3deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_hf3resdcgain_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_hf4deq_gray_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALEQ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_ctlecmnmode_stg1_finish_side_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALFSM_CTLECMNMODE_STG1_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_ctlecmnmode_stg1_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_ctlecmnmode_stg2_finish_side_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALFSM_CTLECMNMODE_STG2_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_ctlecmnmode_stg2_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_ctlecmnmode_stg3_finish_side_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALFSM_CTLECMNMODE_STG3_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_ctlecmnmode_stg3_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_runcount_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_smplroffset_finish_side_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALFSM_SMPLROFFSET_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_smplroffset_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsmmeas_ctlecmnmode_stg1_invert_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALFSMMEAS_CTLECMNMODE_STG1_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsmmeas_ctlecmnmode_stg2_invert_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALFSMMEAS_CTLECMNMODE_STG2_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsmmeas_ctlecmnmode_stg3_invert_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALFSMMEAS_CTLECMNMODE_STG3_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsmmeas_smplroffset_invert_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALFSMMEAS_SMPLROFFSET_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_ctlecmnmode_stg1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_ctlecmnmode_stg2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_ctlecmnmode_stg3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_aux0_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_aux1_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_d0_bot_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_d0_mid_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_d0_top_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_d1_bot_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_d1_mid_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_d1_top_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_e0_lo_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_e1_lo_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeas_pow2count_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasin_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasin_req_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASIN_REQ_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasin_req_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASIN_REQ_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasin_req_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASIN_REQ_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasout_ack_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASOUT_ACK_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasout_ack_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASOUT_ACK_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasout_ack_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASOUT_ACK_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasout_avg_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASOUT_AVG_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasout_avg_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASOUT_AVG_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasout_avg_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASOUT_AVG_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasout_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaloffsetfsmout_auxdatacomp_offset_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALOFFSETFSMOUT_AUXDATACOMP_OFFSET_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaloffsetfsmout_boost_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALOFFSETFSMOUT_BOOST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaloffsetfsmout_edgecomp_offset_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALOFFSETFSMOUT_EDGECOMP_OFFSET_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaloffsetfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalset_cal_clear_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalset_cal_mode_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALSET_CAL_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalset_cal_req_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALSET_CAL_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalset_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalstat_cal_ack_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALSTAT_CAL_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalstat_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalsummerfsmout_comp_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALSUMMERFSMOUT_COMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalsummerfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALSUMMERFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcdrphd_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCDRPHD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcdrphd_override_ignore_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCDRPHD_OVERRIDE_IGNORE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_caloffset_range_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_calstg1offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_calstg1offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_calstg2offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_calstg2offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_calstg3offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_calstg3offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_dccouple_sigpath_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCTLE_DCCOUPLE_SIGPATH_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_lbbiasboost_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCTLE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_stg1tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_stg2tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_stg3tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_tfrtrim_outmem_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCTLE_TFRTRIM_OUTMEM_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_tfrtrim_outpen_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCTLE_TFRTRIM_OUTPEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctledc_dccouple_tgate_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCTLEDC_DCCOUPLE_TGATE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctledc_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCTLEDC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxdfe_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXDFE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxdfe_tapgain_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxdfepam_enable_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXDFEPAM_ENABLE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxdfepam_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXDFEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxdpifjit_enb_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXDPIFJIT_ENB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxdpifjit_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXDPIFJIT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxdpifjit_offset_locovr_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqadj_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQADJ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqadj_yadjust_aux0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqadj_yadjust_aux1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqadj_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqadj_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqadj_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqadj_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqadj_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqadj_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqauxxor_amux_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqauxxor_dmux_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqauxxor_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQAUXXOR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcal2flx_pstate_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCAL2FLX_PSTATE_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcal2flx_rate_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCAL2FLX_RATE_MASK_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_16a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_16b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_16c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_16d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_16e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_1a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_1b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_1c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_1d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_1e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_2a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_2b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_2c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_2d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_2e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_4a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_4b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_4c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_4d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_4e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_8a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_8b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_8c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_8d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_8e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_16a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_16b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_16c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_16d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_16e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_1a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_1b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_1c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_1d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_1e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_2a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_2b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_2c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_2d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_2e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_4a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_4b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_4c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_4d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_4e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_8a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_8b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_8c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_8d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_8e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_16a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_16b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_16c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_16d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_16e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_1a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_1b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_1c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_1d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_1e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_2a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_2b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_2c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_2d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_2e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_4a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_4b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_4c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_4d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_4e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_8a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_8b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_8c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_8d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_8e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcals_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCALS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcals_offset_datasummer0_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcals_offset_datasummer0_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcals_offset_datasummer1_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcals_offset_datasummer1_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcals_offset_edgesummer0_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcals_offset_edgesummer0_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcals_offset_edgesummer1_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcals_offset_edgesummer1_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcdr_force_ltr_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCDR_FORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcdr_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCDR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqctl_clear_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCTL_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqctl_fg_run_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCTL_FG_RUN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqctlelut_hifreqagcres_ovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCTLELUT_HIFREQAGCRES_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqctlelut_hifreqvgagain_ovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCTLELUT_HIFREQVGAGAIN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqctls_oddeven_tapgain_sel_inv_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCTLS_ODDEVEN_TAPGAIN_SEL_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqctls_static_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCTLS_STATIC_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqdat_aux_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQDAT_AUX_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqdat_edge_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQDAT_EDGE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqdatactl_auxswap_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqdatactl_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQDATACTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqdatarate_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQDATARATE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqdatarate_rx_rate_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqdfeyadj_agingl2r_delay_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqdfeyadj_agingl2r_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQDFEYADJ_AGINGL2R_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqedgeadj_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEDGEADJ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqedgeadj_yadjust_edge0lo_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqedgeadj_yadjust_edge1lo_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm2flx_ehm_done_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHM2FLX_EHM_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm2flx_ehm_done_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHM2FLX_EHM_DONE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm2flx_ehm_err_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHM2FLX_EHM_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm2flx_ehm_err_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHM2FLX_EHM_ERR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm2flx_ehm_fom_locovr_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHM2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_data_extshift_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHM_DATA_EXTSHIFT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_distance_th_50p_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_distance_th_rate_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_err_mask_vf00_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_err_mask_vf01_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_event_rate_vf00_attr == 32'd67108864
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_event_rate_vf01_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_general_in_vf00_attr == 32'd5505024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_general_in_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_lms_th_50p_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_lms_th_rate_attr == 20'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_mask_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_no_change_th_50p_attr == 12'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_no_change_th_rate_attr == 12'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_reflections_num_50p_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_reflections_num_rate_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_slicer_swap_cb_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHM_SLICER_SWAP_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_sym_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_sym_dly_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_tap_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_test_aux_slicer_val_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_test_hits_th_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjaux_ehm_yadjust_aux0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjaux_ehm_yadjust_aux1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjaux_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJAUX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjauxen_ehm_aux_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJAUXEN_EHM_AUX_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjauxen_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJAUXEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjauxltch_aux_yadj_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJAUXLTCH_AUX_YADJ_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjauxltch_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJAUXLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdata_ehm_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdata_ehm_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdata_ehm_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdata_ehm_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdata_ehm_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdata_ehm_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdata_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdataen_ehm_data_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJDATAEN_EHM_DATA_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdataen_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJDATAEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdataltch_data_yadj_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJDATALTCH_DATA_YADJ_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdataltch_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJDATALTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2ehm_ehm_run_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2EHM_EHM_RUN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2ehm_ehm_run_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2EHM_EHM_RUN_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2lms_coarse_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2LMS_COARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2lms_ctrl_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2LMS_CTRL_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2lms_dfecore_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2LMS_DFECORE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2lms_force_evrefupd_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2LMS_FORCE_EVREFUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2lms_freeze_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2LMS_FREEZE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2lms_incr_decr_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2LMS_INCR_DECR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2lms_mu_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2LMS_MU_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2lms_rst_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2LMS_RST_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2ofc_ofc_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2OFC_OFC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2ofc_ofc_en_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2OFC_OFC_EN_OVRDEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx_pcs_rxeq_clr_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX_PCS_RXEQ_CLR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx_pcs_rxeq_start_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX_PCS_RXEQ_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx_pcs_rxeq_static_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX_PCS_RXEQ_STATIC_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx_rxrate2pcie1_map_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx_rxrate2pcie2_map_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx_rxrate2pcie3_map_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx_rxrate2pcie4_map_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxehmdata_ehm_data_slc_sel_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXEHMDATA_EHM_DATA_SLC_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxehmdata_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXEHMDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxfsm_generalpurpose_reg_in_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxfsm_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXFSM_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxfsm_pause_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXFSM_PAUSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxfsm_state_obs_hold_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXFSM_STATE_OBS_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxfsm_state_obs_sel_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXFSM_STATE_OBS_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxltr_force_ltr_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXLTR_FORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxltr_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXLTR_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxpcsrxeyediag_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXPCSRXEYEDIAG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxpcsrxeyediag_start_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXPCSRXEYEDIAG_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxsigdet_sel_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXSIGDET_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqfsm2ofc_ofc_cal_req_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFSM2OFC_OFC_CAL_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqfsm2ofc_ofc_cal_req_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFSM2OFC_OFC_CAL_REQ_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_16a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_16b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_16c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_16d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_16e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_1a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_1b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_1c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_1d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_1e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_2a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_2b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_2c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_2d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_2e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_4a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_4b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_4c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_4d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_4e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_8a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_8b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_8c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_8d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_8e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_done_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmax_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmax_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_SATMAX_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmax_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmax_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmax_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_SATMAX_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmax_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_SATMAX_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmax_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_SATMAX_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmin_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmin_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_SATMIN_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmin_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmin_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmin_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_SATMIN_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmin_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_SATMIN_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmin_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_SATMIN_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_stable_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_stable_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_STABLE_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_stable_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_stable_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_stable_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_STABLE_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_stable_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_STABLE_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_stable_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_STABLE_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsupd_chng_ack_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSUPD_CHNG_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsupd_chng_req_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSUPD_CHNG_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsupd_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSUPD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjaux_lms_vref0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjaux_lms_vref1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjaux_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJAUX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjauxen_lms_aux_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJAUXEN_LMS_AUX_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjauxen_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJAUXEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjauxltch_lms_aux_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJAUXLTCH_LMS_AUX_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjauxltch_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJAUXLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdata_lms_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdata_lms_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdata_lms_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdata_lms_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdata_lms_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdata_lms_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdata_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdataen_lms_data_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJDATAEN_LMS_DATA_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdataen_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJDATAEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdataltch_lms_data_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJDATALTCH_LMS_DATA_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdataltch_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJDATALTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjedge_lms_yadjust_edge0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjedge_lms_yadjust_edge1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjedge_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJEDGE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjedgeen_lms_edge_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJEDGEEN_LMS_EDGE_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjedgeen_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJEDGEEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjedgeltch_lms_edge_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJEDGELTCH_LMS_EDGE_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjedgeltch_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJEDGELTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqltch_dfe_aux_yadj_b_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLTCH_DFE_AUX_YADJ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqltch_dfe_b_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLTCH_DFE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqltch_dfe_data_yadj_b_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLTCH_DFE_DATA_YADJ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqltch_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqltchc_auxswap_b_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLTCHC_AUXSWAP_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqltchc_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLTCHC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofc2flx_ofc_cal_done_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQOFC2FLX_OFC_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofc2flx_ofc_cal_done_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQOFC2FLX_OFC_CAL_DONE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_ctle_rxinpprobemuxen_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_ctle_rxstg1_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_ctle_rxstg1probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_ctle_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_ctle_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_ctle_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_ctle_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_summer_rxinpprobemuxen_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_summer_rxstg1_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_summer_rxstg1probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_summer_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_summer_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_summer_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_summer_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_time_h_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_time_l_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_ctle_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_ctle_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_ctle_rxstg1probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_ctle_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_ctle_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_ctle_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_ctle_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_summer_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_summer_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_summer_rxstg1probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_summer_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_summer_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_summer_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_summer_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_time_l_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_compsel_ctle_st1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_compsel_ctle_st2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_compsel_ctle_st3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_compsel_idle_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_compsel_sa_d0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_compsel_sa_d1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_compsel_sa_e0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_compsel_sa_e1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_invert_comp_fb_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_lpexitcal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_lpexitcal_time_l_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_adapt_en_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_adapt_thr_sel_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_cal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_cal_thr_sel_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_data_disp_sticky_clr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQOFCCFG_OFC_DATA_DISP_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_disparity_disable_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQOFCCFG_OFC_DISPARITY_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_disparity_leak_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_disparity_thr_sel_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_lpexitcal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_lpf_bypass_en_cb_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQOFCCFG_OFC_LPF_BYPASS_EN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_ratechangecal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_pre_timer_setting_pow2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ratechangecal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ratechangecal_time_l_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_rxinpprobemuxen_idle_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_rxstg1_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_rxstg1probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_rxstg2_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_rxstg2probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_rxstg3_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_rxstg3probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqout_init_restore_avail_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQOUT_INIT_RESTORE_AVAIL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqprecal_code_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqprecal_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQPRECAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_hf1deq_dir_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_BOOSTLUT_HF1DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_hf2deq_dir_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_BOOSTLUT_HF2DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_hf2reszero_dir_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_BOOSTLUT_HF2RESZERO_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_hf3deq_dir_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_BOOSTLUT_HF3DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_idx_hf1deq_vf00_attr == 32'd599186
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_idx_hf1deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_idx_hf2deq_vf00_attr == 32'd1198372
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_idx_hf2deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_idx_hf2reszero_vf00_attr == 32'd4290772992
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_idx_hf2reszero_vf01_attr == 21'd2097151
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_idx_hf3deq_vf00_attr == 32'd2396744
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_idx_hf3deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_init_hf1deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_init_hf2deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_init_hf2reszero_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_init_hf3deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_cal_hifreqagcres_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_cal_hifreqvgagain_attr == 7'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_cal_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_cal_yadjust_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_biasboost_dir_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_GAINLUT_BIASBOOST_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_hf1resdcgain_dir_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_GAINLUT_HF1RESDCGAIN_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_hf3resdcgain_dir_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_GAINLUT_HF3RESDCGAIN_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_biasboost_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_biasboost_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_biasboost_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf00_attr == 32'd2863311530
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf01_attr == 32'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf00_attr == 32'd1431655764
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf01_attr == 32'd1431655765
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_lbbiasboost_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_lbbiasboost_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_lbbiasboost_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_init_biasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_init_hf1resdcgain_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_init_hf3resdcgain_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_init_lbbiasboost_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_lbbiasboost_dir_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_GAINLUT_LBBIASBOOST_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_latch_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref0_initval_attr == 9'd61
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref1_initval_attr == 9'd191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref2_initval_attr == 9'd321
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref3_initval_attr == 9'd451
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_decr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_AUXVREF_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_frac_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_AUXVREF_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_frac_reset_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_incr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_AUXVREF_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_incr_decr_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_pam4adj_swizzle_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_AUXVREF_PAM4ADJ_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_AUXVREF_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_pol_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_single_step_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_AUXVREF_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_stable_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_AUXVREF_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_AUXVREF_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_targ_0_hi_attr == 9'd149
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_targ_0_lo_attr == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_auxvref_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_auxvref_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_dfe_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_dfe_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_edge_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_edge_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_edgevref_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_edgevref_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_iqalign_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_iqalign_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_level_vga_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_vga_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_vga_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_blockcount_fast_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_BLOCKCOUNT_FAST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_coarse_detect_clear_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_COARSE_DETECT_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_coarse_detect_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_COARSE_DETECT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_continuous_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_CONTINUOUS_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_datastats_incr_decr_swizzle_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_DATASTATS_INCR_DECR_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_datastats_pol_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_DATASTATS_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_datastats_thres_attr == 16'd1023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe1_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe2_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe3_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe4p_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_core_sel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_decr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_DFE_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_frac_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_DFE_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_frac_reset_mask_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_incr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_DFE_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_incr_decr_mask_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_inner_lvl_filter_en_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_DFE_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_pol_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_single_step_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_DFE_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_stable_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_DFE_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_DFE_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_targtap1_attr == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_targtap2_attr == 7'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_targtap3_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_targtap4_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_decr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGE_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_frac_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGE_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_frac_reset_mask_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_incr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGE_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_incr_decr_mask_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGE_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_pol_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_single_step_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGE_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_stable_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGE_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGE_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_decr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGEVREF_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_frac_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGEVREF_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGEVREF_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_incr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGEVREF_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_initval_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGEVREF_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_pol_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGEVREF_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_single_step_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGEVREF_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_stable_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGEVREF_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGEVREF_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_fast_blockcnt_attr == 16'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_filter_mode_auxvref_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_filter_mode_dfe_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_filter_mode_edge_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_filter_mode_edgevref_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_filter_mode_iqalign_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_filter_mode_vga_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_freeze_auxvrefupd_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_freeze_dfeupd_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_freeze_edgeupd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_freeze_edgevrefupd_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_FREEZE_EDGEVREFUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_freeze_forcebg_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_FREEZE_FORCEBG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_freeze_hifreqagcupd_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_FREEZE_HIFREQAGCUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_freeze_iqalignupd_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_FREEZE_IQALIGNUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_freeze_lofreqagcupd_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_FREEZE_LOFREQAGCUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_freeze_vgaupd_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_FREEZE_VGAUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_gated_update_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_GATED_UPDATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_accum_count_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_accum_level_en_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_decr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_HIFREQAGC_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_frac_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_HIFREQAGC_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_HIFREQAGC_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_incr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_HIFREQAGC_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_n1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_n2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_n3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_n4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_n5_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_HIFREQAGC_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_pol_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_HIFREQAGC_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_single_step_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_HIFREQAGC_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_stable_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_HIFREQAGC_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_HIFREQAGC_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_init_adapt_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_INIT_ADAPT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_decr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_IQALIGN_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_frac_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_IQALIGN_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_IQALIGN_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_incr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_IQALIGN_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_IQALIGN_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_pol_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_IQALIGN_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_single_step_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_IQALIGN_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_stable_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_IQALIGN_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_IQALIGN_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_targ_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_itercount_attr == 10'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_latch_delay_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_latch_prepost_delay_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_decr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOFREQAGC_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_frac_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOFREQAGC_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOFREQAGC_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_incr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOFREQAGC_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOFREQAGC_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_pol_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOFREQAGC_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_single_step_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOFREQAGC_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_stable_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOFREQAGC_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOFREQAGC_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_logain_auxvref_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOGAIN_AUXVREF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_logain_dfe_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_logain_edge_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_logain_edgevref_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOGAIN_EDGEVREF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_logain_hifreqagc_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOGAIN_HIFREQAGC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_logain_iqalign_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOGAIN_IQALIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_logain_lofreqagc_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOGAIN_LOFREQAGC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_logain_vga_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOGAIN_VGA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_auxvref_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_dfe1_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_dfe23_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_dfe4p_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_edge2_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_edge3_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_edge4_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_edgevref_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_hifreqagc_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_iqalign_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_lofreqagc_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_vga_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_nrz_to_pam4_mode_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_NRZ_TO_PAM4_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_slow_blockcnt_attr == 16'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_start_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_tsettle_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_accum_count_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_accum_level_en_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_decr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_frac_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_incr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_mode_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_pol_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_single_step_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_stable_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_yadjdata_mid_clamp_zero_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_YADJDATA_MID_CLAMP_ZERO_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lofreqagcgain_sel_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LOFREQAGCGAIN_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_caldfedatatap1gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_caldfedatatap2gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_caldfedatatap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_caldfedatatap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_caldfeedgetap2gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_caldfeedgetap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_caldfeedgetap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_lofreqagcgain_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_caldfedatatap1gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_caldfedatatap1gain_attr == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_caldfedatatap1gain_attr == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_shift_auxshft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_shift_capture_trigger_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_SHIFT_CAPTURE_TRIGGER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_shift_clear_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_SHIFT_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_shift_dat_bitsel_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_SHIFT_DAT_BITSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_shift_datashft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_shift_edgeshft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_shift_edgeshft_nrz8b10b_pam16b20b_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_shift_polarity_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_SHIFT_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap10gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap11gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap12gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap13gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap14gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap15gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap16gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap1gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap2gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap5gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap6gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap7gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap8gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap9gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfeedgetap2gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfeedgetap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfeedgetap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_hifreqvgagain_attr == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_auxvref0_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_auxvref1_attr == 9'd223
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_auxvref2_attr == 9'd339
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_auxvref3_attr == 9'd456
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_caldfedatatap1gain_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_caldfeedgetap2gain_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_calhifreqagcres_attr == 6'd52
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_callofreqagcgain_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_edgevref_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_hifreqvgagain_attr == 7'd77
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_iqalign_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_auxvref0_attr == 9'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_auxvref1_attr == 9'd173
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_auxvref2_attr == 9'd289
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_auxvref3_attr == 9'd356
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_caldfedatatap1gain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_caldfeedgetap2gain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_calhifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_callofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_edgevref_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_iqalign_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqsetnrztopam4_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSETNRZTOPAM4_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqsetnrztopam4_switch_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSETNRZTOPAM4_SWITCH_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqsigdet_pause_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSIGDET_PAUSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqspare0_attr == 32'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqspare1_attr == 32'd15871
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqspare2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqsync2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSYNC2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqsync2flx_rxdatapath_ready_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSYNC2FLX_RXDATAPATH_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqtapctrl_data_tap13to16_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQTAPCTRL_DATA_TAP13TO16_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqtapctrl_data_tap1to4_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQTAPCTRL_DATA_TAP1TO4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqtapctrl_data_tap5to8_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQTAPCTRL_DATA_TAP5TO8_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqtapctrl_data_tap9to12_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQTAPCTRL_DATA_TAP9TO12_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqtapctrl_edge_tap_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQTAPCTRL_EDGE_TAP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqtapctrl_tap1to4gain_dbl_res_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQTAPCTRL_TAP1TO4GAIN_DBL_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqtapctrl_tap5to16gain_dbl_res_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQTAPCTRL_TAP5TO16GAIN_DBL_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvalc_hifreqagcbiasadjust_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvalc_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQVALC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvalc_midbandzero_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvalcl_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQVALCL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvalcl_lofreqagcgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap01gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap02gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap03gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap04gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap05gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap06gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap07gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap08gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap09gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap10gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap11gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap12gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap13gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap14gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap15gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap16gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQVALD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvale_caldfeedgetap02gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvale_caldfeedgetap03gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvale_caldfeedgetap04gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvale_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQVALE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1cal_clear_mask_attr == 13'd8184
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_aux0_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_aux1_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_d0_bot_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_d0_mid_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_d0_top_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_d1_bot_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_d1_mid_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_d1_top_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_e0_lo_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_e1_lo_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2cal_clear_mask_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_aux0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_aux1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_d0_bot_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_d0_mid_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_d0_top_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_d1_bot_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_d1_mid_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_d1_top_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_e0_lo_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_e1_lo_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfgcal_calfsmmeas_dlycount_attr == 10'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfgcal_fsmmaxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfgcal_lpfax_coarse_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfgcal_lpfax_fine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxhifreqagc_inputcmadjust_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxhifreqagc_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXHIFREQAGC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcal_clear_mask_attr == 13'd8191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_ctlecmnmode_stg1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_ctlecmnmode_stg2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_ctlecmnmode_stg3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_aux0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_aux1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_d0_bot_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_d0_mid_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_d0_top_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_d1_bot_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_d1_mid_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_d1_top_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_e0_lo_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_e1_lo_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmargin_flx_jit_offset_shift_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmargin_jit_disable_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmargin_jit_enable_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmargin_jit_offset_shift_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmargin_jit_setup_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmargin_volt_comp_mask_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmargin_volt_forcel2d_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXMARGIN_VOLT_FORCEL2D_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmargin_volt_offset_shift_d0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmargin_volt_offset_shift_d1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmarginin_direction_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXMARGININ_DIRECTION_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmarginin_flx_jit_offset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmarginin_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXMARGININ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmarginin_mode_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXMARGININ_MODE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmarginin_offset_change_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXMARGININ_OFFSET_CHANGE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmarginin_offset_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmarginin_start_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXMARGININ_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxsum_cm_vref_attr == 9'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxsum_summer_cmfb_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXSUM_SUMMER_CMFB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxsum_summer_cmfb_ibias_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_dfeyadj_aging_cdrlock2data_loc_ov_attr == SERDES_IP_LANE_RXEQ_L2_CFG_DFEYADJ_AGING_CDRLOCK2DATA_LOC_OV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_dfeyadj_aging_cdrlock2data_loc_ov_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_DFEYADJ_AGING_CDRLOCK2DATA_LOC_OV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_dfeyadj_aging_div_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_dfeyadj_aging_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_DFEYADJ_AGING_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxagc_ctlecomp_filterbypass_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXAGC_CTLECOMP_FILTERBYPASS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxagc_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXAGC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxbgcal_calfsmmeas_dlycount_attr == 10'd392
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxbgcal_clear_mask_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxbgcal_fsmmaxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxbgcal_lpfax_coarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxbgcal_lpfax_fine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxbgcalorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxbgcalorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxbgcalorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_calbiasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_calbiasboost_use_lut_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_CALBIASBOOST_USE_LUT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_callbbiasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_callbbiasboost_use_lut_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_CALLBBIASBOOST_USE_LUT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlecomp_filterbypass_smplrcal_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_CTLECOMP_FILTERBYPASS_SMPLRCAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg1_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg2_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg3_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctleinput_probe_mux_smplrcal_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg1_probe_mux_en_smplrcal_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg1_state_en_smplrcal_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg1_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg1_state_en_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg1_state_en_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg1_use_stg2code_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_CTLESTG1_USE_STG2CODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg2_probe_mux_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg2_state_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg2_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg2_state_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg2_state_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg3_probe_mux_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg3_state_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg3_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg3_state_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg3_state_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_hifreqagc_n5targin_sel_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_HIFREQAGC_N5TARGIN_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_inputcmadjust_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_inputcmadjust_stg1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_inputcmadjust_stg2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_inputcmadjust_stg3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_sdimode_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_SDIMODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_smplroffset_aux0_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_smplroffset_aux1_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_smplroffset_d0_bot_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_smplroffset_d0_mid_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_smplroffset_d0_top_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_smplroffset_d1_bot_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_smplroffset_d1_mid_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_smplroffset_d1_top_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_tfrtrim_outen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_tfrtrim_outen_tfrcal_stg1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_tfrtrim_outen_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_tfrtrim_outen_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalalign_iqclk_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalalign_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALALIGN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctl_cal_abort_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALCTL_CAL_ABORT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctl_cal_type_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctl_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALCTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctl_post_delay_pow2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctl_pre_delay_pow2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecalctrl_input_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecalctrl_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALCTLECALCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecalctrl_stg1_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecalctrl_stg1_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecalctrl_stg2_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecalctrl_stg2_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecalctrl_stg3_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecalctrl_stg3_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecompoffset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecompoffset_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALCTLECOMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecompoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALCTLECOMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecompoffsetfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALCTLECOMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecompoffsetfsmout_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaldutybkgnd_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALDUTYBKGND_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaldutybkgnd_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALDUTYBKGND_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_biasboost_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_hf1deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_hf1resdcgain_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_hf2cap_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_hf2deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_hf2reszero_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_hf3deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_hf3resdcgain_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_hf4deq_gray_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALEQ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_ctlecmnmode_stg1_finish_side_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALFSM_CTLECMNMODE_STG1_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_ctlecmnmode_stg1_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_ctlecmnmode_stg2_finish_side_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALFSM_CTLECMNMODE_STG2_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_ctlecmnmode_stg2_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_ctlecmnmode_stg3_finish_side_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALFSM_CTLECMNMODE_STG3_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_ctlecmnmode_stg3_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_runcount_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_smplroffset_finish_side_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALFSM_SMPLROFFSET_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_smplroffset_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsmmeas_ctlecmnmode_stg1_invert_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALFSMMEAS_CTLECMNMODE_STG1_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsmmeas_ctlecmnmode_stg2_invert_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALFSMMEAS_CTLECMNMODE_STG2_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsmmeas_ctlecmnmode_stg3_invert_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALFSMMEAS_CTLECMNMODE_STG3_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsmmeas_smplroffset_invert_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALFSMMEAS_SMPLROFFSET_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_ctlecmnmode_stg1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_ctlecmnmode_stg2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_ctlecmnmode_stg3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_aux0_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_aux1_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_d0_bot_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_d0_mid_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_d0_top_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_d1_bot_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_d1_mid_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_d1_top_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_e0_lo_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_e1_lo_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeas_pow2count_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasin_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasin_req_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASIN_REQ_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasin_req_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASIN_REQ_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasin_req_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASIN_REQ_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasout_ack_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASOUT_ACK_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasout_ack_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASOUT_ACK_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasout_ack_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASOUT_ACK_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasout_avg_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASOUT_AVG_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasout_avg_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASOUT_AVG_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasout_avg_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASOUT_AVG_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasout_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaloffsetfsmout_auxdatacomp_offset_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALOFFSETFSMOUT_AUXDATACOMP_OFFSET_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaloffsetfsmout_boost_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALOFFSETFSMOUT_BOOST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaloffsetfsmout_edgecomp_offset_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALOFFSETFSMOUT_EDGECOMP_OFFSET_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaloffsetfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalset_cal_clear_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalset_cal_mode_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALSET_CAL_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalset_cal_req_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALSET_CAL_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalset_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalstat_cal_ack_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALSTAT_CAL_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalstat_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalsummerfsmout_comp_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALSUMMERFSMOUT_COMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalsummerfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALSUMMERFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcdrphd_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCDRPHD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcdrphd_override_ignore_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCDRPHD_OVERRIDE_IGNORE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_caloffset_range_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_calstg1offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_calstg1offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_calstg2offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_calstg2offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_calstg3offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_calstg3offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_dccouple_sigpath_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCTLE_DCCOUPLE_SIGPATH_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_lbbiasboost_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCTLE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_stg1tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_stg2tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_stg3tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_tfrtrim_outmem_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCTLE_TFRTRIM_OUTMEM_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_tfrtrim_outpen_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCTLE_TFRTRIM_OUTPEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctledc_dccouple_tgate_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCTLEDC_DCCOUPLE_TGATE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctledc_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCTLEDC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxdfe_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXDFE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxdfe_tapgain_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxdfepam_enable_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXDFEPAM_ENABLE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxdfepam_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXDFEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxdpifjit_enb_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXDPIFJIT_ENB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxdpifjit_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXDPIFJIT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxdpifjit_offset_locovr_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqadj_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQADJ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqadj_yadjust_aux0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqadj_yadjust_aux1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqadj_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqadj_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqadj_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqadj_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqadj_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqadj_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqauxxor_amux_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqauxxor_dmux_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqauxxor_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQAUXXOR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcal2flx_pstate_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCAL2FLX_PSTATE_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcal2flx_rate_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCAL2FLX_RATE_MASK_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_16a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_16b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_16c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_16d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_16e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_1a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_1b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_1c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_1d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_1e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_2a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_2b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_2c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_2d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_2e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_4a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_4b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_4c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_4d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_4e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_8a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_8b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_8c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_8d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_8e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_16a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_16b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_16c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_16d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_16e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_1a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_1b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_1c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_1d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_1e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_2a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_2b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_2c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_2d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_2e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_4a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_4b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_4c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_4d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_4e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_8a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_8b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_8c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_8d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_8e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_16a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_16b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_16c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_16d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_16e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_1a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_1b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_1c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_1d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_1e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_2a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_2b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_2c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_2d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_2e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_4a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_4b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_4c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_4d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_4e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_8a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_8b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_8c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_8d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_8e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcals_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCALS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcals_offset_datasummer0_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcals_offset_datasummer0_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcals_offset_datasummer1_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcals_offset_datasummer1_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcals_offset_edgesummer0_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcals_offset_edgesummer0_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcals_offset_edgesummer1_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcals_offset_edgesummer1_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcdr_force_ltr_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCDR_FORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcdr_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCDR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqctl_clear_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCTL_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqctl_fg_run_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCTL_FG_RUN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqctlelut_hifreqagcres_ovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCTLELUT_HIFREQAGCRES_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqctlelut_hifreqvgagain_ovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCTLELUT_HIFREQVGAGAIN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqctls_oddeven_tapgain_sel_inv_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCTLS_ODDEVEN_TAPGAIN_SEL_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqctls_static_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCTLS_STATIC_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqdat_aux_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQDAT_AUX_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqdat_edge_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQDAT_EDGE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqdatactl_auxswap_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqdatactl_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQDATACTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqdatarate_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQDATARATE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqdatarate_rx_rate_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqdfeyadj_agingl2r_delay_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqdfeyadj_agingl2r_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQDFEYADJ_AGINGL2R_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqedgeadj_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEDGEADJ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqedgeadj_yadjust_edge0lo_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqedgeadj_yadjust_edge1lo_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm2flx_ehm_done_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHM2FLX_EHM_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm2flx_ehm_done_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHM2FLX_EHM_DONE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm2flx_ehm_err_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHM2FLX_EHM_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm2flx_ehm_err_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHM2FLX_EHM_ERR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm2flx_ehm_fom_locovr_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHM2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_data_extshift_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHM_DATA_EXTSHIFT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_distance_th_50p_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_distance_th_rate_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_err_mask_vf00_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_err_mask_vf01_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_event_rate_vf00_attr == 32'd67108864
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_event_rate_vf01_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_general_in_vf00_attr == 32'd5505024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_general_in_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_lms_th_50p_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_lms_th_rate_attr == 20'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_mask_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_no_change_th_50p_attr == 12'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_no_change_th_rate_attr == 12'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_reflections_num_50p_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_reflections_num_rate_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_slicer_swap_cb_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHM_SLICER_SWAP_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_sym_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_sym_dly_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_tap_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_test_aux_slicer_val_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_test_hits_th_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjaux_ehm_yadjust_aux0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjaux_ehm_yadjust_aux1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjaux_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJAUX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjauxen_ehm_aux_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJAUXEN_EHM_AUX_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjauxen_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJAUXEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjauxltch_aux_yadj_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJAUXLTCH_AUX_YADJ_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjauxltch_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJAUXLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdata_ehm_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdata_ehm_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdata_ehm_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdata_ehm_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdata_ehm_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdata_ehm_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdata_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdataen_ehm_data_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJDATAEN_EHM_DATA_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdataen_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJDATAEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdataltch_data_yadj_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJDATALTCH_DATA_YADJ_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdataltch_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJDATALTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2ehm_ehm_run_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2EHM_EHM_RUN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2ehm_ehm_run_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2EHM_EHM_RUN_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2lms_coarse_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2LMS_COARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2lms_ctrl_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2LMS_CTRL_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2lms_dfecore_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2LMS_DFECORE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2lms_force_evrefupd_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2LMS_FORCE_EVREFUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2lms_freeze_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2LMS_FREEZE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2lms_incr_decr_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2LMS_INCR_DECR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2lms_mu_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2LMS_MU_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2lms_rst_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2LMS_RST_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2ofc_ofc_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2OFC_OFC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2ofc_ofc_en_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2OFC_OFC_EN_OVRDEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx_pcs_rxeq_clr_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX_PCS_RXEQ_CLR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx_pcs_rxeq_start_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX_PCS_RXEQ_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx_pcs_rxeq_static_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX_PCS_RXEQ_STATIC_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx_rxrate2pcie1_map_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx_rxrate2pcie2_map_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx_rxrate2pcie3_map_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx_rxrate2pcie4_map_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxehmdata_ehm_data_slc_sel_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXEHMDATA_EHM_DATA_SLC_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxehmdata_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXEHMDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxfsm_generalpurpose_reg_in_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxfsm_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXFSM_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxfsm_pause_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXFSM_PAUSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxfsm_state_obs_hold_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXFSM_STATE_OBS_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxfsm_state_obs_sel_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXFSM_STATE_OBS_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxltr_force_ltr_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXLTR_FORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxltr_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXLTR_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxpcsrxeyediag_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXPCSRXEYEDIAG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxpcsrxeyediag_start_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXPCSRXEYEDIAG_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxsigdet_sel_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXSIGDET_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqfsm2ofc_ofc_cal_req_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFSM2OFC_OFC_CAL_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqfsm2ofc_ofc_cal_req_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFSM2OFC_OFC_CAL_REQ_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_16a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_16b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_16c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_16d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_16e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_1a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_1b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_1c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_1d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_1e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_2a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_2b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_2c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_2d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_2e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_4a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_4b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_4c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_4d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_4e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_8a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_8b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_8c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_8d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_8e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_done_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmax_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmax_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_SATMAX_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmax_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmax_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmax_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_SATMAX_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmax_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_SATMAX_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmax_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_SATMAX_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmin_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmin_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_SATMIN_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmin_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmin_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmin_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_SATMIN_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmin_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_SATMIN_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmin_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_SATMIN_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_stable_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_stable_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_STABLE_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_stable_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_stable_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_stable_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_STABLE_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_stable_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_STABLE_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_stable_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_STABLE_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsupd_chng_ack_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSUPD_CHNG_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsupd_chng_req_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSUPD_CHNG_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsupd_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSUPD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjaux_lms_vref0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjaux_lms_vref1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjaux_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJAUX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjauxen_lms_aux_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJAUXEN_LMS_AUX_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjauxen_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJAUXEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjauxltch_lms_aux_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJAUXLTCH_LMS_AUX_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjauxltch_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJAUXLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdata_lms_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdata_lms_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdata_lms_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdata_lms_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdata_lms_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdata_lms_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdata_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdataen_lms_data_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJDATAEN_LMS_DATA_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdataen_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJDATAEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdataltch_lms_data_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJDATALTCH_LMS_DATA_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdataltch_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJDATALTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjedge_lms_yadjust_edge0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjedge_lms_yadjust_edge1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjedge_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJEDGE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjedgeen_lms_edge_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJEDGEEN_LMS_EDGE_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjedgeen_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJEDGEEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjedgeltch_lms_edge_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJEDGELTCH_LMS_EDGE_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjedgeltch_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJEDGELTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqltch_dfe_aux_yadj_b_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLTCH_DFE_AUX_YADJ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqltch_dfe_b_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLTCH_DFE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqltch_dfe_data_yadj_b_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLTCH_DFE_DATA_YADJ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqltch_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqltchc_auxswap_b_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLTCHC_AUXSWAP_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqltchc_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLTCHC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofc2flx_ofc_cal_done_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQOFC2FLX_OFC_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofc2flx_ofc_cal_done_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQOFC2FLX_OFC_CAL_DONE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_ctle_rxinpprobemuxen_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_ctle_rxstg1_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_ctle_rxstg1probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_ctle_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_ctle_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_ctle_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_ctle_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_summer_rxinpprobemuxen_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_summer_rxstg1_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_summer_rxstg1probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_summer_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_summer_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_summer_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_summer_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_time_h_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_time_l_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_ctle_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_ctle_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_ctle_rxstg1probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_ctle_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_ctle_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_ctle_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_ctle_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_summer_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_summer_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_summer_rxstg1probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_summer_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_summer_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_summer_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_summer_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_time_l_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_compsel_ctle_st1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_compsel_ctle_st2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_compsel_ctle_st3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_compsel_idle_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_compsel_sa_d0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_compsel_sa_d1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_compsel_sa_e0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_compsel_sa_e1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_invert_comp_fb_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_lpexitcal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_lpexitcal_time_l_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_adapt_en_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_adapt_thr_sel_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_cal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_cal_thr_sel_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_data_disp_sticky_clr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQOFCCFG_OFC_DATA_DISP_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_disparity_disable_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQOFCCFG_OFC_DISPARITY_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_disparity_leak_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_disparity_thr_sel_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_lpexitcal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_lpf_bypass_en_cb_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQOFCCFG_OFC_LPF_BYPASS_EN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_ratechangecal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_pre_timer_setting_pow2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ratechangecal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ratechangecal_time_l_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_rxinpprobemuxen_idle_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_rxstg1_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_rxstg1probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_rxstg2_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_rxstg2probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_rxstg3_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_rxstg3probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqout_init_restore_avail_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQOUT_INIT_RESTORE_AVAIL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqprecal_code_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqprecal_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQPRECAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_hf1deq_dir_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_BOOSTLUT_HF1DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_hf2deq_dir_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_BOOSTLUT_HF2DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_hf2reszero_dir_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_BOOSTLUT_HF2RESZERO_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_hf3deq_dir_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_BOOSTLUT_HF3DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_idx_hf1deq_vf00_attr == 32'd599186
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_idx_hf1deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_idx_hf2deq_vf00_attr == 32'd1198372
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_idx_hf2deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_idx_hf2reszero_vf00_attr == 32'd4290772992
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_idx_hf2reszero_vf01_attr == 21'd2097151
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_idx_hf3deq_vf00_attr == 32'd2396744
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_idx_hf3deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_init_hf1deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_init_hf2deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_init_hf2reszero_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_init_hf3deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_cal_hifreqagcres_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_cal_hifreqvgagain_attr == 7'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_cal_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_cal_yadjust_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_biasboost_dir_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_GAINLUT_BIASBOOST_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_hf1resdcgain_dir_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_GAINLUT_HF1RESDCGAIN_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_hf3resdcgain_dir_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_GAINLUT_HF3RESDCGAIN_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_biasboost_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_biasboost_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_biasboost_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf00_attr == 32'd2863311530
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf01_attr == 32'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf00_attr == 32'd1431655764
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf01_attr == 32'd1431655765
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_lbbiasboost_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_lbbiasboost_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_lbbiasboost_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_init_biasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_init_hf1resdcgain_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_init_hf3resdcgain_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_init_lbbiasboost_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_lbbiasboost_dir_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_GAINLUT_LBBIASBOOST_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_latch_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref0_initval_attr == 9'd61
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref1_initval_attr == 9'd191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref2_initval_attr == 9'd321
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref3_initval_attr == 9'd451
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_decr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_AUXVREF_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_frac_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_AUXVREF_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_frac_reset_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_incr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_AUXVREF_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_incr_decr_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_pam4adj_swizzle_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_AUXVREF_PAM4ADJ_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_AUXVREF_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_pol_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_single_step_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_AUXVREF_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_stable_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_AUXVREF_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_AUXVREF_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_targ_0_hi_attr == 9'd130
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_targ_0_lo_attr == 9'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_auxvref_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_auxvref_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_dfe_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_dfe_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_edge_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_edge_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_edgevref_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_edgevref_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_iqalign_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_iqalign_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_level_vga_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_vga_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_vga_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_blockcount_fast_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_BLOCKCOUNT_FAST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_coarse_detect_clear_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_COARSE_DETECT_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_coarse_detect_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_COARSE_DETECT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_continuous_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_CONTINUOUS_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_datastats_incr_decr_swizzle_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_DATASTATS_INCR_DECR_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_datastats_pol_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_DATASTATS_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_datastats_thres_attr == 16'd1023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe1_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe2_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe3_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe4p_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_core_sel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_decr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_DFE_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_frac_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_DFE_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_frac_reset_mask_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_incr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_DFE_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_incr_decr_mask_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_inner_lvl_filter_en_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_DFE_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_pol_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_single_step_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_DFE_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_stable_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_DFE_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_DFE_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_targtap1_attr == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_targtap2_attr == 7'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_targtap3_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_targtap4_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_decr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGE_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_frac_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGE_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_frac_reset_mask_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_incr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGE_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_incr_decr_mask_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGE_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_pol_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_single_step_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGE_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_stable_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGE_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGE_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_decr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGEVREF_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_frac_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGEVREF_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGEVREF_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_incr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGEVREF_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_initval_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGEVREF_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_pol_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGEVREF_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_single_step_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGEVREF_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_stable_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGEVREF_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGEVREF_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_fast_blockcnt_attr == 16'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_filter_mode_auxvref_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_filter_mode_dfe_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_filter_mode_edge_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_filter_mode_edgevref_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_filter_mode_iqalign_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_filter_mode_vga_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_freeze_auxvrefupd_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_freeze_dfeupd_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_freeze_edgeupd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_freeze_edgevrefupd_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_FREEZE_EDGEVREFUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_freeze_forcebg_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_FREEZE_FORCEBG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_freeze_hifreqagcupd_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_FREEZE_HIFREQAGCUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_freeze_iqalignupd_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_FREEZE_IQALIGNUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_freeze_lofreqagcupd_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_FREEZE_LOFREQAGCUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_freeze_vgaupd_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_FREEZE_VGAUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_gated_update_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_GATED_UPDATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_accum_count_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_accum_level_en_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_decr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_HIFREQAGC_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_frac_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_HIFREQAGC_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_HIFREQAGC_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_incr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_HIFREQAGC_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_n1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_n2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_n3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_n4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_n5_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_HIFREQAGC_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_pol_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_HIFREQAGC_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_single_step_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_HIFREQAGC_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_stable_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_HIFREQAGC_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_HIFREQAGC_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_init_adapt_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_INIT_ADAPT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_decr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_IQALIGN_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_frac_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_IQALIGN_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_IQALIGN_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_incr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_IQALIGN_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_IQALIGN_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_pol_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_IQALIGN_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_single_step_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_IQALIGN_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_stable_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_IQALIGN_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_IQALIGN_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_targ_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_itercount_attr == 10'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_latch_delay_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_latch_prepost_delay_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_decr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOFREQAGC_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_frac_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOFREQAGC_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOFREQAGC_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_incr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOFREQAGC_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOFREQAGC_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_pol_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOFREQAGC_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_single_step_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOFREQAGC_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_stable_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOFREQAGC_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOFREQAGC_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_logain_auxvref_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOGAIN_AUXVREF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_logain_dfe_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_logain_edge_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_logain_edgevref_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOGAIN_EDGEVREF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_logain_hifreqagc_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOGAIN_HIFREQAGC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_logain_iqalign_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOGAIN_IQALIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_logain_lofreqagc_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOGAIN_LOFREQAGC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_logain_vga_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOGAIN_VGA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_auxvref_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_dfe1_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_dfe23_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_dfe4p_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_edge2_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_edge3_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_edge4_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_edgevref_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_hifreqagc_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_iqalign_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_lofreqagc_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_vga_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_nrz_to_pam4_mode_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_NRZ_TO_PAM4_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_slow_blockcnt_attr == 16'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_start_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_tsettle_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_accum_count_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_accum_level_en_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_decr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_frac_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_incr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_mode_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_pol_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_single_step_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_stable_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_yadjdata_mid_clamp_zero_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_YADJDATA_MID_CLAMP_ZERO_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lofreqagcgain_sel_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LOFREQAGCGAIN_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_caldfedatatap1gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_caldfedatatap2gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_caldfedatatap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_caldfedatatap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_caldfeedgetap2gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_caldfeedgetap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_caldfeedgetap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_lofreqagcgain_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_caldfedatatap1gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_caldfedatatap1gain_attr == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_caldfedatatap1gain_attr == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_shift_auxshft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_shift_capture_trigger_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_SHIFT_CAPTURE_TRIGGER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_shift_clear_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_SHIFT_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_shift_dat_bitsel_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_SHIFT_DAT_BITSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_shift_datashft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_shift_edgeshft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_shift_edgeshft_nrz8b10b_pam16b20b_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_shift_polarity_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_SHIFT_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap10gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap11gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap12gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap13gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap14gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap15gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap16gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap1gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap2gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap5gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap6gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap7gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap8gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap9gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfeedgetap2gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfeedgetap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfeedgetap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_auxvref0_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_auxvref1_attr == 9'd223
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_auxvref2_attr == 9'd339
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_auxvref3_attr == 9'd456
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_caldfedatatap1gain_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_caldfeedgetap2gain_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_calhifreqagcres_attr == 6'd52
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_callofreqagcgain_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_edgevref_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_hifreqvgagain_attr == 7'd77
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_iqalign_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_auxvref0_attr == 9'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_auxvref1_attr == 9'd173
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_auxvref2_attr == 9'd289
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_auxvref3_attr == 9'd356
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_caldfedatatap1gain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_caldfeedgetap2gain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_calhifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_callofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_edgevref_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_iqalign_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqsetnrztopam4_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSETNRZTOPAM4_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqsetnrztopam4_switch_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSETNRZTOPAM4_SWITCH_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqsigdet_pause_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSIGDET_PAUSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqspare0_attr == 32'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqspare1_attr == 32'd15871
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqspare2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqsync2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSYNC2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqsync2flx_rxdatapath_ready_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSYNC2FLX_RXDATAPATH_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqtapctrl_data_tap13to16_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQTAPCTRL_DATA_TAP13TO16_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqtapctrl_data_tap1to4_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQTAPCTRL_DATA_TAP1TO4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqtapctrl_data_tap5to8_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQTAPCTRL_DATA_TAP5TO8_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqtapctrl_data_tap9to12_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQTAPCTRL_DATA_TAP9TO12_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqtapctrl_edge_tap_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQTAPCTRL_EDGE_TAP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqtapctrl_tap1to4gain_dbl_res_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQTAPCTRL_TAP1TO4GAIN_DBL_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqtapctrl_tap5to16gain_dbl_res_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQTAPCTRL_TAP5TO16GAIN_DBL_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvalc_hifreqagcbiasadjust_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvalc_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQVALC_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvalc_midbandzero_locovr_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvalcl_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQVALCL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvalcl_lofreqagcgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap01gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap02gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap03gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap04gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap05gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap06gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap07gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap08gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap09gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap10gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap11gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap12gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap13gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap14gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap15gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap16gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQVALD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvale_caldfeedgetap02gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvale_caldfeedgetap03gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvale_caldfeedgetap04gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvale_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQVALE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1cal_clear_mask_attr == 13'd8184
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_aux0_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_aux1_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_d0_bot_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_d0_mid_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_d0_top_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_d1_bot_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_d1_mid_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_d1_top_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_e0_lo_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_e1_lo_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2cal_clear_mask_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_aux0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_aux1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_d0_bot_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_d0_mid_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_d0_top_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_d1_bot_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_d1_mid_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_d1_top_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_e0_lo_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_e1_lo_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfgcal_calfsmmeas_dlycount_attr == 10'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfgcal_fsmmaxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfgcal_lpfax_coarse_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfgcal_lpfax_fine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxhifreqagc_inputcmadjust_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxhifreqagc_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXHIFREQAGC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcal_clear_mask_attr == 13'd8191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_ctlecmnmode_stg1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_ctlecmnmode_stg2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_ctlecmnmode_stg3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_aux0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_aux1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_d0_bot_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_d0_mid_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_d0_top_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_d1_bot_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_d1_mid_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_d1_top_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_e0_lo_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_e1_lo_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmargin_flx_jit_offset_shift_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmargin_jit_disable_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmargin_jit_enable_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmargin_jit_offset_shift_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmargin_jit_setup_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmargin_volt_comp_mask_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmargin_volt_forcel2d_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXMARGIN_VOLT_FORCEL2D_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmargin_volt_offset_shift_d0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmargin_volt_offset_shift_d1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmarginin_direction_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXMARGININ_DIRECTION_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmarginin_flx_jit_offset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmarginin_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXMARGININ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmarginin_mode_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXMARGININ_MODE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmarginin_offset_change_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXMARGININ_OFFSET_CHANGE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmarginin_offset_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmarginin_start_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXMARGININ_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxsum_cm_vref_attr == 9'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxsum_summer_cmfb_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXSUM_SUMMER_CMFB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxsum_summer_cmfb_ibias_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_dfeyadj_aging_cdrlock2data_loc_ov_attr == SERDES_IP_LANE_RXEQ_L3_CFG_DFEYADJ_AGING_CDRLOCK2DATA_LOC_OV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_dfeyadj_aging_cdrlock2data_loc_ov_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_DFEYADJ_AGING_CDRLOCK2DATA_LOC_OV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_dfeyadj_aging_div_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_dfeyadj_aging_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_DFEYADJ_AGING_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxagc_ctlecomp_filterbypass_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXAGC_CTLECOMP_FILTERBYPASS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxagc_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXAGC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxbgcal_calfsmmeas_dlycount_attr == 10'd392
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxbgcal_clear_mask_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxbgcal_fsmmaxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxbgcal_lpfax_coarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxbgcal_lpfax_fine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxbgcalorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxbgcalorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxbgcalorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_calbiasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_calbiasboost_use_lut_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_CALBIASBOOST_USE_LUT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_callbbiasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_callbbiasboost_use_lut_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_CALLBBIASBOOST_USE_LUT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlecomp_filterbypass_smplrcal_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_CTLECOMP_FILTERBYPASS_SMPLRCAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg1_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg2_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg3_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctleinput_probe_mux_smplrcal_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg1_probe_mux_en_smplrcal_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg1_state_en_smplrcal_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg1_state_en_tfrcal_stg1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg1_state_en_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg1_state_en_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg1_use_stg2code_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_CTLESTG1_USE_STG2CODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg2_probe_mux_en_smplrcal_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg2_state_en_smplrcal_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg2_state_en_tfrcal_stg1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg2_state_en_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg2_state_en_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg3_probe_mux_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg3_state_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg3_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg3_state_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg3_state_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_hifreqagc_n5targin_sel_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_HIFREQAGC_N5TARGIN_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_inputcmadjust_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_inputcmadjust_stg1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_inputcmadjust_stg2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_inputcmadjust_stg3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_sdimode_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_SDIMODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_smplroffset_aux0_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_smplroffset_aux1_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_smplroffset_d0_bot_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_smplroffset_d0_mid_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_smplroffset_d0_top_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_smplroffset_d1_bot_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_smplroffset_d1_mid_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_smplroffset_d1_top_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_tfrtrim_outen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_tfrtrim_outen_tfrcal_stg1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_tfrtrim_outen_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_tfrtrim_outen_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalalign_iqclk_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalalign_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALALIGN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctl_cal_abort_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALCTL_CAL_ABORT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctl_cal_type_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctl_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALCTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctl_post_delay_pow2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctl_pre_delay_pow2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecalctrl_input_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecalctrl_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALCTLECALCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecalctrl_stg1_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecalctrl_stg1_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecalctrl_stg2_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecalctrl_stg2_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecalctrl_stg3_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecalctrl_stg3_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecompoffset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecompoffset_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALCTLECOMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecompoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALCTLECOMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecompoffsetfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALCTLECOMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecompoffsetfsmout_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaldutybkgnd_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALDUTYBKGND_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaldutybkgnd_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALDUTYBKGND_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_biasboost_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_hf1deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_hf1resdcgain_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_hf2cap_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_hf2deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_hf2reszero_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_hf3deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_hf3resdcgain_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_hf4deq_gray_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALEQ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_ctlecmnmode_stg1_finish_side_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALFSM_CTLECMNMODE_STG1_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_ctlecmnmode_stg1_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_ctlecmnmode_stg2_finish_side_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALFSM_CTLECMNMODE_STG2_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_ctlecmnmode_stg2_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_ctlecmnmode_stg3_finish_side_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALFSM_CTLECMNMODE_STG3_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_ctlecmnmode_stg3_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_runcount_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_smplroffset_finish_side_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALFSM_SMPLROFFSET_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_smplroffset_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsmmeas_ctlecmnmode_stg1_invert_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALFSMMEAS_CTLECMNMODE_STG1_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsmmeas_ctlecmnmode_stg2_invert_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALFSMMEAS_CTLECMNMODE_STG2_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsmmeas_ctlecmnmode_stg3_invert_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALFSMMEAS_CTLECMNMODE_STG3_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsmmeas_smplroffset_invert_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALFSMMEAS_SMPLROFFSET_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_ctlecmnmode_stg1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_ctlecmnmode_stg2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_ctlecmnmode_stg3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_aux0_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_aux1_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_d0_bot_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_d0_mid_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_d0_top_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_d1_bot_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_d1_mid_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_d1_top_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_e0_lo_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_e1_lo_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeas_pow2count_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasin_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasin_req_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASIN_REQ_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasin_req_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASIN_REQ_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasin_req_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASIN_REQ_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasout_ack_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASOUT_ACK_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasout_ack_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASOUT_ACK_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasout_ack_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASOUT_ACK_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasout_avg_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASOUT_AVG_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasout_avg_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASOUT_AVG_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasout_avg_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASOUT_AVG_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasout_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaloffsetfsmout_auxdatacomp_offset_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALOFFSETFSMOUT_AUXDATACOMP_OFFSET_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaloffsetfsmout_boost_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALOFFSETFSMOUT_BOOST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaloffsetfsmout_edgecomp_offset_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALOFFSETFSMOUT_EDGECOMP_OFFSET_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaloffsetfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalset_cal_clear_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalset_cal_mode_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALSET_CAL_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalset_cal_req_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALSET_CAL_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalset_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalstat_cal_ack_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALSTAT_CAL_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalstat_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalsummerfsmout_comp_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALSUMMERFSMOUT_COMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalsummerfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALSUMMERFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcdrphd_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCDRPHD_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcdrphd_override_ignore_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCDRPHD_OVERRIDE_IGNORE_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_caloffset_range_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_calstg1offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_calstg1offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_calstg2offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_calstg2offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_calstg3offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_calstg3offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_dccouple_sigpath_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCTLE_DCCOUPLE_SIGPATH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_lbbiasboost_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCTLE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_stg1tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_stg2tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_stg3tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_tfrtrim_outmem_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCTLE_TFRTRIM_OUTMEM_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_tfrtrim_outpen_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCTLE_TFRTRIM_OUTPEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctledc_dccouple_tgate_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCTLEDC_DCCOUPLE_TGATE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctledc_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCTLEDC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxdfe_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXDFE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxdfe_tapgain_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxdfepam_enable_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXDFEPAM_ENABLE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxdfepam_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXDFEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxdpifjit_enb_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXDPIFJIT_ENB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxdpifjit_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXDPIFJIT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxdpifjit_offset_locovr_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqadj_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQADJ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqadj_yadjust_aux0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqadj_yadjust_aux1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqadj_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqadj_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqadj_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqadj_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqadj_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqadj_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqauxxor_amux_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqauxxor_dmux_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqauxxor_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQAUXXOR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcal2flx_pstate_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCAL2FLX_PSTATE_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcal2flx_rate_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCAL2FLX_RATE_MASK_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_16a_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_16b_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_16c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_16d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_16e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_1a_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_1b_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_1c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_1d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_1e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_2a_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_2b_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_2c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_2d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_2e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_4a_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_4b_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_4c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_4d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_4e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_8a_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_8b_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_8c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_8d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_8e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_16a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_16b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_16c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_16d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_16e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_1a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_1b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_1c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_1d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_1e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_2a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_2b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_2c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_2d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_2e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_4a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_4b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_4c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_4d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_4e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_8a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_8b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_8c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_8d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_8e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_16a_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_16b_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_16c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_16d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_16e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_1a_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_1b_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_1c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_1d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_1e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_2a_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_2b_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_2c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_2d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_2e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_4a_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_4b_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_4c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_4d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_4e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_8a_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_8b_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_8c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_8d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_8e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcals_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCALS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcals_offset_datasummer0_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcals_offset_datasummer0_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcals_offset_datasummer1_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcals_offset_datasummer1_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcals_offset_edgesummer0_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcals_offset_edgesummer0_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcals_offset_edgesummer1_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcals_offset_edgesummer1_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcdr_force_ltr_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCDR_FORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcdr_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCDR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqctl_clear_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCTL_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqctl_fg_run_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCTL_FG_RUN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqctlelut_hifreqagcres_ovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCTLELUT_HIFREQAGCRES_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqctlelut_hifreqvgagain_ovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCTLELUT_HIFREQVGAGAIN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqctls_oddeven_tapgain_sel_inv_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCTLS_ODDEVEN_TAPGAIN_SEL_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqctls_static_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCTLS_STATIC_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqdat_aux_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQDAT_AUX_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqdat_edge_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQDAT_EDGE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqdatactl_auxswap_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqdatactl_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQDATACTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqdatarate_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQDATARATE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqdatarate_rx_rate_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqdfeyadj_agingl2r_delay_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqdfeyadj_agingl2r_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQDFEYADJ_AGINGL2R_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqedgeadj_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEDGEADJ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqedgeadj_yadjust_edge0lo_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqedgeadj_yadjust_edge1lo_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm2flx_ehm_done_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHM2FLX_EHM_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm2flx_ehm_done_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHM2FLX_EHM_DONE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm2flx_ehm_err_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHM2FLX_EHM_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm2flx_ehm_err_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHM2FLX_EHM_ERR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm2flx_ehm_fom_locovr_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHM2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_data_extshift_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHM_DATA_EXTSHIFT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_distance_th_50p_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_distance_th_rate_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_err_mask_vf00_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_err_mask_vf01_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_event_rate_vf00_attr == 32'd67108864
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_event_rate_vf01_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_general_in_vf00_attr == 32'd5521424
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_general_in_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_lms_th_50p_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_lms_th_rate_attr == 20'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_mask_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_no_change_th_50p_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_no_change_th_rate_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_reflections_num_50p_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_reflections_num_rate_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_slicer_swap_cb_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHM_SLICER_SWAP_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_sym_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_sym_dly_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_tap_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_test_aux_slicer_val_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_test_hits_th_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjaux_ehm_yadjust_aux0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjaux_ehm_yadjust_aux1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjaux_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJAUX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjauxen_ehm_aux_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJAUXEN_EHM_AUX_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjauxen_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJAUXEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjauxltch_aux_yadj_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJAUXLTCH_AUX_YADJ_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjauxltch_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJAUXLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdata_ehm_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdata_ehm_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdata_ehm_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdata_ehm_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdata_ehm_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdata_ehm_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdata_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdataen_ehm_data_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJDATAEN_EHM_DATA_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdataen_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJDATAEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdataltch_data_yadj_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJDATALTCH_DATA_YADJ_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdataltch_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJDATALTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2ehm_ehm_run_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2EHM_EHM_RUN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2ehm_ehm_run_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2EHM_EHM_RUN_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2lms_coarse_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2LMS_COARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2lms_ctrl_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2LMS_CTRL_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2lms_dfecore_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2LMS_DFECORE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2lms_force_evrefupd_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2LMS_FORCE_EVREFUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2lms_freeze_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2LMS_FREEZE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2lms_incr_decr_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2LMS_INCR_DECR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2lms_mu_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2LMS_MU_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2lms_rst_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2LMS_RST_OVRDEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2ofc_ofc_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2OFC_OFC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2ofc_ofc_en_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2OFC_OFC_EN_OVRDEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx_pcs_rxeq_clr_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX_PCS_RXEQ_CLR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx_pcs_rxeq_start_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX_PCS_RXEQ_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx_pcs_rxeq_static_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX_PCS_RXEQ_STATIC_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx_rxrate2pcie1_map_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx_rxrate2pcie2_map_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx_rxrate2pcie3_map_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx_rxrate2pcie4_map_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxehmdata_ehm_data_slc_sel_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXEHMDATA_EHM_DATA_SLC_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxehmdata_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXEHMDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxfsm_generalpurpose_reg_in_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxfsm_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXFSM_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxfsm_pause_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXFSM_PAUSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxfsm_state_obs_hold_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXFSM_STATE_OBS_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxfsm_state_obs_sel_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXFSM_STATE_OBS_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxltr_force_ltr_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXLTR_FORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxltr_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXLTR_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxpcsrxeyediag_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXPCSRXEYEDIAG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxpcsrxeyediag_start_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXPCSRXEYEDIAG_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxsigdet_sel_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXSIGDET_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqfsm2ofc_ofc_cal_req_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFSM2OFC_OFC_CAL_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqfsm2ofc_ofc_cal_req_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFSM2OFC_OFC_CAL_REQ_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_16a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_16b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_16c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_16d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_16e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_1a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_1b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_1c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_1d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_1e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_2a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_2b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_2c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_2d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_2e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_4a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_4b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_4c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_4d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_4e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_8a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_8b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_8c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_8d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_8e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_done_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmax_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmax_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_SATMAX_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmax_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmax_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmax_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_SATMAX_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmax_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_SATMAX_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmax_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_SATMAX_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmin_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmin_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_SATMIN_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmin_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmin_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmin_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_SATMIN_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmin_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_SATMIN_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmin_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_SATMIN_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_stable_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_stable_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_STABLE_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_stable_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_stable_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_stable_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_STABLE_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_stable_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_STABLE_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_stable_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_STABLE_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsupd_chng_ack_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSUPD_CHNG_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsupd_chng_req_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSUPD_CHNG_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsupd_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSUPD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjaux_lms_vref0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjaux_lms_vref1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjaux_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJAUX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjauxen_lms_aux_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJAUXEN_LMS_AUX_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjauxen_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJAUXEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjauxltch_lms_aux_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJAUXLTCH_LMS_AUX_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjauxltch_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJAUXLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdata_lms_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdata_lms_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdata_lms_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdata_lms_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdata_lms_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdata_lms_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdata_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdataen_lms_data_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJDATAEN_LMS_DATA_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdataen_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJDATAEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdataltch_lms_data_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJDATALTCH_LMS_DATA_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdataltch_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJDATALTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjedge_lms_yadjust_edge0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjedge_lms_yadjust_edge1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjedge_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJEDGE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjedgeen_lms_edge_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJEDGEEN_LMS_EDGE_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjedgeen_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJEDGEEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjedgeltch_lms_edge_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJEDGELTCH_LMS_EDGE_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjedgeltch_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJEDGELTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqltch_dfe_aux_yadj_b_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLTCH_DFE_AUX_YADJ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqltch_dfe_b_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLTCH_DFE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqltch_dfe_data_yadj_b_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLTCH_DFE_DATA_YADJ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqltch_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqltchc_auxswap_b_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLTCHC_AUXSWAP_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqltchc_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLTCHC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofc2flx_ofc_cal_done_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQOFC2FLX_OFC_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofc2flx_ofc_cal_done_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQOFC2FLX_OFC_CAL_DONE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_ctle_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_ctle_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_ctle_rxstg1probemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_ctle_rxstg2_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_ctle_rxstg2probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_ctle_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_ctle_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_summer_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_summer_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_summer_rxstg1probemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_summer_rxstg2_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_summer_rxstg2probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_summer_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_summer_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_time_h_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_time_l_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_ctle_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_ctle_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_ctle_rxstg1probemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_ctle_rxstg2_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_ctle_rxstg2probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_ctle_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_ctle_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_summer_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_summer_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_summer_rxstg1probemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_summer_rxstg2_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_summer_rxstg2probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_summer_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_summer_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_time_l_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_compsel_ctle_st1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_compsel_ctle_st2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_compsel_ctle_st3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_compsel_idle_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_compsel_sa_d0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_compsel_sa_d1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_compsel_sa_e0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_compsel_sa_e1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_invert_comp_fb_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_lpexitcal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_lpexitcal_time_l_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_adapt_en_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_adapt_thr_sel_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_cal_en_attr == 8'd249
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_cal_thr_sel_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_data_disp_sticky_clr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQOFCCFG_OFC_DATA_DISP_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_disparity_disable_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQOFCCFG_OFC_DISPARITY_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_disparity_leak_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_disparity_thr_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_lpexitcal_en_attr == 8'd249
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_lpf_bypass_en_cb_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQOFCCFG_OFC_LPF_BYPASS_EN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_ratechangecal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_pre_timer_setting_pow2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ratechangecal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ratechangecal_time_l_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_rxinpprobemuxen_idle_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_rxstg1_stateen_idle_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_rxstg1probemuxen_idle_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_rxstg2_stateen_idle_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_rxstg2probemuxen_idle_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_rxstg3_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_rxstg3probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqout_init_restore_avail_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQOUT_INIT_RESTORE_AVAIL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqprecal_code_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqprecal_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQPRECAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_hf1deq_dir_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_BOOSTLUT_HF1DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_hf2deq_dir_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_BOOSTLUT_HF2DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_hf2reszero_dir_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_BOOSTLUT_HF2RESZERO_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_hf3deq_dir_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_BOOSTLUT_HF3DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_idx_hf1deq_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_idx_hf1deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_idx_hf2deq_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_idx_hf2deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_idx_hf2reszero_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_idx_hf2reszero_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_idx_hf3deq_vf00_attr == 32'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_idx_hf3deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_init_hf1deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_init_hf2deq_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_init_hf2reszero_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_init_hf3deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_cal_hifreqagcres_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_cal_hifreqvgagain_attr == 7'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_cal_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_cal_yadjust_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_biasboost_dir_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_GAINLUT_BIASBOOST_DIR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_hf1resdcgain_dir_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_GAINLUT_HF1RESDCGAIN_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_hf3resdcgain_dir_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_GAINLUT_HF3RESDCGAIN_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_biasboost_vf00_attr == 32'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_biasboost_vf01_attr == 32'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_biasboost_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_lbbiasboost_vf00_attr == 32'd268435454
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_lbbiasboost_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_lbbiasboost_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_init_biasboost_attr == 5'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_init_hf1resdcgain_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_init_hf3resdcgain_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_init_lbbiasboost_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_lbbiasboost_dir_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_GAINLUT_LBBIASBOOST_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_latch_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref0_initval_attr == 9'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref1_initval_attr == 9'd191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref2_initval_attr == 9'd321
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref3_initval_attr == 9'd451
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_decr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_AUXVREF_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_frac_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_AUXVREF_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_frac_reset_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_incr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_AUXVREF_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_incr_decr_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_pam4adj_swizzle_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_AUXVREF_PAM4ADJ_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_AUXVREF_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_pol_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_single_step_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_AUXVREF_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_stable_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_AUXVREF_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_AUXVREF_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_targ_0_hi_attr == 9'd160
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_targ_0_lo_attr == 9'd140
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_auxvref_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_auxvref_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_dfe_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_dfe_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_edge_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_edge_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_edgevref_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_edgevref_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_iqalign_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_iqalign_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_level_vga_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_vga_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_vga_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_blockcount_fast_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_BLOCKCOUNT_FAST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_coarse_detect_clear_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_COARSE_DETECT_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_coarse_detect_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_COARSE_DETECT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_continuous_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_CONTINUOUS_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_datastats_incr_decr_swizzle_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_DATASTATS_INCR_DECR_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_datastats_pol_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_DATASTATS_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_datastats_thres_attr == 16'd1023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe1_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe2_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe3_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe4p_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_core_sel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_decr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_DFE_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_frac_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_DFE_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_frac_reset_mask_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_incr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_DFE_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_incr_decr_mask_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_inner_lvl_filter_en_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_DFE_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_pol_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_single_step_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_DFE_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_stable_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_DFE_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_DFE_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_targtap1_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_targtap2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_targtap3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_targtap4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_decr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGE_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_frac_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGE_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_frac_reset_mask_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_incr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGE_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_incr_decr_mask_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGE_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_pol_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_single_step_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGE_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_stable_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGE_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGE_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_decr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGEVREF_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_frac_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGEVREF_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGEVREF_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_incr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGEVREF_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_initval_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGEVREF_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_pol_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGEVREF_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_single_step_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGEVREF_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_stable_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGEVREF_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGEVREF_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_fast_blockcnt_attr == 16'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_filter_mode_auxvref_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_filter_mode_dfe_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_filter_mode_edge_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_filter_mode_edgevref_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_filter_mode_iqalign_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_filter_mode_vga_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_freeze_auxvrefupd_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_freeze_dfeupd_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_freeze_edgeupd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_freeze_edgevrefupd_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_FREEZE_EDGEVREFUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_freeze_forcebg_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_FREEZE_FORCEBG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_freeze_hifreqagcupd_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_FREEZE_HIFREQAGCUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_freeze_iqalignupd_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_FREEZE_IQALIGNUPD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_freeze_lofreqagcupd_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_FREEZE_LOFREQAGCUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_freeze_vgaupd_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_FREEZE_VGAUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_gated_update_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_GATED_UPDATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_accum_count_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_accum_level_en_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_decr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_HIFREQAGC_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_frac_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_HIFREQAGC_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_HIFREQAGC_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_incr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_HIFREQAGC_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_n1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_n2_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_n3_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_n4_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_n5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_HIFREQAGC_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_pol_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_HIFREQAGC_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_single_step_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_HIFREQAGC_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_stable_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_HIFREQAGC_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_HIFREQAGC_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_init_adapt_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_INIT_ADAPT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_decr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_IQALIGN_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_frac_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_IQALIGN_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_IQALIGN_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_incr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_IQALIGN_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_IQALIGN_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_pol_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_IQALIGN_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_single_step_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_IQALIGN_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_stable_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_IQALIGN_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_IQALIGN_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_targ_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_itercount_attr == 10'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_latch_delay_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_latch_prepost_delay_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_decr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOFREQAGC_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_frac_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOFREQAGC_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOFREQAGC_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_incr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOFREQAGC_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOFREQAGC_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_pol_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOFREQAGC_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_single_step_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOFREQAGC_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_stable_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOFREQAGC_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOFREQAGC_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_logain_auxvref_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOGAIN_AUXVREF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_logain_dfe_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_logain_edge_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_logain_edgevref_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOGAIN_EDGEVREF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_logain_hifreqagc_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOGAIN_HIFREQAGC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_logain_iqalign_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOGAIN_IQALIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_logain_lofreqagc_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOGAIN_LOFREQAGC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_logain_vga_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOGAIN_VGA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_auxvref_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_dfe1_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_dfe23_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_dfe4p_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_edge2_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_edge3_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_edge4_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_edgevref_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_hifreqagc_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_iqalign_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_lofreqagc_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_vga_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_nrz_to_pam4_mode_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_NRZ_TO_PAM4_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_slow_blockcnt_attr == 16'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_start_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_tsettle_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_accum_count_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_accum_level_en_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_decr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_frac_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_incr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_mode_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_pol_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_single_step_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_stable_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_yadjdata_mid_clamp_zero_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_YADJDATA_MID_CLAMP_ZERO_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lofreqagcgain_sel_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LOFREQAGCGAIN_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_caldfedatatap1gain_attr == 6'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_caldfedatatap2gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_caldfedatatap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_caldfedatatap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_caldfeedgetap2gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_caldfeedgetap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_caldfeedgetap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_hifreqagcres_attr == 6'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_hifreqvgagain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_caldfedatatap1gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_caldfedatatap1gain_attr == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_caldfedatatap1gain_attr == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_shift_auxshft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_shift_capture_trigger_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_SHIFT_CAPTURE_TRIGGER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_shift_clear_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_SHIFT_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_shift_dat_bitsel_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_SHIFT_DAT_BITSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_shift_datashft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_shift_edgeshft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_shift_edgeshft_nrz8b10b_pam16b20b_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_shift_polarity_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_SHIFT_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap10gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap11gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap12gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap13gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap14gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap15gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap16gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap1gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap2gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap5gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap6gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap7gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap8gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap9gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfeedgetap2gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfeedgetap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfeedgetap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_hifreqvgagain_attr == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_auxvref0_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_auxvref1_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_auxvref2_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_auxvref3_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_caldfedatatap1gain_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_caldfeedgetap2gain_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_calhifreqagcres_attr == 6'd38
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_callofreqagcgain_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_edgevref_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_hifreqvgagain_attr == 7'd45
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_iqalign_attr == 6'd45
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_auxvref0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_auxvref1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_auxvref2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_auxvref3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_caldfedatatap1gain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_caldfeedgetap2gain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_calhifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_callofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_edgevref_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_iqalign_attr == 6'd21
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqsetnrztopam4_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSETNRZTOPAM4_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqsetnrztopam4_switch_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSETNRZTOPAM4_SWITCH_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqsigdet_pause_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSIGDET_PAUSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqspare0_attr == 32'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqspare1_attr == 32'd15871
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqspare2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqsync2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSYNC2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqsync2flx_rxdatapath_ready_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSYNC2FLX_RXDATAPATH_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqtapctrl_data_tap13to16_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQTAPCTRL_DATA_TAP13TO16_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqtapctrl_data_tap1to4_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQTAPCTRL_DATA_TAP1TO4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqtapctrl_data_tap5to8_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQTAPCTRL_DATA_TAP5TO8_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqtapctrl_data_tap9to12_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQTAPCTRL_DATA_TAP9TO12_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqtapctrl_edge_tap_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQTAPCTRL_EDGE_TAP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqtapctrl_tap1to4gain_dbl_res_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQTAPCTRL_TAP1TO4GAIN_DBL_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqtapctrl_tap5to16gain_dbl_res_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQTAPCTRL_TAP5TO16GAIN_DBL_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvalc_hifreqagcbiasadjust_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvalc_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQVALC_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvalc_midbandzero_locovr_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvalcl_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQVALCL_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvalcl_lofreqagcgain_locovr_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap01gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap02gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap03gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap04gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap05gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap06gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap07gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap08gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap09gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap10gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap11gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap12gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap13gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap14gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap15gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap16gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQVALD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvale_caldfeedgetap02gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvale_caldfeedgetap03gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvale_caldfeedgetap04gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvale_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQVALE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1cal_clear_mask_attr == 13'd8184
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_aux0_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_aux1_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_d0_bot_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_d0_mid_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_d0_top_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_d1_bot_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_d1_mid_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_d1_top_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_e0_lo_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_e1_lo_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2cal_clear_mask_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_aux0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_aux1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_d0_bot_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_d0_mid_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_d0_top_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_d1_bot_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_d1_mid_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_d1_top_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_e0_lo_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_e1_lo_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfgcal_calfsmmeas_dlycount_attr == 10'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfgcal_fsmmaxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfgcal_lpfax_coarse_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfgcal_lpfax_fine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxhifreqagc_inputcmadjust_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxhifreqagc_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXHIFREQAGC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcal_clear_mask_attr == 13'd8191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_ctlecmnmode_stg3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_aux0_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_aux1_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_d0_bot_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_d0_mid_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_d0_top_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_d1_bot_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_d1_mid_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_d1_top_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_e0_lo_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_e1_lo_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmargin_flx_jit_offset_shift_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmargin_jit_disable_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmargin_jit_enable_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmargin_jit_offset_shift_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmargin_jit_setup_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmargin_volt_comp_mask_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmargin_volt_forcel2d_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXMARGIN_VOLT_FORCEL2D_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmargin_volt_offset_shift_d0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmargin_volt_offset_shift_d1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmarginin_direction_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXMARGININ_DIRECTION_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmarginin_flx_jit_offset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmarginin_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXMARGININ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmarginin_mode_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXMARGININ_MODE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmarginin_offset_change_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXMARGININ_OFFSET_CHANGE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmarginin_offset_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmarginin_start_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXMARGININ_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxsum_cm_vref_attr == 9'd75
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxsum_summer_cmfb_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXSUM_SUMMER_CMFB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxsum_summer_cmfb_ibias_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_done_pwr2_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_apb_dwmask_muxd0_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_apb_dwmask_muxd1_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_apb_dwmask_muxd2_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_apb_dwmask_muxd3_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_apb_dwmask_muxd4_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_a2f_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_a2f_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_a2f_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_a2f_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_a2f_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd0_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd1_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd2_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd3_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd4_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd0_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd1_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd2_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd3_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd4_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd0_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd1_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd2_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd3_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd4_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd0_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd1_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd2_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd3_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd4_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd0_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd1_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd2_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd3_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd4_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_marker_muxd0_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_marker_muxd1_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_marker_muxd2_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_marker_muxd3_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_marker_muxd4_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd0_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd1_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd2_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd3_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd4_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd0_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd1_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd2_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd3_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd1_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd2_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd3_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd4_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd0_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd3_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd4_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd0_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd2_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd0_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd2_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd3_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd4_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd0_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd1_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd2_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd3_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd4_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd0_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd1_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd2_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd3_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd4_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd0_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd1_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd2_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd3_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd4_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd0_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd1_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd2_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd3_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd4_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd2_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd3_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd4_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd0_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd2_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd0_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd0_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd1_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd2_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd3_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd4_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd0_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd1_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd2_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd3_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd4_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd4_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd0_attr == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd1_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd2_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd3_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd4_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd0_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd1_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd2_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd3_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd4_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_lock_thresh_muxd0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_lock_thresh_muxd1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_lock_thresh_muxd2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_lock_thresh_muxd3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_lock_thresh_muxd4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd0_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd1_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd2_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd3_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd4_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchn_offset_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchn_offset_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchn_offset_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchn_offset_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchn_offset_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchp_offset_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchp_offset_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchp_offset_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchp_offset_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchp_offset_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_bypass_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_bypass_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_bypass_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_bypass_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_bypass_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd4_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_step_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_step_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_step_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_step_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_step_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd0_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd1_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd2_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd3_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd4_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd0_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd2_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd0_attr == 8'd148
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd1_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd2_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd3_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd4_attr == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd0_attr == 18'd14336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd1_attr == 18'd14336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd2_attr == 18'd14336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd3_attr == 18'd14336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd4_attr == 18'd14336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd2_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd3_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd4_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_fll_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_fll_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_fll_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_fll_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_fll_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_pll_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_pll_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_pll_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_pll_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_pll_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd0_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd1_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd2_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd4_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd0_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd1_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd3_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd4_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_temp_track_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_temp_track_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_temp_track_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_temp_track_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_temp_track_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd0_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd1_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd2_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd3_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd4_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd0_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd1_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd2_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd3_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd4_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd0_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd1_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd2_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd3_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd4_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd0_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd1_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd2_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd3_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd4_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bb_gain_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bb_gain_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bb_gain_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bb_gain_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bb_gain_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbinlock_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbinlock_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbinlock_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbinlock_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbinlock_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbthresh_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbthresh_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbthresh_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbthresh_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbthresh_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrlhext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrlhext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrlhext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrlhext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrlhext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrllext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrllext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrllext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrllext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrllext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_muxd0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_muxd1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_muxd2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_muxd3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_muxd4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcoditheren_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcoditheren_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcoditheren_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcoditheren_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcoditheren_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofine_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofine_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofine_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofine_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofine_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofinedftsel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofinedftsel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofinedftsel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofinedftsel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofinedftsel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dither_value_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dither_value_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dither_value_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dither_value_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dither_value_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_earlylock_criteria_muxd0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_earlylock_criteria_muxd1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_earlylock_criteria_muxd2_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_earlylock_criteria_muxd3_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_earlylock_criteria_muxd4_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_frac_muxd0_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_frac_muxd1_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_frac_muxd2_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_frac_muxd3_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_frac_muxd4_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd0_attr == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd1_attr == 9'd90
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd2_attr == 9'd54
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd3_attr == 9'd72
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd4_attr == 9'd432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdgain_muxd0_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdgain_muxd1_attr == 8'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdgain_muxd2_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdgain_muxd3_attr == 8'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdgain_muxd4_attr == 8'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fracnen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fracnen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fracnen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fracnen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fracnen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_lock_criteria_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_lock_criteria_muxd1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_lock_criteria_muxd2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_lock_criteria_muxd3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_lock_criteria_muxd4_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_regen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_regen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_regen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_regen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_regen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllock_sel_muxd0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllock_sel_muxd1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllock_sel_muxd2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllock_sel_muxd3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllock_sel_muxd4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdc_fine_res_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdc_fine_res_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdc_fine_res_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdc_fine_res_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdc_fine_res_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdccalexten_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdccalexten_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdccalexten_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdccalexten_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdccalexten_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcroen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcroen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcroen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcroen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcroen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcsel_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcsel_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcsel_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcsel_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcsel_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdctargetcnt_muxd0_attr == 8'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdctargetcnt_muxd1_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdctargetcnt_muxd2_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdctargetcnt_muxd3_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdctargetcnt_muxd4_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tribufctrlext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tribufctrlext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tribufctrlext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tribufctrlext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tribufctrlext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_done_pwr2_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_apb_dwmask_muxd0_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_apb_dwmask_muxd1_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_apb_dwmask_muxd2_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_apb_dwmask_muxd3_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_apb_dwmask_muxd4_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_a2f_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_a2f_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_a2f_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_a2f_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_a2f_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd0_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd1_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd2_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd3_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd4_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd0_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd1_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd2_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd3_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd4_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd0_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd1_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd2_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd3_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd4_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd0_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd1_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd2_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd3_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd4_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd0_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd1_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd2_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd3_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd4_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_marker_muxd0_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_marker_muxd1_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_marker_muxd2_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_marker_muxd3_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_marker_muxd4_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd0_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd1_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd2_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd3_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd4_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd0_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd1_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd2_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd3_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd0_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd1_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd2_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd3_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd4_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd0_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd3_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd4_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd0_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd2_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd2_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd3_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd4_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd0_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd1_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd2_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd3_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd4_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd0_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd1_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd2_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd3_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd4_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd0_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd1_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd2_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd3_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd4_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd0_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd1_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd2_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd3_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd4_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd2_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd3_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd4_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd0_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd2_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd0_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd0_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd1_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd2_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd3_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd4_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd0_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd1_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd2_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd3_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd4_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd4_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd0_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd1_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd2_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd3_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd4_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd0_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd1_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd2_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd3_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd4_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_lock_thresh_muxd0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_lock_thresh_muxd1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_lock_thresh_muxd2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_lock_thresh_muxd3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_lock_thresh_muxd4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd0_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd1_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd2_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd3_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd4_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchn_offset_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchn_offset_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchn_offset_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchn_offset_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchn_offset_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchp_offset_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchp_offset_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchp_offset_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchp_offset_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchp_offset_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_bypass_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_bypass_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_bypass_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_bypass_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_bypass_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd4_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_step_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_step_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_step_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_step_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_step_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd0_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd1_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd2_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd3_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd4_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd2_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd0_attr == 8'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd1_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd2_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd3_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd4_attr == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd0_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd1_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd2_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd3_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd4_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd2_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd3_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd4_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_fll_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_fll_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_fll_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_fll_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_fll_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_pll_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_pll_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_pll_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_pll_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_pll_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd0_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd1_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd2_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd4_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd0_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd1_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd3_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd4_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_temp_track_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_temp_track_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_temp_track_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_temp_track_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_temp_track_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd0_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd1_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd2_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd3_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd4_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd0_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd1_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd2_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd3_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd4_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd0_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd1_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd2_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd3_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd4_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd0_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd1_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd2_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd3_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd4_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bb_gain_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bb_gain_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bb_gain_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bb_gain_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bb_gain_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbinlock_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbinlock_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbinlock_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbinlock_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbinlock_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbthresh_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbthresh_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbthresh_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbthresh_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbthresh_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrlhext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrlhext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrlhext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrlhext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrlhext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrllext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrllext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrllext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrllext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrllext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_muxd0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_muxd1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_muxd2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_muxd3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_muxd4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcoditheren_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcoditheren_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcoditheren_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcoditheren_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcoditheren_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofine_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofine_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofine_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofine_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofine_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofinedftsel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofinedftsel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofinedftsel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofinedftsel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofinedftsel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dither_value_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dither_value_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dither_value_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dither_value_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dither_value_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_earlylock_criteria_muxd0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_earlylock_criteria_muxd1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_earlylock_criteria_muxd2_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_earlylock_criteria_muxd3_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_earlylock_criteria_muxd4_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_frac_muxd0_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_frac_muxd1_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_frac_muxd2_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_frac_muxd3_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_frac_muxd4_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd0_attr == 9'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd1_attr == 9'd45
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd2_attr == 9'd27
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd3_attr == 9'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd4_attr == 9'd216
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdgain_muxd0_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdgain_muxd1_attr == 8'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdgain_muxd2_attr == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdgain_muxd3_attr == 8'd23
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdgain_muxd4_attr == 8'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fracnen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fracnen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fracnen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fracnen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fracnen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_lock_criteria_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_lock_criteria_muxd1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_lock_criteria_muxd2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_lock_criteria_muxd3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_lock_criteria_muxd4_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_regen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_regen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_regen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_regen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_regen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllock_sel_muxd0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllock_sel_muxd1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllock_sel_muxd2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllock_sel_muxd3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllock_sel_muxd4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdc_fine_res_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdc_fine_res_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdc_fine_res_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdc_fine_res_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdc_fine_res_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdccalexten_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdccalexten_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdccalexten_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdccalexten_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdccalexten_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcroen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcroen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcroen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcroen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcroen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcsel_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcsel_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcsel_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcsel_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcsel_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdctargetcnt_muxd0_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdctargetcnt_muxd1_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdctargetcnt_muxd2_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdctargetcnt_muxd3_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdctargetcnt_muxd4_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tribufctrlext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tribufctrlext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tribufctrlext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tribufctrlext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tribufctrlext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_done_pwr2_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_apb_dwmask_muxd0_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_apb_dwmask_muxd1_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_apb_dwmask_muxd2_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_apb_dwmask_muxd3_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_apb_dwmask_muxd4_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_a2f_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_a2f_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_a2f_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_a2f_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_a2f_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd0_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd1_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd2_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd3_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd4_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd0_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd1_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd2_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd3_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd4_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd0_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd1_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd2_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd3_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd4_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd0_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd1_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd2_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd3_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd4_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd0_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd1_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd2_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd3_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd4_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_marker_muxd0_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_marker_muxd1_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_marker_muxd2_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_marker_muxd3_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_marker_muxd4_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd0_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd1_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd2_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd3_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd4_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd0_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd1_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd2_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd3_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd1_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd2_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd3_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd4_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd0_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd3_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd4_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd0_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd2_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd0_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd2_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd3_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd4_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd0_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd1_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd2_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd3_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd4_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd0_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd1_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd2_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd3_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd4_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd0_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd1_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd2_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd3_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd4_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd0_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd1_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd2_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd3_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd4_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd2_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd3_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd4_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd0_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd2_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd0_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd0_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd1_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd2_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd3_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd4_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd0_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd1_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd2_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd3_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd4_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd4_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd0_attr == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd1_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd2_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd3_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd4_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd0_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd1_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd2_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd3_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd4_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_lock_thresh_muxd0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_lock_thresh_muxd1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_lock_thresh_muxd2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_lock_thresh_muxd3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_lock_thresh_muxd4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd0_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd1_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd2_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd3_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd4_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchn_offset_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchn_offset_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchn_offset_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchn_offset_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchn_offset_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchp_offset_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchp_offset_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchp_offset_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchp_offset_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchp_offset_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_bypass_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_bypass_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_bypass_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_bypass_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_bypass_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd4_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_step_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_step_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_step_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_step_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_step_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd0_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd1_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd2_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd3_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd4_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd0_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd2_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd0_attr == 8'd148
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd1_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd2_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd3_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd4_attr == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd0_attr == 18'd14336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd1_attr == 18'd14336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd2_attr == 18'd14336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd3_attr == 18'd14336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd4_attr == 18'd14336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd2_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd3_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd4_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_fll_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_fll_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_fll_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_fll_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_fll_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_pll_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_pll_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_pll_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_pll_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_pll_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd0_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd1_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd2_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd4_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd0_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd1_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd3_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd4_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_temp_track_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_temp_track_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_temp_track_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_temp_track_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_temp_track_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd0_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd1_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd2_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd3_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd4_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd0_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd1_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd2_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd3_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd4_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd0_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd1_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd2_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd3_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd4_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd0_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd1_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd2_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd3_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd4_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bb_gain_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bb_gain_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bb_gain_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bb_gain_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bb_gain_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbinlock_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbinlock_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbinlock_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbinlock_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbinlock_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbthresh_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbthresh_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbthresh_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbthresh_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbthresh_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrlhext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrlhext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrlhext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrlhext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrlhext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrllext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrllext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrllext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrllext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrllext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_muxd0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_muxd1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_muxd2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_muxd3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_muxd4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcoditheren_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcoditheren_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcoditheren_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcoditheren_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcoditheren_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofine_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofine_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofine_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofine_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofine_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofinedftsel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofinedftsel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofinedftsel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofinedftsel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofinedftsel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dither_value_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dither_value_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dither_value_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dither_value_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dither_value_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_earlylock_criteria_muxd0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_earlylock_criteria_muxd1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_earlylock_criteria_muxd2_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_earlylock_criteria_muxd3_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_earlylock_criteria_muxd4_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_frac_muxd0_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_frac_muxd1_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_frac_muxd2_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_frac_muxd3_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_frac_muxd4_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd0_attr == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd1_attr == 9'd90
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd2_attr == 9'd54
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd3_attr == 9'd72
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd4_attr == 9'd432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdgain_muxd0_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdgain_muxd1_attr == 8'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdgain_muxd2_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdgain_muxd3_attr == 8'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdgain_muxd4_attr == 8'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fracnen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fracnen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fracnen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fracnen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fracnen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_lock_criteria_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_lock_criteria_muxd1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_lock_criteria_muxd2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_lock_criteria_muxd3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_lock_criteria_muxd4_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_regen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_regen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_regen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_regen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_regen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllock_sel_muxd0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllock_sel_muxd1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllock_sel_muxd2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllock_sel_muxd3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllock_sel_muxd4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdc_fine_res_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdc_fine_res_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdc_fine_res_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdc_fine_res_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdc_fine_res_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdccalexten_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdccalexten_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdccalexten_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdccalexten_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdccalexten_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcroen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcroen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcroen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcroen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcroen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcsel_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcsel_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcsel_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcsel_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcsel_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdctargetcnt_muxd0_attr == 8'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdctargetcnt_muxd1_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdctargetcnt_muxd2_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdctargetcnt_muxd3_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdctargetcnt_muxd4_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tribufctrlext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tribufctrlext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tribufctrlext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tribufctrlext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tribufctrlext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_done_pwr2_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_apb_dwmask_muxd0_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_apb_dwmask_muxd1_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_apb_dwmask_muxd2_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_apb_dwmask_muxd3_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_apb_dwmask_muxd4_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_a2f_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_a2f_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_a2f_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_a2f_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_a2f_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd0_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd1_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd2_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd3_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd4_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd0_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd1_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd2_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd3_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd4_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd0_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd1_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd2_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd3_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd4_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd0_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd1_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd2_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd3_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd4_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd0_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd1_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd2_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd3_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd4_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_marker_muxd0_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_marker_muxd1_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_marker_muxd2_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_marker_muxd3_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_marker_muxd4_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd0_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd1_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd2_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd3_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd4_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd0_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd1_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd2_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd3_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd1_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd2_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd3_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd4_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd0_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd3_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd4_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd0_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd2_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd0_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd2_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd3_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd4_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd0_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd1_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd2_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd3_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd4_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd0_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd1_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd2_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd3_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd4_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd0_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd1_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd2_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd3_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd4_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd0_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd1_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd2_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd3_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd4_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd2_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd3_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd4_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd0_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd2_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd0_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd0_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd1_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd2_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd3_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd4_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd0_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd1_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd2_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd3_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd4_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd4_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd0_attr == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd1_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd2_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd3_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd4_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd0_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd1_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd2_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd3_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd4_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_lock_thresh_muxd0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_lock_thresh_muxd1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_lock_thresh_muxd2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_lock_thresh_muxd3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_lock_thresh_muxd4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd0_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd1_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd2_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd3_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd4_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchn_offset_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchn_offset_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchn_offset_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchn_offset_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchn_offset_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchp_offset_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchp_offset_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchp_offset_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchp_offset_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchp_offset_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_bypass_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_bypass_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_bypass_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_bypass_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_bypass_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd4_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_step_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_step_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_step_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_step_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_step_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd0_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd1_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd2_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd3_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd4_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd0_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd2_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd0_attr == 8'd148
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd1_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd2_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd3_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd4_attr == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd0_attr == 18'd14336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd1_attr == 18'd14336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd2_attr == 18'd14336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd3_attr == 18'd14336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd4_attr == 18'd14336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd2_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd3_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd4_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_fll_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_fll_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_fll_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_fll_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_fll_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_pll_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_pll_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_pll_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_pll_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_pll_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd0_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd1_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd2_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd4_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd0_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd1_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd3_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd4_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_temp_track_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_temp_track_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_temp_track_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_temp_track_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_temp_track_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd0_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd1_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd2_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd3_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd4_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd0_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd1_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd2_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd3_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd4_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd0_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd1_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd2_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd3_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd4_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd0_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd1_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd2_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd3_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd4_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bb_gain_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bb_gain_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bb_gain_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bb_gain_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bb_gain_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbinlock_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbinlock_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbinlock_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbinlock_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbinlock_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbthresh_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbthresh_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbthresh_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbthresh_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbthresh_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrlhext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrlhext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrlhext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrlhext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrlhext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrllext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrllext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrllext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrllext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrllext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_muxd0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_muxd1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_muxd2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_muxd3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_muxd4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcoditheren_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcoditheren_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcoditheren_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcoditheren_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcoditheren_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofine_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofine_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofine_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofine_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofine_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofinedftsel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofinedftsel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofinedftsel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofinedftsel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofinedftsel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dither_value_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dither_value_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dither_value_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dither_value_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dither_value_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_earlylock_criteria_muxd0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_earlylock_criteria_muxd1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_earlylock_criteria_muxd2_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_earlylock_criteria_muxd3_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_earlylock_criteria_muxd4_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_frac_muxd0_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_frac_muxd1_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_frac_muxd2_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_frac_muxd3_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_frac_muxd4_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd0_attr == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd1_attr == 9'd90
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd2_attr == 9'd54
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd3_attr == 9'd72
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd4_attr == 9'd432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdgain_muxd0_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdgain_muxd1_attr == 8'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdgain_muxd2_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdgain_muxd3_attr == 8'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdgain_muxd4_attr == 8'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fracnen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fracnen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fracnen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fracnen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fracnen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_lock_criteria_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_lock_criteria_muxd1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_lock_criteria_muxd2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_lock_criteria_muxd3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_lock_criteria_muxd4_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_regen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_regen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_regen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_regen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_regen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllock_sel_muxd0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllock_sel_muxd1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllock_sel_muxd2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllock_sel_muxd3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllock_sel_muxd4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdc_fine_res_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdc_fine_res_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdc_fine_res_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdc_fine_res_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdc_fine_res_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdccalexten_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdccalexten_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdccalexten_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdccalexten_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdccalexten_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcroen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcroen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcroen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcroen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcroen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcsel_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcsel_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcsel_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcsel_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcsel_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdctargetcnt_muxd0_attr == 8'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdctargetcnt_muxd1_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdctargetcnt_muxd2_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdctargetcnt_muxd3_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdctargetcnt_muxd4_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tribufctrlext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tribufctrlext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tribufctrlext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tribufctrlext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tribufctrlext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_a2f_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_clkouten_cb_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_clkouten_lane_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_en_peak_sense_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_obsmux0_del_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_obsmux1_del_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_pcs40div_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_pll_bypass_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_refclk100div_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_refclk156div_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_sddiv_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_spare_dig2ana_attr == 18'd30720
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_ssc_track_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_stay_fll_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_stay_pll_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_temp_track_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_bbinlock_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_dcoditheren_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_fracnen_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_pll_reg_resetb_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_plllc_regen_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_tdc_fine_res_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_tdccalexten_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_tdcdc_en_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_tdcroen_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_a2f_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_clkouten_cb_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_clkouten_lane_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_en_peak_sense_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_obsmux0_del_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_obsmux1_del_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_pcs40div_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_pll_bypass_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_refclk100div_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_refclk156div_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_sddiv_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_spare_dig2ana_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_ssc_track_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_stay_fll_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_stay_pll_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_temp_track_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_bbinlock_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_dcoditheren_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_fracnen_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_pll_reg_resetb_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_plllc_regen_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_tdc_fine_res_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_tdccalexten_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_tdcdc_en_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_tdcroen_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_a2f_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_clkouten_cb_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_clkouten_lane_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_en_peak_sense_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_obsmux0_del_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_obsmux1_del_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_pcs40div_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_pll_bypass_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_refclk100div_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_refclk156div_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_sddiv_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_spare_dig2ana_attr == 18'd30720
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_ssc_track_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_stay_fll_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_stay_pll_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_temp_track_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_bbinlock_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_dcoditheren_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_fracnen_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_pll_reg_resetb_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_plllc_regen_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_tdc_fine_res_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_tdccalexten_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_tdcdc_en_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_tdcroen_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_a2f_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_clkouten_cb_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_clkouten_lane_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_en_peak_sense_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_obsmux0_del_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_obsmux1_del_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_pcs40div_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_pll_bypass_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_refclk100div_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_refclk156div_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_sddiv_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_spare_dig2ana_attr == 18'd30720
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_ssc_track_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_stay_fll_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_stay_pll_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_temp_track_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_bbinlock_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_dcoditheren_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_fracnen_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_pll_reg_resetb_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_plllc_regen_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_tdc_fine_res_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_tdccalexten_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_tdcdc_en_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_tdcroen_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_a2f_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_clkouten_cb_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_clkouten_lane_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_en_peak_sense_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_obsmux0_del_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_obsmux1_del_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_pcs40div_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_pll_bypass_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_refclk100div_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_refclk156div_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_sddiv_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_spare_dig2ana_attr == 18'd30720
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_ssc_track_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_stay_fll_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_stay_pll_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_temp_track_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_bbinlock_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_dcoditheren_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_fracnen_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_pll_reg_resetb_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_plllc_regen_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_tdc_fine_res_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_tdccalexten_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_tdcdc_en_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_tdcroen_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_a2f_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_clkouten_cb_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_clkouten_lane_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_en_peak_sense_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_obsmux0_del_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_obsmux1_del_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_pcs40div_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_pll_bypass_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_refclk100div_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_refclk156div_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_sddiv_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_spare_dig2ana_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_ssc_track_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_stay_fll_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_stay_pll_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_temp_track_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_bbinlock_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_dcoditheren_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_fracnen_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_pll_reg_resetb_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_plllc_regen_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_tdc_fine_res_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_tdccalexten_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_tdcdc_en_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_tdcroen_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_a2f_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_clkouten_cb_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_clkouten_lane_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_en_peak_sense_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_obsmux0_del_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_obsmux1_del_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_pcs40div_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_pll_bypass_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_refclk100div_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_refclk156div_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_sddiv_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_spare_dig2ana_attr == 18'd30720
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_ssc_track_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_stay_fll_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_stay_pll_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_temp_track_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_bbinlock_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_dcoditheren_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_fracnen_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_pll_reg_resetb_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_plllc_regen_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_tdc_fine_res_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_tdccalexten_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_tdcdc_en_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_tdcroen_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_a2f_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_clkouten_cb_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_clkouten_lane_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_en_peak_sense_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_obsmux0_del_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_obsmux1_del_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_pcs40div_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_pll_bypass_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_refclk100div_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_refclk156div_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_sddiv_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_spare_dig2ana_attr == 18'd30720
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_ssc_track_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_stay_fll_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_stay_pll_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_temp_track_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_bbinlock_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_dcoditheren_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_fracnen_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_pll_reg_resetb_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_plllc_regen_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_tdc_fine_res_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_tdccalexten_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_tdcdc_en_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_tdcroen_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_a2f_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_clkouten_cb_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_clkouten_lane_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_en_peak_sense_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_obsmux0_del_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_obsmux1_del_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_pcs40div_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_pll_bypass_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_refclk100div_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_refclk156div_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_sddiv_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_spare_dig2ana_attr == 18'd14336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_ssc_track_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_stay_fll_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_stay_pll_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_temp_track_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_bbinlock_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_dcoditheren_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_fracnen_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_pll_reg_resetb_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_plllc_regen_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_tdc_fine_res_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_tdccalexten_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_tdcdc_en_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_tdcroen_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_a2f_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_clkouten_cb_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_clkouten_lane_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_en_peak_sense_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_obsmux0_del_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_obsmux1_del_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_pcs40div_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_pll_bypass_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_refclk100div_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_refclk156div_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_sddiv_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_spare_dig2ana_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_ssc_track_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_stay_fll_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_stay_pll_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_temp_track_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_bbinlock_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_dcoditheren_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_fracnen_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_pll_reg_resetb_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_plllc_regen_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_tdc_fine_res_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_tdccalexten_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_tdcdc_en_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_tdcroen_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_a2f_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_clkouten_cb_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_clkouten_lane_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_en_peak_sense_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_obsmux0_del_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_obsmux1_del_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_pcs40div_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_pll_bypass_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_refclk100div_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_refclk156div_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_sddiv_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_spare_dig2ana_attr == 18'd14336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_ssc_track_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_stay_fll_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_stay_pll_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_temp_track_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_bbinlock_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_dcoditheren_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_fracnen_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_pll_reg_resetb_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_plllc_regen_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_tdc_fine_res_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_tdccalexten_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_tdcdc_en_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_tdcroen_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_a2f_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_clkouten_cb_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_clkouten_lane_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_en_peak_sense_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_obsmux0_del_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_obsmux1_del_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_pcs40div_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_pll_bypass_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_refclk100div_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_refclk156div_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_sddiv_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_spare_dig2ana_attr == 18'd14336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_ssc_track_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_stay_fll_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_stay_pll_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_temp_track_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_bbinlock_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_dcoditheren_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_fracnen_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_pll_reg_resetb_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_plllc_regen_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_tdc_fine_res_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_tdccalexten_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_tdcdc_en_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_tdcroen_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_flavor_table_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_flavor_table_en_attr == SERDES_IP_RX_FLEX_L0_CFG_FLX_FLAVOR_TABLE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_force_frame_lock_attr == SERDES_IP_RX_FLEX_L0_CFG_FLX_FORCE_FRAME_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_freeze_in_state_attr == SERDES_IP_RX_FLEX_L0_CFG_FLX_FREEZE_IN_STATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_01_attr == 32'd65536
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_02_attr == 32'd2181070848
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_03_attr == 32'd2147491840
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_04_attr == 32'd2147483649
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_05_attr == 32'd2147483649
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_06_attr == 32'd2147483649
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_07_attr == 32'd2181038081
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_08_attr == 32'd16384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_09_attr == 32'd131072
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_10_attr == 32'd2147614720
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_11_attr == 32'd33554432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_12_attr == 32'd1075838976
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_13_attr == 32'd268435456
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_14_attr == 32'd2147491840
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_15_attr == 32'd2147614720
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_16_attr == 32'd268435457
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_17_attr == 32'd301989889
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_18_attr == 32'd33570816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_19_attr == 32'd33554432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_20_attr == 32'd33554432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_21_attr == 32'd2181054464
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_22_attr == 32'd2147484672
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_23_attr == 32'd33587200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_24_attr == 32'd2147614720
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_25_attr == 32'd33554432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_26_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_27_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_28_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_29_attr == 32'd33587200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_30_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_31_attr == 32'd1107296256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_02_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_03_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_04_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_05_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_06_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_07_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_10_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_12_attr == 5'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_13_attr == 5'd29
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_14_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_15_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_16_attr == 5'd29
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_17_attr == 5'd29
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_18_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_21_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_22_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_24_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_31_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_01_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_02_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_03_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_07_attr == 5'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_10_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_11_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_12_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_13_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_15_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_17_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_18_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_19_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_20_attr == 5'd21
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_21_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_23_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_25_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_29_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_31_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_one_state_inc_pulse_attr == SERDES_IP_RX_FLEX_L0_CFG_FLX_ONE_STATE_INC_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_00_attr == 32'd1187855
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_01_attr == 32'd9576479
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_02_attr == 32'd9437199
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_03_attr == 32'd9437199
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_04_attr == 32'd9554175
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_05_attr == 32'd9554943
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_06_attr == 32'd9554943
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_07_attr == 32'd9554943
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_08_attr == 32'd14680079
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_09_attr == 32'd25952527
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_10_attr == 32'd8651023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_11_attr == 32'd9437215
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_12_attr == 32'd8651023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_13_attr == 32'd8651023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_14_attr == 32'd8651023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_15_attr == 32'd25428239
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_16_attr == 32'd8735743
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_17_attr == 32'd8735487
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_18_attr == 32'd14942223
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_19_attr == 32'd12845071
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_20_attr == 32'd8392719
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_21_attr == 32'd14684175
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_22_attr == 32'd9519167
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_23_attr == 32'd9519119
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_24_attr == 32'd12582927
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_25_attr == 32'd12582927
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_26_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_27_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_28_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_29_attr == 32'd5505295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_30_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_31_attr == 32'd4456719
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_00_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_01_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_02_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_03_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_04_attr == 32'd4210819071
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_05_attr == 32'd4210771012
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_06_attr == 32'd2063305591
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_07_attr == 32'd2054911863
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_08_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_09_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_10_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_11_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_12_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_13_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_14_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_15_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_16_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_17_attr == 32'd1784366148
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_18_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_19_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_20_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_21_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_22_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_23_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_24_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_25_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_26_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_27_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_28_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_29_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_30_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_31_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_state_force_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_state_force_value_en_attr == SERDES_IP_RX_FLEX_L0_CFG_FLX_STATE_FORCE_VALUE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_flx_stop_tmr_in_handshake_attr == SERDES_IP_RX_FLEX_L0_CFG_FLX_STOP_TMR_IN_HANDSHAKE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_00_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_00_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_01_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_01_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_02_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_02_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_03_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_03_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_04_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_04_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_05_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_05_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_06_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_06_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_07_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_07_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_08_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_08_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_09_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_09_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_10_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_10_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_11_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_12_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_13_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_14_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_14_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_15_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_15_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_16_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_16_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_17_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_17_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_18_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_19_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_19_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_20_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_20_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_21_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_21_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_22_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_22_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_23_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_23_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_24_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_24_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_25_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_25_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_26_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_26_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_27_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_27_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_28_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_28_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_29_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_29_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_30_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_30_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_31_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_31_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_02_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_03_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_04_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_05_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_06_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_07_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_10_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_12_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_13_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_15_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_16_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_17_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_18_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_21_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_22_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_31_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_00_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_00_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_01_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_01_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_02_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_02_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_03_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_03_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_04_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_04_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_05_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_05_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_06_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_06_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_07_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_07_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_08_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_08_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_09_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_09_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_10_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_11_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_12_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_13_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_14_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_15_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_16_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_17_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_18_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_19_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_19_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_20_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_20_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_21_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_21_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_22_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_22_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_23_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_23_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_24_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_24_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_25_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_25_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_26_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_26_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_27_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_27_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_28_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_28_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_29_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_29_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_30_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_30_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_31_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_31_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_00_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_02_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_03_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_04_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_05_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_06_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_07_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_10_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_12_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_13_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_15_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_16_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_17_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_18_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_19_attr == 5'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_25_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_31_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_flavor_table_attr == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_flavor_table_en_attr == SERDES_IP_RX_FLEX_L1_CFG_FLX_FLAVOR_TABLE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_force_frame_lock_attr == SERDES_IP_RX_FLEX_L1_CFG_FLX_FORCE_FRAME_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_freeze_in_state_attr == SERDES_IP_RX_FLEX_L1_CFG_FLX_FREEZE_IN_STATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_01_attr == 32'd65537
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_02_attr == 32'd2147516416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_03_attr == 32'd2181169152
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_04_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_05_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_06_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_07_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_08_attr == 32'd16384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_09_attr == 32'd131072
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_10_attr == 32'd2416050176
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_11_attr == 32'd33554432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_12_attr == 32'd1075838976
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_13_attr == 32'd301989888
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_14_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_15_attr == 32'd2181169152
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_16_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_17_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_18_attr == 32'd302006272
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_19_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_20_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_21_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_22_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_23_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_24_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_25_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_26_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_27_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_28_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_29_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_30_attr == 32'd33587200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_31_attr == 32'd1107329024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_02_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_03_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_10_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_12_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_13_attr == 5'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_15_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_18_attr == 5'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_31_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_02_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_03_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_10_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_11_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_12_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_13_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_15_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_18_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_30_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_31_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_one_state_inc_pulse_attr == SERDES_IP_RX_FLEX_L1_CFG_FLX_ONE_STATE_INC_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_00_attr == 32'd1056783
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_01_attr == 32'd9510943
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_02_attr == 32'd9502735
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_03_attr == 32'd9437199
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_04_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_05_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_06_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_07_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_08_attr == 32'd14680079
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_09_attr == 32'd26017807
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_10_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_11_attr == 32'd9502735
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_12_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_13_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_14_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_15_attr == 32'd25493519
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_16_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_17_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_18_attr == 32'd14942223
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_19_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_20_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_21_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_22_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_23_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_24_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_25_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_26_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_27_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_28_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_29_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_30_attr == 32'd1376271
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_31_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_00_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_01_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_02_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_03_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_04_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_05_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_06_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_07_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_08_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_09_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_10_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_11_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_12_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_13_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_14_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_15_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_16_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_17_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_18_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_19_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_20_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_21_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_22_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_23_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_24_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_25_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_26_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_27_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_28_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_29_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_30_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_31_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_state_force_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_state_force_value_en_attr == SERDES_IP_RX_FLEX_L1_CFG_FLX_STATE_FORCE_VALUE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_flx_stop_tmr_in_handshake_attr == SERDES_IP_RX_FLEX_L1_CFG_FLX_STOP_TMR_IN_HANDSHAKE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_00_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_00_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_01_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_01_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_02_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_02_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_03_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_03_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_04_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_04_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_05_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_05_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_06_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_06_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_07_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_07_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_08_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_08_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_09_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_09_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_10_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_10_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_11_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_12_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_13_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_14_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_15_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_15_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_16_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_17_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_18_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_19_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_19_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_20_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_20_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_21_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_21_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_22_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_22_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_23_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_23_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_24_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_24_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_25_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_25_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_26_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_26_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_27_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_27_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_28_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_28_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_29_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_29_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_30_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_30_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_31_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_31_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_02_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_03_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_10_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_12_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_13_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_15_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_18_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_31_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_00_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_00_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_01_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_01_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_02_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_02_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_03_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_03_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_04_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_04_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_05_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_05_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_06_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_06_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_07_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_07_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_08_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_08_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_09_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_09_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_10_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_11_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_12_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_13_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_14_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_15_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_16_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_17_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_18_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_19_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_19_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_20_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_20_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_21_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_21_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_22_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_22_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_23_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_23_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_24_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_24_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_25_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_25_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_26_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_26_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_27_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_27_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_28_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_28_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_29_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_29_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_30_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_30_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_31_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_31_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_00_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_02_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_03_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_10_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_12_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_13_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_15_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_18_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_31_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_flavor_table_attr == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_flavor_table_en_attr == SERDES_IP_RX_FLEX_L2_CFG_FLX_FLAVOR_TABLE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_force_frame_lock_attr == SERDES_IP_RX_FLEX_L2_CFG_FLX_FORCE_FRAME_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_freeze_in_state_attr == SERDES_IP_RX_FLEX_L2_CFG_FLX_FREEZE_IN_STATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_01_attr == 32'd65537
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_02_attr == 32'd2147516416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_03_attr == 32'd2181169152
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_04_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_05_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_06_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_07_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_08_attr == 32'd16384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_09_attr == 32'd131072
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_10_attr == 32'd2416050176
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_11_attr == 32'd33554432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_12_attr == 32'd1075838976
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_13_attr == 32'd301989888
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_14_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_15_attr == 32'd2181169152
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_16_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_17_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_18_attr == 32'd302006272
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_19_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_20_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_21_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_22_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_23_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_24_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_25_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_26_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_27_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_28_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_29_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_30_attr == 32'd33587200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_31_attr == 32'd1107329024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_02_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_03_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_10_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_12_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_13_attr == 5'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_15_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_18_attr == 5'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_31_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_02_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_03_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_10_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_11_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_12_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_13_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_15_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_18_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_30_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_31_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_one_state_inc_pulse_attr == SERDES_IP_RX_FLEX_L2_CFG_FLX_ONE_STATE_INC_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_00_attr == 32'd1056783
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_01_attr == 32'd9510943
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_02_attr == 32'd9502735
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_03_attr == 32'd9437199
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_04_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_05_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_06_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_07_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_08_attr == 32'd14680079
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_09_attr == 32'd26017807
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_10_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_11_attr == 32'd9502735
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_12_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_13_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_14_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_15_attr == 32'd25493519
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_16_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_17_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_18_attr == 32'd14942223
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_19_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_20_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_21_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_22_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_23_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_24_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_25_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_26_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_27_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_28_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_29_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_30_attr == 32'd1376271
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_31_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_00_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_01_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_02_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_03_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_04_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_05_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_06_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_07_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_08_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_09_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_10_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_11_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_12_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_13_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_14_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_15_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_16_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_17_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_18_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_19_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_20_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_21_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_22_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_23_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_24_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_25_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_26_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_27_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_28_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_29_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_30_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_31_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_state_force_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_state_force_value_en_attr == SERDES_IP_RX_FLEX_L2_CFG_FLX_STATE_FORCE_VALUE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_flx_stop_tmr_in_handshake_attr == SERDES_IP_RX_FLEX_L2_CFG_FLX_STOP_TMR_IN_HANDSHAKE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_00_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_00_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_01_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_01_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_02_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_02_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_03_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_03_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_04_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_04_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_05_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_05_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_06_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_06_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_07_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_07_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_08_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_08_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_09_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_09_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_10_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_10_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_11_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_12_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_13_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_14_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_15_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_15_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_16_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_17_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_18_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_19_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_19_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_20_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_20_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_21_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_21_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_22_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_22_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_23_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_23_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_24_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_24_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_25_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_25_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_26_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_26_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_27_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_27_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_28_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_28_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_29_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_29_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_30_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_30_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_31_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_31_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_02_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_03_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_10_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_12_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_13_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_15_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_18_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_31_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_00_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_00_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_01_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_01_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_02_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_02_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_03_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_03_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_04_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_04_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_05_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_05_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_06_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_06_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_07_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_07_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_08_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_08_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_09_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_09_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_10_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_11_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_12_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_13_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_14_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_15_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_16_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_17_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_18_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_19_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_19_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_20_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_20_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_21_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_21_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_22_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_22_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_23_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_23_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_24_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_24_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_25_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_25_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_26_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_26_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_27_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_27_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_28_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_28_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_29_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_29_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_30_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_30_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_31_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_31_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_00_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_02_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_03_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_10_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_12_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_13_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_15_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_18_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_31_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_flavor_table_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_flavor_table_en_attr == SERDES_IP_RX_FLEX_L3_CFG_FLX_FLAVOR_TABLE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_force_frame_lock_attr == SERDES_IP_RX_FLEX_L3_CFG_FLX_FORCE_FRAME_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_freeze_in_state_attr == SERDES_IP_RX_FLEX_L3_CFG_FLX_FREEZE_IN_STATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_01_attr == 32'd65536
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_02_attr == 32'd2181070848
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_03_attr == 32'd2147491840
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_04_attr == 32'd2147483649
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_05_attr == 32'd2147483649
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_06_attr == 32'd2147483649
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_07_attr == 32'd2181038081
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_08_attr == 32'd16384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_09_attr == 32'd131072
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_10_attr == 32'd2147614720
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_11_attr == 32'd33554432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_12_attr == 32'd1075838976
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_13_attr == 32'd268435456
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_14_attr == 32'd2147491840
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_15_attr == 32'd2147614720
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_16_attr == 32'd268435457
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_17_attr == 32'd301989889
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_18_attr == 32'd33570816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_19_attr == 32'd33554432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_20_attr == 32'd33554432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_21_attr == 32'd2181054464
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_22_attr == 32'd2147484672
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_23_attr == 32'd33587200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_24_attr == 32'd2147614720
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_25_attr == 32'd33554432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_26_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_27_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_28_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_29_attr == 32'd33587200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_30_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_31_attr == 32'd1107296256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_02_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_03_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_04_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_05_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_06_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_07_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_10_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_12_attr == 5'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_13_attr == 5'd29
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_14_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_15_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_16_attr == 5'd29
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_17_attr == 5'd29
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_18_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_21_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_22_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_24_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_31_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_01_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_02_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_03_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_07_attr == 5'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_10_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_11_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_12_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_13_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_15_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_17_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_18_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_19_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_20_attr == 5'd21
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_21_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_23_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_25_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_29_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_31_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_one_state_inc_pulse_attr == SERDES_IP_RX_FLEX_L3_CFG_FLX_ONE_STATE_INC_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_00_attr == 32'd1187855
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_01_attr == 32'd9576479
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_02_attr == 32'd9437199
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_03_attr == 32'd9437199
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_04_attr == 32'd9554175
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_05_attr == 32'd9554943
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_06_attr == 32'd9554943
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_07_attr == 32'd9554943
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_08_attr == 32'd14680079
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_09_attr == 32'd25952527
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_10_attr == 32'd8651023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_11_attr == 32'd9437215
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_12_attr == 32'd8651023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_13_attr == 32'd8651023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_14_attr == 32'd8651023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_15_attr == 32'd25428239
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_16_attr == 32'd8735743
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_17_attr == 32'd8735487
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_18_attr == 32'd14942223
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_19_attr == 32'd12845071
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_20_attr == 32'd8392719
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_21_attr == 32'd14684175
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_22_attr == 32'd9519167
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_23_attr == 32'd9519119
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_24_attr == 32'd12582927
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_25_attr == 32'd12582927
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_26_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_27_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_28_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_29_attr == 32'd5505295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_30_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_31_attr == 32'd4456719
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_00_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_01_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_02_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_03_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_04_attr == 32'd4210819071
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_05_attr == 32'd4210771012
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_06_attr == 32'd2063305591
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_07_attr == 32'd2054911863
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_08_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_09_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_10_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_11_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_12_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_13_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_14_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_15_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_16_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_17_attr == 32'd1784366148
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_18_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_19_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_20_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_21_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_22_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_23_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_24_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_25_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_26_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_27_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_28_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_29_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_30_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_31_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_state_force_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_state_force_value_en_attr == SERDES_IP_RX_FLEX_L3_CFG_FLX_STATE_FORCE_VALUE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_flx_stop_tmr_in_handshake_attr == SERDES_IP_RX_FLEX_L3_CFG_FLX_STOP_TMR_IN_HANDSHAKE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_00_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_00_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_01_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_01_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_02_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_02_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_03_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_03_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_04_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_04_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_05_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_05_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_06_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_06_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_07_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_07_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_08_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_08_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_09_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_09_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_10_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_10_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_11_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_12_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_13_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_14_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_14_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_15_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_15_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_16_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_16_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_17_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_17_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_18_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_19_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_19_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_20_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_20_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_21_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_21_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_22_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_22_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_23_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_23_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_24_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_24_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_25_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_25_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_26_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_26_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_27_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_27_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_28_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_28_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_29_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_29_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_30_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_30_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_31_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_31_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_02_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_03_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_04_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_05_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_06_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_07_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_10_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_12_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_13_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_15_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_16_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_17_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_18_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_21_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_22_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_31_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_00_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_00_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_01_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_01_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_02_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_02_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_03_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_03_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_04_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_04_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_05_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_05_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_06_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_06_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_07_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_07_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_08_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_08_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_09_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_09_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_10_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_11_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_12_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_13_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_14_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_15_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_16_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_17_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_18_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_19_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_19_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_20_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_20_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_21_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_21_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_22_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_22_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_23_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_23_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_24_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_24_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_25_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_25_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_26_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_26_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_27_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_27_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_28_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_28_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_29_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_29_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_30_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_30_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_31_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_31_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_00_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_02_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_03_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_04_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_05_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_06_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_07_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_10_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_12_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_13_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_15_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_16_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_17_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_18_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_19_attr == 5'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_25_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_31_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_etrregsynthlcfastclk_ready2_attr == SERDES_IP_SYNTH_FAST_L0_CFG_ETRREGSYNTHLCFASTCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_etrregsynthlcfastclk_ready_attr == SERDES_IP_SYNTH_FAST_L0_CFG_ETRREGSYNTHLCFASTCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_FAST_L0_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_FAST_L0_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_FAST_L0_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_FAST_L0_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_FAST_L0_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_fastregpwrup_en_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFAST_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFAST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_pg_disable_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFAST_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_refdiv_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_refdiv_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_refdiv_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_refdiv_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_static_divrate_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFAST_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_used_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFAST_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastbias_icc400uadj_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldacbg_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldacfsm_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastclk_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastclkstat_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastclkstat_ready_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastdccrst_disable_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastearlylock_dig_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastearlylock_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastfsm_cken_ovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastfsm_cken_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_locovr_muxd0_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_locovr_muxd1_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_locovr_muxd2_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_locovr_muxd3_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_locovr_muxd4_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpllstatus_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastppm_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrecal_on_pd_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_en_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastspare1_attr == 32'd45078
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfaststartup_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfaststartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfasttimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfasttimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_etrregsynthlcfastclk_ready2_attr == SERDES_IP_SYNTH_FAST_L1_CFG_ETRREGSYNTHLCFASTCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_etrregsynthlcfastclk_ready_attr == SERDES_IP_SYNTH_FAST_L1_CFG_ETRREGSYNTHLCFASTCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_FAST_L1_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_FAST_L1_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_FAST_L1_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_FAST_L1_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_FAST_L1_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_fastregpwrup_en_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFAST_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFAST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_pg_disable_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFAST_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_refdiv_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_refdiv_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_refdiv_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_refdiv_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_static_divrate_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFAST_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_used_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFAST_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastbias_icc400uadj_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldacbg_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldacfsm_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastclk_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastclkstat_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastclkstat_ready_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastdccrst_disable_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastearlylock_dig_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastearlylock_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastfsm_cken_ovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastfsm_cken_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_locovr_muxd0_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_locovr_muxd1_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_locovr_muxd2_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_locovr_muxd3_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_locovr_muxd4_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpllstatus_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastppm_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrecal_on_pd_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_en_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastspare1_attr == 32'd45078
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfaststartup_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfaststartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfasttimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfasttimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_etrregsynthlcfastclk_ready2_attr == SERDES_IP_SYNTH_FAST_L2_CFG_ETRREGSYNTHLCFASTCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_etrregsynthlcfastclk_ready_attr == SERDES_IP_SYNTH_FAST_L2_CFG_ETRREGSYNTHLCFASTCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_FAST_L2_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_FAST_L2_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_FAST_L2_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_FAST_L2_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_FAST_L2_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_fastregpwrup_en_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFAST_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFAST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_pg_disable_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFAST_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_refdiv_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_refdiv_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_refdiv_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_refdiv_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_static_divrate_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFAST_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_used_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFAST_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastbias_icc400uadj_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldacbg_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldacfsm_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastclk_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastclkstat_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastclkstat_ready_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastdccrst_disable_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastearlylock_dig_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastearlylock_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastfsm_cken_ovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastfsm_cken_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_locovr_muxd0_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_locovr_muxd1_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_locovr_muxd2_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_locovr_muxd3_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_locovr_muxd4_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpllstatus_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastppm_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrecal_on_pd_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_en_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastspare1_attr == 32'd45078
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfaststartup_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfaststartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfasttimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfasttimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_etrregsynthlcfastclk_ready2_attr == SERDES_IP_SYNTH_FAST_L3_CFG_ETRREGSYNTHLCFASTCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_etrregsynthlcfastclk_ready_attr == SERDES_IP_SYNTH_FAST_L3_CFG_ETRREGSYNTHLCFASTCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_FAST_L3_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_FAST_L3_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_FAST_L3_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_FAST_L3_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_FAST_L3_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_fastregpwrup_en_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFAST_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFAST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_pg_disable_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFAST_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_refdiv_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_refdiv_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_refdiv_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_refdiv_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_static_divrate_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFAST_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_used_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFAST_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastbias_icc400uadj_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldacbg_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldacfsm_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastclk_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastclkstat_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastclkstat_ready_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastdccrst_disable_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastearlylock_dig_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastearlylock_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastfsm_cken_ovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastfsm_cken_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_locovr_muxd0_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_locovr_muxd1_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_locovr_muxd2_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_locovr_muxd3_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_locovr_muxd4_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpllstatus_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastppm_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrecal_on_pd_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_en_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastspare1_attr == 32'd45078
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfaststartup_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfaststartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfasttimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfasttimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_etrregsynthlcmedclk_ready2_attr == SERDES_IP_SYNTH_MED_L0_CFG_ETRREGSYNTHLCMEDCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_etrregsynthlcmedclk_ready_attr == SERDES_IP_SYNTH_MED_L0_CFG_ETRREGSYNTHLCMEDCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_MED_L0_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_MED_L0_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_MED_L0_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_MED_L0_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_MED_L0_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_fastregpwrup_en_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_pg_disable_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_refdiv_muxd0_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_refdiv_muxd1_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_refdiv_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_refdiv_muxd3_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_refdiv_muxd4_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_static_divrate_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_txbitclkselect_muxd0_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_txbitclkselect_muxd1_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_txbitclkselect_muxd2_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_txbitclkselect_muxd3_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_txbitclkselect_muxd4_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_used_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_USED_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedbias_icc400uadj_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldacbg_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldacfsm_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedclk_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedclkstat_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedclkstat_ready_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmeddccrst_disable_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedearlylock_dig_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedearlylock_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedfsm_cken_ovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedfsm_cken_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_locovr_muxd0_attr == 7'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_locovr_muxd1_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_locovr_muxd2_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_locovr_muxd3_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_locovr_muxd4_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpllstatus_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedppm_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrecal_on_pd_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_en_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedstartup_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedstartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedtimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedtimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_etrregsynthlcmedclk_ready2_attr == SERDES_IP_SYNTH_MED_L1_CFG_ETRREGSYNTHLCMEDCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_etrregsynthlcmedclk_ready_attr == SERDES_IP_SYNTH_MED_L1_CFG_ETRREGSYNTHLCMEDCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_MED_L1_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_MED_L1_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_MED_L1_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_MED_L1_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_MED_L1_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_fastregpwrup_en_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_pg_disable_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_refdiv_muxd1_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_refdiv_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_refdiv_muxd3_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_refdiv_muxd4_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_static_divrate_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_txbitclkselect_muxd0_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_txbitclkselect_muxd1_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_txbitclkselect_muxd2_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_txbitclkselect_muxd3_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_txbitclkselect_muxd4_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_used_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedbias_icc400uadj_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldacbg_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldacfsm_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedclk_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedclkstat_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedclkstat_ready_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmeddccrst_disable_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedearlylock_dig_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedearlylock_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedfsm_cken_ovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedfsm_cken_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_locovr_muxd0_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_locovr_muxd1_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_locovr_muxd2_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_locovr_muxd3_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_locovr_muxd4_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpllstatus_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedppm_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrecal_on_pd_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_en_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_entry7_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedstartup_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedstartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedtimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedtimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_etrregsynthlcmedclk_ready2_attr == SERDES_IP_SYNTH_MED_L2_CFG_ETRREGSYNTHLCMEDCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_etrregsynthlcmedclk_ready_attr == SERDES_IP_SYNTH_MED_L2_CFG_ETRREGSYNTHLCMEDCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_MED_L2_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_MED_L2_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_MED_L2_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_MED_L2_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_MED_L2_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_fastregpwrup_en_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_pg_disable_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_refdiv_muxd0_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_refdiv_muxd1_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_refdiv_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_refdiv_muxd3_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_refdiv_muxd4_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_static_divrate_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_txbitclkselect_muxd0_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_txbitclkselect_muxd1_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_txbitclkselect_muxd2_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_txbitclkselect_muxd3_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_txbitclkselect_muxd4_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_used_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_USED_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedbias_icc400uadj_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldacbg_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldacfsm_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedclk_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedclkstat_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedclkstat_ready_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmeddccrst_disable_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedearlylock_dig_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedearlylock_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedfsm_cken_ovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedfsm_cken_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_locovr_muxd0_attr == 7'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_locovr_muxd1_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_locovr_muxd2_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_locovr_muxd3_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_locovr_muxd4_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpllstatus_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedppm_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrecal_on_pd_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_en_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedstartup_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedstartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedtimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedtimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_etrregsynthlcmedclk_ready2_attr == SERDES_IP_SYNTH_MED_L3_CFG_ETRREGSYNTHLCMEDCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_etrregsynthlcmedclk_ready_attr == SERDES_IP_SYNTH_MED_L3_CFG_ETRREGSYNTHLCMEDCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_MED_L3_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_MED_L3_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_MED_L3_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_MED_L3_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_MED_L3_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_fastregpwrup_en_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_pg_disable_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_refdiv_muxd0_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_refdiv_muxd1_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_refdiv_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_refdiv_muxd3_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_refdiv_muxd4_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_static_divrate_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_txbitclkselect_muxd0_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_txbitclkselect_muxd1_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_txbitclkselect_muxd2_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_txbitclkselect_muxd3_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_txbitclkselect_muxd4_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_used_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_USED_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedbias_icc400uadj_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldacbg_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldacfsm_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedclk_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedclkstat_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedclkstat_ready_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmeddccrst_disable_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedearlylock_dig_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedearlylock_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedfsm_cken_ovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedfsm_cken_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_locovr_muxd0_attr == 7'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_locovr_muxd1_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_locovr_muxd2_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_locovr_muxd3_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_locovr_muxd4_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpllstatus_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedppm_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrecal_on_pd_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_en_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedstartup_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedstartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedtimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedtimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_etrregsynthlcslowclk_ready2_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_ETRREGSYNTHLCSLOWCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_etrregsynthlcslowclk_ready_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_ETRREGSYNTHLCSLOWCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_fastregpwrup_en_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_pg_disable_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_refdiv_muxd0_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_refdiv_muxd1_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_refdiv_muxd2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_refdiv_muxd3_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_refdiv_muxd4_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_static_divrate_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_txbitclkselect_muxd0_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_txbitclkselect_muxd1_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_txbitclkselect_muxd2_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_txbitclkselect_muxd3_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_txbitclkselect_muxd4_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_used_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowbias_icc400uadj_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldacbg_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldacfsm_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowclk_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowclkstat_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowclkstat_ready_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowdccrst_disable_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowearlylock_dig_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowearlylock_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowfsm_cken_ovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowfsm_cken_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_locovr_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_locovr_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_locovr_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_locovr_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_locovr_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpllstatus_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowppm_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_clk_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrecal_on_pd_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_en_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_entry7_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowstartup_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowstartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowtimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowtimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_etrregsynthlcslowclk_ready2_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_ETRREGSYNTHLCSLOWCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_etrregsynthlcslowclk_ready_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_ETRREGSYNTHLCSLOWCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_fastregpwrup_en_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_pg_disable_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_refdiv_muxd0_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_refdiv_muxd1_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_refdiv_muxd2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_refdiv_muxd3_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_refdiv_muxd4_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_static_divrate_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_txbitclkselect_muxd0_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_txbitclkselect_muxd1_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_txbitclkselect_muxd2_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_txbitclkselect_muxd3_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_txbitclkselect_muxd4_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_used_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowbias_icc400uadj_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldacbg_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldacfsm_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowclk_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowclkstat_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowclkstat_ready_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowdccrst_disable_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowearlylock_dig_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowearlylock_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowfsm_cken_ovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowfsm_cken_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_locovr_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_locovr_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_locovr_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_locovr_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_locovr_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpllstatus_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowppm_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_clk_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrecal_on_pd_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_en_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_entry7_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowstartup_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowstartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowtimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowtimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_etrregsynthlcslowclk_ready2_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_ETRREGSYNTHLCSLOWCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_etrregsynthlcslowclk_ready_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_ETRREGSYNTHLCSLOWCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_fastregpwrup_en_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_pg_disable_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_refdiv_muxd0_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_refdiv_muxd1_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_refdiv_muxd2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_refdiv_muxd3_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_refdiv_muxd4_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_static_divrate_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_txbitclkselect_muxd0_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_txbitclkselect_muxd1_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_txbitclkselect_muxd2_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_txbitclkselect_muxd3_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_txbitclkselect_muxd4_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_used_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowbias_icc400uadj_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldacbg_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldacfsm_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowclk_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowclkstat_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowclkstat_ready_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowdccrst_disable_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowearlylock_dig_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowearlylock_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowfsm_cken_ovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowfsm_cken_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_locovr_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_locovr_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_locovr_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_locovr_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_locovr_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpllstatus_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowppm_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_clk_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrecal_on_pd_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_en_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_entry7_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowstartup_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowstartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowtimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowtimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_etrregsynthlcslowclk_ready2_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_ETRREGSYNTHLCSLOWCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_etrregsynthlcslowclk_ready_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_ETRREGSYNTHLCSLOWCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_fastregpwrup_en_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_pg_disable_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_refdiv_muxd0_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_refdiv_muxd1_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_refdiv_muxd2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_refdiv_muxd3_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_refdiv_muxd4_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_static_divrate_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_txbitclkselect_muxd0_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_txbitclkselect_muxd1_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_txbitclkselect_muxd2_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_txbitclkselect_muxd3_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_txbitclkselect_muxd4_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_used_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowbias_icc400uadj_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldacbg_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldacfsm_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowclk_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowclkstat_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowclkstat_ready_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowdccrst_disable_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowearlylock_dig_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowearlylock_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowfsm_cken_ovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowfsm_cken_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_locovr_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_locovr_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_locovr_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_locovr_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_locovr_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpllstatus_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowppm_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_clk_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrecal_on_pd_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_en_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_entry7_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowstartup_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowstartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowtimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowtimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_an_idle_stiky_clear_attr == SERDES_SHIM_AN_L0_CFG_AN_IDLE_STIKY_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_an_reserv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_debug_fw_reg1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_debug_fw_reg2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_debug_fw_reg3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_debug_fw_reg4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_dig_cdr_disable_attr == SERDES_SHIM_AN_L0_CFG_DIG_CDR_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_direct_control_bus0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_direct_control_bus1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_direct_control_bus2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_direct_control_bus3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_direct_control_bus4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_direct_control_bus5_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_direct_control_bus6_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_direct_control_bus_en_attr == SERDES_SHIM_AN_L0_CFG_DIRECT_CONTROL_BUS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_edge_too_long_disable_attr == SERDES_SHIM_AN_L0_CFG_EDGE_TOO_LONG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_edge_too_short_disable_attr == SERDES_SHIM_AN_L0_CFG_EDGE_TOO_SHORT_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_page_max_timer_disable_attr == SERDES_SHIM_AN_L0_CFG_PAGE_MAX_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_page_min_timer_disable_attr == SERDES_SHIM_AN_L0_CFG_PAGE_MIN_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_pcs_lock_attr == SERDES_SHIM_AN_L0_CFG_PCS_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_pcs_tx_bypass_sample_attr == SERDES_SHIM_AN_L0_CFG_PCS_TX_BYPASS_SAMPLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_rx_enable_m_attr == SERDES_SHIM_AN_L0_CFG_RX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_rx_lcw_re_attr == SERDES_SHIM_AN_L0_CFG_RX_LCW_RE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_rx_pma_en_attr == SERDES_SHIM_AN_L0_CFG_RX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_rx_unencoder_ctrl_en_attr == SERDES_SHIM_AN_L0_CFG_RX_UNENCODER_CTRL_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_rx_unencoder_gray_en_attr == SERDES_SHIM_AN_L0_CFG_RX_UNENCODER_GRAY_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_rx_unencoder_pam_bitorder_swz_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_rx_unencoder_pam_en_attr == SERDES_SHIM_AN_L0_CFG_RX_UNENCODER_PAM_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_rx_unencoder_polarity_swz_attr == SERDES_SHIM_AN_L0_CFG_RX_UNENCODER_POLARITY_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_rx_unencoder_precode_en_attr == SERDES_SHIM_AN_L0_CFG_RX_UNENCODER_PRECODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_rx_unencoder_width_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_serdes_irq_bus_sel_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_serdes_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_serdes_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_serdes_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_transmit_mode_scan_mode_dbg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_tx_complete_ack_attr == SERDES_SHIM_AN_L0_CFG_TX_COMPLETE_ACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_tx_enable_m_attr == SERDES_SHIM_AN_L0_CFG_TX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_tx_lcw_high_attr == 27'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_tx_lcw_low_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_tx_lcw_reserv_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_tx_lcw_we_attr == SERDES_SHIM_AN_L0_CFG_TX_LCW_WE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l0_cfg_tx_pma_en_attr == SERDES_SHIM_AN_L0_CFG_TX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_an_idle_stiky_clear_attr == SERDES_SHIM_AN_L1_CFG_AN_IDLE_STIKY_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_an_reserv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_debug_fw_reg1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_debug_fw_reg2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_debug_fw_reg3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_debug_fw_reg4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_dig_cdr_disable_attr == SERDES_SHIM_AN_L1_CFG_DIG_CDR_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_direct_control_bus0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_direct_control_bus1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_direct_control_bus2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_direct_control_bus3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_direct_control_bus4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_direct_control_bus5_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_direct_control_bus6_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_direct_control_bus_en_attr == SERDES_SHIM_AN_L1_CFG_DIRECT_CONTROL_BUS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_edge_too_long_disable_attr == SERDES_SHIM_AN_L1_CFG_EDGE_TOO_LONG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_edge_too_short_disable_attr == SERDES_SHIM_AN_L1_CFG_EDGE_TOO_SHORT_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_page_max_timer_disable_attr == SERDES_SHIM_AN_L1_CFG_PAGE_MAX_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_page_min_timer_disable_attr == SERDES_SHIM_AN_L1_CFG_PAGE_MIN_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_pcs_lock_attr == SERDES_SHIM_AN_L1_CFG_PCS_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_pcs_tx_bypass_sample_attr == SERDES_SHIM_AN_L1_CFG_PCS_TX_BYPASS_SAMPLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_rx_enable_m_attr == SERDES_SHIM_AN_L1_CFG_RX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_rx_lcw_re_attr == SERDES_SHIM_AN_L1_CFG_RX_LCW_RE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_rx_pma_en_attr == SERDES_SHIM_AN_L1_CFG_RX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_rx_unencoder_ctrl_en_attr == SERDES_SHIM_AN_L1_CFG_RX_UNENCODER_CTRL_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_rx_unencoder_gray_en_attr == SERDES_SHIM_AN_L1_CFG_RX_UNENCODER_GRAY_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_rx_unencoder_pam_bitorder_swz_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_rx_unencoder_pam_en_attr == SERDES_SHIM_AN_L1_CFG_RX_UNENCODER_PAM_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_rx_unencoder_polarity_swz_attr == SERDES_SHIM_AN_L1_CFG_RX_UNENCODER_POLARITY_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_rx_unencoder_precode_en_attr == SERDES_SHIM_AN_L1_CFG_RX_UNENCODER_PRECODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_rx_unencoder_width_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_serdes_irq_bus_sel_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_serdes_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_serdes_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_serdes_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_transmit_mode_scan_mode_dbg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_tx_complete_ack_attr == SERDES_SHIM_AN_L1_CFG_TX_COMPLETE_ACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_tx_enable_m_attr == SERDES_SHIM_AN_L1_CFG_TX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_tx_lcw_high_attr == 27'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_tx_lcw_low_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_tx_lcw_reserv_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_tx_lcw_we_attr == SERDES_SHIM_AN_L1_CFG_TX_LCW_WE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l1_cfg_tx_pma_en_attr == SERDES_SHIM_AN_L1_CFG_TX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_an_idle_stiky_clear_attr == SERDES_SHIM_AN_L2_CFG_AN_IDLE_STIKY_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_an_reserv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_debug_fw_reg1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_debug_fw_reg2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_debug_fw_reg3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_debug_fw_reg4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_dig_cdr_disable_attr == SERDES_SHIM_AN_L2_CFG_DIG_CDR_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_direct_control_bus0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_direct_control_bus1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_direct_control_bus2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_direct_control_bus3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_direct_control_bus4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_direct_control_bus5_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_direct_control_bus6_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_direct_control_bus_en_attr == SERDES_SHIM_AN_L2_CFG_DIRECT_CONTROL_BUS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_edge_too_long_disable_attr == SERDES_SHIM_AN_L2_CFG_EDGE_TOO_LONG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_edge_too_short_disable_attr == SERDES_SHIM_AN_L2_CFG_EDGE_TOO_SHORT_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_page_max_timer_disable_attr == SERDES_SHIM_AN_L2_CFG_PAGE_MAX_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_page_min_timer_disable_attr == SERDES_SHIM_AN_L2_CFG_PAGE_MIN_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_pcs_lock_attr == SERDES_SHIM_AN_L2_CFG_PCS_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_pcs_tx_bypass_sample_attr == SERDES_SHIM_AN_L2_CFG_PCS_TX_BYPASS_SAMPLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_rx_enable_m_attr == SERDES_SHIM_AN_L2_CFG_RX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_rx_lcw_re_attr == SERDES_SHIM_AN_L2_CFG_RX_LCW_RE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_rx_pma_en_attr == SERDES_SHIM_AN_L2_CFG_RX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_rx_unencoder_ctrl_en_attr == SERDES_SHIM_AN_L2_CFG_RX_UNENCODER_CTRL_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_rx_unencoder_gray_en_attr == SERDES_SHIM_AN_L2_CFG_RX_UNENCODER_GRAY_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_rx_unencoder_pam_bitorder_swz_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_rx_unencoder_pam_en_attr == SERDES_SHIM_AN_L2_CFG_RX_UNENCODER_PAM_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_rx_unencoder_polarity_swz_attr == SERDES_SHIM_AN_L2_CFG_RX_UNENCODER_POLARITY_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_rx_unencoder_precode_en_attr == SERDES_SHIM_AN_L2_CFG_RX_UNENCODER_PRECODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_rx_unencoder_width_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_serdes_irq_bus_sel_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_serdes_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_serdes_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_serdes_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_transmit_mode_scan_mode_dbg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_tx_complete_ack_attr == SERDES_SHIM_AN_L2_CFG_TX_COMPLETE_ACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_tx_enable_m_attr == SERDES_SHIM_AN_L2_CFG_TX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_tx_lcw_high_attr == 27'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_tx_lcw_low_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_tx_lcw_reserv_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_tx_lcw_we_attr == SERDES_SHIM_AN_L2_CFG_TX_LCW_WE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l2_cfg_tx_pma_en_attr == SERDES_SHIM_AN_L2_CFG_TX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_an_idle_stiky_clear_attr == SERDES_SHIM_AN_L3_CFG_AN_IDLE_STIKY_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_an_reserv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_debug_fw_reg1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_debug_fw_reg2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_debug_fw_reg3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_debug_fw_reg4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_dig_cdr_disable_attr == SERDES_SHIM_AN_L3_CFG_DIG_CDR_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_direct_control_bus0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_direct_control_bus1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_direct_control_bus2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_direct_control_bus3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_direct_control_bus4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_direct_control_bus5_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_direct_control_bus6_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_direct_control_bus_en_attr == SERDES_SHIM_AN_L3_CFG_DIRECT_CONTROL_BUS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_edge_too_long_disable_attr == SERDES_SHIM_AN_L3_CFG_EDGE_TOO_LONG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_edge_too_short_disable_attr == SERDES_SHIM_AN_L3_CFG_EDGE_TOO_SHORT_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_page_max_timer_disable_attr == SERDES_SHIM_AN_L3_CFG_PAGE_MAX_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_page_min_timer_disable_attr == SERDES_SHIM_AN_L3_CFG_PAGE_MIN_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_pcs_lock_attr == SERDES_SHIM_AN_L3_CFG_PCS_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_pcs_tx_bypass_sample_attr == SERDES_SHIM_AN_L3_CFG_PCS_TX_BYPASS_SAMPLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_rx_enable_m_attr == SERDES_SHIM_AN_L3_CFG_RX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_rx_lcw_re_attr == SERDES_SHIM_AN_L3_CFG_RX_LCW_RE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_rx_pma_en_attr == SERDES_SHIM_AN_L3_CFG_RX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_rx_unencoder_ctrl_en_attr == SERDES_SHIM_AN_L3_CFG_RX_UNENCODER_CTRL_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_rx_unencoder_gray_en_attr == SERDES_SHIM_AN_L3_CFG_RX_UNENCODER_GRAY_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_rx_unencoder_pam_bitorder_swz_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_rx_unencoder_pam_en_attr == SERDES_SHIM_AN_L3_CFG_RX_UNENCODER_PAM_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_rx_unencoder_polarity_swz_attr == SERDES_SHIM_AN_L3_CFG_RX_UNENCODER_POLARITY_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_rx_unencoder_precode_en_attr == SERDES_SHIM_AN_L3_CFG_RX_UNENCODER_PRECODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_rx_unencoder_width_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_serdes_irq_bus_sel_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_serdes_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_serdes_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_serdes_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_transmit_mode_scan_mode_dbg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_tx_complete_ack_attr == SERDES_SHIM_AN_L3_CFG_TX_COMPLETE_ACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_tx_enable_m_attr == SERDES_SHIM_AN_L3_CFG_TX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_tx_lcw_high_attr == 27'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_tx_lcw_low_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_tx_lcw_reserv_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_tx_lcw_we_attr == SERDES_SHIM_AN_L3_CFG_TX_LCW_WE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_an_l3_cfg_tx_pma_en_attr == SERDES_SHIM_AN_L3_CFG_TX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_apb_dsp_clk_sel_attr == SERDES_SHIM_CAR_L0_CFG_APB_DSP_CLK_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_apb_dsp_divn_en_attr == SERDES_SHIM_CAR_L0_CFG_APB_DSP_DIVN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_apb_dsp_divn_value_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_apb_dsp_pclken_attr == SERDES_SHIM_CAR_L0_CFG_APB_DSP_PCLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_apb_dsp_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_APB_DSP_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_dp_rx_80b_swz_attr == SERDES_SHIM_CAR_L0_CFG_DP_RX_80B_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_dp_tx_80b_swz_attr == SERDES_SHIM_CAR_L0_CFG_DP_TX_80B_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_eee_alert_force_en_attr == SERDES_SHIM_CAR_L0_CFG_EEE_ALERT_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_eee_alert_force_val_attr == SERDES_SHIM_CAR_L0_CFG_EEE_ALERT_FORCE_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_flux_srds_tx_divn_clken_attr == SERDES_SHIM_CAR_L0_CFG_FLUX_SRDS_TX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_iflux_tx_or_apb_clk_for_ux_ctrl_clk_sel_attr == SERDES_SHIM_CAR_L0_CFG_IFLUX_TX_OR_APB_CLK_FOR_UX_CTRL_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_oflux_srds_rx_clken_attr == SERDES_SHIM_CAR_L0_CFG_OFLUX_SRDS_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_oflux_srds_rx_divn_clken_attr == SERDES_SHIM_CAR_L0_CFG_OFLUX_SRDS_RX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_oflux_srds_tx_clken_attr == SERDES_SHIM_CAR_L0_CFG_OFLUX_SRDS_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_pcs_ick_ctrl_cmn_clk_sel_attr == SERDES_SHIM_CAR_L0_CFG_PCS_ICK_CTRL_CMN_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_pcs_ick_ctrl_l0_clk_sel_attr == SERDES_SHIM_CAR_L0_CFG_PCS_ICK_CTRL_L0_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_rxovrcdrlock2data_attr == SERDES_SHIM_CAR_L0_CFG_RXOVRCDRLOCK2DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_rxovrcdrlock2data_src_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_rxovrcdrlock2dataen_attr == SERDES_SHIM_CAR_L0_CFG_RXOVRCDRLOCK2DATAEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_rxovrcdrlock2dataen_src_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_rxpstate_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_rxpstate_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_srds_an_rx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_AN_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_srds_an_rx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_AN_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_srds_an_tx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_AN_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_srds_an_tx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_AN_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_srds_ctrl_rx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_CTRL_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_srds_ctrl_rx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_CTRL_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_srds_ctrl_tx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_CTRL_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_srds_ctrl_tx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_CTRL_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_srds_dfx_rx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_DFX_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_srds_dfx_rx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_DFX_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_srds_dfx_tx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_DFX_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_srds_dfx_tx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_DFX_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_srds_dsp_rx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_DSP_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_srds_dsp_rx_isi_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_DSP_RX_ISI_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_srds_dsp_rx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_DSP_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_srds_eee_rx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_EEE_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_srds_eee_rx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_EEE_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_srds_eee_tx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_EEE_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_srds_eee_tx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_EEE_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_srds_pcs_tx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_PCS_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_srds_pcs_tx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_PCS_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_srds_trn_rx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_TRN_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_srds_trn_rx_divn_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_TRN_RX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_srds_trn_rx_divn_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_TRN_RX_DIVN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_srds_trn_rx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_TRN_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_srds_trn_tx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_TRN_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_srds_trn_tx_divn_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_TRN_TX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_srds_trn_tx_divn_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_TRN_TX_DIVN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_srds_trn_tx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_TRN_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_srds_ux_ctrl_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_UX_CTRL_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_srds_ux_ctrl_cmn_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_UX_CTRL_CMN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_srds_ux_ctrl_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_UX_CTRL_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_srds_ux_tx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_UX_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_srds_ux_tx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_UX_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_timer_en_attr == SERDES_SHIM_CAR_L0_CFG_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_timer_value_attr == 8'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_transmit_mode_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_tx_postdiv_clk_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_txelecidle_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_txelecidle_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_txpstate_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l0_cfg_txpstate_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_apb_dsp_clk_sel_attr == SERDES_SHIM_CAR_L1_CFG_APB_DSP_CLK_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_apb_dsp_divn_en_attr == SERDES_SHIM_CAR_L1_CFG_APB_DSP_DIVN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_apb_dsp_divn_value_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_apb_dsp_pclken_attr == SERDES_SHIM_CAR_L1_CFG_APB_DSP_PCLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_apb_dsp_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_APB_DSP_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_dp_rx_80b_swz_attr == SERDES_SHIM_CAR_L1_CFG_DP_RX_80B_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_dp_tx_80b_swz_attr == SERDES_SHIM_CAR_L1_CFG_DP_TX_80B_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_eee_alert_force_en_attr == SERDES_SHIM_CAR_L1_CFG_EEE_ALERT_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_eee_alert_force_val_attr == SERDES_SHIM_CAR_L1_CFG_EEE_ALERT_FORCE_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_flux_srds_tx_divn_clken_attr == SERDES_SHIM_CAR_L1_CFG_FLUX_SRDS_TX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_iflux_tx_or_apb_clk_for_ux_ctrl_clk_sel_attr == SERDES_SHIM_CAR_L1_CFG_IFLUX_TX_OR_APB_CLK_FOR_UX_CTRL_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_oflux_srds_rx_clken_attr == SERDES_SHIM_CAR_L1_CFG_OFLUX_SRDS_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_oflux_srds_rx_divn_clken_attr == SERDES_SHIM_CAR_L1_CFG_OFLUX_SRDS_RX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_oflux_srds_tx_clken_attr == SERDES_SHIM_CAR_L1_CFG_OFLUX_SRDS_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_pcs_ick_ctrl_cmn_clk_sel_attr == SERDES_SHIM_CAR_L1_CFG_PCS_ICK_CTRL_CMN_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_pcs_ick_ctrl_l0_clk_sel_attr == SERDES_SHIM_CAR_L1_CFG_PCS_ICK_CTRL_L0_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_rxovrcdrlock2data_attr == SERDES_SHIM_CAR_L1_CFG_RXOVRCDRLOCK2DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_rxovrcdrlock2data_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_rxovrcdrlock2dataen_attr == SERDES_SHIM_CAR_L1_CFG_RXOVRCDRLOCK2DATAEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_rxovrcdrlock2dataen_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_rxpstate_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_rxpstate_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_srds_an_rx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_AN_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_srds_an_rx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_AN_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_srds_an_tx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_AN_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_srds_an_tx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_AN_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_srds_ctrl_rx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_CTRL_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_srds_ctrl_rx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_CTRL_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_srds_ctrl_tx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_CTRL_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_srds_ctrl_tx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_CTRL_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_srds_dfx_rx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_DFX_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_srds_dfx_rx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_DFX_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_srds_dfx_tx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_DFX_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_srds_dfx_tx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_DFX_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_srds_dsp_rx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_DSP_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_srds_dsp_rx_isi_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_DSP_RX_ISI_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_srds_dsp_rx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_DSP_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_srds_eee_rx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_EEE_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_srds_eee_rx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_EEE_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_srds_eee_tx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_EEE_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_srds_eee_tx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_EEE_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_srds_pcs_tx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_PCS_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_srds_pcs_tx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_PCS_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_srds_trn_rx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_TRN_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_srds_trn_rx_divn_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_TRN_RX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_srds_trn_rx_divn_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_TRN_RX_DIVN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_srds_trn_rx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_TRN_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_srds_trn_tx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_TRN_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_srds_trn_tx_divn_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_TRN_TX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_srds_trn_tx_divn_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_TRN_TX_DIVN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_srds_trn_tx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_TRN_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_srds_ux_ctrl_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_UX_CTRL_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_srds_ux_ctrl_cmn_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_UX_CTRL_CMN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_srds_ux_ctrl_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_UX_CTRL_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_srds_ux_tx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_UX_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_srds_ux_tx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_UX_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_timer_en_attr == SERDES_SHIM_CAR_L1_CFG_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_timer_value_attr == 8'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_transmit_mode_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_tx_postdiv_clk_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_txelecidle_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_txelecidle_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_txpstate_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l1_cfg_txpstate_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_apb_dsp_clk_sel_attr == SERDES_SHIM_CAR_L2_CFG_APB_DSP_CLK_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_apb_dsp_divn_en_attr == SERDES_SHIM_CAR_L2_CFG_APB_DSP_DIVN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_apb_dsp_divn_value_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_apb_dsp_pclken_attr == SERDES_SHIM_CAR_L2_CFG_APB_DSP_PCLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_apb_dsp_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_APB_DSP_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_dp_rx_80b_swz_attr == SERDES_SHIM_CAR_L2_CFG_DP_RX_80B_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_dp_tx_80b_swz_attr == SERDES_SHIM_CAR_L2_CFG_DP_TX_80B_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_eee_alert_force_en_attr == SERDES_SHIM_CAR_L2_CFG_EEE_ALERT_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_eee_alert_force_val_attr == SERDES_SHIM_CAR_L2_CFG_EEE_ALERT_FORCE_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_flux_srds_tx_divn_clken_attr == SERDES_SHIM_CAR_L2_CFG_FLUX_SRDS_TX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_iflux_tx_or_apb_clk_for_ux_ctrl_clk_sel_attr == SERDES_SHIM_CAR_L2_CFG_IFLUX_TX_OR_APB_CLK_FOR_UX_CTRL_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_oflux_srds_rx_clken_attr == SERDES_SHIM_CAR_L2_CFG_OFLUX_SRDS_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_oflux_srds_rx_divn_clken_attr == SERDES_SHIM_CAR_L2_CFG_OFLUX_SRDS_RX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_oflux_srds_tx_clken_attr == SERDES_SHIM_CAR_L2_CFG_OFLUX_SRDS_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_pcs_ick_ctrl_cmn_clk_sel_attr == SERDES_SHIM_CAR_L2_CFG_PCS_ICK_CTRL_CMN_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_pcs_ick_ctrl_l0_clk_sel_attr == SERDES_SHIM_CAR_L2_CFG_PCS_ICK_CTRL_L0_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_rxovrcdrlock2data_attr == SERDES_SHIM_CAR_L2_CFG_RXOVRCDRLOCK2DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_rxovrcdrlock2data_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_rxovrcdrlock2dataen_attr == SERDES_SHIM_CAR_L2_CFG_RXOVRCDRLOCK2DATAEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_rxovrcdrlock2dataen_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_rxpstate_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_rxpstate_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_srds_an_rx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_AN_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_srds_an_rx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_AN_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_srds_an_tx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_AN_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_srds_an_tx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_AN_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_srds_ctrl_rx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_CTRL_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_srds_ctrl_rx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_CTRL_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_srds_ctrl_tx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_CTRL_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_srds_ctrl_tx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_CTRL_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_srds_dfx_rx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_DFX_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_srds_dfx_rx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_DFX_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_srds_dfx_tx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_DFX_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_srds_dfx_tx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_DFX_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_srds_dsp_rx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_DSP_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_srds_dsp_rx_isi_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_DSP_RX_ISI_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_srds_dsp_rx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_DSP_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_srds_eee_rx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_EEE_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_srds_eee_rx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_EEE_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_srds_eee_tx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_EEE_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_srds_eee_tx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_EEE_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_srds_pcs_tx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_PCS_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_srds_pcs_tx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_PCS_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_srds_trn_rx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_TRN_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_srds_trn_rx_divn_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_TRN_RX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_srds_trn_rx_divn_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_TRN_RX_DIVN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_srds_trn_rx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_TRN_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_srds_trn_tx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_TRN_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_srds_trn_tx_divn_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_TRN_TX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_srds_trn_tx_divn_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_TRN_TX_DIVN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_srds_trn_tx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_TRN_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_srds_ux_ctrl_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_UX_CTRL_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_srds_ux_ctrl_cmn_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_UX_CTRL_CMN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_srds_ux_ctrl_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_UX_CTRL_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_srds_ux_tx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_UX_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_srds_ux_tx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_UX_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_timer_en_attr == SERDES_SHIM_CAR_L2_CFG_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_timer_value_attr == 8'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_transmit_mode_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_tx_postdiv_clk_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_txelecidle_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_txelecidle_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_txpstate_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l2_cfg_txpstate_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_apb_dsp_clk_sel_attr == SERDES_SHIM_CAR_L3_CFG_APB_DSP_CLK_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_apb_dsp_divn_en_attr == SERDES_SHIM_CAR_L3_CFG_APB_DSP_DIVN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_apb_dsp_divn_value_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_apb_dsp_pclken_attr == SERDES_SHIM_CAR_L3_CFG_APB_DSP_PCLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_apb_dsp_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_APB_DSP_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_dp_rx_80b_swz_attr == SERDES_SHIM_CAR_L3_CFG_DP_RX_80B_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_dp_tx_80b_swz_attr == SERDES_SHIM_CAR_L3_CFG_DP_TX_80B_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_eee_alert_force_en_attr == SERDES_SHIM_CAR_L3_CFG_EEE_ALERT_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_eee_alert_force_val_attr == SERDES_SHIM_CAR_L3_CFG_EEE_ALERT_FORCE_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_flux_srds_tx_divn_clken_attr == SERDES_SHIM_CAR_L3_CFG_FLUX_SRDS_TX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_iflux_tx_or_apb_clk_for_ux_ctrl_clk_sel_attr == SERDES_SHIM_CAR_L3_CFG_IFLUX_TX_OR_APB_CLK_FOR_UX_CTRL_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_oflux_srds_rx_clken_attr == SERDES_SHIM_CAR_L3_CFG_OFLUX_SRDS_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_oflux_srds_rx_divn_clken_attr == SERDES_SHIM_CAR_L3_CFG_OFLUX_SRDS_RX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_oflux_srds_tx_clken_attr == SERDES_SHIM_CAR_L3_CFG_OFLUX_SRDS_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_pcs_ick_ctrl_cmn_clk_sel_attr == SERDES_SHIM_CAR_L3_CFG_PCS_ICK_CTRL_CMN_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_pcs_ick_ctrl_l0_clk_sel_attr == SERDES_SHIM_CAR_L3_CFG_PCS_ICK_CTRL_L0_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_rxovrcdrlock2data_attr == SERDES_SHIM_CAR_L3_CFG_RXOVRCDRLOCK2DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_rxovrcdrlock2data_src_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_rxovrcdrlock2dataen_attr == SERDES_SHIM_CAR_L3_CFG_RXOVRCDRLOCK2DATAEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_rxovrcdrlock2dataen_src_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_rxpstate_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_rxpstate_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_srds_an_rx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_AN_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_srds_an_rx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_AN_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_srds_an_tx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_AN_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_srds_an_tx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_AN_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_srds_ctrl_rx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_CTRL_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_srds_ctrl_rx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_CTRL_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_srds_ctrl_tx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_CTRL_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_srds_ctrl_tx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_CTRL_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_srds_dfx_rx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_DFX_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_srds_dfx_rx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_DFX_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_srds_dfx_tx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_DFX_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_srds_dfx_tx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_DFX_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_srds_dsp_rx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_DSP_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_srds_dsp_rx_isi_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_DSP_RX_ISI_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_srds_dsp_rx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_DSP_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_srds_eee_rx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_EEE_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_srds_eee_rx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_EEE_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_srds_eee_tx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_EEE_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_srds_eee_tx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_EEE_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_srds_pcs_tx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_PCS_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_srds_pcs_tx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_PCS_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_srds_trn_rx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_TRN_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_srds_trn_rx_divn_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_TRN_RX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_srds_trn_rx_divn_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_TRN_RX_DIVN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_srds_trn_rx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_TRN_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_srds_trn_tx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_TRN_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_srds_trn_tx_divn_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_TRN_TX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_srds_trn_tx_divn_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_TRN_TX_DIVN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_srds_trn_tx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_TRN_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_srds_ux_ctrl_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_UX_CTRL_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_srds_ux_ctrl_cmn_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_UX_CTRL_CMN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_srds_ux_ctrl_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_UX_CTRL_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_srds_ux_tx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_UX_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_srds_ux_tx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_UX_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_timer_en_attr == SERDES_SHIM_CAR_L3_CFG_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_timer_value_attr == 8'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_transmit_mode_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_tx_postdiv_clk_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_txelecidle_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_txelecidle_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_txpstate_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_car_l3_cfg_txpstate_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_cpu_atresetn_attr == SERDES_SHIM_CPU_PM_CFG_CPU_ATRESETN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_cpu_breakin_attr == SERDES_SHIM_CPU_PM_CFG_CPU_BREAKIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_cpu_breakoutack_attr == SERDES_SHIM_CPU_PM_CFG_CPU_BREAKOUTACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_cpu_crosstriggerin_attr == SERDES_SHIM_CPU_PM_CFG_CPU_CROSSTRIGGERIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_cpu_crosstriggeroutack_attr == SERDES_SHIM_CPU_PM_CFG_CPU_CROSSTRIGGEROUTACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_cpu_ocdhaltonreset_attr == SERDES_SHIM_CPU_PM_CFG_CPU_OCDHALTONRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_cpu_pdebugenable_attr == SERDES_SHIM_CPU_PM_CFG_CPU_PDEBUGENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_cpu_prid_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_cpu_statvectorsel_attr == SERDES_SHIM_CPU_PM_CFG_CPU_STATVECTORSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_cpu_tmodeclkgateoverride_reserved_attr == SERDES_SHIM_CPU_PM_CFG_CPU_TMODECLKGATEOVERRIDE_RESERVED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_dram_pwr_mgmt_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_dram0_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_DRAM0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_dram1_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_DRAM1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_dram2_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_DRAM2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_dram3_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_DRAM3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_fifo_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_FIFO_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_iram0_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_IRAM0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_iram1_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_IRAM1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_iram2_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_IRAM2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_iram3_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_IRAM3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_iram4_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_IRAM4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_iram5_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_IRAM5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_iram6_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_IRAM6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_iram7_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_IRAM7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_trace_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_TRACE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_dram0_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_DRAM0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_dram1_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_DRAM1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_dram2_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_DRAM2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_dram3_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_DRAM3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_fifo_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_FIFO_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_iram0_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_IRAM0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_iram1_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_IRAM1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_iram2_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_IRAM2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_iram3_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_IRAM3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_iram4_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_IRAM4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_iram5_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_IRAM5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_iram6_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_IRAM6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_iram7_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_IRAM7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_trace_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_TRACE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_dram0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_dram1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_dram2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_dram3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_iram0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_iram1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_iram2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_iram3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_iram4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_iram5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_iram6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_iram7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_trace_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_dram0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_dram1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_dram2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_dram3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_fifo_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_iram0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_iram1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_iram2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_iram3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_iram4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_iram5_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_iram6_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_iram7_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_trace_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_dram0_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_dram1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_dram2_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_dram3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_fifo_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_iram0_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_iram1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_iram2_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_iram3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_iram4_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_iram5_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_iram6_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_iram7_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_trace_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_dram0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_dram1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_dram2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_dram3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_fifo_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_iram0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_iram1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_iram2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_iram3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_iram4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_iram5_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_iram6_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_iram7_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_trace_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_dram0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_dram1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_dram2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_dram3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_fifo_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_iram0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_iram1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_iram2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_iram3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_iram4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_iram5_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_iram6_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_iram7_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_trace_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fw_status_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_fw_version_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_iramh_pwr_mgmt_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_iraml_pwr_mgmt_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_nmi_icu_mux_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_tb_reg0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_tb_reg1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_tb_reg2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_tb_reg3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_tb_reg4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_tie_queue_pwr_mgmt_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_cpu_pm_cfg_tram_pwr_mgmt_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_acc_clr_en_attr == SERDES_SHIM_DSP_L0_CFG_ACC_CLR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_acc_clr_rst_attr == SERDES_SHIM_DSP_L0_CFG_ACC_CLR_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_agc_acc_clr_attr == SERDES_SHIM_DSP_L0_CFG_AGC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_agc_clr_en_attr == SERDES_SHIM_DSP_L0_CFG_AGC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_agc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_agc_coarse_det_en_attr == SERDES_SHIM_DSP_L0_CFG_AGC_COARSE_DET_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_agc_coarse_det_pol_attr == SERDES_SHIM_DSP_L0_CFG_AGC_COARSE_DET_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_agc_d_sign_attr == SERDES_SHIM_DSP_L0_CFG_AGC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_agc_en_attr == SERDES_SHIM_DSP_L0_CFG_AGC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_agc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_agc_event_sign_attr == SERDES_SHIM_DSP_L0_CFG_AGC_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_agc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_agc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_agc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_agc_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_bb_stable_attr == SERDES_SHIM_DSP_L0_CFG_BB_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ctle_hf_stable_attr == SERDES_SHIM_DSP_L0_CFG_CTLE_HF_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_d_dly_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_data_sel_mux_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_data_width_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe10_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe11_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe12_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe13_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe14_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe15_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe16_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe1_clr_en_attr == SERDES_SHIM_DSP_L0_CFG_DFE1_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe1_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe1_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe1_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe2_16_clr_en_attr == SERDES_SHIM_DSP_L0_CFG_DFE2_16_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe2_16_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe2_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe4_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe5_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe6_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe7_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe8_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe9_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_0_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_10_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_11_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_12_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_13_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_14_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_15_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_1_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_2_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_3_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_4_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_5_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_6_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_7_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_8_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_9_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_all_taps_en_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_ALL_TAPS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_0_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_10_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_11_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_12_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_13_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_14_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_15_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_1_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_2_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_3_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_4_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_5_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_6_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_7_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_8_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_9_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_common_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_common_th_en_attr == SERDES_SHIM_DSP_L0_CFG_DFE_COMMON_TH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_d_sign_attr == SERDES_SHIM_DSP_L0_CFG_DFE_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_event_sign_attr == SERDES_SHIM_DSP_L0_CFG_DFE_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_tap10_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_tap11_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_tap12_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_tap13_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_tap14_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_tap15_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_tap16_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_tap1_sel_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dfe_tap9_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dsp_bit_swz_attr == SERDES_SHIM_DSP_L0_CFG_DSP_BIT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dsp_d_swz_attr == SERDES_SHIM_DSP_L0_CFG_DSP_D_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dsp_en_attr == SERDES_SHIM_DSP_L0_CFG_DSP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dsp_inner_d_swz_attr == SERDES_SHIM_DSP_L0_CFG_DSP_INNER_D_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dsp_inner_m_swz_attr == SERDES_SHIM_DSP_L0_CFG_DSP_INNER_M_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dsp_latch_dis_attr == SERDES_SHIM_DSP_L0_CFG_DSP_LATCH_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dsp_m_swz_attr == SERDES_SHIM_DSP_L0_CFG_DSP_M_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_dsp_sticky_clr_attr == SERDES_SHIM_DSP_L0_CFG_DSP_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_e_dly_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ehm_acc_clr_attr == SERDES_SHIM_DSP_L0_CFG_EHM_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ehm_event_rate_lsb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ehm_event_rate_msb_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ehm_event_sign_attr == SERDES_SHIM_DSP_L0_CFG_EHM_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ehm_sym1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ehm_sym_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ehm_tap_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ehm_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_en_duration_cnt_trig_attr == SERDES_SHIM_DSP_L0_CFG_EN_DURATION_CNT_TRIG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_en_duration_val_attr == 16'd625
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_err_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_err_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_error_counter_clr_attr == SERDES_SHIM_DSP_L0_CFG_ERROR_COUNTER_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_error_counter_enable_attr == SERDES_SHIM_DSP_L0_CFG_ERROR_COUNTER_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_error_counter_even_odd_select_attr == SERDES_SHIM_DSP_L0_CFG_ERROR_COUNTER_EVEN_ODD_SELECT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_error_counter_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_error_counter_resetb_attr == SERDES_SHIM_DSP_L0_CFG_ERROR_COUNTER_RESETB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_error_sel_mux_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_fine_attr == SERDES_SHIM_DSP_L0_CFG_FINE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_acc_clr1_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_acc_clr2_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_acc_clr3_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_acc_clr4_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_acc_clr5_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_acc_clr6_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_acc_clr7_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_acc_clr8_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_en_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_gps_tap32_sel_attr == SERDES_SHIM_DSP_L0_CFG_GPS_TAP32_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_gps_tap64_sel_attr == SERDES_SHIM_DSP_L0_CFG_GPS_TAP64_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ingress_dsp_disable_chkn_bit_attr == SERDES_SHIM_DSP_L0_CFG_INGRESS_DSP_DISABLE_CHKN_BIT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_io_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_joint_dfe_en_attr == SERDES_SHIM_DSP_L0_CFG_JOINT_DFE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_acc_clr_attr == SERDES_SHIM_DSP_L0_CFG_OFC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_clr_en_attr == SERDES_SHIM_DSP_L0_CFG_OFC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_cnt_offset_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_d_sign_attr == SERDES_SHIM_DSP_L0_CFG_OFC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_en_attr == SERDES_SHIM_DSP_L0_CFG_OFC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_event_sign_attr == SERDES_SHIM_DSP_L0_CFG_OFC_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_acc_clr1_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_acc_clr2_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_acc_clr3_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_acc_clr4_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_acc_clr5_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_acc_clr6_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_acc_clr7_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_acc_clr8_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_en_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_acc_clr1_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_acc_clr2_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_acc_clr3_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_acc_clr4_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_acc_clr5_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_acc_clr6_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_acc_clr7_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_acc_clr8_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_en_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_lsb_inv_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_LSB_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_lsb_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_ofc_th_attr == 20'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_pam4_bit_flip_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_pam4_gray_enable_attr == SERDES_SHIM_DSP_L0_CFG_PAM4_GRAY_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_pam_4_en_attr == SERDES_SHIM_DSP_L0_CFG_PAM_4_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_phase_cnt_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_phase_mask0_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_phase_mask1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_phase_mask2_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_phase_mask3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_phase_num_mask_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_pol_invert_attr == SERDES_SHIM_DSP_L0_CFG_POL_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_power_save_en_attr == SERDES_SHIM_DSP_L0_CFG_POWER_SAVE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_regs2visa_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_regs2visa_en_attr == SERDES_SHIM_DSP_L0_CFG_REGS2VISA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_res_isi_mes_en_attr == SERDES_SHIM_DSP_L0_CFG_RES_ISI_MES_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_snr_div_facror_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_snr_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_snr_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_snr_meter_en_attr == SERDES_SHIM_DSP_L0_CFG_SNR_METER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_snr_smooth_bw_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_0_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_10_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_11_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_12_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_13_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_14_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_15_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_16_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_17_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_18_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_1_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_2_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_3_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_4_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_5_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_6_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_7_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_8_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_9_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_swap_bot_en_attr == SERDES_SHIM_DSP_L0_CFG_SWAP_BOT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_swap_top_en_attr == SERDES_SHIM_DSP_L0_CFG_SWAP_TOP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_timeout_counter_value_attr == 17'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_vga_acc_clr_attr == SERDES_SHIM_DSP_L0_CFG_VGA_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_vga_clr_en_attr == SERDES_SHIM_DSP_L0_CFG_VGA_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_vga_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_vga_en_attr == SERDES_SHIM_DSP_L0_CFG_VGA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_vga_range_detect_comp_const_h_attr == 7'd126
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_vga_range_detect_comp_const_l_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_vga_range_detect_sub_const_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_vga_shift_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_vga_sticky_clr_attr == SERDES_SHIM_DSP_L0_CFG_VGA_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_vga_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_vref_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_x3_acc_clr_attr == SERDES_SHIM_DSP_L0_CFG_X3_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_x3_en_attr == SERDES_SHIM_DSP_L0_CFG_X3_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_x3_sticky_clr_attr == SERDES_SHIM_DSP_L0_CFG_X3_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l0_cfg_x3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_acc_clr_en_attr == SERDES_SHIM_DSP_L1_CFG_ACC_CLR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_acc_clr_rst_attr == SERDES_SHIM_DSP_L1_CFG_ACC_CLR_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_agc_acc_clr_attr == SERDES_SHIM_DSP_L1_CFG_AGC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_agc_clr_en_attr == SERDES_SHIM_DSP_L1_CFG_AGC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_agc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_agc_coarse_det_en_attr == SERDES_SHIM_DSP_L1_CFG_AGC_COARSE_DET_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_agc_coarse_det_pol_attr == SERDES_SHIM_DSP_L1_CFG_AGC_COARSE_DET_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_agc_d_sign_attr == SERDES_SHIM_DSP_L1_CFG_AGC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_agc_en_attr == SERDES_SHIM_DSP_L1_CFG_AGC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_agc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_agc_event_sign_attr == SERDES_SHIM_DSP_L1_CFG_AGC_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_agc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_agc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_agc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_agc_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_bb_stable_attr == SERDES_SHIM_DSP_L1_CFG_BB_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ctle_hf_stable_attr == SERDES_SHIM_DSP_L1_CFG_CTLE_HF_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_d_dly_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_data_sel_mux_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_data_width_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe10_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe11_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe12_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe13_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe14_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe15_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe16_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe1_clr_en_attr == SERDES_SHIM_DSP_L1_CFG_DFE1_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe1_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe1_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe1_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe2_16_clr_en_attr == SERDES_SHIM_DSP_L1_CFG_DFE2_16_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe2_16_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe2_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe4_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe5_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe6_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe7_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe8_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe9_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_0_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_10_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_11_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_12_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_13_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_14_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_15_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_1_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_2_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_3_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_4_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_5_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_6_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_7_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_8_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_9_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_all_taps_en_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_ALL_TAPS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_0_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_10_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_11_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_12_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_13_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_14_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_15_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_1_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_2_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_3_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_4_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_5_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_6_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_7_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_8_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_9_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_common_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_common_th_en_attr == SERDES_SHIM_DSP_L1_CFG_DFE_COMMON_TH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_d_sign_attr == SERDES_SHIM_DSP_L1_CFG_DFE_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_event_sign_attr == SERDES_SHIM_DSP_L1_CFG_DFE_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_tap10_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_tap11_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_tap12_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_tap13_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_tap14_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_tap15_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_tap16_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_tap1_sel_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dfe_tap9_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dsp_bit_swz_attr == SERDES_SHIM_DSP_L1_CFG_DSP_BIT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dsp_d_swz_attr == SERDES_SHIM_DSP_L1_CFG_DSP_D_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dsp_en_attr == SERDES_SHIM_DSP_L1_CFG_DSP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dsp_inner_d_swz_attr == SERDES_SHIM_DSP_L1_CFG_DSP_INNER_D_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dsp_inner_m_swz_attr == SERDES_SHIM_DSP_L1_CFG_DSP_INNER_M_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dsp_latch_dis_attr == SERDES_SHIM_DSP_L1_CFG_DSP_LATCH_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dsp_m_swz_attr == SERDES_SHIM_DSP_L1_CFG_DSP_M_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_dsp_sticky_clr_attr == SERDES_SHIM_DSP_L1_CFG_DSP_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_e_dly_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ehm_acc_clr_attr == SERDES_SHIM_DSP_L1_CFG_EHM_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ehm_event_rate_lsb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ehm_event_rate_msb_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ehm_event_sign_attr == SERDES_SHIM_DSP_L1_CFG_EHM_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ehm_sym1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ehm_sym_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ehm_tap_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ehm_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_en_duration_cnt_trig_attr == SERDES_SHIM_DSP_L1_CFG_EN_DURATION_CNT_TRIG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_en_duration_val_attr == 16'd625
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_err_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_err_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_error_counter_clr_attr == SERDES_SHIM_DSP_L1_CFG_ERROR_COUNTER_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_error_counter_enable_attr == SERDES_SHIM_DSP_L1_CFG_ERROR_COUNTER_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_error_counter_even_odd_select_attr == SERDES_SHIM_DSP_L1_CFG_ERROR_COUNTER_EVEN_ODD_SELECT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_error_counter_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_error_counter_resetb_attr == SERDES_SHIM_DSP_L1_CFG_ERROR_COUNTER_RESETB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_error_sel_mux_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_fine_attr == SERDES_SHIM_DSP_L1_CFG_FINE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_acc_clr1_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_acc_clr2_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_acc_clr3_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_acc_clr4_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_acc_clr5_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_acc_clr6_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_acc_clr7_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_acc_clr8_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_en_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_gps_tap32_sel_attr == SERDES_SHIM_DSP_L1_CFG_GPS_TAP32_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_gps_tap64_sel_attr == SERDES_SHIM_DSP_L1_CFG_GPS_TAP64_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ingress_dsp_disable_chkn_bit_attr == SERDES_SHIM_DSP_L1_CFG_INGRESS_DSP_DISABLE_CHKN_BIT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_io_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_joint_dfe_en_attr == SERDES_SHIM_DSP_L1_CFG_JOINT_DFE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_acc_clr_attr == SERDES_SHIM_DSP_L1_CFG_OFC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_clr_en_attr == SERDES_SHIM_DSP_L1_CFG_OFC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_cnt_offset_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_d_sign_attr == SERDES_SHIM_DSP_L1_CFG_OFC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_en_attr == SERDES_SHIM_DSP_L1_CFG_OFC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_event_sign_attr == SERDES_SHIM_DSP_L1_CFG_OFC_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_acc_clr1_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_acc_clr2_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_acc_clr3_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_acc_clr4_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_acc_clr5_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_acc_clr6_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_acc_clr7_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_acc_clr8_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_en_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_acc_clr1_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_acc_clr2_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_acc_clr3_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_acc_clr4_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_acc_clr5_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_acc_clr6_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_acc_clr7_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_acc_clr8_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_en_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_lsb_inv_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_LSB_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_lsb_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_ofc_th_attr == 20'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_pam4_bit_flip_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_pam4_gray_enable_attr == SERDES_SHIM_DSP_L1_CFG_PAM4_GRAY_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_pam_4_en_attr == SERDES_SHIM_DSP_L1_CFG_PAM_4_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_phase_cnt_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_phase_mask0_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_phase_mask1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_phase_mask2_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_phase_mask3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_phase_num_mask_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_pol_invert_attr == SERDES_SHIM_DSP_L1_CFG_POL_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_power_save_en_attr == SERDES_SHIM_DSP_L1_CFG_POWER_SAVE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_regs2visa_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_regs2visa_en_attr == SERDES_SHIM_DSP_L1_CFG_REGS2VISA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_res_isi_mes_en_attr == SERDES_SHIM_DSP_L1_CFG_RES_ISI_MES_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_snr_div_facror_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_snr_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_snr_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_snr_meter_en_attr == SERDES_SHIM_DSP_L1_CFG_SNR_METER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_snr_smooth_bw_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_0_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_10_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_11_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_12_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_13_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_14_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_15_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_16_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_17_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_18_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_1_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_2_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_3_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_4_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_5_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_6_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_7_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_8_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_9_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_swap_bot_en_attr == SERDES_SHIM_DSP_L1_CFG_SWAP_BOT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_swap_top_en_attr == SERDES_SHIM_DSP_L1_CFG_SWAP_TOP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_timeout_counter_value_attr == 17'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_vga_acc_clr_attr == SERDES_SHIM_DSP_L1_CFG_VGA_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_vga_clr_en_attr == SERDES_SHIM_DSP_L1_CFG_VGA_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_vga_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_vga_en_attr == SERDES_SHIM_DSP_L1_CFG_VGA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_vga_range_detect_comp_const_h_attr == 7'd126
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_vga_range_detect_comp_const_l_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_vga_range_detect_sub_const_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_vga_shift_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_vga_sticky_clr_attr == SERDES_SHIM_DSP_L1_CFG_VGA_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_vga_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_vref_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_x3_acc_clr_attr == SERDES_SHIM_DSP_L1_CFG_X3_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_x3_en_attr == SERDES_SHIM_DSP_L1_CFG_X3_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_x3_sticky_clr_attr == SERDES_SHIM_DSP_L1_CFG_X3_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l1_cfg_x3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_acc_clr_en_attr == SERDES_SHIM_DSP_L2_CFG_ACC_CLR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_acc_clr_rst_attr == SERDES_SHIM_DSP_L2_CFG_ACC_CLR_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_agc_acc_clr_attr == SERDES_SHIM_DSP_L2_CFG_AGC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_agc_clr_en_attr == SERDES_SHIM_DSP_L2_CFG_AGC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_agc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_agc_coarse_det_en_attr == SERDES_SHIM_DSP_L2_CFG_AGC_COARSE_DET_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_agc_coarse_det_pol_attr == SERDES_SHIM_DSP_L2_CFG_AGC_COARSE_DET_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_agc_d_sign_attr == SERDES_SHIM_DSP_L2_CFG_AGC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_agc_en_attr == SERDES_SHIM_DSP_L2_CFG_AGC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_agc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_agc_event_sign_attr == SERDES_SHIM_DSP_L2_CFG_AGC_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_agc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_agc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_agc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_agc_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_bb_stable_attr == SERDES_SHIM_DSP_L2_CFG_BB_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ctle_hf_stable_attr == SERDES_SHIM_DSP_L2_CFG_CTLE_HF_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_d_dly_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_data_sel_mux_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_data_width_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe10_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe11_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe12_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe13_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe14_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe15_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe16_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe1_clr_en_attr == SERDES_SHIM_DSP_L2_CFG_DFE1_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe1_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe1_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe1_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe2_16_clr_en_attr == SERDES_SHIM_DSP_L2_CFG_DFE2_16_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe2_16_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe2_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe4_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe5_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe6_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe7_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe8_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe9_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_0_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_10_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_11_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_12_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_13_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_14_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_15_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_1_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_2_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_3_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_4_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_5_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_6_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_7_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_8_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_9_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_all_taps_en_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_ALL_TAPS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_0_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_10_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_11_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_12_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_13_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_14_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_15_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_1_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_2_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_3_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_4_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_5_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_6_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_7_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_8_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_9_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_common_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_common_th_en_attr == SERDES_SHIM_DSP_L2_CFG_DFE_COMMON_TH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_d_sign_attr == SERDES_SHIM_DSP_L2_CFG_DFE_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_event_sign_attr == SERDES_SHIM_DSP_L2_CFG_DFE_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_tap10_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_tap11_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_tap12_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_tap13_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_tap14_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_tap15_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_tap16_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_tap1_sel_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dfe_tap9_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dsp_bit_swz_attr == SERDES_SHIM_DSP_L2_CFG_DSP_BIT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dsp_d_swz_attr == SERDES_SHIM_DSP_L2_CFG_DSP_D_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dsp_en_attr == SERDES_SHIM_DSP_L2_CFG_DSP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dsp_inner_d_swz_attr == SERDES_SHIM_DSP_L2_CFG_DSP_INNER_D_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dsp_inner_m_swz_attr == SERDES_SHIM_DSP_L2_CFG_DSP_INNER_M_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dsp_latch_dis_attr == SERDES_SHIM_DSP_L2_CFG_DSP_LATCH_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dsp_m_swz_attr == SERDES_SHIM_DSP_L2_CFG_DSP_M_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_dsp_sticky_clr_attr == SERDES_SHIM_DSP_L2_CFG_DSP_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_e_dly_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ehm_acc_clr_attr == SERDES_SHIM_DSP_L2_CFG_EHM_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ehm_event_rate_lsb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ehm_event_rate_msb_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ehm_event_sign_attr == SERDES_SHIM_DSP_L2_CFG_EHM_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ehm_sym1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ehm_sym_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ehm_tap_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ehm_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_en_duration_cnt_trig_attr == SERDES_SHIM_DSP_L2_CFG_EN_DURATION_CNT_TRIG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_en_duration_val_attr == 16'd625
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_err_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_err_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_error_counter_clr_attr == SERDES_SHIM_DSP_L2_CFG_ERROR_COUNTER_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_error_counter_enable_attr == SERDES_SHIM_DSP_L2_CFG_ERROR_COUNTER_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_error_counter_even_odd_select_attr == SERDES_SHIM_DSP_L2_CFG_ERROR_COUNTER_EVEN_ODD_SELECT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_error_counter_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_error_counter_resetb_attr == SERDES_SHIM_DSP_L2_CFG_ERROR_COUNTER_RESETB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_error_sel_mux_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_fine_attr == SERDES_SHIM_DSP_L2_CFG_FINE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_acc_clr1_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_acc_clr2_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_acc_clr3_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_acc_clr4_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_acc_clr5_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_acc_clr6_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_acc_clr7_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_acc_clr8_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_en_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_gps_tap32_sel_attr == SERDES_SHIM_DSP_L2_CFG_GPS_TAP32_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_gps_tap64_sel_attr == SERDES_SHIM_DSP_L2_CFG_GPS_TAP64_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ingress_dsp_disable_chkn_bit_attr == SERDES_SHIM_DSP_L2_CFG_INGRESS_DSP_DISABLE_CHKN_BIT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_io_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_joint_dfe_en_attr == SERDES_SHIM_DSP_L2_CFG_JOINT_DFE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_acc_clr_attr == SERDES_SHIM_DSP_L2_CFG_OFC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_clr_en_attr == SERDES_SHIM_DSP_L2_CFG_OFC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_cnt_offset_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_d_sign_attr == SERDES_SHIM_DSP_L2_CFG_OFC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_en_attr == SERDES_SHIM_DSP_L2_CFG_OFC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_event_sign_attr == SERDES_SHIM_DSP_L2_CFG_OFC_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_acc_clr1_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_acc_clr2_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_acc_clr3_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_acc_clr4_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_acc_clr5_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_acc_clr6_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_acc_clr7_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_acc_clr8_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_en_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_acc_clr1_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_acc_clr2_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_acc_clr3_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_acc_clr4_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_acc_clr5_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_acc_clr6_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_acc_clr7_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_acc_clr8_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_en_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_lsb_inv_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_LSB_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_lsb_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_ofc_th_attr == 20'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_pam4_bit_flip_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_pam4_gray_enable_attr == SERDES_SHIM_DSP_L2_CFG_PAM4_GRAY_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_pam_4_en_attr == SERDES_SHIM_DSP_L2_CFG_PAM_4_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_phase_cnt_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_phase_mask0_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_phase_mask1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_phase_mask2_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_phase_mask3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_phase_num_mask_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_pol_invert_attr == SERDES_SHIM_DSP_L2_CFG_POL_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_power_save_en_attr == SERDES_SHIM_DSP_L2_CFG_POWER_SAVE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_regs2visa_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_regs2visa_en_attr == SERDES_SHIM_DSP_L2_CFG_REGS2VISA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_res_isi_mes_en_attr == SERDES_SHIM_DSP_L2_CFG_RES_ISI_MES_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_snr_div_facror_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_snr_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_snr_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_snr_meter_en_attr == SERDES_SHIM_DSP_L2_CFG_SNR_METER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_snr_smooth_bw_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_0_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_10_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_11_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_12_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_13_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_14_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_15_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_16_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_17_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_18_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_1_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_2_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_3_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_4_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_5_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_6_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_7_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_8_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_9_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_swap_bot_en_attr == SERDES_SHIM_DSP_L2_CFG_SWAP_BOT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_swap_top_en_attr == SERDES_SHIM_DSP_L2_CFG_SWAP_TOP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_timeout_counter_value_attr == 17'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_vga_acc_clr_attr == SERDES_SHIM_DSP_L2_CFG_VGA_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_vga_clr_en_attr == SERDES_SHIM_DSP_L2_CFG_VGA_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_vga_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_vga_en_attr == SERDES_SHIM_DSP_L2_CFG_VGA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_vga_range_detect_comp_const_h_attr == 7'd126
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_vga_range_detect_comp_const_l_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_vga_range_detect_sub_const_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_vga_shift_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_vga_sticky_clr_attr == SERDES_SHIM_DSP_L2_CFG_VGA_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_vga_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_vref_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_x3_acc_clr_attr == SERDES_SHIM_DSP_L2_CFG_X3_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_x3_en_attr == SERDES_SHIM_DSP_L2_CFG_X3_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_x3_sticky_clr_attr == SERDES_SHIM_DSP_L2_CFG_X3_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l2_cfg_x3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_acc_clr_en_attr == SERDES_SHIM_DSP_L3_CFG_ACC_CLR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_acc_clr_rst_attr == SERDES_SHIM_DSP_L3_CFG_ACC_CLR_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_agc_acc_clr_attr == SERDES_SHIM_DSP_L3_CFG_AGC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_agc_clr_en_attr == SERDES_SHIM_DSP_L3_CFG_AGC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_agc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_agc_coarse_det_en_attr == SERDES_SHIM_DSP_L3_CFG_AGC_COARSE_DET_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_agc_coarse_det_pol_attr == SERDES_SHIM_DSP_L3_CFG_AGC_COARSE_DET_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_agc_d_sign_attr == SERDES_SHIM_DSP_L3_CFG_AGC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_agc_en_attr == SERDES_SHIM_DSP_L3_CFG_AGC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_agc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_agc_event_sign_attr == SERDES_SHIM_DSP_L3_CFG_AGC_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_agc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_agc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_agc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_agc_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_bb_stable_attr == SERDES_SHIM_DSP_L3_CFG_BB_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ctle_hf_stable_attr == SERDES_SHIM_DSP_L3_CFG_CTLE_HF_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_d_dly_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_data_sel_mux_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_data_width_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe10_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe11_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe12_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe13_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe14_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe15_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe16_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe1_clr_en_attr == SERDES_SHIM_DSP_L3_CFG_DFE1_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe1_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe1_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe1_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe2_16_clr_en_attr == SERDES_SHIM_DSP_L3_CFG_DFE2_16_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe2_16_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe2_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe4_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe5_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe6_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe7_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe8_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe9_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_0_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_10_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_11_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_12_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_13_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_14_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_15_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_1_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_2_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_3_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_4_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_5_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_6_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_7_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_8_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_9_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_all_taps_en_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_ALL_TAPS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_0_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_10_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_11_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_12_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_13_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_14_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_15_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_1_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_2_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_3_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_4_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_5_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_6_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_7_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_8_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_9_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_common_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_common_th_en_attr == SERDES_SHIM_DSP_L3_CFG_DFE_COMMON_TH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_d_sign_attr == SERDES_SHIM_DSP_L3_CFG_DFE_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_event_sign_attr == SERDES_SHIM_DSP_L3_CFG_DFE_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_tap10_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_tap11_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_tap12_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_tap13_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_tap14_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_tap15_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_tap16_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_tap1_sel_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dfe_tap9_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dsp_bit_swz_attr == SERDES_SHIM_DSP_L3_CFG_DSP_BIT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dsp_d_swz_attr == SERDES_SHIM_DSP_L3_CFG_DSP_D_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dsp_en_attr == SERDES_SHIM_DSP_L3_CFG_DSP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dsp_inner_d_swz_attr == SERDES_SHIM_DSP_L3_CFG_DSP_INNER_D_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dsp_inner_m_swz_attr == SERDES_SHIM_DSP_L3_CFG_DSP_INNER_M_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dsp_latch_dis_attr == SERDES_SHIM_DSP_L3_CFG_DSP_LATCH_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dsp_m_swz_attr == SERDES_SHIM_DSP_L3_CFG_DSP_M_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_dsp_sticky_clr_attr == SERDES_SHIM_DSP_L3_CFG_DSP_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_e_dly_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ehm_acc_clr_attr == SERDES_SHIM_DSP_L3_CFG_EHM_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ehm_event_rate_lsb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ehm_event_rate_msb_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ehm_event_sign_attr == SERDES_SHIM_DSP_L3_CFG_EHM_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ehm_sym1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ehm_sym_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ehm_tap_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ehm_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_en_duration_cnt_trig_attr == SERDES_SHIM_DSP_L3_CFG_EN_DURATION_CNT_TRIG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_en_duration_val_attr == 16'd625
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_err_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_err_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_error_counter_clr_attr == SERDES_SHIM_DSP_L3_CFG_ERROR_COUNTER_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_error_counter_enable_attr == SERDES_SHIM_DSP_L3_CFG_ERROR_COUNTER_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_error_counter_even_odd_select_attr == SERDES_SHIM_DSP_L3_CFG_ERROR_COUNTER_EVEN_ODD_SELECT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_error_counter_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_error_counter_resetb_attr == SERDES_SHIM_DSP_L3_CFG_ERROR_COUNTER_RESETB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_error_sel_mux_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_fine_attr == SERDES_SHIM_DSP_L3_CFG_FINE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_acc_clr1_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_acc_clr2_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_acc_clr3_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_acc_clr4_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_acc_clr5_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_acc_clr6_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_acc_clr7_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_acc_clr8_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_en_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_gps_tap32_sel_attr == SERDES_SHIM_DSP_L3_CFG_GPS_TAP32_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_gps_tap64_sel_attr == SERDES_SHIM_DSP_L3_CFG_GPS_TAP64_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ingress_dsp_disable_chkn_bit_attr == SERDES_SHIM_DSP_L3_CFG_INGRESS_DSP_DISABLE_CHKN_BIT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_io_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_joint_dfe_en_attr == SERDES_SHIM_DSP_L3_CFG_JOINT_DFE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_acc_clr_attr == SERDES_SHIM_DSP_L3_CFG_OFC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_clr_en_attr == SERDES_SHIM_DSP_L3_CFG_OFC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_cnt_offset_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_d_sign_attr == SERDES_SHIM_DSP_L3_CFG_OFC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_en_attr == SERDES_SHIM_DSP_L3_CFG_OFC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_event_sign_attr == SERDES_SHIM_DSP_L3_CFG_OFC_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_acc_clr1_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_acc_clr2_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_acc_clr3_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_acc_clr4_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_acc_clr5_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_acc_clr6_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_acc_clr7_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_acc_clr8_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_en_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_acc_clr1_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_acc_clr2_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_acc_clr3_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_acc_clr4_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_acc_clr5_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_acc_clr6_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_acc_clr7_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_acc_clr8_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_en_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_lsb_inv_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_LSB_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_lsb_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_ofc_th_attr == 20'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_pam4_bit_flip_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_pam4_gray_enable_attr == SERDES_SHIM_DSP_L3_CFG_PAM4_GRAY_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_pam_4_en_attr == SERDES_SHIM_DSP_L3_CFG_PAM_4_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_phase_cnt_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_phase_mask0_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_phase_mask1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_phase_mask2_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_phase_mask3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_phase_num_mask_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_pol_invert_attr == SERDES_SHIM_DSP_L3_CFG_POL_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_power_save_en_attr == SERDES_SHIM_DSP_L3_CFG_POWER_SAVE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_regs2visa_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_regs2visa_en_attr == SERDES_SHIM_DSP_L3_CFG_REGS2VISA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_res_isi_mes_en_attr == SERDES_SHIM_DSP_L3_CFG_RES_ISI_MES_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_snr_div_facror_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_snr_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_snr_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_snr_meter_en_attr == SERDES_SHIM_DSP_L3_CFG_SNR_METER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_snr_smooth_bw_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_0_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_10_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_11_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_12_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_13_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_14_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_15_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_16_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_17_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_18_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_1_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_2_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_3_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_4_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_5_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_6_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_7_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_8_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_9_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_swap_bot_en_attr == SERDES_SHIM_DSP_L3_CFG_SWAP_BOT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_swap_top_en_attr == SERDES_SHIM_DSP_L3_CFG_SWAP_TOP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_timeout_counter_value_attr == 17'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_vga_acc_clr_attr == SERDES_SHIM_DSP_L3_CFG_VGA_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_vga_clr_en_attr == SERDES_SHIM_DSP_L3_CFG_VGA_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_vga_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_vga_en_attr == SERDES_SHIM_DSP_L3_CFG_VGA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_vga_range_detect_comp_const_h_attr == 7'd126
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_vga_range_detect_comp_const_l_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_vga_range_detect_sub_const_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_vga_shift_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_vga_sticky_clr_attr == SERDES_SHIM_DSP_L3_CFG_VGA_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_vga_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_vref_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_x3_acc_clr_attr == SERDES_SHIM_DSP_L3_CFG_X3_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_x3_en_attr == SERDES_SHIM_DSP_L3_CFG_X3_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_x3_sticky_clr_attr == SERDES_SHIM_DSP_L3_CFG_X3_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_dsp_l3_cfg_x3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_cfg_prbs13_seed_2_attr == 13'd7571
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_cfg_prbs13_seed_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_cfg_tfl_prbs11_en_attr == SERDES_SHIM_TFL_L0_CFG_CFG_TFL_PRBS11_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_cl136_ctrl_field_11_10_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_cl136_ctrl_field_13_12_init_cond_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_cl136_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_cl136_ctrl_field_1_0_coeff_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_cl136_ctrl_field_4_2_coeff_select_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_cl136_ctrl_field_7_5_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_cl136_ctrl_field_9_8_mod_precode_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_cl136_frame_cycle_to_lock_attr == 10'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_cl136_prbs_encoder_select_even_attr == SERDES_SHIM_TFL_L0_CFG_CL136_PRBS_ENCODER_SELECT_EVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_cl136_precoder_out_swz_attr == SERDES_SHIM_TFL_L0_CFG_CL136_PRECODER_OUT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_cl136_precoder_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_cl136_stts_field_11_10_mod_precode_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_cl136_stts_field_14_12_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_cl136_stts_field_15_rx_ready_attr == SERDES_SHIM_TFL_L0_CFG_CL136_STTS_FIELD_15_RX_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_cl136_stts_field_2_0_coeff_stts_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_cl136_stts_field_5_3_coeff_sel_echo_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_cl136_stts_field_6_rsvd_attr == SERDES_SHIM_TFL_L0_CFG_CL136_STTS_FIELD_6_RSVD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_cl136_stts_field_7_parity_attr == SERDES_SHIM_TFL_L0_CFG_CL136_STTS_FIELD_7_PARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_cl136_stts_field_8_init_cond_stts_attr == SERDES_SHIM_TFL_L0_CFG_CL136_STTS_FIELD_8_INIT_COND_STTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_cl136_stts_field_9_rx_frame_lock_attr == SERDES_SHIM_TFL_L0_CFG_CL136_STTS_FIELD_9_RX_FRAME_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_cl72_ctrl_field_11_6_rsvd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_cl72_ctrl_field_12_initialize_attr == SERDES_SHIM_TFL_L0_CFG_CL72_CTRL_FIELD_12_INITIALIZE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_cl72_ctrl_field_13_preset_attr == SERDES_SHIM_TFL_L0_CFG_CL72_CTRL_FIELD_13_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_cl72_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_cl72_ctrl_field_1_0_coef_m1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_cl72_ctrl_field_3_2_coef_0_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_cl72_ctrl_field_5_4_coef_p1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_cl72_frame_cycle_to_lock_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_cl72_stts_field_14_6_rsvd_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_cl72_stts_field_15_rcv_ready_attr == SERDES_SHIM_TFL_L0_CFG_CL72_STTS_FIELD_15_RCV_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_cl72_stts_field_1_0_coef_m1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_cl72_stts_field_3_2_coef_0_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_cl72_stts_field_5_4_coef_p1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_frame_boundary_early_attr == SERDES_SHIM_TFL_L0_CFG_FRAME_BOUNDARY_EARLY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_gb_128_80_en_attr == SERDES_SHIM_TFL_L0_CFG_GB_128_80_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_ignore_tfl_en_to_avoid_cut_frame_attr == SERDES_SHIM_TFL_L0_CFG_IGNORE_TFL_EN_TO_AVOID_CUT_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_polynomial_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_prbs11_seed_2_attr == 11'd977
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_prbs11_seed_attr == 11'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_ber_count_snap_lock_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL136_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_ber_counter_clear_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL136_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_clear_one_marker_seen_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL136_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL136_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL136_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL136_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_pam4_modulation_select_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_prbs_ber_en_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL136_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_prbs_seed_force_en_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL136_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_prbs_seed_force_val_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_ber_count_snap_lock_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL72_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_ber_counter_clear_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL72_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_clear_one_marker_seen_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL72_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL72_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL72_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL72_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_prbs_ber_en_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL72_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_prbs_seed_force_en_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL72_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_prbs_seed_force_val_attr == 13'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_gb_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_rx_sync_pulse_attr == SERDES_SHIM_TFL_L0_CFG_RX_SYNC_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_scrambler_force_init_at_each_frame_attr == SERDES_SHIM_TFL_L0_CFG_SCRAMBLER_FORCE_INIT_AT_EACH_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_send_data_attr == SERDES_SHIM_TFL_L0_CFG_SEND_DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_sync_ctrl_stts_word_pulse_attr == SERDES_SHIM_TFL_L0_CFG_SYNC_CTRL_STTS_WORD_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_tfl_prbs13_en_attr == SERDES_SHIM_TFL_L0_CFG_TFL_PRBS13_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_tfl_pulse_sync_attr == SERDES_SHIM_TFL_L0_CFG_TFL_PULSE_SYNC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_tfl_training_enable_rx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_tfl_training_enable_tx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l0_cfg_tx_gb_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_cfg_prbs13_seed_2_attr == 13'd7571
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_cfg_prbs13_seed_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_cfg_tfl_prbs11_en_attr == SERDES_SHIM_TFL_L1_CFG_CFG_TFL_PRBS11_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_cl136_ctrl_field_11_10_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_cl136_ctrl_field_13_12_init_cond_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_cl136_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_cl136_ctrl_field_1_0_coeff_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_cl136_ctrl_field_4_2_coeff_select_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_cl136_ctrl_field_7_5_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_cl136_ctrl_field_9_8_mod_precode_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_cl136_frame_cycle_to_lock_attr == 10'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_cl136_prbs_encoder_select_even_attr == SERDES_SHIM_TFL_L1_CFG_CL136_PRBS_ENCODER_SELECT_EVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_cl136_precoder_out_swz_attr == SERDES_SHIM_TFL_L1_CFG_CL136_PRECODER_OUT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_cl136_precoder_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_cl136_stts_field_11_10_mod_precode_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_cl136_stts_field_14_12_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_cl136_stts_field_15_rx_ready_attr == SERDES_SHIM_TFL_L1_CFG_CL136_STTS_FIELD_15_RX_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_cl136_stts_field_2_0_coeff_stts_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_cl136_stts_field_5_3_coeff_sel_echo_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_cl136_stts_field_6_rsvd_attr == SERDES_SHIM_TFL_L1_CFG_CL136_STTS_FIELD_6_RSVD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_cl136_stts_field_7_parity_attr == SERDES_SHIM_TFL_L1_CFG_CL136_STTS_FIELD_7_PARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_cl136_stts_field_8_init_cond_stts_attr == SERDES_SHIM_TFL_L1_CFG_CL136_STTS_FIELD_8_INIT_COND_STTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_cl136_stts_field_9_rx_frame_lock_attr == SERDES_SHIM_TFL_L1_CFG_CL136_STTS_FIELD_9_RX_FRAME_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_cl72_ctrl_field_11_6_rsvd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_cl72_ctrl_field_12_initialize_attr == SERDES_SHIM_TFL_L1_CFG_CL72_CTRL_FIELD_12_INITIALIZE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_cl72_ctrl_field_13_preset_attr == SERDES_SHIM_TFL_L1_CFG_CL72_CTRL_FIELD_13_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_cl72_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_cl72_ctrl_field_1_0_coef_m1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_cl72_ctrl_field_3_2_coef_0_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_cl72_ctrl_field_5_4_coef_p1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_cl72_frame_cycle_to_lock_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_cl72_stts_field_14_6_rsvd_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_cl72_stts_field_15_rcv_ready_attr == SERDES_SHIM_TFL_L1_CFG_CL72_STTS_FIELD_15_RCV_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_cl72_stts_field_1_0_coef_m1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_cl72_stts_field_3_2_coef_0_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_cl72_stts_field_5_4_coef_p1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_frame_boundary_early_attr == SERDES_SHIM_TFL_L1_CFG_FRAME_BOUNDARY_EARLY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_gb_128_80_en_attr == SERDES_SHIM_TFL_L1_CFG_GB_128_80_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_ignore_tfl_en_to_avoid_cut_frame_attr == SERDES_SHIM_TFL_L1_CFG_IGNORE_TFL_EN_TO_AVOID_CUT_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_polynomial_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_prbs11_seed_2_attr == 11'd977
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_prbs11_seed_attr == 11'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_ber_count_snap_lock_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL136_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_ber_counter_clear_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL136_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_clear_one_marker_seen_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL136_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL136_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL136_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL136_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_pam4_modulation_select_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_prbs_ber_en_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL136_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_prbs_seed_force_en_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL136_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_prbs_seed_force_val_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_ber_count_snap_lock_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL72_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_ber_counter_clear_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL72_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_clear_one_marker_seen_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL72_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL72_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL72_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL72_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_prbs_ber_en_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL72_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_prbs_seed_force_en_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL72_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_prbs_seed_force_val_attr == 13'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_gb_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_rx_sync_pulse_attr == SERDES_SHIM_TFL_L1_CFG_RX_SYNC_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_scrambler_force_init_at_each_frame_attr == SERDES_SHIM_TFL_L1_CFG_SCRAMBLER_FORCE_INIT_AT_EACH_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_send_data_attr == SERDES_SHIM_TFL_L1_CFG_SEND_DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_sync_ctrl_stts_word_pulse_attr == SERDES_SHIM_TFL_L1_CFG_SYNC_CTRL_STTS_WORD_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_tfl_prbs13_en_attr == SERDES_SHIM_TFL_L1_CFG_TFL_PRBS13_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_tfl_pulse_sync_attr == SERDES_SHIM_TFL_L1_CFG_TFL_PULSE_SYNC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_tfl_training_enable_rx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_tfl_training_enable_tx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l1_cfg_tx_gb_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_cfg_prbs13_seed_2_attr == 13'd7571
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_cfg_prbs13_seed_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_cfg_tfl_prbs11_en_attr == SERDES_SHIM_TFL_L2_CFG_CFG_TFL_PRBS11_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_cl136_ctrl_field_11_10_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_cl136_ctrl_field_13_12_init_cond_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_cl136_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_cl136_ctrl_field_1_0_coeff_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_cl136_ctrl_field_4_2_coeff_select_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_cl136_ctrl_field_7_5_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_cl136_ctrl_field_9_8_mod_precode_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_cl136_frame_cycle_to_lock_attr == 10'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_cl136_prbs_encoder_select_even_attr == SERDES_SHIM_TFL_L2_CFG_CL136_PRBS_ENCODER_SELECT_EVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_cl136_precoder_out_swz_attr == SERDES_SHIM_TFL_L2_CFG_CL136_PRECODER_OUT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_cl136_precoder_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_cl136_stts_field_11_10_mod_precode_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_cl136_stts_field_14_12_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_cl136_stts_field_15_rx_ready_attr == SERDES_SHIM_TFL_L2_CFG_CL136_STTS_FIELD_15_RX_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_cl136_stts_field_2_0_coeff_stts_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_cl136_stts_field_5_3_coeff_sel_echo_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_cl136_stts_field_6_rsvd_attr == SERDES_SHIM_TFL_L2_CFG_CL136_STTS_FIELD_6_RSVD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_cl136_stts_field_7_parity_attr == SERDES_SHIM_TFL_L2_CFG_CL136_STTS_FIELD_7_PARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_cl136_stts_field_8_init_cond_stts_attr == SERDES_SHIM_TFL_L2_CFG_CL136_STTS_FIELD_8_INIT_COND_STTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_cl136_stts_field_9_rx_frame_lock_attr == SERDES_SHIM_TFL_L2_CFG_CL136_STTS_FIELD_9_RX_FRAME_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_cl72_ctrl_field_11_6_rsvd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_cl72_ctrl_field_12_initialize_attr == SERDES_SHIM_TFL_L2_CFG_CL72_CTRL_FIELD_12_INITIALIZE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_cl72_ctrl_field_13_preset_attr == SERDES_SHIM_TFL_L2_CFG_CL72_CTRL_FIELD_13_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_cl72_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_cl72_ctrl_field_1_0_coef_m1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_cl72_ctrl_field_3_2_coef_0_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_cl72_ctrl_field_5_4_coef_p1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_cl72_frame_cycle_to_lock_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_cl72_stts_field_14_6_rsvd_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_cl72_stts_field_15_rcv_ready_attr == SERDES_SHIM_TFL_L2_CFG_CL72_STTS_FIELD_15_RCV_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_cl72_stts_field_1_0_coef_m1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_cl72_stts_field_3_2_coef_0_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_cl72_stts_field_5_4_coef_p1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_frame_boundary_early_attr == SERDES_SHIM_TFL_L2_CFG_FRAME_BOUNDARY_EARLY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_gb_128_80_en_attr == SERDES_SHIM_TFL_L2_CFG_GB_128_80_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_ignore_tfl_en_to_avoid_cut_frame_attr == SERDES_SHIM_TFL_L2_CFG_IGNORE_TFL_EN_TO_AVOID_CUT_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_polynomial_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_prbs11_seed_2_attr == 11'd977
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_prbs11_seed_attr == 11'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_ber_count_snap_lock_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL136_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_ber_counter_clear_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL136_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_clear_one_marker_seen_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL136_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL136_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL136_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL136_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_pam4_modulation_select_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_prbs_ber_en_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL136_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_prbs_seed_force_en_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL136_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_prbs_seed_force_val_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_ber_count_snap_lock_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL72_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_ber_counter_clear_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL72_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_clear_one_marker_seen_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL72_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL72_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL72_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL72_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_prbs_ber_en_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL72_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_prbs_seed_force_en_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL72_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_prbs_seed_force_val_attr == 13'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_gb_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_rx_sync_pulse_attr == SERDES_SHIM_TFL_L2_CFG_RX_SYNC_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_scrambler_force_init_at_each_frame_attr == SERDES_SHIM_TFL_L2_CFG_SCRAMBLER_FORCE_INIT_AT_EACH_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_send_data_attr == SERDES_SHIM_TFL_L2_CFG_SEND_DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_sync_ctrl_stts_word_pulse_attr == SERDES_SHIM_TFL_L2_CFG_SYNC_CTRL_STTS_WORD_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_tfl_prbs13_en_attr == SERDES_SHIM_TFL_L2_CFG_TFL_PRBS13_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_tfl_pulse_sync_attr == SERDES_SHIM_TFL_L2_CFG_TFL_PULSE_SYNC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_tfl_training_enable_rx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_tfl_training_enable_tx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l2_cfg_tx_gb_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_cfg_prbs13_seed_2_attr == 13'd7571
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_cfg_prbs13_seed_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_cfg_tfl_prbs11_en_attr == SERDES_SHIM_TFL_L3_CFG_CFG_TFL_PRBS11_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_cl136_ctrl_field_11_10_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_cl136_ctrl_field_13_12_init_cond_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_cl136_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_cl136_ctrl_field_1_0_coeff_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_cl136_ctrl_field_4_2_coeff_select_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_cl136_ctrl_field_7_5_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_cl136_ctrl_field_9_8_mod_precode_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_cl136_frame_cycle_to_lock_attr == 10'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_cl136_prbs_encoder_select_even_attr == SERDES_SHIM_TFL_L3_CFG_CL136_PRBS_ENCODER_SELECT_EVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_cl136_precoder_out_swz_attr == SERDES_SHIM_TFL_L3_CFG_CL136_PRECODER_OUT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_cl136_precoder_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_cl136_stts_field_11_10_mod_precode_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_cl136_stts_field_14_12_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_cl136_stts_field_15_rx_ready_attr == SERDES_SHIM_TFL_L3_CFG_CL136_STTS_FIELD_15_RX_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_cl136_stts_field_2_0_coeff_stts_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_cl136_stts_field_5_3_coeff_sel_echo_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_cl136_stts_field_6_rsvd_attr == SERDES_SHIM_TFL_L3_CFG_CL136_STTS_FIELD_6_RSVD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_cl136_stts_field_7_parity_attr == SERDES_SHIM_TFL_L3_CFG_CL136_STTS_FIELD_7_PARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_cl136_stts_field_8_init_cond_stts_attr == SERDES_SHIM_TFL_L3_CFG_CL136_STTS_FIELD_8_INIT_COND_STTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_cl136_stts_field_9_rx_frame_lock_attr == SERDES_SHIM_TFL_L3_CFG_CL136_STTS_FIELD_9_RX_FRAME_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_cl72_ctrl_field_11_6_rsvd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_cl72_ctrl_field_12_initialize_attr == SERDES_SHIM_TFL_L3_CFG_CL72_CTRL_FIELD_12_INITIALIZE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_cl72_ctrl_field_13_preset_attr == SERDES_SHIM_TFL_L3_CFG_CL72_CTRL_FIELD_13_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_cl72_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_cl72_ctrl_field_1_0_coef_m1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_cl72_ctrl_field_3_2_coef_0_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_cl72_ctrl_field_5_4_coef_p1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_cl72_frame_cycle_to_lock_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_cl72_stts_field_14_6_rsvd_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_cl72_stts_field_15_rcv_ready_attr == SERDES_SHIM_TFL_L3_CFG_CL72_STTS_FIELD_15_RCV_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_cl72_stts_field_1_0_coef_m1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_cl72_stts_field_3_2_coef_0_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_cl72_stts_field_5_4_coef_p1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_frame_boundary_early_attr == SERDES_SHIM_TFL_L3_CFG_FRAME_BOUNDARY_EARLY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_gb_128_80_en_attr == SERDES_SHIM_TFL_L3_CFG_GB_128_80_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_ignore_tfl_en_to_avoid_cut_frame_attr == SERDES_SHIM_TFL_L3_CFG_IGNORE_TFL_EN_TO_AVOID_CUT_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_polynomial_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_prbs11_seed_2_attr == 11'd977
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_prbs11_seed_attr == 11'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_ber_count_snap_lock_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL136_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_ber_counter_clear_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL136_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_clear_one_marker_seen_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL136_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL136_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL136_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL136_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_pam4_modulation_select_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_prbs_ber_en_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL136_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_prbs_seed_force_en_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL136_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_prbs_seed_force_val_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_ber_count_snap_lock_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL72_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_ber_counter_clear_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL72_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_clear_one_marker_seen_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL72_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL72_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL72_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL72_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_prbs_ber_en_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL72_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_prbs_seed_force_en_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL72_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_prbs_seed_force_val_attr == 13'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_gb_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_rx_sync_pulse_attr == SERDES_SHIM_TFL_L3_CFG_RX_SYNC_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_scrambler_force_init_at_each_frame_attr == SERDES_SHIM_TFL_L3_CFG_SCRAMBLER_FORCE_INIT_AT_EACH_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_send_data_attr == SERDES_SHIM_TFL_L3_CFG_SEND_DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_sync_ctrl_stts_word_pulse_attr == SERDES_SHIM_TFL_L3_CFG_SYNC_CTRL_STTS_WORD_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_tfl_prbs13_en_attr == SERDES_SHIM_TFL_L3_CFG_TFL_PRBS13_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_tfl_pulse_sync_attr == SERDES_SHIM_TFL_L3_CFG_TFL_PULSE_SYNC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_tfl_training_enable_rx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_tfl_training_enable_tx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_tfl_l3_cfg_tx_gb_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_top_cfg_broadcast_feature_en_attr == SERDES_SHIM_TOP_CFG_BROADCAST_FEATURE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_top_cfg_broadcast_type_attr == SERDES_SHIM_TOP_CFG_BROADCAST_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_top_cfg_fabric_wd_counter_max_attr == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_top_cfg_fec_ber_datawidth_sel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_top_cfg_fec_ber_en_attr == SERDES_SHIM_TOP_CFG_FEC_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_top_cfg_fec_ber_mask8_attr == 8'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_top_cfg_fec_ber_packet_sel_attr == SERDES_SHIM_TOP_CFG_FEC_BER_PACKET_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_top_cfg_fec_ber_poly_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_top_cfg_fec_ber_rs_type_sel_attr == SERDES_SHIM_TOP_CFG_FEC_BER_RS_TYPE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_top_cfg_fec_ber_statistic_en_attr == SERDES_SHIM_TOP_CFG_FEC_BER_STATISTIC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_top_cfg_serdes_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_top_cfg_serdes_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_top_cfg_serdes_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_top_cfg_wdt_clr_attr == SERDES_SHIM_TOP_CFG_WDT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_top_cfg_wdt_en_attr == SERDES_SHIM_TOP_CFG_WDT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_top_cfg_wdt_pre_scale_attr == 32'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_top_cfg_wdt_rst_after_irq_mode_attr == SERDES_SHIM_TOP_CFG_WDT_RST_AFTER_IRQ_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_top_cfg_wdt_swrst_en_attr == SERDES_SHIM_TOP_CFG_WDT_SWRST_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_top_cfg_wdt_time_val_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_apb_cfg_presetn_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_CFG_PRESETN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_apb_lgc_rstn_serdes_ux_lane0_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_LGC_RSTN_SERDES_UX_LANE0_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_apb_lgc_rstn_serdes_ux_lane1_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_LGC_RSTN_SERDES_UX_LANE1_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_apb_lgc_rstn_serdes_ux_lane2_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_LGC_RSTN_SERDES_UX_LANE2_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_apb_lgc_rstn_serdes_ux_lane3_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_LGC_RSTN_SERDES_UX_LANE3_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_apb_mem_rstn_serdes_ux_lane0_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_MEM_RSTN_SERDES_UX_LANE0_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_apb_mem_rstn_serdes_ux_lane1_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_MEM_RSTN_SERDES_UX_LANE1_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_apb_mem_rstn_serdes_ux_lane2_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_MEM_RSTN_SERDES_UX_LANE2_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_apb_mem_rstn_serdes_ux_lane3_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_MEM_RSTN_SERDES_UX_LANE3_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_clkrx_bot_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_CLKRX_BOT_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_clkrx_top_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_CLKRX_TOP_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_lane0_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_LANE0_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_lane1_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_LANE1_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_lane2_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_LANE2_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_lane3_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_LANE3_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_scmng_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_SCMNG_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_srds_ctrl_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_SRDS_CTRL_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_srds_ux_lane0_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_SRDS_UX_LANE0_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_srds_ux_lane1_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_SRDS_UX_LANE1_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_srds_ux_lane2_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_SRDS_UX_LANE2_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_srds_ux_lane3_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_SRDS_UX_LANE3_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_clkrx_bot_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_CLKRX_BOT_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_clkrx_top_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_CLKRX_TOP_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_lane0_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_LANE0_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_lane1_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_LANE1_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_lane2_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_LANE2_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_lane3_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_LANE3_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_scmng_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_SCMNG_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_srds_ctrl_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_SRDS_CTRL_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_srds_ux_lane0_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_SRDS_UX_LANE0_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_srds_ux_lane1_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_SRDS_UX_LANE1_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_srds_ux_lane2_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_SRDS_UX_LANE2_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_srds_ux_lane3_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_SRDS_UX_LANE3_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_car_ux_lane_rst_src_sel_lane0_attr == SERDES_SHIM_WRAP_CAR_CFG_CAR_UX_LANE_RST_SRC_SEL_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_car_ux_lane_rst_src_sel_lane1_attr == SERDES_SHIM_WRAP_CAR_CFG_CAR_UX_LANE_RST_SRC_SEL_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_car_ux_lane_rst_src_sel_lane2_attr == SERDES_SHIM_WRAP_CAR_CFG_CAR_UX_LANE_RST_SRC_SEL_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_car_ux_lane_rst_src_sel_lane3_attr == SERDES_SHIM_WRAP_CAR_CFG_CAR_UX_LANE_RST_SRC_SEL_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_clkrx_ref_clk_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_cpu_apb_clocks_ratio_attr == SERDES_SHIM_WRAP_CAR_CFG_CPU_APB_CLOCKS_RATIO_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_cpu_clk_sel_attr == SERDES_SHIM_WRAP_CAR_CFG_CPU_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_cpu_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_CPU_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_cpu_runstall_attr == SERDES_SHIM_WRAP_CAR_CFG_CPU_RUNSTALL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_cpu_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_CPU_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_fast_clk_divn_en_attr == SERDES_SHIM_WRAP_CAR_CFG_FAST_CLK_DIVN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_fast_clk_divn_val_attr == 8'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_fast_clk_lane_sel_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_fb_cpu_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_FB_CPU_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_fb_cpu_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_FB_CPU_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_fb_rx_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_FB_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_fb_rx_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_FB_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_fec_ber_lane_select_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_hwrstn_clkrx_bot_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_CLKRX_BOT_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_hwrstn_clkrx_top_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_CLKRX_TOP_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_hwrstn_lane0_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_LANE0_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_hwrstn_lane1_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_LANE1_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_hwrstn_lane2_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_LANE2_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_hwrstn_lane3_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_LANE3_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_hwrstn_scmng_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_SCMNG_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_hwrstn_serdes_ctrl_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_SERDES_CTRL_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_hwrstn_serdes_ux_lane0_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_SERDES_UX_LANE0_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_hwrstn_serdes_ux_lane1_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_SERDES_UX_LANE1_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_hwrstn_serdes_ux_lane2_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_SERDES_UX_LANE2_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_hwrstn_serdes_ux_lane3_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_SERDES_UX_LANE3_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_lane_car_apb_cfg_presetn_swrstn_lane0_attr == SERDES_SHIM_WRAP_CAR_CFG_LANE_CAR_APB_CFG_PRESETN_SWRSTN_LANE0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_lane_car_apb_cfg_presetn_swrstn_lane1_attr == SERDES_SHIM_WRAP_CAR_CFG_LANE_CAR_APB_CFG_PRESETN_SWRSTN_LANE1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_lane_car_apb_cfg_presetn_swrstn_lane2_attr == SERDES_SHIM_WRAP_CAR_CFG_LANE_CAR_APB_CFG_PRESETN_SWRSTN_LANE2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_lane_car_apb_cfg_presetn_swrstn_lane3_attr == SERDES_SHIM_WRAP_CAR_CFG_LANE_CAR_APB_CFG_PRESETN_SWRSTN_LANE3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.serdes_shim_wrap_car_cfg_wrap_car_apb_cfg_presetn_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_WRAP_CAR_APB_CFG_PRESETN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.top_f_fastest_reconfig_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.top_refclk_reconfig_span == TOP_REFCLK_RECONFIG_SPAN_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.top_syspll_refclk_output_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_0_rx_synth_select == UX0_0_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_0_tx_synth_select == UX0_0_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_1_rx_synth_select == UX0_1_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_1_tx_synth_select == UX0_1_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_2_rx_synth_select == UX0_2_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_2_tx_synth_select == UX0_2_TX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_3_rx_synth_select == UX0_3_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_3_tx_synth_select == UX0_3_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_4_rx_synth_select == UX0_4_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_4_tx_synth_select == UX0_4_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_0_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_0_hscount == 8'd181
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_0_m_counter_physical == 9'd194
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_0_meascount == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_0_mod_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_0_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_0_postdiv_counter_physical == 7'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_0_postdiv_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_0_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_0_refclk_type_select == UX0_CDR_0_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_0_watchdogtmr == 16'd1188
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_1_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_1_hscount == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_1_m_counter_physical == 9'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_1_meascount == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_1_mod_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_1_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_1_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_1_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_1_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_1_refclk_type_select == UX0_CDR_1_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_1_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_2_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_2_hscount == 8'd180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_2_m_counter_physical == 9'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_2_meascount == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_2_mod_counter == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_2_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_2_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_2_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_2_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_2_refclk_type_select == UX0_CDR_2_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_2_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_3_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_3_hscount == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_3_m_counter_physical == 9'd66
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_3_meascount == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_3_mod_counter == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_3_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_3_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_3_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_3_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_3_refclk_type_select == UX0_CDR_3_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_3_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_4_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_4_hscount == 8'd206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_4_m_counter_physical == 9'd210
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_4_meascount == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_4_mod_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_4_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_4_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_4_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_4_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_4_refclk_type_select == UX0_CDR_4_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_4_watchdogtmr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_bw_sel == UX0_CDR_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_f_mod_hz == 40'd990000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_f_out_hz == 40'd5940000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_f_pfd_hz == 40'd29700000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_f_postdiv_hz == 40'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_f_ref_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_f_vco_hz == 40'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_hscount_scratch == 40'd181
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_is_cascaded == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_is_fractional == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_l_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_l_counter_physical == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_m_counter == 9'd200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_meascount_scratch == 40'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_mod_counter_scratch == 40'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_postdiv_counter == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_ppm_driftcount == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_ppm_driftmax == 16'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_ppm_driftmax_scratch == 47'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_ppm_driftmax_scratch_denominator == 47'd1015257760000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_ppm_driftmax_scratch_numerator == 47'd31129600000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_ppm_tolerance == 16'd7600
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_refclk_mux_select == UX0_CDR_REFCLK_MUX_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_refclk_select == UX0_CDR_REFCLK_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_squelch_sample_count == 10'd144
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_squelch_sample_scratch == 40'd144
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cdr_watchdogtmr_scratch == 40'd1188
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cmn_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cmn_rx_cdr_refclk_mux_select == UX0_CMN_RX_CDR_REFCLK_MUX_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cmnrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cmnrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cmnrpu_evdn_delay_lut_entry3 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cmnrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cmnrpu_evup_delay_lut_entry2 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cmnrpu_evup_delay_lut_entry3 == 50'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cmnrpu_evup_delay_lut_entry4 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cmnrpu_evup_delay_lut_entry5 == 50'd62
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cmnrpu_evup_delay_lut_entry6 == 50'd390
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_cmnrpu_evup_delay_lut_entry7 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_core_pll == UX0_CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_core_pll_bw_sel == UX0_CORE_PLL_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_core_pll_refclk_select == UX0_CORE_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_dpma_f_out_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_dpma_n_counter == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_dpma_n_counter_physical == UX0_DPMA_N_COUNTER_PHYSICAL_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_dpma_n_counter_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_dpma_refclk_source == UX0_DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_dts_ssdiv_scratch == 40'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_duplex_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_enable_med_lc_0_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_enable_med_lc_1_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_enable_med_lc_2_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_enable_med_lc_3_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_enable_med_lc_4_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_enable_port_control_of_cdr_ltr_ltd == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_enable_slow_lc_0_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_enable_slow_lc_1_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_enable_slow_lc_2_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_enable_slow_lc_3_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_enable_slow_lc_4_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_ethernet_source == UX0_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_expose_pcie_gen1_gen6_critical_signals == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_f_cascade_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_feed_forward_gain_scratch == 47'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_feed_forward_temp_one == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_feed_forward_temp_two == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_flux_mode == UX0_FLUX_MODE_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_kvcc_settle_maxcnt_scratch == 40'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_lane_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_loopback_mode == UX0_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_master_sup_mode == UX0_MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_oversampling_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_primary_use == UX0_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_ref_clk_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_refclk_in_1us_scratch == 40'd148
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rx_ac_couple_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rx_adapt_mode == UX0_RX_ADAPT_MODE_STATIC_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rx_bond_size == UX0_RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rx_cal_dutymeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rx_datarate == 40'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rx_line_rate_bps == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rx_master_bond_chnl == UX0_RX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rx_o_clk_e2_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rx_o_clk_e4_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rx_o_usr_clk_e2_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rx_o_usr_clk_e4_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rx_onchip_termination == UX0_RX_ONCHIP_TERMINATION_R_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rx_over_sample == UX0_RX_OVER_SAMPLE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rx_protocol == UX0_RX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rx_term_mode_select == UX0_RX_TERM_MODE_SELECT_DIFFERENTIAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rx_tuning_hint == UX0_RX_TUNING_HINT_SDI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rx_user_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rx_which_lane_to_copy == UX0_RX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rx_width == UX0_RX_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxeq_ctle_bias_adj == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxeq_ctle_biasboost == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxeq_ctle_lf_gain == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxeq_ctle_midband_zero == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxeq_ctle_stage_1_dcgain == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxeq_ctle_stage_1_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxeq_ctle_stage_2_cap == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxeq_ctle_stage_2_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxeq_ctle_stage_2_reszero == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxeq_ctle_stage_3_dcgain == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxeq_ctle_stage_3_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxeq_dfe_data_tap_10 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxeq_dfe_data_tap_11 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxeq_dfe_data_tap_12 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxeq_dfe_data_tap_13 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxeq_dfe_data_tap_14 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxeq_dfe_data_tap_15 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxeq_dfe_data_tap_16 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxeq_dfe_data_tap_2 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxeq_dfe_data_tap_3 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxeq_dfe_data_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxeq_dfe_data_tap_5 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxeq_dfe_data_tap_6 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxeq_dfe_data_tap_7 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxeq_dfe_data_tap_8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxeq_dfe_data_tap_9 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxeq_dfe_edge_tap_2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxeq_dfe_edge_tap_3 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxeq_dfe_edge_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxeq_iq_clk == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxeq_targ_0_hi == 9'd160
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxeq_targ_0_lo == 9'd140
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxeq_vga_gain == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxratewidth_pd_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxrpu_evup_delay_lut_entry4 == 50'd78
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxrpu_evup_delay_lut_entry5 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxrpu_evup_delay_lut_entry6 == 50'd1406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_rxrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_select_lc_0_tx_path == UX0_SELECT_LC_0_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_select_lc_1_tx_path == UX0_SELECT_LC_1_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_select_lc_2_tx_path == UX0_SELECT_LC_2_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_select_lc_3_tx_path == UX0_SELECT_LC_3_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_select_lc_4_tx_path == UX0_SELECT_LC_4_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_sup_mode == UX0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_afc_range == UX0_SYNTH_LC_0_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_dtr_int_coeff == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_dtr_prop_coeff == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_f_max_vco_hz == 40'd12500000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_f_min_vco_hz == 40'd10500000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_f_out_hz == 40'd5940000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_f_pfd_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_f_ref_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_f_vco_hz == 40'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_fast_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_fast_tx_postdiv_counter == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_feed_forward_gain == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_fine_int_coeff == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_fine_int_coeff_tmp == 4'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_fine_prop_coeff == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_fine_prop_coeff_tmp == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_kvcc_settle_maxcnt == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_m_counter == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_med_f_tx_postdiv_hz == 40'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_med_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_med_tx_postdiv_counter == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_med_tx_postdiv_counter_physical == 7'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_med_tx_postdiv_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_refclk_in_1us == 8'd148
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_slow_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_slow_tx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_tdc_fine_res_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_tdc_target_count == 8'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_0_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_afc_range == UX0_SYNTH_LC_1_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_feed_forward_gain == 8'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_m_counter == 9'd90
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_1_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_afc_range == UX0_SYNTH_LC_2_AFC_RANGE_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_dtr_int_coeff == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_feed_forward_gain == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_m_counter == 9'd54
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_2_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_afc_range == UX0_SYNTH_LC_3_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_feed_forward_gain == 8'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_m_counter == 9'd72
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_3_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_afc_range == UX0_SYNTH_LC_4_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_afc_refclk_count == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_dtr_int_coeff == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_feed_forward_gain == 8'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_fine_int_coeff == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_kvcc_settle_maxcnt == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_m_counter == 9'd432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_med_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_refclk_in_1us == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_tdc_refclk_count == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_tdc_target_count == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_4_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_fast_bw_sel == UX0_SYNTH_LC_FAST_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_fast_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_fast_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_fast_primary_use == UX0_SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_fast_refclk_mux_select == UX0_SYNTH_LC_FAST_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_fast_refclk_type_select == UX0_SYNTH_LC_FAST_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_fast_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_fb_div_emb_mult_counter == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_fb_div_n_frac_mode == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_l_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_l_counter_physical == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_med_bw_sel == UX0_SYNTH_LC_MED_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_med_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_med_f_out_hz == 40'd5940000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_med_f_ref_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_med_f_tx_postdiv_hz == 40'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_med_f_vco_hz == 40'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_med_l_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_med_m_counter == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_med_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_med_primary_use == UX0_SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_med_refclk_mux_select == UX0_SYNTH_LC_MED_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_med_refclk_type_select == UX0_SYNTH_LC_MED_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_med_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_med_tx_postdiv_counter == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_med_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_slow_bw_sel == UX0_SYNTH_LC_SLOW_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_slow_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_slow_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_slow_primary_use == UX0_SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_slow_refclk_mux_select == UX0_SYNTH_LC_SLOW_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_slow_refclk_type_select == UX0_SYNTH_LC_SLOW_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synth_lc_slow_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlc_0_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlc_0_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlc_0_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlc_0_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlc_1_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlc_1_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlc_1_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlc_1_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlc_2_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlc_2_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlc_2_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlc_2_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlc_3_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlc_3_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlc_3_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlc_3_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlc_4_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlc_4_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlc_4_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlc_4_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlc_dcdmeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlcfastratewidth_pd_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlcfastrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlcfastrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlcfastrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlcfastrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlcfastrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlcfastrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlcfastrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlcfastrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlcfastrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlcfastrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlcfastrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlcmedrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlcmedrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlcmedrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlcmedrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlcmedrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlcmedrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlcmedrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlcmedrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlcmedrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlcmedrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlcslowrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlcslowrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlcslowrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlcslowrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlcslowrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlcslowrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlcslowrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlcslowrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlcslowrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_synthlcslowrpu_evup_delay_lut_entry7 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tdc_refclk_count_divisor == 40'd850000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tdc_refclk_count_scratch == 40'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tdc_target_count_scratch == 40'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tx_bond_size == UX0_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tx_cal_dutymeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tx_datarate == 40'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tx_i_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tx_i_clk_e4_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tx_i_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tx_line_rate_bps == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tx_master_bond_chnl == UX0_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tx_o_clk_e2_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tx_o_clk_e4_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tx_o_usr_clk_1_e2_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tx_o_usr_clk_1_e4_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tx_o_usr_clk_2_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tx_over_sample == UX0_TX_OVER_SAMPLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tx_pll == UX0_TX_PLL_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tx_pll_bw_sel == UX0_TX_PLL_BW_SEL_MEDIUM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tx_pll_is_downstream_pll == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tx_pll_refclk_mux_select == UX0_TX_PLL_REFCLK_MUX_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tx_pll_refclk_select == UX0_TX_PLL_REFCLK_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tx_protocol == UX0_TX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tx_tuning_hint == UX0_TX_TUNING_HINT_SDI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tx_user_clk1_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tx_user_clk1_mux == UX0_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tx_user_clk2_mux == UX0_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tx_user_clk_slow_med_mux == UX0_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tx_which_lane_to_copy == UX0_TX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_tx_width == UX0_TX_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_txeq_main_tap == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_txratewidth_rst_b0_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_txrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_txrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_txrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_txrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_txrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_txrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_txrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_txrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_txrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_txrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_txrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_txrx_channel_operation == UX0_TXRX_CHANNEL_OPERATION_DUAL_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_txrx_line_encoding_type == UX0_TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_txrx_xcvr_speed_bucket == UX0_TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux0_vreg_loopen_maxcnt_scratch == 40'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_0_rx_synth_select == UX1_0_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_0_tx_synth_select == UX1_0_TX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_1_rx_synth_select == UX1_1_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_1_tx_synth_select == UX1_1_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_2_rx_synth_select == UX1_2_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_2_tx_synth_select == UX1_2_TX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_3_rx_synth_select == UX1_3_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_3_tx_synth_select == UX1_3_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_4_rx_synth_select == UX1_4_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_4_tx_synth_select == UX1_4_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_0_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_0_hscount == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_0_m_counter_physical == 9'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_0_meascount == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_0_mod_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_0_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_0_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_0_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_0_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_0_refclk_type_select == UX1_CDR_0_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_0_watchdogtmr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_1_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_1_hscount == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_1_m_counter_physical == 9'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_1_meascount == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_1_mod_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_1_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_1_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_1_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_1_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_1_refclk_type_select == UX1_CDR_1_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_1_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_2_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_2_hscount == 8'd180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_2_m_counter_physical == 9'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_2_meascount == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_2_mod_counter == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_2_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_2_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_2_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_2_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_2_refclk_type_select == UX1_CDR_2_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_2_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_3_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_3_hscount == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_3_m_counter_physical == 9'd66
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_3_meascount == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_3_mod_counter == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_3_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_3_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_3_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_3_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_3_refclk_type_select == UX1_CDR_3_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_3_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_4_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_4_hscount == 8'd206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_4_m_counter_physical == 9'd210
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_4_meascount == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_4_mod_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_4_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_4_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_4_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_4_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_4_refclk_type_select == UX1_CDR_4_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_4_watchdogtmr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_bw_sel == UX1_CDR_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_f_mod_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_f_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_hscount_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_is_cascaded == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_is_fractional == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_l_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_l_counter_physical == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_m_counter == 9'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_meascount_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_mod_counter_scratch == 40'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_ppm_driftcount == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_ppm_driftmax == 16'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_ppm_driftmax_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_ppm_driftmax_scratch_denominator == 47'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_ppm_driftmax_scratch_numerator == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_ppm_tolerance == 16'd7600
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_refclk_mux_select == UX1_CDR_REFCLK_MUX_SELECT_REGIONAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_refclk_select == UX1_CDR_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_squelch_sample_count == 10'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_squelch_sample_scratch == 40'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cdr_watchdogtmr_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cmn_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cmn_rx_cdr_refclk_mux_select == UX1_CMN_RX_CDR_REFCLK_MUX_SELECT_REGIONAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cmnrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cmnrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cmnrpu_evdn_delay_lut_entry3 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cmnrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cmnrpu_evup_delay_lut_entry2 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cmnrpu_evup_delay_lut_entry3 == 50'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cmnrpu_evup_delay_lut_entry4 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cmnrpu_evup_delay_lut_entry5 == 50'd62
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cmnrpu_evup_delay_lut_entry6 == 50'd390
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_cmnrpu_evup_delay_lut_entry7 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_core_pll == UX1_CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_core_pll_bw_sel == UX1_CORE_PLL_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_core_pll_refclk_select == UX1_CORE_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_dpma_f_out_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_dpma_n_counter == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_dpma_n_counter_physical == UX1_DPMA_N_COUNTER_PHYSICAL_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_dpma_n_counter_scratch == 40'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_dpma_refclk_source == UX1_DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_dts_ssdiv_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_duplex_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_enable_med_lc_0_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_enable_med_lc_1_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_enable_med_lc_2_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_enable_med_lc_3_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_enable_med_lc_4_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_enable_port_control_of_cdr_ltr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_enable_slow_lc_0_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_enable_slow_lc_1_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_enable_slow_lc_2_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_enable_slow_lc_3_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_enable_slow_lc_4_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_ethernet_source == UX1_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_expose_pcie_gen1_gen6_critical_signals == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_f_cascade_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_feed_forward_gain_scratch == 47'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_feed_forward_temp_one == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_feed_forward_temp_two == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_flux_mode == UX1_FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_kvcc_settle_maxcnt_scratch == 40'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_lane_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_loopback_mode == UX1_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_master_sup_mode == UX1_MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_oversampling_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_primary_use == UX1_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_ref_clk_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_refclk_in_1us_scratch == 40'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rx_adapt_mode == UX1_RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rx_bond_size == UX1_RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rx_cal_dutymeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rx_master_bond_chnl == UX1_RX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rx_o_usr_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rx_o_usr_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rx_onchip_termination == UX1_RX_ONCHIP_TERMINATION_R_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rx_over_sample == UX1_RX_OVER_SAMPLE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rx_protocol == UX1_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rx_term_mode_select == UX1_RX_TERM_MODE_SELECT_GROUNDED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rx_tuning_hint == UX1_RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rx_which_lane_to_copy == UX1_RX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rx_width == UX1_RX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxeq_ctle_bias_adj == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxeq_ctle_biasboost == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxeq_ctle_lf_gain == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxeq_ctle_midband_zero == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxeq_ctle_stage_1_dcgain == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxeq_ctle_stage_1_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxeq_ctle_stage_2_cap == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxeq_ctle_stage_2_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxeq_ctle_stage_2_reszero == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxeq_ctle_stage_3_dcgain == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxeq_ctle_stage_3_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxeq_dfe_data_tap_10 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxeq_dfe_data_tap_11 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxeq_dfe_data_tap_12 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxeq_dfe_data_tap_13 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxeq_dfe_data_tap_14 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxeq_dfe_data_tap_15 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxeq_dfe_data_tap_16 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxeq_dfe_data_tap_2 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxeq_dfe_data_tap_3 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxeq_dfe_data_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxeq_dfe_data_tap_5 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxeq_dfe_data_tap_6 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxeq_dfe_data_tap_7 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxeq_dfe_data_tap_8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxeq_dfe_data_tap_9 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxeq_dfe_edge_tap_2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxeq_dfe_edge_tap_3 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxeq_dfe_edge_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxeq_iq_clk == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxeq_targ_0_hi == 9'd149
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxeq_targ_0_lo == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxeq_vga_gain == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxratewidth_pd_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxrpu_evup_delay_lut_entry2 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxrpu_evup_delay_lut_entry4 == 50'd78
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxrpu_evup_delay_lut_entry5 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxrpu_evup_delay_lut_entry6 == 50'd1406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_rxrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_select_lc_0_tx_path == UX1_SELECT_LC_0_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_select_lc_1_tx_path == UX1_SELECT_LC_1_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_select_lc_2_tx_path == UX1_SELECT_LC_2_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_select_lc_3_tx_path == UX1_SELECT_LC_3_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_select_lc_4_tx_path == UX1_SELECT_LC_4_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_sup_mode == UX1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_afc_range == UX1_SYNTH_LC_0_AFC_RANGE_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_afc_refclk_count == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_dtr_prop_coeff == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_f_max_vco_hz == 40'd10500000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_f_min_vco_hz == 40'd8000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_fast_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_fast_tx_postdiv_counter == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_feed_forward_gain == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_fine_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_fine_int_coeff_tmp == 4'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_fine_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_fine_prop_coeff_tmp == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_kvcc_settle_maxcnt == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_m_counter == 9'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_med_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_med_tx_postdiv_counter == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_refclk_in_1us == 8'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_slow_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_slow_tx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_tdc_fine_res_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_tdc_target_count == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_0_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_afc_range == UX1_SYNTH_LC_1_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_feed_forward_gain == 8'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_m_counter == 9'd45
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_1_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_afc_range == UX1_SYNTH_LC_2_AFC_RANGE_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_dtr_int_coeff == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_feed_forward_gain == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_m_counter == 9'd27
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_2_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_afc_range == UX1_SYNTH_LC_3_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_feed_forward_gain == 8'd23
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_m_counter == 9'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_3_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_afc_range == UX1_SYNTH_LC_4_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_afc_refclk_count == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_dtr_int_coeff == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_feed_forward_gain == 8'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_fine_int_coeff == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_kvcc_settle_maxcnt == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_m_counter == 9'd216
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_med_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_refclk_in_1us == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_tdc_refclk_count == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_tdc_target_count == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_4_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_fast_bw_sel == UX1_SYNTH_LC_FAST_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_fast_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_fast_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_fast_primary_use == UX1_SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_fast_refclk_mux_select == UX1_SYNTH_LC_FAST_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_fast_refclk_type_select == UX1_SYNTH_LC_FAST_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_fast_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_fb_div_emb_mult_counter == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_l_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_l_counter_physical == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_med_bw_sel == UX1_SYNTH_LC_MED_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_med_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_med_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_med_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_med_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_med_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_med_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_med_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_med_primary_use == UX1_SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_med_refclk_mux_select == UX1_SYNTH_LC_MED_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_med_refclk_type_select == UX1_SYNTH_LC_MED_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_med_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_slow_bw_sel == UX1_SYNTH_LC_SLOW_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_slow_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_slow_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_slow_primary_use == UX1_SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_slow_refclk_mux_select == UX1_SYNTH_LC_SLOW_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_slow_refclk_type_select == UX1_SYNTH_LC_SLOW_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synth_lc_slow_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlc_0_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlc_0_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlc_0_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlc_0_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlc_1_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlc_1_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlc_1_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlc_1_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlc_2_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlc_2_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlc_2_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlc_2_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlc_3_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlc_3_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlc_3_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlc_3_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlc_4_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlc_4_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlc_4_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlc_4_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlc_dcdmeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlcfastratewidth_pd_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlcfastrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlcfastrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlcfastrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlcfastrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlcfastrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlcfastrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlcfastrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlcfastrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlcfastrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlcfastrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlcfastrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlcmedrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlcmedrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlcmedrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlcmedrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlcmedrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlcmedrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlcmedrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlcmedrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlcmedrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlcmedrpu_evup_delay_lut_entry7 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlcslowrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlcslowrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlcslowrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlcslowrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlcslowrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlcslowrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlcslowrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlcslowrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlcslowrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_synthlcslowrpu_evup_delay_lut_entry7 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tdc_refclk_count_divisor == 40'd850000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tdc_refclk_count_scratch == 40'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tdc_target_count_scratch == 40'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tx_bond_size == UX1_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tx_cal_dutymeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tx_i_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tx_i_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tx_i_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tx_master_bond_chnl == UX1_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tx_o_usr_clk_1_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tx_o_usr_clk_1_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tx_o_usr_clk_2_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tx_over_sample == UX1_TX_OVER_SAMPLE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tx_pll == UX1_TX_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tx_pll_bw_sel == UX1_TX_PLL_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tx_pll_is_downstream_pll == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tx_pll_refclk_mux_select == UX1_TX_PLL_REFCLK_MUX_SELECT_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tx_pll_refclk_select == UX1_TX_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tx_protocol == UX1_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tx_tuning_hint == UX1_TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tx_user_clk1_mux == UX1_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tx_user_clk2_mux == UX1_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tx_user_clk_slow_med_mux == UX1_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tx_which_lane_to_copy == UX1_TX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_tx_width == UX1_TX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_txeq_main_tap == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_txratewidth_rst_b0_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_txrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_txrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_txrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_txrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_txrpu_evup_delay_lut_entry2 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_txrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_txrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_txrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_txrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_txrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_txrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_txrx_channel_operation == UX1_TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_txrx_line_encoding_type == UX1_TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_txrx_xcvr_speed_bucket == UX1_TXRX_XCVR_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux1_vreg_loopen_maxcnt_scratch == 40'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_0_rx_synth_select == UX2_0_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_0_tx_synth_select == UX2_0_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_1_rx_synth_select == UX2_1_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_1_tx_synth_select == UX2_1_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_2_rx_synth_select == UX2_2_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_2_tx_synth_select == UX2_2_TX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_3_rx_synth_select == UX2_3_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_3_tx_synth_select == UX2_3_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_4_rx_synth_select == UX2_4_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_4_tx_synth_select == UX2_4_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_0_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_0_hscount == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_0_m_counter_physical == 9'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_0_meascount == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_0_mod_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_0_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_0_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_0_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_0_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_0_refclk_type_select == UX2_CDR_0_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_0_watchdogtmr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_1_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_1_hscount == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_1_m_counter_physical == 9'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_1_meascount == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_1_mod_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_1_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_1_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_1_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_1_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_1_refclk_type_select == UX2_CDR_1_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_1_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_2_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_2_hscount == 8'd180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_2_m_counter_physical == 9'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_2_meascount == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_2_mod_counter == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_2_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_2_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_2_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_2_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_2_refclk_type_select == UX2_CDR_2_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_2_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_3_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_3_hscount == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_3_m_counter_physical == 9'd66
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_3_meascount == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_3_mod_counter == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_3_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_3_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_3_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_3_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_3_refclk_type_select == UX2_CDR_3_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_3_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_4_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_4_hscount == 8'd206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_4_m_counter_physical == 9'd210
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_4_meascount == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_4_mod_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_4_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_4_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_4_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_4_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_4_refclk_type_select == UX2_CDR_4_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_4_watchdogtmr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_bw_sel == UX2_CDR_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_f_mod_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_f_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_hscount_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_is_cascaded == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_is_fractional == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_l_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_l_counter_physical == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_m_counter == 9'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_meascount_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_mod_counter_scratch == 40'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_ppm_driftcount == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_ppm_driftmax == 16'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_ppm_driftmax_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_ppm_driftmax_scratch_denominator == 47'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_ppm_driftmax_scratch_numerator == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_ppm_tolerance == 16'd7600
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_refclk_mux_select == UX2_CDR_REFCLK_MUX_SELECT_REGIONAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_refclk_select == UX2_CDR_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_squelch_sample_count == 10'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_squelch_sample_scratch == 40'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cdr_watchdogtmr_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cmn_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cmn_rx_cdr_refclk_mux_select == UX2_CMN_RX_CDR_REFCLK_MUX_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cmnrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cmnrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cmnrpu_evdn_delay_lut_entry3 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cmnrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cmnrpu_evup_delay_lut_entry2 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cmnrpu_evup_delay_lut_entry3 == 50'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cmnrpu_evup_delay_lut_entry4 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cmnrpu_evup_delay_lut_entry5 == 50'd62
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cmnrpu_evup_delay_lut_entry6 == 50'd390
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_cmnrpu_evup_delay_lut_entry7 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_core_pll == UX2_CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_core_pll_bw_sel == UX2_CORE_PLL_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_core_pll_refclk_select == UX2_CORE_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_dpma_f_out_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_dpma_n_counter == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_dpma_n_counter_physical == UX2_DPMA_N_COUNTER_PHYSICAL_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_dpma_n_counter_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_dpma_refclk_source == UX2_DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_dts_ssdiv_scratch == 40'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_duplex_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_enable_med_lc_0_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_enable_med_lc_1_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_enable_med_lc_2_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_enable_med_lc_3_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_enable_med_lc_4_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_enable_port_control_of_cdr_ltr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_enable_slow_lc_0_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_enable_slow_lc_1_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_enable_slow_lc_2_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_enable_slow_lc_3_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_enable_slow_lc_4_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_ethernet_source == UX2_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_expose_pcie_gen1_gen6_critical_signals == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_f_cascade_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_feed_forward_gain_scratch == 47'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_feed_forward_temp_one == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_feed_forward_temp_two == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_flux_mode == UX2_FLUX_MODE_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_kvcc_settle_maxcnt_scratch == 40'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_lane_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_loopback_mode == UX2_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_master_sup_mode == UX2_MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_oversampling_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_prbs_mon_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_primary_use == UX2_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_ref_clk_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_refclk_in_1us_scratch == 40'd148
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rx_adapt_mode == UX2_RX_ADAPT_MODE_STATIC_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rx_bond_size == UX2_RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rx_cal_dutymeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rx_master_bond_chnl == UX2_RX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rx_o_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rx_o_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rx_o_usr_clk_e2_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rx_o_usr_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rx_onchip_termination == UX2_RX_ONCHIP_TERMINATION_R_4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rx_over_sample == UX2_RX_OVER_SAMPLE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rx_protocol == UX2_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rx_protocol_hard_pcie_lowloss == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rx_term_mode_select == UX2_RX_TERM_MODE_SELECT_GROUNDED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rx_tuning_hint == UX2_RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rx_user_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rx_which_lane_to_copy == UX2_RX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rx_width == UX2_RX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxeq_ctle_bias_adj == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxeq_ctle_biasboost == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxeq_ctle_lf_gain == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxeq_ctle_midband_zero == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxeq_ctle_stage_1_dcgain == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxeq_ctle_stage_1_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxeq_ctle_stage_2_cap == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxeq_ctle_stage_2_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxeq_ctle_stage_2_reszero == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxeq_ctle_stage_3_dcgain == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxeq_ctle_stage_3_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxeq_dfe_data_tap_10 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxeq_dfe_data_tap_11 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxeq_dfe_data_tap_12 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxeq_dfe_data_tap_13 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxeq_dfe_data_tap_14 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxeq_dfe_data_tap_15 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxeq_dfe_data_tap_16 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxeq_dfe_data_tap_2 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxeq_dfe_data_tap_3 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxeq_dfe_data_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxeq_dfe_data_tap_5 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxeq_dfe_data_tap_6 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxeq_dfe_data_tap_7 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxeq_dfe_data_tap_8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxeq_dfe_data_tap_9 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxeq_dfe_edge_tap_2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxeq_dfe_edge_tap_3 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxeq_dfe_edge_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxeq_iq_clk == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxeq_targ_0_hi == 9'd130
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxeq_targ_0_lo == 9'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxeq_vga_gain == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxratewidth_pd_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxrpu_evup_delay_lut_entry4 == 50'd78
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxrpu_evup_delay_lut_entry5 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxrpu_evup_delay_lut_entry6 == 50'd1406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_rxrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_select_lc_0_tx_path == UX2_SELECT_LC_0_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_select_lc_1_tx_path == UX2_SELECT_LC_1_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_select_lc_2_tx_path == UX2_SELECT_LC_2_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_select_lc_3_tx_path == UX2_SELECT_LC_3_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_select_lc_4_tx_path == UX2_SELECT_LC_4_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_squelch_detect == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_sup_mode == UX2_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_afc_range == UX2_SYNTH_LC_0_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_dtr_int_coeff == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_dtr_prop_coeff == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_f_max_vco_hz == 40'd12500000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_f_min_vco_hz == 40'd10500000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_f_out_hz == 40'd5940000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_f_pfd_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_f_ref_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_f_vco_hz == 40'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_fast_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_fast_tx_postdiv_counter == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_feed_forward_gain == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_fine_int_coeff == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_fine_int_coeff_tmp == 4'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_fine_prop_coeff == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_fine_prop_coeff_tmp == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_kvcc_settle_maxcnt == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_m_counter == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_med_f_tx_postdiv_hz == 40'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_med_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_med_tx_postdiv_counter == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_med_tx_postdiv_counter_physical == 7'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_med_tx_postdiv_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_refclk_in_1us == 8'd148
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_slow_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_slow_tx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_tdc_fine_res_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_tdc_target_count == 8'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_0_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_afc_range == UX2_SYNTH_LC_1_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_feed_forward_gain == 8'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_m_counter == 9'd90
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_1_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_afc_range == UX2_SYNTH_LC_2_AFC_RANGE_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_dtr_int_coeff == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_feed_forward_gain == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_m_counter == 9'd54
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_2_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_afc_range == UX2_SYNTH_LC_3_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_feed_forward_gain == 8'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_m_counter == 9'd72
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_3_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_afc_range == UX2_SYNTH_LC_4_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_afc_refclk_count == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_dtr_int_coeff == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_feed_forward_gain == 8'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_fine_int_coeff == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_kvcc_settle_maxcnt == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_m_counter == 9'd432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_med_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_refclk_in_1us == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_tdc_refclk_count == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_tdc_target_count == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_4_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_fast_bw_sel == UX2_SYNTH_LC_FAST_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_fast_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_fast_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_fast_primary_use == UX2_SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_fast_refclk_mux_select == UX2_SYNTH_LC_FAST_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_fast_refclk_type_select == UX2_SYNTH_LC_FAST_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_fast_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_fb_div_emb_mult_counter == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_fb_div_n_frac_mode == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_l_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_l_counter_physical == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_med_bw_sel == UX2_SYNTH_LC_MED_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_med_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_med_f_out_hz == 40'd5940000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_med_f_ref_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_med_f_tx_postdiv_hz == 40'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_med_f_vco_hz == 40'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_med_l_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_med_m_counter == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_med_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_med_primary_use == UX2_SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_med_refclk_mux_select == UX2_SYNTH_LC_MED_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_med_refclk_type_select == UX2_SYNTH_LC_MED_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_med_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_med_tx_postdiv_counter == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_med_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_slow_bw_sel == UX2_SYNTH_LC_SLOW_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_slow_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_slow_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_slow_primary_use == UX2_SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_slow_refclk_mux_select == UX2_SYNTH_LC_SLOW_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_slow_refclk_type_select == UX2_SYNTH_LC_SLOW_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synth_lc_slow_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlc_0_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlc_0_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlc_0_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlc_0_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlc_1_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlc_1_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlc_1_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlc_1_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlc_2_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlc_2_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlc_2_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlc_2_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlc_3_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlc_3_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlc_3_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlc_3_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlc_4_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlc_4_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlc_4_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlc_4_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlc_dcdmeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlcfastratewidth_pd_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlcfastrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlcfastrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlcfastrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlcfastrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlcfastrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlcfastrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlcfastrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlcfastrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlcfastrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlcfastrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlcfastrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlcmedrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlcmedrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlcmedrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlcmedrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlcmedrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlcmedrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlcmedrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlcmedrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlcmedrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlcmedrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlcslowrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlcslowrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlcslowrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlcslowrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlcslowrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlcslowrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlcslowrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlcslowrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlcslowrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_synthlcslowrpu_evup_delay_lut_entry7 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tdc_refclk_count_divisor == 40'd850000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tdc_refclk_count_scratch == 40'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tdc_target_count_scratch == 40'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tx_bond_size == UX2_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tx_cal_dutymeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tx_datarate == 40'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tx_i_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tx_i_clk_e4_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tx_i_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tx_line_rate_bps == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tx_master_bond_chnl == UX2_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tx_o_clk_e2_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tx_o_clk_e4_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tx_o_usr_clk_1_e2_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tx_o_usr_clk_1_e4_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tx_o_usr_clk_2_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tx_over_sample == UX2_TX_OVER_SAMPLE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tx_pll == UX2_TX_PLL_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tx_pll_bw_sel == UX2_TX_PLL_BW_SEL_MEDIUM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tx_pll_is_downstream_pll == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tx_pll_refclk_mux_select == UX2_TX_PLL_REFCLK_MUX_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tx_pll_refclk_select == UX2_TX_PLL_REFCLK_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tx_protocol == UX2_TX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tx_tuning_hint == UX2_TX_TUNING_HINT_SDI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tx_user_clk1_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tx_user_clk1_mux == UX2_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tx_user_clk2_mux == UX2_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tx_user_clk_slow_med_mux == UX2_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tx_which_lane_to_copy == UX2_TX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_tx_width == UX2_TX_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_txeq_main_tap == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_txratewidth_rst_b0_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_txrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_txrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_txrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_txrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_txrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_txrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_txrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_txrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_txrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_txrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_txrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_txrx_channel_operation == UX2_TXRX_CHANNEL_OPERATION_DUAL_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_txrx_line_encoding_type == UX2_TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_txrx_xcvr_speed_bucket == UX2_TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux2_vreg_loopen_maxcnt_scratch == 40'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_0_rx_synth_select == UX3_0_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_0_tx_synth_select == UX3_0_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_1_rx_synth_select == UX3_1_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_1_tx_synth_select == UX3_1_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_2_rx_synth_select == UX3_2_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_2_tx_synth_select == UX3_2_TX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_3_rx_synth_select == UX3_3_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_3_tx_synth_select == UX3_3_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_4_rx_synth_select == UX3_4_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_4_tx_synth_select == UX3_4_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_0_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_0_hscount == 8'd181
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_0_m_counter_physical == 9'd194
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_0_meascount == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_0_mod_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_0_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_0_postdiv_counter_physical == 7'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_0_postdiv_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_0_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_0_refclk_type_select == UX3_CDR_0_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_0_watchdogtmr == 16'd1188
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_1_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_1_hscount == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_1_m_counter_physical == 9'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_1_meascount == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_1_mod_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_1_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_1_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_1_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_1_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_1_refclk_type_select == UX3_CDR_1_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_1_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_2_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_2_hscount == 8'd180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_2_m_counter_physical == 9'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_2_meascount == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_2_mod_counter == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_2_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_2_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_2_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_2_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_2_refclk_type_select == UX3_CDR_2_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_2_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_3_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_3_hscount == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_3_m_counter_physical == 9'd66
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_3_meascount == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_3_mod_counter == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_3_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_3_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_3_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_3_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_3_refclk_type_select == UX3_CDR_3_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_3_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_4_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_4_hscount == 8'd206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_4_m_counter_physical == 9'd210
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_4_meascount == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_4_mod_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_4_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_4_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_4_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_4_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_4_refclk_type_select == UX3_CDR_4_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_4_watchdogtmr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_bw_sel == UX3_CDR_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_f_mod_hz == 40'd990000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_f_out_hz == 40'd5940000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_f_pfd_hz == 40'd29700000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_f_postdiv_hz == 40'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_f_ref_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_f_vco_hz == 40'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_hscount_scratch == 40'd181
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_is_cascaded == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_is_fractional == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_l_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_l_counter_physical == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_m_counter == 9'd200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_meascount_scratch == 40'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_mod_counter_scratch == 40'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_postdiv_counter == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_ppm_driftcount == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_ppm_driftmax == 16'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_ppm_driftmax_scratch == 47'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_ppm_driftmax_scratch_denominator == 47'd1015257760000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_ppm_driftmax_scratch_numerator == 47'd31129600000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_ppm_tolerance == 16'd7600
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_refclk_mux_select == UX3_CDR_REFCLK_MUX_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_refclk_select == UX3_CDR_REFCLK_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_squelch_sample_count == 10'd144
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_squelch_sample_scratch == 40'd144
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cdr_watchdogtmr_scratch == 40'd1188
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cmn_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cmn_rx_cdr_refclk_mux_select == UX3_CMN_RX_CDR_REFCLK_MUX_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cmnrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cmnrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cmnrpu_evdn_delay_lut_entry3 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cmnrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cmnrpu_evup_delay_lut_entry2 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cmnrpu_evup_delay_lut_entry3 == 50'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cmnrpu_evup_delay_lut_entry4 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cmnrpu_evup_delay_lut_entry5 == 50'd62
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cmnrpu_evup_delay_lut_entry6 == 50'd390
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_cmnrpu_evup_delay_lut_entry7 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_core_pll == UX3_CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_core_pll_bw_sel == UX3_CORE_PLL_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_core_pll_refclk_select == UX3_CORE_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_dpma_f_out_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_dpma_n_counter == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_dpma_n_counter_physical == UX3_DPMA_N_COUNTER_PHYSICAL_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_dpma_n_counter_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_dpma_refclk_source == UX3_DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_dts_ssdiv_scratch == 40'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_duplex_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_enable_med_lc_0_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_enable_med_lc_1_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_enable_med_lc_2_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_enable_med_lc_3_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_enable_med_lc_4_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_enable_port_control_of_cdr_ltr_ltd == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_enable_slow_lc_0_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_enable_slow_lc_1_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_enable_slow_lc_2_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_enable_slow_lc_3_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_enable_slow_lc_4_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_ethernet_source == UX3_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_expose_pcie_gen1_gen6_critical_signals == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_f_cascade_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_feed_forward_gain_scratch == 47'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_feed_forward_temp_one == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_feed_forward_temp_two == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_flux_mode == UX3_FLUX_MODE_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_kvcc_settle_maxcnt_scratch == 40'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_lane_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_loopback_mode == UX3_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_master_sup_mode == UX3_MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_oversampling_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_primary_use == UX3_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_ref_clk_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_refclk_in_1us_scratch == 40'd148
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rx_ac_couple_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rx_adapt_mode == UX3_RX_ADAPT_MODE_STATIC_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rx_bond_size == UX3_RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rx_cal_dutymeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rx_datarate == 40'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rx_line_rate_bps == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rx_master_bond_chnl == UX3_RX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rx_o_clk_e2_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rx_o_clk_e4_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rx_o_usr_clk_e2_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rx_o_usr_clk_e4_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rx_onchip_termination == UX3_RX_ONCHIP_TERMINATION_R_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rx_over_sample == UX3_RX_OVER_SAMPLE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rx_protocol == UX3_RX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rx_term_mode_select == UX3_RX_TERM_MODE_SELECT_DIFFERENTIAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rx_tuning_hint == UX3_RX_TUNING_HINT_SDI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rx_user_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rx_which_lane_to_copy == UX3_RX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rx_width == UX3_RX_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxeq_ctle_bias_adj == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxeq_ctle_biasboost == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxeq_ctle_lf_gain == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxeq_ctle_midband_zero == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxeq_ctle_stage_1_dcgain == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxeq_ctle_stage_1_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxeq_ctle_stage_2_cap == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxeq_ctle_stage_2_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxeq_ctle_stage_2_reszero == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxeq_ctle_stage_3_dcgain == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxeq_ctle_stage_3_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxeq_dfe_data_tap_10 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxeq_dfe_data_tap_11 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxeq_dfe_data_tap_12 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxeq_dfe_data_tap_13 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxeq_dfe_data_tap_14 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxeq_dfe_data_tap_15 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxeq_dfe_data_tap_16 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxeq_dfe_data_tap_2 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxeq_dfe_data_tap_3 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxeq_dfe_data_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxeq_dfe_data_tap_5 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxeq_dfe_data_tap_6 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxeq_dfe_data_tap_7 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxeq_dfe_data_tap_8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxeq_dfe_data_tap_9 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxeq_dfe_edge_tap_2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxeq_dfe_edge_tap_3 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxeq_dfe_edge_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxeq_iq_clk == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxeq_targ_0_hi == 9'd160
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxeq_targ_0_lo == 9'd140
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxeq_vga_gain == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxratewidth_pd_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxrpu_evup_delay_lut_entry4 == 50'd78
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxrpu_evup_delay_lut_entry5 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxrpu_evup_delay_lut_entry6 == 50'd1406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_rxrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_select_lc_0_tx_path == UX3_SELECT_LC_0_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_select_lc_1_tx_path == UX3_SELECT_LC_1_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_select_lc_2_tx_path == UX3_SELECT_LC_2_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_select_lc_3_tx_path == UX3_SELECT_LC_3_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_select_lc_4_tx_path == UX3_SELECT_LC_4_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_sup_mode == UX3_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_afc_range == UX3_SYNTH_LC_0_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_dtr_int_coeff == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_dtr_prop_coeff == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_f_max_vco_hz == 40'd12500000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_f_min_vco_hz == 40'd10500000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_f_out_hz == 40'd5940000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_f_pfd_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_f_ref_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_f_vco_hz == 40'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_fast_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_fast_tx_postdiv_counter == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_feed_forward_gain == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_fine_int_coeff == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_fine_int_coeff_tmp == 4'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_fine_prop_coeff == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_fine_prop_coeff_tmp == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_kvcc_settle_maxcnt == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_m_counter == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_med_f_tx_postdiv_hz == 40'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_med_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_med_tx_postdiv_counter == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_med_tx_postdiv_counter_physical == 7'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_med_tx_postdiv_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_refclk_in_1us == 8'd148
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_slow_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_slow_tx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_tdc_fine_res_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_tdc_target_count == 8'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_0_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_afc_range == UX3_SYNTH_LC_1_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_feed_forward_gain == 8'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_m_counter == 9'd90
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_1_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_afc_range == UX3_SYNTH_LC_2_AFC_RANGE_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_dtr_int_coeff == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_feed_forward_gain == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_m_counter == 9'd54
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_2_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_afc_range == UX3_SYNTH_LC_3_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_feed_forward_gain == 8'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_m_counter == 9'd72
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_3_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_afc_range == UX3_SYNTH_LC_4_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_afc_refclk_count == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_dtr_int_coeff == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_feed_forward_gain == 8'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_fine_int_coeff == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_kvcc_settle_maxcnt == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_m_counter == 9'd432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_med_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_refclk_in_1us == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_tdc_refclk_count == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_tdc_target_count == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_4_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_fast_bw_sel == UX3_SYNTH_LC_FAST_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_fast_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_fast_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_fast_primary_use == UX3_SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_fast_refclk_mux_select == UX3_SYNTH_LC_FAST_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_fast_refclk_type_select == UX3_SYNTH_LC_FAST_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_fast_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_fb_div_emb_mult_counter == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_fb_div_n_frac_mode == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_l_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_l_counter_physical == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_med_bw_sel == UX3_SYNTH_LC_MED_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_med_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_med_f_out_hz == 40'd5940000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_med_f_ref_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_med_f_tx_postdiv_hz == 40'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_med_f_vco_hz == 40'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_med_l_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_med_m_counter == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_med_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_med_primary_use == UX3_SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_med_refclk_mux_select == UX3_SYNTH_LC_MED_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_med_refclk_type_select == UX3_SYNTH_LC_MED_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_med_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_med_tx_postdiv_counter == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_med_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_slow_bw_sel == UX3_SYNTH_LC_SLOW_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_slow_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_slow_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_slow_primary_use == UX3_SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_slow_refclk_mux_select == UX3_SYNTH_LC_SLOW_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_slow_refclk_type_select == UX3_SYNTH_LC_SLOW_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synth_lc_slow_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlc_0_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlc_0_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlc_0_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlc_0_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlc_1_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlc_1_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlc_1_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlc_1_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlc_2_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlc_2_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlc_2_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlc_2_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlc_3_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlc_3_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlc_3_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlc_3_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlc_4_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlc_4_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlc_4_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlc_4_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlc_dcdmeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlcfastratewidth_pd_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlcfastrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlcfastrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlcfastrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlcfastrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlcfastrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlcfastrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlcfastrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlcfastrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlcfastrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlcfastrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlcfastrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlcmedrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlcmedrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlcmedrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlcmedrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlcmedrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlcmedrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlcmedrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlcmedrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlcmedrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlcmedrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlcslowrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlcslowrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlcslowrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlcslowrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlcslowrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlcslowrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlcslowrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlcslowrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlcslowrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_synthlcslowrpu_evup_delay_lut_entry7 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tdc_refclk_count_divisor == 40'd850000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tdc_refclk_count_scratch == 40'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tdc_target_count_scratch == 40'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tx_bond_size == UX3_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tx_cal_dutymeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tx_datarate == 40'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tx_i_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tx_i_clk_e4_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tx_i_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tx_line_rate_bps == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tx_master_bond_chnl == UX3_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tx_o_clk_e2_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tx_o_clk_e4_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tx_o_usr_clk_1_e2_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tx_o_usr_clk_1_e4_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tx_o_usr_clk_2_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tx_over_sample == UX3_TX_OVER_SAMPLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tx_pll == UX3_TX_PLL_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tx_pll_bw_sel == UX3_TX_PLL_BW_SEL_MEDIUM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tx_pll_is_downstream_pll == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tx_pll_refclk_mux_select == UX3_TX_PLL_REFCLK_MUX_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tx_pll_refclk_select == UX3_TX_PLL_REFCLK_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tx_protocol == UX3_TX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tx_tuning_hint == UX3_TX_TUNING_HINT_SDI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tx_user_clk1_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tx_user_clk1_mux == UX3_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tx_user_clk2_mux == UX3_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tx_user_clk_slow_med_mux == UX3_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tx_which_lane_to_copy == UX3_TX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_tx_width == UX3_TX_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_txeq_main_tap == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_txratewidth_rst_b0_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_txrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_txrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_txrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_txrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_txrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_txrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_txrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_txrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_txrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_txrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_txrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_txrx_channel_operation == UX3_TXRX_CHANNEL_OPERATION_DUAL_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_txrx_line_encoding_type == UX3_TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_txrx_xcvr_speed_bucket == UX3_TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux3_vreg_loopen_maxcnt_scratch == 40'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux_quad_instance == UX_QUAD_INSTANCE_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.flux_top.ux_speed_grade == UX_SPEED_GRADE_DASH2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.all_enabled_refclks_always_running == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.all_ux_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.hard_all_ux_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.refclk0_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.refclk1_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.refclk2_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.refclk3_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.refclk4_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.refclk5_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.refclk6_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.refclk7_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.refclk8_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.refclk9_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_01_st_pt == 6'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_10_st_pt == 6'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_bonding_size_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_bonding_size_cfg_reserved_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ethernet_source == UX0_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_external_dpma_refclk_source == UX0_EXTERNAL_DPMA_REFCLK_SOURCE_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_fec_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_flux_mode == UX0_FLUX_MODE_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_loopback_mode == UX0_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_q_dl_cfg_latpls_bw_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_q_dl_cfg_rst_rxbit_cntr_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_q_dl_cfg_sel_rxbit_adder_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_rx_adapt_mode == UX0_RX_ADAPT_MODE_STATIC_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_rx_protocol == UX0_RX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_rx_rst_value_pre_user_mode_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_rx_tuning_hint == UX0_RX_TUNING_HINT_SDI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_rx_user_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_standalone_core_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_standalone_core_clk_mux == UX0_STANDALONE_CORE_CLK_MUX_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_0_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_0_31 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_1_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_2_16to15 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_syspll0_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_syspll1_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_syspll2_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_tx_bond_size == UX0_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_tx_master_bond_chnl == UX0_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_tx_protocol == UX0_TX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_tx_rst_value_pre_user_mode_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_tx_tuning_hint == UX0_TX_TUNING_HINT_SDI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_tx_user_clk1_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_tx_user_clk1_mux == UX0_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_tx_user_clk2_mux == UX0_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_tx_user_clk_slow_med_mux == UX0_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_tx_width == UX0_TX_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_0_23 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_0_31 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_1_1 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_2_16to15 == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxeiosdetectstat_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxeq_clr_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxeq_precal_code_sel_lx_nt_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxeq_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxeq_static_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxeyediag_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxovrcdrlock2dataen_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxterm_hiz_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txbeacon_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txclkdivrate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txdetectrx_req_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txdrv_levn_lx_5to0 == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txdrv_levnm1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txdrv_levnp1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txdrv_levnp2_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txdrv_spare_l0_1to0 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txdrv_spare_l0_3to2 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txdrv_spare_l0_5to4 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txdrv_spare_l0_9to6 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txelecidle_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_0_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_0_31 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_1_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_2_16to15 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux0_vsr_mode == UX0_VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_01_st_pt == 6'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_10_st_pt == 6'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_bonding_size_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_bonding_size_cfg_reserved_attr == 25'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ethernet_source == UX1_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_external_dpma_refclk_source == UX1_EXTERNAL_DPMA_REFCLK_SOURCE_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_flux_mode == UX1_FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_loopback_mode == UX1_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_q_dl_cfg_latpls_bw_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_q_dl_cfg_rst_rxbit_cntr_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_q_dl_cfg_sel_rxbit_adder_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_rx_adapt_mode == UX1_RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_rx_protocol == UX1_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_rx_rst_value_pre_user_mode_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_rx_tuning_hint == UX1_RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_standalone_core_clk_mux == UX1_STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_0_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_0_31 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_1_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_2_16to15 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_syspll0_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_syspll1_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_syspll2_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_tx_bond_size == UX1_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_tx_master_bond_chnl == UX1_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_tx_protocol == UX1_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_tx_rst_value_pre_user_mode_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_tx_tuning_hint == UX1_TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_tx_user_clk1_mux == UX1_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_tx_user_clk2_mux == UX1_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_tx_user_clk_slow_med_mux == UX1_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_tx_width == UX1_TX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_0_23 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_0_31 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_1_1 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_2_16to15 == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxeiosdetectstat_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxeq_clr_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxeq_precal_code_sel_lx_nt_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxeq_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxeq_static_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxeyediag_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxovrcdrlock2dataen_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxterm_hiz_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txbeacon_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txclkdivrate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txdetectrx_req_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txdrv_levn_lx_5to0 == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txdrv_levnm1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txdrv_levnp1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txdrv_levnp2_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txdrv_spare_l0_1to0 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txdrv_spare_l0_3to2 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txdrv_spare_l0_5to4 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txdrv_spare_l0_9to6 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txelecidle_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_0_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_0_31 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_1_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_2_16to15 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux1_vsr_mode == UX1_VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_01_st_pt == 6'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_10_st_pt == 6'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_bonding_size_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_bonding_size_cfg_reserved_attr == 25'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ethernet_source == UX2_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_external_dpma_refclk_source == UX2_EXTERNAL_DPMA_REFCLK_SOURCE_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_fec_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_flux_mode == UX2_FLUX_MODE_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_loopback_mode == UX2_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_q_dl_cfg_latpls_bw_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_q_dl_cfg_rst_rxbit_cntr_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_q_dl_cfg_sel_rxbit_adder_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_rx_adapt_mode == UX2_RX_ADAPT_MODE_STATIC_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_rx_protocol == UX2_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_rx_rst_value_pre_user_mode_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_rx_tuning_hint == UX2_RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_rx_user_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_standalone_core_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_standalone_core_clk_mux == UX2_STANDALONE_CORE_CLK_MUX_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_0_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_0_31 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_1_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_2_16to15 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_syspll0_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_syspll1_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_syspll2_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_tx_bond_size == UX2_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_tx_master_bond_chnl == UX2_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_tx_protocol == UX2_TX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_tx_rst_value_pre_user_mode_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_tx_tuning_hint == UX2_TX_TUNING_HINT_SDI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_tx_user_clk1_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_tx_user_clk1_mux == UX2_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_tx_user_clk2_mux == UX2_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_tx_user_clk_slow_med_mux == UX2_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_tx_width == UX2_TX_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_0_23 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_0_31 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_1_1 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_2_16to15 == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxeiosdetectstat_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxeq_clr_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxeq_precal_code_sel_lx_nt_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxeq_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxeq_static_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxeyediag_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxovrcdrlock2dataen_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxterm_hiz_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txbeacon_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txclkdivrate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txdetectrx_req_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txdrv_levn_lx_5to0 == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txdrv_levnm1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txdrv_levnp1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txdrv_levnp2_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txdrv_spare_l0_1to0 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txdrv_spare_l0_3to2 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txdrv_spare_l0_5to4 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txdrv_spare_l0_9to6 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txelecidle_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_0_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_0_31 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_1_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_2_16to15 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux2_vsr_mode == UX2_VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_01_st_pt == 6'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_10_st_pt == 6'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_bonding_size_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_bonding_size_cfg_reserved_attr == 25'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ethernet_source == UX3_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_external_dpma_refclk_source == UX3_EXTERNAL_DPMA_REFCLK_SOURCE_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_fec_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_flux_mode == UX3_FLUX_MODE_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_loopback_mode == UX3_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_q_dl_cfg_latpls_bw_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_q_dl_cfg_rst_rxbit_cntr_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_q_dl_cfg_sel_rxbit_adder_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_rx_adapt_mode == UX3_RX_ADAPT_MODE_STATIC_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_rx_protocol == UX3_RX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_rx_rst_value_pre_user_mode_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_rx_tuning_hint == UX3_RX_TUNING_HINT_SDI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_rx_user_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_standalone_core_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_standalone_core_clk_mux == UX3_STANDALONE_CORE_CLK_MUX_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_0_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_0_31 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_1_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_2_16to15 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_syspll0_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_syspll1_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_syspll2_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_tx_bond_size == UX3_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_tx_master_bond_chnl == UX3_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_tx_protocol == UX3_TX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_tx_rst_value_pre_user_mode_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_tx_tuning_hint == UX3_TX_TUNING_HINT_SDI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_tx_user_clk1_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_tx_user_clk1_mux == UX3_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_tx_user_clk2_mux == UX3_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_tx_user_clk_slow_med_mux == UX3_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_tx_width == UX3_TX_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_0_23 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_0_31 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_1_1 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_2_16to15 == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxeiosdetectstat_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxeq_clr_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxeq_precal_code_sel_lx_nt_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxeq_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxeq_static_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxeyediag_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxovrcdrlock2dataen_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxterm_hiz_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txbeacon_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txclkdivrate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txdetectrx_req_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txdrv_levn_lx_5to0 == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txdrv_levnm1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txdrv_levnp1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txdrv_levnp2_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txdrv_spare_l0_1to0 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txdrv_spare_l0_3to2 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txdrv_spare_l0_5to4 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txdrv_spare_l0_9to6 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txelecidle_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_0_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_0_31 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_1_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_2_16to15 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux3_vsr_mode == UX3_VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_cpi_cmn2_st_pt == 11'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_cpi_lm_addr == 30'd589884
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_cpi_phy_addr == 30'd589888
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_cpi_reserved == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_cpi_seq_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_cpi_timer_max == 16'd500
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_end_pt == 11'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_flux_cpu_freq == 36'd250
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK1_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_bonding_ctrl_cfg_bonding_ctrl_l0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_bonding_ctrl_cfg_bonding_ctrl_l1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_bonding_ctrl_cfg_bonding_ctrl_l2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_bonding_ctrl_cfg_bonding_ctrl_l3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_bonding_ctrl_cfg_bonding_enable_l0_attr == BONDING_L0_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_bonding_ctrl_cfg_bonding_enable_l1_attr == BONDING_L1_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_bonding_ctrl_cfg_bonding_enable_l2_attr == BONDING_L2_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_bonding_ctrl_cfg_bonding_enable_l3_attr == BONDING_L3_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_ckmux_cpu_attr == CKMUX_CPU_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_cpi_seq_ctrl_cfg_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_datapath_loopback_en_cfg_datapath_loopback_en_l0_attr == LB_L0_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_datapath_loopback_en_cfg_datapath_loopback_en_l1_attr == LB_L1_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_datapath_loopback_en_cfg_datapath_loopback_en_l2_attr == LB_L2_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_datapath_loopback_en_cfg_datapath_loopback_en_l3_attr == LB_L3_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_a_cfg_clk_en_dfd_clk_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_a_cfg_dfd_clk_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_a_cfg_dfd_extrig_muxsel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_a_cfg_dfd_mux_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_a_cfg_dfd_rsvd_muxsel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_a_cfg_pattern_cntr_data_sel_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_a_cfg_pattern_cntr_inc_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_a_cfg_pattern_cntr_rst_b_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_b_cfg_apb_rdata_sel_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_b_cfg_rst_dfd_extrig_cntr_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_dl_ctrl_a_l2_cfg_ctrl_reserved_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_dl_ctrl_a_l3_cfg_ctrl_reserved_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_dpma_clk_mux_reserved_attr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e200_rxclk_en_l0_attr == E200_RXCLK_EN_L0_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e200_rxclk_en_l1_attr == E200_RXCLK_EN_L1_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e200_rxclk_en_l2_attr == E200_RXCLK_EN_L2_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e200_rxclk_en_l3_attr == E200_RXCLK_EN_L3_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e200_txclk_en_l0_attr == E200_TXCLK_EN_L0_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e200_txclk_en_l1_attr == E200_TXCLK_EN_L1_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e200_txclk_en_l2_attr == E200_TXCLK_EN_L2_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e200_txclk_en_l3_attr == E200_TXCLK_EN_L3_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_slow_med_l0_attr == E400_CKMUX_SLOW_MED_L0_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_slow_med_l1_attr == E400_CKMUX_SLOW_MED_L1_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_slow_med_l2_attr == E400_CKMUX_SLOW_MED_L2_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_slow_med_l3_attr == E400_CKMUX_SLOW_MED_L3_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser0_l0_attr == E400_CKMUX_TXUSER0_L0_NON_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser0_l1_attr == E400_CKMUX_TXUSER0_L1_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser0_l2_attr == E400_CKMUX_TXUSER0_L2_NON_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser0_l3_attr == E400_CKMUX_TXUSER0_L3_NON_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser1_l0_attr == E400_CKMUX_TXUSER1_L0_NON_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser1_l1_attr == E400_CKMUX_TXUSER1_L1_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser1_l2_attr == E400_CKMUX_TXUSER1_L2_NON_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser1_l3_attr == E400_CKMUX_TXUSER1_L3_NON_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser2_l0_attr == E400_CKMUX_TXUSER2_L0_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser2_l1_attr == E400_CKMUX_TXUSER2_L1_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser2_l2_attr == E400_CKMUX_TXUSER2_L2_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser2_l3_attr == E400_CKMUX_TXUSER2_L3_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_rxclk_en_l0_attr == E400_RXCLK_EN_L0_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_rxclk_en_l1_attr == E400_RXCLK_EN_L1_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_rxclk_en_l2_attr == E400_RXCLK_EN_L2_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_rxclk_en_l3_attr == E400_RXCLK_EN_L3_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_rxusrclk_en_l0_attr == E400_RXUSRCLK_EN_L0_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_rxusrclk_en_l1_attr == E400_RXUSRCLK_EN_L1_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_rxusrclk_en_l2_attr == E400_RXUSRCLK_EN_L2_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_rxusrclk_en_l3_attr == E400_RXUSRCLK_EN_L3_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_txclk_en_l0_attr == E400_TXCLK_EN_L0_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_txclk_en_l1_attr == E400_TXCLK_EN_L1_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_txclk_en_l2_attr == E400_TXCLK_EN_L2_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_txclk_en_l3_attr == E400_TXCLK_EN_L3_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk0_en_l0_attr == E400_USRCLK0_EN_L0_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk0_en_l1_attr == E400_USRCLK0_EN_L1_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk0_en_l2_attr == E400_USRCLK0_EN_L2_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk0_en_l3_attr == E400_USRCLK0_EN_L3_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk1_en_l0_attr == E400_USRCLK1_EN_L0_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk1_en_l1_attr == E400_USRCLK1_EN_L1_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk1_en_l2_attr == E400_USRCLK1_EN_L2_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk1_en_l3_attr == E400_USRCLK1_EN_L3_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk2_en_l0_attr == E400_USRCLK2_EN_L0_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk2_en_l1_attr == E400_USRCLK2_EN_L1_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk2_en_l2_attr == E400_USRCLK2_EN_L2_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk2_en_l3_attr == E400_USRCLK2_EN_L3_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e_rx_dp_pipe_l0_attr == E_RX_DP_PIPE_L0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e_rx_dp_pipe_l1_attr == E_RX_DP_PIPE_L1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e_rx_dp_pipe_l2_attr == E_RX_DP_PIPE_L2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e_rx_dp_pipe_l3_attr == E_RX_DP_PIPE_L3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e_tx_dp_pipe_l0_attr == E_TX_DP_PIPE_L0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e_tx_dp_pipe_l1_attr == E_TX_DP_PIPE_L1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e_tx_dp_pipe_l2_attr == E_TX_DP_PIPE_L2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_e_tx_dp_pipe_l3_attr == E_TX_DP_PIPE_L3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_fw_load_base_l0_cfg_value_attr == 32'd277792
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_fw_load_base_l1_cfg_value_attr == 32'd310560
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_fw_load_base_l2_cfg_value_attr == 32'd343328
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_fw_load_base_l3_cfg_value_attr == 32'd376096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_i_pll0_hz == 36'd250000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_i_pll1_hz == 36'd250000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_i_pll2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_indirect_access_ctrl_cfg_fw_load_disable_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_indirect_access_ctrl_cfg_fw_load_mode_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_indirect_access_ctrl_cfg_mapped_base_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_indirect_access_ctrl_cfg_reserved_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_indirect_access_ctrl_cfg_unmapped_base_attr == 18'd16384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_mode_ctrl_cfg_func_mode_l0_attr == FUNC_MODE_E400_L0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_mode_ctrl_cfg_func_mode_l1_attr == FUNC_MODE_E400_L1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_mode_ctrl_cfg_func_mode_l2_attr == FUNC_MODE_E400_L2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_mode_ctrl_cfg_func_mode_l3_attr == FUNC_MODE_E400_L3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_medclk_en_l0_attr == PCIE_MEDCLK_EN_L0_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_medclk_en_l1_attr == PCIE_MEDCLK_EN_L1_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_medclk_en_l2_attr == PCIE_MEDCLK_EN_L2_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_medclk_en_l3_attr == PCIE_MEDCLK_EN_L3_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_pclk_en_l0_attr == PCIE_PCLK_EN_L0_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_pclk_en_l1_attr == PCIE_PCLK_EN_L1_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_pclk_en_l2_attr == PCIE_PCLK_EN_L2_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_pclk_en_l3_attr == PCIE_PCLK_EN_L3_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_refclk_en_l0_attr == PCIE_REFCLK_EN_L0_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_refclk_en_l1_attr == PCIE_REFCLK_EN_L1_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_refclk_en_l2_attr == PCIE_REFCLK_EN_L2_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_refclk_en_l3_attr == PCIE_REFCLK_EN_L3_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_rxclk_en_l0_attr == PCIE_RXCLK_EN_L0_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_rxclk_en_l1_attr == PCIE_RXCLK_EN_L1_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_rxclk_en_l2_attr == PCIE_RXCLK_EN_L2_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_rxclk_en_l3_attr == PCIE_RXCLK_EN_L3_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_slowclk_en_l0_attr == PCIE_SLOWCLK_EN_L0_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_slowclk_en_l1_attr == PCIE_SLOWCLK_EN_L1_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_slowclk_en_l2_attr == PCIE_SLOWCLK_EN_L2_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_slowclk_en_l3_attr == PCIE_SLOWCLK_EN_L3_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_reserved0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_10_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_11_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_12_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_13_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_14_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_15_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_16_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_17_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_18_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_19_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_20_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_21_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_22_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_23_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_24_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_25_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_26_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_27_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_28_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_29_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_30_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_31_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_32_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_33_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_34_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_35_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_36_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_37_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_38_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_39_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_40_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_41_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_42_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_43_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_44_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_45_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_46_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_47_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_48_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_49_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_50_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_51_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_52_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_53_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_54_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_55_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_56_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_57_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_58_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_59_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_5_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_60_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_61_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_62_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_63_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_6_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_7_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_8_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_9_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_ctrl_0_cfg_restart_seq_sm_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_ctrl_0_cfg_skip_rd_seq_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_ctrl_1_cfg_seqen_0to31_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_ctrl_2_cfg_seqen_32to63_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_ctrl_3_cfg_seq_rdwrb_0to31_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_ctrl_4_cfg_seq_rdwrb_32to63_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_0_attr == 32'd32874599
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_10_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_11_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_12_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_13_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_14_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_15_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_16_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_17_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_18_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_19_attr == 32'd41200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_1_attr == 32'd41138
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_20_attr == 32'd41456
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_21_attr == 32'd41712
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_22_attr == 32'd41968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_23_attr == 32'd41060
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_24_attr == 32'd41316
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_25_attr == 32'd41572
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_26_attr == 32'd41828
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_27_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_28_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_29_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_2_attr == 32'd134258864
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_30_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_31_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_32_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_33_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_34_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_35_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_36_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_37_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_38_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_39_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_3_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_40_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_41_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_42_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_43_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_44_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_45_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_46_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_47_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_48_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_49_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_4_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_50_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_51_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_52_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_53_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_54_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_55_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_56_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_57_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_58_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_59_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_5_attr == 32'd16359695
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_60_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_61_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_62_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_63_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_6_attr == 32'd41219
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_7_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_8_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_9_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_0_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_10_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_11_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_12_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_13_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_14_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_15_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_16_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_17_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_18_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_19_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_1_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_20_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_21_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_22_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_23_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_24_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_25_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_26_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_27_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_28_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_29_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_2_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_30_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_31_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_32_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_33_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_34_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_35_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_36_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_37_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_38_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_39_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_3_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_40_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_41_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_42_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_43_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_44_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_45_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_46_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_47_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_48_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_49_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_4_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_50_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_51_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_52_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_53_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_54_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_55_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_56_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_57_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_58_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_59_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_5_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_60_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_61_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_62_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_63_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_6_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_7_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_8_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_9_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_quad_instance == UX_QUAD_INSTANCE_ZERO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_0.gdr_ux_quad_avmm_cfgcsr.ux_rst_value_pre_user_mode_reserved_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.all_enabled_refclks_always_running == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.all_ux_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.bot_f_fastest_reconfig_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.bot_refclk_reconfig_span == BOT_REFCLK_RECONFIG_SPAN_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.bot_syspll_refclk_output_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ch1_ch0_master_pll_pair_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ch3_ch2_master_pll_pair_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.clkrx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.f_avmm_clk_hz == 40'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.f_bot_refclk_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.f_bot_syspll_refclk_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.f_fastest_reconfig_refclk_global_refclk_0_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.f_fastest_reconfig_refclk_global_refclk_1_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.f_fastest_reconfig_refclk_global_refclk_2_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.f_fastest_reconfig_refclk_global_refclk_3_hz == 40'd800000001
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.f_fastest_reconfig_refclk_regional_refclk_0_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.f_fastest_reconfig_refclk_regional_refclk_1_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.f_global_refclk_0_bot_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.f_global_refclk_0_bot_right_top_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.f_global_refclk_1_bot_right_top_left_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.f_global_refclk_1_top_right_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.f_global_refclk_2_bot_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.f_global_refclk_2_bot_right_top_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.f_global_refclk_3_bot_right_top_left_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.f_global_refclk_3_top_right_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.f_local_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.f_regional_refclk_0_bot_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.f_regional_refclk_0_bot_right_top_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.f_regional_refclk_1_bot_right_top_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.f_regional_refclk_1_top_right_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.f_top_refclk_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.f_top_syspll_refclk_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.global_refclk_0_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.global_refclk_0_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.global_refclk_1_left_adjacent_active == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.global_refclk_1_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.global_refclk_2_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.global_refclk_2_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.global_refclk_3_left_adjacent_active == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.global_refclk_3_right_adjacent_active == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.hard_all_ux_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_avmm == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_bot_clkrx_base == POWERMODE_AC_MODE_BOT_CLKRX_BASE_NON_PIN_PRIMARY_DRIVER_HIGH_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_bot_cmos_driver == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_flux == POWERMODE_AC_MODE_FLUX_FLUX_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_global_refclk_0_bot == POWERMODE_AC_MODE_GLOBAL_REFCLK_0_BOT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_global_refclk_0_top == POWERMODE_AC_MODE_GLOBAL_REFCLK_0_TOP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_global_refclk_1_bot == POWERMODE_AC_MODE_GLOBAL_REFCLK_1_BOT_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_global_refclk_1_top == POWERMODE_AC_MODE_GLOBAL_REFCLK_1_TOP_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_global_refclk_2_bot == POWERMODE_AC_MODE_GLOBAL_REFCLK_2_BOT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_global_refclk_2_top == POWERMODE_AC_MODE_GLOBAL_REFCLK_2_TOP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_global_refclk_3_bot == POWERMODE_AC_MODE_GLOBAL_REFCLK_3_BOT_HIGH_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_global_refclk_3_top == POWERMODE_AC_MODE_GLOBAL_REFCLK_3_TOP_HIGH_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_regional_refclk_0_bot == POWERMODE_AC_MODE_REGIONAL_REFCLK_0_BOT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_regional_refclk_0_top == POWERMODE_AC_MODE_REGIONAL_REFCLK_0_TOP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_regional_refclk_1_bot == POWERMODE_AC_MODE_REGIONAL_REFCLK_1_BOT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_regional_refclk_1_top == POWERMODE_AC_MODE_REGIONAL_REFCLK_1_TOP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_rx_ux0 == UX0_POWERMODE_AC_MODE_RX_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_rx_ux1 == UX1_POWERMODE_AC_MODE_RX_NRZ_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_rx_ux2 == UX2_POWERMODE_AC_MODE_RX_NRZ_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_rx_ux3 == UX3_POWERMODE_AC_MODE_RX_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_synth_lc_fast_ux0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_synth_lc_fast_ux1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_synth_lc_fast_ux2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_synth_lc_fast_ux3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_synth_lc_med_ux0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_synth_lc_med_ux1 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_synth_lc_med_ux2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_synth_lc_med_ux3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_synth_lc_slow_ux0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_synth_lc_slow_ux1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_synth_lc_slow_ux2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_synth_lc_slow_ux3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_top_clkrx_base == POWERMODE_AC_MODE_TOP_CLKRX_BASE_PIN_TO_CLKRX_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_top_cmos_driver == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_tx_ux0 == UX0_POWERMODE_AC_MODE_TX_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_tx_ux1 == UX1_POWERMODE_AC_MODE_TX_NRZ_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_tx_ux2 == UX2_POWERMODE_AC_MODE_TX_NRZ_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_ac_mode_tx_ux3 == UX3_POWERMODE_AC_MODE_TX_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_avmm == 40'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_bot_clkrx_base == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_bot_cmos_driver == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_flux == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_global_refclk_0_bot == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_global_refclk_0_top == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_global_refclk_1_bot == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_global_refclk_1_top == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_global_refclk_2_bot == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_global_refclk_2_top == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_global_refclk_3_bot == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_global_refclk_3_top == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_regional_refclk_0_bot == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_regional_refclk_0_top == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_regional_refclk_1_bot == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_regional_refclk_1_top == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_rx_parallel_ux0 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_rx_parallel_ux1 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_rx_parallel_ux2 == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_rx_parallel_ux3 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_rx_ux0 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_rx_ux1 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_rx_ux2 == 36'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_rx_ux3 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_synth_lc_fast_ux0 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_synth_lc_fast_ux1 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_synth_lc_fast_ux2 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_synth_lc_fast_ux3 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_synth_lc_med_ux0 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_synth_lc_med_ux1 == 40'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_synth_lc_med_ux2 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_synth_lc_med_ux3 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_synth_lc_slow_ux0 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_synth_lc_slow_ux1 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_synth_lc_slow_ux2 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_synth_lc_slow_ux3 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_top_clkrx_base == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_top_cmos_driver == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_tx_parallel_ux0 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_tx_parallel_ux1 == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_tx_parallel_ux2 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_tx_parallel_ux3 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_tx_ux0 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_tx_ux1 == 36'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_tx_ux2 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.powermode_freq_hz_tx_ux3 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.refclk0_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.refclk1_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.refclk2_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.refclk3_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.refclk4_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.refclk5_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.refclk6_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.refclk7_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.refclk8_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.refclk9_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.regional_refclk_0_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.regional_refclk_0_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.regional_refclk_1_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.regional_refclk_1_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.top_f_fastest_reconfig_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.top_refclk_reconfig_span == TOP_REFCLK_RECONFIG_SPAN_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.top_syspll_refclk_output_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_cdr_bw_sel == UX0_CDR_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_cdr_f_mod_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_cdr_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_cdr_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_cdr_f_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_cdr_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_cdr_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_cdr_is_cascaded == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_cdr_l_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_cdr_m_counter == 9'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_cdr_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_cdr_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_cdr_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_cdr_ppm_driftcount == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_cdr_refclk_mux_select == UX0_CDR_REFCLK_MUX_SELECT_REGIONAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_cdr_refclk_select == UX0_CDR_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_cmn_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_core_pll == UX0_CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_core_pll_refclk_select == UX0_CORE_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_dpma_refclk_source == UX0_DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_duplex_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_enable_port_control_of_cdr_ltr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ethernet_source == UX0_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_expose_pcie_gen1_gen6_critical_signals == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_external_dpma_refclk_source == UX0_EXTERNAL_DPMA_REFCLK_SOURCE_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_flux_mode == UX0_FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_lane_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_loopback_mode == UX0_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_master_sup_mode == UX0_MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_primary_use == UX0_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ref_clk_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_rx_adapt_mode == UX0_RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_rx_bond_size == UX0_RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_rx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_rx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_rx_master_bond_chnl == UX0_RX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_rx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_rx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_rx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_rx_o_usr_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_rx_o_usr_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_rx_onchip_termination == UX0_RX_ONCHIP_TERMINATION_R_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_rx_protocol == UX0_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_rx_term_mode_select == UX0_RX_TERM_MODE_SELECT_GROUNDED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_rx_tuning_hint == UX0_RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_rx_width == UX0_RX_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_rxeq_vga_gain == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_standalone_core_clk_mux == UX0_STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sup_mode == UX0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sv_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sv_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sv_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sv_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sv_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sv_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sv_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sv_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sv_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sv_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sv_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sv_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sv_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sv_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sv_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sv_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_sv_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_0_feed_forward_gain == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_0_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_fast_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_fast_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_fast_primary_use == UX0_SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_fb_div_emb_mult_counter == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_med_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_med_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_med_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_med_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_med_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_med_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_med_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_med_primary_use == UX0_SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_slow_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_slow_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_slow_primary_use == UX0_SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_syspll0_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_syspll1_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_syspll2_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_tx_bond_size == UX0_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_tx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_tx_i_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_tx_i_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_tx_i_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_tx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_tx_master_bond_chnl == UX0_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_tx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_tx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_tx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_tx_o_usr_clk_1_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_tx_o_usr_clk_1_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_tx_o_usr_clk_2_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_tx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_tx_pll == UX0_TX_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_tx_pll_bw_sel == UX0_TX_PLL_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_tx_pll_refclk_mux_select == UX0_TX_PLL_REFCLK_MUX_SELECT_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_tx_pll_refclk_select == UX0_TX_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_tx_protocol == UX0_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_tx_tuning_hint == UX0_TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_tx_user_clk1_mux == UX0_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_tx_user_clk2_mux == UX0_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_tx_user_clk_slow_med_mux == UX0_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_tx_width == UX0_TX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_txeq_main_tap == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_txrx_channel_operation == UX0_TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_txrx_line_encoding_type == UX0_TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_txrx_xcvr_speed_bucket == UX0_TXRX_XCVR_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_en_rxbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_en_rxeiosdetectstat_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_en_rxeq_clr_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_en_rxeq_precal_code_sel_lx_nt_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_en_rxeq_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_en_rxeq_static_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_en_rxeyediag_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_en_rxovrcdrlock2dataen_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_en_rxpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_en_rxrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_en_rxterm_hiz_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_en_rxwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_en_txbeacon_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_en_txbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_en_txclkdivrate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_en_txdetectrx_req_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_en_txdrv_levn_lx_5to0 == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_en_txdrv_levnm1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_en_txdrv_levnp1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_en_txdrv_levnp2_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_en_txdrv_spare_l0_1to0 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_en_txdrv_spare_l0_3to2 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_en_txdrv_spare_l0_5to4 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_en_txdrv_spare_l0_9to6 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_en_txelecidle_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_en_txpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_en_txrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_en_txwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_ovr_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_ovr_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_ovr_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_ovr_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_ovr_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_ovr_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_ovr_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_ovr_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_ovr_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_ovr_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_ovr_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_ovr_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_ovr_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_ovr_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_ovr_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_ovr_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_ur_ovr_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux0_vsr_mode == UX0_VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_cdr_bw_sel == UX1_CDR_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_cdr_f_mod_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_cdr_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_cdr_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_cdr_f_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_cdr_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_cdr_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_cdr_is_cascaded == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_cdr_l_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_cdr_m_counter == 9'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_cdr_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_cdr_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_cdr_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_cdr_ppm_driftcount == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_cdr_refclk_mux_select == UX1_CDR_REFCLK_MUX_SELECT_REGIONAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_cdr_refclk_select == UX1_CDR_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_cmn_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_core_pll == UX1_CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_core_pll_refclk_select == UX1_CORE_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_dpma_refclk_source == UX1_DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_duplex_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_enable_port_control_of_cdr_ltr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ethernet_source == UX1_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_expose_pcie_gen1_gen6_critical_signals == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_external_dpma_refclk_source == UX1_EXTERNAL_DPMA_REFCLK_SOURCE_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_fec_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_flux_mode == UX1_FLUX_MODE_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_lane_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_loopback_mode == UX1_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_master_sup_mode == UX1_MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_prbs_mon_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_primary_use == UX1_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ref_clk_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_rx_adapt_mode == UX1_RX_ADAPT_MODE_STATIC_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_rx_bond_size == UX1_RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_rx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_rx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_rx_master_bond_chnl == UX1_RX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_rx_o_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_rx_o_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_rx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_rx_o_usr_clk_e2_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_rx_o_usr_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_rx_onchip_termination == UX1_RX_ONCHIP_TERMINATION_R_4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_rx_protocol == UX1_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_rx_protocol_hard_pcie_lowloss == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_rx_term_mode_select == UX1_RX_TERM_MODE_SELECT_GROUNDED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_rx_tuning_hint == UX1_RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_rx_user_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_rx_width == UX1_RX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_rxeq_vga_gain == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_squelch_detect == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_standalone_core_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_standalone_core_clk_mux == UX1_STANDALONE_CORE_CLK_MUX_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sup_mode == UX1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sv_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sv_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sv_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sv_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sv_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sv_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sv_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sv_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sv_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sv_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sv_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sv_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sv_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sv_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sv_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sv_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_sv_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_0_feed_forward_gain == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_0_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_fast_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_fast_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_fast_primary_use == UX1_SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_fb_div_emb_mult_counter == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_fb_div_n_frac_mode == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_med_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_med_f_out_hz == 40'd5940000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_med_f_ref_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_med_f_tx_postdiv_hz == 40'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_med_f_vco_hz == 40'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_med_l_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_med_m_counter == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_med_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_med_primary_use == UX1_SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_med_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_med_tx_postdiv_counter == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_slow_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_slow_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_slow_primary_use == UX1_SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_syspll0_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_syspll1_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_syspll2_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_tx_bond_size == UX1_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_tx_datarate == 40'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_tx_i_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_tx_i_clk_e4_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_tx_i_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_tx_line_rate_bps == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_tx_master_bond_chnl == UX1_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_tx_o_clk_e2_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_tx_o_clk_e4_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_tx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_tx_o_usr_clk_1_e2_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_tx_o_usr_clk_1_e4_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_tx_o_usr_clk_2_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_tx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_tx_pll == UX1_TX_PLL_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_tx_pll_bw_sel == UX1_TX_PLL_BW_SEL_MEDIUM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_tx_pll_refclk_mux_select == UX1_TX_PLL_REFCLK_MUX_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_tx_pll_refclk_select == UX1_TX_PLL_REFCLK_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_tx_protocol == UX1_TX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_tx_tuning_hint == UX1_TX_TUNING_HINT_SDI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_tx_user_clk1_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_tx_user_clk1_mux == UX1_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_tx_user_clk2_mux == UX1_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_tx_user_clk_slow_med_mux == UX1_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_tx_width == UX1_TX_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_txeq_main_tap == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_txrx_channel_operation == UX1_TXRX_CHANNEL_OPERATION_DUAL_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_txrx_line_encoding_type == UX1_TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_txrx_xcvr_speed_bucket == UX1_TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_en_rxbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_en_rxeiosdetectstat_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_en_rxeq_clr_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_en_rxeq_precal_code_sel_lx_nt_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_en_rxeq_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_en_rxeq_static_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_en_rxeyediag_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_en_rxovrcdrlock2dataen_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_en_rxpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_en_rxrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_en_rxterm_hiz_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_en_rxwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_en_txbeacon_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_en_txbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_en_txclkdivrate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_en_txdetectrx_req_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_en_txdrv_levn_lx_5to0 == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_en_txdrv_levnm1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_en_txdrv_levnp1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_en_txdrv_levnp2_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_en_txdrv_spare_l0_1to0 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_en_txdrv_spare_l0_3to2 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_en_txdrv_spare_l0_5to4 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_en_txdrv_spare_l0_9to6 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_en_txelecidle_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_en_txpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_en_txrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_en_txwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_ovr_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_ovr_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_ovr_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_ovr_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_ovr_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_ovr_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_ovr_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_ovr_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_ovr_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_ovr_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_ovr_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_ovr_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_ovr_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_ovr_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_ovr_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_ovr_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_ur_ovr_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux1_vsr_mode == UX1_VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_cdr_bw_sel == UX2_CDR_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_cdr_f_mod_hz == 40'd990000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_cdr_f_out_hz == 40'd5940000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_cdr_f_pfd_hz == 40'd29700000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_cdr_f_postdiv_hz == 40'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_cdr_f_ref_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_cdr_f_vco_hz == 40'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_cdr_is_cascaded == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_cdr_l_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_cdr_m_counter == 9'd200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_cdr_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_cdr_postdiv_counter == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_cdr_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_cdr_ppm_driftcount == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_cdr_refclk_mux_select == UX2_CDR_REFCLK_MUX_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_cdr_refclk_select == UX2_CDR_REFCLK_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_cmn_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_core_pll == UX2_CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_core_pll_refclk_select == UX2_CORE_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_dpma_refclk_source == UX2_DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_duplex_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_enable_port_control_of_cdr_ltr_ltd == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ethernet_source == UX2_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_expose_pcie_gen1_gen6_critical_signals == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_external_dpma_refclk_source == UX2_EXTERNAL_DPMA_REFCLK_SOURCE_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_fec_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_flux_mode == UX2_FLUX_MODE_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_lane_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_loopback_mode == UX2_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_master_sup_mode == UX2_MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_prbs_gen_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_primary_use == UX2_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ref_clk_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_rx_adapt_mode == UX2_RX_ADAPT_MODE_UX_RX_ADAPT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_rx_bond_size == UX2_RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_rx_datarate == 40'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_rx_line_rate_bps == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_rx_master_bond_chnl == UX2_RX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_rx_o_clk_e2_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_rx_o_clk_e4_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_rx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_rx_o_usr_clk_e2_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_rx_o_usr_clk_e4_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_rx_onchip_termination == UX2_RX_ONCHIP_TERMINATION_R_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_rx_protocol == UX2_RX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_rx_term_mode_select == UX2_RX_TERM_MODE_SELECT_DIFFERENTIAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_rx_tuning_hint == UX2_RX_TUNING_HINT_SDI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_rx_user_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_rx_width == UX2_RX_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_rxeq_vga_gain == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_standalone_core_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_standalone_core_clk_mux == UX2_STANDALONE_CORE_CLK_MUX_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sup_mode == UX2_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sv_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sv_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sv_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sv_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sv_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sv_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sv_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sv_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sv_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sv_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sv_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sv_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sv_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sv_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sv_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sv_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_sv_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_0_feed_forward_gain == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_0_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_fast_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_fast_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_fast_primary_use == UX2_SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_fb_div_emb_mult_counter == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_fb_div_n_frac_mode == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_med_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_med_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_med_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_med_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_med_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_med_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_med_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_med_primary_use == UX2_SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_slow_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_slow_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_slow_primary_use == UX2_SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_syspll0_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_syspll1_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_syspll2_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_tx_bond_size == UX2_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_tx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_tx_i_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_tx_i_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_tx_i_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_tx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_tx_master_bond_chnl == UX2_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_tx_o_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_tx_o_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_tx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_tx_o_usr_clk_1_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_tx_o_usr_clk_1_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_tx_o_usr_clk_2_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_tx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_tx_pll == UX2_TX_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_tx_pll_bw_sel == UX2_TX_PLL_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_tx_pll_refclk_mux_select == UX2_TX_PLL_REFCLK_MUX_SELECT_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_tx_pll_refclk_select == UX2_TX_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_tx_protocol == UX2_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_tx_protocol_hard_pcie_lowloss == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_tx_tuning_hint == UX2_TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_tx_user_clk1_mux == UX2_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_tx_user_clk2_mux == UX2_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_tx_user_clk_slow_med_mux == UX2_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_tx_width == UX2_TX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_txeq_main_tap == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_txrx_channel_operation == UX2_TXRX_CHANNEL_OPERATION_DUAL_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_txrx_line_encoding_type == UX2_TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_txrx_xcvr_speed_bucket == UX2_TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_en_rxbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_en_rxeiosdetectstat_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_en_rxeq_clr_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_en_rxeq_precal_code_sel_lx_nt_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_en_rxeq_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_en_rxeq_static_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_en_rxeyediag_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_en_rxovrcdrlock2dataen_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_en_rxpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_en_rxrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_en_rxterm_hiz_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_en_rxwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_en_txbeacon_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_en_txbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_en_txclkdivrate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_en_txdetectrx_req_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_en_txdrv_levn_lx_5to0 == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_en_txdrv_levnm1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_en_txdrv_levnp1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_en_txdrv_levnp2_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_en_txdrv_spare_l0_1to0 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_en_txdrv_spare_l0_3to2 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_en_txdrv_spare_l0_5to4 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_en_txdrv_spare_l0_9to6 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_en_txelecidle_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_en_txpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_en_txrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_en_txwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_ovr_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_ovr_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_ovr_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_ovr_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_ovr_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_ovr_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_ovr_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_ovr_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_ovr_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_ovr_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_ovr_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_ovr_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_ovr_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_ovr_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_ovr_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_ovr_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_ur_ovr_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux2_vsr_mode == UX2_VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_cdr_bw_sel == UX3_CDR_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_cdr_f_mod_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_cdr_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_cdr_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_cdr_f_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_cdr_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_cdr_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_cdr_is_cascaded == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_cdr_l_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_cdr_m_counter == 9'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_cdr_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_cdr_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_cdr_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_cdr_ppm_driftcount == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_cdr_refclk_mux_select == UX3_CDR_REFCLK_MUX_SELECT_REGIONAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_cdr_refclk_select == UX3_CDR_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_cmn_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_core_pll == UX3_CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_core_pll_refclk_select == UX3_CORE_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_dpma_refclk_source == UX3_DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_duplex_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_enable_port_control_of_cdr_ltr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ethernet_source == UX3_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_expose_pcie_gen1_gen6_critical_signals == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_external_dpma_refclk_source == UX3_EXTERNAL_DPMA_REFCLK_SOURCE_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_flux_mode == UX3_FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_lane_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_loopback_mode == UX3_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_master_sup_mode == UX3_MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_primary_use == UX3_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ref_clk_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_rx_adapt_mode == UX3_RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_rx_bond_size == UX3_RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_rx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_rx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_rx_master_bond_chnl == UX3_RX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_rx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_rx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_rx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_rx_o_usr_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_rx_o_usr_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_rx_onchip_termination == UX3_RX_ONCHIP_TERMINATION_R_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_rx_protocol == UX3_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_rx_term_mode_select == UX3_RX_TERM_MODE_SELECT_GROUNDED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_rx_tuning_hint == UX3_RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_rx_width == UX3_RX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_rxeq_vga_gain == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_standalone_core_clk_mux == UX3_STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sup_mode == UX3_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sv_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sv_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sv_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sv_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sv_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sv_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sv_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sv_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sv_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sv_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sv_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sv_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sv_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sv_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sv_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sv_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_sv_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_0_feed_forward_gain == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_0_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_fast_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_fast_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_fast_primary_use == UX3_SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_fb_div_emb_mult_counter == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_med_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_med_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_med_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_med_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_med_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_med_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_med_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_med_primary_use == UX3_SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_slow_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_slow_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_slow_primary_use == UX3_SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_syspll0_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_syspll1_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_syspll2_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_tx_bond_size == UX3_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_tx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_tx_i_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_tx_i_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_tx_i_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_tx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_tx_master_bond_chnl == UX3_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_tx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_tx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_tx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_tx_o_usr_clk_1_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_tx_o_usr_clk_1_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_tx_o_usr_clk_2_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_tx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_tx_pll == UX3_TX_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_tx_pll_bw_sel == UX3_TX_PLL_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_tx_pll_refclk_mux_select == UX3_TX_PLL_REFCLK_MUX_SELECT_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_tx_pll_refclk_select == UX3_TX_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_tx_protocol == UX3_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_tx_tuning_hint == UX3_TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_tx_user_clk1_mux == UX3_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_tx_user_clk2_mux == UX3_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_tx_user_clk_slow_med_mux == UX3_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_tx_width == UX3_TX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_txeq_main_tap == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_txrx_channel_operation == UX3_TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_txrx_line_encoding_type == UX3_TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_txrx_xcvr_speed_bucket == UX3_TXRX_XCVR_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_en_rxbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_en_rxeiosdetectstat_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_en_rxeq_clr_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_en_rxeq_precal_code_sel_lx_nt_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_en_rxeq_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_en_rxeq_static_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_en_rxeyediag_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_en_rxovrcdrlock2dataen_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_en_rxpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_en_rxrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_en_rxterm_hiz_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_en_rxwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_en_txbeacon_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_en_txbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_en_txclkdivrate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_en_txdetectrx_req_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_en_txdrv_levn_lx_5to0 == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_en_txdrv_levnm1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_en_txdrv_levnp1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_en_txdrv_levnp2_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_en_txdrv_spare_l0_1to0 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_en_txdrv_spare_l0_3to2 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_en_txdrv_spare_l0_5to4 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_en_txdrv_spare_l0_9to6 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_en_txelecidle_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_en_txpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_en_txrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_en_txwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_ovr_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_ovr_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_ovr_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_ovr_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_ovr_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_ovr_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_ovr_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_ovr_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_ovr_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_ovr_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_ovr_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_ovr_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_ovr_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_ovr_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_ovr_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_ovr_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_ur_ovr_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux3_vsr_mode == UX3_VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux_q_ckmux_cpu_attr == CKMUX_CPU_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux_q_i_pll0_hz == 36'd250000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux_q_i_pll1_hz == 36'd250000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux_q_i_pll2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux_quad_instance == UX_QUAD_INSTANCE_ONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.ux_speed_grade == UX_SPEED_GRADE_DASH2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.all_ux_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.bot_f_fastest_reconfig_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.bot_refclk_reconfig_span == BOT_REFCLK_RECONFIG_SPAN_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.bot_syspll_refclk_output_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.cdrdiv_offchip_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ch1_ch0_master_pll_pair_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ch3_ch2_master_pll_pair_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.clkrx_bot_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.clkrx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.clkrx_top_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_bot_refclk_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_bot_syspll_refclk_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_ch1_ch0_master_pll_pair_cascade_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_ch3_ch2_master_pll_pair_cascade_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_fastest_reconfig_refclk_global_refclk_0_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_fastest_reconfig_refclk_global_refclk_1_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_fastest_reconfig_refclk_global_refclk_2_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_fastest_reconfig_refclk_global_refclk_3_hz == 40'd800000001
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_fastest_reconfig_refclk_regional_refclk_0_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_fastest_reconfig_refclk_regional_refclk_1_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_full_quad_master_pll_cascade_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_global_refclk_0_bot_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_global_refclk_0_bot_right_top_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_global_refclk_0_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_global_refclk_0_top_right_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_global_refclk_1_bot_left_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_global_refclk_1_bot_right_top_left_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_global_refclk_1_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_global_refclk_1_top_right_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_global_refclk_2_bot_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_global_refclk_2_bot_right_top_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_global_refclk_2_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_global_refclk_2_top_right_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_global_refclk_3_bot_left_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_global_refclk_3_bot_right_top_left_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_global_refclk_3_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_global_refclk_3_top_right_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_local_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_regional_refclk_0_bot_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_regional_refclk_0_bot_right_top_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_regional_refclk_0_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_regional_refclk_0_top_right_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_regional_refclk_1_bot_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_regional_refclk_1_bot_right_top_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_regional_refclk_1_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_regional_refclk_1_top_right_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_regional_refclk_2_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_regional_refclk_3_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_top_refclk_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.f_top_syspll_refclk_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.fabric_iram_fabric_iram_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.global_refclk_0_bot_control == GLOBAL_REFCLK_0_BOT_CONTROL_ENABLE_T2R_B2L_NO_PASS_THRU
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.global_refclk_0_bot_power_mode == GLOBAL_REFCLK_0_BOT_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.global_refclk_0_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.global_refclk_0_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.global_refclk_0_top_control == GLOBAL_REFCLK_0_TOP_CONTROL_ENABLE_T2R_B2L_NO_PASS_THRU
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.global_refclk_0_top_power_mode == GLOBAL_REFCLK_0_TOP_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.global_refclk_1_bot_control == GLOBAL_REFCLK_1_BOT_CONTROL_ENABLE_R2L_L2B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.global_refclk_1_bot_power_mode == GLOBAL_REFCLK_1_BOT_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.global_refclk_1_left_adjacent_active == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.global_refclk_1_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.global_refclk_1_top_control == GLOBAL_REFCLK_1_TOP_CONTROL_ENABLE_P2L_L2B_P2R_R2T
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.global_refclk_1_top_power_mode == GLOBAL_REFCLK_1_TOP_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.global_refclk_2_bot_control == GLOBAL_REFCLK_2_BOT_CONTROL_ENABLE_T2R_B2L_NO_PASS_THRU
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.global_refclk_2_bot_power_mode == GLOBAL_REFCLK_2_BOT_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.global_refclk_2_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.global_refclk_2_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.global_refclk_2_top_control == GLOBAL_REFCLK_2_TOP_CONTROL_ENABLE_T2R_B2L_NO_PASS_THRU
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.global_refclk_2_top_power_mode == GLOBAL_REFCLK_2_TOP_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.global_refclk_3_bot_control == GLOBAL_REFCLK_3_BOT_CONTROL_ENABLE_R2L_L2B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.global_refclk_3_bot_power_mode == GLOBAL_REFCLK_3_BOT_POWER_MODE_HIGH_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.global_refclk_3_left_adjacent_active == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.global_refclk_3_right_adjacent_active == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.global_refclk_3_top_control == GLOBAL_REFCLK_3_TOP_CONTROL_ENABLE_L2R_R2T
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.global_refclk_3_top_power_mode == GLOBAL_REFCLK_3_TOP_POWER_MODE_HIGH_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.hard_all_ux_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.local_clock_line_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.quad_global_refclk_0_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.quad_global_refclk_1_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.quad_global_refclk_2_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.quad_global_refclk_3_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.quad_regional_refclk_0_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.quad_regional_refclk_1_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.regional_refclk_0_bot_control == REGIONAL_REFCLK_0_BOT_CONTROL_ENABLE_T2R_B2L_NO_PASS_THRU
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.regional_refclk_0_bot_power_mode == REGIONAL_REFCLK_0_BOT_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.regional_refclk_0_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.regional_refclk_0_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.regional_refclk_0_top_control == REGIONAL_REFCLK_0_TOP_CONTROL_ENABLE_T2R_B2L_NO_PASS_THRU
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.regional_refclk_0_top_power_mode == REGIONAL_REFCLK_0_TOP_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.regional_refclk_1_bot_control == REGIONAL_REFCLK_1_BOT_CONTROL_ENABLE_T2R_B2L_NO_PASS_THRU
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.regional_refclk_1_bot_power_mode == REGIONAL_REFCLK_1_BOT_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.regional_refclk_1_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.regional_refclk_1_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.regional_refclk_1_top_control == REGIONAL_REFCLK_1_TOP_CONTROL_ENABLE_T2R_B2L_NO_PASS_THRU
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.regional_refclk_1_top_power_mode == REGIONAL_REFCLK_1_TOP_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_fw_loader_cfg_data_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_fw_loader_cfg_fw_loader_en_attr == SCMNG_FW_LOADER_CFG_FW_LOADER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_fw_loader_cfg_offset_addr_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_fw_loader_cfg_single_mode_en_attr == SCMNG_FW_LOADER_CFG_SINGLE_MODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_ahb_non_posted_write_attr == SCMNG_PM_CFG_AHB_NON_POSTED_WRITE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_an_done_lane0_attr == SCMNG_PM_CFG_AN_DONE_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_an_done_lane1_attr == SCMNG_PM_CFG_AN_DONE_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_an_done_lane2_attr == SCMNG_PM_CFG_AN_DONE_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_an_done_lane3_attr == SCMNG_PM_CFG_AN_DONE_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_apb_broadcast_feature_en_attr == SCMNG_PM_CFG_APB_BROADCAST_FEATURE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_apb_broadcast_type_attr == SCMNG_PM_CFG_APB_BROADCAST_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_apb_security_check_en_attr == SCMNG_PM_CFG_APB_SECURITY_CHECK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_cfg_top_head_visactl0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_cfg_top_head_visactl1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_cfg_top_head_visactl2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_cfg_top_head_visactl3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_cfg_top_head_visaenable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_cpi_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_cpi_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_cpi_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_ecc_double_attr == SCMNG_PM_CFG_ECC_DOUBLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_error_l0_attr == SCMNG_PM_CFG_ERROR_L0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_error_l1_attr == SCMNG_PM_CFG_ERROR_L1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_error_l2_attr == SCMNG_PM_CFG_ERROR_L2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_error_l3_attr == SCMNG_PM_CFG_ERROR_L3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_fabric_wd_counter_max_attr == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_link_mng_cpi_cmd_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_link_mng_cpi_data_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_one_bit_error_corrected_attr == SCMNG_PM_CFG_ONE_BIT_ERROR_CORRECTED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_phy_cpi_cmd_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_phy_cpi_data_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_phy_owner_cpi_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_probe_addr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_rx_ready_lane0_attr == SCMNG_PM_CFG_RX_READY_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_rx_ready_lane1_attr == SCMNG_PM_CFG_RX_READY_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_rx_ready_lane2_attr == SCMNG_PM_CFG_RX_READY_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_rx_ready_lane3_attr == SCMNG_PM_CFG_RX_READY_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_sw_reserved_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_trn_done_lane0_attr == SCMNG_PM_CFG_TRN_DONE_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_trn_done_lane1_attr == SCMNG_PM_CFG_TRN_DONE_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_trn_done_lane2_attr == SCMNG_PM_CFG_TRN_DONE_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_trn_done_lane3_attr == SCMNG_PM_CFG_TRN_DONE_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_tx_ready_lane0_attr == SCMNG_PM_CFG_TX_READY_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_tx_ready_lane1_attr == SCMNG_PM_CFG_TX_READY_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_tx_ready_lane2_attr == SCMNG_PM_CFG_TX_READY_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_tx_ready_lane3_attr == SCMNG_PM_CFG_TX_READY_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_visa_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_visa_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.scmng_pm_cfg_visa_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_aon_cfg_ckgate_disable_attr == SERDES_IP_CLKRX_BOT_AON_CFG_CKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_aon_cfg_cmn_powerup_attr == SERDES_IP_CLKRX_BOT_AON_CFG_CMN_POWERUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_aon_cfg_cmn_powerup_override_en_attr == SERDES_IP_CLKRX_BOT_AON_CFG_CMN_POWERUP_OVERRIDE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_aon_cfg_cmntstbus_addr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_aon_cfg_synth_force_pup_attr == SERDES_IP_CLKRX_BOT_AON_CFG_SYNTH_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_aon_cfg_synth_force_pup_en_attr == SERDES_IP_CLKRX_BOT_AON_CFG_SYNTH_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_aprobe_bot_en_attr == SERDES_IP_CLKRX_BOT_CFG_APROBE_BOT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_aprobe_left_en_attr == SERDES_IP_CLKRX_BOT_CFG_APROBE_LEFT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_aprobe_right_en_attr == SERDES_IP_CLKRX_BOT_CFG_APROBE_RIGHT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_aprobe_top_en_attr == SERDES_IP_CLKRX_BOT_CFG_APROBE_TOP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmn_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmn_pg_disable_attr == SERDES_IP_CLKRX_BOT_CFG_CMN_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmn_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnaprobeclkrx_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnbs_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnbshihyst_attr == SERDES_IP_CLKRX_BOT_CFG_CMNBSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalptr_pstate_refckregopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalptr_pstate_swfabricregopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalptr_quad_refckregopampoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalptr_quad_swfabricregopampoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffset_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREFCKREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffsetfsm_clear_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREFCKREGOPAMPOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffsetfsm_init_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREFCKREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffsetfsm_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREFCKREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffsetfsm_req_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREFCKREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREFCKREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffsetfsmout_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREFCKREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffsetmeas_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREFCKREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffsetmeas_req_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREFCKREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_finish_side_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_invert_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_round_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_runcount_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_signmagen_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetmeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetmeas_validdlycount_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffset_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALSWFABRICREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffsetfsm_clear_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffsetfsm_init_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffsetfsm_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffsetfsm_req_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffsetfsmout_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffsetmeas_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALSWFABRICREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffsetmeas_req_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALSWFABRICREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrx_bypass_en_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRX_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxcdrdiv_bot_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXCDRDIV_BOT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxcdrdiv_input_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxcdrdiv_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXCDRDIV_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxcdrdiv_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXCDRDIV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxcdrdiv_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXCDRDIV_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxcdrdiv_top_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXCDRDIV_TOP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbuf_buf2dpma_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXREFCKBUF_BUF2DPMA_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbuf_cml_ena_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXREFCKBUF_CML_ENA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbuf_core_cmos_ena_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXREFCKBUF_CORE_CMOS_ENA_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbuf_hs_cmos_ena_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXREFCKBUF_HS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbuf_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXREFCKBUF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbuf_powersave_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXREFCKBUF_POWERSAVE_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbuf_termcal_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbuf_termhiz_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXREFCKBUF_TERMHIZ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbufsel_hs_ls_b_path_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXREFCKBUFSEL_HS_LS_B_PATH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbufsel_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXREFCKBUFSEL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxspare_attr == 16'd61440
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxsynthdiv_bot_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXSYNTHDIV_BOT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxsynthdiv_input_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxsynthdiv_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXSYNTHDIV_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxsynthdiv_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXSYNTHDIV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxsynthdiv_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXSYNTHDIV_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxsynthdiv_top_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXSYNTHDIV_TOP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmndprobe_addr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnfsm_cken_ovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnfsm_cken_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_changeref_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_REFCK_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_changeref_val_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_REFCK_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_en_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_REFCK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_smpltime_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refckm_charge_up_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_REFCKM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refckm_pull_dn_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_REFCKM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refckm_sense_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_REFCKM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refckp_charge_up_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_REFCKP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refckp_pull_dn_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_REFCKP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refckp_sense_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_REFCKP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_cdrdivsel_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_hsrefsel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_hsrefsel_powersave_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_HSREFSEL_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_lcrefsel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_lcrefsel_powersave_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_LCREFSEL_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_pad2cmos_ana_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_PAD2CMOS_ANA_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_pad2cmos_dig_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_PAD2CMOS_DIG_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel0_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel0_powersave_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_REFSEL0_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel1_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel1_powersave_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_REFSEL1_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel2_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel2_powersave_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_REFSEL2_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel3_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel3_powersave_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_REFSEL3_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel4_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel4_powersave_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_REFSEL4_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel5_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel5_powersave_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_REFSEL5_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_synthdivsel_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_termhiz_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_TERMHIZ_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrefckctrl_auto_powerdown_en_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREFCKCTRL_AUTO_POWERDOWN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrefckctrl_cml_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREFCKCTRL_CML_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrefckctrl_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREFCKCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrefckreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s0q0_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s0q1_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s0q2_attr == 10'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s0q3_attr == 10'd250
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s0q4_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s0q5_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s0q6_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s0q7_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s1q0_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s1q1_attr == 10'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s1q2_attr == 10'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s1q3_attr == 10'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s1q4_attr == 10'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s1q5_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s1q6_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s1q7_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s2q0_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s2q1_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s2q2_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s2q3_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s2q4_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s2q5_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s2q6_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s2q7_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_en_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_dn_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_up_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_up_ptr1_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_dn_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_up_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_up_ptr1_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_aetrcmn_refckregpwrupacc_ovr_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_AETRCMN_REFCKREGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_aetrcmn_refckregpwrupacc_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_AETRCMN_REFCKREGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_aetrcmn_swfabricregpwrupacc_ovr_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_AETRCMN_SWFABRICREGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_aetrcmn_swfabricregpwrupacc_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_AETRCMN_SWFABRICREGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdcmn_refckbuf_ovr_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdcmn_refckbuf_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdcmn_refckreg_ovr_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDCMN_REFCKREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdcmn_refckreg_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDCMN_REFCKREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdcmn_swfabric_ovr_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDCMN_SWFABRIC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdcmn_swfabric_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDCMN_SWFABRIC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdcmn_swfabricreg_ovr_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDCMN_SWFABRICREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdcmn_swfabricreg_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDCMN_SWFABRICREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdrefck_ntl_b_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDREFCK_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdrefck_ntl_ovr_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDREFCK_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_arstcmn_refckregreset_ovr_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_ARSTCMN_REFCKREGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_arstcmn_refckregreset_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_ARSTCMN_REFCKREGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_arstcmn_swfabricregreset_ovr_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_ARSTCMN_SWFABRICREGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_arstcmn_swfabricregreset_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_ARSTCMN_SWFABRICREGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref0_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF0_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref0_powersave_b_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF0_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref0_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF0_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref0_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref1_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF1_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref1_powersave_b_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF1_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref1_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF1_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref1_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref2_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF2_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref2_powersave_b_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF2_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref2_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF2_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref2_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref3_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF3_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref3_powersave_b_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF3_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref3_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF3_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref3_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref4_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF4_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref4_powersave_b_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF4_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref4_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF4_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref4_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref5_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF5_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref5_powersave_b_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF5_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref5_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF5_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref5_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref6_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF6_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref6_powersave_b_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF6_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref6_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF6_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref6_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref7_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF7_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref7_powersave_b_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF7_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref7_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF7_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref7_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabricreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_egress_override_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_EGRESS_OVERRIDE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_egress_override_val_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_p_vdd_pwrgood_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_P_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_p_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_P_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_pa_vdd_ehv_pwrgood_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_pa_vdd_ehv_pwrgood_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_pa_vdd_pwrgood_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_PA_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_pa_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_PA_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_burnin_mode_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_BURNIN_MODE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_burnin_mode_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_BURNIN_MODE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_cdrdivsel_nt_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_cdrdivsel_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_CDRDIVSEL_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_cmnclkrxrefckbufsel_hs_ls_b_path_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_CMNCLKRXREFCKBUFSEL_HS_LS_B_PATH_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_cmnclkrxrefckbufsel_hs_ls_b_path_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_CMNCLKRXREFCKBUFSEL_HS_LS_B_PATH_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_hsrefsel_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_hsrefsel_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_HSREFSEL_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_hsrefsel_powersave_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_HSREFSEL_POWERSAVE_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_hsrefsel_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_HSREFSEL_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_jtagid_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_JTAGID_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_jtagslvid_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_JTAGSLVID_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_pad2cmos_ana_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_PAD2CMOS_ANA_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_pad2cmos_ana_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_PAD2CMOS_ANA_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_pad2cmos_dig_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_PAD2CMOS_DIG_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_pad2cmos_dig_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_PAD2CMOS_DIG_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_powerup_a_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_POWERUP_A_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_powerup_a_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_POWERUP_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel0_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel0_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel0_powersave_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL0_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel0_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL0_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel1_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel1_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL1_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel1_powersave_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL1_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel1_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL1_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel2_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel2_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL2_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel2_powersave_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL2_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel2_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL2_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel3_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel3_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL3_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel3_powersave_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL3_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel3_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL3_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel4_nt_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel4_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL4_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel4_powersave_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL4_POWERSAVE_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel4_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL4_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel5_nt_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel5_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL5_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel5_powersave_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL5_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel5_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL5_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_synthdivsel_nt_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_synthdivsel_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_SYNTHDIVSEL_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_termhiz_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_TERMHIZ_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_termhiz_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_TERMHIZ_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_vdd_ehv_sel_nt_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_vdd_ehv_sel_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_VDD_EHV_SEL_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_spare_nt_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_spare_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_SPARE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_idat_txbscan_n_attr == SERDES_IP_CLKRX_BOT_IF_CFG_IDAT_TXBSCAN_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_idat_txbscan_n_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_IDAT_TXBSCAN_N_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_idat_txbscan_p_attr == SERDES_IP_CLKRX_BOT_IF_CFG_IDAT_TXBSCAN_P_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_idat_txbscan_p_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_IDAT_TXBSCAN_P_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_irst_ref_por_b_a_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_IRST_REF_POR_B_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_irst_ref_tstbus_b_a_attr == SERDES_IP_CLKRX_BOT_IF_CFG_IRST_REF_TSTBUS_B_A_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_bot_if_cfg_irst_ref_tstbus_b_a_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_IRST_REF_TSTBUS_B_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_aon_cfg_ckgate_disable_attr == SERDES_IP_CLKRX_TOP_AON_CFG_CKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_aon_cfg_cmn_powerup_attr == SERDES_IP_CLKRX_TOP_AON_CFG_CMN_POWERUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_aon_cfg_cmn_powerup_override_en_attr == SERDES_IP_CLKRX_TOP_AON_CFG_CMN_POWERUP_OVERRIDE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_aon_cfg_cmntstbus_addr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_aon_cfg_synth_force_pup_attr == SERDES_IP_CLKRX_TOP_AON_CFG_SYNTH_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_aon_cfg_synth_force_pup_en_attr == SERDES_IP_CLKRX_TOP_AON_CFG_SYNTH_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_aprobe_bot_en_attr == SERDES_IP_CLKRX_TOP_CFG_APROBE_BOT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_aprobe_left_en_attr == SERDES_IP_CLKRX_TOP_CFG_APROBE_LEFT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_aprobe_right_en_attr == SERDES_IP_CLKRX_TOP_CFG_APROBE_RIGHT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_aprobe_top_en_attr == SERDES_IP_CLKRX_TOP_CFG_APROBE_TOP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmn_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmn_pg_disable_attr == SERDES_IP_CLKRX_TOP_CFG_CMN_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmn_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnaprobeclkrx_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnbs_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnbshihyst_attr == SERDES_IP_CLKRX_TOP_CFG_CMNBSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalptr_pstate_refckregopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalptr_pstate_swfabricregopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalptr_quad_refckregopampoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalptr_quad_swfabricregopampoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffset_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREFCKREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffsetfsm_clear_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREFCKREGOPAMPOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffsetfsm_init_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREFCKREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffsetfsm_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREFCKREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffsetfsm_req_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREFCKREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREFCKREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffsetfsmout_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREFCKREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffsetmeas_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREFCKREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffsetmeas_req_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREFCKREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_finish_side_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_invert_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_round_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_runcount_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_signmagen_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetmeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetmeas_validdlycount_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffset_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALSWFABRICREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffsetfsm_clear_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffsetfsm_init_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffsetfsm_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffsetfsm_req_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffsetfsmout_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffsetmeas_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALSWFABRICREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffsetmeas_req_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALSWFABRICREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrx_bypass_en_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRX_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxcdrdiv_bot_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXCDRDIV_BOT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxcdrdiv_input_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxcdrdiv_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXCDRDIV_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxcdrdiv_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXCDRDIV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxcdrdiv_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXCDRDIV_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxcdrdiv_top_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXCDRDIV_TOP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbuf_buf2dpma_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXREFCKBUF_BUF2DPMA_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbuf_cml_ena_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXREFCKBUF_CML_ENA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbuf_core_cmos_ena_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXREFCKBUF_CORE_CMOS_ENA_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbuf_hs_cmos_ena_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXREFCKBUF_HS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbuf_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXREFCKBUF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbuf_powersave_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXREFCKBUF_POWERSAVE_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbuf_termcal_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbuf_termhiz_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXREFCKBUF_TERMHIZ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbufsel_hs_ls_b_path_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXREFCKBUFSEL_HS_LS_B_PATH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbufsel_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXREFCKBUFSEL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxspare_attr == 16'd61440
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxsynthdiv_bot_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXSYNTHDIV_BOT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxsynthdiv_input_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxsynthdiv_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXSYNTHDIV_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxsynthdiv_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXSYNTHDIV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxsynthdiv_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXSYNTHDIV_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxsynthdiv_top_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXSYNTHDIV_TOP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmndprobe_addr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnfsm_cken_ovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnfsm_cken_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_changeref_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_REFCK_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_changeref_val_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_REFCK_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_en_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_REFCK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_smpltime_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refckm_charge_up_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_REFCKM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refckm_pull_dn_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_REFCKM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refckm_sense_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_REFCKM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refckp_charge_up_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_REFCKP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refckp_pull_dn_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_REFCKP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refckp_sense_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_REFCKP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnref_cdrdivsel_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnref_hsrefsel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnref_hsrefsel_powersave_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_HSREFSEL_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnref_lcrefsel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnref_lcrefsel_powersave_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_LCREFSEL_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnref_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnref_pad2cmos_ana_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_PAD2CMOS_ANA_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnref_pad2cmos_dig_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_PAD2CMOS_DIG_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel0_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel0_powersave_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_REFSEL0_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel1_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel1_powersave_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_REFSEL1_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel2_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel2_powersave_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_REFSEL2_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel3_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel3_powersave_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_REFSEL3_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel4_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel4_powersave_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_REFSEL4_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel5_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel5_powersave_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_REFSEL5_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnref_synthdivsel_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnref_termhiz_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_TERMHIZ_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrefckctrl_auto_powerdown_en_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREFCKCTRL_AUTO_POWERDOWN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrefckctrl_cml_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREFCKCTRL_CML_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrefckctrl_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREFCKCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrefckreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s0q0_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s0q1_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s0q2_attr == 10'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s0q3_attr == 10'd250
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s0q4_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s0q5_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s0q6_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s0q7_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s1q0_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s1q1_attr == 10'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s1q2_attr == 10'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s1q3_attr == 10'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s1q4_attr == 10'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s1q5_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s1q6_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s1q7_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s2q0_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s2q1_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s2q2_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s2q3_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s2q4_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s2q5_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s2q6_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s2q7_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_en_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_dn_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_up_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_up_ptr1_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_dn_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_up_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_up_ptr1_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_aetrcmn_refckregpwrupacc_ovr_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_AETRCMN_REFCKREGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_aetrcmn_refckregpwrupacc_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_AETRCMN_REFCKREGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_aetrcmn_swfabricregpwrupacc_ovr_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_AETRCMN_SWFABRICREGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_aetrcmn_swfabricregpwrupacc_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_AETRCMN_SWFABRICREGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdcmn_refckbuf_ovr_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdcmn_refckbuf_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdcmn_refckreg_ovr_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDCMN_REFCKREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdcmn_refckreg_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDCMN_REFCKREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdcmn_swfabric_ovr_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDCMN_SWFABRIC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdcmn_swfabric_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDCMN_SWFABRIC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdcmn_swfabricreg_ovr_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDCMN_SWFABRICREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdcmn_swfabricreg_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDCMN_SWFABRICREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdrefck_ntl_b_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDREFCK_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdrefck_ntl_ovr_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDREFCK_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_arstcmn_refckregreset_ovr_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_ARSTCMN_REFCKREGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_arstcmn_refckregreset_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_ARSTCMN_REFCKREGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_arstcmn_swfabricregreset_ovr_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_ARSTCMN_SWFABRICREGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_arstcmn_swfabricregreset_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_ARSTCMN_SWFABRICREGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref0_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF0_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref0_powersave_b_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF0_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref0_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF0_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref0_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref1_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF1_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref1_powersave_b_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF1_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref1_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF1_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref1_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref2_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF2_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref2_powersave_b_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF2_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref2_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF2_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref2_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref3_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF3_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref3_powersave_b_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF3_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref3_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF3_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref3_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref4_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF4_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref4_powersave_b_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF4_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref4_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF4_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref4_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref5_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF5_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref5_powersave_b_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF5_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref5_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF5_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref5_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref6_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF6_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref6_powersave_b_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF6_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref6_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF6_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref6_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref7_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF7_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref7_powersave_b_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF7_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref7_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF7_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref7_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabricreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_egress_override_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_EGRESS_OVERRIDE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_egress_override_val_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_p_vdd_pwrgood_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_P_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_p_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_P_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_pa_vdd_ehv_pwrgood_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_pa_vdd_ehv_pwrgood_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_pa_vdd_pwrgood_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_PA_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_pa_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_PA_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_burnin_mode_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_BURNIN_MODE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_burnin_mode_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_BURNIN_MODE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_cdrdivsel_nt_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_cdrdivsel_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_CDRDIVSEL_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_cmnclkrxrefckbufsel_hs_ls_b_path_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_CMNCLKRXREFCKBUFSEL_HS_LS_B_PATH_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_cmnclkrxrefckbufsel_hs_ls_b_path_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_CMNCLKRXREFCKBUFSEL_HS_LS_B_PATH_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_hsrefsel_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_hsrefsel_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_HSREFSEL_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_hsrefsel_powersave_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_HSREFSEL_POWERSAVE_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_hsrefsel_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_HSREFSEL_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_jtagid_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_JTAGID_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_jtagslvid_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_JTAGSLVID_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_pad2cmos_ana_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_PAD2CMOS_ANA_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_pad2cmos_ana_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_PAD2CMOS_ANA_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_pad2cmos_dig_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_PAD2CMOS_DIG_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_pad2cmos_dig_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_PAD2CMOS_DIG_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_powerup_a_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_POWERUP_A_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_powerup_a_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_POWERUP_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel0_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel0_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel0_powersave_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL0_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel0_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL0_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel1_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel1_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL1_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel1_powersave_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL1_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel1_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL1_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel2_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel2_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL2_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel2_powersave_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL2_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel2_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL2_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel3_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel3_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL3_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel3_powersave_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL3_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel3_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL3_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel4_nt_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel4_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL4_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel4_powersave_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL4_POWERSAVE_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel4_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL4_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel5_nt_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel5_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL5_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel5_powersave_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL5_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel5_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL5_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_synthdivsel_nt_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_synthdivsel_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_SYNTHDIVSEL_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_termhiz_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_TERMHIZ_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_termhiz_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_TERMHIZ_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_vdd_ehv_sel_nt_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_vdd_ehv_sel_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_VDD_EHV_SEL_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_spare_nt_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_spare_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_SPARE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_idat_txbscan_n_attr == SERDES_IP_CLKRX_TOP_IF_CFG_IDAT_TXBSCAN_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_idat_txbscan_n_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_IDAT_TXBSCAN_N_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_idat_txbscan_p_attr == SERDES_IP_CLKRX_TOP_IF_CFG_IDAT_TXBSCAN_P_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_idat_txbscan_p_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_IDAT_TXBSCAN_P_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_irst_ref_por_b_a_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_IRST_REF_POR_B_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_irst_ref_tstbus_b_a_attr == SERDES_IP_CLKRX_TOP_IF_CFG_IRST_REF_TSTBUS_B_A_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_clkrx_top_if_cfg_irst_ref_tstbus_b_a_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_IRST_REF_TSTBUS_B_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l0_cfg_ckgate_disable_attr == SERDES_IP_CMN_AON_L0_CFG_CKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l0_cfg_cmn_force_pup_attr == SERDES_IP_CMN_AON_L0_CFG_CMN_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l0_cfg_cmn_force_pup_en_attr == SERDES_IP_CMN_AON_L0_CFG_CMN_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l0_cfg_cmn_rst_b_attr == SERDES_IP_CMN_AON_L0_CFG_CMN_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l0_cfg_cmn_rst_en_attr == SERDES_IP_CMN_AON_L0_CFG_CMN_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l0_cfg_cmnclk_ctrl_attr == SERDES_IP_CMN_AON_L0_CFG_CMNCLK_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l0_cfg_cmnclkdiv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l0_cfg_cmnfsm_pmu_req_attr == SERDES_IP_CMN_AON_L0_CFG_CMNFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l0_cfg_cmnfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L0_CFG_CMNFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l0_cfg_cmntstbus_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcfast_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcfast_force_pup_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCFAST_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcfast_force_pup_en_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCFAST_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcfast_ignore_mode_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCFAST_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcfast_rst_b_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCFAST_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcfast_rst_en_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCFAST_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcfastfsm_pmu_req_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCFASTFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcfastfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCFASTFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcmed_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcmed_force_pup_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCMED_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcmed_force_pup_en_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCMED_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcmed_ignore_mode_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCMED_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcmed_rst_b_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCMED_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcmed_rst_en_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCMED_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcmedfsm_pmu_req_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCMEDFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcmedfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCMEDFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcslow_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcslow_force_pup_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCSLOW_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcslow_force_pup_en_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCSLOW_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcslow_ignore_mode_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCSLOW_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcslow_rst_b_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCSLOW_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcslow_rst_en_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCSLOW_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcslowfsm_pmu_req_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCSLOWFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcslowfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCSLOWFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l0_cfg_tstbus_rst_bypass_attr == SERDES_IP_CMN_AON_L0_CFG_TSTBUS_RST_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l0_cfg_tstbus_rst_bypass_en_attr == SERDES_IP_CMN_AON_L0_CFG_TSTBUS_RST_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l1_cfg_ckgate_disable_attr == SERDES_IP_CMN_AON_L1_CFG_CKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l1_cfg_cmn_force_pup_attr == SERDES_IP_CMN_AON_L1_CFG_CMN_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l1_cfg_cmn_force_pup_en_attr == SERDES_IP_CMN_AON_L1_CFG_CMN_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l1_cfg_cmn_rst_b_attr == SERDES_IP_CMN_AON_L1_CFG_CMN_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l1_cfg_cmn_rst_en_attr == SERDES_IP_CMN_AON_L1_CFG_CMN_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l1_cfg_cmnclk_ctrl_attr == SERDES_IP_CMN_AON_L1_CFG_CMNCLK_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l1_cfg_cmnclkdiv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l1_cfg_cmnfsm_pmu_req_attr == SERDES_IP_CMN_AON_L1_CFG_CMNFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l1_cfg_cmnfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L1_CFG_CMNFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l1_cfg_cmntstbus_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcfast_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcfast_force_pup_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCFAST_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcfast_force_pup_en_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCFAST_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcfast_ignore_mode_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCFAST_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcfast_rst_b_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCFAST_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcfast_rst_en_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCFAST_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcfastfsm_pmu_req_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCFASTFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcfastfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCFASTFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcmed_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcmed_force_pup_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCMED_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcmed_force_pup_en_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCMED_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcmed_ignore_mode_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCMED_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcmed_rst_b_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCMED_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcmed_rst_en_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCMED_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcmedfsm_pmu_req_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCMEDFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcmedfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCMEDFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcslow_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcslow_force_pup_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCSLOW_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcslow_force_pup_en_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCSLOW_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcslow_ignore_mode_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCSLOW_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcslow_rst_b_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCSLOW_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcslow_rst_en_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCSLOW_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcslowfsm_pmu_req_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCSLOWFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcslowfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCSLOWFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l1_cfg_tstbus_rst_bypass_attr == SERDES_IP_CMN_AON_L1_CFG_TSTBUS_RST_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l1_cfg_tstbus_rst_bypass_en_attr == SERDES_IP_CMN_AON_L1_CFG_TSTBUS_RST_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l2_cfg_ckgate_disable_attr == SERDES_IP_CMN_AON_L2_CFG_CKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l2_cfg_cmn_force_pup_attr == SERDES_IP_CMN_AON_L2_CFG_CMN_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l2_cfg_cmn_force_pup_en_attr == SERDES_IP_CMN_AON_L2_CFG_CMN_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l2_cfg_cmn_rst_b_attr == SERDES_IP_CMN_AON_L2_CFG_CMN_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l2_cfg_cmn_rst_en_attr == SERDES_IP_CMN_AON_L2_CFG_CMN_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l2_cfg_cmnclk_ctrl_attr == SERDES_IP_CMN_AON_L2_CFG_CMNCLK_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l2_cfg_cmnclkdiv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l2_cfg_cmnfsm_pmu_req_attr == SERDES_IP_CMN_AON_L2_CFG_CMNFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l2_cfg_cmnfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L2_CFG_CMNFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l2_cfg_cmntstbus_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcfast_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcfast_force_pup_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCFAST_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcfast_force_pup_en_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCFAST_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcfast_ignore_mode_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCFAST_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcfast_rst_b_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCFAST_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcfast_rst_en_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCFAST_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcfastfsm_pmu_req_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCFASTFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcfastfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCFASTFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcmed_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcmed_force_pup_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCMED_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcmed_force_pup_en_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCMED_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcmed_ignore_mode_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCMED_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcmed_rst_b_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCMED_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcmed_rst_en_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCMED_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcmedfsm_pmu_req_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCMEDFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcmedfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCMEDFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcslow_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcslow_force_pup_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCSLOW_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcslow_force_pup_en_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCSLOW_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcslow_ignore_mode_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCSLOW_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcslow_rst_b_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCSLOW_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcslow_rst_en_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCSLOW_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcslowfsm_pmu_req_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCSLOWFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcslowfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCSLOWFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l2_cfg_tstbus_rst_bypass_attr == SERDES_IP_CMN_AON_L2_CFG_TSTBUS_RST_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l2_cfg_tstbus_rst_bypass_en_attr == SERDES_IP_CMN_AON_L2_CFG_TSTBUS_RST_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l3_cfg_ckgate_disable_attr == SERDES_IP_CMN_AON_L3_CFG_CKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l3_cfg_cmn_force_pup_attr == SERDES_IP_CMN_AON_L3_CFG_CMN_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l3_cfg_cmn_force_pup_en_attr == SERDES_IP_CMN_AON_L3_CFG_CMN_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l3_cfg_cmn_rst_b_attr == SERDES_IP_CMN_AON_L3_CFG_CMN_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l3_cfg_cmn_rst_en_attr == SERDES_IP_CMN_AON_L3_CFG_CMN_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l3_cfg_cmnclk_ctrl_attr == SERDES_IP_CMN_AON_L3_CFG_CMNCLK_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l3_cfg_cmnclkdiv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l3_cfg_cmnfsm_pmu_req_attr == SERDES_IP_CMN_AON_L3_CFG_CMNFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l3_cfg_cmnfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L3_CFG_CMNFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l3_cfg_cmntstbus_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcfast_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcfast_force_pup_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCFAST_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcfast_force_pup_en_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCFAST_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcfast_ignore_mode_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCFAST_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcfast_rst_b_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCFAST_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcfast_rst_en_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCFAST_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcfastfsm_pmu_req_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCFASTFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcfastfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCFASTFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcmed_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcmed_force_pup_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCMED_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcmed_force_pup_en_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCMED_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcmed_ignore_mode_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCMED_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcmed_rst_b_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCMED_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcmed_rst_en_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCMED_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcmedfsm_pmu_req_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCMEDFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcmedfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCMEDFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcslow_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcslow_force_pup_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCSLOW_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcslow_force_pup_en_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCSLOW_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcslow_ignore_mode_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCSLOW_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcslow_rst_b_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCSLOW_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcslow_rst_en_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCSLOW_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcslowfsm_pmu_req_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCSLOWFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcslowfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCSLOWFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l3_cfg_tstbus_rst_bypass_attr == SERDES_IP_CMN_AON_L3_CFG_TSTBUS_RST_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_aon_l3_cfg_tstbus_rst_bypass_en_attr == SERDES_IP_CMN_AON_L3_CFG_TSTBUS_RST_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_bti_div_attr == 7'd54
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_bti_div_rst_attr == SERDES_IP_CMN_L0_CFG_BTI_DIV_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_bti_en_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_bti_static_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmn_pg_disable_attr == SERDES_IP_CMN_L0_CFG_CMN_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmn_scratch_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnadc_req_attr == SERDES_IP_CMN_L0_CFG_CMNADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnapb2strbbridgecfg_acc_ctrl_field_mask_write_en_attr == SERDES_IP_CMN_L0_CFG_CMNAPB2STRBBRIDGECFG_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnapb2strbbridgecfg_force_state_en_attr == SERDES_IP_CMN_L0_CFG_CMNAPB2STRBBRIDGECFG_FORCE_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnapb2strbbridgecfg_force_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnapb2strbbridgecfg_stbl_time_aftr_strb_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnapb2strbbridgecfg_stbl_time_bfr_strb_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnapb2strbbridgecfg_strb_pulse_width_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnapbmaster_timeout_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobe_addr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobe_lastmux_isolate_attr == SERDES_IP_CMN_L0_CFG_CMNAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobeadc_current_direction_attr == SERDES_IP_CMN_L0_CFG_CMNAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobeadc_resistor_enable_attr == SERDES_IP_CMN_L0_CFG_CMNAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobedac_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobedac_en_attr == SERDES_IP_CMN_L0_CFG_CMNAPROBEDAC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobedacctrl_block_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobedacctrl_en_attr == SERDES_IP_CMN_L0_CFG_CMNAPROBEDACCTRL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobedacctrl_mask_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobedacctrl_rotate_left_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobedacctrl_tstbus_clkdiv_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnbias_icc20uadj_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnbias_icc80uadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnbias_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnbias_termcal_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnbscan_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnbshihyst_attr == SERDES_IP_CMN_L0_CFG_CMNBSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_bg_en_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_bg_one_step_cal_en_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_fg_inc_cal_en_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_fg_one_step_cal_en_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_finish_side_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_initval_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_invert_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_restore_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_round_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_runcount_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_signmagen_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetmeas_req_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_SYNTHDUTYOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncaldacbg_abort_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncaldacbg_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncaldacbg_ready_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncaldacfsm_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncaldacfsm_synthdutyoffsetfsm_clear_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncaldacfsm_synthdutyoffsetfsm_init_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncaldacfsm_synthdutyoffsetfsm_req_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncaldacsynthdutyoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALDACSYNTHDUTYOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncaldacsynthdutyoffsetfsmout_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALDACSYNTHDUTYOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalptr_pstate_rcomp_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalptr_pstate_synthdutyoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalptr_quad_rcomp_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalptr_quad_regopampoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalptr_quad_synthdutyoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_biastrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_cap_tune_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_divrate_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_mode_select_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_ref_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMP_REF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_rx_term_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMP_RX_TERM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_tfr_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMP_TFR_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_tx_term_pd_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMP_TX_TERM_PD_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_tx_term_pu_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMP_TX_TERM_PU_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_txterm_nmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_txterm_pmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_clear_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_code_delay_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_init_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rcomp_tfr_init_cal_value_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rcomp_tfr_max_value_attr == 4'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rcomp_tfr_min_value_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rcomp_txpd_valid_code_lut_vf00_attr == 32'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rcomp_txpd_valid_code_lut_vf01_attr == 32'd4246868100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rcomp_txpu_valid_code_lut_vf00_attr == 32'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rcomp_txpu_valid_code_lut_vf01_attr == 32'd4246868100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_req_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rx_comp_inv_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_RX_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rx_init_cal_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rx_initval_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rx_step_sign_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_RX_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rx_termcode_delta_lut_attr == 31'd24084352
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tfr_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tfr_comp_inv_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_TFR_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tfr_initval_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tfr_step_sign_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_TFR_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tfr_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_time_comp_config_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_time_lpfsetup_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_time_mode_setup_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_time_reset_release_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_time_sample_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tx_pd_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tx_pd_init_cal_value_attr == 6'd49
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tx_pd_max_value_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tx_pd_min_value_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tx_pu_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tx_pu_init_cal_value_attr == 6'd49
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tx_pu_max_value_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tx_pu_min_value_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_txpd_comp_inv_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_TXPD_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_txpd_initval_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_txpd_step_sign_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_TXPD_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_txpd_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_txpu_comp_inv_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_TXPU_COMP_INV_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_txpu_initval_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_txpu_step_sign_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_TXPU_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_txpu_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_txterm_pmos_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmaster_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPMASTER_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmaster_rx_locovr_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmaster_tfr_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmaster_txpd_locovr_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmaster_txpu_locovr_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmaster_valid_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPMASTER_VALID_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmeas_dlycount_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffset_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_clear_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_finish_side_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_init_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_invert_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_req_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_runcount_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsmout_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetmeas_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetmeas_req_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_avg_en_attr == SERDES_IP_CMN_L0_CFG_CMNCKM_AVG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_clk_en_attr == SERDES_IP_CMN_L0_CFG_CMNCKM_CLK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_continuous_attr == SERDES_IP_CMN_L0_CFG_CMNCKM_CONTINUOUS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_dig_meas_en_attr == SERDES_IP_CMN_L0_CFG_CMNCKM_DIG_MEAS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_dig_meas_err_clr_attr == SERDES_IP_CMN_L0_CFG_CMNCKM_DIG_MEAS_ERR_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_en_attr == SERDES_IP_CMN_L0_CFG_CMNCKM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_max_thr_attr == 25'd33554431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_meas_ck_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_ref_ck_div_ratio_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_result_clr_attr == SERDES_IP_CMN_L0_CFG_CMNCKM_RESULT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_start_attr == SERDES_IP_CMN_L0_CFG_CMNCKM_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_wdt_interval_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_win_thr_ref_attr == 25'd16777215
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnclk_keepalive_en_b_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnclk_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmndmondac_en_attr == SERDES_IP_CMN_L0_CFG_CMNDMONDAC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnfsm_cken_ovr_attr == SERDES_IP_CMN_L0_CFG_CMNFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnfsm_cken_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_aprobe1_charge_up_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_APROBE1_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_aprobe1_pull_dn_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_APROBE1_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_aprobe1_sense_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_APROBE1_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_aprobe2_charge_up_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_APROBE2_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_aprobe2_pull_dn_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_APROBE2_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_aprobe2_sense_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_APROBE2_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_changeref_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_changeref_val_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_en_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_CMN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_ntl_sel_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_CMN_NTL_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_refckm_charge_up_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_REFCKM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_refckm_pull_dn_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_REFCKM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_refckm_sense_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_REFCKM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_refckp_charge_up_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_REFCKP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_refckp_pull_dn_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_REFCKP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_refckp_sense_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_REFCKP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnpcs_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnpcs_ref_sel_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnpcs_ref_sel_tx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnperfmon_compare_val_start_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnperfmon_compare_val_stop_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnperfmon_en_attr == SERDES_IP_CMN_L0_CFG_CMNPERFMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnperfmon_mask_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprefckbufprelut_delta_attr == 15'd32767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprefckbufprelut_init_termcal_rx_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprefckbufprelut_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNRCOMPREFCKBUFPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprefckbufprelut_termcal_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprefcktxdrvprelut_delta_attr == 15'd4672
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprefcktxdrvprelut_init_termcal_rx_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprefcktxdrvprelut_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNRCOMPREFCKTXDRVPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprefcktxdrvprelut_termcal_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprxdfeprelut_delta_attr == 15'd32767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprxdfeprelut_init_termcal_tfr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprxdfeprelut_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNRCOMPRXDFEPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprxdfeprelut_termcal_tfr_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckbuf_cml_ena_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKBUF_CML_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckbuf_hs_cmos_ena_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKBUF_HS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckbuf_hs_ls_b_path_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKBUF_HS_LS_B_PATH_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckbuf_hs_ref_to_cdrdiv_ena_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKBUF_HS_REF_TO_CDRDIV_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckbuf_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKBUF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckbuf_ls_cmos_ena_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKBUF_LS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckbuf_powersave_b_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKBUF_POWERSAVE_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckbuf_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckbuf_termhiz_b_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKBUF_TERMHIZ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckdrv_powersave_en_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKDRV_POWERSAVE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrefcktxdrv_cdrdiv_en_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKTXDRV_CDRDIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrefcktxdrv_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKTXDRV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrefcktxdrv_termcal_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_en_b_attr == SERDES_IP_CMN_L0_CFG_CMNRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_entry3_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s0q2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s0q3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s1q4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s1q5_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s1q6_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s1q7_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s2q0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_entry2_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_entry3_attr == 13'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_entry4_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_entry5_attr == 13'd62
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_entry6_attr == 13'd390
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_entry7_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s0q2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s0q3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s1q1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s1q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s1q5_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s1q7_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s2q0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_term_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_term_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_term_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_term_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_term_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_term_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_term_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_term_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_keepalive_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_keepalive_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_bias_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_bias_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_refckbuf_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_refckbuf_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_refckbuf_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_refckbuf_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_rxref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_rxref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_rxref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_rxref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_synthdutycomp_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_synthdutycomp_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_synthdutycomp_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_synthdutycomp_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_synthlcslowref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_synthlcslowref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_synthlcslowref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_synthlcslowref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_txref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_txref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_txref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_txref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpurst_regreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpurst_regreset_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpurst_regreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrpurst_regreset_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_aetrcmn_regpwrupacc_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_AETRCMN_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_aetrcmn_regpwrupacc_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_AETRCMN_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_adc_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_adc_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_ADC_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_biasicc_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_biasicc_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_ntl_b_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_ntl_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_refckbuf_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_refckbuf_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_reg_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_reg_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_rxref_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_RXREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_rxref_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_RXREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_synthlcslowref_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_SYNTHLCSLOWREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_synthlcslowref_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_SYNTHLCSLOWREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_txref_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_TXREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_txref_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_TXREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_arstcmn_adc_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_ARSTCMN_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_arstcmn_adc_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_ARSTCMN_ADC_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_arstcmn_aprobedac_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_ARSTCMN_APROBEDAC_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_arstcmn_refcktxdrv_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_ARSTCMN_REFCKTXDRV_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_arstcmn_refcktxdrv_hiz_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_ARSTCMN_REFCKTXDRV_HIZ_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_arstcmn_regreset_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_ARSTCMN_REGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_arstcmn_regreset_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_ARSTCMN_REGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_synthdutycomp_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_SYNTHDUTYCOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_synthdutycomp_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_SYNTHDUTYCOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrxref_dpma_en_attr == SERDES_IP_CMN_L0_CFG_CMNRXREF_DPMA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrxref_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNRXREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnrxref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnspare0_attr == 32'd163
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnspare_attr == 9'd384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_rxlane0_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_rxlane1_timer_attr == 12'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_rxlane2_timer_attr == 12'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_rxlane3_timer_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_synthlcfast_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_synthlcmed_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_synthlcslow_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_txlane0_timer_attr == 12'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_txlane1_timer_attr == 12'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_txlane2_timer_attr == 12'd70
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_txlane3_timer_attr == 12'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthdiv_cdrdiv_en_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHDIV_CDRDIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthdiv_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHDIV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthdiv_slowmed_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHDIV_SLOWMED_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthdutyoffsetcal_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHDUTYOFFSETCAL_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthdutyoffsetcal_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHDUTYOFFSETCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthdutysel_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHDUTYSEL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthdutysel_mux_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlccaldac_currentdacdcdmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlccaldac_currentdacdcdmeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlccaldac_currentdacdcdmeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlccaldac_currentdacdcdmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlccaldac_synthdutyoffsetmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlccaldac_tx_disable_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHLCCALDAC_TX_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlccaldacerr_calsynthdutyerr_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHLCCALDACERR_CALSYNTHDUTYERR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlccaldacerr_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHLCCALDACERR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlcslowref_dpma_en_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHLCSLOWREF_DPMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlcslowref_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHLCSLOWREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlcslowref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmntxref_dpma_en_attr == SERDES_IP_CMN_L0_CFG_CMNTXREF_DPMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmntxref_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNTXREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmntxref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_cmnynthdutyselpolarity_attr == SERDES_IP_CMN_L0_CFG_CMNYNTHDUTYSELPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_lbcmn_locovren_attr == SERDES_IP_CMN_L0_CFG_LBCMN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_lbcmn_synthlcslowmedpostdivclk2cdrrefclken_locovr_attr == SERDES_IP_CMN_L0_CFG_LBCMN_SYNTHLCSLOWMEDPOSTDIVCLK2CDRREFCLKEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_rcompmaster_en_locovr_attr == SERDES_IP_CMN_L0_CFG_RCOMPMASTER_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_rcompmaster_locovren_attr == SERDES_IP_CMN_L0_CFG_RCOMPMASTER_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_rcompslave_locovr_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_rcompslave_locovren_attr == SERDES_IP_CMN_L0_CFG_RCOMPSLAVE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_rcompslave_valid_locovr_attr == SERDES_IP_CMN_L0_CFG_RCOMPSLAVE_VALID_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_rcompterm_rx_termcode_base_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_rcompterm_tfr_termcode_base_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_rcompterm_txpd_termcode_base_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_rcompterm_txpu_termcode_base_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmed_locovren_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMED_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmed_txbitclkselect_locovr_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMED_TXBITCLKSELECT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedcaldac_locovren_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMEDCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedcalregopampoffset_locovren_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedcalregopampoffsetfsmout_locovren_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedpcs_locovren_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMEDPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedpcs_postdiv2clk0_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedpcs_postdiv2clk0en_locovr_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMEDPCS_POSTDIV2CLK0EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedpcs_postdivclk0en_locovr_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMEDPCS_POSTDIVCLK0EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedreg_lev_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedreg_locovren_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMEDREG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_bti_div_attr == 7'd54
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_bti_div_rst_attr == SERDES_IP_CMN_L1_CFG_BTI_DIV_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_bti_en_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_bti_static_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmn_pg_disable_attr == SERDES_IP_CMN_L1_CFG_CMN_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmn_scratch_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnadc_req_attr == SERDES_IP_CMN_L1_CFG_CMNADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnapb2strbbridgecfg_acc_ctrl_field_mask_write_en_attr == SERDES_IP_CMN_L1_CFG_CMNAPB2STRBBRIDGECFG_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnapb2strbbridgecfg_force_state_en_attr == SERDES_IP_CMN_L1_CFG_CMNAPB2STRBBRIDGECFG_FORCE_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnapb2strbbridgecfg_force_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnapb2strbbridgecfg_stbl_time_aftr_strb_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnapb2strbbridgecfg_stbl_time_bfr_strb_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnapb2strbbridgecfg_strb_pulse_width_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnapbmaster_timeout_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobe_addr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobe_lastmux_isolate_attr == SERDES_IP_CMN_L1_CFG_CMNAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobeadc_current_direction_attr == SERDES_IP_CMN_L1_CFG_CMNAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobeadc_resistor_enable_attr == SERDES_IP_CMN_L1_CFG_CMNAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobedac_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobedac_en_attr == SERDES_IP_CMN_L1_CFG_CMNAPROBEDAC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobedacctrl_block_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobedacctrl_en_attr == SERDES_IP_CMN_L1_CFG_CMNAPROBEDACCTRL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobedacctrl_mask_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobedacctrl_rotate_left_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobedacctrl_tstbus_clkdiv_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnbias_icc20uadj_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnbias_icc80uadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnbias_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnbias_termcal_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnbscan_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnbshihyst_attr == SERDES_IP_CMN_L1_CFG_CMNBSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_bg_en_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_bg_one_step_cal_en_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_fg_inc_cal_en_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_fg_one_step_cal_en_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_finish_side_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_initval_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_invert_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_restore_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_round_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_runcount_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_signmagen_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetmeas_req_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_SYNTHDUTYOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncaldacbg_abort_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncaldacbg_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncaldacbg_ready_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncaldacfsm_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncaldacfsm_synthdutyoffsetfsm_clear_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncaldacfsm_synthdutyoffsetfsm_init_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncaldacfsm_synthdutyoffsetfsm_req_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncaldacsynthdutyoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALDACSYNTHDUTYOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncaldacsynthdutyoffsetfsmout_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALDACSYNTHDUTYOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalptr_pstate_rcomp_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalptr_pstate_synthdutyoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalptr_quad_rcomp_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalptr_quad_regopampoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalptr_quad_synthdutyoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_biastrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_cap_tune_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_divrate_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_mode_select_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_ref_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMP_REF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_rx_term_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMP_RX_TERM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_tfr_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMP_TFR_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_tx_term_pd_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMP_TX_TERM_PD_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_tx_term_pu_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMP_TX_TERM_PU_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_txterm_nmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_txterm_pmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_clear_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_code_delay_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_init_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rcomp_tfr_init_cal_value_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rcomp_tfr_max_value_attr == 4'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rcomp_tfr_min_value_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rcomp_txpd_valid_code_lut_vf00_attr == 32'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rcomp_txpd_valid_code_lut_vf01_attr == 32'd4246868100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rcomp_txpu_valid_code_lut_vf00_attr == 32'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rcomp_txpu_valid_code_lut_vf01_attr == 32'd4246868100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_req_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rx_comp_inv_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_RX_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rx_init_cal_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rx_initval_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rx_step_sign_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_RX_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rx_termcode_delta_lut_attr == 31'd24084352
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tfr_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tfr_comp_inv_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_TFR_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tfr_initval_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tfr_step_sign_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_TFR_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tfr_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_time_comp_config_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_time_lpfsetup_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_time_mode_setup_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_time_reset_release_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_time_sample_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tx_pd_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tx_pd_init_cal_value_attr == 6'd49
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tx_pd_max_value_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tx_pd_min_value_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tx_pu_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tx_pu_init_cal_value_attr == 6'd49
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tx_pu_max_value_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tx_pu_min_value_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_txpd_comp_inv_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_TXPD_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_txpd_initval_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_txpd_step_sign_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_TXPD_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_txpd_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_txpu_comp_inv_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_TXPU_COMP_INV_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_txpu_initval_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_txpu_step_sign_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_TXPU_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_txpu_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_txterm_pmos_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmaster_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPMASTER_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmaster_rx_locovr_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmaster_tfr_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmaster_txpd_locovr_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmaster_txpu_locovr_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmaster_valid_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPMASTER_VALID_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmeas_dlycount_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffset_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_clear_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_finish_side_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_init_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_invert_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_req_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_runcount_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsmout_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetmeas_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetmeas_req_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_avg_en_attr == SERDES_IP_CMN_L1_CFG_CMNCKM_AVG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_clk_en_attr == SERDES_IP_CMN_L1_CFG_CMNCKM_CLK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_continuous_attr == SERDES_IP_CMN_L1_CFG_CMNCKM_CONTINUOUS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_dig_meas_en_attr == SERDES_IP_CMN_L1_CFG_CMNCKM_DIG_MEAS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_dig_meas_err_clr_attr == SERDES_IP_CMN_L1_CFG_CMNCKM_DIG_MEAS_ERR_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_en_attr == SERDES_IP_CMN_L1_CFG_CMNCKM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_max_thr_attr == 25'd33554431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_meas_ck_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_ref_ck_div_ratio_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_result_clr_attr == SERDES_IP_CMN_L1_CFG_CMNCKM_RESULT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_start_attr == SERDES_IP_CMN_L1_CFG_CMNCKM_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_wdt_interval_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_win_thr_ref_attr == 25'd16777215
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnclk_keepalive_en_b_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnclk_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmndmondac_en_attr == SERDES_IP_CMN_L1_CFG_CMNDMONDAC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnfsm_cken_ovr_attr == SERDES_IP_CMN_L1_CFG_CMNFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnfsm_cken_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_aprobe1_charge_up_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_APROBE1_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_aprobe1_pull_dn_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_APROBE1_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_aprobe1_sense_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_APROBE1_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_aprobe2_charge_up_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_APROBE2_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_aprobe2_pull_dn_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_APROBE2_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_aprobe2_sense_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_APROBE2_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_changeref_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_changeref_val_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_en_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_CMN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_ntl_sel_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_CMN_NTL_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_refckm_charge_up_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_REFCKM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_refckm_pull_dn_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_REFCKM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_refckm_sense_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_REFCKM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_refckp_charge_up_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_REFCKP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_refckp_pull_dn_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_REFCKP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_refckp_sense_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_REFCKP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnpcs_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnpcs_ref_sel_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnpcs_ref_sel_tx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnperfmon_compare_val_start_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnperfmon_compare_val_stop_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnperfmon_en_attr == SERDES_IP_CMN_L1_CFG_CMNPERFMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnperfmon_mask_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprefckbufprelut_delta_attr == 15'd32767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprefckbufprelut_init_termcal_rx_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprefckbufprelut_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNRCOMPREFCKBUFPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprefckbufprelut_termcal_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprefcktxdrvprelut_delta_attr == 15'd4672
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprefcktxdrvprelut_init_termcal_rx_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprefcktxdrvprelut_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNRCOMPREFCKTXDRVPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprefcktxdrvprelut_termcal_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprxdfeprelut_delta_attr == 15'd32767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprxdfeprelut_init_termcal_tfr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprxdfeprelut_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNRCOMPRXDFEPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprxdfeprelut_termcal_tfr_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckbuf_cml_ena_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKBUF_CML_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckbuf_hs_cmos_ena_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKBUF_HS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckbuf_hs_ls_b_path_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKBUF_HS_LS_B_PATH_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckbuf_hs_ref_to_cdrdiv_ena_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKBUF_HS_REF_TO_CDRDIV_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckbuf_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKBUF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckbuf_ls_cmos_ena_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKBUF_LS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckbuf_powersave_b_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKBUF_POWERSAVE_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckbuf_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckbuf_termhiz_b_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKBUF_TERMHIZ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckdrv_powersave_en_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKDRV_POWERSAVE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrefcktxdrv_cdrdiv_en_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKTXDRV_CDRDIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrefcktxdrv_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKTXDRV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrefcktxdrv_termcal_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_en_b_attr == SERDES_IP_CMN_L1_CFG_CMNRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_entry3_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s0q2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s0q3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s1q4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s1q5_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s1q6_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s1q7_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s2q0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_entry2_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_entry3_attr == 13'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_entry4_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_entry5_attr == 13'd62
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_entry6_attr == 13'd390
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_entry7_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s0q2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s0q3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s1q1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s1q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s1q5_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s1q7_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s2q0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_term_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_term_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_term_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_term_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_term_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_term_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_term_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_term_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_keepalive_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_keepalive_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_bias_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_bias_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_refckbuf_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_refckbuf_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_refckbuf_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_refckbuf_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_rxref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_rxref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_rxref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_rxref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_synthdutycomp_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_synthdutycomp_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_synthdutycomp_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_synthdutycomp_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_synthlcslowref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_synthlcslowref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_synthlcslowref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_synthlcslowref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_txref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_txref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_txref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_txref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpurst_regreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpurst_regreset_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpurst_regreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrpurst_regreset_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_aetrcmn_regpwrupacc_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_AETRCMN_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_aetrcmn_regpwrupacc_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_AETRCMN_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_adc_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_adc_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_ADC_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_biasicc_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_biasicc_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_ntl_b_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_ntl_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_refckbuf_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_refckbuf_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_reg_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_reg_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_rxref_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_RXREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_rxref_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_RXREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_synthlcslowref_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_SYNTHLCSLOWREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_synthlcslowref_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_SYNTHLCSLOWREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_txref_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_TXREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_txref_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_TXREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_arstcmn_adc_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_ARSTCMN_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_arstcmn_adc_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_ARSTCMN_ADC_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_arstcmn_aprobedac_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_ARSTCMN_APROBEDAC_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_arstcmn_refcktxdrv_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_ARSTCMN_REFCKTXDRV_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_arstcmn_refcktxdrv_hiz_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_ARSTCMN_REFCKTXDRV_HIZ_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_arstcmn_regreset_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_ARSTCMN_REGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_arstcmn_regreset_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_ARSTCMN_REGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_synthdutycomp_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_SYNTHDUTYCOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_synthdutycomp_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_SYNTHDUTYCOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrxref_dpma_en_attr == SERDES_IP_CMN_L1_CFG_CMNRXREF_DPMA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrxref_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNRXREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnrxref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnspare0_attr == 32'd163
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnspare_attr == 9'd384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_rxlane0_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_rxlane1_timer_attr == 12'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_rxlane2_timer_attr == 12'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_rxlane3_timer_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_synthlcfast_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_synthlcmed_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_synthlcslow_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_txlane0_timer_attr == 12'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_txlane1_timer_attr == 12'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_txlane2_timer_attr == 12'd70
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_txlane3_timer_attr == 12'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthdiv_cdrdiv_en_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHDIV_CDRDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthdiv_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHDIV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthdiv_slowmed_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHDIV_SLOWMED_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthdutyoffsetcal_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHDUTYOFFSETCAL_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthdutyoffsetcal_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHDUTYOFFSETCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthdutysel_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHDUTYSEL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthdutysel_mux_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlccaldac_currentdacdcdmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlccaldac_currentdacdcdmeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlccaldac_currentdacdcdmeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlccaldac_currentdacdcdmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlccaldac_synthdutyoffsetmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlccaldac_tx_disable_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHLCCALDAC_TX_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlccaldacerr_calsynthdutyerr_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHLCCALDACERR_CALSYNTHDUTYERR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlccaldacerr_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHLCCALDACERR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlcslowref_dpma_en_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHLCSLOWREF_DPMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlcslowref_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHLCSLOWREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlcslowref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmntxref_dpma_en_attr == SERDES_IP_CMN_L1_CFG_CMNTXREF_DPMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmntxref_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNTXREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmntxref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_cmnynthdutyselpolarity_attr == SERDES_IP_CMN_L1_CFG_CMNYNTHDUTYSELPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_lbcmn_locovren_attr == SERDES_IP_CMN_L1_CFG_LBCMN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_lbcmn_synthlcslowmedpostdivclk2cdrrefclken_locovr_attr == SERDES_IP_CMN_L1_CFG_LBCMN_SYNTHLCSLOWMEDPOSTDIVCLK2CDRREFCLKEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_rcompmaster_en_locovr_attr == SERDES_IP_CMN_L1_CFG_RCOMPMASTER_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_rcompmaster_locovren_attr == SERDES_IP_CMN_L1_CFG_RCOMPMASTER_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_rcompslave_locovr_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_rcompslave_locovren_attr == SERDES_IP_CMN_L1_CFG_RCOMPSLAVE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_rcompslave_valid_locovr_attr == SERDES_IP_CMN_L1_CFG_RCOMPSLAVE_VALID_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_rcompterm_rx_termcode_base_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_rcompterm_tfr_termcode_base_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_rcompterm_txpd_termcode_base_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_rcompterm_txpu_termcode_base_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmed_locovren_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMED_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmed_txbitclkselect_locovr_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMED_TXBITCLKSELECT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedcaldac_locovren_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMEDCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedcalregopampoffset_locovren_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedcalregopampoffsetfsmout_locovren_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedpcs_locovren_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMEDPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedpcs_postdiv2clk0_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedpcs_postdiv2clk0en_locovr_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMEDPCS_POSTDIV2CLK0EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedpcs_postdivclk0en_locovr_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMEDPCS_POSTDIVCLK0EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedreg_lev_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedreg_locovren_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMEDREG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_bti_div_attr == 7'd54
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_bti_div_rst_attr == SERDES_IP_CMN_L2_CFG_BTI_DIV_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_bti_en_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_bti_static_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmn_pg_disable_attr == SERDES_IP_CMN_L2_CFG_CMN_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmn_scratch_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnadc_req_attr == SERDES_IP_CMN_L2_CFG_CMNADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnapb2strbbridgecfg_acc_ctrl_field_mask_write_en_attr == SERDES_IP_CMN_L2_CFG_CMNAPB2STRBBRIDGECFG_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnapb2strbbridgecfg_force_state_en_attr == SERDES_IP_CMN_L2_CFG_CMNAPB2STRBBRIDGECFG_FORCE_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnapb2strbbridgecfg_force_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnapb2strbbridgecfg_stbl_time_aftr_strb_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnapb2strbbridgecfg_stbl_time_bfr_strb_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnapb2strbbridgecfg_strb_pulse_width_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnapbmaster_timeout_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobe_addr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobe_lastmux_isolate_attr == SERDES_IP_CMN_L2_CFG_CMNAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobeadc_current_direction_attr == SERDES_IP_CMN_L2_CFG_CMNAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobeadc_resistor_enable_attr == SERDES_IP_CMN_L2_CFG_CMNAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobedac_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobedac_en_attr == SERDES_IP_CMN_L2_CFG_CMNAPROBEDAC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobedacctrl_block_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobedacctrl_en_attr == SERDES_IP_CMN_L2_CFG_CMNAPROBEDACCTRL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobedacctrl_mask_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobedacctrl_rotate_left_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobedacctrl_tstbus_clkdiv_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnbias_icc20uadj_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnbias_icc80uadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnbias_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnbias_termcal_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnbscan_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnbshihyst_attr == SERDES_IP_CMN_L2_CFG_CMNBSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_bg_en_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_bg_one_step_cal_en_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_fg_inc_cal_en_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_fg_one_step_cal_en_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_finish_side_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_initval_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_invert_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_restore_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_round_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_runcount_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_signmagen_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetmeas_req_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_SYNTHDUTYOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncaldacbg_abort_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncaldacbg_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncaldacbg_ready_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncaldacfsm_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncaldacfsm_synthdutyoffsetfsm_clear_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncaldacfsm_synthdutyoffsetfsm_init_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncaldacfsm_synthdutyoffsetfsm_req_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncaldacsynthdutyoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALDACSYNTHDUTYOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncaldacsynthdutyoffsetfsmout_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALDACSYNTHDUTYOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalptr_pstate_rcomp_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalptr_pstate_synthdutyoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalptr_quad_rcomp_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalptr_quad_regopampoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalptr_quad_synthdutyoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_biastrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_cap_tune_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_divrate_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_mode_select_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_ref_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMP_REF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_rx_term_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMP_RX_TERM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_tfr_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMP_TFR_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_tx_term_pd_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMP_TX_TERM_PD_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_tx_term_pu_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMP_TX_TERM_PU_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_txterm_nmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_txterm_pmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_clear_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_code_delay_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_init_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rcomp_tfr_init_cal_value_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rcomp_tfr_max_value_attr == 4'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rcomp_tfr_min_value_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rcomp_txpd_valid_code_lut_vf00_attr == 32'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rcomp_txpd_valid_code_lut_vf01_attr == 32'd4246868100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rcomp_txpu_valid_code_lut_vf00_attr == 32'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rcomp_txpu_valid_code_lut_vf01_attr == 32'd4246868100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_req_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rx_comp_inv_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_RX_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rx_init_cal_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rx_initval_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rx_step_sign_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_RX_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rx_termcode_delta_lut_attr == 31'd24084352
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tfr_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tfr_comp_inv_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_TFR_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tfr_initval_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tfr_step_sign_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_TFR_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tfr_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_time_comp_config_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_time_lpfsetup_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_time_mode_setup_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_time_reset_release_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_time_sample_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tx_pd_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tx_pd_init_cal_value_attr == 6'd49
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tx_pd_max_value_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tx_pd_min_value_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tx_pu_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tx_pu_init_cal_value_attr == 6'd49
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tx_pu_max_value_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tx_pu_min_value_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_txpd_comp_inv_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_TXPD_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_txpd_initval_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_txpd_step_sign_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_TXPD_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_txpd_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_txpu_comp_inv_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_TXPU_COMP_INV_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_txpu_initval_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_txpu_step_sign_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_TXPU_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_txpu_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_txterm_pmos_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmaster_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPMASTER_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmaster_rx_locovr_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmaster_tfr_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmaster_txpd_locovr_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmaster_txpu_locovr_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmaster_valid_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPMASTER_VALID_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmeas_dlycount_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffset_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_clear_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_finish_side_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_init_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_invert_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_req_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_runcount_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsmout_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetmeas_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetmeas_req_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_avg_en_attr == SERDES_IP_CMN_L2_CFG_CMNCKM_AVG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_clk_en_attr == SERDES_IP_CMN_L2_CFG_CMNCKM_CLK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_continuous_attr == SERDES_IP_CMN_L2_CFG_CMNCKM_CONTINUOUS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_dig_meas_en_attr == SERDES_IP_CMN_L2_CFG_CMNCKM_DIG_MEAS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_dig_meas_err_clr_attr == SERDES_IP_CMN_L2_CFG_CMNCKM_DIG_MEAS_ERR_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_en_attr == SERDES_IP_CMN_L2_CFG_CMNCKM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_max_thr_attr == 25'd33554431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_meas_ck_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_ref_ck_div_ratio_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_result_clr_attr == SERDES_IP_CMN_L2_CFG_CMNCKM_RESULT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_start_attr == SERDES_IP_CMN_L2_CFG_CMNCKM_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_wdt_interval_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_win_thr_ref_attr == 25'd16777215
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnclk_keepalive_en_b_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnclk_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmndmondac_en_attr == SERDES_IP_CMN_L2_CFG_CMNDMONDAC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnfsm_cken_ovr_attr == SERDES_IP_CMN_L2_CFG_CMNFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnfsm_cken_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_aprobe1_charge_up_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_APROBE1_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_aprobe1_pull_dn_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_APROBE1_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_aprobe1_sense_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_APROBE1_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_aprobe2_charge_up_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_APROBE2_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_aprobe2_pull_dn_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_APROBE2_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_aprobe2_sense_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_APROBE2_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_changeref_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_changeref_val_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_en_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_CMN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_ntl_sel_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_CMN_NTL_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_refckm_charge_up_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_REFCKM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_refckm_pull_dn_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_REFCKM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_refckm_sense_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_REFCKM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_refckp_charge_up_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_REFCKP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_refckp_pull_dn_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_REFCKP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_refckp_sense_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_REFCKP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnpcs_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnpcs_ref_sel_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnpcs_ref_sel_tx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnperfmon_compare_val_start_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnperfmon_compare_val_stop_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnperfmon_en_attr == SERDES_IP_CMN_L2_CFG_CMNPERFMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnperfmon_mask_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprefckbufprelut_delta_attr == 15'd32767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprefckbufprelut_init_termcal_rx_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprefckbufprelut_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNRCOMPREFCKBUFPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprefckbufprelut_termcal_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprefcktxdrvprelut_delta_attr == 15'd4672
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprefcktxdrvprelut_init_termcal_rx_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprefcktxdrvprelut_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNRCOMPREFCKTXDRVPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprefcktxdrvprelut_termcal_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprxdfeprelut_delta_attr == 15'd32767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprxdfeprelut_init_termcal_tfr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprxdfeprelut_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNRCOMPRXDFEPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprxdfeprelut_termcal_tfr_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckbuf_cml_ena_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKBUF_CML_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckbuf_hs_cmos_ena_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKBUF_HS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckbuf_hs_ls_b_path_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKBUF_HS_LS_B_PATH_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckbuf_hs_ref_to_cdrdiv_ena_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKBUF_HS_REF_TO_CDRDIV_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckbuf_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKBUF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckbuf_ls_cmos_ena_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKBUF_LS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckbuf_powersave_b_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKBUF_POWERSAVE_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckbuf_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckbuf_termhiz_b_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKBUF_TERMHIZ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckdrv_powersave_en_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKDRV_POWERSAVE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrefcktxdrv_cdrdiv_en_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKTXDRV_CDRDIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrefcktxdrv_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKTXDRV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrefcktxdrv_termcal_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_en_b_attr == SERDES_IP_CMN_L2_CFG_CMNRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_entry3_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s0q2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s0q3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s1q4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s1q5_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s1q6_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s1q7_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s2q0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_entry2_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_entry3_attr == 13'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_entry4_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_entry5_attr == 13'd62
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_entry6_attr == 13'd390
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_entry7_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s0q2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s0q3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s1q1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s1q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s1q5_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s1q7_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s2q0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_term_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_term_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_term_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_term_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_term_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_term_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_term_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_term_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_keepalive_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_keepalive_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_bias_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_bias_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_refckbuf_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_refckbuf_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_refckbuf_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_refckbuf_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_rxref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_rxref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_rxref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_rxref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_synthdutycomp_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_synthdutycomp_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_synthdutycomp_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_synthdutycomp_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_synthlcslowref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_synthlcslowref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_synthlcslowref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_synthlcslowref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_txref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_txref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_txref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_txref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpurst_regreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpurst_regreset_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpurst_regreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrpurst_regreset_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_aetrcmn_regpwrupacc_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_AETRCMN_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_aetrcmn_regpwrupacc_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_AETRCMN_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_adc_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_adc_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_ADC_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_biasicc_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_biasicc_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_ntl_b_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_ntl_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_refckbuf_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_refckbuf_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_reg_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_reg_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_rxref_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_RXREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_rxref_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_RXREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_synthlcslowref_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_SYNTHLCSLOWREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_synthlcslowref_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_SYNTHLCSLOWREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_txref_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_TXREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_txref_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_TXREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_arstcmn_adc_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_ARSTCMN_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_arstcmn_adc_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_ARSTCMN_ADC_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_arstcmn_aprobedac_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_ARSTCMN_APROBEDAC_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_arstcmn_refcktxdrv_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_ARSTCMN_REFCKTXDRV_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_arstcmn_refcktxdrv_hiz_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_ARSTCMN_REFCKTXDRV_HIZ_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_arstcmn_regreset_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_ARSTCMN_REGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_arstcmn_regreset_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_ARSTCMN_REGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_synthdutycomp_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_SYNTHDUTYCOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_synthdutycomp_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_SYNTHDUTYCOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrxref_dpma_en_attr == SERDES_IP_CMN_L2_CFG_CMNRXREF_DPMA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrxref_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNRXREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnrxref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnspare0_attr == 32'd163
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnspare_attr == 9'd384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_rxlane0_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_rxlane1_timer_attr == 12'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_rxlane2_timer_attr == 12'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_rxlane3_timer_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_synthlcfast_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_synthlcmed_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_synthlcslow_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_txlane0_timer_attr == 12'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_txlane1_timer_attr == 12'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_txlane2_timer_attr == 12'd70
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_txlane3_timer_attr == 12'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthdiv_cdrdiv_en_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHDIV_CDRDIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthdiv_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHDIV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthdiv_slowmed_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHDIV_SLOWMED_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthdutyoffsetcal_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHDUTYOFFSETCAL_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthdutyoffsetcal_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHDUTYOFFSETCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthdutysel_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHDUTYSEL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthdutysel_mux_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlccaldac_currentdacdcdmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlccaldac_currentdacdcdmeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlccaldac_currentdacdcdmeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlccaldac_currentdacdcdmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlccaldac_synthdutyoffsetmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlccaldac_tx_disable_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHLCCALDAC_TX_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlccaldacerr_calsynthdutyerr_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHLCCALDACERR_CALSYNTHDUTYERR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlccaldacerr_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHLCCALDACERR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlcslowref_dpma_en_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHLCSLOWREF_DPMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlcslowref_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHLCSLOWREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlcslowref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmntxref_dpma_en_attr == SERDES_IP_CMN_L2_CFG_CMNTXREF_DPMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmntxref_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNTXREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmntxref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_cmnynthdutyselpolarity_attr == SERDES_IP_CMN_L2_CFG_CMNYNTHDUTYSELPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_lbcmn_locovren_attr == SERDES_IP_CMN_L2_CFG_LBCMN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_lbcmn_synthlcslowmedpostdivclk2cdrrefclken_locovr_attr == SERDES_IP_CMN_L2_CFG_LBCMN_SYNTHLCSLOWMEDPOSTDIVCLK2CDRREFCLKEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_rcompmaster_en_locovr_attr == SERDES_IP_CMN_L2_CFG_RCOMPMASTER_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_rcompmaster_locovren_attr == SERDES_IP_CMN_L2_CFG_RCOMPMASTER_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_rcompslave_locovr_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_rcompslave_locovren_attr == SERDES_IP_CMN_L2_CFG_RCOMPSLAVE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_rcompslave_valid_locovr_attr == SERDES_IP_CMN_L2_CFG_RCOMPSLAVE_VALID_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_rcompterm_rx_termcode_base_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_rcompterm_tfr_termcode_base_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_rcompterm_txpd_termcode_base_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_rcompterm_txpu_termcode_base_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmed_locovren_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMED_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmed_txbitclkselect_locovr_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMED_TXBITCLKSELECT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedcaldac_locovren_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMEDCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedcalregopampoffset_locovren_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedcalregopampoffsetfsmout_locovren_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedpcs_locovren_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMEDPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedpcs_postdiv2clk0_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedpcs_postdiv2clk0en_locovr_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMEDPCS_POSTDIV2CLK0EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedpcs_postdivclk0en_locovr_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMEDPCS_POSTDIVCLK0EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedreg_lev_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedreg_locovren_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMEDREG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_bti_div_attr == 7'd54
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_bti_div_rst_attr == SERDES_IP_CMN_L3_CFG_BTI_DIV_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_bti_en_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_bti_static_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmn_pg_disable_attr == SERDES_IP_CMN_L3_CFG_CMN_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmn_scratch_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnadc_req_attr == SERDES_IP_CMN_L3_CFG_CMNADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnapb2strbbridgecfg_acc_ctrl_field_mask_write_en_attr == SERDES_IP_CMN_L3_CFG_CMNAPB2STRBBRIDGECFG_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnapb2strbbridgecfg_force_state_en_attr == SERDES_IP_CMN_L3_CFG_CMNAPB2STRBBRIDGECFG_FORCE_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnapb2strbbridgecfg_force_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnapb2strbbridgecfg_stbl_time_aftr_strb_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnapb2strbbridgecfg_stbl_time_bfr_strb_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnapb2strbbridgecfg_strb_pulse_width_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnapbmaster_timeout_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobe_addr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobe_lastmux_isolate_attr == SERDES_IP_CMN_L3_CFG_CMNAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobeadc_current_direction_attr == SERDES_IP_CMN_L3_CFG_CMNAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobeadc_resistor_enable_attr == SERDES_IP_CMN_L3_CFG_CMNAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobedac_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobedac_en_attr == SERDES_IP_CMN_L3_CFG_CMNAPROBEDAC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobedacctrl_block_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobedacctrl_en_attr == SERDES_IP_CMN_L3_CFG_CMNAPROBEDACCTRL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobedacctrl_mask_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobedacctrl_rotate_left_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobedacctrl_tstbus_clkdiv_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnbias_icc20uadj_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnbias_icc80uadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnbias_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnbias_termcal_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnbscan_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnbshihyst_attr == SERDES_IP_CMN_L3_CFG_CMNBSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_bg_en_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_bg_one_step_cal_en_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_fg_inc_cal_en_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_fg_one_step_cal_en_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_finish_side_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_initval_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_invert_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_restore_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_round_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_runcount_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_signmagen_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetmeas_req_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_SYNTHDUTYOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncaldacbg_abort_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncaldacbg_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncaldacbg_ready_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncaldacfsm_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncaldacfsm_synthdutyoffsetfsm_clear_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncaldacfsm_synthdutyoffsetfsm_init_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncaldacfsm_synthdutyoffsetfsm_req_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncaldacsynthdutyoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALDACSYNTHDUTYOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncaldacsynthdutyoffsetfsmout_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALDACSYNTHDUTYOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalptr_pstate_rcomp_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalptr_pstate_synthdutyoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalptr_quad_rcomp_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalptr_quad_regopampoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalptr_quad_synthdutyoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_biastrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_cap_tune_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_divrate_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_mode_select_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_ref_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMP_REF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_rx_term_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMP_RX_TERM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_tfr_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMP_TFR_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_tx_term_pd_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMP_TX_TERM_PD_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_tx_term_pu_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMP_TX_TERM_PU_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_txterm_nmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_txterm_pmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_clear_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_code_delay_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_init_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rcomp_tfr_init_cal_value_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rcomp_tfr_max_value_attr == 4'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rcomp_tfr_min_value_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rcomp_txpd_valid_code_lut_vf00_attr == 32'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rcomp_txpd_valid_code_lut_vf01_attr == 32'd4246868100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rcomp_txpu_valid_code_lut_vf00_attr == 32'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rcomp_txpu_valid_code_lut_vf01_attr == 32'd4246868100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_req_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rx_comp_inv_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_RX_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rx_init_cal_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rx_initval_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rx_step_sign_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_RX_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rx_termcode_delta_lut_attr == 31'd24084352
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tfr_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tfr_comp_inv_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_TFR_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tfr_initval_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tfr_step_sign_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_TFR_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tfr_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_time_comp_config_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_time_lpfsetup_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_time_mode_setup_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_time_reset_release_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_time_sample_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tx_pd_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tx_pd_init_cal_value_attr == 6'd49
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tx_pd_max_value_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tx_pd_min_value_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tx_pu_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tx_pu_init_cal_value_attr == 6'd49
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tx_pu_max_value_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tx_pu_min_value_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_txpd_comp_inv_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_TXPD_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_txpd_initval_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_txpd_step_sign_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_TXPD_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_txpd_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_txpu_comp_inv_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_TXPU_COMP_INV_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_txpu_initval_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_txpu_step_sign_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_TXPU_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_txpu_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_txterm_pmos_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmaster_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPMASTER_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmaster_rx_locovr_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmaster_tfr_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmaster_txpd_locovr_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmaster_txpu_locovr_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmaster_valid_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPMASTER_VALID_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmeas_dlycount_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffset_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_clear_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_finish_side_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_init_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_invert_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_req_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_runcount_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsmout_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetmeas_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetmeas_req_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_avg_en_attr == SERDES_IP_CMN_L3_CFG_CMNCKM_AVG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_clk_en_attr == SERDES_IP_CMN_L3_CFG_CMNCKM_CLK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_continuous_attr == SERDES_IP_CMN_L3_CFG_CMNCKM_CONTINUOUS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_dig_meas_en_attr == SERDES_IP_CMN_L3_CFG_CMNCKM_DIG_MEAS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_dig_meas_err_clr_attr == SERDES_IP_CMN_L3_CFG_CMNCKM_DIG_MEAS_ERR_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_en_attr == SERDES_IP_CMN_L3_CFG_CMNCKM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_max_thr_attr == 25'd33554431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_meas_ck_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_ref_ck_div_ratio_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_result_clr_attr == SERDES_IP_CMN_L3_CFG_CMNCKM_RESULT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_start_attr == SERDES_IP_CMN_L3_CFG_CMNCKM_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_wdt_interval_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_win_thr_ref_attr == 25'd16777215
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnclk_keepalive_en_b_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnclk_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmndmondac_en_attr == SERDES_IP_CMN_L3_CFG_CMNDMONDAC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnfsm_cken_ovr_attr == SERDES_IP_CMN_L3_CFG_CMNFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnfsm_cken_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_aprobe1_charge_up_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_APROBE1_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_aprobe1_pull_dn_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_APROBE1_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_aprobe1_sense_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_APROBE1_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_aprobe2_charge_up_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_APROBE2_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_aprobe2_pull_dn_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_APROBE2_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_aprobe2_sense_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_APROBE2_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_changeref_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_changeref_val_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_en_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_CMN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_ntl_sel_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_CMN_NTL_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_refckm_charge_up_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_REFCKM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_refckm_pull_dn_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_REFCKM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_refckm_sense_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_REFCKM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_refckp_charge_up_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_REFCKP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_refckp_pull_dn_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_REFCKP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_refckp_sense_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_REFCKP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnpcs_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnpcs_ref_sel_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnpcs_ref_sel_tx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnperfmon_compare_val_start_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnperfmon_compare_val_stop_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnperfmon_en_attr == SERDES_IP_CMN_L3_CFG_CMNPERFMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnperfmon_mask_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprefckbufprelut_delta_attr == 15'd32767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprefckbufprelut_init_termcal_rx_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprefckbufprelut_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNRCOMPREFCKBUFPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprefckbufprelut_termcal_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprefcktxdrvprelut_delta_attr == 15'd4672
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprefcktxdrvprelut_init_termcal_rx_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprefcktxdrvprelut_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNRCOMPREFCKTXDRVPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprefcktxdrvprelut_termcal_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprxdfeprelut_delta_attr == 15'd32767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprxdfeprelut_init_termcal_tfr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprxdfeprelut_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNRCOMPRXDFEPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprxdfeprelut_termcal_tfr_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckbuf_cml_ena_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKBUF_CML_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckbuf_hs_cmos_ena_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKBUF_HS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckbuf_hs_ls_b_path_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKBUF_HS_LS_B_PATH_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckbuf_hs_ref_to_cdrdiv_ena_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKBUF_HS_REF_TO_CDRDIV_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckbuf_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKBUF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckbuf_ls_cmos_ena_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKBUF_LS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckbuf_powersave_b_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKBUF_POWERSAVE_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckbuf_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckbuf_termhiz_b_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKBUF_TERMHIZ_B_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckdrv_powersave_en_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKDRV_POWERSAVE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrefcktxdrv_cdrdiv_en_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKTXDRV_CDRDIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrefcktxdrv_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKTXDRV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrefcktxdrv_termcal_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_en_b_attr == SERDES_IP_CMN_L3_CFG_CMNRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_entry3_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s0q2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s0q3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s1q4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s1q5_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s1q6_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s1q7_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s2q0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_entry2_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_entry3_attr == 13'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_entry4_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_entry5_attr == 13'd62
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_entry6_attr == 13'd390
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_entry7_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s0q2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s0q3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s1q1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s1q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s1q5_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s1q7_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s2q0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_term_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_term_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_term_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_term_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_term_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_term_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_term_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_term_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_keepalive_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_keepalive_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_bias_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_bias_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_refckbuf_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_refckbuf_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_refckbuf_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_refckbuf_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_rxref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_rxref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_rxref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_rxref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_synthdutycomp_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_synthdutycomp_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_synthdutycomp_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_synthdutycomp_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_synthlcslowref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_synthlcslowref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_synthlcslowref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_synthlcslowref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_txref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_txref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_txref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_txref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpurst_regreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpurst_regreset_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpurst_regreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrpurst_regreset_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_aetrcmn_regpwrupacc_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_AETRCMN_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_aetrcmn_regpwrupacc_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_AETRCMN_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_adc_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_adc_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_ADC_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_biasicc_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_biasicc_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_ntl_b_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_ntl_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_refckbuf_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_refckbuf_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_reg_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_reg_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_rxref_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_RXREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_rxref_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_RXREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_synthlcslowref_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_SYNTHLCSLOWREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_synthlcslowref_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_SYNTHLCSLOWREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_txref_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_TXREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_txref_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_TXREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_arstcmn_adc_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_ARSTCMN_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_arstcmn_adc_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_ARSTCMN_ADC_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_arstcmn_aprobedac_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_ARSTCMN_APROBEDAC_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_arstcmn_refcktxdrv_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_ARSTCMN_REFCKTXDRV_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_arstcmn_refcktxdrv_hiz_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_ARSTCMN_REFCKTXDRV_HIZ_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_arstcmn_regreset_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_ARSTCMN_REGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_arstcmn_regreset_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_ARSTCMN_REGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_synthdutycomp_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_SYNTHDUTYCOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_synthdutycomp_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_SYNTHDUTYCOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrxref_dpma_en_attr == SERDES_IP_CMN_L3_CFG_CMNRXREF_DPMA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrxref_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNRXREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnrxref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnspare0_attr == 32'd163
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnspare_attr == 9'd384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_rxlane0_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_rxlane1_timer_attr == 12'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_rxlane2_timer_attr == 12'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_rxlane3_timer_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_synthlcfast_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_synthlcmed_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_synthlcslow_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_txlane0_timer_attr == 12'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_txlane1_timer_attr == 12'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_txlane2_timer_attr == 12'd70
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_txlane3_timer_attr == 12'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthdiv_cdrdiv_en_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHDIV_CDRDIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthdiv_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHDIV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthdiv_slowmed_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHDIV_SLOWMED_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthdutyoffsetcal_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHDUTYOFFSETCAL_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthdutyoffsetcal_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHDUTYOFFSETCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthdutysel_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHDUTYSEL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthdutysel_mux_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlccaldac_currentdacdcdmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlccaldac_currentdacdcdmeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlccaldac_currentdacdcdmeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlccaldac_currentdacdcdmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlccaldac_synthdutyoffsetmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlccaldac_tx_disable_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHLCCALDAC_TX_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlccaldacerr_calsynthdutyerr_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHLCCALDACERR_CALSYNTHDUTYERR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlccaldacerr_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHLCCALDACERR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlcslowref_dpma_en_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHLCSLOWREF_DPMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlcslowref_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHLCSLOWREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlcslowref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmntxref_dpma_en_attr == SERDES_IP_CMN_L3_CFG_CMNTXREF_DPMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmntxref_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNTXREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmntxref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_cmnynthdutyselpolarity_attr == SERDES_IP_CMN_L3_CFG_CMNYNTHDUTYSELPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_lbcmn_locovren_attr == SERDES_IP_CMN_L3_CFG_LBCMN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_lbcmn_synthlcslowmedpostdivclk2cdrrefclken_locovr_attr == SERDES_IP_CMN_L3_CFG_LBCMN_SYNTHLCSLOWMEDPOSTDIVCLK2CDRREFCLKEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_rcompmaster_en_locovr_attr == SERDES_IP_CMN_L3_CFG_RCOMPMASTER_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_rcompmaster_locovren_attr == SERDES_IP_CMN_L3_CFG_RCOMPMASTER_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_rcompslave_locovr_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_rcompslave_locovren_attr == SERDES_IP_CMN_L3_CFG_RCOMPSLAVE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_rcompslave_valid_locovr_attr == SERDES_IP_CMN_L3_CFG_RCOMPSLAVE_VALID_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_rcompterm_rx_termcode_base_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_rcompterm_tfr_termcode_base_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_rcompterm_txpd_termcode_base_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_rcompterm_txpu_termcode_base_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmed_locovren_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMED_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmed_txbitclkselect_locovr_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMED_TXBITCLKSELECT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedcaldac_locovren_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMEDCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedcalregopampoffset_locovren_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedcalregopampoffsetfsmout_locovren_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedpcs_locovren_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMEDPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedpcs_postdiv2clk0_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedpcs_postdiv2clk0en_locovr_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMEDPCS_POSTDIV2CLK0EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedpcs_postdivclk0en_locovr_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMEDPCS_POSTDIVCLK0EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedreg_lev_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedreg_locovren_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMEDREG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_clock_ratio_cnt_max_timer_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_clock_ratio_cnt_min_timer_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_enable_flex_override_en_attr == SERDES_IP_FLEX_FW_LOADER_L0_CFG_CFG_ENABLE_FLEX_OVERRIDE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_enable_flex_override_value_attr == SERDES_IP_FLEX_FW_LOADER_L0_CFG_CFG_ENABLE_FLEX_OVERRIDE_VALUE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_flex_gpi_attr == 17'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_gp_lvl_attr == SERDES_IP_FLEX_FW_LOADER_L0_CFG_CFG_GP_LVL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_gp_pls_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_lms_cont_dis_attr == SERDES_IP_FLEX_FW_LOADER_L0_CFG_CFG_LMS_CONT_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_local_tp_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_periodical_rst_dis_attr == SERDES_IP_FLEX_FW_LOADER_L0_CFG_CFG_PERIODICAL_RST_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_spa_sat_dir_attr == SERDES_IP_FLEX_FW_LOADER_L0_CFG_CFG_SPA_SAT_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_vg_inv_cb_attr == SERDES_IP_FLEX_FW_LOADER_L0_CFG_CFG_VG_INV_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l0_cfg_data_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l0_cfg_fw_loader_en_attr == SERDES_IP_FLEX_FW_LOADER_L0_CFG_FW_LOADER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l0_cfg_offset_addr_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l0_cfg_single_mode_en_attr == SERDES_IP_FLEX_FW_LOADER_L0_CFG_SINGLE_MODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_clock_ratio_cnt_max_timer_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_clock_ratio_cnt_min_timer_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_enable_flex_override_en_attr == SERDES_IP_FLEX_FW_LOADER_L1_CFG_CFG_ENABLE_FLEX_OVERRIDE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_enable_flex_override_value_attr == SERDES_IP_FLEX_FW_LOADER_L1_CFG_CFG_ENABLE_FLEX_OVERRIDE_VALUE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_flex_gpi_attr == 17'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_gp_lvl_attr == SERDES_IP_FLEX_FW_LOADER_L1_CFG_CFG_GP_LVL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_gp_pls_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_lms_cont_dis_attr == SERDES_IP_FLEX_FW_LOADER_L1_CFG_CFG_LMS_CONT_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_local_tp_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_periodical_rst_dis_attr == SERDES_IP_FLEX_FW_LOADER_L1_CFG_CFG_PERIODICAL_RST_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_spa_sat_dir_attr == SERDES_IP_FLEX_FW_LOADER_L1_CFG_CFG_SPA_SAT_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_vg_inv_cb_attr == SERDES_IP_FLEX_FW_LOADER_L1_CFG_CFG_VG_INV_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l1_cfg_data_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l1_cfg_fw_loader_en_attr == SERDES_IP_FLEX_FW_LOADER_L1_CFG_FW_LOADER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l1_cfg_offset_addr_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l1_cfg_single_mode_en_attr == SERDES_IP_FLEX_FW_LOADER_L1_CFG_SINGLE_MODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_clock_ratio_cnt_max_timer_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_clock_ratio_cnt_min_timer_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_enable_flex_override_en_attr == SERDES_IP_FLEX_FW_LOADER_L2_CFG_CFG_ENABLE_FLEX_OVERRIDE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_enable_flex_override_value_attr == SERDES_IP_FLEX_FW_LOADER_L2_CFG_CFG_ENABLE_FLEX_OVERRIDE_VALUE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_flex_gpi_attr == 17'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_gp_lvl_attr == SERDES_IP_FLEX_FW_LOADER_L2_CFG_CFG_GP_LVL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_gp_pls_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_lms_cont_dis_attr == SERDES_IP_FLEX_FW_LOADER_L2_CFG_CFG_LMS_CONT_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_local_tp_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_periodical_rst_dis_attr == SERDES_IP_FLEX_FW_LOADER_L2_CFG_CFG_PERIODICAL_RST_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_spa_sat_dir_attr == SERDES_IP_FLEX_FW_LOADER_L2_CFG_CFG_SPA_SAT_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_vg_inv_cb_attr == SERDES_IP_FLEX_FW_LOADER_L2_CFG_CFG_VG_INV_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l2_cfg_data_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l2_cfg_fw_loader_en_attr == SERDES_IP_FLEX_FW_LOADER_L2_CFG_FW_LOADER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l2_cfg_offset_addr_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l2_cfg_single_mode_en_attr == SERDES_IP_FLEX_FW_LOADER_L2_CFG_SINGLE_MODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_clock_ratio_cnt_max_timer_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_clock_ratio_cnt_min_timer_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_enable_flex_override_en_attr == SERDES_IP_FLEX_FW_LOADER_L3_CFG_CFG_ENABLE_FLEX_OVERRIDE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_enable_flex_override_value_attr == SERDES_IP_FLEX_FW_LOADER_L3_CFG_CFG_ENABLE_FLEX_OVERRIDE_VALUE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_flex_gpi_attr == 17'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_gp_lvl_attr == SERDES_IP_FLEX_FW_LOADER_L3_CFG_CFG_GP_LVL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_gp_pls_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_lms_cont_dis_attr == SERDES_IP_FLEX_FW_LOADER_L3_CFG_CFG_LMS_CONT_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_local_tp_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_periodical_rst_dis_attr == SERDES_IP_FLEX_FW_LOADER_L3_CFG_CFG_PERIODICAL_RST_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_spa_sat_dir_attr == SERDES_IP_FLEX_FW_LOADER_L3_CFG_CFG_SPA_SAT_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_vg_inv_cb_attr == SERDES_IP_FLEX_FW_LOADER_L3_CFG_CFG_VG_INV_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l3_cfg_data_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l3_cfg_fw_loader_en_attr == SERDES_IP_FLEX_FW_LOADER_L3_CFG_FW_LOADER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l3_cfg_offset_addr_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_flex_fw_loader_l3_cfg_single_mode_en_attr == SERDES_IP_FLEX_FW_LOADER_L3_CFG_SINGLE_MODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_cpi_port_mode_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_dfx_secure_visa_nt_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_dfx_secure_visa_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_DFX_SECURE_VISA_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_p_vdd_pwrgood_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_P_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_p_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_P_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pa_vdd_ehv_pwrgood_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pa_vdd_ehv_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pa_vdd_pwrgood_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PA_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pa_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PA_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_andme_en_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_ANDME_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_andme_en_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_ANDME_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bist_modesel_l0_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bist_modesel_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BIST_MODESEL_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_capturedr_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_CAPTUREDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_clamp_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_CLAMP_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_exit1dr_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_EXIT1DR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_exit2dr_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_EXIT2DR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_extest_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_EXTEST_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_extestpulse_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_EXTESTPULSE_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_extesttrain_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_EXTESTTRAIN_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_highz_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_HIGHZ_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_mode_en_nt_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_MODE_EN_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_preload_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_PRELOAD_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_runtestidle_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_RUNTESTIDLE_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_shiftdr_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_SHIFTDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_txinvert_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_TXINVERT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_updatedr_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_UPDATEDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_cmn_force_pup_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_CMN_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_cmn_force_pup_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_CMN_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_disconnect_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_DISCONNECT_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_disconnect_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_DISCONNECT_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_isolate_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_ISOLATE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_isolate_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_ISOLATE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_jtagid_nt_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_JTAGID_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_jtagslvid_nt_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_JTAGSLVID_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_lb_cdrclk2txen_l0_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_LB_CDRCLK2TXEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_lb_cdrclk2txen_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_LB_CDRCLK2TXEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_lb_parrx2txtimeden_l0_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_LB_PARRX2TXTIMEDEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_lb_parrx2txtimeden_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_LB_PARRX2TXTIMEDEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_lb_tx2rxbuftimeden_l0_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_LB_TX2RXBUFTIMEDEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_lb_tx2rxbuftimeden_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_LB_TX2RXBUFTIMEDEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_lfps_en_l0_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_LFPS_EN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_lfps_en_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_LFPS_EN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_mode_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_MODE_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_mode_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_MODE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_pcie_l1d1_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_PCIE_L1D1_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_pcie_l1d1_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_PCIE_L1D1_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_pcie_l1d2_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_PCIE_L1D2_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_pcie_l1d2_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_PCIE_L1D2_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rcomp_slave_en_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RCOMP_SLAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rcomp_slave_en_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RCOMP_SLAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rcomp_slave_nt_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rcomp_slave_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RCOMP_SLAVE_NT_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rcomp_slave_valid_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RCOMP_SLAVE_VALID_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rcomp_slave_valid_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RCOMP_SLAVE_VALID_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_ref_sel_rx_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_ref_sel_rx_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_REF_SEL_RX_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_ref_sel_tx_nt_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_ref_sel_tx_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_REF_SEL_TX_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_ref_term_hiz_en_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_REF_TERM_HIZ_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_ref_term_hiz_en_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_REF_TERM_HIZ_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxbist_en_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXBIST_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxbist_en_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXBIST_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxbitslip_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXBITSLIP_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxbitslip_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXBITSLIP_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeiosdetectstat_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEIOSDETECTSTAT_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeiosdetectstat_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEIOSDETECTSTAT_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeq_clr_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEQ_CLR_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeq_clr_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEQ_CLR_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeq_precal_code_sel_l0_nt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeq_precal_code_sel_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEQ_PRECAL_CODE_SEL_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeq_start_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEQ_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeq_start_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEQ_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeq_static_en_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEQ_STATIC_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeq_static_en_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEQ_STATIC_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeyediag_start_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEYEDIAG_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeyediag_start_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEYEDIAG_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_direction_l0_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXMARGIN_DIRECTION_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_direction_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXMARGIN_DIRECTION_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_mode_l0_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXMARGIN_MODE_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_mode_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXMARGIN_MODE_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_offset_change_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXMARGIN_OFFSET_CHANGE_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_offset_change_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXMARGIN_OFFSET_CHANGE_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_offset_l0_nt_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_offset_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXMARGIN_OFFSET_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_start_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXMARGIN_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_start_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXMARGIN_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxpam_gray_en_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXPAM_GRAY_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxpam_gray_en_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXPAM_GRAY_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxpam_precode_en_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXPAM_PRECODE_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxpam_precode_en_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXPAM_PRECODE_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxrate_l0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxrate_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxterm_hiz_en_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXTERM_HIZ_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxterm_hiz_en_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXTERM_HIZ_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxwidth_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxwidth_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXWIDTH_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_spare_nt_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_spare_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SPARE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcfast_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcfast_divrate_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SYNTHLCFAST_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcfast_force_pup_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SYNTHLCFAST_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcfast_force_pup_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SYNTHLCFAST_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcmed_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcmed_divrate_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SYNTHLCMED_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcmed_force_pup_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SYNTHLCMED_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcmed_force_pup_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SYNTHLCMED_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcslow_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcslow_divrate_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SYNTHLCSLOW_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcslow_force_pup_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SYNTHLCSLOW_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcslow_force_pup_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SYNTHLCSLOW_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txbeacon_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXBEACON_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txbeacon_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXBEACON_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txbist_en_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXBIST_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txbist_en_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXBIST_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txclkdivrate_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txclkdivrate_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXCLKDIVRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdetectrx_req_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXDETECTRX_REQ_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdetectrx_req_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXDETECTRX_REQ_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_levn_l0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_levn_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXDRV_LEVN_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_levnm1_l0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_levnm1_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXDRV_LEVNM1_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_levnm2_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_levnm2_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXDRV_LEVNM2_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_levnp1_l0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_levnp1_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXDRV_LEVNP1_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_slew_l0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_slew_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXDRV_SLEW_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_spare_l0_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_spare_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXDRV_SPARE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txenable_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXENABLE_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txenable_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXENABLE_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txpam_gray_en_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXPAM_GRAY_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txpam_gray_en_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXPAM_GRAY_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txpam_precode_en_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXPAM_PRECODE_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txpam_precode_en_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXPAM_PRECODE_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txrate_l0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txrate_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txwidth_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txwidth_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXWIDTH_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_visa_unit_id_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_ictl_visa_unit_id_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_VISA_UNIT_ID_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_idat_dfx_obs_dig_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_idat_visa_serial_cfg_in_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_irst_apb_mem_b_attr == SERDES_IP_IF_L0_CFG_IRST_APB_MEM_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_irst_apb_mem_b_reg_en_attr == SERDES_IP_IF_L0_CFG_IRST_APB_MEM_B_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_irst_pcs_rx_l0_b_a_attr == SERDES_IP_IF_L0_CFG_IRST_PCS_RX_L0_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_irst_pcs_rx_l0_b_a_reg_en_attr == SERDES_IP_IF_L0_CFG_IRST_PCS_RX_L0_B_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_irst_pcs_tstbus_b_a_attr == SERDES_IP_IF_L0_CFG_IRST_PCS_TSTBUS_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_irst_pcs_tx_l0_b_a_attr == SERDES_IP_IF_L0_CFG_IRST_PCS_TX_L0_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_irst_pcs_tx_l0_b_a_reg_en_attr == SERDES_IP_IF_L0_CFG_IRST_PCS_TX_L0_B_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l0_cfg_irst_visa_reset_b_a_attr == SERDES_IP_IF_L0_CFG_IRST_VISA_RESET_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_cpi_port_mode_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_dfx_secure_visa_nt_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_dfx_secure_visa_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_DFX_SECURE_VISA_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_p_vdd_pwrgood_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_P_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_p_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_P_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pa_vdd_ehv_pwrgood_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pa_vdd_ehv_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pa_vdd_pwrgood_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PA_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pa_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PA_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_andme_en_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_ANDME_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_andme_en_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_ANDME_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bist_modesel_l0_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bist_modesel_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BIST_MODESEL_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_capturedr_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_CAPTUREDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_clamp_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_CLAMP_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_exit1dr_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_EXIT1DR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_exit2dr_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_EXIT2DR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_extest_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_EXTEST_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_extestpulse_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_EXTESTPULSE_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_extesttrain_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_EXTESTTRAIN_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_highz_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_HIGHZ_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_mode_en_nt_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_MODE_EN_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_preload_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_PRELOAD_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_runtestidle_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_RUNTESTIDLE_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_shiftdr_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_SHIFTDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_txinvert_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_TXINVERT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_updatedr_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_UPDATEDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_cmn_force_pup_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_CMN_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_cmn_force_pup_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_CMN_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_disconnect_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_DISCONNECT_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_disconnect_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_DISCONNECT_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_isolate_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_ISOLATE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_isolate_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_ISOLATE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_jtagid_nt_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_JTAGID_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_jtagslvid_nt_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_JTAGSLVID_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_lb_cdrclk2txen_l0_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_LB_CDRCLK2TXEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_lb_cdrclk2txen_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_LB_CDRCLK2TXEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_lb_parrx2txtimeden_l0_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_LB_PARRX2TXTIMEDEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_lb_parrx2txtimeden_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_LB_PARRX2TXTIMEDEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_lb_tx2rxbuftimeden_l0_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_LB_TX2RXBUFTIMEDEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_lb_tx2rxbuftimeden_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_LB_TX2RXBUFTIMEDEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_lfps_en_l0_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_LFPS_EN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_lfps_en_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_LFPS_EN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_mode_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_MODE_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_mode_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_MODE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_pcie_l1d1_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_PCIE_L1D1_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_pcie_l1d1_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_PCIE_L1D1_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_pcie_l1d2_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_PCIE_L1D2_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_pcie_l1d2_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_PCIE_L1D2_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rcomp_slave_en_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RCOMP_SLAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rcomp_slave_en_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RCOMP_SLAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rcomp_slave_nt_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rcomp_slave_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RCOMP_SLAVE_NT_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rcomp_slave_valid_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RCOMP_SLAVE_VALID_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rcomp_slave_valid_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RCOMP_SLAVE_VALID_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_ref_sel_rx_nt_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_ref_sel_rx_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_REF_SEL_RX_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_ref_sel_tx_nt_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_ref_sel_tx_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_REF_SEL_TX_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_ref_term_hiz_en_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_REF_TERM_HIZ_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_ref_term_hiz_en_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_REF_TERM_HIZ_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxbist_en_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXBIST_EN_L0_A_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxbist_en_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXBIST_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxbitslip_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXBITSLIP_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxbitslip_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXBITSLIP_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeiosdetectstat_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEIOSDETECTSTAT_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeiosdetectstat_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEIOSDETECTSTAT_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeq_clr_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEQ_CLR_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeq_clr_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEQ_CLR_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeq_precal_code_sel_l0_nt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeq_precal_code_sel_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEQ_PRECAL_CODE_SEL_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeq_start_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEQ_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeq_start_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEQ_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeq_static_en_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEQ_STATIC_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeq_static_en_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEQ_STATIC_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeyediag_start_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEYEDIAG_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeyediag_start_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEYEDIAG_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_direction_l0_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXMARGIN_DIRECTION_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_direction_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXMARGIN_DIRECTION_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_mode_l0_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXMARGIN_MODE_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_mode_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXMARGIN_MODE_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_offset_change_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXMARGIN_OFFSET_CHANGE_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_offset_change_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXMARGIN_OFFSET_CHANGE_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_offset_l0_nt_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_offset_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXMARGIN_OFFSET_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_start_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXMARGIN_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_start_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXMARGIN_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxpam_gray_en_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXPAM_GRAY_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxpam_gray_en_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXPAM_GRAY_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxpam_precode_en_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXPAM_PRECODE_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxpam_precode_en_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXPAM_PRECODE_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxrate_l0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxrate_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxterm_hiz_en_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXTERM_HIZ_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxterm_hiz_en_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXTERM_HIZ_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxwidth_l0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxwidth_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXWIDTH_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_spare_nt_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_spare_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SPARE_NT_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcfast_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcfast_divrate_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SYNTHLCFAST_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcfast_force_pup_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SYNTHLCFAST_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcfast_force_pup_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SYNTHLCFAST_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcmed_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcmed_divrate_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SYNTHLCMED_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcmed_force_pup_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SYNTHLCMED_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcmed_force_pup_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SYNTHLCMED_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcslow_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcslow_divrate_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SYNTHLCSLOW_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcslow_force_pup_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SYNTHLCSLOW_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcslow_force_pup_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SYNTHLCSLOW_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txbeacon_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXBEACON_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txbeacon_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXBEACON_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txbist_en_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXBIST_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txbist_en_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXBIST_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txclkdivrate_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txclkdivrate_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXCLKDIVRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdetectrx_req_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXDETECTRX_REQ_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdetectrx_req_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXDETECTRX_REQ_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_levn_l0_attr == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_levn_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXDRV_LEVN_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_levnm1_l0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_levnm1_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXDRV_LEVNM1_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_levnm2_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_levnm2_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXDRV_LEVNM2_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_levnp1_l0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_levnp1_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXDRV_LEVNP1_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_slew_l0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_slew_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXDRV_SLEW_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_spare_l0_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_spare_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXDRV_SPARE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txenable_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXENABLE_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txenable_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXENABLE_L0_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txpam_gray_en_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXPAM_GRAY_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txpam_gray_en_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXPAM_GRAY_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txpam_precode_en_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXPAM_PRECODE_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txpam_precode_en_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXPAM_PRECODE_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txrate_l0_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txrate_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txwidth_l0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txwidth_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXWIDTH_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_visa_unit_id_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_ictl_visa_unit_id_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_VISA_UNIT_ID_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_idat_dfx_obs_dig_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_idat_visa_serial_cfg_in_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_irst_apb_mem_b_attr == SERDES_IP_IF_L1_CFG_IRST_APB_MEM_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_irst_apb_mem_b_reg_en_attr == SERDES_IP_IF_L1_CFG_IRST_APB_MEM_B_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_irst_pcs_rx_l0_b_a_attr == SERDES_IP_IF_L1_CFG_IRST_PCS_RX_L0_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_irst_pcs_rx_l0_b_a_reg_en_attr == SERDES_IP_IF_L1_CFG_IRST_PCS_RX_L0_B_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_irst_pcs_tstbus_b_a_attr == SERDES_IP_IF_L1_CFG_IRST_PCS_TSTBUS_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_irst_pcs_tx_l0_b_a_attr == SERDES_IP_IF_L1_CFG_IRST_PCS_TX_L0_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_irst_pcs_tx_l0_b_a_reg_en_attr == SERDES_IP_IF_L1_CFG_IRST_PCS_TX_L0_B_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l1_cfg_irst_visa_reset_b_a_attr == SERDES_IP_IF_L1_CFG_IRST_VISA_RESET_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_cpi_port_mode_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_dfx_secure_visa_nt_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_dfx_secure_visa_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_DFX_SECURE_VISA_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_p_vdd_pwrgood_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_P_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_p_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_P_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pa_vdd_ehv_pwrgood_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pa_vdd_ehv_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pa_vdd_pwrgood_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PA_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pa_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PA_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_andme_en_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_ANDME_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_andme_en_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_ANDME_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bist_modesel_l0_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bist_modesel_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BIST_MODESEL_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_capturedr_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_CAPTUREDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_clamp_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_CLAMP_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_exit1dr_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_EXIT1DR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_exit2dr_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_EXIT2DR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_extest_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_EXTEST_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_extestpulse_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_EXTESTPULSE_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_extesttrain_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_EXTESTTRAIN_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_highz_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_HIGHZ_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_mode_en_nt_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_MODE_EN_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_preload_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_PRELOAD_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_runtestidle_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_RUNTESTIDLE_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_shiftdr_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_SHIFTDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_txinvert_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_TXINVERT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_updatedr_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_UPDATEDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_cmn_force_pup_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_CMN_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_cmn_force_pup_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_CMN_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_disconnect_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_DISCONNECT_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_disconnect_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_DISCONNECT_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_isolate_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_ISOLATE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_isolate_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_ISOLATE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_jtagid_nt_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_JTAGID_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_jtagslvid_nt_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_JTAGSLVID_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_lb_cdrclk2txen_l0_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_LB_CDRCLK2TXEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_lb_cdrclk2txen_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_LB_CDRCLK2TXEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_lb_parrx2txtimeden_l0_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_LB_PARRX2TXTIMEDEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_lb_parrx2txtimeden_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_LB_PARRX2TXTIMEDEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_lb_tx2rxbuftimeden_l0_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_LB_TX2RXBUFTIMEDEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_lb_tx2rxbuftimeden_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_LB_TX2RXBUFTIMEDEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_lfps_en_l0_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_LFPS_EN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_lfps_en_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_LFPS_EN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_mode_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_MODE_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_mode_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_MODE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_pcie_l1d1_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_PCIE_L1D1_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_pcie_l1d1_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_PCIE_L1D1_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_pcie_l1d2_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_PCIE_L1D2_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_pcie_l1d2_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_PCIE_L1D2_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rcomp_slave_en_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RCOMP_SLAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rcomp_slave_en_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RCOMP_SLAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rcomp_slave_nt_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rcomp_slave_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RCOMP_SLAVE_NT_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rcomp_slave_valid_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RCOMP_SLAVE_VALID_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rcomp_slave_valid_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RCOMP_SLAVE_VALID_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_ref_sel_rx_nt_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_ref_sel_rx_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_REF_SEL_RX_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_ref_sel_tx_nt_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_ref_sel_tx_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_REF_SEL_TX_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_ref_term_hiz_en_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_REF_TERM_HIZ_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_ref_term_hiz_en_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_REF_TERM_HIZ_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxbist_en_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXBIST_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxbist_en_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXBIST_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxbitslip_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXBITSLIP_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxbitslip_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXBITSLIP_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeiosdetectstat_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEIOSDETECTSTAT_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeiosdetectstat_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEIOSDETECTSTAT_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeq_clr_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEQ_CLR_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeq_clr_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEQ_CLR_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeq_precal_code_sel_l0_nt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeq_precal_code_sel_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEQ_PRECAL_CODE_SEL_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeq_start_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEQ_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeq_start_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEQ_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeq_static_en_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEQ_STATIC_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeq_static_en_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEQ_STATIC_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeyediag_start_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEYEDIAG_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeyediag_start_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEYEDIAG_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_direction_l0_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXMARGIN_DIRECTION_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_direction_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXMARGIN_DIRECTION_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_mode_l0_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXMARGIN_MODE_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_mode_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXMARGIN_MODE_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_offset_change_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXMARGIN_OFFSET_CHANGE_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_offset_change_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXMARGIN_OFFSET_CHANGE_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_offset_l0_nt_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_offset_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXMARGIN_OFFSET_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_start_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXMARGIN_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_start_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXMARGIN_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxpam_gray_en_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXPAM_GRAY_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxpam_gray_en_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXPAM_GRAY_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxpam_precode_en_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXPAM_PRECODE_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxpam_precode_en_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXPAM_PRECODE_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxrate_l0_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxrate_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxterm_hiz_en_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXTERM_HIZ_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxterm_hiz_en_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXTERM_HIZ_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxwidth_l0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxwidth_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXWIDTH_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_spare_nt_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_spare_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SPARE_NT_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcfast_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcfast_divrate_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SYNTHLCFAST_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcfast_force_pup_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SYNTHLCFAST_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcfast_force_pup_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SYNTHLCFAST_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcmed_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcmed_divrate_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SYNTHLCMED_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcmed_force_pup_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SYNTHLCMED_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcmed_force_pup_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SYNTHLCMED_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcslow_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcslow_divrate_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SYNTHLCSLOW_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcslow_force_pup_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SYNTHLCSLOW_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcslow_force_pup_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SYNTHLCSLOW_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txbeacon_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXBEACON_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txbeacon_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXBEACON_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txbist_en_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXBIST_EN_L0_A_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txbist_en_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXBIST_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txclkdivrate_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txclkdivrate_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXCLKDIVRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdetectrx_req_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXDETECTRX_REQ_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdetectrx_req_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXDETECTRX_REQ_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_levn_l0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_levn_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXDRV_LEVN_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_levnm1_l0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_levnm1_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXDRV_LEVNM1_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_levnm2_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_levnm2_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXDRV_LEVNM2_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_levnp1_l0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_levnp1_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXDRV_LEVNP1_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_slew_l0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_slew_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXDRV_SLEW_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_spare_l0_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_spare_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXDRV_SPARE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txenable_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXENABLE_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txenable_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXENABLE_L0_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txpam_gray_en_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXPAM_GRAY_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txpam_gray_en_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXPAM_GRAY_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txpam_precode_en_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXPAM_PRECODE_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txpam_precode_en_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXPAM_PRECODE_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txrate_l0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txrate_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txwidth_l0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txwidth_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXWIDTH_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_visa_unit_id_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_ictl_visa_unit_id_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_VISA_UNIT_ID_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_idat_dfx_obs_dig_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_idat_visa_serial_cfg_in_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_irst_apb_mem_b_attr == SERDES_IP_IF_L2_CFG_IRST_APB_MEM_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_irst_apb_mem_b_reg_en_attr == SERDES_IP_IF_L2_CFG_IRST_APB_MEM_B_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_irst_pcs_rx_l0_b_a_attr == SERDES_IP_IF_L2_CFG_IRST_PCS_RX_L0_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_irst_pcs_rx_l0_b_a_reg_en_attr == SERDES_IP_IF_L2_CFG_IRST_PCS_RX_L0_B_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_irst_pcs_tstbus_b_a_attr == SERDES_IP_IF_L2_CFG_IRST_PCS_TSTBUS_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_irst_pcs_tx_l0_b_a_attr == SERDES_IP_IF_L2_CFG_IRST_PCS_TX_L0_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_irst_pcs_tx_l0_b_a_reg_en_attr == SERDES_IP_IF_L2_CFG_IRST_PCS_TX_L0_B_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l2_cfg_irst_visa_reset_b_a_attr == SERDES_IP_IF_L2_CFG_IRST_VISA_RESET_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_cpi_port_mode_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_dfx_secure_visa_nt_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_dfx_secure_visa_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_DFX_SECURE_VISA_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_p_vdd_pwrgood_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_P_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_p_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_P_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pa_vdd_ehv_pwrgood_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pa_vdd_ehv_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pa_vdd_pwrgood_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PA_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pa_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PA_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_andme_en_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_ANDME_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_andme_en_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_ANDME_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bist_modesel_l0_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bist_modesel_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BIST_MODESEL_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_capturedr_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_CAPTUREDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_clamp_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_CLAMP_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_exit1dr_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_EXIT1DR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_exit2dr_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_EXIT2DR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_extest_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_EXTEST_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_extestpulse_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_EXTESTPULSE_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_extesttrain_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_EXTESTTRAIN_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_highz_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_HIGHZ_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_mode_en_nt_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_MODE_EN_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_preload_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_PRELOAD_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_runtestidle_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_RUNTESTIDLE_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_shiftdr_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_SHIFTDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_txinvert_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_TXINVERT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_updatedr_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_UPDATEDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_cmn_force_pup_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_CMN_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_cmn_force_pup_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_CMN_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_disconnect_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_DISCONNECT_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_disconnect_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_DISCONNECT_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_isolate_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_ISOLATE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_isolate_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_ISOLATE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_jtagid_nt_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_JTAGID_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_jtagslvid_nt_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_JTAGSLVID_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_lb_cdrclk2txen_l0_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_LB_CDRCLK2TXEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_lb_cdrclk2txen_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_LB_CDRCLK2TXEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_lb_parrx2txtimeden_l0_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_LB_PARRX2TXTIMEDEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_lb_parrx2txtimeden_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_LB_PARRX2TXTIMEDEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_lb_tx2rxbuftimeden_l0_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_LB_TX2RXBUFTIMEDEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_lb_tx2rxbuftimeden_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_LB_TX2RXBUFTIMEDEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_lfps_en_l0_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_LFPS_EN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_lfps_en_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_LFPS_EN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_mode_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_MODE_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_mode_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_MODE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_pcie_l1d1_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_PCIE_L1D1_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_pcie_l1d1_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_PCIE_L1D1_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_pcie_l1d2_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_PCIE_L1D2_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_pcie_l1d2_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_PCIE_L1D2_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rcomp_slave_en_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RCOMP_SLAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rcomp_slave_en_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RCOMP_SLAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rcomp_slave_nt_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rcomp_slave_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RCOMP_SLAVE_NT_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rcomp_slave_valid_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RCOMP_SLAVE_VALID_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rcomp_slave_valid_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RCOMP_SLAVE_VALID_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_ref_sel_rx_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_ref_sel_rx_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_REF_SEL_RX_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_ref_sel_tx_nt_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_ref_sel_tx_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_REF_SEL_TX_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_ref_term_hiz_en_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_REF_TERM_HIZ_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_ref_term_hiz_en_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_REF_TERM_HIZ_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxbist_en_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXBIST_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxbist_en_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXBIST_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxbitslip_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXBITSLIP_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxbitslip_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXBITSLIP_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeiosdetectstat_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEIOSDETECTSTAT_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeiosdetectstat_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEIOSDETECTSTAT_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeq_clr_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEQ_CLR_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeq_clr_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEQ_CLR_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeq_precal_code_sel_l0_nt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeq_precal_code_sel_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEQ_PRECAL_CODE_SEL_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeq_start_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEQ_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeq_start_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEQ_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeq_static_en_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEQ_STATIC_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeq_static_en_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEQ_STATIC_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeyediag_start_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEYEDIAG_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeyediag_start_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEYEDIAG_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_direction_l0_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXMARGIN_DIRECTION_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_direction_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXMARGIN_DIRECTION_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_mode_l0_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXMARGIN_MODE_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_mode_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXMARGIN_MODE_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_offset_change_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXMARGIN_OFFSET_CHANGE_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_offset_change_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXMARGIN_OFFSET_CHANGE_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_offset_l0_nt_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_offset_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXMARGIN_OFFSET_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_start_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXMARGIN_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_start_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXMARGIN_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxpam_gray_en_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXPAM_GRAY_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxpam_gray_en_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXPAM_GRAY_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxpam_precode_en_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXPAM_PRECODE_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxpam_precode_en_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXPAM_PRECODE_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxrate_l0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxrate_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxterm_hiz_en_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXTERM_HIZ_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxterm_hiz_en_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXTERM_HIZ_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxwidth_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxwidth_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXWIDTH_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_spare_nt_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_spare_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SPARE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcfast_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcfast_divrate_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SYNTHLCFAST_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcfast_force_pup_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SYNTHLCFAST_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcfast_force_pup_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SYNTHLCFAST_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcmed_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcmed_divrate_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SYNTHLCMED_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcmed_force_pup_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SYNTHLCMED_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcmed_force_pup_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SYNTHLCMED_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcslow_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcslow_divrate_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SYNTHLCSLOW_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcslow_force_pup_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SYNTHLCSLOW_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcslow_force_pup_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SYNTHLCSLOW_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txbeacon_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXBEACON_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txbeacon_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXBEACON_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txbist_en_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXBIST_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txbist_en_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXBIST_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txclkdivrate_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txclkdivrate_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXCLKDIVRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdetectrx_req_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXDETECTRX_REQ_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdetectrx_req_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXDETECTRX_REQ_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_levn_l0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_levn_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXDRV_LEVN_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_levnm1_l0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_levnm1_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXDRV_LEVNM1_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_levnm2_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_levnm2_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXDRV_LEVNM2_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_levnp1_l0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_levnp1_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXDRV_LEVNP1_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_slew_l0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_slew_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXDRV_SLEW_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_spare_l0_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_spare_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXDRV_SPARE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txenable_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXENABLE_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txenable_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXENABLE_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txpam_gray_en_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXPAM_GRAY_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txpam_gray_en_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXPAM_GRAY_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txpam_precode_en_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXPAM_PRECODE_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txpam_precode_en_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXPAM_PRECODE_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txrate_l0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txrate_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txwidth_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txwidth_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXWIDTH_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_visa_unit_id_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_ictl_visa_unit_id_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_VISA_UNIT_ID_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_idat_dfx_obs_dig_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_idat_visa_serial_cfg_in_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_irst_apb_mem_b_attr == SERDES_IP_IF_L3_CFG_IRST_APB_MEM_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_irst_apb_mem_b_reg_en_attr == SERDES_IP_IF_L3_CFG_IRST_APB_MEM_B_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_irst_pcs_rx_l0_b_a_attr == SERDES_IP_IF_L3_CFG_IRST_PCS_RX_L0_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_irst_pcs_rx_l0_b_a_reg_en_attr == SERDES_IP_IF_L3_CFG_IRST_PCS_RX_L0_B_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_irst_pcs_tstbus_b_a_attr == SERDES_IP_IF_L3_CFG_IRST_PCS_TSTBUS_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_irst_pcs_tx_l0_b_a_attr == SERDES_IP_IF_L3_CFG_IRST_PCS_TX_L0_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_irst_pcs_tx_l0_b_a_reg_en_attr == SERDES_IP_IF_L3_CFG_IRST_PCS_TX_L0_B_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_if_l3_cfg_irst_visa_reset_b_a_attr == SERDES_IP_IF_L3_CFG_IRST_VISA_RESET_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l0_cfg_laneclk_ctrl_attr == SERDES_IP_LANE_AON_L0_CFG_LANECLK_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l0_cfg_lanefsm_pmu_req_attr == SERDES_IP_LANE_AON_L0_CFG_LANEFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l0_cfg_lanefsm_pmu_req_en_attr == SERDES_IP_LANE_AON_L0_CFG_LANEFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l0_cfg_lanetstbus_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l0_cfg_rxmem_clr_attr == SERDES_IP_LANE_AON_L0_CFG_RXMEM_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l0_cfg_rxmem_en_attr == SERDES_IP_LANE_AON_L0_CFG_RXMEM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l0_cfg_rxmem_pstate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l0_cfg_rxmem_rate_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l0_cfg_rxmem_req_attr == SERDES_IP_LANE_AON_L0_CFG_RXMEM_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l0_cfg_rxmem_rst_b_attr == SERDES_IP_LANE_AON_L0_CFG_RXMEM_RST_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l0_cfg_rxmem_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l0_cfg_rxrstpdovr_apdrx_sqlch_ovr_b_attr == SERDES_IP_LANE_AON_L0_CFG_RXRSTPDOVR_APDRX_SQLCH_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l0_cfg_rxrstpdovr_apdrx_sqlch_ovren_attr == SERDES_IP_LANE_AON_L0_CFG_RXRSTPDOVR_APDRX_SQLCH_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l0_cfg_rxsussigdetout_ovr_attr == SERDES_IP_LANE_AON_L0_CFG_RXSUSSIGDETOUT_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l0_cfg_rxsussigdetout_ovr_en_attr == SERDES_IP_LANE_AON_L0_CFG_RXSUSSIGDETOUT_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l0_cfg_rxsussqlch_enable_attr == SERDES_IP_LANE_AON_L0_CFG_RXSUSSQLCH_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l0_cfg_txmem_clr_attr == SERDES_IP_LANE_AON_L0_CFG_TXMEM_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l0_cfg_txmem_en_attr == SERDES_IP_LANE_AON_L0_CFG_TXMEM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l0_cfg_txmem_pstate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l0_cfg_txmem_rate_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l0_cfg_txmem_req_attr == SERDES_IP_LANE_AON_L0_CFG_TXMEM_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l0_cfg_txmem_rst_b_attr == SERDES_IP_LANE_AON_L0_CFG_TXMEM_RST_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l0_cfg_txmem_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l0_cfg_txpcs_pciel1d1_ovr_attr == SERDES_IP_LANE_AON_L0_CFG_TXPCS_PCIEL1D1_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l0_cfg_txpcs_pciel1d1_ovren_attr == SERDES_IP_LANE_AON_L0_CFG_TXPCS_PCIEL1D1_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l0_cfg_txpcs_pciel1d2_ovr_attr == SERDES_IP_LANE_AON_L0_CFG_TXPCS_PCIEL1D2_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l0_cfg_txpcs_pciel1d2_ovren_attr == SERDES_IP_LANE_AON_L0_CFG_TXPCS_PCIEL1D2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l0_cfg_txrstpdovr_apdtx_bias_ovr_b_attr == SERDES_IP_LANE_AON_L0_CFG_TXRSTPDOVR_APDTX_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l0_cfg_txrstpdovr_apdtx_bias_ovren_attr == SERDES_IP_LANE_AON_L0_CFG_TXRSTPDOVR_APDTX_BIAS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l0_cfg_txrstpdovr_apdtx_drv_ovr_b_attr == SERDES_IP_LANE_AON_L0_CFG_TXRSTPDOVR_APDTX_DRV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l0_cfg_txrstpdovr_apdtx_drv_ovren_attr == SERDES_IP_LANE_AON_L0_CFG_TXRSTPDOVR_APDTX_DRV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l1_cfg_laneclk_ctrl_attr == SERDES_IP_LANE_AON_L1_CFG_LANECLK_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l1_cfg_lanefsm_pmu_req_attr == SERDES_IP_LANE_AON_L1_CFG_LANEFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l1_cfg_lanefsm_pmu_req_en_attr == SERDES_IP_LANE_AON_L1_CFG_LANEFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l1_cfg_lanetstbus_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l1_cfg_rxmem_clr_attr == SERDES_IP_LANE_AON_L1_CFG_RXMEM_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l1_cfg_rxmem_en_attr == SERDES_IP_LANE_AON_L1_CFG_RXMEM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l1_cfg_rxmem_pstate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l1_cfg_rxmem_rate_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l1_cfg_rxmem_req_attr == SERDES_IP_LANE_AON_L1_CFG_RXMEM_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l1_cfg_rxmem_rst_b_attr == SERDES_IP_LANE_AON_L1_CFG_RXMEM_RST_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l1_cfg_rxmem_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l1_cfg_rxrstpdovr_apdrx_sqlch_ovr_b_attr == SERDES_IP_LANE_AON_L1_CFG_RXRSTPDOVR_APDRX_SQLCH_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l1_cfg_rxrstpdovr_apdrx_sqlch_ovren_attr == SERDES_IP_LANE_AON_L1_CFG_RXRSTPDOVR_APDRX_SQLCH_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l1_cfg_rxsussigdetout_ovr_attr == SERDES_IP_LANE_AON_L1_CFG_RXSUSSIGDETOUT_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l1_cfg_rxsussigdetout_ovr_en_attr == SERDES_IP_LANE_AON_L1_CFG_RXSUSSIGDETOUT_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l1_cfg_rxsussqlch_enable_attr == SERDES_IP_LANE_AON_L1_CFG_RXSUSSQLCH_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l1_cfg_txmem_clr_attr == SERDES_IP_LANE_AON_L1_CFG_TXMEM_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l1_cfg_txmem_en_attr == SERDES_IP_LANE_AON_L1_CFG_TXMEM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l1_cfg_txmem_pstate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l1_cfg_txmem_rate_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l1_cfg_txmem_req_attr == SERDES_IP_LANE_AON_L1_CFG_TXMEM_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l1_cfg_txmem_rst_b_attr == SERDES_IP_LANE_AON_L1_CFG_TXMEM_RST_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l1_cfg_txmem_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l1_cfg_txpcs_pciel1d1_ovr_attr == SERDES_IP_LANE_AON_L1_CFG_TXPCS_PCIEL1D1_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l1_cfg_txpcs_pciel1d1_ovren_attr == SERDES_IP_LANE_AON_L1_CFG_TXPCS_PCIEL1D1_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l1_cfg_txpcs_pciel1d2_ovr_attr == SERDES_IP_LANE_AON_L1_CFG_TXPCS_PCIEL1D2_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l1_cfg_txpcs_pciel1d2_ovren_attr == SERDES_IP_LANE_AON_L1_CFG_TXPCS_PCIEL1D2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l1_cfg_txrstpdovr_apdtx_bias_ovr_b_attr == SERDES_IP_LANE_AON_L1_CFG_TXRSTPDOVR_APDTX_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l1_cfg_txrstpdovr_apdtx_bias_ovren_attr == SERDES_IP_LANE_AON_L1_CFG_TXRSTPDOVR_APDTX_BIAS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l1_cfg_txrstpdovr_apdtx_drv_ovr_b_attr == SERDES_IP_LANE_AON_L1_CFG_TXRSTPDOVR_APDTX_DRV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l1_cfg_txrstpdovr_apdtx_drv_ovren_attr == SERDES_IP_LANE_AON_L1_CFG_TXRSTPDOVR_APDTX_DRV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l2_cfg_laneclk_ctrl_attr == SERDES_IP_LANE_AON_L2_CFG_LANECLK_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l2_cfg_lanefsm_pmu_req_attr == SERDES_IP_LANE_AON_L2_CFG_LANEFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l2_cfg_lanefsm_pmu_req_en_attr == SERDES_IP_LANE_AON_L2_CFG_LANEFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l2_cfg_lanetstbus_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l2_cfg_rxmem_clr_attr == SERDES_IP_LANE_AON_L2_CFG_RXMEM_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l2_cfg_rxmem_en_attr == SERDES_IP_LANE_AON_L2_CFG_RXMEM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l2_cfg_rxmem_pstate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l2_cfg_rxmem_rate_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l2_cfg_rxmem_req_attr == SERDES_IP_LANE_AON_L2_CFG_RXMEM_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l2_cfg_rxmem_rst_b_attr == SERDES_IP_LANE_AON_L2_CFG_RXMEM_RST_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l2_cfg_rxmem_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l2_cfg_rxrstpdovr_apdrx_sqlch_ovr_b_attr == SERDES_IP_LANE_AON_L2_CFG_RXRSTPDOVR_APDRX_SQLCH_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l2_cfg_rxrstpdovr_apdrx_sqlch_ovren_attr == SERDES_IP_LANE_AON_L2_CFG_RXRSTPDOVR_APDRX_SQLCH_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l2_cfg_rxsussigdetout_ovr_attr == SERDES_IP_LANE_AON_L2_CFG_RXSUSSIGDETOUT_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l2_cfg_rxsussigdetout_ovr_en_attr == SERDES_IP_LANE_AON_L2_CFG_RXSUSSIGDETOUT_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l2_cfg_rxsussqlch_enable_attr == SERDES_IP_LANE_AON_L2_CFG_RXSUSSQLCH_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l2_cfg_txmem_clr_attr == SERDES_IP_LANE_AON_L2_CFG_TXMEM_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l2_cfg_txmem_en_attr == SERDES_IP_LANE_AON_L2_CFG_TXMEM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l2_cfg_txmem_pstate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l2_cfg_txmem_rate_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l2_cfg_txmem_req_attr == SERDES_IP_LANE_AON_L2_CFG_TXMEM_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l2_cfg_txmem_rst_b_attr == SERDES_IP_LANE_AON_L2_CFG_TXMEM_RST_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l2_cfg_txmem_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l2_cfg_txpcs_pciel1d1_ovr_attr == SERDES_IP_LANE_AON_L2_CFG_TXPCS_PCIEL1D1_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l2_cfg_txpcs_pciel1d1_ovren_attr == SERDES_IP_LANE_AON_L2_CFG_TXPCS_PCIEL1D1_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l2_cfg_txpcs_pciel1d2_ovr_attr == SERDES_IP_LANE_AON_L2_CFG_TXPCS_PCIEL1D2_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l2_cfg_txpcs_pciel1d2_ovren_attr == SERDES_IP_LANE_AON_L2_CFG_TXPCS_PCIEL1D2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l2_cfg_txrstpdovr_apdtx_bias_ovr_b_attr == SERDES_IP_LANE_AON_L2_CFG_TXRSTPDOVR_APDTX_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l2_cfg_txrstpdovr_apdtx_bias_ovren_attr == SERDES_IP_LANE_AON_L2_CFG_TXRSTPDOVR_APDTX_BIAS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l2_cfg_txrstpdovr_apdtx_drv_ovr_b_attr == SERDES_IP_LANE_AON_L2_CFG_TXRSTPDOVR_APDTX_DRV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l2_cfg_txrstpdovr_apdtx_drv_ovren_attr == SERDES_IP_LANE_AON_L2_CFG_TXRSTPDOVR_APDTX_DRV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l3_cfg_laneclk_ctrl_attr == SERDES_IP_LANE_AON_L3_CFG_LANECLK_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l3_cfg_lanefsm_pmu_req_attr == SERDES_IP_LANE_AON_L3_CFG_LANEFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l3_cfg_lanefsm_pmu_req_en_attr == SERDES_IP_LANE_AON_L3_CFG_LANEFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l3_cfg_lanetstbus_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l3_cfg_rxmem_clr_attr == SERDES_IP_LANE_AON_L3_CFG_RXMEM_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l3_cfg_rxmem_en_attr == SERDES_IP_LANE_AON_L3_CFG_RXMEM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l3_cfg_rxmem_pstate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l3_cfg_rxmem_rate_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l3_cfg_rxmem_req_attr == SERDES_IP_LANE_AON_L3_CFG_RXMEM_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l3_cfg_rxmem_rst_b_attr == SERDES_IP_LANE_AON_L3_CFG_RXMEM_RST_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l3_cfg_rxmem_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l3_cfg_rxrstpdovr_apdrx_sqlch_ovr_b_attr == SERDES_IP_LANE_AON_L3_CFG_RXRSTPDOVR_APDRX_SQLCH_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l3_cfg_rxrstpdovr_apdrx_sqlch_ovren_attr == SERDES_IP_LANE_AON_L3_CFG_RXRSTPDOVR_APDRX_SQLCH_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l3_cfg_rxsussigdetout_ovr_attr == SERDES_IP_LANE_AON_L3_CFG_RXSUSSIGDETOUT_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l3_cfg_rxsussigdetout_ovr_en_attr == SERDES_IP_LANE_AON_L3_CFG_RXSUSSIGDETOUT_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l3_cfg_rxsussqlch_enable_attr == SERDES_IP_LANE_AON_L3_CFG_RXSUSSQLCH_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l3_cfg_txmem_clr_attr == SERDES_IP_LANE_AON_L3_CFG_TXMEM_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l3_cfg_txmem_en_attr == SERDES_IP_LANE_AON_L3_CFG_TXMEM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l3_cfg_txmem_pstate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l3_cfg_txmem_rate_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l3_cfg_txmem_req_attr == SERDES_IP_LANE_AON_L3_CFG_TXMEM_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l3_cfg_txmem_rst_b_attr == SERDES_IP_LANE_AON_L3_CFG_TXMEM_RST_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l3_cfg_txmem_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l3_cfg_txpcs_pciel1d1_ovr_attr == SERDES_IP_LANE_AON_L3_CFG_TXPCS_PCIEL1D1_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l3_cfg_txpcs_pciel1d1_ovren_attr == SERDES_IP_LANE_AON_L3_CFG_TXPCS_PCIEL1D1_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l3_cfg_txpcs_pciel1d2_ovr_attr == SERDES_IP_LANE_AON_L3_CFG_TXPCS_PCIEL1D2_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l3_cfg_txpcs_pciel1d2_ovren_attr == SERDES_IP_LANE_AON_L3_CFG_TXPCS_PCIEL1D2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l3_cfg_txrstpdovr_apdtx_bias_ovr_b_attr == SERDES_IP_LANE_AON_L3_CFG_TXRSTPDOVR_APDTX_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l3_cfg_txrstpdovr_apdtx_bias_ovren_attr == SERDES_IP_LANE_AON_L3_CFG_TXRSTPDOVR_APDTX_BIAS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l3_cfg_txrstpdovr_apdtx_drv_ovr_b_attr == SERDES_IP_LANE_AON_L3_CFG_TXRSTPDOVR_APDTX_DRV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_aon_l3_cfg_txrstpdovr_apdtx_drv_ovren_attr == SERDES_IP_LANE_AON_L3_CFG_TXRSTPDOVR_APDTX_DRV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_bshihyst_attr == SERDES_IP_LANE_L0_CFG_BSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_bstxdrv_levn_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_bstxdrv_levnm1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_bstxdrv_levnp1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_bstxdrv_levnp2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_calsqlchosc_locovren_attr == SERDES_IP_LANE_L0_CFG_CALSQLCHOSC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_calsqlchosc_trimcode_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_cdrclkstat_locovren_attr == SERDES_IP_LANE_L0_CFG_CDRCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_cdrclkstat_ready_locovr_attr == SERDES_IP_LANE_L0_CFG_CDRCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_etrregrxcdrclk_ready_attr == SERDES_IP_LANE_L0_CFG_ETRREGRXCDRCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_laneckm_avg_en_attr == SERDES_IP_LANE_L0_CFG_LANECKM_AVG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_laneckm_clk_en_attr == SERDES_IP_LANE_L0_CFG_LANECKM_CLK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_laneckm_continuous_attr == SERDES_IP_LANE_L0_CFG_LANECKM_CONTINUOUS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_laneckm_dig_meas_en_attr == SERDES_IP_LANE_L0_CFG_LANECKM_DIG_MEAS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_laneckm_dig_meas_err_clr_attr == SERDES_IP_LANE_L0_CFG_LANECKM_DIG_MEAS_ERR_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_laneckm_en_attr == SERDES_IP_LANE_L0_CFG_LANECKM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_laneckm_max_thr_attr == 25'd33554431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_laneckm_meas_ck_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_laneckm_ref_ck_div_ratio_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_laneckm_result_clr_attr == SERDES_IP_LANE_L0_CFG_LANECKM_RESULT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_laneckm_start_attr == SERDES_IP_LANE_L0_CFG_LANECKM_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_laneckm_wdt_interval_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_laneckm_win_thr_ref_attr == 25'd16777215
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_lanepcs_locovren_attr == SERDES_IP_LANE_L0_CFG_LANEPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_lanepcs_mode_locovr_attr == SERDES_IP_LANE_L0_CFG_LANEPCS_MODE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_laneperfmon_compare_val_start_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_laneperfmon_compare_val_stop_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_laneperfmon_en_attr == SERDES_IP_LANE_L0_CFG_LANEPERFMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_laneperfmon_mask_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_lanepmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_lanepmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_lanepmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_lanepmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_lanepmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_lanepmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_lb_cdrclk2txen_locovr_attr == SERDES_IP_LANE_L0_CFG_LB_CDRCLK2TXEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_lb_cdrclkdiven_attr == SERDES_IP_LANE_L0_CFG_LB_CDRCLKDIVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_lb_cdrdivclk2exten_attr == SERDES_IP_LANE_L0_CFG_LB_CDRDIVCLK2EXTEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_lb_cdrdivclk2txen_attr == SERDES_IP_LANE_L0_CFG_LB_CDRDIVCLK2TXEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_lb_hsclk2cdrdiven_attr == SERDES_IP_LANE_L0_CFG_LB_HSCLK2CDRDIVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_lb_locovren_attr == SERDES_IP_LANE_L0_CFG_LB_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_lb_parrx2txtimeden_locovr_attr == SERDES_IP_LANE_L0_CFG_LB_PARRX2TXTIMEDEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_lb_pllfbclk2cdrrefclken_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_lb_pllfbclk2cdrrefclken_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_lb_pllfbclk2cdrrefclken_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_lb_pllfbclk2cdrrefclken_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_lb_pllfbclk2cdrrefclken_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_lb_rx2txuntimeden_attr == SERDES_IP_LANE_L0_CFG_LB_RX2TXUNTIMEDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_lb_rxwordck2pcstxwordcken_attr == SERDES_IP_LANE_L0_CFG_LB_RXWORDCK2PCSTXWORDCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_lb_tx2rxbuftimeden_lsb_locovr_attr == SERDES_IP_LANE_L0_CFG_LB_TX2RXBUFTIMEDEN_LSB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_lb_tx2rxbuftimeden_msb_locovr_attr == SERDES_IP_LANE_L0_CFG_LB_TX2RXBUFTIMEDEN_MSB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_lb_tx2rxiotimeden_attr == SERDES_IP_LANE_L0_CFG_LB_TX2RXIOTIMEDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_lfps_det_locovr_attr == SERDES_IP_LANE_L0_CFG_LFPS_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_lfps_locovren_attr == SERDES_IP_LANE_L0_CFG_LFPS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_lfps_out_en_attr == SERDES_IP_LANE_L0_CFG_LFPS_OUT_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_pcslfps_en_locovr_attr == SERDES_IP_LANE_L0_CFG_PCSLFPS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_pcslfps_locovren_attr == SERDES_IP_LANE_L0_CFG_PCSLFPS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_pcsrx_dme_en_locovr_attr == SERDES_IP_LANE_L0_CFG_PCSRX_DME_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_pcsrx_locovren_attr == SERDES_IP_LANE_L0_CFG_PCSRX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_pcsrxbist_locovren_attr == SERDES_IP_LANE_L0_CFG_PCSRXBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_pcsrxbist_modesel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_pcstx_beaconen_locovr_attr == SERDES_IP_LANE_L0_CFG_PCSTX_BEACONEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_pcstx_locovren_attr == SERDES_IP_LANE_L0_CFG_PCSTX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_polarity_rx_attr == SERDES_IP_LANE_L0_CFG_POLARITY_RX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_polarity_tx_attr == SERDES_IP_LANE_L0_CFG_POLARITY_TX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rx_cmn_on_state_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rx_fastregpwrup_en_attr == SERDES_IP_LANE_L0_CFG_RX_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rx_frac_mode_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rx_on_state_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rx_pg_disable_attr == SERDES_IP_LANE_L0_CFG_RX_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rx_synth_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rx_synth_sel_amode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rx_synth_sel_bmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rx_synth_sel_cmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rx_synth_sel_dmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rx_synth_sel_emode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxadc_req_attr == SERDES_IP_LANE_L0_CFG_RXADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxagc_dccoupleen_attr == SERDES_IP_LANE_L0_CFG_RXAGC_DCCOUPLEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxaprobe_addr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxaprobe_lastmux_isolate_attr == SERDES_IP_LANE_L0_CFG_RXAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxaprobeadc_current_direction_attr == SERDES_IP_LANE_L0_CFG_RXAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxaprobeadc_resistor_enable_attr == SERDES_IP_LANE_L0_CFG_RXAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxbias_iccadj_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxbias_icvadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxbias_locovren_attr == SERDES_IP_LANE_L0_CFG_RXBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxbias_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxbist_burst_four_errtype_attr == SERDES_IP_LANE_L0_CFG_RXBIST_BURST_FOUR_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxbist_burst_one_errtype_attr == SERDES_IP_LANE_L0_CFG_RXBIST_BURST_ONE_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxbist_burst_three_errtype_attr == SERDES_IP_LANE_L0_CFG_RXBIST_BURST_THREE_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxbist_burst_two_errtype_attr == SERDES_IP_LANE_L0_CFG_RXBIST_BURST_TWO_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxbist_cdrlock2data_bypass_attr == SERDES_IP_LANE_L0_CFG_RXBIST_CDRLOCK2DATA_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxbist_cdrlock2data_postamble_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxbist_clear_errcount_attr == SERDES_IP_LANE_L0_CFG_RXBIST_CLEAR_ERRCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxbist_err_en_attr == SERDES_IP_LANE_L0_CFG_RXBIST_ERR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxbist_err_trig_type_attr == SERDES_IP_LANE_L0_CFG_RXBIST_ERR_TRIG_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxbist_errmask_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxbist_errtype_attr == SERDES_IP_LANE_L0_CFG_RXBIST_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxbist_firsterr_type_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxbist_lockchk_count_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxbist_maxbitcnt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxbist_mostrecent_err_attr == SERDES_IP_LANE_L0_CFG_RXBIST_MOSTRECENT_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxbist_relock_itercount_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxbist_seed_attr == 31'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxbist_status_hold_attr == SERDES_IP_LANE_L0_CFG_RXBIST_STATUS_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxbitslip_locovr_attr == SERDES_IP_LANE_L0_CFG_RXBITSLIP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxbitslip_locovren_attr == SERDES_IP_LANE_L0_CFG_RXBITSLIP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxbscan_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxbshicm_attr == SERDES_IP_LANE_L0_CFG_RXBSHICM_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalcdrfbdiv_div2_bypass_muxd0_attr == SERDES_IP_LANE_L0_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalcdrfbdiv_div2_bypass_muxd1_attr == SERDES_IP_LANE_L0_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalcdrfbdiv_div2_bypass_muxd2_attr == SERDES_IP_LANE_L0_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalcdrfbdiv_div2_bypass_muxd3_attr == SERDES_IP_LANE_L0_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalcdrfbdiv_div2_bypass_muxd4_attr == SERDES_IP_LANE_L0_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalduty_iclk_gray_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalduty_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTY_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalduty_qclk_gray_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalduty_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutybg_abort_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutybg_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutybg_ready_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycomp_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycomp_offset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_finish_side_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_init_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_initval_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_invert_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_round_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_runcount_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_signmagen_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsmout_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsmout_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_disable_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCTRL_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_i_div1_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_i_div2_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_i_div4_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_i_div8_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_q_div1_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_q_div2_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_q_div4_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_q_div8_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_bg_en_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_bg_one_step_cal_en_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_finish_side_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_i_polarity_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_I_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_i_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_I_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_init_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_q_polarity_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_Q_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_q_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_Q_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_round_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_runcount_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_signmagen_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_comp_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEAS_COMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_comp_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEAS_COMP_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_i_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEAS_I_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_i_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEAS_I_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_q_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEAS_Q_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_q_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEAS_Q_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeasout_comp_ack_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEASOUT_COMP_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeasout_comp_erravg_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEASOUT_COMP_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeasout_i_ack_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEASOUT_I_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeasout_i_erravg_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEASOUT_I_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeasout_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeasout_q_ack_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEASOUT_Q_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeasout_q_erravg_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEASOUT_Q_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutystat_done_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaldutystat_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_centerfreq_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_end_delay_attr == 9'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_hscount_muxd0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_hscount_muxd1_attr == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_hscount_muxd2_attr == 8'd180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_hscount_muxd3_attr == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_hscount_muxd4_attr == 8'd206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_initval_centerfreq_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_initval_fosc_attr == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_centerfreq_finish_side_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_CENTERFREQ_FINISH_SIDE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_centerfreq_to_fosc_offset_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_centerfreqen_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_CENTERFREQEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_centerfreqoffset_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_fosc_finishside_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_FOSC_FINISHSIDE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_foscen_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_FOSCEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_foscoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_init_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_invert_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_lpfax_calfosccoarse_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_lpfax_calfoscfine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_lpfax_centerfreqcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_lpfax_centerfreqfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_runcount_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_signmagen_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_vcorepen_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_VCOREPEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsmout_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsmout_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_count_muxd0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_count_muxd1_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_count_muxd2_attr == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_count_muxd3_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_count_muxd4_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_dlycount_attr == 9'd68
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeasout_clear_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCMEASOUT_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeasout_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeasout_start_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCMEASOUT_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscval_int_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscval_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalintsval_int_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalintsval_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALINTSVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaloffsetfsm_init_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaloffsetfsm_init_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaloffsetfsm_init_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALOFFSETFSM_INIT_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaloffsetfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcaloffsetfsmout_input_en_attr == SERDES_IP_LANE_L0_CFG_RXCALOFFSETFSMOUT_INPUT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_duty_i_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_duty_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_dutycomp_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_foscfsm_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_offsetfsm_init_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_regopampoffset_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_rxppm_lockstatus_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_sqlch_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_sqlchosc_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_synthppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_voscregopampoffset_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_duty_i_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_duty_q_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_dutycomp_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_foscfsm_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_offsetfsm_init_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_rxppm_lockstatus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_sqlch_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_sqlchosc_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_synthppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_voscregopampoffset_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffset_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_finish_side_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_round_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_runcount_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_signmagen_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchfsm_clear_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchfsm_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchfsmout_caldone_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHFSMOUT_CALDONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchfsmout_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_codeoffset_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_finish_side_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHOSCFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_init_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHOSCFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_initval_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_invert_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHOSCFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHOSCFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHOSCFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_round_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHOSCFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_runcount_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHOSCFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscmeas_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHOSCMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscmeas_ref_cnt_attr == 10'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscmeas_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHOSCMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscmeas_settle_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscmeas_smpl_cnt_attr == 10'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvbiascap_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALVBIASCAP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvbiascap_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALVBIASCAP_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvcoopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvcoopampoffsetmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvcoopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvcoopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffset_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffset_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_codeoffset_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_finish_side_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_initval_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_invert_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_lpfaxcoarse_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_round_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_runcount_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETFSM_RUNCOUNT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_signmagen_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsmout_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsmout_runcount_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETFSMOUT_RUNCOUNT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetmeas_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffset_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALVOSCREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALVOSCREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L0_CFG_RXCALVOSCREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALVOSCREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALVOSCREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALVOSCREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALVOSCREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALVOSCREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALVOSCREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrdiv_local_en_attr == SERDES_IP_LANE_L0_CFG_RXCDRDIV_LOCAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdiv_moddiv_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdiv_moddiv_muxd1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdiv_moddiv_muxd2_attr == 4'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdiv_moddiv_muxd3_attr == 4'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdiv_moddiv_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdivslip_mdiv_muxd0_attr == 9'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdivslip_mdiv_muxd1_attr == 9'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdivslip_mdiv_muxd2_attr == 9'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdivslip_mdiv_muxd3_attr == 9'd66
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdivslip_mdiv_muxd4_attr == 9'd210
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrpfd_forcedn_attr == SERDES_IP_LANE_L0_CFG_RXCDRPFD_FORCEDN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrpfd_forceen_attr == SERDES_IP_LANE_L0_CFG_RXCDRPFD_FORCEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrpfd_forceup_attr == SERDES_IP_LANE_L0_CFG_RXCDRPFD_FORCEUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrpfd_propgain_attr == SERDES_IP_LANE_L0_CFG_RXCDRPFD_PROPGAIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrpfd_pulsewidth_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrphd_asym_override_ignore_attr == SERDES_IP_LANE_L0_CFG_RXCDRPHD_ASYM_OVERRIDE_IGNORE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrphd_bitshift_en_attr == SERDES_IP_LANE_L0_CFG_RXCDRPHD_BITSHIFT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrphd_forcedn_attr == SERDES_IP_LANE_L0_CFG_RXCDRPHD_FORCEDN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrphd_forceen_attr == SERDES_IP_LANE_L0_CFG_RXCDRPHD_FORCEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrphd_forceup_attr == SERDES_IP_LANE_L0_CFG_RXCDRPHD_FORCEUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrphdrate_doublerate2s2p_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCDRPHDRATE_DOUBLERATE2S2P_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrphdrate_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCDRPHDRATE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrrefck_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrrefck_refdiv_muxd1_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrrefck_refdiv_muxd2_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrrefck_refdiv_muxd3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrrefck_refdiv_muxd4_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_biastop_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_biastopbypass_attr == SERDES_IP_LANE_L0_CFG_RXCDRVCO_BIASTOPBYPASS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_datapropgain_high_attr == 5'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_datapropgain_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_datapropgain_low_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_ff_ovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_ff_ovr_en_attr == SERDES_IP_LANE_L0_CFG_RXCDRVCO_FF_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_fil_short_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_flickerdegen_attr == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_gmfoscshort_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCDRVCO_GMFOSCSHORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_intf_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_intf_fil_short_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_intrj_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCDRVCO_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_refpropgain_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_refpropgain_nom_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxclk_cdrfb_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCLK_CDRFB_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxclk_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxclk_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdat_nrz_64b80b_bcword_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdata_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXDATA_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdata_locovren_attr == SERDES_IP_LANE_L0_CFG_RXDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdatapath_locovren_attr == SERDES_IP_LANE_L0_CFG_RXDATAPATH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdatapath_on_state_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdatapath_ready_locovr_attr == SERDES_IP_LANE_L0_CFG_RXDATAPATH_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdfe_datatap_vcasc_attr == 4'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdfe_dfebiasadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdfe_nbiasctle_en_attr == SERDES_IP_LANE_L0_CFG_RXDFE_NBIASCTLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdfe_vcasc_sel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdfeterm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXDFETERM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdfeterm_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdfeyadjdac_datamid_edge_coarse_en_attr == SERDES_IP_LANE_L0_CFG_RXDFEYADJDAC_DATAMID_EDGE_COARSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdfeyadjdac_datatopbot_aux_coarse_en_attr == SERDES_IP_LANE_L0_CFG_RXDFEYADJDAC_DATATOPBOT_AUX_COARSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_accum_mon_en_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_ACCUM_MON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_accum_mon_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_bypasscdrpdetupdnsmpl_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_bypassenfosc_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_BYPASSENFOSC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_bypassenints_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_BYPASSENINTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_bypassenupdnsmpl_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_BYPASSENUPDNSMPL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_bypassfosc_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_bypasspllpfdupdnsmpl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_bypassrxints_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_data2pll_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_deltasigmode_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_DELTASIGMODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_fastref_muxd0_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_FASTREF_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_fastref_muxd1_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_FASTREF_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_fastref_muxd2_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_FASTREF_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_fastref_muxd3_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_FASTREF_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_fastref_muxd4_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_FASTREF_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_fosc_mod_bypass_en_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_FOSC_MOD_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_fosc_sample_pedge_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_FOSC_SAMPLE_PEDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gain_step_on_lock_recovery_en_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_GAIN_STEP_ON_LOCK_RECOVERY_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gaindelaycount_init_attr == 9'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gaindelaycount_pow2_muxd0_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gaindelaycount_pow2_muxd1_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gaindelaycount_pow2_muxd2_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gaindelaycount_pow2_muxd3_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gaindelaycount_pow2_muxd4_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2ref_pow2_muxd0_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2ref_pow2_muxd1_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2ref_pow2_muxd2_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2ref_pow2_muxd3_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2ref_pow2_muxd4_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainunlocked_pow2_muxd0_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainunlocked_pow2_muxd1_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainunlocked_pow2_muxd2_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainunlocked_pow2_muxd3_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainunlocked_pow2_muxd4_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_initintegrator_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_INITINTEGRATOR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_initmodulator_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_INITMODULATOR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_deltasig_mode_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_INTS_DELTASIG_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_freeze_en_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_INTS_FREEZE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gaindelaycount_pow2_muxd0_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gaindelaycount_pow2_muxd1_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gaindelaycount_pow2_muxd2_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gaindelaycount_pow2_muxd3_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gaindelaycount_pow2_muxd4_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd0_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd1_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd2_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd3_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd4_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd0_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd1_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd2_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd3_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd4_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainunlocked_pow2_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainunlocked_pow2_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainunlocked_pow2_muxd2_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainunlocked_pow2_muxd3_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainunlocked_pow2_muxd4_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_guardband_hi_attr == 8'd200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_guardband_lo_attr == 8'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_loop_sel_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_INTS_LOOP_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_mod_bypass_en_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_INTS_MOD_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_mod_load_pedge_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_INTS_MOD_LOAD_PEDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_step_to_integer_en_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_INTS_STEP_TO_INTEGER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_jit_length_attr == 18'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_jit_mode_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_JIT_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_modck_ctrl_en_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_MODCK_CTRL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_pll2data_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_restore_cntr_attr == 9'd258
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_store_cntr_attr == 16'd258
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpif_trnsfrdelay_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpiffreeze_inten_attr == SERDES_IP_LANE_L0_CFG_RXDPIFFREEZE_INTEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdpiffreeze_moden_attr == SERDES_IP_LANE_L0_CFG_RXDPIFFREEZE_MODEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxdutyselpolarity_attr == SERDES_IP_LANE_L0_CFG_RXDUTYSELPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxflxgate_force_rxeq_gate_locovr_attr == SERDES_IP_LANE_L0_CFG_RXFLXGATE_FORCE_RXEQ_GATE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxflxgate_locovren_attr == SERDES_IP_LANE_L0_CFG_RXFLXGATE_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxfoscstat_done_locovr_attr == SERDES_IP_LANE_L0_CFG_RXFOSCSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxfoscstat_locovren_attr == SERDES_IP_LANE_L0_CFG_RXFOSCSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxfsm_cken_ovr_attr == SERDES_IP_LANE_L0_CFG_RXFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxfsm_cken_ovren_attr == SERDES_IP_LANE_L0_CFG_RXFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxints_prev_votes_hold_en_attr == SERDES_IP_LANE_L0_CFG_RXINTS_PREV_VOTES_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxlanepam_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXLANEPAM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxlanepam_locovren_attr == SERDES_IP_LANE_L0_CFG_RXLANEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxlock2datatmr_attr == 8'd240
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxlock2datatmr_short_attr == 8'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxntl_changeref_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxntl_changeref_val_locovr_attr == SERDES_IP_LANE_L0_CFG_RXNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxntl_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxntl_en_attr == SERDES_IP_LANE_L0_CFG_RXNTL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxntl_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxntl_locovren_attr == SERDES_IP_LANE_L0_CFG_RXNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxntl_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxntl_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxntl_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxntl_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxntl_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxntl_rxm_charge_up_locovr_attr == SERDES_IP_LANE_L0_CFG_RXNTL_RXM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxntl_rxm_pull_dn_locovr_attr == SERDES_IP_LANE_L0_CFG_RXNTL_RXM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxntl_rxm_sense_locovr_attr == SERDES_IP_LANE_L0_CFG_RXNTL_RXM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxntl_rxp_charge_up_locovr_attr == SERDES_IP_LANE_L0_CFG_RXNTL_RXP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxntl_rxp_pull_dn_locovr_attr == SERDES_IP_LANE_L0_CFG_RXNTL_RXP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxntl_rxp_sense_locovr_attr == SERDES_IP_LANE_L0_CFG_RXNTL_RXP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxntl_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_acc_freeze_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_ACC_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_cdrlock2data_gater_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_cdrlock2data_gater_hold_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_cdrlock2data_gater_ovrd_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_cdrlock2datatmr_optcl_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_cdrlock2datatmr_optcl_sel_ovrd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_enter_lock2data_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_ENTER_LOCK2DATA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_enter_lock2data_hold_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_ENTER_LOCK2DATA_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_exit_lock2data_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_EXIT_LOCK2DATA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_exit_lock2data_hold_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_EXIT_LOCK2DATA_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_force_lock2data_ovrd_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_FORCE_LOCK2DATA_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_force_lock2ref_ovrd_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_FORCE_LOCK2REF_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_hold_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_hold_timer_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_intf_ovrd_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_INTF_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_intf_ovrd_type_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_INTF_OVRD_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_mod_freeze_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_MOD_FREEZE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_ovrd_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_ppm_detect_freeze_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_PPM_DETECT_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_ppm_detect_freeze_ovrd_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_PPM_DETECT_FREEZE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_ppm_detect_hold_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_PPM_DETECT_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_prop_freeze_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_PROP_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_prop_freeze_ovrd_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_PROP_FREEZE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_rxdata_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_RXDATA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_skip_init_lock2data_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_SKIP_INIT_LOCK2DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxpam_bitorder_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxpam_gray_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXPAM_GRAY_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxpam_locovren_attr == SERDES_IP_LANE_L0_CFG_RXPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxpam_precode_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXPAM_PRECODE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_p5_muxd0_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIV_P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_p5_muxd1_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIV_P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_p5_muxd2_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIV_P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_p5_muxd3_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIV_P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_p5_muxd4_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIV_P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdivclken_muxd0_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIVCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdivclken_muxd1_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIVCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdivclken_muxd2_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIVCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdivclken_muxd3_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIVCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdivclken_muxd4_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIVCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxpcsbist_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXPCSBIST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxpcsbist_locovren_attr == SERDES_IP_LANE_L0_CFG_RXPCSBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxphd_gain_hold_en_attr == SERDES_IP_LANE_L0_CFG_RXPHD_GAIN_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxphd_gain_zero_locovr_attr == SERDES_IP_LANE_L0_CFG_RXPHD_GAIN_ZERO_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxphd_locovren_attr == SERDES_IP_LANE_L0_CFG_RXPHD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxphd_majvote_basegain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxphd_majvote_en_attr == SERDES_IP_LANE_L0_CFG_RXPHD_MAJVOTE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxphd_mute_cntr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxphd_nrz8b10b_pam16b20b_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxphd_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxphd_pam_transition_sel_attr == SERDES_IP_LANE_L0_CFG_RXPHD_PAM_TRANSITION_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxphd_sign_invert_attr == SERDES_IP_LANE_L0_CFG_RXPHD_SIGN_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxpostdiv_wait_for_lock_disable_attr == SERDES_IP_LANE_L0_CFG_RXPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxppm_freq_max_offset_h_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxppm_freq_max_offset_l_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxppm_freq_ref_cnt_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxppm_lockstatus_locovr_attr == SERDES_IP_LANE_L0_CFG_RXPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxppm_lockstatus_synthlcfast_en_attr == SERDES_IP_LANE_L0_CFG_RXPPM_LOCKSTATUS_SYNTHLCFAST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxppm_lockstatus_synthlcmed_en_attr == SERDES_IP_LANE_L0_CFG_RXPPM_LOCKSTATUS_SYNTHLCMED_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxppm_lockstatus_synthlcslow_en_attr == SERDES_IP_LANE_L0_CFG_RXPPM_LOCKSTATUS_SYNTHLCSLOW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxppm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxppm_ppmdriftcount_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxppm_ppmdriftmax_attr == 16'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxppm_status_hold_attr == SERDES_IP_LANE_L0_CFG_RXPPM_STATUS_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxppm_unlock_clear_attr == SERDES_IP_LANE_L0_CFG_RXPPM_UNLOCK_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_fast_muxd0_attr == 16'd666
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_fast_muxd1_attr == 16'd4000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_fast_muxd2_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_fast_muxd3_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_fast_muxd4_attr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_muxd0_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_muxd1_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_muxd2_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_muxd3_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_muxd4_attr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxppmctrl_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXPPMCTRL_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxppmctrl_locovren_attr == SERDES_IP_LANE_L0_CFG_RXPPMCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxppmlockstat_locovren_attr == SERDES_IP_LANE_L0_CFG_RXPPMLOCKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxppmlockstat_sticky_locovr_attr == SERDES_IP_LANE_L0_CFG_RXPPMLOCKSTAT_STICKY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxppmtmr_locovren_attr == SERDES_IP_LANE_L0_CFG_RXPPMTMR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxppmtmr_watchdogtmr_sel_locovr_attr == SERDES_IP_LANE_L0_CFG_RXPPMTMR_WATCHDOGTMR_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_cal_clear_delay_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_clk_chk_disable_attr == SERDES_IP_LANE_L0_CFG_RXRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_clk_delay_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_etr_on_delay_attr == 12'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_locovren_attr == SERDES_IP_LANE_L0_CFG_RXRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxreg_lev_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxreg_toggle_reset_on_rate_change_en_attr == SERDES_IP_LANE_L0_CFG_RXREG_TOGGLE_RESET_ON_RATE_CHANGE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxreg_vreg_bypass_attr == SERDES_IP_LANE_L0_CFG_RXREG_VREG_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_en_b_attr == SERDES_IP_LANE_L0_CFG_RXRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s0q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s0q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s2q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s2q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s2q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s2q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s2q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s2q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s2q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s3q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s3q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s3q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s3q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s3q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s3q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s3q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s3q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s4q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s4q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s5q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_entry2_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_entry4_attr == 13'd78
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_entry5_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_entry6_attr == 13'd1406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s0q2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s0q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s1q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s1q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s1q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s1q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s1q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s1q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s2q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s2q2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s2q3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s2q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s2q5_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s2q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s2q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s3q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s3q1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s3q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s3q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s3q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s3q5_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s3q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s3q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s4q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s4q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s5q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_aetrrx_cdrfbdivcken_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_AETRRX_CDRFBDIVCKEN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_aetrrx_cdrfbdivcken_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_AETRRX_CDRFBDIVCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_aetrrx_cdrmoddivcken_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_AETRRX_CDRMODDIVCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_aetrrx_cdrmoddivcken_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_AETRRX_CDRMODDIVCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_aetrrx_termhiz_en_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_AETRRX_TERMHIZ_EN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_aetrrx_termhiz_en_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_AETRRX_TERMHIZ_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_aetrsynth_pcspostdivclksel_ovr_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_AETRSYNTH_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_aetrsynth_pcspostdivclksel_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_AETRSYNTH_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_adc_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_adc_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_auxcomp_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_AUXCOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_auxcomp_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_AUXCOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_bias_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_bias_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_BIAS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_ctlecomp_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_CTLECOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_ctlecomp_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_CTLECOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_datfbdiv_b_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DATFBDIV_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_datfbdiv_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DATFBDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_dfe_bias_b_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DFE_BIAS_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_dfe_bias_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DFE_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_dfe_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DFE_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_dfe_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DFE_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_dfe_yadj_b_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DFE_YADJ_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_dfe_yadj_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DFE_YADJ_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_duty_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DUTY_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_duty_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DUTY_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_hifreqagc_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_HIFREQAGC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_hifreqagc_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_HIFREQAGC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_ntl_b_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_ntl_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_reg_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_reg_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_vco_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_VCO_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_vco_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_VCO_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_voscreg_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_VOSCREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_voscreg_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_VOSCREG_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_adc_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_adc_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_cdrfbdiv_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_CDRFBDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_cdrfbdiv_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_CDRFBDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_pdet_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_PDET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_pdet_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_PDET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_pfd_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_PFD_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_pfd_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_PFD_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_refdiv_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_refdiv_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_reg_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_reg_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_s2pa_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_S2PA_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_s2pa_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_S2PA_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_s2pb_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_S2PB_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_s2pb_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_S2PB_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_vco_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_VCO_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_vco_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_VCO_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_voscreg_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_VOSCREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_voscreg_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_VOSCREG_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstsynth_postdiv_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTSYNTH_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstsynth_postdiv_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTSYNTH_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_drstrx_dpif_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_DRSTRX_DPIF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_drstrx_dpif_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_DRSTRX_DPIF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_drstrx_ppm_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_DRSTRX_PPM_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_drstrx_ppm_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_DRSTRX_PPM_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_cdrlock2data_locovr_attr == SERDES_IP_LANE_L0_CFG_RXSIGDET_CDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_diglfpsdeten_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_diglfpsdeten_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_diglfpsdeten_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_diglfpsdeten_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_diglfpsdeten_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrancnten_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrancnten_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrancnten_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrancnten_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrancnten_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrancnten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrandeten_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrandeten_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrandeten_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrandeten_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrandeten_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrandeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_eiosdeten_muxd0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_eiosdeten_muxd1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_eiosdeten_muxd2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_eiosdeten_muxd3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_eiosdeten_muxd4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_eiosdeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_enable_attr == SERDES_IP_LANE_L0_CFG_RXSIGDET_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_fastlock_winsize_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_leveldeten_muxd0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_leveldeten_muxd1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_leveldeten_muxd2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_leveldeten_muxd3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_leveldeten_muxd4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_leveldeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_lfpsexit_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_locovren_attr == SERDES_IP_LANE_L0_CFG_RXSIGDET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_ppmdeten_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_ppmdeten_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_ppmdeten_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_ppmdeten_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_ppmdeten_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_ppmdeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_rxeq_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_rxeqen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_rxeqen_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_rxleveldet_debounce_dncount_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_rxleveldet_debounce_flush_en_attr == SERDES_IP_LANE_L0_CFG_RXSIGDET_RXLEVELDET_DEBOUNCE_FLUSH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_rxleveldet_debounce_upcount_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_sigdet_debounce_attr == SERDES_IP_LANE_L0_CFG_RXSIGDET_SIGDET_DEBOUNCE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_tmr_clksel_attr == SERDES_IP_LANE_L0_CFG_RXSIGDET_TMR_CLKSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_toggle_count_en_attr == SERDES_IP_LANE_L0_CFG_RXSIGDET_TOGGLE_COUNT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_toggle_count_pause_attr == SERDES_IP_LANE_L0_CFG_RXSIGDET_TOGGLE_COUNT_PAUSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_toggle_monitor_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdetin_eiosdetectstat_locovr_attr == SERDES_IP_LANE_L0_CFG_RXSIGDETIN_EIOSDETECTSTAT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdetin_locovren_attr == SERDES_IP_LANE_L0_CFG_RXSIGDETIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdetin_ovrcdrlock2data_locovr_attr == SERDES_IP_LANE_L0_CFG_RXSIGDETIN_OVRCDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdetin_ovrencdrlock2data_locovr_attr == SERDES_IP_LANE_L0_CFG_RXSIGDETIN_OVRENCDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdetout_lock2data_noforce_ltr_locovr_attr == SERDES_IP_LANE_L0_CFG_RXSIGDETOUT_LOCK2DATA_NOFORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsigdetout_locovren_attr == SERDES_IP_LANE_L0_CFG_RXSIGDETOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxspare0_attr == 32'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxspare_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsqlchlfps_consec_one_thresh_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsqlchlfps_consec_zero_thresh_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsqlchlfps_cycle_thresh_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsqlchlfps_dat_bitorder_attr == SERDES_IP_LANE_L0_CFG_RXSQLCHLFPS_DAT_BITORDER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsqlchlfps_debounce_type_attr == SERDES_IP_LANE_L0_CFG_RXSQLCHLFPS_DEBOUNCE_TYPE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsqlchlfps_one_run_length_thresh_attr == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsqlchlfps_one_run_length_timeout_attr == 8'd103
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsqlchlfps_zero_run_length_thresh_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsqlchlfps_zero_run_length_timeout_attr == 8'd103
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsynthdiv_slowmed_en_muxd0_attr == SERDES_IP_LANE_L0_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsynthdiv_slowmed_en_muxd1_attr == SERDES_IP_LANE_L0_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsynthdiv_slowmed_en_muxd2_attr == SERDES_IP_LANE_L0_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsynthdiv_slowmed_en_muxd3_attr == SERDES_IP_LANE_L0_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxsynthdiv_slowmed_en_muxd4_attr == SERDES_IP_LANE_L0_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxterm_cal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxterm_coarse_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxterm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXTERM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxterm_modeselect_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxtermhiz_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXTERMHIZ_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxtermhiz_locovren_attr == SERDES_IP_LANE_L0_CFG_RXTERMHIZ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxvoscreg_bypass_vosc_attr == SERDES_IP_LANE_L0_CFG_RXVOSCREG_BYPASS_VOSC_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxvoscregopampoffsetctrl_sel_attr == SERDES_IP_LANE_L0_CFG_RXVOSCREGOPAMPOFFSETCTRL_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxvoscregopampoffseterr_locovren_attr == SERDES_IP_LANE_L0_CFG_RXVOSCREGOPAMPOFFSETERR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxvoscregopampoffseterr_sel_locovr_attr == SERDES_IP_LANE_L0_CFG_RXVOSCREGOPAMPOFFSETERR_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxvoscregvref_locovren_attr == SERDES_IP_LANE_L0_CFG_RXVOSCREGVREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_rxvoscregvref_sel_locovr_attr == SERDES_IP_LANE_L0_CFG_RXVOSCREGVREF_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlch_acqgain_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlch_acqtime_attr == 13'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlch_cal_quiet_locovr_attr == SERDES_IP_LANE_L0_CFG_SQLCH_CAL_QUIET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlch_cal_sel_locovr_attr == SERDES_IP_LANE_L0_CFG_SQLCH_CAL_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlch_calctrl_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlch_calen_locovr_attr == SERDES_IP_LANE_L0_CFG_SQLCH_CALEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlch_caltimer_attr == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlch_clkgate_locovr_attr == SERDES_IP_LANE_L0_CFG_SQLCH_CLKGATE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlch_cmshiften_attr == SERDES_IP_LANE_L0_CFG_SQLCH_CMSHIFTEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_acq_gain_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_acq_pct_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_cal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_clr_errlog_attr == SERDES_IP_LANE_L0_CFG_SQLCH_CONT_CLR_ERRLOG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_controller_mode_attr == SERDES_IP_LANE_L0_CFG_SQLCH_CONT_CONTROLLER_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_dis_attr == SERDES_IP_LANE_L0_CFG_SQLCH_CONT_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_pause_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_postcal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_precal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_quiet_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlch_lfps_en_attr == SERDES_IP_LANE_L0_CFG_SQLCH_LFPS_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlch_locovren_attr == SERDES_IP_LANE_L0_CFG_SQLCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlch_ovrd_val_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlch_pkdet_freqsel_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlch_polarity_attr == SERDES_IP_LANE_L0_CFG_SQLCH_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlch_rdacen_attr == SERDES_IP_LANE_L0_CFG_SQLCH_RDACEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlch_thresh_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlch_time_out_attr == 16'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlch_vrefsel0_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlch_vrefsel1_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlch_vrefsel_ovr_en_attr == SERDES_IP_LANE_L0_CFG_SQLCH_VREFSEL_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlchdeb_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlchdeb_deb_cnt_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlchdeb_deb_status_cnt_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlchdeb_en_attr == SERDES_IP_LANE_L0_CFG_SQLCHDEB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlchdeb_ign_cnt_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlchdeb_sigdet_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlchdeb_thresh_cnt_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlchdebout_exit_good_debounced_locovr_attr == SERDES_IP_LANE_L0_CFG_SQLCHDEBOUT_EXIT_GOOD_DEBOUNCED_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlchdebout_exit_good_debounced_status_locovr_attr == SERDES_IP_LANE_L0_CFG_SQLCHDEBOUT_EXIT_GOOD_DEBOUNCED_STATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlchdebout_exit_good_locovr_attr == SERDES_IP_LANE_L0_CFG_SQLCHDEBOUT_EXIT_GOOD_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_sqlchdebout_locovren_attr == SERDES_IP_LANE_L0_CFG_SQLCHDEBOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_trancnt_off_attr == 10'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_trancnt_on_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_trancntout_det_locovr_attr == SERDES_IP_LANE_L0_CFG_TRANCNTOUT_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_trancntout_locovren_attr == SERDES_IP_LANE_L0_CFG_TRANCNTOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_trandet_ax_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_trandet_ay_attr == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_trandet_off_h_attr == 6'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_trandet_off_l_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_trandet_on_h_attr == 6'd39
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_trandet_on_l_attr == 6'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_trandetout_det_locovr_attr == SERDES_IP_LANE_L0_CFG_TRANDETOUT_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_trandetout_locovren_attr == SERDES_IP_LANE_L0_CFG_TRANDETOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_tx2rxlb_en_attr == SERDES_IP_LANE_L0_CFG_TX2RXLB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_tx2rxlb_init_offset_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_tx_cmn_on_state_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_tx_fastregpwrup_en_attr == SERDES_IP_LANE_L0_CFG_TX_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_tx_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_tx_pg_disable_attr == SERDES_IP_LANE_L0_CFG_TX_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_tx_synth_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_tx_synth_sel_amode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_tx_synth_sel_bmode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_tx_synth_sel_cmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_tx_synth_sel_dmode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_tx_synth_sel_emode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_tx_txdetrx_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txadc_req_attr == SERDES_IP_LANE_L0_CFG_TXADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txaprobe_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txaprobe_lastmux_isolate_attr == SERDES_IP_LANE_L0_CFG_TXAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txaprobeadc_current_direction_attr == SERDES_IP_LANE_L0_CFG_TXAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txaprobeadc_resistor_enable_attr == SERDES_IP_LANE_L0_CFG_TXAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txbdvdr_pma2pcstxworden_attr == SERDES_IP_LANE_L0_CFG_TXBDVDR_PMA2PCSTXWORDEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txbeacon_div_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txbeacon_sel_attr == SERDES_IP_LANE_L0_CFG_TXBEACON_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txbias_icc20uadj_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txbias_icc80uadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txbias_locovren_attr == SERDES_IP_LANE_L0_CFG_TXBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txbias_termcal_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txbist_biterror_en_attr == SERDES_IP_LANE_L0_CFG_TXBIST_BITERROR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txbist_locovren_attr == SERDES_IP_LANE_L0_CFG_TXBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txbist_modesel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txbist_oobmode_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txbist_oobtburst_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txbist_oobtcomrstinit_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txbist_oobtcomsas_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txbist_oobtcomwake_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txbist_seed_attr == 31'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_size_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf00_attr == 32'd1985229328
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf01_attr == 32'd4275878552
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf02_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf03_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf04_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf05_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf06_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf07_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf08_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf09_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txbit_select_muxd0_attr == SERDES_IP_LANE_L0_CFG_TXBIT_SELECT_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txbit_select_muxd1_attr == SERDES_IP_LANE_L0_CFG_TXBIT_SELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txbit_select_muxd2_attr == SERDES_IP_LANE_L0_CFG_TXBIT_SELECT_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txbit_select_muxd3_attr == SERDES_IP_LANE_L0_CFG_TXBIT_SELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txbit_select_muxd4_attr == SERDES_IP_LANE_L0_CFG_TXBIT_SELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txbti_data_replication_attr == SERDES_IP_LANE_L0_CFG_TXBTI_DATA_REPLICATION_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txbti_tx_idle_data_en_attr == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcal_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcal_tclkduty_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalduty_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalduty_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTY_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalduty_sel_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutybg_abort_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutybg_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutybg_ready_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutycomp_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutycomp_offset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_finish_side_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_init_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_initval_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_invert_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_req_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_round_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_runcount_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_signmagen_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsmout_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsmout_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompmeas_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompmeas_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompmeas_req_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompmeasout_ack_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPMEASOUT_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompmeasout_erravg_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPMEASOUT_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompmeasout_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_bg_en_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_bg_one_step_cal_en_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_finish_side_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_init_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_invert_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_req_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_round_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_runcount_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_signmagen_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeas_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeas_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeas_req_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeasout_ack_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYMEASOUT_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeasout_erravg_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYMEASOUT_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeasout_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutystat_done_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaldutystat_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalptr_pstate_duty_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalptr_pstate_dutycomp_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalptr_pstate_regopampoffset_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_duty_muxd0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_duty_muxd1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_duty_muxd2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_duty_muxd3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_duty_muxd4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_dutycomp_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_dutycomp_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_dutycomp_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_dutycomp_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_dutycomp_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_regopampoffset_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffset_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_finish_side_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_round_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_runcount_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_signmagen_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcaltclkdutyforce_div1_attr == SERDES_IP_LANE_L0_CFG_TXCALTCLKDUTYFORCE_DIV1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txcdrdiv_local_en_attr == SERDES_IP_LANE_L0_CFG_TXCDRDIV_LOCAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txclk_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txclk_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txclkgenmuxsel_txinternal_attr == SERDES_IP_LANE_L0_CFG_TXCLKGENMUXSEL_TXINTERNAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txdetectrx_thr_attr == 5'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeas_count_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeas_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXDETECTRXMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeas_locovren_attr == SERDES_IP_LANE_L0_CFG_TXDETECTRXMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeas_validdlycount_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeasin_locovren_attr == SERDES_IP_LANE_L0_CFG_TXDETECTRXMEASIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeasin_start_locovr_attr == SERDES_IP_LANE_L0_CFG_TXDETECTRXMEASIN_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeaspcs_locovren_attr == SERDES_IP_LANE_L0_CFG_TXDETECTRXMEASPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeaspcs_req_locovr_attr == SERDES_IP_LANE_L0_CFG_TXDETECTRXMEASPCS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeasval_locovren_attr == SERDES_IP_LANE_L0_CFG_TXDETECTRXMEASVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeasval_stat_locovr_attr == SERDES_IP_LANE_L0_CFG_TXDETECTRXMEASVAL_STAT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txdetrx_levn_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txdetrx_levnm1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txdetrx_levnp1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txdetrx_levnp2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txdrv_hizen_locovr_attr == SERDES_IP_LANE_L0_CFG_TXDRV_HIZEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txdrv_levn_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txdrv_levnm1_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txdrv_levnp1_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txdrv_levnp2_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txdrv_locovren_attr == SERDES_IP_LANE_L0_CFG_TXDRV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txdrv_refcken_attr == SERDES_IP_LANE_L0_CFG_TXDRV_REFCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txdrv_termref_attr == SERDES_IP_LANE_L0_CFG_TXDRV_TERMREF_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txdrvmute_locovr_attr == SERDES_IP_LANE_L0_CFG_TXDRVMUTE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txdrvmute_locovren_attr == SERDES_IP_LANE_L0_CFG_TXDRVMUTE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txduty_ctrl_disable_attr == SERDES_IP_LANE_L0_CFG_TXDUTY_CTRL_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txduty_pad_sense_en_attr == SERDES_IP_LANE_L0_CFG_TXDUTY_PAD_SENSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txdutycal_div16_en_attr == SERDES_IP_LANE_L0_CFG_TXDUTYCAL_DIV16_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txdutycal_div1_en_attr == SERDES_IP_LANE_L0_CFG_TXDUTYCAL_DIV1_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txdutycal_div2_en_attr == SERDES_IP_LANE_L0_CFG_TXDUTYCAL_DIV2_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txdutycal_div4_en_attr == SERDES_IP_LANE_L0_CFG_TXDUTYCAL_DIV4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txdutycal_div8_en_attr == SERDES_IP_LANE_L0_CFG_TXDUTYCAL_DIV8_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txfifo_elecidle_deskew_en_attr == SERDES_IP_LANE_L0_CFG_TXFIFO_ELECIDLE_DESKEW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txfifo_force_txidlebit1_zero_disable_attr == SERDES_IP_LANE_L0_CFG_TXFIFO_FORCE_TXIDLEBIT1_ZERO_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txfifo_kill_dly_10b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txfifo_kill_dly_16b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txfifo_kill_dly_20b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txfifo_kill_dly_32b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txfifo_kill_dly_40b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txfifo_kill_dly_64b_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txfifo_kill_dly_80b_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txfifo_kill_dly_8b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txfifo_kill_en_attr == SERDES_IP_LANE_L0_CFG_TXFIFO_KILL_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txfsm_cken_ovr_attr == SERDES_IP_LANE_L0_CFG_TXFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txfsm_cken_ovren_attr == SERDES_IP_LANE_L0_CFG_TXFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txfsm_main_on_state_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txl1d1_doze_ctrl_attr == SERDES_IP_LANE_L0_CFG_TXL1D1_DOZE_CTRL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txl1d1_txbias_ctrl_attr == SERDES_IP_LANE_L0_CFG_TXL1D1_TXBIAS_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txlanepam_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXLANEPAM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txlanepam_locovren_attr == SERDES_IP_LANE_L0_CFG_TXLANEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txmeaslatovrhd_meas_sel_attr == SERDES_IP_LANE_L0_CFG_TXMEASLATOVRHD_MEAS_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txmute_delay_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txntl_changeref_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txntl_changeref_val_locovr_attr == SERDES_IP_LANE_L0_CFG_TXNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txntl_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txntl_en_attr == SERDES_IP_LANE_L0_CFG_TXNTL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txntl_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txntl_locovren_attr == SERDES_IP_LANE_L0_CFG_TXNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txntl_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txntl_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txntl_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txntl_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txntl_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txntl_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txntl_txm_charge_up_locovr_attr == SERDES_IP_LANE_L0_CFG_TXNTL_TXM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txntl_txm_pull_dn_locovr_attr == SERDES_IP_LANE_L0_CFG_TXNTL_TXM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txntl_txm_sense_locovr_attr == SERDES_IP_LANE_L0_CFG_TXNTL_TXM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txntl_txp_charge_up_locovr_attr == SERDES_IP_LANE_L0_CFG_TXNTL_TXP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txntl_txp_pull_dn_locovr_attr == SERDES_IP_LANE_L0_CFG_TXNTL_TXP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txntl_txp_sense_locovr_attr == SERDES_IP_LANE_L0_CFG_TXNTL_TXP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txp2s_txwordsyncbypen_attr == SERDES_IP_LANE_L0_CFG_TXP2S_TXWORDSYNCBYPEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txpam_bitorder_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txpam_gray_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXPAM_GRAY_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txpam_locovren_attr == SERDES_IP_LANE_L0_CFG_TXPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txpam_precode_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXPAM_PRECODE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txpcs_locovren_attr == SERDES_IP_LANE_L0_CFG_TXPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txpcs_txenable_locovr_attr == SERDES_IP_LANE_L0_CFG_TXPCS_TXENABLE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txpcsbist_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXPCSBIST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txpcsbist_locovren_attr == SERDES_IP_LANE_L0_CFG_TXPCSBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txratewidth_clk_chk_disable_attr == SERDES_IP_LANE_L0_CFG_TXRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txratewidth_etr_on_delay_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txratewidth_locovren_attr == SERDES_IP_LANE_L0_CFG_TXRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txreg_toggle_pwrupacc_on_rate_change_en_attr == SERDES_IP_LANE_L0_CFG_TXREG_TOGGLE_PWRUPACC_ON_RATE_CHANGE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txreg_toggle_reset_on_rate_change_en_attr == SERDES_IP_LANE_L0_CFG_TXREG_TOGGLE_RESET_ON_RATE_CHANGE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txresetdel_sel_attr == SERDES_IP_LANE_L0_CFG_TXRESETDEL_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_en_b_attr == SERDES_IP_LANE_L0_CFG_TXRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s0q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s0q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s1q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s1q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s2q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s2q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s2q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s2q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s2q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s2q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s2q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s3q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s3q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s3q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s3q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s3q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s3q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s3q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s3q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s4q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s4q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s5q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_entry2_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s0q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s0q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s1q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s1q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s1q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s1q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s1q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s1q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s2q0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s2q1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s2q2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s2q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s2q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s2q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s2q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s2q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s3q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s3q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s3q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s3q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s3q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s3q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s3q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s3q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s4q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s4q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s5q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_dn_ptr0_s_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_up_ptr0_s_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_aetrtx_bitckdvdrcken_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_AETRTX_BITCKDVDRCKEN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_aetrtx_bitckdvdrcken_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_AETRTX_BITCKDVDRCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_aetrtx_regpwrupacc_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_AETRTX_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_aetrtx_regpwrupacc_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_AETRTX_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_adc_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_adc_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_drvdoze_b_ovr_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_DRVDOZE_B_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_drvdoze_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_DRVDOZE_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_duty_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_DUTY_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_duty_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_DUTY_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_ntl_b_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_ntl_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_p2s_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_P2S_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_p2s_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_P2S_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_reg_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_reg_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_arsttx_adc_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_ARSTTX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_arsttx_adc_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_ARSTTX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_arsttx_pma2pcstxword_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_ARSTTX_PMA2PCSTXWORD_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_arsttx_pma2pcstxword_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_ARSTTX_PMA2PCSTXWORD_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_arsttx_regreset_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_ARSTTX_REGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_arsttx_regreset_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_ARSTTX_REGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_arsttx_txdetectrx_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_ARSTTX_TXDETECTRX_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_arsttx_txdetectrx_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_ARSTTX_TXDETECTRX_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txrststate_hiz_en_attr == SERDES_IP_LANE_L0_CFG_TXRSTSTATE_HIZ_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txspare0_attr == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txspare_attr == 10'd384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txterm_coarse_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txtermtrim_locovren_attr == SERDES_IP_LANE_L0_CFG_TXTERMTRIM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txtermtrim_nmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txtermtrim_pmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txwclk_div_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txwclk_div_en_attr == SERDES_IP_LANE_L0_CFG_TXWCLK_DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txwclk_div_smpl_attr == SERDES_IP_LANE_L0_CFG_TXWCLK_DIV_SMPL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txwptr_init01_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txwptr_init02_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txwptr_init04_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txwptr_init08_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txwptr_init16_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txwptr_init32_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l0_cfg_txwptr_init_rx2txparlb_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_bshihyst_attr == SERDES_IP_LANE_L1_CFG_BSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_bstxdrv_levn_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_bstxdrv_levnm1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_bstxdrv_levnp1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_bstxdrv_levnp2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_calsqlchosc_locovren_attr == SERDES_IP_LANE_L1_CFG_CALSQLCHOSC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_calsqlchosc_trimcode_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_cdrclkstat_locovren_attr == SERDES_IP_LANE_L1_CFG_CDRCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_cdrclkstat_ready_locovr_attr == SERDES_IP_LANE_L1_CFG_CDRCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_etrregrxcdrclk_ready_attr == SERDES_IP_LANE_L1_CFG_ETRREGRXCDRCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_laneckm_avg_en_attr == SERDES_IP_LANE_L1_CFG_LANECKM_AVG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_laneckm_clk_en_attr == SERDES_IP_LANE_L1_CFG_LANECKM_CLK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_laneckm_continuous_attr == SERDES_IP_LANE_L1_CFG_LANECKM_CONTINUOUS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_laneckm_dig_meas_en_attr == SERDES_IP_LANE_L1_CFG_LANECKM_DIG_MEAS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_laneckm_dig_meas_err_clr_attr == SERDES_IP_LANE_L1_CFG_LANECKM_DIG_MEAS_ERR_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_laneckm_en_attr == SERDES_IP_LANE_L1_CFG_LANECKM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_laneckm_max_thr_attr == 25'd33554431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_laneckm_meas_ck_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_laneckm_ref_ck_div_ratio_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_laneckm_result_clr_attr == SERDES_IP_LANE_L1_CFG_LANECKM_RESULT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_laneckm_start_attr == SERDES_IP_LANE_L1_CFG_LANECKM_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_laneckm_wdt_interval_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_laneckm_win_thr_ref_attr == 25'd16777215
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_lanepcs_locovren_attr == SERDES_IP_LANE_L1_CFG_LANEPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_lanepcs_mode_locovr_attr == SERDES_IP_LANE_L1_CFG_LANEPCS_MODE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_laneperfmon_compare_val_start_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_laneperfmon_compare_val_stop_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_laneperfmon_en_attr == SERDES_IP_LANE_L1_CFG_LANEPERFMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_laneperfmon_mask_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_lanepmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_lanepmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_lanepmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_lanepmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_lanepmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_lanepmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_lb_cdrclk2txen_locovr_attr == SERDES_IP_LANE_L1_CFG_LB_CDRCLK2TXEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_lb_cdrclkdiven_attr == SERDES_IP_LANE_L1_CFG_LB_CDRCLKDIVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_lb_cdrdivclk2exten_attr == SERDES_IP_LANE_L1_CFG_LB_CDRDIVCLK2EXTEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_lb_cdrdivclk2txen_attr == SERDES_IP_LANE_L1_CFG_LB_CDRDIVCLK2TXEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_lb_hsclk2cdrdiven_attr == SERDES_IP_LANE_L1_CFG_LB_HSCLK2CDRDIVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_lb_locovren_attr == SERDES_IP_LANE_L1_CFG_LB_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_lb_parrx2txtimeden_locovr_attr == SERDES_IP_LANE_L1_CFG_LB_PARRX2TXTIMEDEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_lb_pllfbclk2cdrrefclken_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_lb_pllfbclk2cdrrefclken_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_lb_pllfbclk2cdrrefclken_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_lb_pllfbclk2cdrrefclken_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_lb_pllfbclk2cdrrefclken_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_lb_rx2txuntimeden_attr == SERDES_IP_LANE_L1_CFG_LB_RX2TXUNTIMEDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_lb_rxwordck2pcstxwordcken_attr == SERDES_IP_LANE_L1_CFG_LB_RXWORDCK2PCSTXWORDCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_lb_tx2rxbuftimeden_lsb_locovr_attr == SERDES_IP_LANE_L1_CFG_LB_TX2RXBUFTIMEDEN_LSB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_lb_tx2rxbuftimeden_msb_locovr_attr == SERDES_IP_LANE_L1_CFG_LB_TX2RXBUFTIMEDEN_MSB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_lb_tx2rxiotimeden_attr == SERDES_IP_LANE_L1_CFG_LB_TX2RXIOTIMEDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_lfps_det_locovr_attr == SERDES_IP_LANE_L1_CFG_LFPS_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_lfps_locovren_attr == SERDES_IP_LANE_L1_CFG_LFPS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_lfps_out_en_attr == SERDES_IP_LANE_L1_CFG_LFPS_OUT_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_pcslfps_en_locovr_attr == SERDES_IP_LANE_L1_CFG_PCSLFPS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_pcslfps_locovren_attr == SERDES_IP_LANE_L1_CFG_PCSLFPS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_pcsrx_dme_en_locovr_attr == SERDES_IP_LANE_L1_CFG_PCSRX_DME_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_pcsrx_locovren_attr == SERDES_IP_LANE_L1_CFG_PCSRX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_pcsrxbist_locovren_attr == SERDES_IP_LANE_L1_CFG_PCSRXBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_pcsrxbist_modesel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_pcstx_beaconen_locovr_attr == SERDES_IP_LANE_L1_CFG_PCSTX_BEACONEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_pcstx_locovren_attr == SERDES_IP_LANE_L1_CFG_PCSTX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_polarity_rx_attr == SERDES_IP_LANE_L1_CFG_POLARITY_RX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_polarity_tx_attr == SERDES_IP_LANE_L1_CFG_POLARITY_TX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rx_cmn_on_state_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rx_fastregpwrup_en_attr == SERDES_IP_LANE_L1_CFG_RX_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rx_frac_mode_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rx_on_state_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rx_pg_disable_attr == SERDES_IP_LANE_L1_CFG_RX_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rx_synth_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rx_synth_sel_amode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rx_synth_sel_bmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rx_synth_sel_cmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rx_synth_sel_dmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rx_synth_sel_emode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxadc_req_attr == SERDES_IP_LANE_L1_CFG_RXADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxagc_dccoupleen_attr == SERDES_IP_LANE_L1_CFG_RXAGC_DCCOUPLEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxaprobe_addr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxaprobe_lastmux_isolate_attr == SERDES_IP_LANE_L1_CFG_RXAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxaprobeadc_current_direction_attr == SERDES_IP_LANE_L1_CFG_RXAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxaprobeadc_resistor_enable_attr == SERDES_IP_LANE_L1_CFG_RXAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxbias_iccadj_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxbias_icvadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxbias_locovren_attr == SERDES_IP_LANE_L1_CFG_RXBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxbias_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxbist_burst_four_errtype_attr == SERDES_IP_LANE_L1_CFG_RXBIST_BURST_FOUR_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxbist_burst_one_errtype_attr == SERDES_IP_LANE_L1_CFG_RXBIST_BURST_ONE_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxbist_burst_three_errtype_attr == SERDES_IP_LANE_L1_CFG_RXBIST_BURST_THREE_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxbist_burst_two_errtype_attr == SERDES_IP_LANE_L1_CFG_RXBIST_BURST_TWO_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxbist_cdrlock2data_bypass_attr == SERDES_IP_LANE_L1_CFG_RXBIST_CDRLOCK2DATA_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxbist_cdrlock2data_postamble_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxbist_clear_errcount_attr == SERDES_IP_LANE_L1_CFG_RXBIST_CLEAR_ERRCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxbist_err_en_attr == SERDES_IP_LANE_L1_CFG_RXBIST_ERR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxbist_err_trig_type_attr == SERDES_IP_LANE_L1_CFG_RXBIST_ERR_TRIG_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxbist_errmask_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxbist_errtype_attr == SERDES_IP_LANE_L1_CFG_RXBIST_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxbist_firsterr_type_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxbist_lockchk_count_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxbist_maxbitcnt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxbist_mostrecent_err_attr == SERDES_IP_LANE_L1_CFG_RXBIST_MOSTRECENT_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxbist_relock_itercount_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxbist_seed_attr == 31'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxbist_status_hold_attr == SERDES_IP_LANE_L1_CFG_RXBIST_STATUS_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxbitslip_locovr_attr == SERDES_IP_LANE_L1_CFG_RXBITSLIP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxbitslip_locovren_attr == SERDES_IP_LANE_L1_CFG_RXBITSLIP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxbscan_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxbshicm_attr == SERDES_IP_LANE_L1_CFG_RXBSHICM_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalcdrfbdiv_div2_bypass_muxd0_attr == SERDES_IP_LANE_L1_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalcdrfbdiv_div2_bypass_muxd1_attr == SERDES_IP_LANE_L1_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalcdrfbdiv_div2_bypass_muxd2_attr == SERDES_IP_LANE_L1_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalcdrfbdiv_div2_bypass_muxd3_attr == SERDES_IP_LANE_L1_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalcdrfbdiv_div2_bypass_muxd4_attr == SERDES_IP_LANE_L1_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalduty_iclk_gray_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalduty_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTY_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalduty_qclk_gray_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalduty_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutybg_abort_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutybg_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutybg_ready_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycomp_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycomp_offset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_finish_side_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_init_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_initval_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_invert_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_round_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_runcount_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_signmagen_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsmout_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsmout_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_disable_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCTRL_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_i_div1_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_i_div2_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_i_div4_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_i_div8_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_q_div1_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_q_div2_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_q_div4_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_q_div8_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_bg_en_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_bg_one_step_cal_en_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_finish_side_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_i_polarity_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_I_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_i_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_I_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_init_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_q_polarity_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_Q_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_q_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_Q_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_round_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_runcount_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_signmagen_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_comp_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEAS_COMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_comp_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEAS_COMP_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_i_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEAS_I_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_i_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEAS_I_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_q_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEAS_Q_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_q_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEAS_Q_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeasout_comp_ack_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEASOUT_COMP_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeasout_comp_erravg_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEASOUT_COMP_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeasout_i_ack_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEASOUT_I_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeasout_i_erravg_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEASOUT_I_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeasout_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeasout_q_ack_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEASOUT_Q_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeasout_q_erravg_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEASOUT_Q_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutystat_done_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaldutystat_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_centerfreq_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_end_delay_attr == 9'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_hscount_muxd0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_hscount_muxd1_attr == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_hscount_muxd2_attr == 8'd180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_hscount_muxd3_attr == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_hscount_muxd4_attr == 8'd206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_initval_centerfreq_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_initval_fosc_attr == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_centerfreq_finish_side_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_CENTERFREQ_FINISH_SIDE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_centerfreq_to_fosc_offset_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_centerfreqen_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_CENTERFREQEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_centerfreqoffset_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_fosc_finishside_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_FOSC_FINISHSIDE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_foscen_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_FOSCEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_foscoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_init_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_invert_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_lpfax_calfosccoarse_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_lpfax_calfoscfine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_lpfax_centerfreqcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_lpfax_centerfreqfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_runcount_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_signmagen_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_vcorepen_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_VCOREPEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsmout_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsmout_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_count_muxd0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_count_muxd1_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_count_muxd2_attr == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_count_muxd3_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_count_muxd4_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_dlycount_attr == 9'd68
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeasout_clear_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCMEASOUT_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeasout_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeasout_start_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCMEASOUT_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscval_int_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscval_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalintsval_int_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalintsval_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALINTSVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaloffsetfsm_init_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaloffsetfsm_init_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaloffsetfsm_init_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALOFFSETFSM_INIT_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaloffsetfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcaloffsetfsmout_input_en_attr == SERDES_IP_LANE_L1_CFG_RXCALOFFSETFSMOUT_INPUT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_duty_i_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_duty_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_dutycomp_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_foscfsm_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_offsetfsm_init_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_regopampoffset_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_rxppm_lockstatus_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_sqlch_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_sqlchosc_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_synthppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_voscregopampoffset_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_duty_i_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_duty_q_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_dutycomp_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_foscfsm_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_offsetfsm_init_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_rxppm_lockstatus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_sqlch_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_sqlchosc_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_synthppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_voscregopampoffset_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffset_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_finish_side_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_round_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_runcount_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_signmagen_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchfsm_clear_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchfsm_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchfsmout_caldone_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHFSMOUT_CALDONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchfsmout_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_codeoffset_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_finish_side_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHOSCFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_init_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHOSCFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_initval_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_invert_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHOSCFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHOSCFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHOSCFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_round_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHOSCFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_runcount_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHOSCFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscmeas_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHOSCMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscmeas_ref_cnt_attr == 10'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscmeas_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHOSCMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscmeas_settle_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscmeas_smpl_cnt_attr == 10'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvbiascap_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALVBIASCAP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvbiascap_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALVBIASCAP_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvcoopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvcoopampoffsetmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvcoopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvcoopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffset_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffset_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_codeoffset_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_finish_side_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_initval_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_invert_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_lpfaxcoarse_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_round_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_runcount_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETFSM_RUNCOUNT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_signmagen_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsmout_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsmout_runcount_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETFSMOUT_RUNCOUNT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetmeas_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffset_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALVOSCREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALVOSCREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L1_CFG_RXCALVOSCREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALVOSCREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALVOSCREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALVOSCREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALVOSCREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALVOSCREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALVOSCREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrdiv_local_en_attr == SERDES_IP_LANE_L1_CFG_RXCDRDIV_LOCAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdiv_moddiv_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdiv_moddiv_muxd1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdiv_moddiv_muxd2_attr == 4'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdiv_moddiv_muxd3_attr == 4'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdiv_moddiv_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdivslip_mdiv_muxd0_attr == 9'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdivslip_mdiv_muxd1_attr == 9'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdivslip_mdiv_muxd2_attr == 9'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdivslip_mdiv_muxd3_attr == 9'd66
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdivslip_mdiv_muxd4_attr == 9'd210
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrpfd_forcedn_attr == SERDES_IP_LANE_L1_CFG_RXCDRPFD_FORCEDN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrpfd_forceen_attr == SERDES_IP_LANE_L1_CFG_RXCDRPFD_FORCEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrpfd_forceup_attr == SERDES_IP_LANE_L1_CFG_RXCDRPFD_FORCEUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrpfd_propgain_attr == SERDES_IP_LANE_L1_CFG_RXCDRPFD_PROPGAIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrpfd_pulsewidth_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrphd_asym_override_ignore_attr == SERDES_IP_LANE_L1_CFG_RXCDRPHD_ASYM_OVERRIDE_IGNORE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrphd_bitshift_en_attr == SERDES_IP_LANE_L1_CFG_RXCDRPHD_BITSHIFT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrphd_forcedn_attr == SERDES_IP_LANE_L1_CFG_RXCDRPHD_FORCEDN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrphd_forceen_attr == SERDES_IP_LANE_L1_CFG_RXCDRPHD_FORCEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrphd_forceup_attr == SERDES_IP_LANE_L1_CFG_RXCDRPHD_FORCEUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrphdrate_doublerate2s2p_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCDRPHDRATE_DOUBLERATE2S2P_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrphdrate_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCDRPHDRATE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrrefck_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrrefck_refdiv_muxd1_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrrefck_refdiv_muxd2_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrrefck_refdiv_muxd3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrrefck_refdiv_muxd4_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_biastop_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_biastopbypass_attr == SERDES_IP_LANE_L1_CFG_RXCDRVCO_BIASTOPBYPASS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_datapropgain_high_attr == 5'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_datapropgain_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_datapropgain_low_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_ff_ovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_ff_ovr_en_attr == SERDES_IP_LANE_L1_CFG_RXCDRVCO_FF_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_fil_short_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_flickerdegen_attr == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_gmfoscshort_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCDRVCO_GMFOSCSHORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_intf_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_intf_fil_short_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_intrj_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCDRVCO_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_refpropgain_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_refpropgain_nom_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxclk_cdrfb_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCLK_CDRFB_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxclk_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxclk_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdat_nrz_64b80b_bcword_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdata_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXDATA_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdata_locovren_attr == SERDES_IP_LANE_L1_CFG_RXDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdatapath_locovren_attr == SERDES_IP_LANE_L1_CFG_RXDATAPATH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdatapath_on_state_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdatapath_ready_locovr_attr == SERDES_IP_LANE_L1_CFG_RXDATAPATH_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdfe_datatap_vcasc_attr == 4'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdfe_dfebiasadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdfe_nbiasctle_en_attr == SERDES_IP_LANE_L1_CFG_RXDFE_NBIASCTLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdfe_vcasc_sel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdfeterm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXDFETERM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdfeterm_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdfeyadjdac_datamid_edge_coarse_en_attr == SERDES_IP_LANE_L1_CFG_RXDFEYADJDAC_DATAMID_EDGE_COARSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdfeyadjdac_datatopbot_aux_coarse_en_attr == SERDES_IP_LANE_L1_CFG_RXDFEYADJDAC_DATATOPBOT_AUX_COARSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_accum_mon_en_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_ACCUM_MON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_accum_mon_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_bypasscdrpdetupdnsmpl_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_bypassenfosc_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_BYPASSENFOSC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_bypassenints_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_BYPASSENINTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_bypassenupdnsmpl_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_BYPASSENUPDNSMPL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_bypassfosc_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_bypasspllpfdupdnsmpl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_bypassrxints_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_data2pll_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_deltasigmode_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_DELTASIGMODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_fastref_muxd0_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_FASTREF_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_fastref_muxd1_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_FASTREF_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_fastref_muxd2_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_FASTREF_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_fastref_muxd3_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_FASTREF_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_fastref_muxd4_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_FASTREF_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_fosc_mod_bypass_en_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_FOSC_MOD_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_fosc_sample_pedge_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_FOSC_SAMPLE_PEDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gain_step_on_lock_recovery_en_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_GAIN_STEP_ON_LOCK_RECOVERY_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gaindelaycount_init_attr == 9'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gaindelaycount_pow2_muxd0_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gaindelaycount_pow2_muxd1_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gaindelaycount_pow2_muxd2_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gaindelaycount_pow2_muxd3_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gaindelaycount_pow2_muxd4_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2ref_pow2_muxd0_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2ref_pow2_muxd1_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2ref_pow2_muxd2_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2ref_pow2_muxd3_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2ref_pow2_muxd4_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainunlocked_pow2_muxd0_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainunlocked_pow2_muxd1_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainunlocked_pow2_muxd2_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainunlocked_pow2_muxd3_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainunlocked_pow2_muxd4_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_initintegrator_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_INITINTEGRATOR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_initmodulator_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_INITMODULATOR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_deltasig_mode_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_INTS_DELTASIG_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_freeze_en_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_INTS_FREEZE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gaindelaycount_pow2_muxd0_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gaindelaycount_pow2_muxd1_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gaindelaycount_pow2_muxd2_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gaindelaycount_pow2_muxd3_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gaindelaycount_pow2_muxd4_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd0_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd1_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd2_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd3_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd4_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd0_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd1_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd2_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd3_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd4_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainunlocked_pow2_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainunlocked_pow2_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainunlocked_pow2_muxd2_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainunlocked_pow2_muxd3_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainunlocked_pow2_muxd4_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_guardband_hi_attr == 8'd200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_guardband_lo_attr == 8'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_loop_sel_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_INTS_LOOP_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_mod_bypass_en_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_INTS_MOD_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_mod_load_pedge_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_INTS_MOD_LOAD_PEDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_step_to_integer_en_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_INTS_STEP_TO_INTEGER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_jit_length_attr == 18'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_jit_mode_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_JIT_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_modck_ctrl_en_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_MODCK_CTRL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_pll2data_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_restore_cntr_attr == 9'd258
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_store_cntr_attr == 16'd258
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpif_trnsfrdelay_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpiffreeze_inten_attr == SERDES_IP_LANE_L1_CFG_RXDPIFFREEZE_INTEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdpiffreeze_moden_attr == SERDES_IP_LANE_L1_CFG_RXDPIFFREEZE_MODEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxdutyselpolarity_attr == SERDES_IP_LANE_L1_CFG_RXDUTYSELPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxflxgate_force_rxeq_gate_locovr_attr == SERDES_IP_LANE_L1_CFG_RXFLXGATE_FORCE_RXEQ_GATE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxflxgate_locovren_attr == SERDES_IP_LANE_L1_CFG_RXFLXGATE_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxfoscstat_done_locovr_attr == SERDES_IP_LANE_L1_CFG_RXFOSCSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxfoscstat_locovren_attr == SERDES_IP_LANE_L1_CFG_RXFOSCSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxfsm_cken_ovr_attr == SERDES_IP_LANE_L1_CFG_RXFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxfsm_cken_ovren_attr == SERDES_IP_LANE_L1_CFG_RXFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxints_prev_votes_hold_en_attr == SERDES_IP_LANE_L1_CFG_RXINTS_PREV_VOTES_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxlanepam_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXLANEPAM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxlanepam_locovren_attr == SERDES_IP_LANE_L1_CFG_RXLANEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxlock2datatmr_attr == 8'd240
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxlock2datatmr_short_attr == 8'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxntl_changeref_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxntl_changeref_val_locovr_attr == SERDES_IP_LANE_L1_CFG_RXNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxntl_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxntl_en_attr == SERDES_IP_LANE_L1_CFG_RXNTL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxntl_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxntl_locovren_attr == SERDES_IP_LANE_L1_CFG_RXNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxntl_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxntl_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxntl_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxntl_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxntl_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxntl_rxm_charge_up_locovr_attr == SERDES_IP_LANE_L1_CFG_RXNTL_RXM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxntl_rxm_pull_dn_locovr_attr == SERDES_IP_LANE_L1_CFG_RXNTL_RXM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxntl_rxm_sense_locovr_attr == SERDES_IP_LANE_L1_CFG_RXNTL_RXM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxntl_rxp_charge_up_locovr_attr == SERDES_IP_LANE_L1_CFG_RXNTL_RXP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxntl_rxp_pull_dn_locovr_attr == SERDES_IP_LANE_L1_CFG_RXNTL_RXP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxntl_rxp_sense_locovr_attr == SERDES_IP_LANE_L1_CFG_RXNTL_RXP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxntl_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_acc_freeze_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_ACC_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_cdrlock2data_gater_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_cdrlock2data_gater_hold_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_cdrlock2data_gater_ovrd_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_cdrlock2datatmr_optcl_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_cdrlock2datatmr_optcl_sel_ovrd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_enter_lock2data_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_ENTER_LOCK2DATA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_enter_lock2data_hold_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_ENTER_LOCK2DATA_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_exit_lock2data_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_EXIT_LOCK2DATA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_exit_lock2data_hold_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_EXIT_LOCK2DATA_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_force_lock2data_ovrd_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_FORCE_LOCK2DATA_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_force_lock2ref_ovrd_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_FORCE_LOCK2REF_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_hold_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_hold_timer_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_intf_ovrd_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_INTF_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_intf_ovrd_type_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_INTF_OVRD_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_mod_freeze_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_MOD_FREEZE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_ovrd_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_ppm_detect_freeze_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_PPM_DETECT_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_ppm_detect_freeze_ovrd_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_PPM_DETECT_FREEZE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_ppm_detect_hold_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_PPM_DETECT_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_prop_freeze_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_PROP_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_prop_freeze_ovrd_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_PROP_FREEZE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_rxdata_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_RXDATA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_skip_init_lock2data_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_SKIP_INIT_LOCK2DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxpam_bitorder_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxpam_gray_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXPAM_GRAY_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxpam_locovren_attr == SERDES_IP_LANE_L1_CFG_RXPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxpam_precode_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXPAM_PRECODE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_p5_muxd0_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIV_P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_p5_muxd1_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIV_P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_p5_muxd2_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIV_P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_p5_muxd3_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIV_P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_p5_muxd4_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIV_P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdivclken_muxd0_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIVCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdivclken_muxd1_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIVCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdivclken_muxd2_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIVCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdivclken_muxd3_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIVCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdivclken_muxd4_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIVCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxpcsbist_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXPCSBIST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxpcsbist_locovren_attr == SERDES_IP_LANE_L1_CFG_RXPCSBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxphd_gain_hold_en_attr == SERDES_IP_LANE_L1_CFG_RXPHD_GAIN_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxphd_gain_zero_locovr_attr == SERDES_IP_LANE_L1_CFG_RXPHD_GAIN_ZERO_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxphd_locovren_attr == SERDES_IP_LANE_L1_CFG_RXPHD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxphd_majvote_basegain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxphd_majvote_en_attr == SERDES_IP_LANE_L1_CFG_RXPHD_MAJVOTE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxphd_mute_cntr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxphd_nrz8b10b_pam16b20b_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxphd_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxphd_pam_transition_sel_attr == SERDES_IP_LANE_L1_CFG_RXPHD_PAM_TRANSITION_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxphd_sign_invert_attr == SERDES_IP_LANE_L1_CFG_RXPHD_SIGN_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxpostdiv_wait_for_lock_disable_attr == SERDES_IP_LANE_L1_CFG_RXPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxppm_freq_max_offset_h_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxppm_freq_max_offset_l_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxppm_freq_ref_cnt_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxppm_lockstatus_locovr_attr == SERDES_IP_LANE_L1_CFG_RXPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxppm_lockstatus_synthlcfast_en_attr == SERDES_IP_LANE_L1_CFG_RXPPM_LOCKSTATUS_SYNTHLCFAST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxppm_lockstatus_synthlcmed_en_attr == SERDES_IP_LANE_L1_CFG_RXPPM_LOCKSTATUS_SYNTHLCMED_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxppm_lockstatus_synthlcslow_en_attr == SERDES_IP_LANE_L1_CFG_RXPPM_LOCKSTATUS_SYNTHLCSLOW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxppm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxppm_ppmdriftcount_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxppm_ppmdriftmax_attr == 16'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxppm_status_hold_attr == SERDES_IP_LANE_L1_CFG_RXPPM_STATUS_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxppm_unlock_clear_attr == SERDES_IP_LANE_L1_CFG_RXPPM_UNLOCK_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_fast_muxd0_attr == 16'd666
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_fast_muxd1_attr == 16'd4000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_fast_muxd2_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_fast_muxd3_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_fast_muxd4_attr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_muxd0_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_muxd1_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_muxd2_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_muxd3_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_muxd4_attr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxppmctrl_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXPPMCTRL_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxppmctrl_locovren_attr == SERDES_IP_LANE_L1_CFG_RXPPMCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxppmlockstat_locovren_attr == SERDES_IP_LANE_L1_CFG_RXPPMLOCKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxppmlockstat_sticky_locovr_attr == SERDES_IP_LANE_L1_CFG_RXPPMLOCKSTAT_STICKY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxppmtmr_locovren_attr == SERDES_IP_LANE_L1_CFG_RXPPMTMR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxppmtmr_watchdogtmr_sel_locovr_attr == SERDES_IP_LANE_L1_CFG_RXPPMTMR_WATCHDOGTMR_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_cal_clear_delay_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_clk_chk_disable_attr == SERDES_IP_LANE_L1_CFG_RXRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_clk_delay_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_etr_on_delay_attr == 12'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_locovren_attr == SERDES_IP_LANE_L1_CFG_RXRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxreg_lev_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxreg_toggle_reset_on_rate_change_en_attr == SERDES_IP_LANE_L1_CFG_RXREG_TOGGLE_RESET_ON_RATE_CHANGE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxreg_vreg_bypass_attr == SERDES_IP_LANE_L1_CFG_RXREG_VREG_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_en_b_attr == SERDES_IP_LANE_L1_CFG_RXRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s0q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s0q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s2q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s2q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s2q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s2q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s2q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s2q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s2q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s3q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s3q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s3q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s3q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s3q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s3q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s3q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s3q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s4q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s4q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s5q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_entry4_attr == 13'd78
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_entry5_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_entry6_attr == 13'd1406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s0q2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s0q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s1q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s1q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s1q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s1q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s1q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s1q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s2q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s2q2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s2q3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s2q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s2q5_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s2q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s2q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s3q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s3q1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s3q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s3q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s3q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s3q5_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s3q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s3q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s4q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s4q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s5q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_aetrrx_cdrfbdivcken_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_AETRRX_CDRFBDIVCKEN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_aetrrx_cdrfbdivcken_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_AETRRX_CDRFBDIVCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_aetrrx_cdrmoddivcken_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_AETRRX_CDRMODDIVCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_aetrrx_cdrmoddivcken_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_AETRRX_CDRMODDIVCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_aetrrx_termhiz_en_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_AETRRX_TERMHIZ_EN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_aetrrx_termhiz_en_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_AETRRX_TERMHIZ_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_aetrsynth_pcspostdivclksel_ovr_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_AETRSYNTH_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_aetrsynth_pcspostdivclksel_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_AETRSYNTH_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_adc_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_adc_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_auxcomp_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_AUXCOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_auxcomp_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_AUXCOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_bias_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_bias_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_BIAS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_ctlecomp_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_CTLECOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_ctlecomp_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_CTLECOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_datfbdiv_b_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DATFBDIV_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_datfbdiv_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DATFBDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_dfe_bias_b_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DFE_BIAS_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_dfe_bias_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DFE_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_dfe_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DFE_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_dfe_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DFE_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_dfe_yadj_b_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DFE_YADJ_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_dfe_yadj_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DFE_YADJ_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_duty_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DUTY_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_duty_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DUTY_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_hifreqagc_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_HIFREQAGC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_hifreqagc_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_HIFREQAGC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_ntl_b_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_ntl_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_reg_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_reg_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_vco_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_VCO_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_vco_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_VCO_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_voscreg_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_VOSCREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_voscreg_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_VOSCREG_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_adc_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_adc_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_cdrfbdiv_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_CDRFBDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_cdrfbdiv_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_CDRFBDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_pdet_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_PDET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_pdet_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_PDET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_pfd_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_PFD_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_pfd_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_PFD_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_refdiv_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_refdiv_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_reg_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_reg_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_s2pa_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_S2PA_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_s2pa_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_S2PA_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_s2pb_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_S2PB_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_s2pb_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_S2PB_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_vco_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_VCO_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_vco_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_VCO_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_voscreg_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_VOSCREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_voscreg_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_VOSCREG_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstsynth_postdiv_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTSYNTH_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstsynth_postdiv_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTSYNTH_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_drstrx_dpif_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_DRSTRX_DPIF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_drstrx_dpif_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_DRSTRX_DPIF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_drstrx_ppm_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_DRSTRX_PPM_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_drstrx_ppm_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_DRSTRX_PPM_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_cdrlock2data_locovr_attr == SERDES_IP_LANE_L1_CFG_RXSIGDET_CDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_diglfpsdeten_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_diglfpsdeten_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_diglfpsdeten_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_diglfpsdeten_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_diglfpsdeten_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrancnten_muxd0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrancnten_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrancnten_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrancnten_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrancnten_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrancnten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrandeten_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrandeten_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrandeten_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrandeten_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrandeten_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrandeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_eiosdeten_muxd0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_eiosdeten_muxd1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_eiosdeten_muxd2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_eiosdeten_muxd3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_eiosdeten_muxd4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_eiosdeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_enable_attr == SERDES_IP_LANE_L1_CFG_RXSIGDET_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_fastlock_winsize_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_leveldeten_muxd0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_leveldeten_muxd1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_leveldeten_muxd2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_leveldeten_muxd3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_leveldeten_muxd4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_leveldeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_lfpsexit_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_locovren_attr == SERDES_IP_LANE_L1_CFG_RXSIGDET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_ppmdeten_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_ppmdeten_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_ppmdeten_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_ppmdeten_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_ppmdeten_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_ppmdeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_rxeq_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_rxeqen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_rxeqen_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_rxleveldet_debounce_dncount_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_rxleveldet_debounce_flush_en_attr == SERDES_IP_LANE_L1_CFG_RXSIGDET_RXLEVELDET_DEBOUNCE_FLUSH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_rxleveldet_debounce_upcount_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_sigdet_debounce_attr == SERDES_IP_LANE_L1_CFG_RXSIGDET_SIGDET_DEBOUNCE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_tmr_clksel_attr == SERDES_IP_LANE_L1_CFG_RXSIGDET_TMR_CLKSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_toggle_count_en_attr == SERDES_IP_LANE_L1_CFG_RXSIGDET_TOGGLE_COUNT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_toggle_count_pause_attr == SERDES_IP_LANE_L1_CFG_RXSIGDET_TOGGLE_COUNT_PAUSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_toggle_monitor_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdetin_eiosdetectstat_locovr_attr == SERDES_IP_LANE_L1_CFG_RXSIGDETIN_EIOSDETECTSTAT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdetin_locovren_attr == SERDES_IP_LANE_L1_CFG_RXSIGDETIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdetin_ovrcdrlock2data_locovr_attr == SERDES_IP_LANE_L1_CFG_RXSIGDETIN_OVRCDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdetin_ovrencdrlock2data_locovr_attr == SERDES_IP_LANE_L1_CFG_RXSIGDETIN_OVRENCDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdetout_lock2data_noforce_ltr_locovr_attr == SERDES_IP_LANE_L1_CFG_RXSIGDETOUT_LOCK2DATA_NOFORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsigdetout_locovren_attr == SERDES_IP_LANE_L1_CFG_RXSIGDETOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxspare0_attr == 32'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxspare_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsqlchlfps_consec_one_thresh_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsqlchlfps_consec_zero_thresh_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsqlchlfps_cycle_thresh_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsqlchlfps_dat_bitorder_attr == SERDES_IP_LANE_L1_CFG_RXSQLCHLFPS_DAT_BITORDER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsqlchlfps_debounce_type_attr == SERDES_IP_LANE_L1_CFG_RXSQLCHLFPS_DEBOUNCE_TYPE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsqlchlfps_one_run_length_thresh_attr == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsqlchlfps_one_run_length_timeout_attr == 8'd103
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsqlchlfps_zero_run_length_thresh_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsqlchlfps_zero_run_length_timeout_attr == 8'd103
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsynthdiv_slowmed_en_muxd0_attr == SERDES_IP_LANE_L1_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsynthdiv_slowmed_en_muxd1_attr == SERDES_IP_LANE_L1_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsynthdiv_slowmed_en_muxd2_attr == SERDES_IP_LANE_L1_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsynthdiv_slowmed_en_muxd3_attr == SERDES_IP_LANE_L1_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxsynthdiv_slowmed_en_muxd4_attr == SERDES_IP_LANE_L1_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxterm_cal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxterm_coarse_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxterm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXTERM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxterm_modeselect_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxtermhiz_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXTERMHIZ_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxtermhiz_locovren_attr == SERDES_IP_LANE_L1_CFG_RXTERMHIZ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxvoscreg_bypass_vosc_attr == SERDES_IP_LANE_L1_CFG_RXVOSCREG_BYPASS_VOSC_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxvoscregopampoffsetctrl_sel_attr == SERDES_IP_LANE_L1_CFG_RXVOSCREGOPAMPOFFSETCTRL_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxvoscregopampoffseterr_locovren_attr == SERDES_IP_LANE_L1_CFG_RXVOSCREGOPAMPOFFSETERR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxvoscregopampoffseterr_sel_locovr_attr == SERDES_IP_LANE_L1_CFG_RXVOSCREGOPAMPOFFSETERR_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxvoscregvref_locovren_attr == SERDES_IP_LANE_L1_CFG_RXVOSCREGVREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_rxvoscregvref_sel_locovr_attr == SERDES_IP_LANE_L1_CFG_RXVOSCREGVREF_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlch_acqgain_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlch_acqtime_attr == 13'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlch_cal_quiet_locovr_attr == SERDES_IP_LANE_L1_CFG_SQLCH_CAL_QUIET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlch_cal_sel_locovr_attr == SERDES_IP_LANE_L1_CFG_SQLCH_CAL_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlch_calctrl_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlch_calen_locovr_attr == SERDES_IP_LANE_L1_CFG_SQLCH_CALEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlch_caltimer_attr == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlch_clkgate_locovr_attr == SERDES_IP_LANE_L1_CFG_SQLCH_CLKGATE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlch_cmshiften_attr == SERDES_IP_LANE_L1_CFG_SQLCH_CMSHIFTEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_acq_gain_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_acq_pct_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_cal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_clr_errlog_attr == SERDES_IP_LANE_L1_CFG_SQLCH_CONT_CLR_ERRLOG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_controller_mode_attr == SERDES_IP_LANE_L1_CFG_SQLCH_CONT_CONTROLLER_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_dis_attr == SERDES_IP_LANE_L1_CFG_SQLCH_CONT_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_pause_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_postcal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_precal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_quiet_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlch_lfps_en_attr == SERDES_IP_LANE_L1_CFG_SQLCH_LFPS_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlch_locovren_attr == SERDES_IP_LANE_L1_CFG_SQLCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlch_ovrd_val_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlch_pkdet_freqsel_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlch_polarity_attr == SERDES_IP_LANE_L1_CFG_SQLCH_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlch_rdacen_attr == SERDES_IP_LANE_L1_CFG_SQLCH_RDACEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlch_thresh_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlch_time_out_attr == 16'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlch_vrefsel0_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlch_vrefsel1_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlch_vrefsel_ovr_en_attr == SERDES_IP_LANE_L1_CFG_SQLCH_VREFSEL_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlchdeb_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlchdeb_deb_cnt_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlchdeb_deb_status_cnt_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlchdeb_en_attr == SERDES_IP_LANE_L1_CFG_SQLCHDEB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlchdeb_ign_cnt_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlchdeb_sigdet_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlchdeb_thresh_cnt_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlchdebout_exit_good_debounced_locovr_attr == SERDES_IP_LANE_L1_CFG_SQLCHDEBOUT_EXIT_GOOD_DEBOUNCED_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlchdebout_exit_good_debounced_status_locovr_attr == SERDES_IP_LANE_L1_CFG_SQLCHDEBOUT_EXIT_GOOD_DEBOUNCED_STATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlchdebout_exit_good_locovr_attr == SERDES_IP_LANE_L1_CFG_SQLCHDEBOUT_EXIT_GOOD_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_sqlchdebout_locovren_attr == SERDES_IP_LANE_L1_CFG_SQLCHDEBOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_trancnt_off_attr == 10'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_trancnt_on_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_trancntout_det_locovr_attr == SERDES_IP_LANE_L1_CFG_TRANCNTOUT_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_trancntout_locovren_attr == SERDES_IP_LANE_L1_CFG_TRANCNTOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_trandet_ax_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_trandet_ay_attr == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_trandet_off_h_attr == 6'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_trandet_off_l_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_trandet_on_h_attr == 6'd39
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_trandet_on_l_attr == 6'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_trandetout_det_locovr_attr == SERDES_IP_LANE_L1_CFG_TRANDETOUT_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_trandetout_locovren_attr == SERDES_IP_LANE_L1_CFG_TRANDETOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_tx2rxlb_en_attr == SERDES_IP_LANE_L1_CFG_TX2RXLB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_tx2rxlb_init_offset_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_tx_cmn_on_state_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_tx_fastregpwrup_en_attr == SERDES_IP_LANE_L1_CFG_TX_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_tx_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_tx_pg_disable_attr == SERDES_IP_LANE_L1_CFG_TX_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_tx_synth_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_tx_synth_sel_amode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_tx_synth_sel_bmode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_tx_synth_sel_cmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_tx_synth_sel_dmode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_tx_synth_sel_emode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_tx_txdetrx_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txadc_req_attr == SERDES_IP_LANE_L1_CFG_TXADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txaprobe_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txaprobe_lastmux_isolate_attr == SERDES_IP_LANE_L1_CFG_TXAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txaprobeadc_current_direction_attr == SERDES_IP_LANE_L1_CFG_TXAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txaprobeadc_resistor_enable_attr == SERDES_IP_LANE_L1_CFG_TXAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txbdvdr_pma2pcstxworden_attr == SERDES_IP_LANE_L1_CFG_TXBDVDR_PMA2PCSTXWORDEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txbeacon_div_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txbeacon_sel_attr == SERDES_IP_LANE_L1_CFG_TXBEACON_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txbias_icc20uadj_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txbias_icc80uadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txbias_locovren_attr == SERDES_IP_LANE_L1_CFG_TXBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txbias_termcal_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txbist_biterror_en_attr == SERDES_IP_LANE_L1_CFG_TXBIST_BITERROR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txbist_locovren_attr == SERDES_IP_LANE_L1_CFG_TXBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txbist_modesel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txbist_oobmode_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txbist_oobtburst_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txbist_oobtcomrstinit_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txbist_oobtcomsas_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txbist_oobtcomwake_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txbist_seed_attr == 31'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_size_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf00_attr == 32'd1985229328
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf01_attr == 32'd4275878552
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf02_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf03_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf04_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf05_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf06_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf07_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf08_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf09_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txbit_select_muxd0_attr == SERDES_IP_LANE_L1_CFG_TXBIT_SELECT_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txbit_select_muxd1_attr == SERDES_IP_LANE_L1_CFG_TXBIT_SELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txbit_select_muxd2_attr == SERDES_IP_LANE_L1_CFG_TXBIT_SELECT_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txbit_select_muxd3_attr == SERDES_IP_LANE_L1_CFG_TXBIT_SELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txbit_select_muxd4_attr == SERDES_IP_LANE_L1_CFG_TXBIT_SELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txbti_data_replication_attr == SERDES_IP_LANE_L1_CFG_TXBTI_DATA_REPLICATION_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txbti_tx_idle_data_en_attr == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcal_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcal_tclkduty_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalduty_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalduty_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTY_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalduty_sel_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutybg_abort_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutybg_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutybg_ready_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutycomp_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutycomp_offset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_finish_side_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_init_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_initval_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_invert_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_req_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_round_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_runcount_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_signmagen_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsmout_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsmout_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompmeas_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompmeas_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompmeas_req_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompmeasout_ack_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPMEASOUT_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompmeasout_erravg_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPMEASOUT_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompmeasout_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_bg_en_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_bg_one_step_cal_en_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_finish_side_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_init_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_invert_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_req_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_round_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_runcount_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_signmagen_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeas_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeas_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeas_req_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeasout_ack_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYMEASOUT_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeasout_erravg_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYMEASOUT_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeasout_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutystat_done_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaldutystat_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalptr_pstate_duty_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalptr_pstate_dutycomp_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalptr_pstate_regopampoffset_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_duty_muxd0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_duty_muxd1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_duty_muxd2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_duty_muxd3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_duty_muxd4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_dutycomp_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_dutycomp_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_dutycomp_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_dutycomp_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_dutycomp_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_regopampoffset_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffset_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_finish_side_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_round_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_runcount_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_signmagen_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcaltclkdutyforce_div1_attr == SERDES_IP_LANE_L1_CFG_TXCALTCLKDUTYFORCE_DIV1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txcdrdiv_local_en_attr == SERDES_IP_LANE_L1_CFG_TXCDRDIV_LOCAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txclk_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txclk_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txclkgenmuxsel_txinternal_attr == SERDES_IP_LANE_L1_CFG_TXCLKGENMUXSEL_TXINTERNAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txdetectrx_thr_attr == 5'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeas_count_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeas_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXDETECTRXMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeas_locovren_attr == SERDES_IP_LANE_L1_CFG_TXDETECTRXMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeas_validdlycount_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeasin_locovren_attr == SERDES_IP_LANE_L1_CFG_TXDETECTRXMEASIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeasin_start_locovr_attr == SERDES_IP_LANE_L1_CFG_TXDETECTRXMEASIN_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeaspcs_locovren_attr == SERDES_IP_LANE_L1_CFG_TXDETECTRXMEASPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeaspcs_req_locovr_attr == SERDES_IP_LANE_L1_CFG_TXDETECTRXMEASPCS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeasval_locovren_attr == SERDES_IP_LANE_L1_CFG_TXDETECTRXMEASVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeasval_stat_locovr_attr == SERDES_IP_LANE_L1_CFG_TXDETECTRXMEASVAL_STAT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txdetrx_levn_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txdetrx_levnm1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txdetrx_levnp1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txdetrx_levnp2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txdrv_hizen_locovr_attr == SERDES_IP_LANE_L1_CFG_TXDRV_HIZEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txdrv_levn_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txdrv_levnm1_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txdrv_levnp1_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txdrv_levnp2_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txdrv_locovren_attr == SERDES_IP_LANE_L1_CFG_TXDRV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txdrv_refcken_attr == SERDES_IP_LANE_L1_CFG_TXDRV_REFCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txdrv_termref_attr == SERDES_IP_LANE_L1_CFG_TXDRV_TERMREF_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txdrvmute_locovr_attr == SERDES_IP_LANE_L1_CFG_TXDRVMUTE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txdrvmute_locovren_attr == SERDES_IP_LANE_L1_CFG_TXDRVMUTE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txduty_ctrl_disable_attr == SERDES_IP_LANE_L1_CFG_TXDUTY_CTRL_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txduty_pad_sense_en_attr == SERDES_IP_LANE_L1_CFG_TXDUTY_PAD_SENSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txdutycal_div16_en_attr == SERDES_IP_LANE_L1_CFG_TXDUTYCAL_DIV16_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txdutycal_div1_en_attr == SERDES_IP_LANE_L1_CFG_TXDUTYCAL_DIV1_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txdutycal_div2_en_attr == SERDES_IP_LANE_L1_CFG_TXDUTYCAL_DIV2_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txdutycal_div4_en_attr == SERDES_IP_LANE_L1_CFG_TXDUTYCAL_DIV4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txdutycal_div8_en_attr == SERDES_IP_LANE_L1_CFG_TXDUTYCAL_DIV8_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txfifo_elecidle_deskew_en_attr == SERDES_IP_LANE_L1_CFG_TXFIFO_ELECIDLE_DESKEW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txfifo_force_txidlebit1_zero_disable_attr == SERDES_IP_LANE_L1_CFG_TXFIFO_FORCE_TXIDLEBIT1_ZERO_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txfifo_kill_dly_10b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txfifo_kill_dly_16b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txfifo_kill_dly_20b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txfifo_kill_dly_32b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txfifo_kill_dly_40b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txfifo_kill_dly_64b_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txfifo_kill_dly_80b_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txfifo_kill_dly_8b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txfifo_kill_en_attr == SERDES_IP_LANE_L1_CFG_TXFIFO_KILL_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txfsm_cken_ovr_attr == SERDES_IP_LANE_L1_CFG_TXFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txfsm_cken_ovren_attr == SERDES_IP_LANE_L1_CFG_TXFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txfsm_main_on_state_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txl1d1_doze_ctrl_attr == SERDES_IP_LANE_L1_CFG_TXL1D1_DOZE_CTRL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txl1d1_txbias_ctrl_attr == SERDES_IP_LANE_L1_CFG_TXL1D1_TXBIAS_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txlanepam_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXLANEPAM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txlanepam_locovren_attr == SERDES_IP_LANE_L1_CFG_TXLANEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txmeaslatovrhd_meas_sel_attr == SERDES_IP_LANE_L1_CFG_TXMEASLATOVRHD_MEAS_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txmute_delay_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txntl_changeref_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txntl_changeref_val_locovr_attr == SERDES_IP_LANE_L1_CFG_TXNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txntl_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txntl_en_attr == SERDES_IP_LANE_L1_CFG_TXNTL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txntl_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txntl_locovren_attr == SERDES_IP_LANE_L1_CFG_TXNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txntl_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txntl_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txntl_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txntl_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txntl_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txntl_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txntl_txm_charge_up_locovr_attr == SERDES_IP_LANE_L1_CFG_TXNTL_TXM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txntl_txm_pull_dn_locovr_attr == SERDES_IP_LANE_L1_CFG_TXNTL_TXM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txntl_txm_sense_locovr_attr == SERDES_IP_LANE_L1_CFG_TXNTL_TXM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txntl_txp_charge_up_locovr_attr == SERDES_IP_LANE_L1_CFG_TXNTL_TXP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txntl_txp_pull_dn_locovr_attr == SERDES_IP_LANE_L1_CFG_TXNTL_TXP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txntl_txp_sense_locovr_attr == SERDES_IP_LANE_L1_CFG_TXNTL_TXP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txp2s_txwordsyncbypen_attr == SERDES_IP_LANE_L1_CFG_TXP2S_TXWORDSYNCBYPEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txpam_bitorder_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txpam_gray_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXPAM_GRAY_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txpam_locovren_attr == SERDES_IP_LANE_L1_CFG_TXPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txpam_precode_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXPAM_PRECODE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txpcs_locovren_attr == SERDES_IP_LANE_L1_CFG_TXPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txpcs_txenable_locovr_attr == SERDES_IP_LANE_L1_CFG_TXPCS_TXENABLE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txpcsbist_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXPCSBIST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txpcsbist_locovren_attr == SERDES_IP_LANE_L1_CFG_TXPCSBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txratewidth_clk_chk_disable_attr == SERDES_IP_LANE_L1_CFG_TXRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txratewidth_etr_on_delay_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txratewidth_locovren_attr == SERDES_IP_LANE_L1_CFG_TXRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txreg_toggle_pwrupacc_on_rate_change_en_attr == SERDES_IP_LANE_L1_CFG_TXREG_TOGGLE_PWRUPACC_ON_RATE_CHANGE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txreg_toggle_reset_on_rate_change_en_attr == SERDES_IP_LANE_L1_CFG_TXREG_TOGGLE_RESET_ON_RATE_CHANGE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txresetdel_sel_attr == SERDES_IP_LANE_L1_CFG_TXRESETDEL_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_en_b_attr == SERDES_IP_LANE_L1_CFG_TXRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s0q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s0q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s1q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s1q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s2q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s2q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s2q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s2q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s2q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s2q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s2q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s3q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s3q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s3q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s3q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s3q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s3q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s3q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s3q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s4q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s4q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s5q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s0q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s0q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s1q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s1q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s1q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s1q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s1q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s1q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s2q0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s2q1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s2q2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s2q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s2q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s2q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s2q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s2q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s3q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s3q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s3q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s3q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s3q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s3q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s3q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s3q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s4q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s4q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s5q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_dn_ptr0_s_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_up_ptr0_s_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_aetrtx_bitckdvdrcken_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_AETRTX_BITCKDVDRCKEN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_aetrtx_bitckdvdrcken_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_AETRTX_BITCKDVDRCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_aetrtx_regpwrupacc_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_AETRTX_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_aetrtx_regpwrupacc_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_AETRTX_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_adc_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_adc_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_drvdoze_b_ovr_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_DRVDOZE_B_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_drvdoze_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_DRVDOZE_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_duty_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_DUTY_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_duty_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_DUTY_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_ntl_b_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_ntl_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_p2s_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_P2S_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_p2s_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_P2S_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_reg_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_reg_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_arsttx_adc_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_ARSTTX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_arsttx_adc_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_ARSTTX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_arsttx_pma2pcstxword_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_ARSTTX_PMA2PCSTXWORD_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_arsttx_pma2pcstxword_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_ARSTTX_PMA2PCSTXWORD_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_arsttx_regreset_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_ARSTTX_REGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_arsttx_regreset_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_ARSTTX_REGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_arsttx_txdetectrx_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_ARSTTX_TXDETECTRX_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_arsttx_txdetectrx_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_ARSTTX_TXDETECTRX_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txrststate_hiz_en_attr == SERDES_IP_LANE_L1_CFG_TXRSTSTATE_HIZ_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txspare0_attr == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txspare_attr == 10'd384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txterm_coarse_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txtermtrim_locovren_attr == SERDES_IP_LANE_L1_CFG_TXTERMTRIM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txtermtrim_nmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txtermtrim_pmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txwclk_div_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txwclk_div_en_attr == SERDES_IP_LANE_L1_CFG_TXWCLK_DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txwclk_div_smpl_attr == SERDES_IP_LANE_L1_CFG_TXWCLK_DIV_SMPL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txwptr_init01_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txwptr_init02_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txwptr_init04_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txwptr_init08_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txwptr_init16_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txwptr_init32_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l1_cfg_txwptr_init_rx2txparlb_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_bshihyst_attr == SERDES_IP_LANE_L2_CFG_BSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_bstxdrv_levn_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_bstxdrv_levnm1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_bstxdrv_levnp1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_bstxdrv_levnp2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_calsqlchosc_locovren_attr == SERDES_IP_LANE_L2_CFG_CALSQLCHOSC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_calsqlchosc_trimcode_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_cdrclkstat_locovren_attr == SERDES_IP_LANE_L2_CFG_CDRCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_cdrclkstat_ready_locovr_attr == SERDES_IP_LANE_L2_CFG_CDRCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_etrregrxcdrclk_ready_attr == SERDES_IP_LANE_L2_CFG_ETRREGRXCDRCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_laneckm_avg_en_attr == SERDES_IP_LANE_L2_CFG_LANECKM_AVG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_laneckm_clk_en_attr == SERDES_IP_LANE_L2_CFG_LANECKM_CLK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_laneckm_continuous_attr == SERDES_IP_LANE_L2_CFG_LANECKM_CONTINUOUS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_laneckm_dig_meas_en_attr == SERDES_IP_LANE_L2_CFG_LANECKM_DIG_MEAS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_laneckm_dig_meas_err_clr_attr == SERDES_IP_LANE_L2_CFG_LANECKM_DIG_MEAS_ERR_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_laneckm_en_attr == SERDES_IP_LANE_L2_CFG_LANECKM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_laneckm_max_thr_attr == 25'd33554431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_laneckm_meas_ck_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_laneckm_ref_ck_div_ratio_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_laneckm_result_clr_attr == SERDES_IP_LANE_L2_CFG_LANECKM_RESULT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_laneckm_start_attr == SERDES_IP_LANE_L2_CFG_LANECKM_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_laneckm_wdt_interval_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_laneckm_win_thr_ref_attr == 25'd16777215
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_lanepcs_locovren_attr == SERDES_IP_LANE_L2_CFG_LANEPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_lanepcs_mode_locovr_attr == SERDES_IP_LANE_L2_CFG_LANEPCS_MODE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_laneperfmon_compare_val_start_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_laneperfmon_compare_val_stop_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_laneperfmon_en_attr == SERDES_IP_LANE_L2_CFG_LANEPERFMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_laneperfmon_mask_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_lanepmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_lanepmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_lanepmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_lanepmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_lanepmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_lanepmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_lb_cdrclk2txen_locovr_attr == SERDES_IP_LANE_L2_CFG_LB_CDRCLK2TXEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_lb_cdrclkdiven_attr == SERDES_IP_LANE_L2_CFG_LB_CDRCLKDIVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_lb_cdrdivclk2exten_attr == SERDES_IP_LANE_L2_CFG_LB_CDRDIVCLK2EXTEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_lb_cdrdivclk2txen_attr == SERDES_IP_LANE_L2_CFG_LB_CDRDIVCLK2TXEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_lb_hsclk2cdrdiven_attr == SERDES_IP_LANE_L2_CFG_LB_HSCLK2CDRDIVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_lb_locovren_attr == SERDES_IP_LANE_L2_CFG_LB_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_lb_parrx2txtimeden_locovr_attr == SERDES_IP_LANE_L2_CFG_LB_PARRX2TXTIMEDEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_lb_pllfbclk2cdrrefclken_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_lb_pllfbclk2cdrrefclken_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_lb_pllfbclk2cdrrefclken_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_lb_pllfbclk2cdrrefclken_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_lb_pllfbclk2cdrrefclken_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_lb_rx2txuntimeden_attr == SERDES_IP_LANE_L2_CFG_LB_RX2TXUNTIMEDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_lb_rxwordck2pcstxwordcken_attr == SERDES_IP_LANE_L2_CFG_LB_RXWORDCK2PCSTXWORDCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_lb_tx2rxbuftimeden_lsb_locovr_attr == SERDES_IP_LANE_L2_CFG_LB_TX2RXBUFTIMEDEN_LSB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_lb_tx2rxbuftimeden_msb_locovr_attr == SERDES_IP_LANE_L2_CFG_LB_TX2RXBUFTIMEDEN_MSB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_lb_tx2rxiotimeden_attr == SERDES_IP_LANE_L2_CFG_LB_TX2RXIOTIMEDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_lfps_det_locovr_attr == SERDES_IP_LANE_L2_CFG_LFPS_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_lfps_locovren_attr == SERDES_IP_LANE_L2_CFG_LFPS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_lfps_out_en_attr == SERDES_IP_LANE_L2_CFG_LFPS_OUT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_pcslfps_en_locovr_attr == SERDES_IP_LANE_L2_CFG_PCSLFPS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_pcslfps_locovren_attr == SERDES_IP_LANE_L2_CFG_PCSLFPS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_pcsrx_dme_en_locovr_attr == SERDES_IP_LANE_L2_CFG_PCSRX_DME_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_pcsrx_locovren_attr == SERDES_IP_LANE_L2_CFG_PCSRX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_pcsrxbist_locovren_attr == SERDES_IP_LANE_L2_CFG_PCSRXBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_pcsrxbist_modesel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_pcstx_beaconen_locovr_attr == SERDES_IP_LANE_L2_CFG_PCSTX_BEACONEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_pcstx_locovren_attr == SERDES_IP_LANE_L2_CFG_PCSTX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_polarity_rx_attr == SERDES_IP_LANE_L2_CFG_POLARITY_RX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_polarity_tx_attr == SERDES_IP_LANE_L2_CFG_POLARITY_TX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rx_cmn_on_state_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rx_fastregpwrup_en_attr == SERDES_IP_LANE_L2_CFG_RX_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rx_frac_mode_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rx_on_state_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rx_pg_disable_attr == SERDES_IP_LANE_L2_CFG_RX_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rx_synth_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rx_synth_sel_amode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rx_synth_sel_bmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rx_synth_sel_cmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rx_synth_sel_dmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rx_synth_sel_emode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxadc_req_attr == SERDES_IP_LANE_L2_CFG_RXADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxagc_dccoupleen_attr == SERDES_IP_LANE_L2_CFG_RXAGC_DCCOUPLEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxaprobe_addr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxaprobe_lastmux_isolate_attr == SERDES_IP_LANE_L2_CFG_RXAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxaprobeadc_current_direction_attr == SERDES_IP_LANE_L2_CFG_RXAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxaprobeadc_resistor_enable_attr == SERDES_IP_LANE_L2_CFG_RXAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxbias_iccadj_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxbias_icvadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxbias_locovren_attr == SERDES_IP_LANE_L2_CFG_RXBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxbias_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxbist_burst_four_errtype_attr == SERDES_IP_LANE_L2_CFG_RXBIST_BURST_FOUR_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxbist_burst_one_errtype_attr == SERDES_IP_LANE_L2_CFG_RXBIST_BURST_ONE_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxbist_burst_three_errtype_attr == SERDES_IP_LANE_L2_CFG_RXBIST_BURST_THREE_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxbist_burst_two_errtype_attr == SERDES_IP_LANE_L2_CFG_RXBIST_BURST_TWO_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxbist_cdrlock2data_bypass_attr == SERDES_IP_LANE_L2_CFG_RXBIST_CDRLOCK2DATA_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxbist_cdrlock2data_postamble_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxbist_clear_errcount_attr == SERDES_IP_LANE_L2_CFG_RXBIST_CLEAR_ERRCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxbist_err_en_attr == SERDES_IP_LANE_L2_CFG_RXBIST_ERR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxbist_err_trig_type_attr == SERDES_IP_LANE_L2_CFG_RXBIST_ERR_TRIG_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxbist_errmask_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxbist_errtype_attr == SERDES_IP_LANE_L2_CFG_RXBIST_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxbist_firsterr_type_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxbist_lockchk_count_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxbist_maxbitcnt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxbist_mostrecent_err_attr == SERDES_IP_LANE_L2_CFG_RXBIST_MOSTRECENT_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxbist_relock_itercount_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxbist_seed_attr == 31'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxbist_status_hold_attr == SERDES_IP_LANE_L2_CFG_RXBIST_STATUS_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxbitslip_locovr_attr == SERDES_IP_LANE_L2_CFG_RXBITSLIP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxbitslip_locovren_attr == SERDES_IP_LANE_L2_CFG_RXBITSLIP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxbscan_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxbshicm_attr == SERDES_IP_LANE_L2_CFG_RXBSHICM_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalcdrfbdiv_div2_bypass_muxd0_attr == SERDES_IP_LANE_L2_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalcdrfbdiv_div2_bypass_muxd1_attr == SERDES_IP_LANE_L2_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalcdrfbdiv_div2_bypass_muxd2_attr == SERDES_IP_LANE_L2_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalcdrfbdiv_div2_bypass_muxd3_attr == SERDES_IP_LANE_L2_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalcdrfbdiv_div2_bypass_muxd4_attr == SERDES_IP_LANE_L2_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalduty_iclk_gray_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalduty_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTY_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalduty_qclk_gray_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalduty_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutybg_abort_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutybg_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutybg_ready_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycomp_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycomp_offset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_finish_side_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_init_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_initval_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_invert_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_round_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_runcount_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_signmagen_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsmout_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsmout_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_disable_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCTRL_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_i_div1_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_i_div2_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_i_div4_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_i_div8_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_q_div1_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_q_div2_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_q_div4_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_q_div8_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_bg_en_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_bg_one_step_cal_en_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_finish_side_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_i_polarity_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_I_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_i_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_I_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_init_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_q_polarity_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_Q_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_q_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_Q_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_round_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_runcount_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_signmagen_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_comp_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEAS_COMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_comp_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEAS_COMP_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_i_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEAS_I_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_i_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEAS_I_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_q_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEAS_Q_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_q_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEAS_Q_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeasout_comp_ack_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEASOUT_COMP_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeasout_comp_erravg_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEASOUT_COMP_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeasout_i_ack_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEASOUT_I_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeasout_i_erravg_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEASOUT_I_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeasout_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeasout_q_ack_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEASOUT_Q_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeasout_q_erravg_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEASOUT_Q_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutystat_done_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaldutystat_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_centerfreq_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_end_delay_attr == 9'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_hscount_muxd0_attr == 8'd181
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_hscount_muxd1_attr == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_hscount_muxd2_attr == 8'd180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_hscount_muxd3_attr == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_hscount_muxd4_attr == 8'd206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_initval_centerfreq_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_initval_fosc_attr == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_centerfreq_finish_side_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_CENTERFREQ_FINISH_SIDE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_centerfreq_to_fosc_offset_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_centerfreqen_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_CENTERFREQEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_centerfreqoffset_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_fosc_finishside_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_FOSC_FINISHSIDE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_foscen_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_FOSCEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_foscoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_init_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_invert_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_lpfax_calfosccoarse_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_lpfax_calfoscfine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_lpfax_centerfreqcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_lpfax_centerfreqfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_runcount_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_signmagen_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_vcorepen_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_VCOREPEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsmout_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsmout_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_count_muxd0_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_count_muxd1_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_count_muxd2_attr == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_count_muxd3_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_count_muxd4_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_dlycount_attr == 9'd68
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeasout_clear_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCMEASOUT_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeasout_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeasout_start_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCMEASOUT_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscval_int_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscval_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalintsval_int_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalintsval_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALINTSVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaloffsetfsm_init_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaloffsetfsm_init_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaloffsetfsm_init_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALOFFSETFSM_INIT_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaloffsetfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcaloffsetfsmout_input_en_attr == SERDES_IP_LANE_L2_CFG_RXCALOFFSETFSMOUT_INPUT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_duty_i_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_duty_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_dutycomp_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_foscfsm_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_offsetfsm_init_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_regopampoffset_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_rxppm_lockstatus_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_sqlch_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_sqlchosc_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_synthppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_voscregopampoffset_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_duty_i_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_duty_q_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_dutycomp_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_foscfsm_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_offsetfsm_init_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_rxppm_lockstatus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_sqlch_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_sqlchosc_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_synthppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_voscregopampoffset_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffset_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_finish_side_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_round_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_runcount_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_signmagen_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchfsm_clear_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchfsm_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchfsmout_caldone_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHFSMOUT_CALDONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchfsmout_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_codeoffset_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_finish_side_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHOSCFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_init_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHOSCFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_initval_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_invert_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHOSCFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHOSCFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHOSCFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_round_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHOSCFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_runcount_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHOSCFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscmeas_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHOSCMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscmeas_ref_cnt_attr == 10'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscmeas_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHOSCMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscmeas_settle_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscmeas_smpl_cnt_attr == 10'd144
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvbiascap_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALVBIASCAP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvbiascap_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALVBIASCAP_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvcoopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvcoopampoffsetmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvcoopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvcoopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffset_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffset_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_codeoffset_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_finish_side_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_initval_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_invert_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_lpfaxcoarse_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_round_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_runcount_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETFSM_RUNCOUNT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_signmagen_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsmout_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsmout_runcount_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETFSMOUT_RUNCOUNT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetmeas_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffset_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALVOSCREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALVOSCREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L2_CFG_RXCALVOSCREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALVOSCREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALVOSCREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALVOSCREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALVOSCREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALVOSCREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALVOSCREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrdiv_local_en_attr == SERDES_IP_LANE_L2_CFG_RXCDRDIV_LOCAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdiv_moddiv_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdiv_moddiv_muxd1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdiv_moddiv_muxd2_attr == 4'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdiv_moddiv_muxd3_attr == 4'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdiv_moddiv_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdivslip_mdiv_muxd0_attr == 9'd194
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdivslip_mdiv_muxd1_attr == 9'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdivslip_mdiv_muxd2_attr == 9'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdivslip_mdiv_muxd3_attr == 9'd66
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdivslip_mdiv_muxd4_attr == 9'd210
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrpfd_forcedn_attr == SERDES_IP_LANE_L2_CFG_RXCDRPFD_FORCEDN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrpfd_forceen_attr == SERDES_IP_LANE_L2_CFG_RXCDRPFD_FORCEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrpfd_forceup_attr == SERDES_IP_LANE_L2_CFG_RXCDRPFD_FORCEUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrpfd_propgain_attr == SERDES_IP_LANE_L2_CFG_RXCDRPFD_PROPGAIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrpfd_pulsewidth_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrphd_asym_override_ignore_attr == SERDES_IP_LANE_L2_CFG_RXCDRPHD_ASYM_OVERRIDE_IGNORE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrphd_bitshift_en_attr == SERDES_IP_LANE_L2_CFG_RXCDRPHD_BITSHIFT_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrphd_forcedn_attr == SERDES_IP_LANE_L2_CFG_RXCDRPHD_FORCEDN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrphd_forceen_attr == SERDES_IP_LANE_L2_CFG_RXCDRPHD_FORCEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrphd_forceup_attr == SERDES_IP_LANE_L2_CFG_RXCDRPHD_FORCEUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrphdrate_doublerate2s2p_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCDRPHDRATE_DOUBLERATE2S2P_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrphdrate_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCDRPHDRATE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrrefck_refdiv_muxd0_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrrefck_refdiv_muxd1_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrrefck_refdiv_muxd2_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrrefck_refdiv_muxd3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrrefck_refdiv_muxd4_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_biastop_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_biastopbypass_attr == SERDES_IP_LANE_L2_CFG_RXCDRVCO_BIASTOPBYPASS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_datapropgain_high_attr == 5'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_datapropgain_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_datapropgain_low_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_ff_ovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_ff_ovr_en_attr == SERDES_IP_LANE_L2_CFG_RXCDRVCO_FF_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_fil_short_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_flickerdegen_attr == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_gmfoscshort_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCDRVCO_GMFOSCSHORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_intf_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_intf_fil_short_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_intrj_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCDRVCO_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_refpropgain_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_refpropgain_nom_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxclk_cdrfb_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCLK_CDRFB_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxclk_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxclk_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdat_nrz_64b80b_bcword_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdata_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXDATA_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdata_locovren_attr == SERDES_IP_LANE_L2_CFG_RXDATA_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdatapath_locovren_attr == SERDES_IP_LANE_L2_CFG_RXDATAPATH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdatapath_on_state_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdatapath_ready_locovr_attr == SERDES_IP_LANE_L2_CFG_RXDATAPATH_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdfe_datatap_vcasc_attr == 4'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdfe_dfebiasadj_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdfe_nbiasctle_en_attr == SERDES_IP_LANE_L2_CFG_RXDFE_NBIASCTLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdfe_vcasc_sel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdfeterm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXDFETERM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdfeterm_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdfeyadjdac_datamid_edge_coarse_en_attr == SERDES_IP_LANE_L2_CFG_RXDFEYADJDAC_DATAMID_EDGE_COARSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdfeyadjdac_datatopbot_aux_coarse_en_attr == SERDES_IP_LANE_L2_CFG_RXDFEYADJDAC_DATATOPBOT_AUX_COARSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_accum_mon_en_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_ACCUM_MON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_accum_mon_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_bypasscdrpdetupdnsmpl_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_bypassenfosc_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_BYPASSENFOSC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_bypassenints_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_BYPASSENINTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_bypassenupdnsmpl_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_BYPASSENUPDNSMPL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_bypassfosc_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_bypasspllpfdupdnsmpl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_bypassrxints_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_data2pll_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_deltasigmode_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_DELTASIGMODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_fastref_muxd0_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_FASTREF_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_fastref_muxd1_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_FASTREF_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_fastref_muxd2_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_FASTREF_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_fastref_muxd3_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_FASTREF_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_fastref_muxd4_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_FASTREF_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_fosc_mod_bypass_en_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_FOSC_MOD_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_fosc_sample_pedge_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_FOSC_SAMPLE_PEDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gain_step_on_lock_recovery_en_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_GAIN_STEP_ON_LOCK_RECOVERY_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gaindelaycount_init_attr == 9'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gaindelaycount_pow2_muxd0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gaindelaycount_pow2_muxd1_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gaindelaycount_pow2_muxd2_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gaindelaycount_pow2_muxd3_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gaindelaycount_pow2_muxd4_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2ref_pow2_muxd0_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2ref_pow2_muxd1_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2ref_pow2_muxd2_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2ref_pow2_muxd3_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2ref_pow2_muxd4_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainunlocked_pow2_muxd0_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainunlocked_pow2_muxd1_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainunlocked_pow2_muxd2_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainunlocked_pow2_muxd3_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainunlocked_pow2_muxd4_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_initintegrator_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_INITINTEGRATOR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_initmodulator_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_INITMODULATOR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_deltasig_mode_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_INTS_DELTASIG_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_freeze_en_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_INTS_FREEZE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gaindelaycount_pow2_muxd0_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gaindelaycount_pow2_muxd1_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gaindelaycount_pow2_muxd2_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gaindelaycount_pow2_muxd3_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gaindelaycount_pow2_muxd4_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd0_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd1_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd2_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd3_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd4_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd0_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd1_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd2_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd3_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd4_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainunlocked_pow2_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainunlocked_pow2_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainunlocked_pow2_muxd2_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainunlocked_pow2_muxd3_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainunlocked_pow2_muxd4_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_guardband_hi_attr == 8'd200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_guardband_lo_attr == 8'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_loop_sel_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_INTS_LOOP_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_mod_bypass_en_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_INTS_MOD_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_mod_load_pedge_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_INTS_MOD_LOAD_PEDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_step_to_integer_en_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_INTS_STEP_TO_INTEGER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_jit_length_attr == 18'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_jit_mode_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_JIT_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_modck_ctrl_en_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_MODCK_CTRL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_pll2data_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_restore_cntr_attr == 9'd258
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_store_cntr_attr == 16'd258
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpif_trnsfrdelay_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpiffreeze_inten_attr == SERDES_IP_LANE_L2_CFG_RXDPIFFREEZE_INTEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdpiffreeze_moden_attr == SERDES_IP_LANE_L2_CFG_RXDPIFFREEZE_MODEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxdutyselpolarity_attr == SERDES_IP_LANE_L2_CFG_RXDUTYSELPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxflxgate_force_rxeq_gate_locovr_attr == SERDES_IP_LANE_L2_CFG_RXFLXGATE_FORCE_RXEQ_GATE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxflxgate_locovren_attr == SERDES_IP_LANE_L2_CFG_RXFLXGATE_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxfoscstat_done_locovr_attr == SERDES_IP_LANE_L2_CFG_RXFOSCSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxfoscstat_locovren_attr == SERDES_IP_LANE_L2_CFG_RXFOSCSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxfsm_cken_ovr_attr == SERDES_IP_LANE_L2_CFG_RXFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxfsm_cken_ovren_attr == SERDES_IP_LANE_L2_CFG_RXFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxints_prev_votes_hold_en_attr == SERDES_IP_LANE_L2_CFG_RXINTS_PREV_VOTES_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxlanepam_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXLANEPAM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxlanepam_locovren_attr == SERDES_IP_LANE_L2_CFG_RXLANEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxlock2datatmr_attr == 8'd240
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxlock2datatmr_short_attr == 8'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxntl_changeref_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxntl_changeref_val_locovr_attr == SERDES_IP_LANE_L2_CFG_RXNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxntl_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxntl_en_attr == SERDES_IP_LANE_L2_CFG_RXNTL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxntl_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxntl_locovren_attr == SERDES_IP_LANE_L2_CFG_RXNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxntl_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxntl_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxntl_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxntl_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxntl_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxntl_rxm_charge_up_locovr_attr == SERDES_IP_LANE_L2_CFG_RXNTL_RXM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxntl_rxm_pull_dn_locovr_attr == SERDES_IP_LANE_L2_CFG_RXNTL_RXM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxntl_rxm_sense_locovr_attr == SERDES_IP_LANE_L2_CFG_RXNTL_RXM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxntl_rxp_charge_up_locovr_attr == SERDES_IP_LANE_L2_CFG_RXNTL_RXP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxntl_rxp_pull_dn_locovr_attr == SERDES_IP_LANE_L2_CFG_RXNTL_RXP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxntl_rxp_sense_locovr_attr == SERDES_IP_LANE_L2_CFG_RXNTL_RXP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxntl_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_acc_freeze_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_ACC_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_cdrlock2data_gater_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_cdrlock2data_gater_hold_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_cdrlock2data_gater_ovrd_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_cdrlock2datatmr_optcl_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_cdrlock2datatmr_optcl_sel_ovrd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_enter_lock2data_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_ENTER_LOCK2DATA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_enter_lock2data_hold_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_ENTER_LOCK2DATA_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_exit_lock2data_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_EXIT_LOCK2DATA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_exit_lock2data_hold_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_EXIT_LOCK2DATA_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_force_lock2data_ovrd_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_FORCE_LOCK2DATA_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_force_lock2ref_ovrd_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_FORCE_LOCK2REF_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_hold_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_hold_timer_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_intf_ovrd_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_INTF_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_intf_ovrd_type_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_INTF_OVRD_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_mod_freeze_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_MOD_FREEZE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_ovrd_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_ppm_detect_freeze_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_PPM_DETECT_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_ppm_detect_freeze_ovrd_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_PPM_DETECT_FREEZE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_ppm_detect_hold_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_PPM_DETECT_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_prop_freeze_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_PROP_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_prop_freeze_ovrd_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_PROP_FREEZE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_rxdata_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_RXDATA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_skip_init_lock2data_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_SKIP_INIT_LOCK2DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxpam_bitorder_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxpam_gray_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXPAM_GRAY_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxpam_locovren_attr == SERDES_IP_LANE_L2_CFG_RXPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxpam_precode_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXPAM_PRECODE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_muxd0_attr == 7'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_p5_muxd0_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIV_P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_p5_muxd1_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIV_P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_p5_muxd2_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIV_P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_p5_muxd3_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIV_P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_p5_muxd4_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIV_P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdivclken_muxd0_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIVCLKEN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdivclken_muxd1_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIVCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdivclken_muxd2_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIVCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdivclken_muxd3_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIVCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdivclken_muxd4_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIVCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxpcsbist_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXPCSBIST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxpcsbist_locovren_attr == SERDES_IP_LANE_L2_CFG_RXPCSBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxphd_gain_hold_en_attr == SERDES_IP_LANE_L2_CFG_RXPHD_GAIN_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxphd_gain_zero_locovr_attr == SERDES_IP_LANE_L2_CFG_RXPHD_GAIN_ZERO_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxphd_locovren_attr == SERDES_IP_LANE_L2_CFG_RXPHD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxphd_majvote_basegain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxphd_majvote_en_attr == SERDES_IP_LANE_L2_CFG_RXPHD_MAJVOTE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxphd_mute_cntr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxphd_nrz8b10b_pam16b20b_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxphd_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxphd_pam_transition_sel_attr == SERDES_IP_LANE_L2_CFG_RXPHD_PAM_TRANSITION_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxphd_sign_invert_attr == SERDES_IP_LANE_L2_CFG_RXPHD_SIGN_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxpostdiv_wait_for_lock_disable_attr == SERDES_IP_LANE_L2_CFG_RXPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxppm_freq_max_offset_h_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxppm_freq_max_offset_l_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxppm_freq_ref_cnt_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxppm_lockstatus_locovr_attr == SERDES_IP_LANE_L2_CFG_RXPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxppm_lockstatus_synthlcfast_en_attr == SERDES_IP_LANE_L2_CFG_RXPPM_LOCKSTATUS_SYNTHLCFAST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxppm_lockstatus_synthlcmed_en_attr == SERDES_IP_LANE_L2_CFG_RXPPM_LOCKSTATUS_SYNTHLCMED_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxppm_lockstatus_synthlcslow_en_attr == SERDES_IP_LANE_L2_CFG_RXPPM_LOCKSTATUS_SYNTHLCSLOW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxppm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxppm_ppmdriftcount_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxppm_ppmdriftmax_attr == 16'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxppm_status_hold_attr == SERDES_IP_LANE_L2_CFG_RXPPM_STATUS_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxppm_unlock_clear_attr == SERDES_IP_LANE_L2_CFG_RXPPM_UNLOCK_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_fast_muxd0_attr == 16'd1188
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_fast_muxd1_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_fast_muxd2_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_fast_muxd3_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_fast_muxd4_attr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_muxd0_attr == 16'd1188
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_muxd1_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_muxd2_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_muxd3_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_muxd4_attr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxppmctrl_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXPPMCTRL_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxppmctrl_locovren_attr == SERDES_IP_LANE_L2_CFG_RXPPMCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxppmlockstat_locovren_attr == SERDES_IP_LANE_L2_CFG_RXPPMLOCKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxppmlockstat_sticky_locovr_attr == SERDES_IP_LANE_L2_CFG_RXPPMLOCKSTAT_STICKY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxppmtmr_locovren_attr == SERDES_IP_LANE_L2_CFG_RXPPMTMR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxppmtmr_watchdogtmr_sel_locovr_attr == SERDES_IP_LANE_L2_CFG_RXPPMTMR_WATCHDOGTMR_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_cal_clear_delay_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_clk_chk_disable_attr == SERDES_IP_LANE_L2_CFG_RXRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_clk_delay_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_etr_on_delay_attr == 12'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_locovren_attr == SERDES_IP_LANE_L2_CFG_RXRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxreg_lev_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxreg_toggle_reset_on_rate_change_en_attr == SERDES_IP_LANE_L2_CFG_RXREG_TOGGLE_RESET_ON_RATE_CHANGE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxreg_vreg_bypass_attr == SERDES_IP_LANE_L2_CFG_RXREG_VREG_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_en_b_attr == SERDES_IP_LANE_L2_CFG_RXRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s0q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s0q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s2q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s2q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s2q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s2q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s2q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s2q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s2q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s3q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s3q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s3q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s3q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s3q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s3q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s3q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s3q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s4q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s4q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s5q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_entry4_attr == 13'd78
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_entry5_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_entry6_attr == 13'd1406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s0q2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s0q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s1q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s1q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s1q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s1q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s1q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s1q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s2q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s2q2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s2q3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s2q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s2q5_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s2q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s2q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s3q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s3q1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s3q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s3q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s3q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s3q5_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s3q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s3q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s4q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s4q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s5q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_aetrrx_cdrfbdivcken_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_AETRRX_CDRFBDIVCKEN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_aetrrx_cdrfbdivcken_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_AETRRX_CDRFBDIVCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_aetrrx_cdrmoddivcken_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_AETRRX_CDRMODDIVCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_aetrrx_cdrmoddivcken_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_AETRRX_CDRMODDIVCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_aetrrx_termhiz_en_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_AETRRX_TERMHIZ_EN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_aetrrx_termhiz_en_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_AETRRX_TERMHIZ_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_aetrsynth_pcspostdivclksel_ovr_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_AETRSYNTH_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_aetrsynth_pcspostdivclksel_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_AETRSYNTH_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_adc_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_adc_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_auxcomp_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_AUXCOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_auxcomp_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_AUXCOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_bias_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_bias_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_BIAS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_ctlecomp_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_CTLECOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_ctlecomp_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_CTLECOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_datfbdiv_b_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DATFBDIV_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_datfbdiv_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DATFBDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_dfe_bias_b_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DFE_BIAS_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_dfe_bias_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DFE_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_dfe_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DFE_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_dfe_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DFE_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_dfe_yadj_b_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DFE_YADJ_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_dfe_yadj_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DFE_YADJ_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_duty_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DUTY_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_duty_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DUTY_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_hifreqagc_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_HIFREQAGC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_hifreqagc_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_HIFREQAGC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_ntl_b_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_ntl_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_reg_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_reg_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_vco_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_VCO_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_vco_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_VCO_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_voscreg_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_VOSCREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_voscreg_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_VOSCREG_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_adc_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_adc_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_cdrfbdiv_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_CDRFBDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_cdrfbdiv_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_CDRFBDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_pdet_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_PDET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_pdet_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_PDET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_pfd_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_PFD_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_pfd_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_PFD_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_refdiv_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_refdiv_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_reg_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_reg_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_s2pa_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_S2PA_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_s2pa_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_S2PA_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_s2pb_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_S2PB_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_s2pb_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_S2PB_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_vco_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_VCO_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_vco_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_VCO_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_voscreg_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_VOSCREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_voscreg_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_VOSCREG_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstsynth_postdiv_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTSYNTH_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstsynth_postdiv_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTSYNTH_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_drstrx_dpif_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_DRSTRX_DPIF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_drstrx_dpif_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_DRSTRX_DPIF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_drstrx_ppm_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_DRSTRX_PPM_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_drstrx_ppm_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_DRSTRX_PPM_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_cdrlock2data_locovr_attr == SERDES_IP_LANE_L2_CFG_RXSIGDET_CDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_diglfpsdeten_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_diglfpsdeten_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_diglfpsdeten_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_diglfpsdeten_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_diglfpsdeten_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrancnten_muxd0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrancnten_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrancnten_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrancnten_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrancnten_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrancnten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrandeten_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrandeten_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrandeten_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrandeten_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrandeten_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrandeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_eiosdeten_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_eiosdeten_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_eiosdeten_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_eiosdeten_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_eiosdeten_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_eiosdeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_enable_attr == SERDES_IP_LANE_L2_CFG_RXSIGDET_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_fastlock_winsize_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_leveldeten_muxd0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_leveldeten_muxd1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_leveldeten_muxd2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_leveldeten_muxd3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_leveldeten_muxd4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_leveldeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_lfpsexit_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_locovren_attr == SERDES_IP_LANE_L2_CFG_RXSIGDET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_ppmdeten_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_ppmdeten_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_ppmdeten_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_ppmdeten_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_ppmdeten_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_ppmdeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_rxeq_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_rxeqen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_rxeqen_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_rxleveldet_debounce_dncount_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_rxleveldet_debounce_flush_en_attr == SERDES_IP_LANE_L2_CFG_RXSIGDET_RXLEVELDET_DEBOUNCE_FLUSH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_rxleveldet_debounce_upcount_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_sigdet_debounce_attr == SERDES_IP_LANE_L2_CFG_RXSIGDET_SIGDET_DEBOUNCE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_tmr_clksel_attr == SERDES_IP_LANE_L2_CFG_RXSIGDET_TMR_CLKSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_toggle_count_en_attr == SERDES_IP_LANE_L2_CFG_RXSIGDET_TOGGLE_COUNT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_toggle_count_pause_attr == SERDES_IP_LANE_L2_CFG_RXSIGDET_TOGGLE_COUNT_PAUSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_toggle_monitor_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdetin_eiosdetectstat_locovr_attr == SERDES_IP_LANE_L2_CFG_RXSIGDETIN_EIOSDETECTSTAT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdetin_locovren_attr == SERDES_IP_LANE_L2_CFG_RXSIGDETIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdetin_ovrcdrlock2data_locovr_attr == SERDES_IP_LANE_L2_CFG_RXSIGDETIN_OVRCDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdetin_ovrencdrlock2data_locovr_attr == SERDES_IP_LANE_L2_CFG_RXSIGDETIN_OVRENCDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdetout_lock2data_noforce_ltr_locovr_attr == SERDES_IP_LANE_L2_CFG_RXSIGDETOUT_LOCK2DATA_NOFORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsigdetout_locovren_attr == SERDES_IP_LANE_L2_CFG_RXSIGDETOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxspare0_attr == 32'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxspare_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsqlchlfps_consec_one_thresh_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsqlchlfps_consec_zero_thresh_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsqlchlfps_cycle_thresh_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsqlchlfps_dat_bitorder_attr == SERDES_IP_LANE_L2_CFG_RXSQLCHLFPS_DAT_BITORDER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsqlchlfps_debounce_type_attr == SERDES_IP_LANE_L2_CFG_RXSQLCHLFPS_DEBOUNCE_TYPE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsqlchlfps_one_run_length_thresh_attr == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsqlchlfps_one_run_length_timeout_attr == 8'd103
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsqlchlfps_zero_run_length_thresh_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsqlchlfps_zero_run_length_timeout_attr == 8'd103
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsynthdiv_slowmed_en_muxd0_attr == SERDES_IP_LANE_L2_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsynthdiv_slowmed_en_muxd1_attr == SERDES_IP_LANE_L2_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsynthdiv_slowmed_en_muxd2_attr == SERDES_IP_LANE_L2_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsynthdiv_slowmed_en_muxd3_attr == SERDES_IP_LANE_L2_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxsynthdiv_slowmed_en_muxd4_attr == SERDES_IP_LANE_L2_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxterm_cal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxterm_coarse_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxterm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXTERM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxterm_modeselect_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxtermhiz_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXTERMHIZ_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxtermhiz_locovren_attr == SERDES_IP_LANE_L2_CFG_RXTERMHIZ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxvoscreg_bypass_vosc_attr == SERDES_IP_LANE_L2_CFG_RXVOSCREG_BYPASS_VOSC_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxvoscregopampoffsetctrl_sel_attr == SERDES_IP_LANE_L2_CFG_RXVOSCREGOPAMPOFFSETCTRL_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxvoscregopampoffseterr_locovren_attr == SERDES_IP_LANE_L2_CFG_RXVOSCREGOPAMPOFFSETERR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxvoscregopampoffseterr_sel_locovr_attr == SERDES_IP_LANE_L2_CFG_RXVOSCREGOPAMPOFFSETERR_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxvoscregvref_locovren_attr == SERDES_IP_LANE_L2_CFG_RXVOSCREGVREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_rxvoscregvref_sel_locovr_attr == SERDES_IP_LANE_L2_CFG_RXVOSCREGVREF_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlch_acqgain_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlch_acqtime_attr == 13'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlch_cal_quiet_locovr_attr == SERDES_IP_LANE_L2_CFG_SQLCH_CAL_QUIET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlch_cal_sel_locovr_attr == SERDES_IP_LANE_L2_CFG_SQLCH_CAL_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlch_calctrl_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlch_calen_locovr_attr == SERDES_IP_LANE_L2_CFG_SQLCH_CALEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlch_caltimer_attr == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlch_clkgate_locovr_attr == SERDES_IP_LANE_L2_CFG_SQLCH_CLKGATE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlch_cmshiften_attr == SERDES_IP_LANE_L2_CFG_SQLCH_CMSHIFTEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_acq_gain_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_acq_pct_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_cal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_clr_errlog_attr == SERDES_IP_LANE_L2_CFG_SQLCH_CONT_CLR_ERRLOG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_controller_mode_attr == SERDES_IP_LANE_L2_CFG_SQLCH_CONT_CONTROLLER_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_dis_attr == SERDES_IP_LANE_L2_CFG_SQLCH_CONT_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_pause_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_postcal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_precal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_quiet_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlch_lfps_en_attr == SERDES_IP_LANE_L2_CFG_SQLCH_LFPS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlch_locovren_attr == SERDES_IP_LANE_L2_CFG_SQLCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlch_ovrd_val_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlch_pkdet_freqsel_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlch_polarity_attr == SERDES_IP_LANE_L2_CFG_SQLCH_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlch_rdacen_attr == SERDES_IP_LANE_L2_CFG_SQLCH_RDACEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlch_thresh_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlch_time_out_attr == 16'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlch_vrefsel0_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlch_vrefsel1_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlch_vrefsel_ovr_en_attr == SERDES_IP_LANE_L2_CFG_SQLCH_VREFSEL_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlchdeb_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlchdeb_deb_cnt_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlchdeb_deb_status_cnt_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlchdeb_en_attr == SERDES_IP_LANE_L2_CFG_SQLCHDEB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlchdeb_ign_cnt_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlchdeb_sigdet_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlchdeb_thresh_cnt_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlchdebout_exit_good_debounced_locovr_attr == SERDES_IP_LANE_L2_CFG_SQLCHDEBOUT_EXIT_GOOD_DEBOUNCED_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlchdebout_exit_good_debounced_status_locovr_attr == SERDES_IP_LANE_L2_CFG_SQLCHDEBOUT_EXIT_GOOD_DEBOUNCED_STATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlchdebout_exit_good_locovr_attr == SERDES_IP_LANE_L2_CFG_SQLCHDEBOUT_EXIT_GOOD_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_sqlchdebout_locovren_attr == SERDES_IP_LANE_L2_CFG_SQLCHDEBOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_trancnt_off_attr == 10'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_trancnt_on_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_trancntout_det_locovr_attr == SERDES_IP_LANE_L2_CFG_TRANCNTOUT_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_trancntout_locovren_attr == SERDES_IP_LANE_L2_CFG_TRANCNTOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_trandet_ax_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_trandet_ay_attr == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_trandet_off_h_attr == 6'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_trandet_off_l_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_trandet_on_h_attr == 6'd39
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_trandet_on_l_attr == 6'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_trandetout_det_locovr_attr == SERDES_IP_LANE_L2_CFG_TRANDETOUT_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_trandetout_locovren_attr == SERDES_IP_LANE_L2_CFG_TRANDETOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_tx2rxlb_en_attr == SERDES_IP_LANE_L2_CFG_TX2RXLB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_tx2rxlb_init_offset_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_tx_cmn_on_state_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_tx_fastregpwrup_en_attr == SERDES_IP_LANE_L2_CFG_TX_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_tx_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_tx_pg_disable_attr == SERDES_IP_LANE_L2_CFG_TX_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_tx_synth_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_tx_synth_sel_amode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_tx_synth_sel_bmode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_tx_synth_sel_cmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_tx_synth_sel_dmode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_tx_synth_sel_emode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_tx_txdetrx_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txadc_req_attr == SERDES_IP_LANE_L2_CFG_TXADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txaprobe_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txaprobe_lastmux_isolate_attr == SERDES_IP_LANE_L2_CFG_TXAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txaprobeadc_current_direction_attr == SERDES_IP_LANE_L2_CFG_TXAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txaprobeadc_resistor_enable_attr == SERDES_IP_LANE_L2_CFG_TXAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txbdvdr_pma2pcstxworden_attr == SERDES_IP_LANE_L2_CFG_TXBDVDR_PMA2PCSTXWORDEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txbeacon_div_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txbeacon_sel_attr == SERDES_IP_LANE_L2_CFG_TXBEACON_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txbias_icc20uadj_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txbias_icc80uadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txbias_locovren_attr == SERDES_IP_LANE_L2_CFG_TXBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txbias_termcal_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txbist_biterror_en_attr == SERDES_IP_LANE_L2_CFG_TXBIST_BITERROR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txbist_locovren_attr == SERDES_IP_LANE_L2_CFG_TXBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txbist_modesel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txbist_oobmode_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txbist_oobtburst_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txbist_oobtcomrstinit_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txbist_oobtcomsas_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txbist_oobtcomwake_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txbist_seed_attr == 31'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_size_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf00_attr == 32'd1985229328
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf01_attr == 32'd4275878552
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf02_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf03_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf04_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf05_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf06_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf07_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf08_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf09_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txbit_select_muxd0_attr == SERDES_IP_LANE_L2_CFG_TXBIT_SELECT_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txbit_select_muxd1_attr == SERDES_IP_LANE_L2_CFG_TXBIT_SELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txbit_select_muxd2_attr == SERDES_IP_LANE_L2_CFG_TXBIT_SELECT_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txbit_select_muxd3_attr == SERDES_IP_LANE_L2_CFG_TXBIT_SELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txbit_select_muxd4_attr == SERDES_IP_LANE_L2_CFG_TXBIT_SELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txbti_data_replication_attr == SERDES_IP_LANE_L2_CFG_TXBTI_DATA_REPLICATION_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txbti_tx_idle_data_en_attr == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcal_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcal_tclkduty_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalduty_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalduty_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTY_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalduty_sel_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutybg_abort_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutybg_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutybg_ready_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutycomp_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutycomp_offset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_finish_side_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_init_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_initval_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_invert_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_req_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_round_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_runcount_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_signmagen_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsmout_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsmout_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompmeas_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompmeas_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompmeas_req_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompmeasout_ack_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPMEASOUT_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompmeasout_erravg_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPMEASOUT_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompmeasout_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_bg_en_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_bg_one_step_cal_en_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_finish_side_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_init_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_invert_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_req_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_round_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_runcount_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_signmagen_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeas_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeas_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeas_req_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeasout_ack_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYMEASOUT_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeasout_erravg_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYMEASOUT_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeasout_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutystat_done_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaldutystat_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalptr_pstate_duty_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalptr_pstate_dutycomp_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalptr_pstate_regopampoffset_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_duty_muxd0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_duty_muxd1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_duty_muxd2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_duty_muxd3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_duty_muxd4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_dutycomp_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_dutycomp_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_dutycomp_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_dutycomp_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_dutycomp_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_regopampoffset_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffset_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_finish_side_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_round_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_runcount_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_signmagen_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcaltclkdutyforce_div1_attr == SERDES_IP_LANE_L2_CFG_TXCALTCLKDUTYFORCE_DIV1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txcdrdiv_local_en_attr == SERDES_IP_LANE_L2_CFG_TXCDRDIV_LOCAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txclk_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txclk_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txclkgenmuxsel_txinternal_attr == SERDES_IP_LANE_L2_CFG_TXCLKGENMUXSEL_TXINTERNAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txdetectrx_thr_attr == 5'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeas_count_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeas_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXDETECTRXMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeas_locovren_attr == SERDES_IP_LANE_L2_CFG_TXDETECTRXMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeas_validdlycount_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeasin_locovren_attr == SERDES_IP_LANE_L2_CFG_TXDETECTRXMEASIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeasin_start_locovr_attr == SERDES_IP_LANE_L2_CFG_TXDETECTRXMEASIN_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeaspcs_locovren_attr == SERDES_IP_LANE_L2_CFG_TXDETECTRXMEASPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeaspcs_req_locovr_attr == SERDES_IP_LANE_L2_CFG_TXDETECTRXMEASPCS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeasval_locovren_attr == SERDES_IP_LANE_L2_CFG_TXDETECTRXMEASVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeasval_stat_locovr_attr == SERDES_IP_LANE_L2_CFG_TXDETECTRXMEASVAL_STAT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txdetrx_levn_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txdetrx_levnm1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txdetrx_levnp1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txdetrx_levnp2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txdrv_hizen_locovr_attr == SERDES_IP_LANE_L2_CFG_TXDRV_HIZEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txdrv_levn_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txdrv_levnm1_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txdrv_levnp1_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txdrv_levnp2_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txdrv_locovren_attr == SERDES_IP_LANE_L2_CFG_TXDRV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txdrv_refcken_attr == SERDES_IP_LANE_L2_CFG_TXDRV_REFCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txdrv_termref_attr == SERDES_IP_LANE_L2_CFG_TXDRV_TERMREF_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txdrvmute_locovr_attr == SERDES_IP_LANE_L2_CFG_TXDRVMUTE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txdrvmute_locovren_attr == SERDES_IP_LANE_L2_CFG_TXDRVMUTE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txduty_ctrl_disable_attr == SERDES_IP_LANE_L2_CFG_TXDUTY_CTRL_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txduty_pad_sense_en_attr == SERDES_IP_LANE_L2_CFG_TXDUTY_PAD_SENSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txdutycal_div16_en_attr == SERDES_IP_LANE_L2_CFG_TXDUTYCAL_DIV16_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txdutycal_div1_en_attr == SERDES_IP_LANE_L2_CFG_TXDUTYCAL_DIV1_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txdutycal_div2_en_attr == SERDES_IP_LANE_L2_CFG_TXDUTYCAL_DIV2_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txdutycal_div4_en_attr == SERDES_IP_LANE_L2_CFG_TXDUTYCAL_DIV4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txdutycal_div8_en_attr == SERDES_IP_LANE_L2_CFG_TXDUTYCAL_DIV8_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txfifo_elecidle_deskew_en_attr == SERDES_IP_LANE_L2_CFG_TXFIFO_ELECIDLE_DESKEW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txfifo_force_txidlebit1_zero_disable_attr == SERDES_IP_LANE_L2_CFG_TXFIFO_FORCE_TXIDLEBIT1_ZERO_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txfifo_kill_dly_10b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txfifo_kill_dly_16b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txfifo_kill_dly_20b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txfifo_kill_dly_32b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txfifo_kill_dly_40b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txfifo_kill_dly_64b_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txfifo_kill_dly_80b_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txfifo_kill_dly_8b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txfifo_kill_en_attr == SERDES_IP_LANE_L2_CFG_TXFIFO_KILL_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txfsm_cken_ovr_attr == SERDES_IP_LANE_L2_CFG_TXFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txfsm_cken_ovren_attr == SERDES_IP_LANE_L2_CFG_TXFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txfsm_main_on_state_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txl1d1_doze_ctrl_attr == SERDES_IP_LANE_L2_CFG_TXL1D1_DOZE_CTRL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txl1d1_txbias_ctrl_attr == SERDES_IP_LANE_L2_CFG_TXL1D1_TXBIAS_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txlanepam_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXLANEPAM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txlanepam_locovren_attr == SERDES_IP_LANE_L2_CFG_TXLANEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txmeaslatovrhd_meas_sel_attr == SERDES_IP_LANE_L2_CFG_TXMEASLATOVRHD_MEAS_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txmute_delay_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txntl_changeref_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txntl_changeref_val_locovr_attr == SERDES_IP_LANE_L2_CFG_TXNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txntl_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txntl_en_attr == SERDES_IP_LANE_L2_CFG_TXNTL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txntl_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txntl_locovren_attr == SERDES_IP_LANE_L2_CFG_TXNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txntl_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txntl_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txntl_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txntl_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txntl_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txntl_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txntl_txm_charge_up_locovr_attr == SERDES_IP_LANE_L2_CFG_TXNTL_TXM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txntl_txm_pull_dn_locovr_attr == SERDES_IP_LANE_L2_CFG_TXNTL_TXM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txntl_txm_sense_locovr_attr == SERDES_IP_LANE_L2_CFG_TXNTL_TXM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txntl_txp_charge_up_locovr_attr == SERDES_IP_LANE_L2_CFG_TXNTL_TXP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txntl_txp_pull_dn_locovr_attr == SERDES_IP_LANE_L2_CFG_TXNTL_TXP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txntl_txp_sense_locovr_attr == SERDES_IP_LANE_L2_CFG_TXNTL_TXP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txp2s_txwordsyncbypen_attr == SERDES_IP_LANE_L2_CFG_TXP2S_TXWORDSYNCBYPEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txpam_bitorder_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txpam_gray_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXPAM_GRAY_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txpam_locovren_attr == SERDES_IP_LANE_L2_CFG_TXPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txpam_precode_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXPAM_PRECODE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txpcs_locovren_attr == SERDES_IP_LANE_L2_CFG_TXPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txpcs_txenable_locovr_attr == SERDES_IP_LANE_L2_CFG_TXPCS_TXENABLE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txpcsbist_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXPCSBIST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txpcsbist_locovren_attr == SERDES_IP_LANE_L2_CFG_TXPCSBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txratewidth_clk_chk_disable_attr == SERDES_IP_LANE_L2_CFG_TXRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txratewidth_etr_on_delay_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txratewidth_locovren_attr == SERDES_IP_LANE_L2_CFG_TXRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txreg_toggle_pwrupacc_on_rate_change_en_attr == SERDES_IP_LANE_L2_CFG_TXREG_TOGGLE_PWRUPACC_ON_RATE_CHANGE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txreg_toggle_reset_on_rate_change_en_attr == SERDES_IP_LANE_L2_CFG_TXREG_TOGGLE_RESET_ON_RATE_CHANGE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txresetdel_sel_attr == SERDES_IP_LANE_L2_CFG_TXRESETDEL_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_en_b_attr == SERDES_IP_LANE_L2_CFG_TXRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s0q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s0q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s1q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s1q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s2q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s2q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s2q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s2q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s2q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s2q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s2q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s3q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s3q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s3q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s3q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s3q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s3q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s3q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s3q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s4q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s4q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s5q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s0q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s0q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s1q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s1q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s1q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s1q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s1q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s1q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s2q0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s2q1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s2q2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s2q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s2q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s2q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s2q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s2q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s3q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s3q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s3q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s3q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s3q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s3q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s3q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s3q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s4q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s4q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s5q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_dn_ptr0_s_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_up_ptr0_s_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_aetrtx_bitckdvdrcken_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_AETRTX_BITCKDVDRCKEN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_aetrtx_bitckdvdrcken_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_AETRTX_BITCKDVDRCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_aetrtx_regpwrupacc_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_AETRTX_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_aetrtx_regpwrupacc_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_AETRTX_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_adc_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_adc_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_drvdoze_b_ovr_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_DRVDOZE_B_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_drvdoze_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_DRVDOZE_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_duty_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_DUTY_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_duty_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_DUTY_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_ntl_b_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_ntl_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_p2s_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_P2S_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_p2s_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_P2S_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_reg_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_reg_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_arsttx_adc_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_ARSTTX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_arsttx_adc_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_ARSTTX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_arsttx_pma2pcstxword_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_ARSTTX_PMA2PCSTXWORD_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_arsttx_pma2pcstxword_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_ARSTTX_PMA2PCSTXWORD_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_arsttx_regreset_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_ARSTTX_REGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_arsttx_regreset_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_ARSTTX_REGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_arsttx_txdetectrx_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_ARSTTX_TXDETECTRX_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_arsttx_txdetectrx_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_ARSTTX_TXDETECTRX_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txrststate_hiz_en_attr == SERDES_IP_LANE_L2_CFG_TXRSTSTATE_HIZ_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txspare0_attr == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txspare_attr == 10'd384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txterm_coarse_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txtermtrim_locovren_attr == SERDES_IP_LANE_L2_CFG_TXTERMTRIM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txtermtrim_nmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txtermtrim_pmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txwclk_div_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txwclk_div_en_attr == SERDES_IP_LANE_L2_CFG_TXWCLK_DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txwclk_div_smpl_attr == SERDES_IP_LANE_L2_CFG_TXWCLK_DIV_SMPL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txwptr_init01_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txwptr_init02_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txwptr_init04_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txwptr_init08_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txwptr_init16_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txwptr_init32_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l2_cfg_txwptr_init_rx2txparlb_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_bshihyst_attr == SERDES_IP_LANE_L3_CFG_BSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_bstxdrv_levn_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_bstxdrv_levnm1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_bstxdrv_levnp1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_bstxdrv_levnp2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_calsqlchosc_locovren_attr == SERDES_IP_LANE_L3_CFG_CALSQLCHOSC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_calsqlchosc_trimcode_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_cdrclkstat_locovren_attr == SERDES_IP_LANE_L3_CFG_CDRCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_cdrclkstat_ready_locovr_attr == SERDES_IP_LANE_L3_CFG_CDRCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_etrregrxcdrclk_ready_attr == SERDES_IP_LANE_L3_CFG_ETRREGRXCDRCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_laneckm_avg_en_attr == SERDES_IP_LANE_L3_CFG_LANECKM_AVG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_laneckm_clk_en_attr == SERDES_IP_LANE_L3_CFG_LANECKM_CLK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_laneckm_continuous_attr == SERDES_IP_LANE_L3_CFG_LANECKM_CONTINUOUS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_laneckm_dig_meas_en_attr == SERDES_IP_LANE_L3_CFG_LANECKM_DIG_MEAS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_laneckm_dig_meas_err_clr_attr == SERDES_IP_LANE_L3_CFG_LANECKM_DIG_MEAS_ERR_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_laneckm_en_attr == SERDES_IP_LANE_L3_CFG_LANECKM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_laneckm_max_thr_attr == 25'd33554431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_laneckm_meas_ck_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_laneckm_ref_ck_div_ratio_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_laneckm_result_clr_attr == SERDES_IP_LANE_L3_CFG_LANECKM_RESULT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_laneckm_start_attr == SERDES_IP_LANE_L3_CFG_LANECKM_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_laneckm_wdt_interval_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_laneckm_win_thr_ref_attr == 25'd16777215
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_lanepcs_locovren_attr == SERDES_IP_LANE_L3_CFG_LANEPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_lanepcs_mode_locovr_attr == SERDES_IP_LANE_L3_CFG_LANEPCS_MODE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_laneperfmon_compare_val_start_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_laneperfmon_compare_val_stop_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_laneperfmon_en_attr == SERDES_IP_LANE_L3_CFG_LANEPERFMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_laneperfmon_mask_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_lanepmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_lanepmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_lanepmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_lanepmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_lanepmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_lanepmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_lb_cdrclk2txen_locovr_attr == SERDES_IP_LANE_L3_CFG_LB_CDRCLK2TXEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_lb_cdrclkdiven_attr == SERDES_IP_LANE_L3_CFG_LB_CDRCLKDIVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_lb_cdrdivclk2exten_attr == SERDES_IP_LANE_L3_CFG_LB_CDRDIVCLK2EXTEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_lb_cdrdivclk2txen_attr == SERDES_IP_LANE_L3_CFG_LB_CDRDIVCLK2TXEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_lb_hsclk2cdrdiven_attr == SERDES_IP_LANE_L3_CFG_LB_HSCLK2CDRDIVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_lb_locovren_attr == SERDES_IP_LANE_L3_CFG_LB_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_lb_parrx2txtimeden_locovr_attr == SERDES_IP_LANE_L3_CFG_LB_PARRX2TXTIMEDEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_lb_pllfbclk2cdrrefclken_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_lb_pllfbclk2cdrrefclken_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_lb_pllfbclk2cdrrefclken_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_lb_pllfbclk2cdrrefclken_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_lb_pllfbclk2cdrrefclken_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_lb_rx2txuntimeden_attr == SERDES_IP_LANE_L3_CFG_LB_RX2TXUNTIMEDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_lb_rxwordck2pcstxwordcken_attr == SERDES_IP_LANE_L3_CFG_LB_RXWORDCK2PCSTXWORDCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_lb_tx2rxbuftimeden_lsb_locovr_attr == SERDES_IP_LANE_L3_CFG_LB_TX2RXBUFTIMEDEN_LSB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_lb_tx2rxbuftimeden_msb_locovr_attr == SERDES_IP_LANE_L3_CFG_LB_TX2RXBUFTIMEDEN_MSB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_lb_tx2rxiotimeden_attr == SERDES_IP_LANE_L3_CFG_LB_TX2RXIOTIMEDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_lfps_det_locovr_attr == SERDES_IP_LANE_L3_CFG_LFPS_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_lfps_locovren_attr == SERDES_IP_LANE_L3_CFG_LFPS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_lfps_out_en_attr == SERDES_IP_LANE_L3_CFG_LFPS_OUT_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_pcslfps_en_locovr_attr == SERDES_IP_LANE_L3_CFG_PCSLFPS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_pcslfps_locovren_attr == SERDES_IP_LANE_L3_CFG_PCSLFPS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_pcsrx_dme_en_locovr_attr == SERDES_IP_LANE_L3_CFG_PCSRX_DME_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_pcsrx_locovren_attr == SERDES_IP_LANE_L3_CFG_PCSRX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_pcsrxbist_locovren_attr == SERDES_IP_LANE_L3_CFG_PCSRXBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_pcsrxbist_modesel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_pcstx_beaconen_locovr_attr == SERDES_IP_LANE_L3_CFG_PCSTX_BEACONEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_pcstx_locovren_attr == SERDES_IP_LANE_L3_CFG_PCSTX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_polarity_rx_attr == SERDES_IP_LANE_L3_CFG_POLARITY_RX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_polarity_tx_attr == SERDES_IP_LANE_L3_CFG_POLARITY_TX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rx_cmn_on_state_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rx_fastregpwrup_en_attr == SERDES_IP_LANE_L3_CFG_RX_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rx_frac_mode_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rx_on_state_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rx_pg_disable_attr == SERDES_IP_LANE_L3_CFG_RX_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rx_synth_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rx_synth_sel_amode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rx_synth_sel_bmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rx_synth_sel_cmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rx_synth_sel_dmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rx_synth_sel_emode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxadc_req_attr == SERDES_IP_LANE_L3_CFG_RXADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxagc_dccoupleen_attr == SERDES_IP_LANE_L3_CFG_RXAGC_DCCOUPLEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxaprobe_addr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxaprobe_lastmux_isolate_attr == SERDES_IP_LANE_L3_CFG_RXAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxaprobeadc_current_direction_attr == SERDES_IP_LANE_L3_CFG_RXAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxaprobeadc_resistor_enable_attr == SERDES_IP_LANE_L3_CFG_RXAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxbias_iccadj_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxbias_icvadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxbias_locovren_attr == SERDES_IP_LANE_L3_CFG_RXBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxbias_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxbist_burst_four_errtype_attr == SERDES_IP_LANE_L3_CFG_RXBIST_BURST_FOUR_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxbist_burst_one_errtype_attr == SERDES_IP_LANE_L3_CFG_RXBIST_BURST_ONE_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxbist_burst_three_errtype_attr == SERDES_IP_LANE_L3_CFG_RXBIST_BURST_THREE_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxbist_burst_two_errtype_attr == SERDES_IP_LANE_L3_CFG_RXBIST_BURST_TWO_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxbist_cdrlock2data_bypass_attr == SERDES_IP_LANE_L3_CFG_RXBIST_CDRLOCK2DATA_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxbist_cdrlock2data_postamble_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxbist_clear_errcount_attr == SERDES_IP_LANE_L3_CFG_RXBIST_CLEAR_ERRCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxbist_err_en_attr == SERDES_IP_LANE_L3_CFG_RXBIST_ERR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxbist_err_trig_type_attr == SERDES_IP_LANE_L3_CFG_RXBIST_ERR_TRIG_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxbist_errmask_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxbist_errtype_attr == SERDES_IP_LANE_L3_CFG_RXBIST_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxbist_firsterr_type_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxbist_lockchk_count_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxbist_maxbitcnt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxbist_mostrecent_err_attr == SERDES_IP_LANE_L3_CFG_RXBIST_MOSTRECENT_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxbist_relock_itercount_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxbist_seed_attr == 31'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxbist_status_hold_attr == SERDES_IP_LANE_L3_CFG_RXBIST_STATUS_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxbitslip_locovr_attr == SERDES_IP_LANE_L3_CFG_RXBITSLIP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxbitslip_locovren_attr == SERDES_IP_LANE_L3_CFG_RXBITSLIP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxbscan_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxbshicm_attr == SERDES_IP_LANE_L3_CFG_RXBSHICM_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalcdrfbdiv_div2_bypass_muxd0_attr == SERDES_IP_LANE_L3_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalcdrfbdiv_div2_bypass_muxd1_attr == SERDES_IP_LANE_L3_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalcdrfbdiv_div2_bypass_muxd2_attr == SERDES_IP_LANE_L3_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalcdrfbdiv_div2_bypass_muxd3_attr == SERDES_IP_LANE_L3_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalcdrfbdiv_div2_bypass_muxd4_attr == SERDES_IP_LANE_L3_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalduty_iclk_gray_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalduty_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTY_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalduty_qclk_gray_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalduty_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutybg_abort_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutybg_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutybg_ready_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycomp_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycomp_offset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_finish_side_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_init_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_initval_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_invert_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_round_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_runcount_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_signmagen_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsmout_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsmout_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_disable_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCTRL_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_i_div1_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_i_div2_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_i_div4_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_i_div8_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_q_div1_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_q_div2_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_q_div4_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_q_div8_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_bg_en_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_bg_one_step_cal_en_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_finish_side_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_i_polarity_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_I_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_i_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_I_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_init_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_q_polarity_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_Q_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_q_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_Q_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_round_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_runcount_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_signmagen_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_comp_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEAS_COMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_comp_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEAS_COMP_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_i_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEAS_I_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_i_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEAS_I_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_q_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEAS_Q_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_q_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEAS_Q_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeasout_comp_ack_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEASOUT_COMP_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeasout_comp_erravg_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEASOUT_COMP_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeasout_i_ack_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEASOUT_I_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeasout_i_erravg_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEASOUT_I_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeasout_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeasout_q_ack_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEASOUT_Q_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeasout_q_erravg_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEASOUT_Q_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutystat_done_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaldutystat_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_centerfreq_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_end_delay_attr == 9'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_hscount_muxd0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_hscount_muxd1_attr == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_hscount_muxd2_attr == 8'd180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_hscount_muxd3_attr == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_hscount_muxd4_attr == 8'd206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_initval_centerfreq_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_initval_fosc_attr == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_centerfreq_finish_side_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_CENTERFREQ_FINISH_SIDE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_centerfreq_to_fosc_offset_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_centerfreqen_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_CENTERFREQEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_centerfreqoffset_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_fosc_finishside_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_FOSC_FINISHSIDE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_foscen_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_FOSCEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_foscoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_init_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_invert_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_lpfax_calfosccoarse_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_lpfax_calfoscfine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_lpfax_centerfreqcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_lpfax_centerfreqfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_runcount_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_signmagen_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_vcorepen_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_VCOREPEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsmout_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsmout_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_count_muxd0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_count_muxd1_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_count_muxd2_attr == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_count_muxd3_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_count_muxd4_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_dlycount_attr == 9'd68
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeasout_clear_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCMEASOUT_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeasout_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeasout_start_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCMEASOUT_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscval_int_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscval_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalintsval_int_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalintsval_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALINTSVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaloffsetfsm_init_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaloffsetfsm_init_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaloffsetfsm_init_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALOFFSETFSM_INIT_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaloffsetfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcaloffsetfsmout_input_en_attr == SERDES_IP_LANE_L3_CFG_RXCALOFFSETFSMOUT_INPUT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_duty_i_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_duty_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_dutycomp_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_foscfsm_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_offsetfsm_init_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_regopampoffset_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_rxppm_lockstatus_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_sqlch_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_sqlchosc_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_synthppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_voscregopampoffset_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_duty_i_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_duty_q_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_dutycomp_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_foscfsm_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_offsetfsm_init_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_rxppm_lockstatus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_sqlch_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_sqlchosc_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_synthppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_voscregopampoffset_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffset_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_finish_side_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_round_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_runcount_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_signmagen_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchfsm_clear_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchfsm_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchfsmout_caldone_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHFSMOUT_CALDONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchfsmout_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_codeoffset_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_finish_side_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHOSCFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_init_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHOSCFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_initval_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_invert_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHOSCFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHOSCFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHOSCFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_round_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHOSCFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_runcount_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHOSCFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscmeas_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHOSCMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscmeas_ref_cnt_attr == 10'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscmeas_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHOSCMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscmeas_settle_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscmeas_smpl_cnt_attr == 10'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvbiascap_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALVBIASCAP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvbiascap_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALVBIASCAP_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvcoopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvcoopampoffsetmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvcoopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvcoopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffset_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffset_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_codeoffset_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_finish_side_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_initval_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_invert_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_lpfaxcoarse_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_round_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_runcount_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETFSM_RUNCOUNT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_signmagen_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsmout_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsmout_runcount_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETFSMOUT_RUNCOUNT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetmeas_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffset_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALVOSCREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALVOSCREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L3_CFG_RXCALVOSCREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALVOSCREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALVOSCREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALVOSCREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALVOSCREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALVOSCREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALVOSCREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrdiv_local_en_attr == SERDES_IP_LANE_L3_CFG_RXCDRDIV_LOCAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdiv_moddiv_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdiv_moddiv_muxd1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdiv_moddiv_muxd2_attr == 4'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdiv_moddiv_muxd3_attr == 4'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdiv_moddiv_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdivslip_mdiv_muxd0_attr == 9'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdivslip_mdiv_muxd1_attr == 9'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdivslip_mdiv_muxd2_attr == 9'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdivslip_mdiv_muxd3_attr == 9'd66
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdivslip_mdiv_muxd4_attr == 9'd210
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrpfd_forcedn_attr == SERDES_IP_LANE_L3_CFG_RXCDRPFD_FORCEDN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrpfd_forceen_attr == SERDES_IP_LANE_L3_CFG_RXCDRPFD_FORCEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrpfd_forceup_attr == SERDES_IP_LANE_L3_CFG_RXCDRPFD_FORCEUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrpfd_propgain_attr == SERDES_IP_LANE_L3_CFG_RXCDRPFD_PROPGAIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrpfd_pulsewidth_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrphd_asym_override_ignore_attr == SERDES_IP_LANE_L3_CFG_RXCDRPHD_ASYM_OVERRIDE_IGNORE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrphd_bitshift_en_attr == SERDES_IP_LANE_L3_CFG_RXCDRPHD_BITSHIFT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrphd_forcedn_attr == SERDES_IP_LANE_L3_CFG_RXCDRPHD_FORCEDN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrphd_forceen_attr == SERDES_IP_LANE_L3_CFG_RXCDRPHD_FORCEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrphd_forceup_attr == SERDES_IP_LANE_L3_CFG_RXCDRPHD_FORCEUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrphdrate_doublerate2s2p_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCDRPHDRATE_DOUBLERATE2S2P_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrphdrate_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCDRPHDRATE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrrefck_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrrefck_refdiv_muxd1_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrrefck_refdiv_muxd2_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrrefck_refdiv_muxd3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrrefck_refdiv_muxd4_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_biastop_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_biastopbypass_attr == SERDES_IP_LANE_L3_CFG_RXCDRVCO_BIASTOPBYPASS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_datapropgain_high_attr == 5'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_datapropgain_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_datapropgain_low_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_ff_ovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_ff_ovr_en_attr == SERDES_IP_LANE_L3_CFG_RXCDRVCO_FF_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_fil_short_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_flickerdegen_attr == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_gmfoscshort_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCDRVCO_GMFOSCSHORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_intf_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_intf_fil_short_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_intrj_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCDRVCO_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_refpropgain_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_refpropgain_nom_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxclk_cdrfb_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCLK_CDRFB_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxclk_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxclk_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdat_nrz_64b80b_bcword_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdata_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXDATA_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdata_locovren_attr == SERDES_IP_LANE_L3_CFG_RXDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdatapath_locovren_attr == SERDES_IP_LANE_L3_CFG_RXDATAPATH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdatapath_on_state_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdatapath_ready_locovr_attr == SERDES_IP_LANE_L3_CFG_RXDATAPATH_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdfe_datatap_vcasc_attr == 4'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdfe_dfebiasadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdfe_nbiasctle_en_attr == SERDES_IP_LANE_L3_CFG_RXDFE_NBIASCTLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdfe_vcasc_sel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdfeterm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXDFETERM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdfeterm_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdfeyadjdac_datamid_edge_coarse_en_attr == SERDES_IP_LANE_L3_CFG_RXDFEYADJDAC_DATAMID_EDGE_COARSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdfeyadjdac_datatopbot_aux_coarse_en_attr == SERDES_IP_LANE_L3_CFG_RXDFEYADJDAC_DATATOPBOT_AUX_COARSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_accum_mon_en_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_ACCUM_MON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_accum_mon_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_bypasscdrpdetupdnsmpl_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_bypassenfosc_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_BYPASSENFOSC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_bypassenints_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_BYPASSENINTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_bypassenupdnsmpl_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_BYPASSENUPDNSMPL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_bypassfosc_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_bypasspllpfdupdnsmpl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_bypassrxints_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_data2pll_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_deltasigmode_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_DELTASIGMODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_fastref_muxd0_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_FASTREF_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_fastref_muxd1_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_FASTREF_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_fastref_muxd2_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_FASTREF_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_fastref_muxd3_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_FASTREF_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_fastref_muxd4_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_FASTREF_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_fosc_mod_bypass_en_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_FOSC_MOD_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_fosc_sample_pedge_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_FOSC_SAMPLE_PEDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gain_step_on_lock_recovery_en_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_GAIN_STEP_ON_LOCK_RECOVERY_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gaindelaycount_init_attr == 9'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gaindelaycount_pow2_muxd0_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gaindelaycount_pow2_muxd1_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gaindelaycount_pow2_muxd2_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gaindelaycount_pow2_muxd3_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gaindelaycount_pow2_muxd4_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2ref_pow2_muxd0_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2ref_pow2_muxd1_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2ref_pow2_muxd2_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2ref_pow2_muxd3_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2ref_pow2_muxd4_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainunlocked_pow2_muxd0_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainunlocked_pow2_muxd1_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainunlocked_pow2_muxd2_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainunlocked_pow2_muxd3_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainunlocked_pow2_muxd4_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_initintegrator_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_INITINTEGRATOR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_initmodulator_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_INITMODULATOR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_deltasig_mode_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_INTS_DELTASIG_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_freeze_en_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_INTS_FREEZE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gaindelaycount_pow2_muxd0_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gaindelaycount_pow2_muxd1_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gaindelaycount_pow2_muxd2_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gaindelaycount_pow2_muxd3_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gaindelaycount_pow2_muxd4_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd0_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd1_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd2_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd3_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd4_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd0_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd1_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd2_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd3_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd4_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainunlocked_pow2_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainunlocked_pow2_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainunlocked_pow2_muxd2_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainunlocked_pow2_muxd3_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainunlocked_pow2_muxd4_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_guardband_hi_attr == 8'd200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_guardband_lo_attr == 8'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_loop_sel_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_INTS_LOOP_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_mod_bypass_en_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_INTS_MOD_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_mod_load_pedge_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_INTS_MOD_LOAD_PEDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_step_to_integer_en_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_INTS_STEP_TO_INTEGER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_jit_length_attr == 18'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_jit_mode_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_JIT_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_modck_ctrl_en_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_MODCK_CTRL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_pll2data_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_restore_cntr_attr == 9'd258
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_store_cntr_attr == 16'd258
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpif_trnsfrdelay_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpiffreeze_inten_attr == SERDES_IP_LANE_L3_CFG_RXDPIFFREEZE_INTEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdpiffreeze_moden_attr == SERDES_IP_LANE_L3_CFG_RXDPIFFREEZE_MODEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxdutyselpolarity_attr == SERDES_IP_LANE_L3_CFG_RXDUTYSELPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxflxgate_force_rxeq_gate_locovr_attr == SERDES_IP_LANE_L3_CFG_RXFLXGATE_FORCE_RXEQ_GATE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxflxgate_locovren_attr == SERDES_IP_LANE_L3_CFG_RXFLXGATE_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxfoscstat_done_locovr_attr == SERDES_IP_LANE_L3_CFG_RXFOSCSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxfoscstat_locovren_attr == SERDES_IP_LANE_L3_CFG_RXFOSCSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxfsm_cken_ovr_attr == SERDES_IP_LANE_L3_CFG_RXFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxfsm_cken_ovren_attr == SERDES_IP_LANE_L3_CFG_RXFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxints_prev_votes_hold_en_attr == SERDES_IP_LANE_L3_CFG_RXINTS_PREV_VOTES_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxlanepam_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXLANEPAM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxlanepam_locovren_attr == SERDES_IP_LANE_L3_CFG_RXLANEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxlock2datatmr_attr == 8'd240
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxlock2datatmr_short_attr == 8'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxntl_changeref_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxntl_changeref_val_locovr_attr == SERDES_IP_LANE_L3_CFG_RXNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxntl_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxntl_en_attr == SERDES_IP_LANE_L3_CFG_RXNTL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxntl_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxntl_locovren_attr == SERDES_IP_LANE_L3_CFG_RXNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxntl_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxntl_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxntl_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxntl_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxntl_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxntl_rxm_charge_up_locovr_attr == SERDES_IP_LANE_L3_CFG_RXNTL_RXM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxntl_rxm_pull_dn_locovr_attr == SERDES_IP_LANE_L3_CFG_RXNTL_RXM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxntl_rxm_sense_locovr_attr == SERDES_IP_LANE_L3_CFG_RXNTL_RXM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxntl_rxp_charge_up_locovr_attr == SERDES_IP_LANE_L3_CFG_RXNTL_RXP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxntl_rxp_pull_dn_locovr_attr == SERDES_IP_LANE_L3_CFG_RXNTL_RXP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxntl_rxp_sense_locovr_attr == SERDES_IP_LANE_L3_CFG_RXNTL_RXP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxntl_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_acc_freeze_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_ACC_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_cdrlock2data_gater_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_cdrlock2data_gater_hold_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_cdrlock2data_gater_ovrd_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_cdrlock2datatmr_optcl_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_cdrlock2datatmr_optcl_sel_ovrd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_enter_lock2data_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_ENTER_LOCK2DATA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_enter_lock2data_hold_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_ENTER_LOCK2DATA_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_exit_lock2data_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_EXIT_LOCK2DATA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_exit_lock2data_hold_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_EXIT_LOCK2DATA_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_force_lock2data_ovrd_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_FORCE_LOCK2DATA_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_force_lock2ref_ovrd_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_FORCE_LOCK2REF_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_hold_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_hold_timer_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_intf_ovrd_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_INTF_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_intf_ovrd_type_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_INTF_OVRD_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_mod_freeze_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_MOD_FREEZE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_ovrd_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_ppm_detect_freeze_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_PPM_DETECT_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_ppm_detect_freeze_ovrd_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_PPM_DETECT_FREEZE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_ppm_detect_hold_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_PPM_DETECT_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_prop_freeze_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_PROP_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_prop_freeze_ovrd_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_PROP_FREEZE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_rxdata_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_RXDATA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_skip_init_lock2data_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_SKIP_INIT_LOCK2DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxpam_bitorder_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxpam_gray_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXPAM_GRAY_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxpam_locovren_attr == SERDES_IP_LANE_L3_CFG_RXPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxpam_precode_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXPAM_PRECODE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_p5_muxd0_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIV_P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_p5_muxd1_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIV_P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_p5_muxd2_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIV_P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_p5_muxd3_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIV_P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_p5_muxd4_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIV_P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdivclken_muxd0_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIVCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdivclken_muxd1_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIVCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdivclken_muxd2_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIVCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdivclken_muxd3_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIVCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdivclken_muxd4_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIVCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxpcsbist_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXPCSBIST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxpcsbist_locovren_attr == SERDES_IP_LANE_L3_CFG_RXPCSBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxphd_gain_hold_en_attr == SERDES_IP_LANE_L3_CFG_RXPHD_GAIN_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxphd_gain_zero_locovr_attr == SERDES_IP_LANE_L3_CFG_RXPHD_GAIN_ZERO_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxphd_locovren_attr == SERDES_IP_LANE_L3_CFG_RXPHD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxphd_majvote_basegain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxphd_majvote_en_attr == SERDES_IP_LANE_L3_CFG_RXPHD_MAJVOTE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxphd_mute_cntr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxphd_nrz8b10b_pam16b20b_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxphd_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxphd_pam_transition_sel_attr == SERDES_IP_LANE_L3_CFG_RXPHD_PAM_TRANSITION_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxphd_sign_invert_attr == SERDES_IP_LANE_L3_CFG_RXPHD_SIGN_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxpostdiv_wait_for_lock_disable_attr == SERDES_IP_LANE_L3_CFG_RXPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxppm_freq_max_offset_h_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxppm_freq_max_offset_l_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxppm_freq_ref_cnt_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxppm_lockstatus_locovr_attr == SERDES_IP_LANE_L3_CFG_RXPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxppm_lockstatus_synthlcfast_en_attr == SERDES_IP_LANE_L3_CFG_RXPPM_LOCKSTATUS_SYNTHLCFAST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxppm_lockstatus_synthlcmed_en_attr == SERDES_IP_LANE_L3_CFG_RXPPM_LOCKSTATUS_SYNTHLCMED_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxppm_lockstatus_synthlcslow_en_attr == SERDES_IP_LANE_L3_CFG_RXPPM_LOCKSTATUS_SYNTHLCSLOW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxppm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxppm_ppmdriftcount_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxppm_ppmdriftmax_attr == 16'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxppm_status_hold_attr == SERDES_IP_LANE_L3_CFG_RXPPM_STATUS_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxppm_unlock_clear_attr == SERDES_IP_LANE_L3_CFG_RXPPM_UNLOCK_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_fast_muxd0_attr == 16'd666
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_fast_muxd1_attr == 16'd4000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_fast_muxd2_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_fast_muxd3_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_fast_muxd4_attr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_muxd0_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_muxd1_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_muxd2_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_muxd3_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_muxd4_attr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxppmctrl_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXPPMCTRL_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxppmctrl_locovren_attr == SERDES_IP_LANE_L3_CFG_RXPPMCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxppmlockstat_locovren_attr == SERDES_IP_LANE_L3_CFG_RXPPMLOCKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxppmlockstat_sticky_locovr_attr == SERDES_IP_LANE_L3_CFG_RXPPMLOCKSTAT_STICKY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxppmtmr_locovren_attr == SERDES_IP_LANE_L3_CFG_RXPPMTMR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxppmtmr_watchdogtmr_sel_locovr_attr == SERDES_IP_LANE_L3_CFG_RXPPMTMR_WATCHDOGTMR_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_cal_clear_delay_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_clk_chk_disable_attr == SERDES_IP_LANE_L3_CFG_RXRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_clk_delay_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_etr_on_delay_attr == 12'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_locovren_attr == SERDES_IP_LANE_L3_CFG_RXRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxreg_lev_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxreg_toggle_reset_on_rate_change_en_attr == SERDES_IP_LANE_L3_CFG_RXREG_TOGGLE_RESET_ON_RATE_CHANGE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxreg_vreg_bypass_attr == SERDES_IP_LANE_L3_CFG_RXREG_VREG_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_en_b_attr == SERDES_IP_LANE_L3_CFG_RXRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s0q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s0q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s2q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s2q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s2q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s2q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s2q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s2q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s2q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s3q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s3q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s3q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s3q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s3q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s3q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s3q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s3q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s4q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s4q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s5q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_entry2_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_entry4_attr == 13'd78
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_entry5_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_entry6_attr == 13'd1406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s0q2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s0q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s1q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s1q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s1q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s1q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s1q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s1q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s2q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s2q2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s2q3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s2q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s2q5_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s2q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s2q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s3q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s3q1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s3q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s3q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s3q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s3q5_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s3q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s3q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s4q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s4q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s5q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_aetrrx_cdrfbdivcken_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_AETRRX_CDRFBDIVCKEN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_aetrrx_cdrfbdivcken_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_AETRRX_CDRFBDIVCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_aetrrx_cdrmoddivcken_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_AETRRX_CDRMODDIVCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_aetrrx_cdrmoddivcken_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_AETRRX_CDRMODDIVCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_aetrrx_termhiz_en_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_AETRRX_TERMHIZ_EN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_aetrrx_termhiz_en_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_AETRRX_TERMHIZ_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_aetrsynth_pcspostdivclksel_ovr_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_AETRSYNTH_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_aetrsynth_pcspostdivclksel_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_AETRSYNTH_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_adc_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_adc_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_auxcomp_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_AUXCOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_auxcomp_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_AUXCOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_bias_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_bias_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_BIAS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_ctlecomp_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_CTLECOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_ctlecomp_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_CTLECOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_datfbdiv_b_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DATFBDIV_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_datfbdiv_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DATFBDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_dfe_bias_b_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DFE_BIAS_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_dfe_bias_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DFE_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_dfe_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DFE_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_dfe_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DFE_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_dfe_yadj_b_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DFE_YADJ_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_dfe_yadj_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DFE_YADJ_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_duty_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DUTY_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_duty_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DUTY_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_hifreqagc_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_HIFREQAGC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_hifreqagc_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_HIFREQAGC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_ntl_b_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_ntl_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_reg_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_reg_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_vco_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_VCO_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_vco_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_VCO_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_voscreg_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_VOSCREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_voscreg_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_VOSCREG_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_adc_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_adc_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_cdrfbdiv_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_CDRFBDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_cdrfbdiv_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_CDRFBDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_pdet_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_PDET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_pdet_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_PDET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_pfd_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_PFD_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_pfd_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_PFD_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_refdiv_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_refdiv_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_reg_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_reg_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_s2pa_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_S2PA_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_s2pa_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_S2PA_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_s2pb_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_S2PB_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_s2pb_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_S2PB_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_vco_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_VCO_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_vco_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_VCO_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_voscreg_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_VOSCREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_voscreg_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_VOSCREG_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstsynth_postdiv_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTSYNTH_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstsynth_postdiv_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTSYNTH_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_drstrx_dpif_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_DRSTRX_DPIF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_drstrx_dpif_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_DRSTRX_DPIF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_drstrx_ppm_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_DRSTRX_PPM_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_drstrx_ppm_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_DRSTRX_PPM_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_cdrlock2data_locovr_attr == SERDES_IP_LANE_L3_CFG_RXSIGDET_CDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_diglfpsdeten_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_diglfpsdeten_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_diglfpsdeten_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_diglfpsdeten_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_diglfpsdeten_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrancnten_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrancnten_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrancnten_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrancnten_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrancnten_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrancnten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrandeten_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrandeten_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrandeten_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrandeten_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrandeten_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrandeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_eiosdeten_muxd0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_eiosdeten_muxd1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_eiosdeten_muxd2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_eiosdeten_muxd3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_eiosdeten_muxd4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_eiosdeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_enable_attr == SERDES_IP_LANE_L3_CFG_RXSIGDET_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_fastlock_winsize_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_leveldeten_muxd0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_leveldeten_muxd1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_leveldeten_muxd2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_leveldeten_muxd3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_leveldeten_muxd4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_leveldeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_lfpsexit_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_locovren_attr == SERDES_IP_LANE_L3_CFG_RXSIGDET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_ppmdeten_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_ppmdeten_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_ppmdeten_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_ppmdeten_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_ppmdeten_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_ppmdeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_rxeq_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_rxeqen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_rxeqen_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_rxleveldet_debounce_dncount_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_rxleveldet_debounce_flush_en_attr == SERDES_IP_LANE_L3_CFG_RXSIGDET_RXLEVELDET_DEBOUNCE_FLUSH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_rxleveldet_debounce_upcount_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_sigdet_debounce_attr == SERDES_IP_LANE_L3_CFG_RXSIGDET_SIGDET_DEBOUNCE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_tmr_clksel_attr == SERDES_IP_LANE_L3_CFG_RXSIGDET_TMR_CLKSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_toggle_count_en_attr == SERDES_IP_LANE_L3_CFG_RXSIGDET_TOGGLE_COUNT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_toggle_count_pause_attr == SERDES_IP_LANE_L3_CFG_RXSIGDET_TOGGLE_COUNT_PAUSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_toggle_monitor_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdetin_eiosdetectstat_locovr_attr == SERDES_IP_LANE_L3_CFG_RXSIGDETIN_EIOSDETECTSTAT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdetin_locovren_attr == SERDES_IP_LANE_L3_CFG_RXSIGDETIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdetin_ovrcdrlock2data_locovr_attr == SERDES_IP_LANE_L3_CFG_RXSIGDETIN_OVRCDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdetin_ovrencdrlock2data_locovr_attr == SERDES_IP_LANE_L3_CFG_RXSIGDETIN_OVRENCDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdetout_lock2data_noforce_ltr_locovr_attr == SERDES_IP_LANE_L3_CFG_RXSIGDETOUT_LOCK2DATA_NOFORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsigdetout_locovren_attr == SERDES_IP_LANE_L3_CFG_RXSIGDETOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxspare0_attr == 32'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxspare_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsqlchlfps_consec_one_thresh_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsqlchlfps_consec_zero_thresh_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsqlchlfps_cycle_thresh_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsqlchlfps_dat_bitorder_attr == SERDES_IP_LANE_L3_CFG_RXSQLCHLFPS_DAT_BITORDER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsqlchlfps_debounce_type_attr == SERDES_IP_LANE_L3_CFG_RXSQLCHLFPS_DEBOUNCE_TYPE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsqlchlfps_one_run_length_thresh_attr == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsqlchlfps_one_run_length_timeout_attr == 8'd103
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsqlchlfps_zero_run_length_thresh_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsqlchlfps_zero_run_length_timeout_attr == 8'd103
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsynthdiv_slowmed_en_muxd0_attr == SERDES_IP_LANE_L3_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsynthdiv_slowmed_en_muxd1_attr == SERDES_IP_LANE_L3_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsynthdiv_slowmed_en_muxd2_attr == SERDES_IP_LANE_L3_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsynthdiv_slowmed_en_muxd3_attr == SERDES_IP_LANE_L3_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxsynthdiv_slowmed_en_muxd4_attr == SERDES_IP_LANE_L3_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxterm_cal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxterm_coarse_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxterm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXTERM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxterm_modeselect_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxtermhiz_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXTERMHIZ_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxtermhiz_locovren_attr == SERDES_IP_LANE_L3_CFG_RXTERMHIZ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxvoscreg_bypass_vosc_attr == SERDES_IP_LANE_L3_CFG_RXVOSCREG_BYPASS_VOSC_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxvoscregopampoffsetctrl_sel_attr == SERDES_IP_LANE_L3_CFG_RXVOSCREGOPAMPOFFSETCTRL_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxvoscregopampoffseterr_locovren_attr == SERDES_IP_LANE_L3_CFG_RXVOSCREGOPAMPOFFSETERR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxvoscregopampoffseterr_sel_locovr_attr == SERDES_IP_LANE_L3_CFG_RXVOSCREGOPAMPOFFSETERR_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxvoscregvref_locovren_attr == SERDES_IP_LANE_L3_CFG_RXVOSCREGVREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_rxvoscregvref_sel_locovr_attr == SERDES_IP_LANE_L3_CFG_RXVOSCREGVREF_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlch_acqgain_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlch_acqtime_attr == 13'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlch_cal_quiet_locovr_attr == SERDES_IP_LANE_L3_CFG_SQLCH_CAL_QUIET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlch_cal_sel_locovr_attr == SERDES_IP_LANE_L3_CFG_SQLCH_CAL_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlch_calctrl_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlch_calen_locovr_attr == SERDES_IP_LANE_L3_CFG_SQLCH_CALEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlch_caltimer_attr == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlch_clkgate_locovr_attr == SERDES_IP_LANE_L3_CFG_SQLCH_CLKGATE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlch_cmshiften_attr == SERDES_IP_LANE_L3_CFG_SQLCH_CMSHIFTEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_acq_gain_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_acq_pct_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_cal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_clr_errlog_attr == SERDES_IP_LANE_L3_CFG_SQLCH_CONT_CLR_ERRLOG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_controller_mode_attr == SERDES_IP_LANE_L3_CFG_SQLCH_CONT_CONTROLLER_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_dis_attr == SERDES_IP_LANE_L3_CFG_SQLCH_CONT_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_pause_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_postcal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_precal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_quiet_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlch_lfps_en_attr == SERDES_IP_LANE_L3_CFG_SQLCH_LFPS_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlch_locovren_attr == SERDES_IP_LANE_L3_CFG_SQLCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlch_ovrd_val_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlch_pkdet_freqsel_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlch_polarity_attr == SERDES_IP_LANE_L3_CFG_SQLCH_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlch_rdacen_attr == SERDES_IP_LANE_L3_CFG_SQLCH_RDACEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlch_thresh_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlch_time_out_attr == 16'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlch_vrefsel0_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlch_vrefsel1_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlch_vrefsel_ovr_en_attr == SERDES_IP_LANE_L3_CFG_SQLCH_VREFSEL_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlchdeb_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlchdeb_deb_cnt_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlchdeb_deb_status_cnt_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlchdeb_en_attr == SERDES_IP_LANE_L3_CFG_SQLCHDEB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlchdeb_ign_cnt_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlchdeb_sigdet_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlchdeb_thresh_cnt_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlchdebout_exit_good_debounced_locovr_attr == SERDES_IP_LANE_L3_CFG_SQLCHDEBOUT_EXIT_GOOD_DEBOUNCED_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlchdebout_exit_good_debounced_status_locovr_attr == SERDES_IP_LANE_L3_CFG_SQLCHDEBOUT_EXIT_GOOD_DEBOUNCED_STATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlchdebout_exit_good_locovr_attr == SERDES_IP_LANE_L3_CFG_SQLCHDEBOUT_EXIT_GOOD_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_sqlchdebout_locovren_attr == SERDES_IP_LANE_L3_CFG_SQLCHDEBOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_trancnt_off_attr == 10'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_trancnt_on_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_trancntout_det_locovr_attr == SERDES_IP_LANE_L3_CFG_TRANCNTOUT_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_trancntout_locovren_attr == SERDES_IP_LANE_L3_CFG_TRANCNTOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_trandet_ax_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_trandet_ay_attr == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_trandet_off_h_attr == 6'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_trandet_off_l_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_trandet_on_h_attr == 6'd39
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_trandet_on_l_attr == 6'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_trandetout_det_locovr_attr == SERDES_IP_LANE_L3_CFG_TRANDETOUT_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_trandetout_locovren_attr == SERDES_IP_LANE_L3_CFG_TRANDETOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_tx2rxlb_en_attr == SERDES_IP_LANE_L3_CFG_TX2RXLB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_tx2rxlb_init_offset_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_tx_cmn_on_state_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_tx_fastregpwrup_en_attr == SERDES_IP_LANE_L3_CFG_TX_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_tx_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_tx_pg_disable_attr == SERDES_IP_LANE_L3_CFG_TX_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_tx_synth_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_tx_synth_sel_amode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_tx_synth_sel_bmode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_tx_synth_sel_cmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_tx_synth_sel_dmode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_tx_synth_sel_emode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_tx_txdetrx_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txadc_req_attr == SERDES_IP_LANE_L3_CFG_TXADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txaprobe_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txaprobe_lastmux_isolate_attr == SERDES_IP_LANE_L3_CFG_TXAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txaprobeadc_current_direction_attr == SERDES_IP_LANE_L3_CFG_TXAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txaprobeadc_resistor_enable_attr == SERDES_IP_LANE_L3_CFG_TXAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txbdvdr_pma2pcstxworden_attr == SERDES_IP_LANE_L3_CFG_TXBDVDR_PMA2PCSTXWORDEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txbeacon_div_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txbeacon_sel_attr == SERDES_IP_LANE_L3_CFG_TXBEACON_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txbias_icc20uadj_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txbias_icc80uadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txbias_locovren_attr == SERDES_IP_LANE_L3_CFG_TXBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txbias_termcal_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txbist_biterror_en_attr == SERDES_IP_LANE_L3_CFG_TXBIST_BITERROR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txbist_locovren_attr == SERDES_IP_LANE_L3_CFG_TXBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txbist_modesel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txbist_oobmode_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txbist_oobtburst_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txbist_oobtcomrstinit_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txbist_oobtcomsas_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txbist_oobtcomwake_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txbist_seed_attr == 31'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_size_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf00_attr == 32'd1985229328
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf01_attr == 32'd4275878552
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf02_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf03_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf04_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf05_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf06_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf07_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf08_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf09_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txbit_select_muxd0_attr == SERDES_IP_LANE_L3_CFG_TXBIT_SELECT_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txbit_select_muxd1_attr == SERDES_IP_LANE_L3_CFG_TXBIT_SELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txbit_select_muxd2_attr == SERDES_IP_LANE_L3_CFG_TXBIT_SELECT_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txbit_select_muxd3_attr == SERDES_IP_LANE_L3_CFG_TXBIT_SELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txbit_select_muxd4_attr == SERDES_IP_LANE_L3_CFG_TXBIT_SELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txbti_data_replication_attr == SERDES_IP_LANE_L3_CFG_TXBTI_DATA_REPLICATION_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txbti_tx_idle_data_en_attr == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcal_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcal_tclkduty_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalduty_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalduty_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTY_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalduty_sel_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutybg_abort_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutybg_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutybg_ready_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutycomp_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutycomp_offset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_finish_side_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_init_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_initval_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_invert_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_req_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_round_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_runcount_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_signmagen_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsmout_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsmout_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompmeas_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompmeas_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompmeas_req_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompmeasout_ack_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPMEASOUT_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompmeasout_erravg_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPMEASOUT_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompmeasout_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_bg_en_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_bg_one_step_cal_en_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_finish_side_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_init_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_invert_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_req_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_round_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_runcount_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_signmagen_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeas_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeas_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeas_req_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeasout_ack_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYMEASOUT_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeasout_erravg_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYMEASOUT_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeasout_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutystat_done_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaldutystat_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalptr_pstate_duty_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalptr_pstate_dutycomp_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalptr_pstate_regopampoffset_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_duty_muxd0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_duty_muxd1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_duty_muxd2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_duty_muxd3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_duty_muxd4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_dutycomp_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_dutycomp_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_dutycomp_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_dutycomp_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_dutycomp_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_regopampoffset_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffset_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_finish_side_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_round_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_runcount_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_signmagen_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcaltclkdutyforce_div1_attr == SERDES_IP_LANE_L3_CFG_TXCALTCLKDUTYFORCE_DIV1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txcdrdiv_local_en_attr == SERDES_IP_LANE_L3_CFG_TXCDRDIV_LOCAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txclk_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txclk_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txclkgenmuxsel_txinternal_attr == SERDES_IP_LANE_L3_CFG_TXCLKGENMUXSEL_TXINTERNAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txdetectrx_thr_attr == 5'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeas_count_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeas_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXDETECTRXMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeas_locovren_attr == SERDES_IP_LANE_L3_CFG_TXDETECTRXMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeas_validdlycount_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeasin_locovren_attr == SERDES_IP_LANE_L3_CFG_TXDETECTRXMEASIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeasin_start_locovr_attr == SERDES_IP_LANE_L3_CFG_TXDETECTRXMEASIN_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeaspcs_locovren_attr == SERDES_IP_LANE_L3_CFG_TXDETECTRXMEASPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeaspcs_req_locovr_attr == SERDES_IP_LANE_L3_CFG_TXDETECTRXMEASPCS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeasval_locovren_attr == SERDES_IP_LANE_L3_CFG_TXDETECTRXMEASVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeasval_stat_locovr_attr == SERDES_IP_LANE_L3_CFG_TXDETECTRXMEASVAL_STAT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txdetrx_levn_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txdetrx_levnm1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txdetrx_levnp1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txdetrx_levnp2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txdrv_hizen_locovr_attr == SERDES_IP_LANE_L3_CFG_TXDRV_HIZEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txdrv_levn_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txdrv_levnm1_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txdrv_levnp1_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txdrv_levnp2_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txdrv_locovren_attr == SERDES_IP_LANE_L3_CFG_TXDRV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txdrv_refcken_attr == SERDES_IP_LANE_L3_CFG_TXDRV_REFCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txdrv_termref_attr == SERDES_IP_LANE_L3_CFG_TXDRV_TERMREF_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txdrvmute_locovr_attr == SERDES_IP_LANE_L3_CFG_TXDRVMUTE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txdrvmute_locovren_attr == SERDES_IP_LANE_L3_CFG_TXDRVMUTE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txduty_ctrl_disable_attr == SERDES_IP_LANE_L3_CFG_TXDUTY_CTRL_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txduty_pad_sense_en_attr == SERDES_IP_LANE_L3_CFG_TXDUTY_PAD_SENSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txdutycal_div16_en_attr == SERDES_IP_LANE_L3_CFG_TXDUTYCAL_DIV16_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txdutycal_div1_en_attr == SERDES_IP_LANE_L3_CFG_TXDUTYCAL_DIV1_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txdutycal_div2_en_attr == SERDES_IP_LANE_L3_CFG_TXDUTYCAL_DIV2_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txdutycal_div4_en_attr == SERDES_IP_LANE_L3_CFG_TXDUTYCAL_DIV4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txdutycal_div8_en_attr == SERDES_IP_LANE_L3_CFG_TXDUTYCAL_DIV8_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txfifo_elecidle_deskew_en_attr == SERDES_IP_LANE_L3_CFG_TXFIFO_ELECIDLE_DESKEW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txfifo_force_txidlebit1_zero_disable_attr == SERDES_IP_LANE_L3_CFG_TXFIFO_FORCE_TXIDLEBIT1_ZERO_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txfifo_kill_dly_10b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txfifo_kill_dly_16b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txfifo_kill_dly_20b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txfifo_kill_dly_32b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txfifo_kill_dly_40b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txfifo_kill_dly_64b_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txfifo_kill_dly_80b_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txfifo_kill_dly_8b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txfifo_kill_en_attr == SERDES_IP_LANE_L3_CFG_TXFIFO_KILL_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txfsm_cken_ovr_attr == SERDES_IP_LANE_L3_CFG_TXFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txfsm_cken_ovren_attr == SERDES_IP_LANE_L3_CFG_TXFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txfsm_main_on_state_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txl1d1_doze_ctrl_attr == SERDES_IP_LANE_L3_CFG_TXL1D1_DOZE_CTRL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txl1d1_txbias_ctrl_attr == SERDES_IP_LANE_L3_CFG_TXL1D1_TXBIAS_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txlanepam_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXLANEPAM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txlanepam_locovren_attr == SERDES_IP_LANE_L3_CFG_TXLANEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txmeaslatovrhd_meas_sel_attr == SERDES_IP_LANE_L3_CFG_TXMEASLATOVRHD_MEAS_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txmute_delay_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txntl_changeref_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txntl_changeref_val_locovr_attr == SERDES_IP_LANE_L3_CFG_TXNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txntl_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txntl_en_attr == SERDES_IP_LANE_L3_CFG_TXNTL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txntl_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txntl_locovren_attr == SERDES_IP_LANE_L3_CFG_TXNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txntl_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txntl_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txntl_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txntl_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txntl_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txntl_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txntl_txm_charge_up_locovr_attr == SERDES_IP_LANE_L3_CFG_TXNTL_TXM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txntl_txm_pull_dn_locovr_attr == SERDES_IP_LANE_L3_CFG_TXNTL_TXM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txntl_txm_sense_locovr_attr == SERDES_IP_LANE_L3_CFG_TXNTL_TXM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txntl_txp_charge_up_locovr_attr == SERDES_IP_LANE_L3_CFG_TXNTL_TXP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txntl_txp_pull_dn_locovr_attr == SERDES_IP_LANE_L3_CFG_TXNTL_TXP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txntl_txp_sense_locovr_attr == SERDES_IP_LANE_L3_CFG_TXNTL_TXP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txp2s_txwordsyncbypen_attr == SERDES_IP_LANE_L3_CFG_TXP2S_TXWORDSYNCBYPEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txpam_bitorder_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txpam_gray_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXPAM_GRAY_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txpam_locovren_attr == SERDES_IP_LANE_L3_CFG_TXPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txpam_precode_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXPAM_PRECODE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txpcs_locovren_attr == SERDES_IP_LANE_L3_CFG_TXPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txpcs_txenable_locovr_attr == SERDES_IP_LANE_L3_CFG_TXPCS_TXENABLE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txpcsbist_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXPCSBIST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txpcsbist_locovren_attr == SERDES_IP_LANE_L3_CFG_TXPCSBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txratewidth_clk_chk_disable_attr == SERDES_IP_LANE_L3_CFG_TXRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txratewidth_etr_on_delay_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txratewidth_locovren_attr == SERDES_IP_LANE_L3_CFG_TXRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txreg_toggle_pwrupacc_on_rate_change_en_attr == SERDES_IP_LANE_L3_CFG_TXREG_TOGGLE_PWRUPACC_ON_RATE_CHANGE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txreg_toggle_reset_on_rate_change_en_attr == SERDES_IP_LANE_L3_CFG_TXREG_TOGGLE_RESET_ON_RATE_CHANGE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txresetdel_sel_attr == SERDES_IP_LANE_L3_CFG_TXRESETDEL_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_en_b_attr == SERDES_IP_LANE_L3_CFG_TXRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s0q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s0q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s1q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s1q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s2q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s2q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s2q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s2q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s2q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s2q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s2q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s3q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s3q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s3q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s3q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s3q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s3q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s3q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s3q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s4q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s4q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s5q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_entry2_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s0q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s0q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s1q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s1q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s1q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s1q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s1q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s1q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s2q0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s2q1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s2q2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s2q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s2q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s2q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s2q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s2q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s3q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s3q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s3q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s3q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s3q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s3q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s3q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s3q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s4q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s4q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s5q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_dn_ptr0_s_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_up_ptr0_s_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_aetrtx_bitckdvdrcken_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_AETRTX_BITCKDVDRCKEN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_aetrtx_bitckdvdrcken_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_AETRTX_BITCKDVDRCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_aetrtx_regpwrupacc_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_AETRTX_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_aetrtx_regpwrupacc_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_AETRTX_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_adc_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_adc_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_drvdoze_b_ovr_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_DRVDOZE_B_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_drvdoze_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_DRVDOZE_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_duty_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_DUTY_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_duty_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_DUTY_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_ntl_b_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_ntl_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_p2s_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_P2S_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_p2s_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_P2S_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_reg_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_reg_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_arsttx_adc_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_ARSTTX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_arsttx_adc_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_ARSTTX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_arsttx_pma2pcstxword_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_ARSTTX_PMA2PCSTXWORD_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_arsttx_pma2pcstxword_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_ARSTTX_PMA2PCSTXWORD_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_arsttx_regreset_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_ARSTTX_REGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_arsttx_regreset_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_ARSTTX_REGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_arsttx_txdetectrx_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_ARSTTX_TXDETECTRX_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_arsttx_txdetectrx_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_ARSTTX_TXDETECTRX_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txrststate_hiz_en_attr == SERDES_IP_LANE_L3_CFG_TXRSTSTATE_HIZ_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txspare0_attr == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txspare_attr == 10'd384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txterm_coarse_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txtermtrim_locovren_attr == SERDES_IP_LANE_L3_CFG_TXTERMTRIM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txtermtrim_nmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txtermtrim_pmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txwclk_div_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txwclk_div_en_attr == SERDES_IP_LANE_L3_CFG_TXWCLK_DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txwclk_div_smpl_attr == SERDES_IP_LANE_L3_CFG_TXWCLK_DIV_SMPL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txwptr_init01_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txwptr_init02_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txwptr_init04_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txwptr_init08_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txwptr_init16_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txwptr_init32_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_l3_cfg_txwptr_init_rx2txparlb_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_dfeyadj_aging_cdrlock2data_loc_ov_attr == SERDES_IP_LANE_RXEQ_L0_CFG_DFEYADJ_AGING_CDRLOCK2DATA_LOC_OV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_dfeyadj_aging_cdrlock2data_loc_ov_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_DFEYADJ_AGING_CDRLOCK2DATA_LOC_OV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_dfeyadj_aging_div_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_dfeyadj_aging_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_DFEYADJ_AGING_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxagc_ctlecomp_filterbypass_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXAGC_CTLECOMP_FILTERBYPASS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxagc_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXAGC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxbgcal_calfsmmeas_dlycount_attr == 10'd392
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxbgcal_clear_mask_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxbgcal_fsmmaxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxbgcal_lpfax_coarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxbgcal_lpfax_fine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxbgcalorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxbgcalorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxbgcalorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_calbiasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_calbiasboost_use_lut_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_CALBIASBOOST_USE_LUT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_callbbiasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_callbbiasboost_use_lut_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_CALLBBIASBOOST_USE_LUT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlecomp_filterbypass_smplrcal_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_CTLECOMP_FILTERBYPASS_SMPLRCAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg1_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg2_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg3_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctleinput_probe_mux_smplrcal_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg1_probe_mux_en_smplrcal_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg1_state_en_smplrcal_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg1_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg1_state_en_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg1_state_en_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg1_use_stg2code_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_CTLESTG1_USE_STG2CODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg2_probe_mux_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg2_state_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg2_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg2_state_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg2_state_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg3_probe_mux_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg3_state_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg3_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg3_state_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg3_state_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_hifreqagc_n5targin_sel_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_HIFREQAGC_N5TARGIN_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_inputcmadjust_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_inputcmadjust_stg1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_inputcmadjust_stg2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_inputcmadjust_stg3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_sdimode_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_SDIMODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_smplroffset_aux0_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_smplroffset_aux1_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_smplroffset_d0_bot_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_smplroffset_d0_mid_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_smplroffset_d0_top_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_smplroffset_d1_bot_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_smplroffset_d1_mid_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_smplroffset_d1_top_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_tfrtrim_outen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_tfrtrim_outen_tfrcal_stg1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_tfrtrim_outen_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_tfrtrim_outen_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalalign_iqclk_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalalign_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALALIGN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctl_cal_abort_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALCTL_CAL_ABORT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctl_cal_type_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctl_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALCTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctl_post_delay_pow2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctl_pre_delay_pow2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecalctrl_input_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecalctrl_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALCTLECALCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecalctrl_stg1_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecalctrl_stg1_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecalctrl_stg2_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecalctrl_stg2_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecalctrl_stg3_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecalctrl_stg3_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecompoffset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecompoffset_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALCTLECOMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecompoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALCTLECOMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecompoffsetfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALCTLECOMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecompoffsetfsmout_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaldutybkgnd_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALDUTYBKGND_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaldutybkgnd_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALDUTYBKGND_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_biasboost_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_hf1deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_hf1resdcgain_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_hf2cap_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_hf2deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_hf2reszero_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_hf3deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_hf3resdcgain_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_hf4deq_gray_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALEQ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_ctlecmnmode_stg1_finish_side_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALFSM_CTLECMNMODE_STG1_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_ctlecmnmode_stg1_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_ctlecmnmode_stg2_finish_side_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALFSM_CTLECMNMODE_STG2_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_ctlecmnmode_stg2_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_ctlecmnmode_stg3_finish_side_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALFSM_CTLECMNMODE_STG3_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_ctlecmnmode_stg3_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_runcount_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_smplroffset_finish_side_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALFSM_SMPLROFFSET_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_smplroffset_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsmmeas_ctlecmnmode_stg1_invert_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALFSMMEAS_CTLECMNMODE_STG1_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsmmeas_ctlecmnmode_stg2_invert_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALFSMMEAS_CTLECMNMODE_STG2_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsmmeas_ctlecmnmode_stg3_invert_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALFSMMEAS_CTLECMNMODE_STG3_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsmmeas_smplroffset_invert_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALFSMMEAS_SMPLROFFSET_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_ctlecmnmode_stg1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_ctlecmnmode_stg2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_ctlecmnmode_stg3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_aux0_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_aux1_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_d0_bot_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_d0_mid_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_d0_top_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_d1_bot_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_d1_mid_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_d1_top_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_e0_lo_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_e1_lo_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeas_pow2count_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasin_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasin_req_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASIN_REQ_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasin_req_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASIN_REQ_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasin_req_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASIN_REQ_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasout_ack_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASOUT_ACK_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasout_ack_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASOUT_ACK_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasout_ack_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASOUT_ACK_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasout_avg_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASOUT_AVG_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasout_avg_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASOUT_AVG_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasout_avg_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASOUT_AVG_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasout_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaloffsetfsmout_auxdatacomp_offset_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALOFFSETFSMOUT_AUXDATACOMP_OFFSET_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaloffsetfsmout_boost_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALOFFSETFSMOUT_BOOST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaloffsetfsmout_edgecomp_offset_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALOFFSETFSMOUT_EDGECOMP_OFFSET_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaloffsetfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalset_cal_clear_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalset_cal_mode_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALSET_CAL_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalset_cal_req_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALSET_CAL_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalset_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalstat_cal_ack_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALSTAT_CAL_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalstat_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalsummerfsmout_comp_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALSUMMERFSMOUT_COMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalsummerfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALSUMMERFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcdrphd_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCDRPHD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcdrphd_override_ignore_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCDRPHD_OVERRIDE_IGNORE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_caloffset_range_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_calstg1offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_calstg1offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_calstg2offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_calstg2offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_calstg3offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_calstg3offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_dccouple_sigpath_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCTLE_DCCOUPLE_SIGPATH_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_lbbiasboost_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCTLE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_stg1tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_stg2tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_stg3tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_tfrtrim_outmem_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCTLE_TFRTRIM_OUTMEM_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_tfrtrim_outpen_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCTLE_TFRTRIM_OUTPEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctledc_dccouple_tgate_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCTLEDC_DCCOUPLE_TGATE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctledc_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCTLEDC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxdfe_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXDFE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxdfe_tapgain_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxdfepam_enable_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXDFEPAM_ENABLE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxdfepam_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXDFEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxdpifjit_enb_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXDPIFJIT_ENB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxdpifjit_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXDPIFJIT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxdpifjit_offset_locovr_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqadj_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQADJ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqadj_yadjust_aux0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqadj_yadjust_aux1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqadj_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqadj_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqadj_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqadj_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqadj_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqadj_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqauxxor_amux_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqauxxor_dmux_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqauxxor_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQAUXXOR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcal2flx_pstate_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCAL2FLX_PSTATE_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcal2flx_rate_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCAL2FLX_RATE_MASK_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_16a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_16b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_16c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_16d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_16e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_1a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_1b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_1c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_1d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_1e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_2a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_2b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_2c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_2d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_2e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_4a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_4b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_4c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_4d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_4e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_8a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_8b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_8c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_8d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_8e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_16a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_16b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_16c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_16d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_16e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_1a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_1b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_1c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_1d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_1e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_2a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_2b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_2c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_2d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_2e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_4a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_4b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_4c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_4d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_4e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_8a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_8b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_8c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_8d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_8e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_16a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_16b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_16c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_16d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_16e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_1a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_1b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_1c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_1d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_1e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_2a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_2b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_2c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_2d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_2e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_4a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_4b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_4c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_4d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_4e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_8a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_8b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_8c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_8d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_8e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcals_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCALS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcals_offset_datasummer0_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcals_offset_datasummer0_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcals_offset_datasummer1_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcals_offset_datasummer1_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcals_offset_edgesummer0_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcals_offset_edgesummer0_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcals_offset_edgesummer1_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcals_offset_edgesummer1_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcdr_force_ltr_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCDR_FORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcdr_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCDR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqctl_clear_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCTL_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqctl_fg_run_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCTL_FG_RUN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqctlelut_hifreqagcres_ovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCTLELUT_HIFREQAGCRES_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqctlelut_hifreqvgagain_ovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCTLELUT_HIFREQVGAGAIN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqctls_oddeven_tapgain_sel_inv_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCTLS_ODDEVEN_TAPGAIN_SEL_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqctls_static_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCTLS_STATIC_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqdat_aux_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQDAT_AUX_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqdat_edge_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQDAT_EDGE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqdatactl_auxswap_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqdatactl_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQDATACTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqdatarate_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQDATARATE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqdatarate_rx_rate_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqdfeyadj_agingl2r_delay_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqdfeyadj_agingl2r_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQDFEYADJ_AGINGL2R_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqedgeadj_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEDGEADJ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqedgeadj_yadjust_edge0lo_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqedgeadj_yadjust_edge1lo_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm2flx_ehm_done_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHM2FLX_EHM_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm2flx_ehm_done_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHM2FLX_EHM_DONE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm2flx_ehm_err_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHM2FLX_EHM_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm2flx_ehm_err_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHM2FLX_EHM_ERR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm2flx_ehm_fom_locovr_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHM2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_data_extshift_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHM_DATA_EXTSHIFT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_distance_th_50p_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_distance_th_rate_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_err_mask_vf00_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_err_mask_vf01_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_event_rate_vf00_attr == 32'd67108864
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_event_rate_vf01_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_general_in_vf00_attr == 32'd5505024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_general_in_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_lms_th_50p_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_lms_th_rate_attr == 20'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_mask_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_no_change_th_50p_attr == 12'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_no_change_th_rate_attr == 12'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_reflections_num_50p_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_reflections_num_rate_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_slicer_swap_cb_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHM_SLICER_SWAP_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_sym_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_sym_dly_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_tap_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_test_aux_slicer_val_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_test_hits_th_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjaux_ehm_yadjust_aux0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjaux_ehm_yadjust_aux1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjaux_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJAUX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjauxen_ehm_aux_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJAUXEN_EHM_AUX_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjauxen_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJAUXEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjauxltch_aux_yadj_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJAUXLTCH_AUX_YADJ_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjauxltch_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJAUXLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdata_ehm_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdata_ehm_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdata_ehm_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdata_ehm_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdata_ehm_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdata_ehm_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdata_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdataen_ehm_data_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJDATAEN_EHM_DATA_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdataen_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJDATAEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdataltch_data_yadj_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJDATALTCH_DATA_YADJ_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdataltch_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJDATALTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2ehm_ehm_run_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2EHM_EHM_RUN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2ehm_ehm_run_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2EHM_EHM_RUN_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2lms_coarse_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2LMS_COARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2lms_ctrl_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2LMS_CTRL_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2lms_dfecore_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2LMS_DFECORE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2lms_force_evrefupd_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2LMS_FORCE_EVREFUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2lms_freeze_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2LMS_FREEZE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2lms_incr_decr_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2LMS_INCR_DECR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2lms_mu_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2LMS_MU_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2lms_rst_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2LMS_RST_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2ofc_ofc_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2OFC_OFC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2ofc_ofc_en_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2OFC_OFC_EN_OVRDEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx_pcs_rxeq_clr_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX_PCS_RXEQ_CLR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx_pcs_rxeq_start_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX_PCS_RXEQ_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx_pcs_rxeq_static_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX_PCS_RXEQ_STATIC_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx_rxrate2pcie1_map_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx_rxrate2pcie2_map_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx_rxrate2pcie3_map_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx_rxrate2pcie4_map_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxehmdata_ehm_data_slc_sel_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXEHMDATA_EHM_DATA_SLC_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxehmdata_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXEHMDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxfsm_generalpurpose_reg_in_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxfsm_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXFSM_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxfsm_pause_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXFSM_PAUSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxfsm_state_obs_hold_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXFSM_STATE_OBS_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxfsm_state_obs_sel_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXFSM_STATE_OBS_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxltr_force_ltr_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXLTR_FORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxltr_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXLTR_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxpcsrxeyediag_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXPCSRXEYEDIAG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxpcsrxeyediag_start_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXPCSRXEYEDIAG_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxsigdet_sel_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXSIGDET_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqfsm2ofc_ofc_cal_req_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFSM2OFC_OFC_CAL_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqfsm2ofc_ofc_cal_req_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFSM2OFC_OFC_CAL_REQ_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_16a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_16b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_16c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_16d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_16e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_1a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_1b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_1c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_1d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_1e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_2a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_2b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_2c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_2d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_2e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_4a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_4b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_4c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_4d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_4e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_8a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_8b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_8c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_8d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_8e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_done_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmax_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmax_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_SATMAX_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmax_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmax_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmax_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_SATMAX_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmax_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_SATMAX_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmax_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_SATMAX_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmin_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmin_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_SATMIN_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmin_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmin_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmin_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_SATMIN_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmin_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_SATMIN_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmin_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_SATMIN_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_stable_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_stable_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_STABLE_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_stable_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_stable_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_stable_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_STABLE_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_stable_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_STABLE_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_stable_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_STABLE_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsupd_chng_ack_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSUPD_CHNG_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsupd_chng_req_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSUPD_CHNG_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsupd_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSUPD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjaux_lms_vref0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjaux_lms_vref1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjaux_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJAUX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjauxen_lms_aux_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJAUXEN_LMS_AUX_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjauxen_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJAUXEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjauxltch_lms_aux_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJAUXLTCH_LMS_AUX_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjauxltch_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJAUXLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdata_lms_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdata_lms_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdata_lms_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdata_lms_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdata_lms_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdata_lms_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdata_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdataen_lms_data_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJDATAEN_LMS_DATA_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdataen_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJDATAEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdataltch_lms_data_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJDATALTCH_LMS_DATA_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdataltch_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJDATALTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjedge_lms_yadjust_edge0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjedge_lms_yadjust_edge1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjedge_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJEDGE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjedgeen_lms_edge_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJEDGEEN_LMS_EDGE_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjedgeen_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJEDGEEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjedgeltch_lms_edge_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJEDGELTCH_LMS_EDGE_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjedgeltch_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJEDGELTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqltch_dfe_aux_yadj_b_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLTCH_DFE_AUX_YADJ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqltch_dfe_b_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLTCH_DFE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqltch_dfe_data_yadj_b_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLTCH_DFE_DATA_YADJ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqltch_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqltchc_auxswap_b_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLTCHC_AUXSWAP_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqltchc_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLTCHC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofc2flx_ofc_cal_done_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQOFC2FLX_OFC_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofc2flx_ofc_cal_done_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQOFC2FLX_OFC_CAL_DONE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_ctle_rxinpprobemuxen_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_ctle_rxstg1_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_ctle_rxstg1probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_ctle_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_ctle_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_ctle_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_ctle_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_summer_rxinpprobemuxen_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_summer_rxstg1_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_summer_rxstg1probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_summer_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_summer_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_summer_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_summer_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_time_h_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_time_l_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_ctle_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_ctle_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_ctle_rxstg1probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_ctle_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_ctle_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_ctle_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_ctle_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_summer_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_summer_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_summer_rxstg1probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_summer_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_summer_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_summer_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_summer_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_time_l_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_compsel_ctle_st1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_compsel_ctle_st2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_compsel_ctle_st3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_compsel_idle_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_compsel_sa_d0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_compsel_sa_d1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_compsel_sa_e0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_compsel_sa_e1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_invert_comp_fb_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_lpexitcal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_lpexitcal_time_l_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_adapt_en_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_adapt_thr_sel_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_cal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_cal_thr_sel_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_data_disp_sticky_clr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQOFCCFG_OFC_DATA_DISP_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_disparity_disable_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQOFCCFG_OFC_DISPARITY_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_disparity_leak_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_disparity_thr_sel_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_lpexitcal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_lpf_bypass_en_cb_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQOFCCFG_OFC_LPF_BYPASS_EN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_ratechangecal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_pre_timer_setting_pow2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ratechangecal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ratechangecal_time_l_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_rxinpprobemuxen_idle_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_rxstg1_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_rxstg1probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_rxstg2_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_rxstg2probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_rxstg3_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_rxstg3probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqout_init_restore_avail_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQOUT_INIT_RESTORE_AVAIL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqprecal_code_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqprecal_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQPRECAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_hf1deq_dir_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_BOOSTLUT_HF1DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_hf2deq_dir_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_BOOSTLUT_HF2DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_hf2reszero_dir_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_BOOSTLUT_HF2RESZERO_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_hf3deq_dir_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_BOOSTLUT_HF3DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_idx_hf1deq_vf00_attr == 32'd599186
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_idx_hf1deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_idx_hf2deq_vf00_attr == 32'd1198372
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_idx_hf2deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_idx_hf2reszero_vf00_attr == 32'd4290772992
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_idx_hf2reszero_vf01_attr == 21'd2097151
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_idx_hf3deq_vf00_attr == 32'd2396744
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_idx_hf3deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_init_hf1deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_init_hf2deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_init_hf2reszero_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_init_hf3deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_cal_hifreqagcres_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_cal_hifreqvgagain_attr == 7'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_cal_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_cal_yadjust_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_biasboost_dir_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_GAINLUT_BIASBOOST_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_hf1resdcgain_dir_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_GAINLUT_HF1RESDCGAIN_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_hf3resdcgain_dir_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_GAINLUT_HF3RESDCGAIN_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_biasboost_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_biasboost_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_biasboost_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf00_attr == 32'd2863311530
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf01_attr == 32'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf00_attr == 32'd1431655764
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf01_attr == 32'd1431655765
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_lbbiasboost_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_lbbiasboost_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_lbbiasboost_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_init_biasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_init_hf1resdcgain_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_init_hf3resdcgain_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_init_lbbiasboost_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_lbbiasboost_dir_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_GAINLUT_LBBIASBOOST_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_latch_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref0_initval_attr == 9'd61
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref1_initval_attr == 9'd191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref2_initval_attr == 9'd321
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref3_initval_attr == 9'd451
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_decr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_AUXVREF_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_frac_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_AUXVREF_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_frac_reset_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_incr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_AUXVREF_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_incr_decr_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_pam4adj_swizzle_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_AUXVREF_PAM4ADJ_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_AUXVREF_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_pol_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_single_step_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_AUXVREF_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_stable_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_AUXVREF_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_AUXVREF_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_targ_0_hi_attr == 9'd149
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_targ_0_lo_attr == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_auxvref_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_auxvref_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_dfe_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_dfe_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_edge_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_edge_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_edgevref_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_edgevref_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_iqalign_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_iqalign_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_level_vga_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_vga_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_vga_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_blockcount_fast_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_BLOCKCOUNT_FAST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_coarse_detect_clear_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_COARSE_DETECT_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_coarse_detect_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_COARSE_DETECT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_continuous_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_CONTINUOUS_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_datastats_incr_decr_swizzle_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_DATASTATS_INCR_DECR_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_datastats_pol_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_DATASTATS_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_datastats_thres_attr == 16'd1023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe1_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe2_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe3_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe4p_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_core_sel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_decr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_DFE_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_frac_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_DFE_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_frac_reset_mask_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_incr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_DFE_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_incr_decr_mask_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_inner_lvl_filter_en_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_DFE_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_pol_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_single_step_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_DFE_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_stable_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_DFE_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_DFE_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_targtap1_attr == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_targtap2_attr == 7'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_targtap3_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_targtap4_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_decr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGE_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_frac_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGE_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_frac_reset_mask_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_incr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGE_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_incr_decr_mask_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGE_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_pol_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_single_step_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGE_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_stable_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGE_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGE_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_decr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGEVREF_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_frac_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGEVREF_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGEVREF_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_incr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGEVREF_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_initval_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGEVREF_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_pol_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGEVREF_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_single_step_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGEVREF_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_stable_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGEVREF_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGEVREF_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_fast_blockcnt_attr == 16'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_filter_mode_auxvref_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_filter_mode_dfe_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_filter_mode_edge_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_filter_mode_edgevref_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_filter_mode_iqalign_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_filter_mode_vga_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_freeze_auxvrefupd_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_freeze_dfeupd_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_freeze_edgeupd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_freeze_edgevrefupd_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_FREEZE_EDGEVREFUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_freeze_forcebg_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_FREEZE_FORCEBG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_freeze_hifreqagcupd_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_FREEZE_HIFREQAGCUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_freeze_iqalignupd_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_FREEZE_IQALIGNUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_freeze_lofreqagcupd_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_FREEZE_LOFREQAGCUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_freeze_vgaupd_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_FREEZE_VGAUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_gated_update_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_GATED_UPDATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_accum_count_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_accum_level_en_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_decr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_HIFREQAGC_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_frac_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_HIFREQAGC_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_HIFREQAGC_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_incr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_HIFREQAGC_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_n1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_n2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_n3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_n4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_n5_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_HIFREQAGC_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_pol_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_HIFREQAGC_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_single_step_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_HIFREQAGC_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_stable_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_HIFREQAGC_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_HIFREQAGC_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_init_adapt_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_INIT_ADAPT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_decr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_IQALIGN_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_frac_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_IQALIGN_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_IQALIGN_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_incr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_IQALIGN_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_IQALIGN_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_pol_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_IQALIGN_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_single_step_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_IQALIGN_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_stable_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_IQALIGN_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_IQALIGN_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_targ_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_itercount_attr == 10'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_latch_delay_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_latch_prepost_delay_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_decr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOFREQAGC_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_frac_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOFREQAGC_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOFREQAGC_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_incr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOFREQAGC_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOFREQAGC_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_pol_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOFREQAGC_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_single_step_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOFREQAGC_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_stable_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOFREQAGC_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOFREQAGC_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_logain_auxvref_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOGAIN_AUXVREF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_logain_dfe_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_logain_edge_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_logain_edgevref_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOGAIN_EDGEVREF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_logain_hifreqagc_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOGAIN_HIFREQAGC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_logain_iqalign_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOGAIN_IQALIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_logain_lofreqagc_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOGAIN_LOFREQAGC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_logain_vga_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOGAIN_VGA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_auxvref_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_dfe1_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_dfe23_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_dfe4p_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_edge2_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_edge3_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_edge4_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_edgevref_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_hifreqagc_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_iqalign_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_lofreqagc_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_vga_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_nrz_to_pam4_mode_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_NRZ_TO_PAM4_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_slow_blockcnt_attr == 16'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_start_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_tsettle_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_accum_count_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_accum_level_en_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_decr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_frac_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_incr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_mode_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_pol_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_single_step_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_stable_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_yadjdata_mid_clamp_zero_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_YADJDATA_MID_CLAMP_ZERO_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lofreqagcgain_sel_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LOFREQAGCGAIN_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_caldfedatatap1gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_caldfedatatap2gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_caldfedatatap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_caldfedatatap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_caldfeedgetap2gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_caldfeedgetap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_caldfeedgetap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_lofreqagcgain_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_caldfedatatap1gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_caldfedatatap1gain_attr == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_caldfedatatap1gain_attr == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_shift_auxshft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_shift_capture_trigger_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_SHIFT_CAPTURE_TRIGGER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_shift_clear_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_SHIFT_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_shift_dat_bitsel_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_SHIFT_DAT_BITSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_shift_datashft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_shift_edgeshft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_shift_edgeshft_nrz8b10b_pam16b20b_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_shift_polarity_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_SHIFT_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap10gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap11gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap12gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap13gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap14gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap15gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap16gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap1gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap2gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap5gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap6gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap7gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap8gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap9gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfeedgetap2gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfeedgetap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfeedgetap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_hifreqvgagain_attr == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_auxvref0_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_auxvref1_attr == 9'd223
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_auxvref2_attr == 9'd339
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_auxvref3_attr == 9'd456
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_caldfedatatap1gain_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_caldfeedgetap2gain_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_calhifreqagcres_attr == 6'd52
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_callofreqagcgain_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_edgevref_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_hifreqvgagain_attr == 7'd77
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_iqalign_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_auxvref0_attr == 9'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_auxvref1_attr == 9'd173
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_auxvref2_attr == 9'd289
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_auxvref3_attr == 9'd356
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_caldfedatatap1gain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_caldfeedgetap2gain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_calhifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_callofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_edgevref_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_iqalign_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqsetnrztopam4_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSETNRZTOPAM4_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqsetnrztopam4_switch_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSETNRZTOPAM4_SWITCH_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqsigdet_pause_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSIGDET_PAUSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqspare0_attr == 32'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqspare1_attr == 32'd15871
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqspare2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqsync2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSYNC2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqsync2flx_rxdatapath_ready_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSYNC2FLX_RXDATAPATH_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqtapctrl_data_tap13to16_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQTAPCTRL_DATA_TAP13TO16_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqtapctrl_data_tap1to4_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQTAPCTRL_DATA_TAP1TO4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqtapctrl_data_tap5to8_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQTAPCTRL_DATA_TAP5TO8_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqtapctrl_data_tap9to12_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQTAPCTRL_DATA_TAP9TO12_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqtapctrl_edge_tap_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQTAPCTRL_EDGE_TAP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqtapctrl_tap1to4gain_dbl_res_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQTAPCTRL_TAP1TO4GAIN_DBL_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqtapctrl_tap5to16gain_dbl_res_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQTAPCTRL_TAP5TO16GAIN_DBL_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvalc_hifreqagcbiasadjust_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvalc_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQVALC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvalc_midbandzero_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvalcl_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQVALCL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvalcl_lofreqagcgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap01gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap02gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap03gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap04gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap05gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap06gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap07gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap08gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap09gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap10gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap11gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap12gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap13gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap14gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap15gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap16gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQVALD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvale_caldfeedgetap02gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvale_caldfeedgetap03gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvale_caldfeedgetap04gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvale_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQVALE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1cal_clear_mask_attr == 13'd8184
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_aux0_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_aux1_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_d0_bot_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_d0_mid_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_d0_top_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_d1_bot_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_d1_mid_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_d1_top_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_e0_lo_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_e1_lo_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2cal_clear_mask_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_aux0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_aux1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_d0_bot_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_d0_mid_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_d0_top_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_d1_bot_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_d1_mid_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_d1_top_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_e0_lo_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_e1_lo_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfgcal_calfsmmeas_dlycount_attr == 10'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfgcal_fsmmaxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfgcal_lpfax_coarse_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfgcal_lpfax_fine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxhifreqagc_inputcmadjust_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxhifreqagc_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXHIFREQAGC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcal_clear_mask_attr == 13'd8191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_ctlecmnmode_stg1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_ctlecmnmode_stg2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_ctlecmnmode_stg3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_aux0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_aux1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_d0_bot_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_d0_mid_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_d0_top_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_d1_bot_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_d1_mid_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_d1_top_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_e0_lo_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_e1_lo_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmargin_flx_jit_offset_shift_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmargin_jit_disable_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmargin_jit_enable_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmargin_jit_offset_shift_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmargin_jit_setup_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmargin_volt_comp_mask_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmargin_volt_forcel2d_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXMARGIN_VOLT_FORCEL2D_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmargin_volt_offset_shift_d0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmargin_volt_offset_shift_d1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmarginin_direction_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXMARGININ_DIRECTION_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmarginin_flx_jit_offset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmarginin_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXMARGININ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmarginin_mode_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXMARGININ_MODE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmarginin_offset_change_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXMARGININ_OFFSET_CHANGE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmarginin_offset_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmarginin_start_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXMARGININ_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxsum_cm_vref_attr == 9'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxsum_summer_cmfb_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXSUM_SUMMER_CMFB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxsum_summer_cmfb_ibias_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_dfeyadj_aging_cdrlock2data_loc_ov_attr == SERDES_IP_LANE_RXEQ_L1_CFG_DFEYADJ_AGING_CDRLOCK2DATA_LOC_OV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_dfeyadj_aging_cdrlock2data_loc_ov_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_DFEYADJ_AGING_CDRLOCK2DATA_LOC_OV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_dfeyadj_aging_div_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_dfeyadj_aging_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_DFEYADJ_AGING_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxagc_ctlecomp_filterbypass_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXAGC_CTLECOMP_FILTERBYPASS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxagc_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXAGC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxbgcal_calfsmmeas_dlycount_attr == 10'd392
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxbgcal_clear_mask_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxbgcal_fsmmaxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxbgcal_lpfax_coarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxbgcal_lpfax_fine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxbgcalorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxbgcalorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxbgcalorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_calbiasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_calbiasboost_use_lut_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_CALBIASBOOST_USE_LUT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_callbbiasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_callbbiasboost_use_lut_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_CALLBBIASBOOST_USE_LUT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlecomp_filterbypass_smplrcal_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_CTLECOMP_FILTERBYPASS_SMPLRCAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg1_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg2_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg3_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctleinput_probe_mux_smplrcal_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg1_probe_mux_en_smplrcal_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg1_state_en_smplrcal_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg1_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg1_state_en_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg1_state_en_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg1_use_stg2code_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_CTLESTG1_USE_STG2CODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg2_probe_mux_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg2_state_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg2_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg2_state_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg2_state_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg3_probe_mux_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg3_state_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg3_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg3_state_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg3_state_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_hifreqagc_n5targin_sel_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_HIFREQAGC_N5TARGIN_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_inputcmadjust_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_inputcmadjust_stg1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_inputcmadjust_stg2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_inputcmadjust_stg3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_sdimode_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_SDIMODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_smplroffset_aux0_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_smplroffset_aux1_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_smplroffset_d0_bot_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_smplroffset_d0_mid_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_smplroffset_d0_top_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_smplroffset_d1_bot_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_smplroffset_d1_mid_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_smplroffset_d1_top_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_tfrtrim_outen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_tfrtrim_outen_tfrcal_stg1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_tfrtrim_outen_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_tfrtrim_outen_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalalign_iqclk_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalalign_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALALIGN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctl_cal_abort_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALCTL_CAL_ABORT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctl_cal_type_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctl_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALCTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctl_post_delay_pow2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctl_pre_delay_pow2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecalctrl_input_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecalctrl_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALCTLECALCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecalctrl_stg1_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecalctrl_stg1_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecalctrl_stg2_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecalctrl_stg2_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecalctrl_stg3_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecalctrl_stg3_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecompoffset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecompoffset_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALCTLECOMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecompoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALCTLECOMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecompoffsetfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALCTLECOMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecompoffsetfsmout_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaldutybkgnd_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALDUTYBKGND_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaldutybkgnd_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALDUTYBKGND_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_biasboost_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_hf1deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_hf1resdcgain_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_hf2cap_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_hf2deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_hf2reszero_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_hf3deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_hf3resdcgain_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_hf4deq_gray_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALEQ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_ctlecmnmode_stg1_finish_side_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALFSM_CTLECMNMODE_STG1_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_ctlecmnmode_stg1_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_ctlecmnmode_stg2_finish_side_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALFSM_CTLECMNMODE_STG2_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_ctlecmnmode_stg2_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_ctlecmnmode_stg3_finish_side_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALFSM_CTLECMNMODE_STG3_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_ctlecmnmode_stg3_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_runcount_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_smplroffset_finish_side_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALFSM_SMPLROFFSET_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_smplroffset_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsmmeas_ctlecmnmode_stg1_invert_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALFSMMEAS_CTLECMNMODE_STG1_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsmmeas_ctlecmnmode_stg2_invert_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALFSMMEAS_CTLECMNMODE_STG2_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsmmeas_ctlecmnmode_stg3_invert_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALFSMMEAS_CTLECMNMODE_STG3_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsmmeas_smplroffset_invert_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALFSMMEAS_SMPLROFFSET_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_ctlecmnmode_stg1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_ctlecmnmode_stg2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_ctlecmnmode_stg3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_aux0_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_aux1_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_d0_bot_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_d0_mid_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_d0_top_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_d1_bot_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_d1_mid_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_d1_top_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_e0_lo_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_e1_lo_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeas_pow2count_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasin_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasin_req_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASIN_REQ_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasin_req_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASIN_REQ_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasin_req_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASIN_REQ_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasout_ack_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASOUT_ACK_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasout_ack_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASOUT_ACK_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasout_ack_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASOUT_ACK_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasout_avg_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASOUT_AVG_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasout_avg_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASOUT_AVG_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasout_avg_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASOUT_AVG_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasout_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaloffsetfsmout_auxdatacomp_offset_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALOFFSETFSMOUT_AUXDATACOMP_OFFSET_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaloffsetfsmout_boost_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALOFFSETFSMOUT_BOOST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaloffsetfsmout_edgecomp_offset_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALOFFSETFSMOUT_EDGECOMP_OFFSET_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaloffsetfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalset_cal_clear_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalset_cal_mode_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALSET_CAL_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalset_cal_req_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALSET_CAL_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalset_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalstat_cal_ack_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALSTAT_CAL_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalstat_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalsummerfsmout_comp_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALSUMMERFSMOUT_COMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalsummerfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALSUMMERFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcdrphd_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCDRPHD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcdrphd_override_ignore_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCDRPHD_OVERRIDE_IGNORE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_caloffset_range_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_calstg1offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_calstg1offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_calstg2offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_calstg2offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_calstg3offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_calstg3offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_dccouple_sigpath_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCTLE_DCCOUPLE_SIGPATH_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_lbbiasboost_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCTLE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_stg1tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_stg2tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_stg3tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_tfrtrim_outmem_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCTLE_TFRTRIM_OUTMEM_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_tfrtrim_outpen_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCTLE_TFRTRIM_OUTPEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctledc_dccouple_tgate_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCTLEDC_DCCOUPLE_TGATE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctledc_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCTLEDC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxdfe_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXDFE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxdfe_tapgain_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxdfepam_enable_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXDFEPAM_ENABLE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxdfepam_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXDFEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxdpifjit_enb_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXDPIFJIT_ENB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxdpifjit_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXDPIFJIT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxdpifjit_offset_locovr_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqadj_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQADJ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqadj_yadjust_aux0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqadj_yadjust_aux1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqadj_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqadj_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqadj_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqadj_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqadj_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqadj_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqauxxor_amux_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqauxxor_dmux_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqauxxor_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQAUXXOR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcal2flx_pstate_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCAL2FLX_PSTATE_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcal2flx_rate_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCAL2FLX_RATE_MASK_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_16a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_16b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_16c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_16d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_16e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_1a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_1b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_1c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_1d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_1e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_2a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_2b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_2c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_2d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_2e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_4a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_4b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_4c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_4d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_4e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_8a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_8b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_8c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_8d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_8e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_16a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_16b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_16c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_16d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_16e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_1a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_1b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_1c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_1d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_1e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_2a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_2b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_2c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_2d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_2e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_4a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_4b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_4c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_4d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_4e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_8a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_8b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_8c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_8d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_8e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_16a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_16b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_16c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_16d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_16e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_1a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_1b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_1c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_1d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_1e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_2a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_2b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_2c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_2d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_2e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_4a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_4b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_4c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_4d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_4e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_8a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_8b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_8c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_8d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_8e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcals_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCALS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcals_offset_datasummer0_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcals_offset_datasummer0_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcals_offset_datasummer1_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcals_offset_datasummer1_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcals_offset_edgesummer0_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcals_offset_edgesummer0_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcals_offset_edgesummer1_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcals_offset_edgesummer1_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcdr_force_ltr_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCDR_FORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcdr_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCDR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqctl_clear_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCTL_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqctl_fg_run_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCTL_FG_RUN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqctlelut_hifreqagcres_ovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCTLELUT_HIFREQAGCRES_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqctlelut_hifreqvgagain_ovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCTLELUT_HIFREQVGAGAIN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqctls_oddeven_tapgain_sel_inv_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCTLS_ODDEVEN_TAPGAIN_SEL_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqctls_static_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCTLS_STATIC_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqdat_aux_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQDAT_AUX_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqdat_edge_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQDAT_EDGE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqdatactl_auxswap_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqdatactl_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQDATACTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqdatarate_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQDATARATE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqdatarate_rx_rate_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqdfeyadj_agingl2r_delay_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqdfeyadj_agingl2r_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQDFEYADJ_AGINGL2R_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqedgeadj_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEDGEADJ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqedgeadj_yadjust_edge0lo_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqedgeadj_yadjust_edge1lo_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm2flx_ehm_done_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHM2FLX_EHM_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm2flx_ehm_done_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHM2FLX_EHM_DONE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm2flx_ehm_err_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHM2FLX_EHM_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm2flx_ehm_err_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHM2FLX_EHM_ERR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm2flx_ehm_fom_locovr_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHM2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_data_extshift_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHM_DATA_EXTSHIFT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_distance_th_50p_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_distance_th_rate_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_err_mask_vf00_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_err_mask_vf01_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_event_rate_vf00_attr == 32'd67108864
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_event_rate_vf01_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_general_in_vf00_attr == 32'd5505024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_general_in_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_lms_th_50p_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_lms_th_rate_attr == 20'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_mask_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_no_change_th_50p_attr == 12'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_no_change_th_rate_attr == 12'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_reflections_num_50p_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_reflections_num_rate_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_slicer_swap_cb_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHM_SLICER_SWAP_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_sym_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_sym_dly_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_tap_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_test_aux_slicer_val_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_test_hits_th_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjaux_ehm_yadjust_aux0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjaux_ehm_yadjust_aux1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjaux_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJAUX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjauxen_ehm_aux_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJAUXEN_EHM_AUX_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjauxen_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJAUXEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjauxltch_aux_yadj_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJAUXLTCH_AUX_YADJ_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjauxltch_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJAUXLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdata_ehm_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdata_ehm_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdata_ehm_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdata_ehm_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdata_ehm_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdata_ehm_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdata_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdataen_ehm_data_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJDATAEN_EHM_DATA_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdataen_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJDATAEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdataltch_data_yadj_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJDATALTCH_DATA_YADJ_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdataltch_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJDATALTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2ehm_ehm_run_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2EHM_EHM_RUN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2ehm_ehm_run_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2EHM_EHM_RUN_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2lms_coarse_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2LMS_COARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2lms_ctrl_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2LMS_CTRL_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2lms_dfecore_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2LMS_DFECORE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2lms_force_evrefupd_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2LMS_FORCE_EVREFUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2lms_freeze_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2LMS_FREEZE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2lms_incr_decr_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2LMS_INCR_DECR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2lms_mu_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2LMS_MU_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2lms_rst_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2LMS_RST_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2ofc_ofc_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2OFC_OFC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2ofc_ofc_en_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2OFC_OFC_EN_OVRDEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx_pcs_rxeq_clr_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX_PCS_RXEQ_CLR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx_pcs_rxeq_start_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX_PCS_RXEQ_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx_pcs_rxeq_static_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX_PCS_RXEQ_STATIC_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx_rxrate2pcie1_map_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx_rxrate2pcie2_map_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx_rxrate2pcie3_map_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx_rxrate2pcie4_map_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxehmdata_ehm_data_slc_sel_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXEHMDATA_EHM_DATA_SLC_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxehmdata_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXEHMDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxfsm_generalpurpose_reg_in_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxfsm_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXFSM_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxfsm_pause_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXFSM_PAUSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxfsm_state_obs_hold_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXFSM_STATE_OBS_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxfsm_state_obs_sel_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXFSM_STATE_OBS_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxltr_force_ltr_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXLTR_FORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxltr_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXLTR_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxpcsrxeyediag_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXPCSRXEYEDIAG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxpcsrxeyediag_start_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXPCSRXEYEDIAG_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxsigdet_sel_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXSIGDET_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqfsm2ofc_ofc_cal_req_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFSM2OFC_OFC_CAL_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqfsm2ofc_ofc_cal_req_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFSM2OFC_OFC_CAL_REQ_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_16a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_16b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_16c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_16d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_16e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_1a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_1b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_1c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_1d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_1e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_2a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_2b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_2c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_2d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_2e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_4a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_4b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_4c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_4d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_4e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_8a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_8b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_8c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_8d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_8e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_done_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmax_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmax_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_SATMAX_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmax_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmax_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmax_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_SATMAX_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmax_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_SATMAX_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmax_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_SATMAX_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmin_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmin_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_SATMIN_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmin_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmin_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmin_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_SATMIN_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmin_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_SATMIN_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmin_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_SATMIN_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_stable_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_stable_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_STABLE_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_stable_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_stable_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_stable_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_STABLE_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_stable_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_STABLE_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_stable_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_STABLE_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsupd_chng_ack_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSUPD_CHNG_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsupd_chng_req_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSUPD_CHNG_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsupd_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSUPD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjaux_lms_vref0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjaux_lms_vref1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjaux_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJAUX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjauxen_lms_aux_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJAUXEN_LMS_AUX_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjauxen_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJAUXEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjauxltch_lms_aux_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJAUXLTCH_LMS_AUX_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjauxltch_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJAUXLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdata_lms_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdata_lms_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdata_lms_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdata_lms_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdata_lms_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdata_lms_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdata_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdataen_lms_data_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJDATAEN_LMS_DATA_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdataen_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJDATAEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdataltch_lms_data_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJDATALTCH_LMS_DATA_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdataltch_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJDATALTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjedge_lms_yadjust_edge0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjedge_lms_yadjust_edge1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjedge_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJEDGE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjedgeen_lms_edge_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJEDGEEN_LMS_EDGE_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjedgeen_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJEDGEEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjedgeltch_lms_edge_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJEDGELTCH_LMS_EDGE_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjedgeltch_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJEDGELTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqltch_dfe_aux_yadj_b_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLTCH_DFE_AUX_YADJ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqltch_dfe_b_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLTCH_DFE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqltch_dfe_data_yadj_b_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLTCH_DFE_DATA_YADJ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqltch_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqltchc_auxswap_b_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLTCHC_AUXSWAP_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqltchc_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLTCHC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofc2flx_ofc_cal_done_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQOFC2FLX_OFC_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofc2flx_ofc_cal_done_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQOFC2FLX_OFC_CAL_DONE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_ctle_rxinpprobemuxen_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_ctle_rxstg1_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_ctle_rxstg1probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_ctle_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_ctle_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_ctle_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_ctle_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_summer_rxinpprobemuxen_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_summer_rxstg1_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_summer_rxstg1probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_summer_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_summer_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_summer_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_summer_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_time_h_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_time_l_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_ctle_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_ctle_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_ctle_rxstg1probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_ctle_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_ctle_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_ctle_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_ctle_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_summer_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_summer_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_summer_rxstg1probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_summer_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_summer_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_summer_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_summer_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_time_l_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_compsel_ctle_st1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_compsel_ctle_st2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_compsel_ctle_st3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_compsel_idle_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_compsel_sa_d0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_compsel_sa_d1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_compsel_sa_e0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_compsel_sa_e1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_invert_comp_fb_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_lpexitcal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_lpexitcal_time_l_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_adapt_en_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_adapt_thr_sel_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_cal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_cal_thr_sel_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_data_disp_sticky_clr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQOFCCFG_OFC_DATA_DISP_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_disparity_disable_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQOFCCFG_OFC_DISPARITY_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_disparity_leak_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_disparity_thr_sel_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_lpexitcal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_lpf_bypass_en_cb_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQOFCCFG_OFC_LPF_BYPASS_EN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_ratechangecal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_pre_timer_setting_pow2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ratechangecal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ratechangecal_time_l_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_rxinpprobemuxen_idle_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_rxstg1_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_rxstg1probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_rxstg2_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_rxstg2probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_rxstg3_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_rxstg3probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqout_init_restore_avail_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQOUT_INIT_RESTORE_AVAIL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqprecal_code_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqprecal_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQPRECAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_hf1deq_dir_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_BOOSTLUT_HF1DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_hf2deq_dir_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_BOOSTLUT_HF2DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_hf2reszero_dir_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_BOOSTLUT_HF2RESZERO_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_hf3deq_dir_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_BOOSTLUT_HF3DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_idx_hf1deq_vf00_attr == 32'd599186
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_idx_hf1deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_idx_hf2deq_vf00_attr == 32'd1198372
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_idx_hf2deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_idx_hf2reszero_vf00_attr == 32'd4290772992
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_idx_hf2reszero_vf01_attr == 21'd2097151
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_idx_hf3deq_vf00_attr == 32'd2396744
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_idx_hf3deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_init_hf1deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_init_hf2deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_init_hf2reszero_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_init_hf3deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_cal_hifreqagcres_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_cal_hifreqvgagain_attr == 7'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_cal_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_cal_yadjust_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_biasboost_dir_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_GAINLUT_BIASBOOST_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_hf1resdcgain_dir_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_GAINLUT_HF1RESDCGAIN_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_hf3resdcgain_dir_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_GAINLUT_HF3RESDCGAIN_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_biasboost_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_biasboost_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_biasboost_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf00_attr == 32'd2863311530
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf01_attr == 32'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf00_attr == 32'd1431655764
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf01_attr == 32'd1431655765
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_lbbiasboost_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_lbbiasboost_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_lbbiasboost_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_init_biasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_init_hf1resdcgain_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_init_hf3resdcgain_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_init_lbbiasboost_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_lbbiasboost_dir_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_GAINLUT_LBBIASBOOST_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_latch_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref0_initval_attr == 9'd61
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref1_initval_attr == 9'd191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref2_initval_attr == 9'd321
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref3_initval_attr == 9'd451
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_decr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_AUXVREF_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_frac_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_AUXVREF_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_frac_reset_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_incr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_AUXVREF_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_incr_decr_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_pam4adj_swizzle_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_AUXVREF_PAM4ADJ_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_AUXVREF_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_pol_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_single_step_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_AUXVREF_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_stable_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_AUXVREF_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_AUXVREF_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_targ_0_hi_attr == 9'd130
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_targ_0_lo_attr == 9'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_auxvref_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_auxvref_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_dfe_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_dfe_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_edge_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_edge_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_edgevref_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_edgevref_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_iqalign_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_iqalign_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_level_vga_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_vga_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_vga_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_blockcount_fast_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_BLOCKCOUNT_FAST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_coarse_detect_clear_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_COARSE_DETECT_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_coarse_detect_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_COARSE_DETECT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_continuous_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_CONTINUOUS_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_datastats_incr_decr_swizzle_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_DATASTATS_INCR_DECR_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_datastats_pol_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_DATASTATS_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_datastats_thres_attr == 16'd1023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe1_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe2_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe3_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe4p_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_core_sel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_decr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_DFE_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_frac_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_DFE_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_frac_reset_mask_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_incr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_DFE_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_incr_decr_mask_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_inner_lvl_filter_en_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_DFE_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_pol_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_single_step_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_DFE_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_stable_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_DFE_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_DFE_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_targtap1_attr == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_targtap2_attr == 7'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_targtap3_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_targtap4_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_decr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGE_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_frac_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGE_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_frac_reset_mask_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_incr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGE_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_incr_decr_mask_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGE_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_pol_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_single_step_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGE_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_stable_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGE_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGE_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_decr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGEVREF_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_frac_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGEVREF_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGEVREF_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_incr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGEVREF_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_initval_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGEVREF_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_pol_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGEVREF_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_single_step_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGEVREF_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_stable_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGEVREF_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGEVREF_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_fast_blockcnt_attr == 16'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_filter_mode_auxvref_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_filter_mode_dfe_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_filter_mode_edge_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_filter_mode_edgevref_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_filter_mode_iqalign_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_filter_mode_vga_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_freeze_auxvrefupd_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_freeze_dfeupd_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_freeze_edgeupd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_freeze_edgevrefupd_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_FREEZE_EDGEVREFUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_freeze_forcebg_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_FREEZE_FORCEBG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_freeze_hifreqagcupd_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_FREEZE_HIFREQAGCUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_freeze_iqalignupd_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_FREEZE_IQALIGNUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_freeze_lofreqagcupd_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_FREEZE_LOFREQAGCUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_freeze_vgaupd_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_FREEZE_VGAUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_gated_update_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_GATED_UPDATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_accum_count_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_accum_level_en_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_decr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_HIFREQAGC_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_frac_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_HIFREQAGC_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_HIFREQAGC_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_incr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_HIFREQAGC_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_n1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_n2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_n3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_n4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_n5_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_HIFREQAGC_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_pol_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_HIFREQAGC_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_single_step_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_HIFREQAGC_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_stable_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_HIFREQAGC_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_HIFREQAGC_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_init_adapt_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_INIT_ADAPT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_decr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_IQALIGN_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_frac_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_IQALIGN_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_IQALIGN_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_incr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_IQALIGN_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_IQALIGN_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_pol_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_IQALIGN_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_single_step_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_IQALIGN_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_stable_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_IQALIGN_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_IQALIGN_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_targ_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_itercount_attr == 10'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_latch_delay_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_latch_prepost_delay_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_decr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOFREQAGC_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_frac_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOFREQAGC_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOFREQAGC_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_incr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOFREQAGC_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOFREQAGC_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_pol_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOFREQAGC_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_single_step_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOFREQAGC_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_stable_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOFREQAGC_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOFREQAGC_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_logain_auxvref_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOGAIN_AUXVREF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_logain_dfe_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_logain_edge_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_logain_edgevref_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOGAIN_EDGEVREF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_logain_hifreqagc_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOGAIN_HIFREQAGC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_logain_iqalign_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOGAIN_IQALIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_logain_lofreqagc_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOGAIN_LOFREQAGC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_logain_vga_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOGAIN_VGA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_auxvref_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_dfe1_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_dfe23_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_dfe4p_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_edge2_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_edge3_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_edge4_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_edgevref_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_hifreqagc_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_iqalign_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_lofreqagc_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_vga_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_nrz_to_pam4_mode_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_NRZ_TO_PAM4_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_slow_blockcnt_attr == 16'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_start_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_tsettle_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_accum_count_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_accum_level_en_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_decr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_frac_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_incr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_mode_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_pol_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_single_step_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_stable_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_yadjdata_mid_clamp_zero_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_YADJDATA_MID_CLAMP_ZERO_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lofreqagcgain_sel_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LOFREQAGCGAIN_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_caldfedatatap1gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_caldfedatatap2gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_caldfedatatap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_caldfedatatap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_caldfeedgetap2gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_caldfeedgetap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_caldfeedgetap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_lofreqagcgain_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_caldfedatatap1gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_caldfedatatap1gain_attr == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_caldfedatatap1gain_attr == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_shift_auxshft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_shift_capture_trigger_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_SHIFT_CAPTURE_TRIGGER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_shift_clear_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_SHIFT_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_shift_dat_bitsel_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_SHIFT_DAT_BITSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_shift_datashft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_shift_edgeshft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_shift_edgeshft_nrz8b10b_pam16b20b_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_shift_polarity_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_SHIFT_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap10gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap11gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap12gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap13gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap14gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap15gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap16gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap1gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap2gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap5gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap6gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap7gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap8gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap9gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfeedgetap2gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfeedgetap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfeedgetap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_auxvref0_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_auxvref1_attr == 9'd223
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_auxvref2_attr == 9'd339
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_auxvref3_attr == 9'd456
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_caldfedatatap1gain_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_caldfeedgetap2gain_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_calhifreqagcres_attr == 6'd52
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_callofreqagcgain_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_edgevref_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_hifreqvgagain_attr == 7'd77
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_iqalign_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_auxvref0_attr == 9'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_auxvref1_attr == 9'd173
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_auxvref2_attr == 9'd289
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_auxvref3_attr == 9'd356
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_caldfedatatap1gain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_caldfeedgetap2gain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_calhifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_callofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_edgevref_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_iqalign_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqsetnrztopam4_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSETNRZTOPAM4_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqsetnrztopam4_switch_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSETNRZTOPAM4_SWITCH_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqsigdet_pause_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSIGDET_PAUSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqspare0_attr == 32'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqspare1_attr == 32'd15871
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqspare2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqsync2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSYNC2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqsync2flx_rxdatapath_ready_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSYNC2FLX_RXDATAPATH_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqtapctrl_data_tap13to16_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQTAPCTRL_DATA_TAP13TO16_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqtapctrl_data_tap1to4_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQTAPCTRL_DATA_TAP1TO4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqtapctrl_data_tap5to8_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQTAPCTRL_DATA_TAP5TO8_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqtapctrl_data_tap9to12_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQTAPCTRL_DATA_TAP9TO12_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqtapctrl_edge_tap_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQTAPCTRL_EDGE_TAP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqtapctrl_tap1to4gain_dbl_res_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQTAPCTRL_TAP1TO4GAIN_DBL_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqtapctrl_tap5to16gain_dbl_res_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQTAPCTRL_TAP5TO16GAIN_DBL_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvalc_hifreqagcbiasadjust_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvalc_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQVALC_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvalc_midbandzero_locovr_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvalcl_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQVALCL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvalcl_lofreqagcgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap01gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap02gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap03gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap04gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap05gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap06gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap07gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap08gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap09gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap10gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap11gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap12gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap13gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap14gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap15gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap16gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQVALD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvale_caldfeedgetap02gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvale_caldfeedgetap03gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvale_caldfeedgetap04gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvale_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQVALE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1cal_clear_mask_attr == 13'd8184
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_aux0_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_aux1_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_d0_bot_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_d0_mid_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_d0_top_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_d1_bot_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_d1_mid_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_d1_top_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_e0_lo_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_e1_lo_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2cal_clear_mask_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_aux0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_aux1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_d0_bot_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_d0_mid_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_d0_top_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_d1_bot_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_d1_mid_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_d1_top_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_e0_lo_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_e1_lo_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfgcal_calfsmmeas_dlycount_attr == 10'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfgcal_fsmmaxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfgcal_lpfax_coarse_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfgcal_lpfax_fine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxhifreqagc_inputcmadjust_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxhifreqagc_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXHIFREQAGC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcal_clear_mask_attr == 13'd8191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_ctlecmnmode_stg1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_ctlecmnmode_stg2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_ctlecmnmode_stg3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_aux0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_aux1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_d0_bot_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_d0_mid_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_d0_top_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_d1_bot_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_d1_mid_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_d1_top_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_e0_lo_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_e1_lo_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmargin_flx_jit_offset_shift_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmargin_jit_disable_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmargin_jit_enable_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmargin_jit_offset_shift_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmargin_jit_setup_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmargin_volt_comp_mask_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmargin_volt_forcel2d_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXMARGIN_VOLT_FORCEL2D_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmargin_volt_offset_shift_d0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmargin_volt_offset_shift_d1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmarginin_direction_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXMARGININ_DIRECTION_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmarginin_flx_jit_offset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmarginin_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXMARGININ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmarginin_mode_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXMARGININ_MODE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmarginin_offset_change_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXMARGININ_OFFSET_CHANGE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmarginin_offset_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmarginin_start_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXMARGININ_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxsum_cm_vref_attr == 9'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxsum_summer_cmfb_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXSUM_SUMMER_CMFB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxsum_summer_cmfb_ibias_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_dfeyadj_aging_cdrlock2data_loc_ov_attr == SERDES_IP_LANE_RXEQ_L2_CFG_DFEYADJ_AGING_CDRLOCK2DATA_LOC_OV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_dfeyadj_aging_cdrlock2data_loc_ov_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_DFEYADJ_AGING_CDRLOCK2DATA_LOC_OV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_dfeyadj_aging_div_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_dfeyadj_aging_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_DFEYADJ_AGING_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxagc_ctlecomp_filterbypass_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXAGC_CTLECOMP_FILTERBYPASS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxagc_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXAGC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxbgcal_calfsmmeas_dlycount_attr == 10'd392
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxbgcal_clear_mask_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxbgcal_fsmmaxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxbgcal_lpfax_coarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxbgcal_lpfax_fine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxbgcalorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxbgcalorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxbgcalorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_calbiasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_calbiasboost_use_lut_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_CALBIASBOOST_USE_LUT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_callbbiasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_callbbiasboost_use_lut_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_CALLBBIASBOOST_USE_LUT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlecomp_filterbypass_smplrcal_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_CTLECOMP_FILTERBYPASS_SMPLRCAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg1_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg2_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg3_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctleinput_probe_mux_smplrcal_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg1_probe_mux_en_smplrcal_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg1_state_en_smplrcal_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg1_state_en_tfrcal_stg1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg1_state_en_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg1_state_en_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg1_use_stg2code_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_CTLESTG1_USE_STG2CODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg2_probe_mux_en_smplrcal_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg2_state_en_smplrcal_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg2_state_en_tfrcal_stg1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg2_state_en_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg2_state_en_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg3_probe_mux_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg3_state_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg3_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg3_state_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg3_state_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_hifreqagc_n5targin_sel_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_HIFREQAGC_N5TARGIN_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_inputcmadjust_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_inputcmadjust_stg1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_inputcmadjust_stg2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_inputcmadjust_stg3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_sdimode_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_SDIMODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_smplroffset_aux0_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_smplroffset_aux1_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_smplroffset_d0_bot_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_smplroffset_d0_mid_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_smplroffset_d0_top_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_smplroffset_d1_bot_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_smplroffset_d1_mid_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_smplroffset_d1_top_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_tfrtrim_outen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_tfrtrim_outen_tfrcal_stg1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_tfrtrim_outen_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_tfrtrim_outen_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalalign_iqclk_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalalign_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALALIGN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctl_cal_abort_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALCTL_CAL_ABORT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctl_cal_type_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctl_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALCTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctl_post_delay_pow2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctl_pre_delay_pow2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecalctrl_input_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecalctrl_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALCTLECALCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecalctrl_stg1_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecalctrl_stg1_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecalctrl_stg2_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecalctrl_stg2_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecalctrl_stg3_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecalctrl_stg3_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecompoffset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecompoffset_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALCTLECOMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecompoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALCTLECOMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecompoffsetfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALCTLECOMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecompoffsetfsmout_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaldutybkgnd_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALDUTYBKGND_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaldutybkgnd_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALDUTYBKGND_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_biasboost_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_hf1deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_hf1resdcgain_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_hf2cap_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_hf2deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_hf2reszero_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_hf3deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_hf3resdcgain_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_hf4deq_gray_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALEQ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_ctlecmnmode_stg1_finish_side_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALFSM_CTLECMNMODE_STG1_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_ctlecmnmode_stg1_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_ctlecmnmode_stg2_finish_side_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALFSM_CTLECMNMODE_STG2_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_ctlecmnmode_stg2_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_ctlecmnmode_stg3_finish_side_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALFSM_CTLECMNMODE_STG3_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_ctlecmnmode_stg3_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_runcount_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_smplroffset_finish_side_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALFSM_SMPLROFFSET_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_smplroffset_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsmmeas_ctlecmnmode_stg1_invert_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALFSMMEAS_CTLECMNMODE_STG1_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsmmeas_ctlecmnmode_stg2_invert_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALFSMMEAS_CTLECMNMODE_STG2_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsmmeas_ctlecmnmode_stg3_invert_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALFSMMEAS_CTLECMNMODE_STG3_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsmmeas_smplroffset_invert_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALFSMMEAS_SMPLROFFSET_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_ctlecmnmode_stg1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_ctlecmnmode_stg2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_ctlecmnmode_stg3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_aux0_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_aux1_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_d0_bot_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_d0_mid_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_d0_top_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_d1_bot_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_d1_mid_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_d1_top_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_e0_lo_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_e1_lo_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeas_pow2count_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasin_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasin_req_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASIN_REQ_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasin_req_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASIN_REQ_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasin_req_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASIN_REQ_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasout_ack_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASOUT_ACK_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasout_ack_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASOUT_ACK_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasout_ack_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASOUT_ACK_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasout_avg_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASOUT_AVG_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasout_avg_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASOUT_AVG_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasout_avg_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASOUT_AVG_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasout_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaloffsetfsmout_auxdatacomp_offset_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALOFFSETFSMOUT_AUXDATACOMP_OFFSET_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaloffsetfsmout_boost_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALOFFSETFSMOUT_BOOST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaloffsetfsmout_edgecomp_offset_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALOFFSETFSMOUT_EDGECOMP_OFFSET_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaloffsetfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalset_cal_clear_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalset_cal_mode_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALSET_CAL_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalset_cal_req_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALSET_CAL_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalset_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalstat_cal_ack_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALSTAT_CAL_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalstat_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalsummerfsmout_comp_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALSUMMERFSMOUT_COMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalsummerfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALSUMMERFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcdrphd_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCDRPHD_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcdrphd_override_ignore_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCDRPHD_OVERRIDE_IGNORE_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_caloffset_range_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_calstg1offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_calstg1offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_calstg2offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_calstg2offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_calstg3offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_calstg3offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_dccouple_sigpath_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCTLE_DCCOUPLE_SIGPATH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_lbbiasboost_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCTLE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_stg1tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_stg2tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_stg3tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_tfrtrim_outmem_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCTLE_TFRTRIM_OUTMEM_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_tfrtrim_outpen_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCTLE_TFRTRIM_OUTPEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctledc_dccouple_tgate_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCTLEDC_DCCOUPLE_TGATE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctledc_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCTLEDC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxdfe_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXDFE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxdfe_tapgain_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxdfepam_enable_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXDFEPAM_ENABLE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxdfepam_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXDFEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxdpifjit_enb_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXDPIFJIT_ENB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxdpifjit_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXDPIFJIT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxdpifjit_offset_locovr_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqadj_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQADJ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqadj_yadjust_aux0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqadj_yadjust_aux1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqadj_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqadj_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqadj_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqadj_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqadj_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqadj_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqauxxor_amux_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqauxxor_dmux_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqauxxor_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQAUXXOR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcal2flx_pstate_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCAL2FLX_PSTATE_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcal2flx_rate_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCAL2FLX_RATE_MASK_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_16a_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_16b_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_16c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_16d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_16e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_1a_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_1b_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_1c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_1d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_1e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_2a_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_2b_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_2c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_2d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_2e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_4a_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_4b_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_4c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_4d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_4e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_8a_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_8b_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_8c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_8d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_8e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_16a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_16b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_16c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_16d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_16e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_1a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_1b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_1c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_1d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_1e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_2a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_2b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_2c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_2d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_2e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_4a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_4b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_4c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_4d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_4e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_8a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_8b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_8c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_8d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_8e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_16a_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_16b_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_16c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_16d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_16e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_1a_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_1b_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_1c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_1d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_1e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_2a_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_2b_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_2c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_2d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_2e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_4a_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_4b_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_4c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_4d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_4e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_8a_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_8b_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_8c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_8d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_8e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcals_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCALS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcals_offset_datasummer0_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcals_offset_datasummer0_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcals_offset_datasummer1_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcals_offset_datasummer1_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcals_offset_edgesummer0_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcals_offset_edgesummer0_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcals_offset_edgesummer1_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcals_offset_edgesummer1_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcdr_force_ltr_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCDR_FORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcdr_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCDR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqctl_clear_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCTL_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqctl_fg_run_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCTL_FG_RUN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqctlelut_hifreqagcres_ovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCTLELUT_HIFREQAGCRES_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqctlelut_hifreqvgagain_ovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCTLELUT_HIFREQVGAGAIN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqctls_oddeven_tapgain_sel_inv_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCTLS_ODDEVEN_TAPGAIN_SEL_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqctls_static_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCTLS_STATIC_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqdat_aux_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQDAT_AUX_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqdat_edge_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQDAT_EDGE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqdatactl_auxswap_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqdatactl_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQDATACTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqdatarate_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQDATARATE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqdatarate_rx_rate_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqdfeyadj_agingl2r_delay_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqdfeyadj_agingl2r_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQDFEYADJ_AGINGL2R_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqedgeadj_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEDGEADJ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqedgeadj_yadjust_edge0lo_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqedgeadj_yadjust_edge1lo_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm2flx_ehm_done_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHM2FLX_EHM_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm2flx_ehm_done_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHM2FLX_EHM_DONE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm2flx_ehm_err_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHM2FLX_EHM_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm2flx_ehm_err_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHM2FLX_EHM_ERR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm2flx_ehm_fom_locovr_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHM2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_data_extshift_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHM_DATA_EXTSHIFT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_distance_th_50p_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_distance_th_rate_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_err_mask_vf00_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_err_mask_vf01_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_event_rate_vf00_attr == 32'd67108864
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_event_rate_vf01_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_general_in_vf00_attr == 32'd5521424
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_general_in_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_lms_th_50p_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_lms_th_rate_attr == 20'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_mask_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_no_change_th_50p_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_no_change_th_rate_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_reflections_num_50p_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_reflections_num_rate_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_slicer_swap_cb_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHM_SLICER_SWAP_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_sym_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_sym_dly_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_tap_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_test_aux_slicer_val_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_test_hits_th_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjaux_ehm_yadjust_aux0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjaux_ehm_yadjust_aux1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjaux_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJAUX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjauxen_ehm_aux_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJAUXEN_EHM_AUX_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjauxen_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJAUXEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjauxltch_aux_yadj_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJAUXLTCH_AUX_YADJ_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjauxltch_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJAUXLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdata_ehm_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdata_ehm_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdata_ehm_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdata_ehm_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdata_ehm_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdata_ehm_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdata_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdataen_ehm_data_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJDATAEN_EHM_DATA_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdataen_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJDATAEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdataltch_data_yadj_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJDATALTCH_DATA_YADJ_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdataltch_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJDATALTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2ehm_ehm_run_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2EHM_EHM_RUN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2ehm_ehm_run_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2EHM_EHM_RUN_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2lms_coarse_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2LMS_COARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2lms_ctrl_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2LMS_CTRL_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2lms_dfecore_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2LMS_DFECORE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2lms_force_evrefupd_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2LMS_FORCE_EVREFUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2lms_freeze_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2LMS_FREEZE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2lms_incr_decr_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2LMS_INCR_DECR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2lms_mu_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2LMS_MU_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2lms_rst_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2LMS_RST_OVRDEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2ofc_ofc_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2OFC_OFC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2ofc_ofc_en_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2OFC_OFC_EN_OVRDEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx_pcs_rxeq_clr_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX_PCS_RXEQ_CLR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx_pcs_rxeq_start_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX_PCS_RXEQ_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx_pcs_rxeq_static_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX_PCS_RXEQ_STATIC_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx_rxrate2pcie1_map_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx_rxrate2pcie2_map_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx_rxrate2pcie3_map_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx_rxrate2pcie4_map_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxehmdata_ehm_data_slc_sel_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXEHMDATA_EHM_DATA_SLC_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxehmdata_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXEHMDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxfsm_generalpurpose_reg_in_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxfsm_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXFSM_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxfsm_pause_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXFSM_PAUSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxfsm_state_obs_hold_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXFSM_STATE_OBS_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxfsm_state_obs_sel_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXFSM_STATE_OBS_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxltr_force_ltr_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXLTR_FORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxltr_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXLTR_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxpcsrxeyediag_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXPCSRXEYEDIAG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxpcsrxeyediag_start_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXPCSRXEYEDIAG_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxsigdet_sel_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXSIGDET_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqfsm2ofc_ofc_cal_req_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFSM2OFC_OFC_CAL_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqfsm2ofc_ofc_cal_req_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFSM2OFC_OFC_CAL_REQ_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_16a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_16b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_16c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_16d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_16e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_1a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_1b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_1c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_1d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_1e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_2a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_2b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_2c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_2d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_2e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_4a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_4b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_4c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_4d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_4e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_8a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_8b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_8c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_8d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_8e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_done_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmax_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmax_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_SATMAX_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmax_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmax_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmax_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_SATMAX_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmax_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_SATMAX_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmax_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_SATMAX_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmin_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmin_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_SATMIN_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmin_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmin_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmin_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_SATMIN_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmin_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_SATMIN_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmin_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_SATMIN_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_stable_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_stable_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_STABLE_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_stable_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_stable_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_stable_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_STABLE_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_stable_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_STABLE_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_stable_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_STABLE_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsupd_chng_ack_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSUPD_CHNG_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsupd_chng_req_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSUPD_CHNG_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsupd_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSUPD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjaux_lms_vref0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjaux_lms_vref1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjaux_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJAUX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjauxen_lms_aux_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJAUXEN_LMS_AUX_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjauxen_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJAUXEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjauxltch_lms_aux_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJAUXLTCH_LMS_AUX_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjauxltch_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJAUXLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdata_lms_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdata_lms_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdata_lms_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdata_lms_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdata_lms_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdata_lms_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdata_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdataen_lms_data_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJDATAEN_LMS_DATA_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdataen_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJDATAEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdataltch_lms_data_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJDATALTCH_LMS_DATA_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdataltch_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJDATALTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjedge_lms_yadjust_edge0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjedge_lms_yadjust_edge1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjedge_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJEDGE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjedgeen_lms_edge_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJEDGEEN_LMS_EDGE_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjedgeen_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJEDGEEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjedgeltch_lms_edge_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJEDGELTCH_LMS_EDGE_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjedgeltch_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJEDGELTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqltch_dfe_aux_yadj_b_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLTCH_DFE_AUX_YADJ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqltch_dfe_b_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLTCH_DFE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqltch_dfe_data_yadj_b_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLTCH_DFE_DATA_YADJ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqltch_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqltchc_auxswap_b_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLTCHC_AUXSWAP_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqltchc_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLTCHC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofc2flx_ofc_cal_done_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQOFC2FLX_OFC_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofc2flx_ofc_cal_done_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQOFC2FLX_OFC_CAL_DONE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_ctle_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_ctle_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_ctle_rxstg1probemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_ctle_rxstg2_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_ctle_rxstg2probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_ctle_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_ctle_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_summer_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_summer_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_summer_rxstg1probemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_summer_rxstg2_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_summer_rxstg2probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_summer_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_summer_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_time_h_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_time_l_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_ctle_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_ctle_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_ctle_rxstg1probemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_ctle_rxstg2_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_ctle_rxstg2probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_ctle_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_ctle_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_summer_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_summer_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_summer_rxstg1probemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_summer_rxstg2_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_summer_rxstg2probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_summer_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_summer_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_time_l_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_compsel_ctle_st1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_compsel_ctle_st2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_compsel_ctle_st3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_compsel_idle_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_compsel_sa_d0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_compsel_sa_d1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_compsel_sa_e0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_compsel_sa_e1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_invert_comp_fb_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_lpexitcal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_lpexitcal_time_l_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_adapt_en_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_adapt_thr_sel_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_cal_en_attr == 8'd249
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_cal_thr_sel_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_data_disp_sticky_clr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQOFCCFG_OFC_DATA_DISP_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_disparity_disable_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQOFCCFG_OFC_DISPARITY_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_disparity_leak_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_disparity_thr_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_lpexitcal_en_attr == 8'd249
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_lpf_bypass_en_cb_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQOFCCFG_OFC_LPF_BYPASS_EN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_ratechangecal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_pre_timer_setting_pow2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ratechangecal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ratechangecal_time_l_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_rxinpprobemuxen_idle_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_rxstg1_stateen_idle_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_rxstg1probemuxen_idle_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_rxstg2_stateen_idle_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_rxstg2probemuxen_idle_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_rxstg3_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_rxstg3probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqout_init_restore_avail_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQOUT_INIT_RESTORE_AVAIL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqprecal_code_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqprecal_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQPRECAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_hf1deq_dir_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_BOOSTLUT_HF1DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_hf2deq_dir_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_BOOSTLUT_HF2DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_hf2reszero_dir_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_BOOSTLUT_HF2RESZERO_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_hf3deq_dir_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_BOOSTLUT_HF3DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_idx_hf1deq_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_idx_hf1deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_idx_hf2deq_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_idx_hf2deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_idx_hf2reszero_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_idx_hf2reszero_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_idx_hf3deq_vf00_attr == 32'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_idx_hf3deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_init_hf1deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_init_hf2deq_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_init_hf2reszero_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_init_hf3deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_cal_hifreqagcres_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_cal_hifreqvgagain_attr == 7'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_cal_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_cal_yadjust_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_biasboost_dir_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_GAINLUT_BIASBOOST_DIR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_hf1resdcgain_dir_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_GAINLUT_HF1RESDCGAIN_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_hf3resdcgain_dir_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_GAINLUT_HF3RESDCGAIN_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_biasboost_vf00_attr == 32'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_biasboost_vf01_attr == 32'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_biasboost_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_lbbiasboost_vf00_attr == 32'd268435454
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_lbbiasboost_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_lbbiasboost_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_init_biasboost_attr == 5'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_init_hf1resdcgain_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_init_hf3resdcgain_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_init_lbbiasboost_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_lbbiasboost_dir_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_GAINLUT_LBBIASBOOST_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_latch_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref0_initval_attr == 9'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref1_initval_attr == 9'd191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref2_initval_attr == 9'd321
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref3_initval_attr == 9'd451
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_decr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_AUXVREF_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_frac_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_AUXVREF_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_frac_reset_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_incr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_AUXVREF_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_incr_decr_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_pam4adj_swizzle_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_AUXVREF_PAM4ADJ_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_AUXVREF_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_pol_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_single_step_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_AUXVREF_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_stable_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_AUXVREF_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_AUXVREF_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_targ_0_hi_attr == 9'd160
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_targ_0_lo_attr == 9'd140
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_auxvref_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_auxvref_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_dfe_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_dfe_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_edge_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_edge_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_edgevref_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_edgevref_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_iqalign_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_iqalign_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_level_vga_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_vga_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_vga_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_blockcount_fast_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_BLOCKCOUNT_FAST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_coarse_detect_clear_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_COARSE_DETECT_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_coarse_detect_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_COARSE_DETECT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_continuous_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_CONTINUOUS_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_datastats_incr_decr_swizzle_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_DATASTATS_INCR_DECR_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_datastats_pol_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_DATASTATS_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_datastats_thres_attr == 16'd1023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe1_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe2_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe3_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe4p_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_core_sel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_decr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_DFE_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_frac_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_DFE_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_frac_reset_mask_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_incr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_DFE_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_incr_decr_mask_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_inner_lvl_filter_en_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_DFE_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_pol_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_single_step_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_DFE_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_stable_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_DFE_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_DFE_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_targtap1_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_targtap2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_targtap3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_targtap4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_decr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGE_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_frac_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGE_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_frac_reset_mask_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_incr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGE_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_incr_decr_mask_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGE_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_pol_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_single_step_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGE_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_stable_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGE_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGE_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_decr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGEVREF_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_frac_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGEVREF_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGEVREF_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_incr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGEVREF_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_initval_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGEVREF_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_pol_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGEVREF_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_single_step_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGEVREF_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_stable_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGEVREF_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGEVREF_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_fast_blockcnt_attr == 16'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_filter_mode_auxvref_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_filter_mode_dfe_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_filter_mode_edge_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_filter_mode_edgevref_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_filter_mode_iqalign_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_filter_mode_vga_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_freeze_auxvrefupd_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_freeze_dfeupd_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_freeze_edgeupd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_freeze_edgevrefupd_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_FREEZE_EDGEVREFUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_freeze_forcebg_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_FREEZE_FORCEBG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_freeze_hifreqagcupd_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_FREEZE_HIFREQAGCUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_freeze_iqalignupd_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_FREEZE_IQALIGNUPD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_freeze_lofreqagcupd_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_FREEZE_LOFREQAGCUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_freeze_vgaupd_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_FREEZE_VGAUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_gated_update_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_GATED_UPDATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_accum_count_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_accum_level_en_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_decr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_HIFREQAGC_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_frac_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_HIFREQAGC_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_HIFREQAGC_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_incr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_HIFREQAGC_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_n1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_n2_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_n3_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_n4_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_n5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_HIFREQAGC_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_pol_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_HIFREQAGC_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_single_step_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_HIFREQAGC_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_stable_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_HIFREQAGC_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_HIFREQAGC_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_init_adapt_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_INIT_ADAPT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_decr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_IQALIGN_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_frac_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_IQALIGN_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_IQALIGN_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_incr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_IQALIGN_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_IQALIGN_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_pol_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_IQALIGN_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_single_step_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_IQALIGN_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_stable_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_IQALIGN_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_IQALIGN_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_targ_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_itercount_attr == 10'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_latch_delay_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_latch_prepost_delay_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_decr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOFREQAGC_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_frac_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOFREQAGC_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOFREQAGC_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_incr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOFREQAGC_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOFREQAGC_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_pol_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOFREQAGC_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_single_step_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOFREQAGC_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_stable_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOFREQAGC_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOFREQAGC_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_logain_auxvref_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOGAIN_AUXVREF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_logain_dfe_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_logain_edge_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_logain_edgevref_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOGAIN_EDGEVREF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_logain_hifreqagc_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOGAIN_HIFREQAGC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_logain_iqalign_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOGAIN_IQALIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_logain_lofreqagc_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOGAIN_LOFREQAGC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_logain_vga_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOGAIN_VGA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_auxvref_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_dfe1_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_dfe23_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_dfe4p_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_edge2_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_edge3_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_edge4_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_edgevref_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_hifreqagc_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_iqalign_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_lofreqagc_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_vga_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_nrz_to_pam4_mode_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_NRZ_TO_PAM4_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_slow_blockcnt_attr == 16'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_start_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_tsettle_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_accum_count_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_accum_level_en_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_decr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_frac_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_incr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_mode_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_pol_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_single_step_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_stable_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_yadjdata_mid_clamp_zero_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_YADJDATA_MID_CLAMP_ZERO_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lofreqagcgain_sel_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LOFREQAGCGAIN_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_caldfedatatap1gain_attr == 6'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_caldfedatatap2gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_caldfedatatap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_caldfedatatap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_caldfeedgetap2gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_caldfeedgetap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_caldfeedgetap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_hifreqagcres_attr == 6'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_hifreqvgagain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_caldfedatatap1gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_caldfedatatap1gain_attr == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_caldfedatatap1gain_attr == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_shift_auxshft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_shift_capture_trigger_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_SHIFT_CAPTURE_TRIGGER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_shift_clear_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_SHIFT_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_shift_dat_bitsel_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_SHIFT_DAT_BITSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_shift_datashft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_shift_edgeshft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_shift_edgeshft_nrz8b10b_pam16b20b_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_shift_polarity_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_SHIFT_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap10gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap11gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap12gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap13gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap14gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap15gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap16gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap1gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap2gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap5gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap6gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap7gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap8gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap9gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfeedgetap2gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfeedgetap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfeedgetap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_hifreqvgagain_attr == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_auxvref0_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_auxvref1_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_auxvref2_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_auxvref3_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_caldfedatatap1gain_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_caldfeedgetap2gain_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_calhifreqagcres_attr == 6'd38
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_callofreqagcgain_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_edgevref_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_hifreqvgagain_attr == 7'd45
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_iqalign_attr == 6'd45
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_auxvref0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_auxvref1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_auxvref2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_auxvref3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_caldfedatatap1gain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_caldfeedgetap2gain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_calhifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_callofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_edgevref_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_iqalign_attr == 6'd21
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqsetnrztopam4_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSETNRZTOPAM4_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqsetnrztopam4_switch_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSETNRZTOPAM4_SWITCH_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqsigdet_pause_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSIGDET_PAUSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqspare0_attr == 32'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqspare1_attr == 32'd15871
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqspare2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqsync2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSYNC2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqsync2flx_rxdatapath_ready_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSYNC2FLX_RXDATAPATH_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqtapctrl_data_tap13to16_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQTAPCTRL_DATA_TAP13TO16_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqtapctrl_data_tap1to4_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQTAPCTRL_DATA_TAP1TO4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqtapctrl_data_tap5to8_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQTAPCTRL_DATA_TAP5TO8_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqtapctrl_data_tap9to12_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQTAPCTRL_DATA_TAP9TO12_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqtapctrl_edge_tap_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQTAPCTRL_EDGE_TAP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqtapctrl_tap1to4gain_dbl_res_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQTAPCTRL_TAP1TO4GAIN_DBL_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqtapctrl_tap5to16gain_dbl_res_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQTAPCTRL_TAP5TO16GAIN_DBL_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvalc_hifreqagcbiasadjust_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvalc_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQVALC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvalc_midbandzero_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvalcl_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQVALCL_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvalcl_lofreqagcgain_locovr_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap01gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap02gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap03gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap04gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap05gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap06gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap07gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap08gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap09gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap10gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap11gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap12gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap13gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap14gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap15gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap16gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQVALD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvale_caldfeedgetap02gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvale_caldfeedgetap03gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvale_caldfeedgetap04gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvale_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQVALE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1cal_clear_mask_attr == 13'd8184
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_aux0_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_aux1_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_d0_bot_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_d0_mid_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_d0_top_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_d1_bot_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_d1_mid_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_d1_top_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_e0_lo_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_e1_lo_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2cal_clear_mask_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_aux0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_aux1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_d0_bot_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_d0_mid_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_d0_top_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_d1_bot_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_d1_mid_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_d1_top_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_e0_lo_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_e1_lo_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfgcal_calfsmmeas_dlycount_attr == 10'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfgcal_fsmmaxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfgcal_lpfax_coarse_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfgcal_lpfax_fine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxhifreqagc_inputcmadjust_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxhifreqagc_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXHIFREQAGC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcal_clear_mask_attr == 13'd8191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_ctlecmnmode_stg3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_aux0_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_aux1_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_d0_bot_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_d0_mid_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_d0_top_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_d1_bot_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_d1_mid_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_d1_top_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_e0_lo_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_e1_lo_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmargin_flx_jit_offset_shift_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmargin_jit_disable_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmargin_jit_enable_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmargin_jit_offset_shift_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmargin_jit_setup_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmargin_volt_comp_mask_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmargin_volt_forcel2d_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXMARGIN_VOLT_FORCEL2D_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmargin_volt_offset_shift_d0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmargin_volt_offset_shift_d1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmarginin_direction_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXMARGININ_DIRECTION_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmarginin_flx_jit_offset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmarginin_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXMARGININ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmarginin_mode_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXMARGININ_MODE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmarginin_offset_change_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXMARGININ_OFFSET_CHANGE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmarginin_offset_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmarginin_start_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXMARGININ_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxsum_cm_vref_attr == 9'd75
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxsum_summer_cmfb_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXSUM_SUMMER_CMFB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxsum_summer_cmfb_ibias_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_dfeyadj_aging_cdrlock2data_loc_ov_attr == SERDES_IP_LANE_RXEQ_L3_CFG_DFEYADJ_AGING_CDRLOCK2DATA_LOC_OV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_dfeyadj_aging_cdrlock2data_loc_ov_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_DFEYADJ_AGING_CDRLOCK2DATA_LOC_OV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_dfeyadj_aging_div_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_dfeyadj_aging_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_DFEYADJ_AGING_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxagc_ctlecomp_filterbypass_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXAGC_CTLECOMP_FILTERBYPASS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxagc_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXAGC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxbgcal_calfsmmeas_dlycount_attr == 10'd392
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxbgcal_clear_mask_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxbgcal_fsmmaxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxbgcal_lpfax_coarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxbgcal_lpfax_fine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxbgcalorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxbgcalorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxbgcalorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_calbiasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_calbiasboost_use_lut_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_CALBIASBOOST_USE_LUT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_callbbiasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_callbbiasboost_use_lut_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_CALLBBIASBOOST_USE_LUT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlecomp_filterbypass_smplrcal_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_CTLECOMP_FILTERBYPASS_SMPLRCAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg1_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg2_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg3_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctleinput_probe_mux_smplrcal_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg1_probe_mux_en_smplrcal_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg1_state_en_smplrcal_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg1_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg1_state_en_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg1_state_en_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg1_use_stg2code_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_CTLESTG1_USE_STG2CODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg2_probe_mux_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg2_state_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg2_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg2_state_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg2_state_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg3_probe_mux_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg3_state_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg3_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg3_state_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg3_state_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_hifreqagc_n5targin_sel_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_HIFREQAGC_N5TARGIN_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_inputcmadjust_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_inputcmadjust_stg1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_inputcmadjust_stg2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_inputcmadjust_stg3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_sdimode_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_SDIMODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_smplroffset_aux0_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_smplroffset_aux1_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_smplroffset_d0_bot_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_smplroffset_d0_mid_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_smplroffset_d0_top_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_smplroffset_d1_bot_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_smplroffset_d1_mid_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_smplroffset_d1_top_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_tfrtrim_outen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_tfrtrim_outen_tfrcal_stg1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_tfrtrim_outen_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_tfrtrim_outen_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalalign_iqclk_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalalign_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALALIGN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctl_cal_abort_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALCTL_CAL_ABORT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctl_cal_type_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctl_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALCTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctl_post_delay_pow2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctl_pre_delay_pow2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecalctrl_input_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecalctrl_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALCTLECALCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecalctrl_stg1_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecalctrl_stg1_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecalctrl_stg2_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecalctrl_stg2_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecalctrl_stg3_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecalctrl_stg3_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecompoffset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecompoffset_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALCTLECOMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecompoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALCTLECOMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecompoffsetfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALCTLECOMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecompoffsetfsmout_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaldutybkgnd_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALDUTYBKGND_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaldutybkgnd_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALDUTYBKGND_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_biasboost_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_hf1deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_hf1resdcgain_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_hf2cap_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_hf2deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_hf2reszero_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_hf3deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_hf3resdcgain_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_hf4deq_gray_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALEQ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_ctlecmnmode_stg1_finish_side_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALFSM_CTLECMNMODE_STG1_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_ctlecmnmode_stg1_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_ctlecmnmode_stg2_finish_side_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALFSM_CTLECMNMODE_STG2_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_ctlecmnmode_stg2_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_ctlecmnmode_stg3_finish_side_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALFSM_CTLECMNMODE_STG3_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_ctlecmnmode_stg3_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_runcount_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_smplroffset_finish_side_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALFSM_SMPLROFFSET_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_smplroffset_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsmmeas_ctlecmnmode_stg1_invert_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALFSMMEAS_CTLECMNMODE_STG1_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsmmeas_ctlecmnmode_stg2_invert_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALFSMMEAS_CTLECMNMODE_STG2_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsmmeas_ctlecmnmode_stg3_invert_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALFSMMEAS_CTLECMNMODE_STG3_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsmmeas_smplroffset_invert_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALFSMMEAS_SMPLROFFSET_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_ctlecmnmode_stg1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_ctlecmnmode_stg2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_ctlecmnmode_stg3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_aux0_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_aux1_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_d0_bot_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_d0_mid_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_d0_top_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_d1_bot_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_d1_mid_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_d1_top_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_e0_lo_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_e1_lo_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeas_pow2count_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasin_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasin_req_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASIN_REQ_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasin_req_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASIN_REQ_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasin_req_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASIN_REQ_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasout_ack_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASOUT_ACK_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasout_ack_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASOUT_ACK_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasout_ack_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASOUT_ACK_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasout_avg_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASOUT_AVG_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasout_avg_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASOUT_AVG_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasout_avg_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASOUT_AVG_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasout_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaloffsetfsmout_auxdatacomp_offset_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALOFFSETFSMOUT_AUXDATACOMP_OFFSET_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaloffsetfsmout_boost_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALOFFSETFSMOUT_BOOST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaloffsetfsmout_edgecomp_offset_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALOFFSETFSMOUT_EDGECOMP_OFFSET_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaloffsetfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalset_cal_clear_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalset_cal_mode_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALSET_CAL_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalset_cal_req_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALSET_CAL_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalset_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalstat_cal_ack_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALSTAT_CAL_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalstat_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalsummerfsmout_comp_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALSUMMERFSMOUT_COMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalsummerfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALSUMMERFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcdrphd_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCDRPHD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcdrphd_override_ignore_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCDRPHD_OVERRIDE_IGNORE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_caloffset_range_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_calstg1offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_calstg1offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_calstg2offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_calstg2offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_calstg3offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_calstg3offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_dccouple_sigpath_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCTLE_DCCOUPLE_SIGPATH_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_lbbiasboost_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCTLE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_stg1tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_stg2tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_stg3tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_tfrtrim_outmem_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCTLE_TFRTRIM_OUTMEM_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_tfrtrim_outpen_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCTLE_TFRTRIM_OUTPEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctledc_dccouple_tgate_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCTLEDC_DCCOUPLE_TGATE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctledc_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCTLEDC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxdfe_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXDFE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxdfe_tapgain_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxdfepam_enable_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXDFEPAM_ENABLE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxdfepam_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXDFEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxdpifjit_enb_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXDPIFJIT_ENB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxdpifjit_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXDPIFJIT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxdpifjit_offset_locovr_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqadj_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQADJ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqadj_yadjust_aux0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqadj_yadjust_aux1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqadj_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqadj_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqadj_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqadj_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqadj_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqadj_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqauxxor_amux_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqauxxor_dmux_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqauxxor_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQAUXXOR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcal2flx_pstate_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCAL2FLX_PSTATE_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcal2flx_rate_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCAL2FLX_RATE_MASK_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_16a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_16b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_16c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_16d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_16e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_1a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_1b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_1c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_1d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_1e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_2a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_2b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_2c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_2d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_2e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_4a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_4b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_4c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_4d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_4e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_8a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_8b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_8c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_8d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_8e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_16a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_16b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_16c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_16d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_16e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_1a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_1b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_1c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_1d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_1e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_2a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_2b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_2c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_2d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_2e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_4a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_4b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_4c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_4d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_4e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_8a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_8b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_8c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_8d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_8e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_16a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_16b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_16c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_16d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_16e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_1a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_1b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_1c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_1d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_1e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_2a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_2b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_2c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_2d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_2e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_4a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_4b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_4c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_4d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_4e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_8a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_8b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_8c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_8d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_8e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcals_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCALS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcals_offset_datasummer0_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcals_offset_datasummer0_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcals_offset_datasummer1_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcals_offset_datasummer1_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcals_offset_edgesummer0_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcals_offset_edgesummer0_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcals_offset_edgesummer1_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcals_offset_edgesummer1_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcdr_force_ltr_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCDR_FORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcdr_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCDR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqctl_clear_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCTL_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqctl_fg_run_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCTL_FG_RUN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqctlelut_hifreqagcres_ovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCTLELUT_HIFREQAGCRES_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqctlelut_hifreqvgagain_ovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCTLELUT_HIFREQVGAGAIN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqctls_oddeven_tapgain_sel_inv_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCTLS_ODDEVEN_TAPGAIN_SEL_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqctls_static_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCTLS_STATIC_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqdat_aux_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQDAT_AUX_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqdat_edge_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQDAT_EDGE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqdatactl_auxswap_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqdatactl_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQDATACTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqdatarate_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQDATARATE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqdatarate_rx_rate_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqdfeyadj_agingl2r_delay_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqdfeyadj_agingl2r_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQDFEYADJ_AGINGL2R_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqedgeadj_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEDGEADJ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqedgeadj_yadjust_edge0lo_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqedgeadj_yadjust_edge1lo_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm2flx_ehm_done_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHM2FLX_EHM_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm2flx_ehm_done_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHM2FLX_EHM_DONE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm2flx_ehm_err_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHM2FLX_EHM_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm2flx_ehm_err_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHM2FLX_EHM_ERR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm2flx_ehm_fom_locovr_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHM2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_data_extshift_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHM_DATA_EXTSHIFT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_distance_th_50p_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_distance_th_rate_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_err_mask_vf00_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_err_mask_vf01_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_event_rate_vf00_attr == 32'd67108864
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_event_rate_vf01_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_general_in_vf00_attr == 32'd5505024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_general_in_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_lms_th_50p_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_lms_th_rate_attr == 20'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_mask_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_no_change_th_50p_attr == 12'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_no_change_th_rate_attr == 12'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_reflections_num_50p_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_reflections_num_rate_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_slicer_swap_cb_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHM_SLICER_SWAP_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_sym_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_sym_dly_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_tap_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_test_aux_slicer_val_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_test_hits_th_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjaux_ehm_yadjust_aux0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjaux_ehm_yadjust_aux1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjaux_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJAUX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjauxen_ehm_aux_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJAUXEN_EHM_AUX_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjauxen_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJAUXEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjauxltch_aux_yadj_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJAUXLTCH_AUX_YADJ_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjauxltch_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJAUXLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdata_ehm_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdata_ehm_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdata_ehm_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdata_ehm_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdata_ehm_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdata_ehm_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdata_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdataen_ehm_data_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJDATAEN_EHM_DATA_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdataen_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJDATAEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdataltch_data_yadj_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJDATALTCH_DATA_YADJ_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdataltch_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJDATALTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2ehm_ehm_run_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2EHM_EHM_RUN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2ehm_ehm_run_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2EHM_EHM_RUN_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2lms_coarse_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2LMS_COARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2lms_ctrl_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2LMS_CTRL_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2lms_dfecore_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2LMS_DFECORE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2lms_force_evrefupd_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2LMS_FORCE_EVREFUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2lms_freeze_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2LMS_FREEZE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2lms_incr_decr_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2LMS_INCR_DECR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2lms_mu_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2LMS_MU_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2lms_rst_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2LMS_RST_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2ofc_ofc_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2OFC_OFC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2ofc_ofc_en_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2OFC_OFC_EN_OVRDEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx_pcs_rxeq_clr_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX_PCS_RXEQ_CLR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx_pcs_rxeq_start_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX_PCS_RXEQ_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx_pcs_rxeq_static_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX_PCS_RXEQ_STATIC_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx_rxrate2pcie1_map_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx_rxrate2pcie2_map_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx_rxrate2pcie3_map_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx_rxrate2pcie4_map_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxehmdata_ehm_data_slc_sel_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXEHMDATA_EHM_DATA_SLC_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxehmdata_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXEHMDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxfsm_generalpurpose_reg_in_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxfsm_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXFSM_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxfsm_pause_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXFSM_PAUSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxfsm_state_obs_hold_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXFSM_STATE_OBS_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxfsm_state_obs_sel_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXFSM_STATE_OBS_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxltr_force_ltr_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXLTR_FORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxltr_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXLTR_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxpcsrxeyediag_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXPCSRXEYEDIAG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxpcsrxeyediag_start_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXPCSRXEYEDIAG_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxsigdet_sel_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXSIGDET_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqfsm2ofc_ofc_cal_req_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFSM2OFC_OFC_CAL_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqfsm2ofc_ofc_cal_req_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFSM2OFC_OFC_CAL_REQ_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_16a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_16b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_16c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_16d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_16e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_1a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_1b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_1c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_1d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_1e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_2a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_2b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_2c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_2d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_2e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_4a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_4b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_4c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_4d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_4e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_8a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_8b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_8c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_8d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_8e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_done_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmax_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmax_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_SATMAX_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmax_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmax_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmax_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_SATMAX_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmax_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_SATMAX_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmax_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_SATMAX_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmin_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmin_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_SATMIN_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmin_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmin_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmin_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_SATMIN_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmin_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_SATMIN_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmin_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_SATMIN_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_stable_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_stable_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_STABLE_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_stable_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_stable_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_stable_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_STABLE_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_stable_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_STABLE_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_stable_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_STABLE_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsupd_chng_ack_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSUPD_CHNG_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsupd_chng_req_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSUPD_CHNG_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsupd_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSUPD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjaux_lms_vref0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjaux_lms_vref1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjaux_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJAUX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjauxen_lms_aux_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJAUXEN_LMS_AUX_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjauxen_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJAUXEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjauxltch_lms_aux_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJAUXLTCH_LMS_AUX_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjauxltch_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJAUXLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdata_lms_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdata_lms_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdata_lms_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdata_lms_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdata_lms_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdata_lms_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdata_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdataen_lms_data_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJDATAEN_LMS_DATA_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdataen_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJDATAEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdataltch_lms_data_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJDATALTCH_LMS_DATA_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdataltch_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJDATALTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjedge_lms_yadjust_edge0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjedge_lms_yadjust_edge1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjedge_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJEDGE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjedgeen_lms_edge_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJEDGEEN_LMS_EDGE_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjedgeen_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJEDGEEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjedgeltch_lms_edge_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJEDGELTCH_LMS_EDGE_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjedgeltch_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJEDGELTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqltch_dfe_aux_yadj_b_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLTCH_DFE_AUX_YADJ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqltch_dfe_b_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLTCH_DFE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqltch_dfe_data_yadj_b_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLTCH_DFE_DATA_YADJ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqltch_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqltchc_auxswap_b_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLTCHC_AUXSWAP_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqltchc_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLTCHC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofc2flx_ofc_cal_done_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQOFC2FLX_OFC_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofc2flx_ofc_cal_done_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQOFC2FLX_OFC_CAL_DONE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_ctle_rxinpprobemuxen_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_ctle_rxstg1_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_ctle_rxstg1probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_ctle_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_ctle_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_ctle_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_ctle_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_summer_rxinpprobemuxen_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_summer_rxstg1_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_summer_rxstg1probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_summer_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_summer_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_summer_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_summer_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_time_h_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_time_l_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_ctle_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_ctle_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_ctle_rxstg1probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_ctle_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_ctle_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_ctle_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_ctle_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_summer_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_summer_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_summer_rxstg1probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_summer_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_summer_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_summer_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_summer_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_time_l_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_compsel_ctle_st1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_compsel_ctle_st2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_compsel_ctle_st3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_compsel_idle_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_compsel_sa_d0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_compsel_sa_d1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_compsel_sa_e0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_compsel_sa_e1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_invert_comp_fb_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_lpexitcal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_lpexitcal_time_l_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_adapt_en_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_adapt_thr_sel_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_cal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_cal_thr_sel_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_data_disp_sticky_clr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQOFCCFG_OFC_DATA_DISP_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_disparity_disable_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQOFCCFG_OFC_DISPARITY_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_disparity_leak_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_disparity_thr_sel_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_lpexitcal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_lpf_bypass_en_cb_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQOFCCFG_OFC_LPF_BYPASS_EN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_ratechangecal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_pre_timer_setting_pow2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ratechangecal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ratechangecal_time_l_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_rxinpprobemuxen_idle_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_rxstg1_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_rxstg1probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_rxstg2_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_rxstg2probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_rxstg3_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_rxstg3probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqout_init_restore_avail_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQOUT_INIT_RESTORE_AVAIL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqprecal_code_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqprecal_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQPRECAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_hf1deq_dir_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_BOOSTLUT_HF1DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_hf2deq_dir_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_BOOSTLUT_HF2DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_hf2reszero_dir_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_BOOSTLUT_HF2RESZERO_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_hf3deq_dir_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_BOOSTLUT_HF3DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_idx_hf1deq_vf00_attr == 32'd599186
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_idx_hf1deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_idx_hf2deq_vf00_attr == 32'd1198372
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_idx_hf2deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_idx_hf2reszero_vf00_attr == 32'd4290772992
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_idx_hf2reszero_vf01_attr == 21'd2097151
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_idx_hf3deq_vf00_attr == 32'd2396744
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_idx_hf3deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_init_hf1deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_init_hf2deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_init_hf2reszero_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_init_hf3deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_cal_hifreqagcres_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_cal_hifreqvgagain_attr == 7'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_cal_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_cal_yadjust_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_biasboost_dir_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_GAINLUT_BIASBOOST_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_hf1resdcgain_dir_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_GAINLUT_HF1RESDCGAIN_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_hf3resdcgain_dir_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_GAINLUT_HF3RESDCGAIN_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_biasboost_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_biasboost_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_biasboost_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf00_attr == 32'd2863311530
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf01_attr == 32'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf00_attr == 32'd1431655764
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf01_attr == 32'd1431655765
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_lbbiasboost_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_lbbiasboost_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_lbbiasboost_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_init_biasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_init_hf1resdcgain_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_init_hf3resdcgain_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_init_lbbiasboost_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_lbbiasboost_dir_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_GAINLUT_LBBIASBOOST_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_latch_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref0_initval_attr == 9'd61
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref1_initval_attr == 9'd191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref2_initval_attr == 9'd321
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref3_initval_attr == 9'd451
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_decr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_AUXVREF_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_frac_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_AUXVREF_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_frac_reset_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_incr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_AUXVREF_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_incr_decr_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_pam4adj_swizzle_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_AUXVREF_PAM4ADJ_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_AUXVREF_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_pol_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_single_step_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_AUXVREF_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_stable_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_AUXVREF_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_AUXVREF_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_targ_0_hi_attr == 9'd149
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_targ_0_lo_attr == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_auxvref_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_auxvref_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_dfe_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_dfe_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_edge_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_edge_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_edgevref_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_edgevref_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_iqalign_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_iqalign_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_level_vga_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_vga_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_vga_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_blockcount_fast_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_BLOCKCOUNT_FAST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_coarse_detect_clear_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_COARSE_DETECT_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_coarse_detect_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_COARSE_DETECT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_continuous_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_CONTINUOUS_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_datastats_incr_decr_swizzle_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_DATASTATS_INCR_DECR_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_datastats_pol_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_DATASTATS_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_datastats_thres_attr == 16'd1023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe1_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe2_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe3_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe4p_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_core_sel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_decr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_DFE_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_frac_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_DFE_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_frac_reset_mask_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_incr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_DFE_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_incr_decr_mask_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_inner_lvl_filter_en_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_DFE_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_pol_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_single_step_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_DFE_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_stable_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_DFE_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_DFE_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_targtap1_attr == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_targtap2_attr == 7'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_targtap3_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_targtap4_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_decr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGE_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_frac_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGE_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_frac_reset_mask_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_incr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGE_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_incr_decr_mask_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGE_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_pol_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_single_step_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGE_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_stable_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGE_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGE_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_decr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGEVREF_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_frac_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGEVREF_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGEVREF_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_incr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGEVREF_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_initval_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGEVREF_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_pol_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGEVREF_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_single_step_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGEVREF_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_stable_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGEVREF_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGEVREF_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_fast_blockcnt_attr == 16'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_filter_mode_auxvref_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_filter_mode_dfe_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_filter_mode_edge_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_filter_mode_edgevref_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_filter_mode_iqalign_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_filter_mode_vga_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_freeze_auxvrefupd_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_freeze_dfeupd_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_freeze_edgeupd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_freeze_edgevrefupd_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_FREEZE_EDGEVREFUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_freeze_forcebg_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_FREEZE_FORCEBG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_freeze_hifreqagcupd_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_FREEZE_HIFREQAGCUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_freeze_iqalignupd_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_FREEZE_IQALIGNUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_freeze_lofreqagcupd_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_FREEZE_LOFREQAGCUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_freeze_vgaupd_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_FREEZE_VGAUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_gated_update_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_GATED_UPDATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_accum_count_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_accum_level_en_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_decr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_HIFREQAGC_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_frac_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_HIFREQAGC_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_HIFREQAGC_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_incr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_HIFREQAGC_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_n1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_n2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_n3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_n4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_n5_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_HIFREQAGC_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_pol_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_HIFREQAGC_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_single_step_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_HIFREQAGC_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_stable_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_HIFREQAGC_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_HIFREQAGC_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_init_adapt_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_INIT_ADAPT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_decr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_IQALIGN_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_frac_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_IQALIGN_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_IQALIGN_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_incr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_IQALIGN_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_IQALIGN_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_pol_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_IQALIGN_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_single_step_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_IQALIGN_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_stable_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_IQALIGN_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_IQALIGN_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_targ_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_itercount_attr == 10'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_latch_delay_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_latch_prepost_delay_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_decr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOFREQAGC_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_frac_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOFREQAGC_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOFREQAGC_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_incr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOFREQAGC_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOFREQAGC_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_pol_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOFREQAGC_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_single_step_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOFREQAGC_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_stable_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOFREQAGC_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOFREQAGC_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_logain_auxvref_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOGAIN_AUXVREF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_logain_dfe_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_logain_edge_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_logain_edgevref_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOGAIN_EDGEVREF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_logain_hifreqagc_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOGAIN_HIFREQAGC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_logain_iqalign_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOGAIN_IQALIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_logain_lofreqagc_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOGAIN_LOFREQAGC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_logain_vga_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOGAIN_VGA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_auxvref_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_dfe1_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_dfe23_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_dfe4p_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_edge2_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_edge3_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_edge4_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_edgevref_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_hifreqagc_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_iqalign_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_lofreqagc_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_vga_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_nrz_to_pam4_mode_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_NRZ_TO_PAM4_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_slow_blockcnt_attr == 16'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_start_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_tsettle_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_accum_count_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_accum_level_en_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_decr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_frac_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_incr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_mode_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_pol_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_single_step_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_stable_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_yadjdata_mid_clamp_zero_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_YADJDATA_MID_CLAMP_ZERO_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lofreqagcgain_sel_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LOFREQAGCGAIN_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_caldfedatatap1gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_caldfedatatap2gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_caldfedatatap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_caldfedatatap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_caldfeedgetap2gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_caldfeedgetap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_caldfeedgetap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_lofreqagcgain_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_caldfedatatap1gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_caldfedatatap1gain_attr == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_caldfedatatap1gain_attr == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_shift_auxshft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_shift_capture_trigger_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_SHIFT_CAPTURE_TRIGGER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_shift_clear_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_SHIFT_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_shift_dat_bitsel_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_SHIFT_DAT_BITSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_shift_datashft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_shift_edgeshft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_shift_edgeshft_nrz8b10b_pam16b20b_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_shift_polarity_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_SHIFT_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap10gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap11gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap12gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap13gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap14gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap15gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap16gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap1gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap2gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap5gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap6gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap7gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap8gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap9gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfeedgetap2gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfeedgetap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfeedgetap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_hifreqvgagain_attr == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_auxvref0_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_auxvref1_attr == 9'd223
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_auxvref2_attr == 9'd339
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_auxvref3_attr == 9'd456
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_caldfedatatap1gain_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_caldfeedgetap2gain_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_calhifreqagcres_attr == 6'd52
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_callofreqagcgain_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_edgevref_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_hifreqvgagain_attr == 7'd77
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_iqalign_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_auxvref0_attr == 9'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_auxvref1_attr == 9'd173
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_auxvref2_attr == 9'd289
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_auxvref3_attr == 9'd356
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_caldfedatatap1gain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_caldfeedgetap2gain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_calhifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_callofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_edgevref_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_iqalign_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqsetnrztopam4_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSETNRZTOPAM4_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqsetnrztopam4_switch_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSETNRZTOPAM4_SWITCH_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqsigdet_pause_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSIGDET_PAUSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqspare0_attr == 32'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqspare1_attr == 32'd15871
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqspare2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqsync2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSYNC2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqsync2flx_rxdatapath_ready_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSYNC2FLX_RXDATAPATH_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqtapctrl_data_tap13to16_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQTAPCTRL_DATA_TAP13TO16_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqtapctrl_data_tap1to4_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQTAPCTRL_DATA_TAP1TO4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqtapctrl_data_tap5to8_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQTAPCTRL_DATA_TAP5TO8_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqtapctrl_data_tap9to12_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQTAPCTRL_DATA_TAP9TO12_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqtapctrl_edge_tap_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQTAPCTRL_EDGE_TAP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqtapctrl_tap1to4gain_dbl_res_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQTAPCTRL_TAP1TO4GAIN_DBL_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqtapctrl_tap5to16gain_dbl_res_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQTAPCTRL_TAP5TO16GAIN_DBL_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvalc_hifreqagcbiasadjust_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvalc_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQVALC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvalc_midbandzero_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvalcl_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQVALCL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvalcl_lofreqagcgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap01gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap02gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap03gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap04gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap05gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap06gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap07gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap08gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap09gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap10gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap11gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap12gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap13gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap14gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap15gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap16gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQVALD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvale_caldfeedgetap02gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvale_caldfeedgetap03gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvale_caldfeedgetap04gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvale_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQVALE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1cal_clear_mask_attr == 13'd8184
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_aux0_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_aux1_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_d0_bot_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_d0_mid_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_d0_top_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_d1_bot_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_d1_mid_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_d1_top_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_e0_lo_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_e1_lo_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2cal_clear_mask_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_aux0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_aux1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_d0_bot_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_d0_mid_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_d0_top_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_d1_bot_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_d1_mid_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_d1_top_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_e0_lo_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_e1_lo_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfgcal_calfsmmeas_dlycount_attr == 10'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfgcal_fsmmaxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfgcal_lpfax_coarse_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfgcal_lpfax_fine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxhifreqagc_inputcmadjust_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxhifreqagc_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXHIFREQAGC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcal_clear_mask_attr == 13'd8191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_ctlecmnmode_stg1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_ctlecmnmode_stg2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_ctlecmnmode_stg3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_aux0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_aux1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_d0_bot_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_d0_mid_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_d0_top_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_d1_bot_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_d1_mid_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_d1_top_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_e0_lo_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_e1_lo_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmargin_flx_jit_offset_shift_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmargin_jit_disable_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmargin_jit_enable_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmargin_jit_offset_shift_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmargin_jit_setup_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmargin_volt_comp_mask_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmargin_volt_forcel2d_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXMARGIN_VOLT_FORCEL2D_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmargin_volt_offset_shift_d0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmargin_volt_offset_shift_d1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmarginin_direction_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXMARGININ_DIRECTION_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmarginin_flx_jit_offset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmarginin_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXMARGININ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmarginin_mode_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXMARGININ_MODE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmarginin_offset_change_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXMARGININ_OFFSET_CHANGE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmarginin_offset_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmarginin_start_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXMARGININ_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxsum_cm_vref_attr == 9'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxsum_summer_cmfb_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXSUM_SUMMER_CMFB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxsum_summer_cmfb_ibias_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_done_pwr2_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_apb_dwmask_muxd0_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_apb_dwmask_muxd1_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_apb_dwmask_muxd2_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_apb_dwmask_muxd3_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_apb_dwmask_muxd4_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_a2f_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_a2f_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_a2f_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_a2f_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_a2f_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd0_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd1_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd2_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd3_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd4_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd0_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd1_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd2_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd3_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd4_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd0_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd1_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd2_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd3_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd4_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd0_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd1_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd2_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd3_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd4_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd0_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd1_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd2_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd3_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd4_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_marker_muxd0_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_marker_muxd1_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_marker_muxd2_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_marker_muxd3_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_marker_muxd4_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd0_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd1_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd2_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd3_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd4_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd0_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd1_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd2_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd3_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd0_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd1_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd2_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd3_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd4_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd0_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd3_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd4_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd0_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd2_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd2_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd3_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd4_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd0_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd1_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd2_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd3_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd4_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd0_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd1_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd2_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd3_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd4_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd0_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd1_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd2_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd3_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd4_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd0_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd1_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd2_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd3_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd4_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd2_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd3_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd4_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd0_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd2_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd0_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd0_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd1_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd2_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd3_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd4_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd0_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd1_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd2_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd3_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd4_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd4_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd0_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd1_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd2_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd3_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd4_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd0_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd1_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd2_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd3_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd4_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_lock_thresh_muxd0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_lock_thresh_muxd1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_lock_thresh_muxd2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_lock_thresh_muxd3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_lock_thresh_muxd4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd0_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd1_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd2_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd3_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd4_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchn_offset_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchn_offset_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchn_offset_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchn_offset_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchn_offset_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchp_offset_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchp_offset_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchp_offset_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchp_offset_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchp_offset_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_bypass_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_bypass_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_bypass_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_bypass_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_bypass_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd4_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_step_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_step_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_step_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_step_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_step_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd0_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd1_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd2_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd3_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd4_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd2_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd0_attr == 8'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd1_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd2_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd3_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd4_attr == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd0_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd1_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd2_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd3_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd4_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd2_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd3_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd4_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_fll_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_fll_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_fll_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_fll_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_fll_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_pll_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_pll_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_pll_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_pll_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_pll_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd0_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd1_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd2_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd4_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd0_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd1_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd3_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd4_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_temp_track_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_temp_track_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_temp_track_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_temp_track_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_temp_track_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd0_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd1_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd2_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd3_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd4_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd0_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd1_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd2_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd3_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd4_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd0_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd1_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd2_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd3_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd4_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd0_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd1_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd2_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd3_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd4_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bb_gain_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bb_gain_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bb_gain_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bb_gain_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bb_gain_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbinlock_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbinlock_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbinlock_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbinlock_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbinlock_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbthresh_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbthresh_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbthresh_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbthresh_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbthresh_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrlhext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrlhext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrlhext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrlhext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrlhext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrllext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrllext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrllext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrllext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrllext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_muxd0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_muxd1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_muxd2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_muxd3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_muxd4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcoditheren_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcoditheren_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcoditheren_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcoditheren_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcoditheren_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofine_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofine_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofine_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofine_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofine_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofinedftsel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofinedftsel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofinedftsel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofinedftsel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofinedftsel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dither_value_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dither_value_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dither_value_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dither_value_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dither_value_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_earlylock_criteria_muxd0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_earlylock_criteria_muxd1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_earlylock_criteria_muxd2_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_earlylock_criteria_muxd3_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_earlylock_criteria_muxd4_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_frac_muxd0_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_frac_muxd1_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_frac_muxd2_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_frac_muxd3_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_frac_muxd4_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd0_attr == 9'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd1_attr == 9'd45
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd2_attr == 9'd27
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd3_attr == 9'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd4_attr == 9'd216
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdgain_muxd0_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdgain_muxd1_attr == 8'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdgain_muxd2_attr == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdgain_muxd3_attr == 8'd23
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdgain_muxd4_attr == 8'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fracnen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fracnen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fracnen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fracnen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fracnen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_lock_criteria_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_lock_criteria_muxd1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_lock_criteria_muxd2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_lock_criteria_muxd3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_lock_criteria_muxd4_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_regen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_regen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_regen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_regen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_regen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllock_sel_muxd0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllock_sel_muxd1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllock_sel_muxd2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllock_sel_muxd3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllock_sel_muxd4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdc_fine_res_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdc_fine_res_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdc_fine_res_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdc_fine_res_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdc_fine_res_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdccalexten_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdccalexten_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdccalexten_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdccalexten_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdccalexten_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcroen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcroen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcroen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcroen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcroen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcsel_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcsel_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcsel_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcsel_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcsel_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdctargetcnt_muxd0_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdctargetcnt_muxd1_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdctargetcnt_muxd2_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdctargetcnt_muxd3_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdctargetcnt_muxd4_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tribufctrlext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tribufctrlext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tribufctrlext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tribufctrlext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tribufctrlext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_done_pwr2_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_apb_dwmask_muxd0_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_apb_dwmask_muxd1_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_apb_dwmask_muxd2_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_apb_dwmask_muxd3_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_apb_dwmask_muxd4_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_a2f_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_a2f_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_a2f_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_a2f_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_a2f_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd0_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd1_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd2_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd3_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd4_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd0_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd1_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd2_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd3_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd4_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd0_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd1_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd2_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd3_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd4_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd0_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd1_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd2_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd3_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd4_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd0_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd1_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd2_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd3_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd4_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_marker_muxd0_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_marker_muxd1_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_marker_muxd2_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_marker_muxd3_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_marker_muxd4_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd0_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd1_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd2_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd3_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd4_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd0_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd1_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd2_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd3_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd1_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd2_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd3_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd4_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd0_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd3_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd4_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd0_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd2_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd0_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd2_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd3_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd4_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd0_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd1_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd2_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd3_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd4_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd0_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd1_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd2_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd3_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd4_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd0_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd1_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd2_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd3_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd4_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd0_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd1_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd2_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd3_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd4_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd2_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd3_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd4_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd0_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd2_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd0_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd0_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd1_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd2_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd3_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd4_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd0_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd1_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd2_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd3_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd4_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd4_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd0_attr == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd1_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd2_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd3_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd4_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd0_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd1_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd2_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd3_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd4_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_lock_thresh_muxd0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_lock_thresh_muxd1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_lock_thresh_muxd2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_lock_thresh_muxd3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_lock_thresh_muxd4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd0_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd1_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd2_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd3_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd4_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchn_offset_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchn_offset_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchn_offset_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchn_offset_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchn_offset_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchp_offset_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchp_offset_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchp_offset_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchp_offset_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchp_offset_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_bypass_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_bypass_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_bypass_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_bypass_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_bypass_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd4_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_step_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_step_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_step_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_step_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_step_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd0_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd1_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd2_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd3_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd4_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd0_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd2_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd0_attr == 8'd148
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd1_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd2_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd3_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd4_attr == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd0_attr == 18'd14336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd1_attr == 18'd14336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd2_attr == 18'd14336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd3_attr == 18'd14336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd4_attr == 18'd14336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd2_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd3_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd4_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_fll_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_fll_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_fll_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_fll_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_fll_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_pll_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_pll_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_pll_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_pll_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_pll_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd0_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd1_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd2_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd4_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd0_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd1_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd3_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd4_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_temp_track_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_temp_track_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_temp_track_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_temp_track_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_temp_track_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd0_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd1_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd2_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd3_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd4_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd0_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd1_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd2_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd3_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd4_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd0_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd1_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd2_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd3_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd4_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd0_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd1_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd2_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd3_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd4_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bb_gain_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bb_gain_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bb_gain_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bb_gain_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bb_gain_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbinlock_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbinlock_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbinlock_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbinlock_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbinlock_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbthresh_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbthresh_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbthresh_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbthresh_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbthresh_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrlhext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrlhext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrlhext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrlhext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrlhext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrllext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrllext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrllext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrllext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrllext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_muxd0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_muxd1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_muxd2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_muxd3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_muxd4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcoditheren_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcoditheren_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcoditheren_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcoditheren_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcoditheren_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofine_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofine_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofine_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofine_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofine_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofinedftsel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofinedftsel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofinedftsel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofinedftsel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofinedftsel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dither_value_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dither_value_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dither_value_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dither_value_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dither_value_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_earlylock_criteria_muxd0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_earlylock_criteria_muxd1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_earlylock_criteria_muxd2_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_earlylock_criteria_muxd3_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_earlylock_criteria_muxd4_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_frac_muxd0_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_frac_muxd1_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_frac_muxd2_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_frac_muxd3_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_frac_muxd4_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd0_attr == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd1_attr == 9'd90
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd2_attr == 9'd54
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd3_attr == 9'd72
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd4_attr == 9'd432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdgain_muxd0_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdgain_muxd1_attr == 8'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdgain_muxd2_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdgain_muxd3_attr == 8'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdgain_muxd4_attr == 8'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fracnen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fracnen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fracnen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fracnen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fracnen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_lock_criteria_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_lock_criteria_muxd1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_lock_criteria_muxd2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_lock_criteria_muxd3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_lock_criteria_muxd4_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_regen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_regen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_regen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_regen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_regen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllock_sel_muxd0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllock_sel_muxd1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllock_sel_muxd2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllock_sel_muxd3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllock_sel_muxd4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdc_fine_res_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdc_fine_res_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdc_fine_res_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdc_fine_res_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdc_fine_res_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdccalexten_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdccalexten_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdccalexten_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdccalexten_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdccalexten_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcroen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcroen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcroen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcroen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcroen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcsel_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcsel_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcsel_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcsel_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcsel_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdctargetcnt_muxd0_attr == 8'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdctargetcnt_muxd1_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdctargetcnt_muxd2_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdctargetcnt_muxd3_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdctargetcnt_muxd4_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tribufctrlext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tribufctrlext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tribufctrlext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tribufctrlext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tribufctrlext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_done_pwr2_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_apb_dwmask_muxd0_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_apb_dwmask_muxd1_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_apb_dwmask_muxd2_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_apb_dwmask_muxd3_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_apb_dwmask_muxd4_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_a2f_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_a2f_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_a2f_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_a2f_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_a2f_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd0_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd1_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd2_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd3_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd4_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd0_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd1_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd2_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd3_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd4_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd0_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd1_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd2_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd3_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd4_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd0_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd1_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd2_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd3_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd4_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd0_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd1_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd2_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd3_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd4_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_marker_muxd0_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_marker_muxd1_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_marker_muxd2_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_marker_muxd3_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_marker_muxd4_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd0_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd1_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd2_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd3_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd4_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd0_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd1_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd2_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd3_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd0_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd1_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd2_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd3_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd4_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd0_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd3_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd4_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd0_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd2_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd2_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd3_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd4_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd0_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd1_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd2_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd3_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd4_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd0_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd1_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd2_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd3_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd4_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd0_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd1_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd2_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd3_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd4_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd0_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd1_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd2_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd3_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd4_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd2_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd3_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd4_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd0_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd2_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd0_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd0_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd1_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd2_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd3_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd4_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd0_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd1_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd2_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd3_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd4_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd4_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd0_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd1_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd2_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd3_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd4_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd0_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd1_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd2_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd3_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd4_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_lock_thresh_muxd0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_lock_thresh_muxd1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_lock_thresh_muxd2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_lock_thresh_muxd3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_lock_thresh_muxd4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd0_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd1_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd2_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd3_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd4_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchn_offset_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchn_offset_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchn_offset_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchn_offset_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchn_offset_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchp_offset_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchp_offset_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchp_offset_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchp_offset_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchp_offset_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_bypass_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_bypass_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_bypass_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_bypass_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_bypass_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd4_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_step_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_step_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_step_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_step_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_step_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd0_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd1_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd2_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd3_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd4_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd2_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd0_attr == 8'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd1_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd2_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd3_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd4_attr == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd0_attr == 18'd14336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd1_attr == 18'd14336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd2_attr == 18'd14336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd3_attr == 18'd14336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd4_attr == 18'd14336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd2_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd3_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd4_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_fll_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_fll_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_fll_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_fll_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_fll_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_pll_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_pll_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_pll_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_pll_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_pll_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd0_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd1_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd2_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd4_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd0_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd1_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd3_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd4_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_temp_track_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_temp_track_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_temp_track_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_temp_track_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_temp_track_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd0_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd1_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd2_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd3_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd4_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd0_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd1_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd2_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd3_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd4_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd0_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd1_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd2_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd3_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd4_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd0_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd1_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd2_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd3_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd4_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bb_gain_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bb_gain_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bb_gain_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bb_gain_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bb_gain_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbinlock_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbinlock_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbinlock_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbinlock_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbinlock_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbthresh_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbthresh_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbthresh_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbthresh_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbthresh_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrlhext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrlhext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrlhext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrlhext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrlhext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrllext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrllext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrllext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrllext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrllext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_muxd0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_muxd1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_muxd2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_muxd3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_muxd4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcoditheren_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcoditheren_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcoditheren_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcoditheren_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcoditheren_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofine_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofine_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofine_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofine_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofine_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofinedftsel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofinedftsel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofinedftsel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofinedftsel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofinedftsel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dither_value_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dither_value_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dither_value_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dither_value_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dither_value_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_earlylock_criteria_muxd0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_earlylock_criteria_muxd1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_earlylock_criteria_muxd2_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_earlylock_criteria_muxd3_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_earlylock_criteria_muxd4_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_frac_muxd0_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_frac_muxd1_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_frac_muxd2_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_frac_muxd3_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_frac_muxd4_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd0_attr == 9'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd1_attr == 9'd90
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd2_attr == 9'd54
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd3_attr == 9'd72
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd4_attr == 9'd432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdgain_muxd0_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdgain_muxd1_attr == 8'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdgain_muxd2_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdgain_muxd3_attr == 8'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdgain_muxd4_attr == 8'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fracnen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fracnen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fracnen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fracnen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fracnen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_lock_criteria_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_lock_criteria_muxd1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_lock_criteria_muxd2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_lock_criteria_muxd3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_lock_criteria_muxd4_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_regen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_regen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_regen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_regen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_regen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllock_sel_muxd0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllock_sel_muxd1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllock_sel_muxd2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllock_sel_muxd3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllock_sel_muxd4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdc_fine_res_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdc_fine_res_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdc_fine_res_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdc_fine_res_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdc_fine_res_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdccalexten_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdccalexten_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdccalexten_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdccalexten_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdccalexten_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcroen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcroen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcroen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcroen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcroen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcsel_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcsel_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcsel_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcsel_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcsel_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdctargetcnt_muxd0_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdctargetcnt_muxd1_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdctargetcnt_muxd2_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdctargetcnt_muxd3_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdctargetcnt_muxd4_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tribufctrlext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tribufctrlext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tribufctrlext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tribufctrlext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tribufctrlext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_done_pwr2_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_apb_dwmask_muxd0_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_apb_dwmask_muxd1_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_apb_dwmask_muxd2_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_apb_dwmask_muxd3_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_apb_dwmask_muxd4_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_a2f_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_a2f_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_a2f_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_a2f_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_a2f_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd0_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd1_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd2_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd3_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd4_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd0_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd1_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd2_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd3_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd4_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd0_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd1_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd2_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd3_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd4_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd0_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd1_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd2_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd3_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd4_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd0_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd1_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd2_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd3_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd4_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_marker_muxd0_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_marker_muxd1_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_marker_muxd2_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_marker_muxd3_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_marker_muxd4_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd0_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd1_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd2_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd3_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd4_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd0_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd1_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd2_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd3_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd0_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd1_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd2_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd3_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd4_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd0_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd3_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd4_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd0_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd2_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd2_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd3_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd4_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd0_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd1_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd2_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd3_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd4_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd0_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd1_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd2_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd3_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd4_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd0_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd1_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd2_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd3_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd4_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd0_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd1_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd2_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd3_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd4_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd2_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd3_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd4_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd0_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd2_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd0_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd0_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd1_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd2_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd3_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd4_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd0_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd1_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd2_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd3_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd4_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd4_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd0_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd1_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd2_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd3_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd4_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd0_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd1_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd2_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd3_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd4_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_lock_thresh_muxd0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_lock_thresh_muxd1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_lock_thresh_muxd2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_lock_thresh_muxd3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_lock_thresh_muxd4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd0_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd1_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd2_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd3_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd4_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchn_offset_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchn_offset_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchn_offset_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchn_offset_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchn_offset_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchp_offset_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchp_offset_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchp_offset_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchp_offset_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchp_offset_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_bypass_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_bypass_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_bypass_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_bypass_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_bypass_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd4_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_step_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_step_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_step_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_step_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_step_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd0_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd1_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd2_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd3_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd4_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd2_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd0_attr == 8'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd1_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd2_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd3_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd4_attr == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd0_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd1_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd2_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd3_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd4_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd2_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd3_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd4_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_fll_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_fll_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_fll_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_fll_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_fll_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_pll_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_pll_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_pll_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_pll_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_pll_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd0_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd1_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd2_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd4_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd0_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd1_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd3_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd4_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_temp_track_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_temp_track_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_temp_track_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_temp_track_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_temp_track_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd0_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd1_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd2_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd3_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd4_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd0_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd1_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd2_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd3_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd4_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd0_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd1_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd2_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd3_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd4_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd0_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd1_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd2_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd3_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd4_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bb_gain_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bb_gain_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bb_gain_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bb_gain_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bb_gain_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbinlock_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbinlock_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbinlock_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbinlock_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbinlock_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbthresh_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbthresh_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbthresh_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbthresh_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbthresh_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrlhext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrlhext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrlhext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrlhext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrlhext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrllext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrllext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrllext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrllext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrllext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_muxd0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_muxd1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_muxd2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_muxd3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_muxd4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcoditheren_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcoditheren_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcoditheren_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcoditheren_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcoditheren_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofine_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofine_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofine_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofine_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofine_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofinedftsel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofinedftsel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofinedftsel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofinedftsel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofinedftsel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dither_value_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dither_value_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dither_value_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dither_value_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dither_value_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_earlylock_criteria_muxd0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_earlylock_criteria_muxd1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_earlylock_criteria_muxd2_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_earlylock_criteria_muxd3_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_earlylock_criteria_muxd4_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_frac_muxd0_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_frac_muxd1_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_frac_muxd2_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_frac_muxd3_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_frac_muxd4_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd0_attr == 9'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd1_attr == 9'd45
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd2_attr == 9'd27
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd3_attr == 9'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd4_attr == 9'd216
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdgain_muxd0_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdgain_muxd1_attr == 8'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdgain_muxd2_attr == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdgain_muxd3_attr == 8'd23
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdgain_muxd4_attr == 8'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fracnen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fracnen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fracnen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fracnen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fracnen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_lock_criteria_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_lock_criteria_muxd1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_lock_criteria_muxd2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_lock_criteria_muxd3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_lock_criteria_muxd4_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_regen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_regen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_regen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_regen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_regen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllock_sel_muxd0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllock_sel_muxd1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllock_sel_muxd2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllock_sel_muxd3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllock_sel_muxd4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdc_fine_res_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdc_fine_res_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdc_fine_res_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdc_fine_res_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdc_fine_res_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdccalexten_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdccalexten_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdccalexten_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdccalexten_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdccalexten_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcroen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcroen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcroen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcroen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcroen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcsel_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcsel_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcsel_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcsel_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcsel_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdctargetcnt_muxd0_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdctargetcnt_muxd1_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdctargetcnt_muxd2_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdctargetcnt_muxd3_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdctargetcnt_muxd4_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tribufctrlext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tribufctrlext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tribufctrlext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tribufctrlext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tribufctrlext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_a2f_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_clkouten_cb_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_clkouten_lane_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_en_peak_sense_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_obsmux0_del_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_obsmux1_del_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_pcs40div_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_pll_bypass_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_refclk100div_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_refclk156div_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_sddiv_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_spare_dig2ana_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_ssc_track_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_stay_fll_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_stay_pll_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_temp_track_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_bbinlock_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_dcoditheren_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_fracnen_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_pll_reg_resetb_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_plllc_regen_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_tdc_fine_res_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_tdccalexten_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_tdcdc_en_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_tdcroen_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_a2f_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_clkouten_cb_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_clkouten_lane_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_en_peak_sense_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_obsmux0_del_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_obsmux1_del_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_pcs40div_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_pll_bypass_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_refclk100div_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_refclk156div_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_sddiv_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_spare_dig2ana_attr == 18'd30720
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_ssc_track_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_stay_fll_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_stay_pll_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_temp_track_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_bbinlock_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_dcoditheren_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_fracnen_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_pll_reg_resetb_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_plllc_regen_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_tdc_fine_res_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_tdccalexten_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_tdcdc_en_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_tdcroen_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_a2f_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_clkouten_cb_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_clkouten_lane_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_en_peak_sense_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_obsmux0_del_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_obsmux1_del_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_pcs40div_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_pll_bypass_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_refclk100div_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_refclk156div_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_sddiv_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_spare_dig2ana_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_ssc_track_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_stay_fll_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_stay_pll_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_temp_track_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_bbinlock_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_dcoditheren_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_fracnen_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_pll_reg_resetb_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_plllc_regen_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_tdc_fine_res_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_tdccalexten_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_tdcdc_en_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_tdcroen_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_a2f_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_clkouten_cb_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_clkouten_lane_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_en_peak_sense_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_obsmux0_del_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_obsmux1_del_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_pcs40div_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_pll_bypass_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_refclk100div_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_refclk156div_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_sddiv_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_spare_dig2ana_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_ssc_track_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_stay_fll_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_stay_pll_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_temp_track_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_bbinlock_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_dcoditheren_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_fracnen_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_pll_reg_resetb_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_plllc_regen_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_tdc_fine_res_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_tdccalexten_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_tdcdc_en_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_tdcroen_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_a2f_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_clkouten_cb_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_clkouten_lane_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_en_peak_sense_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_obsmux0_del_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_obsmux1_del_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_pcs40div_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_pll_bypass_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_refclk100div_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_refclk156div_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_sddiv_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_spare_dig2ana_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_ssc_track_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_stay_fll_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_stay_pll_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_temp_track_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_bbinlock_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_dcoditheren_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_fracnen_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_pll_reg_resetb_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_plllc_regen_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_tdc_fine_res_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_tdccalexten_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_tdcdc_en_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_tdcroen_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_a2f_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_clkouten_cb_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_clkouten_lane_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_en_peak_sense_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_obsmux0_del_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_obsmux1_del_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_pcs40div_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_pll_bypass_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_refclk100div_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_refclk156div_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_sddiv_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_spare_dig2ana_attr == 18'd30720
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_ssc_track_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_stay_fll_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_stay_pll_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_temp_track_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_bbinlock_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_dcoditheren_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_fracnen_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_pll_reg_resetb_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_plllc_regen_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_tdc_fine_res_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_tdccalexten_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_tdcdc_en_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_tdcroen_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_a2f_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_clkouten_cb_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_clkouten_lane_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_en_peak_sense_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_obsmux0_del_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_obsmux1_del_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_pcs40div_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_pll_bypass_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_refclk100div_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_refclk156div_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_sddiv_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_spare_dig2ana_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_ssc_track_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_stay_fll_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_stay_pll_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_temp_track_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_bbinlock_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_dcoditheren_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_fracnen_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_pll_reg_resetb_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_plllc_regen_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_tdc_fine_res_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_tdccalexten_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_tdcdc_en_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_tdcroen_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_a2f_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_clkouten_cb_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_clkouten_lane_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_en_peak_sense_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_obsmux0_del_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_obsmux1_del_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_pcs40div_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_pll_bypass_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_refclk100div_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_refclk156div_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_sddiv_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_spare_dig2ana_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_ssc_track_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_stay_fll_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_stay_pll_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_temp_track_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_bbinlock_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_dcoditheren_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_fracnen_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_pll_reg_resetb_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_plllc_regen_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_tdc_fine_res_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_tdccalexten_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_tdcdc_en_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_tdcroen_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_a2f_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_clkouten_cb_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_clkouten_lane_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_en_peak_sense_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_obsmux0_del_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_obsmux1_del_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_pcs40div_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_pll_bypass_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_refclk100div_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_refclk156div_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_sddiv_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_spare_dig2ana_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_ssc_track_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_stay_fll_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_stay_pll_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_temp_track_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_bbinlock_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_dcoditheren_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_fracnen_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_pll_reg_resetb_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_plllc_regen_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_tdc_fine_res_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_tdccalexten_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_tdcdc_en_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_tdcroen_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_a2f_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_clkouten_cb_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_clkouten_lane_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_en_peak_sense_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_obsmux0_del_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_obsmux1_del_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_pcs40div_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_pll_bypass_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_refclk100div_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_refclk156div_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_sddiv_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_spare_dig2ana_attr == 18'd14336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_ssc_track_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_stay_fll_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_stay_pll_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_temp_track_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_bbinlock_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_dcoditheren_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_fracnen_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_pll_reg_resetb_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_plllc_regen_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_tdc_fine_res_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_tdccalexten_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_tdcdc_en_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_tdcroen_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_a2f_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_clkouten_cb_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_clkouten_lane_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_en_peak_sense_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_obsmux0_del_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_obsmux1_del_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_pcs40div_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_pll_bypass_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_refclk100div_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_refclk156div_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_sddiv_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_spare_dig2ana_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_ssc_track_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_stay_fll_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_stay_pll_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_temp_track_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_bbinlock_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_dcoditheren_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_fracnen_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_pll_reg_resetb_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_plllc_regen_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_tdc_fine_res_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_tdccalexten_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_tdcdc_en_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_tdcroen_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_a2f_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_clkouten_cb_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_clkouten_lane_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_en_peak_sense_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_obsmux0_del_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_obsmux1_del_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_pcs40div_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_pll_bypass_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_refclk100div_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_refclk156div_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_sddiv_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_spare_dig2ana_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_ssc_track_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_stay_fll_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_stay_pll_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_temp_track_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_bbinlock_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_dcoditheren_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_fracnen_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_pll_reg_resetb_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_plllc_regen_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_tdc_fine_res_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_tdccalexten_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_tdcdc_en_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_tdcroen_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_flavor_table_attr == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_flavor_table_en_attr == SERDES_IP_RX_FLEX_L0_CFG_FLX_FLAVOR_TABLE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_force_frame_lock_attr == SERDES_IP_RX_FLEX_L0_CFG_FLX_FORCE_FRAME_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_freeze_in_state_attr == SERDES_IP_RX_FLEX_L0_CFG_FLX_FREEZE_IN_STATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_01_attr == 32'd65537
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_02_attr == 32'd2147516416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_03_attr == 32'd2181169152
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_04_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_05_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_06_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_07_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_08_attr == 32'd16384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_09_attr == 32'd131072
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_10_attr == 32'd2416050176
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_11_attr == 32'd33554432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_12_attr == 32'd1075838976
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_13_attr == 32'd301989888
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_14_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_15_attr == 32'd2181169152
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_16_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_17_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_18_attr == 32'd302006272
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_19_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_20_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_21_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_22_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_23_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_24_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_25_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_26_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_27_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_28_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_29_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_30_attr == 32'd33587200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_31_attr == 32'd1107329024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_02_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_03_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_10_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_12_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_13_attr == 5'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_15_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_18_attr == 5'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_31_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_02_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_03_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_10_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_11_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_12_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_13_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_15_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_18_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_30_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_31_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_one_state_inc_pulse_attr == SERDES_IP_RX_FLEX_L0_CFG_FLX_ONE_STATE_INC_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_00_attr == 32'd1056783
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_01_attr == 32'd9510943
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_02_attr == 32'd9502735
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_03_attr == 32'd9437199
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_04_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_05_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_06_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_07_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_08_attr == 32'd14680079
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_09_attr == 32'd26017807
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_10_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_11_attr == 32'd9502735
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_12_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_13_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_14_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_15_attr == 32'd25493519
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_16_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_17_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_18_attr == 32'd14942223
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_19_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_20_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_21_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_22_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_23_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_24_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_25_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_26_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_27_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_28_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_29_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_30_attr == 32'd1376271
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_31_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_00_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_01_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_02_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_03_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_04_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_05_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_06_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_07_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_08_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_09_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_10_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_11_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_12_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_13_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_14_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_15_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_16_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_17_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_18_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_19_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_20_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_21_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_22_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_23_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_24_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_25_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_26_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_27_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_28_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_29_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_30_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_31_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_state_force_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_state_force_value_en_attr == SERDES_IP_RX_FLEX_L0_CFG_FLX_STATE_FORCE_VALUE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_flx_stop_tmr_in_handshake_attr == SERDES_IP_RX_FLEX_L0_CFG_FLX_STOP_TMR_IN_HANDSHAKE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_00_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_00_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_01_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_01_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_02_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_02_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_03_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_03_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_04_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_04_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_05_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_05_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_06_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_06_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_07_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_07_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_08_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_08_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_09_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_09_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_10_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_10_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_11_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_12_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_13_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_14_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_15_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_15_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_16_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_17_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_18_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_19_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_19_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_20_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_20_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_21_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_21_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_22_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_22_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_23_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_23_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_24_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_24_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_25_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_25_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_26_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_26_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_27_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_27_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_28_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_28_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_29_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_29_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_30_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_30_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_31_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_31_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_02_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_03_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_10_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_12_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_13_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_15_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_18_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_31_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_00_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_00_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_01_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_01_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_02_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_02_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_03_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_03_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_04_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_04_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_05_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_05_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_06_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_06_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_07_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_07_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_08_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_08_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_09_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_09_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_10_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_11_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_12_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_13_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_14_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_15_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_16_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_17_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_18_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_19_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_19_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_20_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_20_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_21_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_21_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_22_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_22_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_23_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_23_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_24_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_24_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_25_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_25_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_26_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_26_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_27_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_27_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_28_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_28_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_29_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_29_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_30_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_30_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_31_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_31_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_00_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_02_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_03_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_10_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_12_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_13_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_15_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_18_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_31_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_flavor_table_attr == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_flavor_table_en_attr == SERDES_IP_RX_FLEX_L1_CFG_FLX_FLAVOR_TABLE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_force_frame_lock_attr == SERDES_IP_RX_FLEX_L1_CFG_FLX_FORCE_FRAME_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_freeze_in_state_attr == SERDES_IP_RX_FLEX_L1_CFG_FLX_FREEZE_IN_STATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_01_attr == 32'd65537
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_02_attr == 32'd2147516416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_03_attr == 32'd2181169152
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_04_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_05_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_06_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_07_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_08_attr == 32'd16384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_09_attr == 32'd131072
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_10_attr == 32'd2416050176
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_11_attr == 32'd33554432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_12_attr == 32'd1075838976
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_13_attr == 32'd301989888
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_14_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_15_attr == 32'd2181169152
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_16_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_17_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_18_attr == 32'd302006272
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_19_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_20_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_21_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_22_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_23_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_24_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_25_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_26_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_27_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_28_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_29_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_30_attr == 32'd33587200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_31_attr == 32'd1107329024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_02_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_03_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_10_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_12_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_13_attr == 5'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_15_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_18_attr == 5'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_31_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_02_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_03_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_10_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_11_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_12_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_13_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_15_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_18_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_30_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_31_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_one_state_inc_pulse_attr == SERDES_IP_RX_FLEX_L1_CFG_FLX_ONE_STATE_INC_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_00_attr == 32'd1056783
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_01_attr == 32'd9510943
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_02_attr == 32'd9502735
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_03_attr == 32'd9437199
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_04_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_05_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_06_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_07_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_08_attr == 32'd14680079
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_09_attr == 32'd26017807
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_10_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_11_attr == 32'd9502735
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_12_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_13_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_14_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_15_attr == 32'd25493519
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_16_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_17_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_18_attr == 32'd14942223
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_19_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_20_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_21_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_22_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_23_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_24_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_25_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_26_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_27_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_28_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_29_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_30_attr == 32'd1376271
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_31_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_00_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_01_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_02_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_03_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_04_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_05_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_06_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_07_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_08_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_09_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_10_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_11_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_12_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_13_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_14_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_15_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_16_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_17_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_18_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_19_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_20_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_21_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_22_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_23_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_24_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_25_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_26_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_27_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_28_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_29_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_30_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_31_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_state_force_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_state_force_value_en_attr == SERDES_IP_RX_FLEX_L1_CFG_FLX_STATE_FORCE_VALUE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_flx_stop_tmr_in_handshake_attr == SERDES_IP_RX_FLEX_L1_CFG_FLX_STOP_TMR_IN_HANDSHAKE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_00_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_00_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_01_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_01_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_02_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_02_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_03_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_03_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_04_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_04_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_05_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_05_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_06_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_06_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_07_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_07_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_08_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_08_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_09_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_09_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_10_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_10_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_11_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_12_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_13_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_14_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_15_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_15_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_16_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_17_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_18_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_19_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_19_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_20_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_20_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_21_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_21_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_22_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_22_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_23_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_23_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_24_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_24_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_25_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_25_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_26_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_26_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_27_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_27_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_28_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_28_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_29_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_29_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_30_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_30_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_31_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_31_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_02_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_03_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_10_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_12_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_13_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_15_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_18_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_31_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_00_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_00_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_01_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_01_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_02_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_02_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_03_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_03_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_04_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_04_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_05_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_05_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_06_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_06_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_07_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_07_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_08_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_08_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_09_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_09_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_10_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_11_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_12_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_13_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_14_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_15_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_16_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_17_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_18_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_19_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_19_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_20_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_20_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_21_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_21_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_22_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_22_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_23_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_23_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_24_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_24_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_25_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_25_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_26_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_26_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_27_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_27_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_28_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_28_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_29_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_29_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_30_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_30_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_31_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_31_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_00_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_02_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_03_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_10_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_12_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_13_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_15_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_18_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_31_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_flavor_table_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_flavor_table_en_attr == SERDES_IP_RX_FLEX_L2_CFG_FLX_FLAVOR_TABLE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_force_frame_lock_attr == SERDES_IP_RX_FLEX_L2_CFG_FLX_FORCE_FRAME_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_freeze_in_state_attr == SERDES_IP_RX_FLEX_L2_CFG_FLX_FREEZE_IN_STATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_01_attr == 32'd65536
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_02_attr == 32'd2181070848
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_03_attr == 32'd2147491840
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_04_attr == 32'd2147483649
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_05_attr == 32'd2147483649
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_06_attr == 32'd2147483649
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_07_attr == 32'd2181038081
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_08_attr == 32'd16384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_09_attr == 32'd131072
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_10_attr == 32'd2147614720
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_11_attr == 32'd33554432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_12_attr == 32'd1075838976
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_13_attr == 32'd268435456
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_14_attr == 32'd2147491840
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_15_attr == 32'd2147614720
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_16_attr == 32'd268435457
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_17_attr == 32'd301989889
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_18_attr == 32'd33570816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_19_attr == 32'd33554432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_20_attr == 32'd33554432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_21_attr == 32'd2181054464
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_22_attr == 32'd2147484672
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_23_attr == 32'd33587200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_24_attr == 32'd2147614720
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_25_attr == 32'd33554432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_26_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_27_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_28_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_29_attr == 32'd33587200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_30_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_31_attr == 32'd1107296256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_02_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_03_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_04_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_05_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_06_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_07_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_10_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_12_attr == 5'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_13_attr == 5'd29
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_14_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_15_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_16_attr == 5'd29
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_17_attr == 5'd29
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_18_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_21_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_22_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_24_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_31_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_01_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_02_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_03_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_07_attr == 5'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_10_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_11_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_12_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_13_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_15_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_17_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_18_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_19_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_20_attr == 5'd21
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_21_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_23_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_25_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_29_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_31_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_one_state_inc_pulse_attr == SERDES_IP_RX_FLEX_L2_CFG_FLX_ONE_STATE_INC_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_00_attr == 32'd1187855
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_01_attr == 32'd9576479
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_02_attr == 32'd9437199
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_03_attr == 32'd9437199
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_04_attr == 32'd9554175
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_05_attr == 32'd9554943
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_06_attr == 32'd9554943
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_07_attr == 32'd9554943
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_08_attr == 32'd14680079
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_09_attr == 32'd25952527
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_10_attr == 32'd8651023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_11_attr == 32'd9437215
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_12_attr == 32'd8651023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_13_attr == 32'd8651023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_14_attr == 32'd8651023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_15_attr == 32'd25428239
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_16_attr == 32'd8735743
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_17_attr == 32'd8735487
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_18_attr == 32'd14942223
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_19_attr == 32'd12845071
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_20_attr == 32'd8392719
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_21_attr == 32'd14684175
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_22_attr == 32'd9519167
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_23_attr == 32'd9519119
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_24_attr == 32'd12582927
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_25_attr == 32'd12582927
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_26_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_27_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_28_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_29_attr == 32'd5505295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_30_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_31_attr == 32'd4456719
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_00_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_01_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_02_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_03_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_04_attr == 32'd4210819071
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_05_attr == 32'd4210771012
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_06_attr == 32'd2063305591
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_07_attr == 32'd2054911863
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_08_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_09_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_10_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_11_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_12_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_13_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_14_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_15_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_16_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_17_attr == 32'd1784366148
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_18_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_19_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_20_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_21_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_22_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_23_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_24_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_25_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_26_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_27_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_28_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_29_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_30_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_31_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_state_force_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_state_force_value_en_attr == SERDES_IP_RX_FLEX_L2_CFG_FLX_STATE_FORCE_VALUE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_flx_stop_tmr_in_handshake_attr == SERDES_IP_RX_FLEX_L2_CFG_FLX_STOP_TMR_IN_HANDSHAKE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_00_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_00_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_01_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_01_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_02_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_02_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_03_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_03_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_04_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_04_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_05_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_05_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_06_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_06_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_07_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_07_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_08_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_08_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_09_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_09_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_10_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_10_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_11_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_12_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_13_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_14_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_14_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_15_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_15_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_16_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_16_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_17_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_17_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_18_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_19_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_19_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_20_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_20_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_21_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_21_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_22_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_22_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_23_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_23_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_24_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_24_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_25_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_25_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_26_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_26_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_27_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_27_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_28_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_28_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_29_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_29_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_30_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_30_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_31_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_31_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_02_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_03_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_04_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_05_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_06_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_07_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_10_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_12_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_13_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_15_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_16_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_17_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_18_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_21_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_22_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_31_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_00_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_00_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_01_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_01_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_02_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_02_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_03_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_03_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_04_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_04_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_05_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_05_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_06_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_06_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_07_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_07_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_08_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_08_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_09_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_09_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_10_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_11_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_12_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_13_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_14_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_15_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_16_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_17_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_18_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_19_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_19_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_20_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_20_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_21_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_21_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_22_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_22_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_23_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_23_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_24_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_24_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_25_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_25_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_26_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_26_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_27_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_27_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_28_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_28_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_29_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_29_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_30_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_30_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_31_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_31_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_00_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_02_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_03_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_04_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_05_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_06_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_07_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_10_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_12_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_13_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_15_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_16_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_17_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_18_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_19_attr == 5'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_25_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_31_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_flavor_table_attr == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_flavor_table_en_attr == SERDES_IP_RX_FLEX_L3_CFG_FLX_FLAVOR_TABLE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_force_frame_lock_attr == SERDES_IP_RX_FLEX_L3_CFG_FLX_FORCE_FRAME_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_freeze_in_state_attr == SERDES_IP_RX_FLEX_L3_CFG_FLX_FREEZE_IN_STATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_01_attr == 32'd65537
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_02_attr == 32'd2147516416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_03_attr == 32'd2181169152
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_04_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_05_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_06_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_07_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_08_attr == 32'd16384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_09_attr == 32'd131072
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_10_attr == 32'd2416050176
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_11_attr == 32'd33554432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_12_attr == 32'd1075838976
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_13_attr == 32'd301989888
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_14_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_15_attr == 32'd2181169152
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_16_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_17_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_18_attr == 32'd302006272
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_19_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_20_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_21_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_22_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_23_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_24_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_25_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_26_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_27_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_28_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_29_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_30_attr == 32'd33587200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_31_attr == 32'd1107329024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_02_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_03_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_10_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_12_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_13_attr == 5'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_15_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_18_attr == 5'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_31_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_02_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_03_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_10_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_11_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_12_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_13_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_15_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_18_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_30_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_31_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_one_state_inc_pulse_attr == SERDES_IP_RX_FLEX_L3_CFG_FLX_ONE_STATE_INC_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_00_attr == 32'd1056783
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_01_attr == 32'd9510943
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_02_attr == 32'd9502735
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_03_attr == 32'd9437199
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_04_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_05_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_06_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_07_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_08_attr == 32'd14680079
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_09_attr == 32'd26017807
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_10_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_11_attr == 32'd9502735
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_12_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_13_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_14_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_15_attr == 32'd25493519
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_16_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_17_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_18_attr == 32'd14942223
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_19_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_20_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_21_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_22_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_23_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_24_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_25_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_26_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_27_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_28_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_29_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_30_attr == 32'd1376271
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_31_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_00_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_01_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_02_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_03_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_04_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_05_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_06_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_07_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_08_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_09_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_10_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_11_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_12_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_13_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_14_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_15_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_16_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_17_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_18_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_19_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_20_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_21_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_22_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_23_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_24_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_25_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_26_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_27_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_28_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_29_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_30_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_31_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_state_force_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_state_force_value_en_attr == SERDES_IP_RX_FLEX_L3_CFG_FLX_STATE_FORCE_VALUE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_flx_stop_tmr_in_handshake_attr == SERDES_IP_RX_FLEX_L3_CFG_FLX_STOP_TMR_IN_HANDSHAKE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_00_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_00_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_01_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_01_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_02_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_02_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_03_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_03_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_04_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_04_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_05_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_05_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_06_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_06_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_07_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_07_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_08_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_08_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_09_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_09_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_10_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_10_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_11_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_12_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_13_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_14_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_15_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_15_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_16_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_17_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_18_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_19_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_19_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_20_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_20_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_21_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_21_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_22_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_22_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_23_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_23_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_24_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_24_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_25_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_25_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_26_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_26_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_27_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_27_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_28_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_28_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_29_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_29_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_30_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_30_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_31_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_31_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_02_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_03_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_10_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_12_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_13_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_15_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_18_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_31_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_00_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_00_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_01_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_01_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_02_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_02_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_03_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_03_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_04_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_04_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_05_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_05_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_06_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_06_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_07_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_07_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_08_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_08_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_09_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_09_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_10_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_11_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_12_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_13_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_14_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_15_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_16_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_17_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_18_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_19_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_19_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_20_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_20_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_21_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_21_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_22_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_22_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_23_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_23_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_24_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_24_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_25_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_25_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_26_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_26_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_27_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_27_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_28_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_28_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_29_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_29_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_30_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_30_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_31_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_31_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_00_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_02_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_03_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_10_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_12_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_13_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_15_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_18_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_31_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_etrregsynthlcfastclk_ready2_attr == SERDES_IP_SYNTH_FAST_L0_CFG_ETRREGSYNTHLCFASTCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_etrregsynthlcfastclk_ready_attr == SERDES_IP_SYNTH_FAST_L0_CFG_ETRREGSYNTHLCFASTCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_FAST_L0_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_FAST_L0_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_FAST_L0_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_FAST_L0_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_FAST_L0_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_fastregpwrup_en_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFAST_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFAST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_pg_disable_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFAST_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_refdiv_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_refdiv_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_refdiv_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_refdiv_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_static_divrate_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFAST_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_used_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFAST_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastbias_icc400uadj_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldacbg_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldacfsm_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastclk_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastclkstat_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastclkstat_ready_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastdccrst_disable_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastearlylock_dig_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastearlylock_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastfsm_cken_ovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastfsm_cken_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_locovr_muxd0_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_locovr_muxd1_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_locovr_muxd2_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_locovr_muxd3_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_locovr_muxd4_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpllstatus_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastppm_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrecal_on_pd_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_en_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastspare1_attr == 32'd45078
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfaststartup_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfaststartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfasttimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfasttimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_etrregsynthlcfastclk_ready2_attr == SERDES_IP_SYNTH_FAST_L1_CFG_ETRREGSYNTHLCFASTCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_etrregsynthlcfastclk_ready_attr == SERDES_IP_SYNTH_FAST_L1_CFG_ETRREGSYNTHLCFASTCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_FAST_L1_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_FAST_L1_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_FAST_L1_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_FAST_L1_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_FAST_L1_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_fastregpwrup_en_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFAST_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFAST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_pg_disable_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFAST_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_refdiv_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_refdiv_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_refdiv_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_refdiv_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_static_divrate_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFAST_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_used_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFAST_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastbias_icc400uadj_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldacbg_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldacfsm_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastclk_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastclkstat_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastclkstat_ready_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastdccrst_disable_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastearlylock_dig_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastearlylock_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastfsm_cken_ovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastfsm_cken_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_locovr_muxd0_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_locovr_muxd1_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_locovr_muxd2_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_locovr_muxd3_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_locovr_muxd4_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpllstatus_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastppm_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrecal_on_pd_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_en_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastspare1_attr == 32'd45078
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfaststartup_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfaststartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfasttimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfasttimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_etrregsynthlcfastclk_ready2_attr == SERDES_IP_SYNTH_FAST_L2_CFG_ETRREGSYNTHLCFASTCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_etrregsynthlcfastclk_ready_attr == SERDES_IP_SYNTH_FAST_L2_CFG_ETRREGSYNTHLCFASTCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_FAST_L2_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_FAST_L2_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_FAST_L2_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_FAST_L2_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_FAST_L2_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_fastregpwrup_en_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFAST_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFAST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_pg_disable_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFAST_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_refdiv_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_refdiv_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_refdiv_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_refdiv_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_static_divrate_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFAST_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_used_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFAST_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastbias_icc400uadj_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldacbg_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldacfsm_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastclk_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastclkstat_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastclkstat_ready_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastdccrst_disable_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastearlylock_dig_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastearlylock_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastfsm_cken_ovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastfsm_cken_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_locovr_muxd0_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_locovr_muxd1_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_locovr_muxd2_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_locovr_muxd3_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_locovr_muxd4_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpllstatus_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastppm_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrecal_on_pd_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_en_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastspare1_attr == 32'd45078
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfaststartup_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfaststartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfasttimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfasttimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_etrregsynthlcfastclk_ready2_attr == SERDES_IP_SYNTH_FAST_L3_CFG_ETRREGSYNTHLCFASTCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_etrregsynthlcfastclk_ready_attr == SERDES_IP_SYNTH_FAST_L3_CFG_ETRREGSYNTHLCFASTCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_FAST_L3_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_FAST_L3_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_FAST_L3_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_FAST_L3_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_FAST_L3_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_fastregpwrup_en_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFAST_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFAST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_pg_disable_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFAST_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_refdiv_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_refdiv_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_refdiv_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_refdiv_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_static_divrate_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFAST_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_used_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFAST_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastbias_icc400uadj_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldacbg_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldacfsm_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastclk_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastclkstat_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastclkstat_ready_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastdccrst_disable_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastearlylock_dig_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastearlylock_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastfsm_cken_ovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastfsm_cken_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_locovr_muxd0_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_locovr_muxd1_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_locovr_muxd2_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_locovr_muxd3_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_locovr_muxd4_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpllstatus_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastppm_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrecal_on_pd_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_en_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastspare1_attr == 32'd45078
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfaststartup_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfaststartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfasttimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfasttimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_etrregsynthlcmedclk_ready2_attr == SERDES_IP_SYNTH_MED_L0_CFG_ETRREGSYNTHLCMEDCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_etrregsynthlcmedclk_ready_attr == SERDES_IP_SYNTH_MED_L0_CFG_ETRREGSYNTHLCMEDCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_MED_L0_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_MED_L0_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_MED_L0_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_MED_L0_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_MED_L0_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_fastregpwrup_en_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_pg_disable_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_refdiv_muxd1_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_refdiv_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_refdiv_muxd3_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_refdiv_muxd4_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_static_divrate_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_txbitclkselect_muxd0_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_txbitclkselect_muxd1_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_txbitclkselect_muxd2_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_txbitclkselect_muxd3_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_txbitclkselect_muxd4_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_used_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedbias_icc400uadj_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldacbg_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldacfsm_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedclk_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedclkstat_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedclkstat_ready_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmeddccrst_disable_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedearlylock_dig_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedearlylock_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedfsm_cken_ovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedfsm_cken_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_locovr_muxd0_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_locovr_muxd1_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_locovr_muxd2_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_locovr_muxd3_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_locovr_muxd4_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpllstatus_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedppm_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrecal_on_pd_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_en_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_entry7_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedstartup_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedstartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedtimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedtimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_etrregsynthlcmedclk_ready2_attr == SERDES_IP_SYNTH_MED_L1_CFG_ETRREGSYNTHLCMEDCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_etrregsynthlcmedclk_ready_attr == SERDES_IP_SYNTH_MED_L1_CFG_ETRREGSYNTHLCMEDCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_MED_L1_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_MED_L1_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_MED_L1_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_MED_L1_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_MED_L1_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_fastregpwrup_en_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_pg_disable_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_refdiv_muxd0_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_refdiv_muxd1_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_refdiv_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_refdiv_muxd3_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_refdiv_muxd4_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_static_divrate_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_txbitclkselect_muxd0_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_txbitclkselect_muxd1_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_txbitclkselect_muxd2_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_txbitclkselect_muxd3_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_txbitclkselect_muxd4_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_used_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_USED_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedbias_icc400uadj_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldacbg_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldacfsm_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedclk_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedclkstat_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedclkstat_ready_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmeddccrst_disable_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedearlylock_dig_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedearlylock_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedfsm_cken_ovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedfsm_cken_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_locovr_muxd0_attr == 7'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_locovr_muxd1_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_locovr_muxd2_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_locovr_muxd3_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_locovr_muxd4_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpllstatus_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedppm_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrecal_on_pd_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_en_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedstartup_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedstartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedtimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedtimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_etrregsynthlcmedclk_ready2_attr == SERDES_IP_SYNTH_MED_L2_CFG_ETRREGSYNTHLCMEDCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_etrregsynthlcmedclk_ready_attr == SERDES_IP_SYNTH_MED_L2_CFG_ETRREGSYNTHLCMEDCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_MED_L2_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_MED_L2_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_MED_L2_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_MED_L2_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_MED_L2_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_fastregpwrup_en_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_pg_disable_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_refdiv_muxd1_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_refdiv_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_refdiv_muxd3_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_refdiv_muxd4_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_static_divrate_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_txbitclkselect_muxd0_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_txbitclkselect_muxd1_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_txbitclkselect_muxd2_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_txbitclkselect_muxd3_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_txbitclkselect_muxd4_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_used_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedbias_icc400uadj_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldacbg_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldacfsm_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedclk_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedclkstat_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedclkstat_ready_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmeddccrst_disable_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedearlylock_dig_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedearlylock_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedfsm_cken_ovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedfsm_cken_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_locovr_muxd0_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_locovr_muxd1_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_locovr_muxd2_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_locovr_muxd3_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_locovr_muxd4_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpllstatus_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedppm_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrecal_on_pd_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_en_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_entry7_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedstartup_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedstartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedtimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedtimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_etrregsynthlcmedclk_ready2_attr == SERDES_IP_SYNTH_MED_L3_CFG_ETRREGSYNTHLCMEDCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_etrregsynthlcmedclk_ready_attr == SERDES_IP_SYNTH_MED_L3_CFG_ETRREGSYNTHLCMEDCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_MED_L3_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_MED_L3_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_MED_L3_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_MED_L3_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_MED_L3_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_fastregpwrup_en_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_pg_disable_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_refdiv_muxd1_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_refdiv_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_refdiv_muxd3_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_refdiv_muxd4_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_static_divrate_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_txbitclkselect_muxd0_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_txbitclkselect_muxd1_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_txbitclkselect_muxd2_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_txbitclkselect_muxd3_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_txbitclkselect_muxd4_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_used_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedbias_icc400uadj_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldacbg_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldacfsm_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedclk_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedclkstat_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedclkstat_ready_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmeddccrst_disable_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedearlylock_dig_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedearlylock_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedfsm_cken_ovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedfsm_cken_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_locovr_muxd0_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_locovr_muxd1_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_locovr_muxd2_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_locovr_muxd3_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_locovr_muxd4_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpllstatus_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedppm_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrecal_on_pd_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_en_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_entry7_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedstartup_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedstartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedtimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedtimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_etrregsynthlcslowclk_ready2_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_ETRREGSYNTHLCSLOWCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_etrregsynthlcslowclk_ready_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_ETRREGSYNTHLCSLOWCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_fastregpwrup_en_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_pg_disable_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_refdiv_muxd0_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_refdiv_muxd1_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_refdiv_muxd2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_refdiv_muxd3_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_refdiv_muxd4_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_static_divrate_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_txbitclkselect_muxd0_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_txbitclkselect_muxd1_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_txbitclkselect_muxd2_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_txbitclkselect_muxd3_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_txbitclkselect_muxd4_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_used_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowbias_icc400uadj_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldacbg_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldacfsm_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowclk_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowclkstat_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowclkstat_ready_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowdccrst_disable_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowearlylock_dig_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowearlylock_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowfsm_cken_ovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowfsm_cken_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_locovr_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_locovr_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_locovr_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_locovr_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_locovr_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpllstatus_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowppm_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_clk_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrecal_on_pd_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_en_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_entry7_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowstartup_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowstartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowtimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowtimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_etrregsynthlcslowclk_ready2_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_ETRREGSYNTHLCSLOWCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_etrregsynthlcslowclk_ready_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_ETRREGSYNTHLCSLOWCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_fastregpwrup_en_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_pg_disable_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_refdiv_muxd0_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_refdiv_muxd1_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_refdiv_muxd2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_refdiv_muxd3_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_refdiv_muxd4_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_static_divrate_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_txbitclkselect_muxd0_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_txbitclkselect_muxd1_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_txbitclkselect_muxd2_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_txbitclkselect_muxd3_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_txbitclkselect_muxd4_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_used_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowbias_icc400uadj_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldacbg_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldacfsm_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowclk_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowclkstat_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowclkstat_ready_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowdccrst_disable_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowearlylock_dig_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowearlylock_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowfsm_cken_ovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowfsm_cken_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_locovr_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_locovr_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_locovr_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_locovr_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_locovr_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpllstatus_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowppm_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_clk_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrecal_on_pd_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_en_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_entry7_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowstartup_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowstartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowtimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowtimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_etrregsynthlcslowclk_ready2_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_ETRREGSYNTHLCSLOWCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_etrregsynthlcslowclk_ready_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_ETRREGSYNTHLCSLOWCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_fastregpwrup_en_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_pg_disable_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_refdiv_muxd0_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_refdiv_muxd1_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_refdiv_muxd2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_refdiv_muxd3_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_refdiv_muxd4_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_static_divrate_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_txbitclkselect_muxd0_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_txbitclkselect_muxd1_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_txbitclkselect_muxd2_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_txbitclkselect_muxd3_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_txbitclkselect_muxd4_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_used_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowbias_icc400uadj_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldacbg_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldacfsm_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowclk_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowclkstat_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowclkstat_ready_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowdccrst_disable_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowearlylock_dig_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowearlylock_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowfsm_cken_ovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowfsm_cken_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_locovr_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_locovr_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_locovr_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_locovr_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_locovr_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpllstatus_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowppm_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_clk_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrecal_on_pd_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_en_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_entry7_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowstartup_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowstartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowtimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowtimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_etrregsynthlcslowclk_ready2_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_ETRREGSYNTHLCSLOWCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_etrregsynthlcslowclk_ready_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_ETRREGSYNTHLCSLOWCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_fastregpwrup_en_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_pg_disable_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_refdiv_muxd0_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_refdiv_muxd1_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_refdiv_muxd2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_refdiv_muxd3_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_refdiv_muxd4_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_static_divrate_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_txbitclkselect_muxd0_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_txbitclkselect_muxd1_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_txbitclkselect_muxd2_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_txbitclkselect_muxd3_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_txbitclkselect_muxd4_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_used_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowbias_icc400uadj_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldacbg_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldacfsm_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowclk_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowclkstat_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowclkstat_ready_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowdccrst_disable_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowearlylock_dig_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowearlylock_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowfsm_cken_ovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowfsm_cken_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_locovr_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_locovr_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_locovr_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_locovr_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_locovr_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpllstatus_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowppm_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_clk_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrecal_on_pd_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_en_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_entry7_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowstartup_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowstartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowtimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowtimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_an_idle_stiky_clear_attr == SERDES_SHIM_AN_L0_CFG_AN_IDLE_STIKY_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_an_reserv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_debug_fw_reg1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_debug_fw_reg2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_debug_fw_reg3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_debug_fw_reg4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_dig_cdr_disable_attr == SERDES_SHIM_AN_L0_CFG_DIG_CDR_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_direct_control_bus0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_direct_control_bus1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_direct_control_bus2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_direct_control_bus3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_direct_control_bus4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_direct_control_bus5_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_direct_control_bus6_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_direct_control_bus_en_attr == SERDES_SHIM_AN_L0_CFG_DIRECT_CONTROL_BUS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_edge_too_long_disable_attr == SERDES_SHIM_AN_L0_CFG_EDGE_TOO_LONG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_edge_too_short_disable_attr == SERDES_SHIM_AN_L0_CFG_EDGE_TOO_SHORT_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_page_max_timer_disable_attr == SERDES_SHIM_AN_L0_CFG_PAGE_MAX_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_page_min_timer_disable_attr == SERDES_SHIM_AN_L0_CFG_PAGE_MIN_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_pcs_lock_attr == SERDES_SHIM_AN_L0_CFG_PCS_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_pcs_tx_bypass_sample_attr == SERDES_SHIM_AN_L0_CFG_PCS_TX_BYPASS_SAMPLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_rx_enable_m_attr == SERDES_SHIM_AN_L0_CFG_RX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_rx_lcw_re_attr == SERDES_SHIM_AN_L0_CFG_RX_LCW_RE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_rx_pma_en_attr == SERDES_SHIM_AN_L0_CFG_RX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_rx_unencoder_ctrl_en_attr == SERDES_SHIM_AN_L0_CFG_RX_UNENCODER_CTRL_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_rx_unencoder_gray_en_attr == SERDES_SHIM_AN_L0_CFG_RX_UNENCODER_GRAY_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_rx_unencoder_pam_bitorder_swz_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_rx_unencoder_pam_en_attr == SERDES_SHIM_AN_L0_CFG_RX_UNENCODER_PAM_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_rx_unencoder_polarity_swz_attr == SERDES_SHIM_AN_L0_CFG_RX_UNENCODER_POLARITY_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_rx_unencoder_precode_en_attr == SERDES_SHIM_AN_L0_CFG_RX_UNENCODER_PRECODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_rx_unencoder_width_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_serdes_irq_bus_sel_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_serdes_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_serdes_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_serdes_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_transmit_mode_scan_mode_dbg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_tx_complete_ack_attr == SERDES_SHIM_AN_L0_CFG_TX_COMPLETE_ACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_tx_enable_m_attr == SERDES_SHIM_AN_L0_CFG_TX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_tx_lcw_high_attr == 27'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_tx_lcw_low_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_tx_lcw_reserv_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_tx_lcw_we_attr == SERDES_SHIM_AN_L0_CFG_TX_LCW_WE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l0_cfg_tx_pma_en_attr == SERDES_SHIM_AN_L0_CFG_TX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_an_idle_stiky_clear_attr == SERDES_SHIM_AN_L1_CFG_AN_IDLE_STIKY_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_an_reserv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_debug_fw_reg1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_debug_fw_reg2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_debug_fw_reg3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_debug_fw_reg4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_dig_cdr_disable_attr == SERDES_SHIM_AN_L1_CFG_DIG_CDR_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_direct_control_bus0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_direct_control_bus1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_direct_control_bus2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_direct_control_bus3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_direct_control_bus4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_direct_control_bus5_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_direct_control_bus6_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_direct_control_bus_en_attr == SERDES_SHIM_AN_L1_CFG_DIRECT_CONTROL_BUS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_edge_too_long_disable_attr == SERDES_SHIM_AN_L1_CFG_EDGE_TOO_LONG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_edge_too_short_disable_attr == SERDES_SHIM_AN_L1_CFG_EDGE_TOO_SHORT_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_page_max_timer_disable_attr == SERDES_SHIM_AN_L1_CFG_PAGE_MAX_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_page_min_timer_disable_attr == SERDES_SHIM_AN_L1_CFG_PAGE_MIN_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_pcs_lock_attr == SERDES_SHIM_AN_L1_CFG_PCS_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_pcs_tx_bypass_sample_attr == SERDES_SHIM_AN_L1_CFG_PCS_TX_BYPASS_SAMPLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_rx_enable_m_attr == SERDES_SHIM_AN_L1_CFG_RX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_rx_lcw_re_attr == SERDES_SHIM_AN_L1_CFG_RX_LCW_RE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_rx_pma_en_attr == SERDES_SHIM_AN_L1_CFG_RX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_rx_unencoder_ctrl_en_attr == SERDES_SHIM_AN_L1_CFG_RX_UNENCODER_CTRL_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_rx_unencoder_gray_en_attr == SERDES_SHIM_AN_L1_CFG_RX_UNENCODER_GRAY_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_rx_unencoder_pam_bitorder_swz_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_rx_unencoder_pam_en_attr == SERDES_SHIM_AN_L1_CFG_RX_UNENCODER_PAM_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_rx_unencoder_polarity_swz_attr == SERDES_SHIM_AN_L1_CFG_RX_UNENCODER_POLARITY_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_rx_unencoder_precode_en_attr == SERDES_SHIM_AN_L1_CFG_RX_UNENCODER_PRECODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_rx_unencoder_width_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_serdes_irq_bus_sel_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_serdes_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_serdes_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_serdes_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_transmit_mode_scan_mode_dbg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_tx_complete_ack_attr == SERDES_SHIM_AN_L1_CFG_TX_COMPLETE_ACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_tx_enable_m_attr == SERDES_SHIM_AN_L1_CFG_TX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_tx_lcw_high_attr == 27'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_tx_lcw_low_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_tx_lcw_reserv_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_tx_lcw_we_attr == SERDES_SHIM_AN_L1_CFG_TX_LCW_WE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l1_cfg_tx_pma_en_attr == SERDES_SHIM_AN_L1_CFG_TX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_an_idle_stiky_clear_attr == SERDES_SHIM_AN_L2_CFG_AN_IDLE_STIKY_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_an_reserv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_debug_fw_reg1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_debug_fw_reg2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_debug_fw_reg3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_debug_fw_reg4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_dig_cdr_disable_attr == SERDES_SHIM_AN_L2_CFG_DIG_CDR_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_direct_control_bus0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_direct_control_bus1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_direct_control_bus2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_direct_control_bus3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_direct_control_bus4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_direct_control_bus5_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_direct_control_bus6_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_direct_control_bus_en_attr == SERDES_SHIM_AN_L2_CFG_DIRECT_CONTROL_BUS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_edge_too_long_disable_attr == SERDES_SHIM_AN_L2_CFG_EDGE_TOO_LONG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_edge_too_short_disable_attr == SERDES_SHIM_AN_L2_CFG_EDGE_TOO_SHORT_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_page_max_timer_disable_attr == SERDES_SHIM_AN_L2_CFG_PAGE_MAX_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_page_min_timer_disable_attr == SERDES_SHIM_AN_L2_CFG_PAGE_MIN_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_pcs_lock_attr == SERDES_SHIM_AN_L2_CFG_PCS_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_pcs_tx_bypass_sample_attr == SERDES_SHIM_AN_L2_CFG_PCS_TX_BYPASS_SAMPLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_rx_enable_m_attr == SERDES_SHIM_AN_L2_CFG_RX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_rx_lcw_re_attr == SERDES_SHIM_AN_L2_CFG_RX_LCW_RE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_rx_pma_en_attr == SERDES_SHIM_AN_L2_CFG_RX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_rx_unencoder_ctrl_en_attr == SERDES_SHIM_AN_L2_CFG_RX_UNENCODER_CTRL_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_rx_unencoder_gray_en_attr == SERDES_SHIM_AN_L2_CFG_RX_UNENCODER_GRAY_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_rx_unencoder_pam_bitorder_swz_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_rx_unencoder_pam_en_attr == SERDES_SHIM_AN_L2_CFG_RX_UNENCODER_PAM_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_rx_unencoder_polarity_swz_attr == SERDES_SHIM_AN_L2_CFG_RX_UNENCODER_POLARITY_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_rx_unencoder_precode_en_attr == SERDES_SHIM_AN_L2_CFG_RX_UNENCODER_PRECODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_rx_unencoder_width_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_serdes_irq_bus_sel_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_serdes_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_serdes_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_serdes_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_transmit_mode_scan_mode_dbg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_tx_complete_ack_attr == SERDES_SHIM_AN_L2_CFG_TX_COMPLETE_ACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_tx_enable_m_attr == SERDES_SHIM_AN_L2_CFG_TX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_tx_lcw_high_attr == 27'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_tx_lcw_low_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_tx_lcw_reserv_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_tx_lcw_we_attr == SERDES_SHIM_AN_L2_CFG_TX_LCW_WE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l2_cfg_tx_pma_en_attr == SERDES_SHIM_AN_L2_CFG_TX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_an_idle_stiky_clear_attr == SERDES_SHIM_AN_L3_CFG_AN_IDLE_STIKY_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_an_reserv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_debug_fw_reg1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_debug_fw_reg2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_debug_fw_reg3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_debug_fw_reg4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_dig_cdr_disable_attr == SERDES_SHIM_AN_L3_CFG_DIG_CDR_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_direct_control_bus0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_direct_control_bus1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_direct_control_bus2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_direct_control_bus3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_direct_control_bus4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_direct_control_bus5_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_direct_control_bus6_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_direct_control_bus_en_attr == SERDES_SHIM_AN_L3_CFG_DIRECT_CONTROL_BUS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_edge_too_long_disable_attr == SERDES_SHIM_AN_L3_CFG_EDGE_TOO_LONG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_edge_too_short_disable_attr == SERDES_SHIM_AN_L3_CFG_EDGE_TOO_SHORT_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_page_max_timer_disable_attr == SERDES_SHIM_AN_L3_CFG_PAGE_MAX_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_page_min_timer_disable_attr == SERDES_SHIM_AN_L3_CFG_PAGE_MIN_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_pcs_lock_attr == SERDES_SHIM_AN_L3_CFG_PCS_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_pcs_tx_bypass_sample_attr == SERDES_SHIM_AN_L3_CFG_PCS_TX_BYPASS_SAMPLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_rx_enable_m_attr == SERDES_SHIM_AN_L3_CFG_RX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_rx_lcw_re_attr == SERDES_SHIM_AN_L3_CFG_RX_LCW_RE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_rx_pma_en_attr == SERDES_SHIM_AN_L3_CFG_RX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_rx_unencoder_ctrl_en_attr == SERDES_SHIM_AN_L3_CFG_RX_UNENCODER_CTRL_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_rx_unencoder_gray_en_attr == SERDES_SHIM_AN_L3_CFG_RX_UNENCODER_GRAY_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_rx_unencoder_pam_bitorder_swz_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_rx_unencoder_pam_en_attr == SERDES_SHIM_AN_L3_CFG_RX_UNENCODER_PAM_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_rx_unencoder_polarity_swz_attr == SERDES_SHIM_AN_L3_CFG_RX_UNENCODER_POLARITY_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_rx_unencoder_precode_en_attr == SERDES_SHIM_AN_L3_CFG_RX_UNENCODER_PRECODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_rx_unencoder_width_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_serdes_irq_bus_sel_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_serdes_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_serdes_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_serdes_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_transmit_mode_scan_mode_dbg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_tx_complete_ack_attr == SERDES_SHIM_AN_L3_CFG_TX_COMPLETE_ACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_tx_enable_m_attr == SERDES_SHIM_AN_L3_CFG_TX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_tx_lcw_high_attr == 27'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_tx_lcw_low_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_tx_lcw_reserv_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_tx_lcw_we_attr == SERDES_SHIM_AN_L3_CFG_TX_LCW_WE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_an_l3_cfg_tx_pma_en_attr == SERDES_SHIM_AN_L3_CFG_TX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_apb_dsp_clk_sel_attr == SERDES_SHIM_CAR_L0_CFG_APB_DSP_CLK_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_apb_dsp_divn_en_attr == SERDES_SHIM_CAR_L0_CFG_APB_DSP_DIVN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_apb_dsp_divn_value_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_apb_dsp_pclken_attr == SERDES_SHIM_CAR_L0_CFG_APB_DSP_PCLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_apb_dsp_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_APB_DSP_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_dp_rx_80b_swz_attr == SERDES_SHIM_CAR_L0_CFG_DP_RX_80B_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_dp_tx_80b_swz_attr == SERDES_SHIM_CAR_L0_CFG_DP_TX_80B_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_eee_alert_force_en_attr == SERDES_SHIM_CAR_L0_CFG_EEE_ALERT_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_eee_alert_force_val_attr == SERDES_SHIM_CAR_L0_CFG_EEE_ALERT_FORCE_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_flux_srds_tx_divn_clken_attr == SERDES_SHIM_CAR_L0_CFG_FLUX_SRDS_TX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_iflux_tx_or_apb_clk_for_ux_ctrl_clk_sel_attr == SERDES_SHIM_CAR_L0_CFG_IFLUX_TX_OR_APB_CLK_FOR_UX_CTRL_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_oflux_srds_rx_clken_attr == SERDES_SHIM_CAR_L0_CFG_OFLUX_SRDS_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_oflux_srds_rx_divn_clken_attr == SERDES_SHIM_CAR_L0_CFG_OFLUX_SRDS_RX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_oflux_srds_tx_clken_attr == SERDES_SHIM_CAR_L0_CFG_OFLUX_SRDS_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_pcs_ick_ctrl_cmn_clk_sel_attr == SERDES_SHIM_CAR_L0_CFG_PCS_ICK_CTRL_CMN_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_pcs_ick_ctrl_l0_clk_sel_attr == SERDES_SHIM_CAR_L0_CFG_PCS_ICK_CTRL_L0_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_rxovrcdrlock2data_attr == SERDES_SHIM_CAR_L0_CFG_RXOVRCDRLOCK2DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_rxovrcdrlock2data_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_rxovrcdrlock2dataen_attr == SERDES_SHIM_CAR_L0_CFG_RXOVRCDRLOCK2DATAEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_rxovrcdrlock2dataen_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_rxpstate_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_rxpstate_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_srds_an_rx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_AN_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_srds_an_rx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_AN_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_srds_an_tx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_AN_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_srds_an_tx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_AN_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_srds_ctrl_rx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_CTRL_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_srds_ctrl_rx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_CTRL_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_srds_ctrl_tx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_CTRL_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_srds_ctrl_tx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_CTRL_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_srds_dfx_rx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_DFX_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_srds_dfx_rx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_DFX_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_srds_dfx_tx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_DFX_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_srds_dfx_tx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_DFX_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_srds_dsp_rx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_DSP_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_srds_dsp_rx_isi_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_DSP_RX_ISI_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_srds_dsp_rx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_DSP_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_srds_eee_rx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_EEE_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_srds_eee_rx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_EEE_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_srds_eee_tx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_EEE_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_srds_eee_tx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_EEE_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_srds_pcs_tx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_PCS_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_srds_pcs_tx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_PCS_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_srds_trn_rx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_TRN_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_srds_trn_rx_divn_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_TRN_RX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_srds_trn_rx_divn_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_TRN_RX_DIVN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_srds_trn_rx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_TRN_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_srds_trn_tx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_TRN_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_srds_trn_tx_divn_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_TRN_TX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_srds_trn_tx_divn_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_TRN_TX_DIVN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_srds_trn_tx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_TRN_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_srds_ux_ctrl_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_UX_CTRL_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_srds_ux_ctrl_cmn_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_UX_CTRL_CMN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_srds_ux_ctrl_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_UX_CTRL_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_srds_ux_tx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_UX_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_srds_ux_tx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_UX_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_timer_en_attr == SERDES_SHIM_CAR_L0_CFG_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_timer_value_attr == 8'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_transmit_mode_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_tx_postdiv_clk_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_txelecidle_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_txelecidle_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_txpstate_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l0_cfg_txpstate_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_apb_dsp_clk_sel_attr == SERDES_SHIM_CAR_L1_CFG_APB_DSP_CLK_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_apb_dsp_divn_en_attr == SERDES_SHIM_CAR_L1_CFG_APB_DSP_DIVN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_apb_dsp_divn_value_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_apb_dsp_pclken_attr == SERDES_SHIM_CAR_L1_CFG_APB_DSP_PCLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_apb_dsp_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_APB_DSP_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_dp_rx_80b_swz_attr == SERDES_SHIM_CAR_L1_CFG_DP_RX_80B_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_dp_tx_80b_swz_attr == SERDES_SHIM_CAR_L1_CFG_DP_TX_80B_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_eee_alert_force_en_attr == SERDES_SHIM_CAR_L1_CFG_EEE_ALERT_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_eee_alert_force_val_attr == SERDES_SHIM_CAR_L1_CFG_EEE_ALERT_FORCE_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_flux_srds_tx_divn_clken_attr == SERDES_SHIM_CAR_L1_CFG_FLUX_SRDS_TX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_iflux_tx_or_apb_clk_for_ux_ctrl_clk_sel_attr == SERDES_SHIM_CAR_L1_CFG_IFLUX_TX_OR_APB_CLK_FOR_UX_CTRL_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_oflux_srds_rx_clken_attr == SERDES_SHIM_CAR_L1_CFG_OFLUX_SRDS_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_oflux_srds_rx_divn_clken_attr == SERDES_SHIM_CAR_L1_CFG_OFLUX_SRDS_RX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_oflux_srds_tx_clken_attr == SERDES_SHIM_CAR_L1_CFG_OFLUX_SRDS_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_pcs_ick_ctrl_cmn_clk_sel_attr == SERDES_SHIM_CAR_L1_CFG_PCS_ICK_CTRL_CMN_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_pcs_ick_ctrl_l0_clk_sel_attr == SERDES_SHIM_CAR_L1_CFG_PCS_ICK_CTRL_L0_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_rxovrcdrlock2data_attr == SERDES_SHIM_CAR_L1_CFG_RXOVRCDRLOCK2DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_rxovrcdrlock2data_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_rxovrcdrlock2dataen_attr == SERDES_SHIM_CAR_L1_CFG_RXOVRCDRLOCK2DATAEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_rxovrcdrlock2dataen_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_rxpstate_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_rxpstate_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_srds_an_rx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_AN_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_srds_an_rx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_AN_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_srds_an_tx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_AN_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_srds_an_tx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_AN_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_srds_ctrl_rx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_CTRL_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_srds_ctrl_rx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_CTRL_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_srds_ctrl_tx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_CTRL_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_srds_ctrl_tx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_CTRL_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_srds_dfx_rx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_DFX_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_srds_dfx_rx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_DFX_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_srds_dfx_tx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_DFX_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_srds_dfx_tx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_DFX_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_srds_dsp_rx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_DSP_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_srds_dsp_rx_isi_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_DSP_RX_ISI_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_srds_dsp_rx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_DSP_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_srds_eee_rx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_EEE_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_srds_eee_rx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_EEE_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_srds_eee_tx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_EEE_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_srds_eee_tx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_EEE_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_srds_pcs_tx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_PCS_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_srds_pcs_tx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_PCS_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_srds_trn_rx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_TRN_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_srds_trn_rx_divn_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_TRN_RX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_srds_trn_rx_divn_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_TRN_RX_DIVN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_srds_trn_rx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_TRN_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_srds_trn_tx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_TRN_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_srds_trn_tx_divn_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_TRN_TX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_srds_trn_tx_divn_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_TRN_TX_DIVN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_srds_trn_tx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_TRN_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_srds_ux_ctrl_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_UX_CTRL_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_srds_ux_ctrl_cmn_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_UX_CTRL_CMN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_srds_ux_ctrl_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_UX_CTRL_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_srds_ux_tx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_UX_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_srds_ux_tx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_UX_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_timer_en_attr == SERDES_SHIM_CAR_L1_CFG_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_timer_value_attr == 8'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_transmit_mode_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_tx_postdiv_clk_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_txelecidle_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_txelecidle_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_txpstate_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l1_cfg_txpstate_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_apb_dsp_clk_sel_attr == SERDES_SHIM_CAR_L2_CFG_APB_DSP_CLK_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_apb_dsp_divn_en_attr == SERDES_SHIM_CAR_L2_CFG_APB_DSP_DIVN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_apb_dsp_divn_value_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_apb_dsp_pclken_attr == SERDES_SHIM_CAR_L2_CFG_APB_DSP_PCLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_apb_dsp_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_APB_DSP_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_dp_rx_80b_swz_attr == SERDES_SHIM_CAR_L2_CFG_DP_RX_80B_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_dp_tx_80b_swz_attr == SERDES_SHIM_CAR_L2_CFG_DP_TX_80B_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_eee_alert_force_en_attr == SERDES_SHIM_CAR_L2_CFG_EEE_ALERT_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_eee_alert_force_val_attr == SERDES_SHIM_CAR_L2_CFG_EEE_ALERT_FORCE_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_flux_srds_tx_divn_clken_attr == SERDES_SHIM_CAR_L2_CFG_FLUX_SRDS_TX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_iflux_tx_or_apb_clk_for_ux_ctrl_clk_sel_attr == SERDES_SHIM_CAR_L2_CFG_IFLUX_TX_OR_APB_CLK_FOR_UX_CTRL_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_oflux_srds_rx_clken_attr == SERDES_SHIM_CAR_L2_CFG_OFLUX_SRDS_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_oflux_srds_rx_divn_clken_attr == SERDES_SHIM_CAR_L2_CFG_OFLUX_SRDS_RX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_oflux_srds_tx_clken_attr == SERDES_SHIM_CAR_L2_CFG_OFLUX_SRDS_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_pcs_ick_ctrl_cmn_clk_sel_attr == SERDES_SHIM_CAR_L2_CFG_PCS_ICK_CTRL_CMN_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_pcs_ick_ctrl_l0_clk_sel_attr == SERDES_SHIM_CAR_L2_CFG_PCS_ICK_CTRL_L0_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_rxovrcdrlock2data_attr == SERDES_SHIM_CAR_L2_CFG_RXOVRCDRLOCK2DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_rxovrcdrlock2data_src_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_rxovrcdrlock2dataen_attr == SERDES_SHIM_CAR_L2_CFG_RXOVRCDRLOCK2DATAEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_rxovrcdrlock2dataen_src_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_rxpstate_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_rxpstate_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_srds_an_rx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_AN_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_srds_an_rx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_AN_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_srds_an_tx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_AN_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_srds_an_tx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_AN_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_srds_ctrl_rx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_CTRL_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_srds_ctrl_rx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_CTRL_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_srds_ctrl_tx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_CTRL_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_srds_ctrl_tx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_CTRL_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_srds_dfx_rx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_DFX_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_srds_dfx_rx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_DFX_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_srds_dfx_tx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_DFX_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_srds_dfx_tx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_DFX_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_srds_dsp_rx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_DSP_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_srds_dsp_rx_isi_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_DSP_RX_ISI_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_srds_dsp_rx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_DSP_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_srds_eee_rx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_EEE_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_srds_eee_rx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_EEE_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_srds_eee_tx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_EEE_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_srds_eee_tx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_EEE_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_srds_pcs_tx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_PCS_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_srds_pcs_tx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_PCS_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_srds_trn_rx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_TRN_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_srds_trn_rx_divn_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_TRN_RX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_srds_trn_rx_divn_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_TRN_RX_DIVN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_srds_trn_rx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_TRN_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_srds_trn_tx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_TRN_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_srds_trn_tx_divn_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_TRN_TX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_srds_trn_tx_divn_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_TRN_TX_DIVN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_srds_trn_tx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_TRN_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_srds_ux_ctrl_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_UX_CTRL_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_srds_ux_ctrl_cmn_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_UX_CTRL_CMN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_srds_ux_ctrl_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_UX_CTRL_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_srds_ux_tx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_UX_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_srds_ux_tx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_UX_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_timer_en_attr == SERDES_SHIM_CAR_L2_CFG_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_timer_value_attr == 8'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_transmit_mode_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_tx_postdiv_clk_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_txelecidle_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_txelecidle_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_txpstate_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l2_cfg_txpstate_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_apb_dsp_clk_sel_attr == SERDES_SHIM_CAR_L3_CFG_APB_DSP_CLK_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_apb_dsp_divn_en_attr == SERDES_SHIM_CAR_L3_CFG_APB_DSP_DIVN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_apb_dsp_divn_value_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_apb_dsp_pclken_attr == SERDES_SHIM_CAR_L3_CFG_APB_DSP_PCLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_apb_dsp_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_APB_DSP_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_dp_rx_80b_swz_attr == SERDES_SHIM_CAR_L3_CFG_DP_RX_80B_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_dp_tx_80b_swz_attr == SERDES_SHIM_CAR_L3_CFG_DP_TX_80B_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_eee_alert_force_en_attr == SERDES_SHIM_CAR_L3_CFG_EEE_ALERT_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_eee_alert_force_val_attr == SERDES_SHIM_CAR_L3_CFG_EEE_ALERT_FORCE_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_flux_srds_tx_divn_clken_attr == SERDES_SHIM_CAR_L3_CFG_FLUX_SRDS_TX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_iflux_tx_or_apb_clk_for_ux_ctrl_clk_sel_attr == SERDES_SHIM_CAR_L3_CFG_IFLUX_TX_OR_APB_CLK_FOR_UX_CTRL_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_oflux_srds_rx_clken_attr == SERDES_SHIM_CAR_L3_CFG_OFLUX_SRDS_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_oflux_srds_rx_divn_clken_attr == SERDES_SHIM_CAR_L3_CFG_OFLUX_SRDS_RX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_oflux_srds_tx_clken_attr == SERDES_SHIM_CAR_L3_CFG_OFLUX_SRDS_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_pcs_ick_ctrl_cmn_clk_sel_attr == SERDES_SHIM_CAR_L3_CFG_PCS_ICK_CTRL_CMN_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_pcs_ick_ctrl_l0_clk_sel_attr == SERDES_SHIM_CAR_L3_CFG_PCS_ICK_CTRL_L0_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_rxovrcdrlock2data_attr == SERDES_SHIM_CAR_L3_CFG_RXOVRCDRLOCK2DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_rxovrcdrlock2data_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_rxovrcdrlock2dataen_attr == SERDES_SHIM_CAR_L3_CFG_RXOVRCDRLOCK2DATAEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_rxovrcdrlock2dataen_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_rxpstate_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_rxpstate_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_srds_an_rx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_AN_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_srds_an_rx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_AN_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_srds_an_tx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_AN_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_srds_an_tx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_AN_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_srds_ctrl_rx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_CTRL_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_srds_ctrl_rx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_CTRL_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_srds_ctrl_tx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_CTRL_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_srds_ctrl_tx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_CTRL_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_srds_dfx_rx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_DFX_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_srds_dfx_rx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_DFX_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_srds_dfx_tx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_DFX_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_srds_dfx_tx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_DFX_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_srds_dsp_rx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_DSP_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_srds_dsp_rx_isi_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_DSP_RX_ISI_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_srds_dsp_rx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_DSP_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_srds_eee_rx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_EEE_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_srds_eee_rx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_EEE_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_srds_eee_tx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_EEE_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_srds_eee_tx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_EEE_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_srds_pcs_tx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_PCS_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_srds_pcs_tx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_PCS_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_srds_trn_rx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_TRN_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_srds_trn_rx_divn_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_TRN_RX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_srds_trn_rx_divn_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_TRN_RX_DIVN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_srds_trn_rx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_TRN_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_srds_trn_tx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_TRN_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_srds_trn_tx_divn_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_TRN_TX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_srds_trn_tx_divn_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_TRN_TX_DIVN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_srds_trn_tx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_TRN_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_srds_ux_ctrl_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_UX_CTRL_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_srds_ux_ctrl_cmn_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_UX_CTRL_CMN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_srds_ux_ctrl_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_UX_CTRL_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_srds_ux_tx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_UX_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_srds_ux_tx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_UX_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_timer_en_attr == SERDES_SHIM_CAR_L3_CFG_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_timer_value_attr == 8'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_transmit_mode_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_tx_postdiv_clk_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_txelecidle_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_txelecidle_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_txpstate_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_car_l3_cfg_txpstate_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_cpu_atresetn_attr == SERDES_SHIM_CPU_PM_CFG_CPU_ATRESETN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_cpu_breakin_attr == SERDES_SHIM_CPU_PM_CFG_CPU_BREAKIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_cpu_breakoutack_attr == SERDES_SHIM_CPU_PM_CFG_CPU_BREAKOUTACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_cpu_crosstriggerin_attr == SERDES_SHIM_CPU_PM_CFG_CPU_CROSSTRIGGERIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_cpu_crosstriggeroutack_attr == SERDES_SHIM_CPU_PM_CFG_CPU_CROSSTRIGGEROUTACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_cpu_ocdhaltonreset_attr == SERDES_SHIM_CPU_PM_CFG_CPU_OCDHALTONRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_cpu_pdebugenable_attr == SERDES_SHIM_CPU_PM_CFG_CPU_PDEBUGENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_cpu_prid_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_cpu_statvectorsel_attr == SERDES_SHIM_CPU_PM_CFG_CPU_STATVECTORSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_cpu_tmodeclkgateoverride_reserved_attr == SERDES_SHIM_CPU_PM_CFG_CPU_TMODECLKGATEOVERRIDE_RESERVED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_dram_pwr_mgmt_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_dram0_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_DRAM0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_dram1_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_DRAM1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_dram2_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_DRAM2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_dram3_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_DRAM3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_fifo_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_FIFO_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_iram0_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_IRAM0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_iram1_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_IRAM1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_iram2_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_IRAM2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_iram3_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_IRAM3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_iram4_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_IRAM4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_iram5_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_IRAM5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_iram6_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_IRAM6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_iram7_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_IRAM7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_trace_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_TRACE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_dram0_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_DRAM0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_dram1_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_DRAM1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_dram2_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_DRAM2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_dram3_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_DRAM3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_fifo_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_FIFO_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_iram0_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_IRAM0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_iram1_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_IRAM1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_iram2_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_IRAM2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_iram3_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_IRAM3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_iram4_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_IRAM4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_iram5_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_IRAM5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_iram6_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_IRAM6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_iram7_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_IRAM7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_trace_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_TRACE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_dram0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_dram1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_dram2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_dram3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_iram0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_iram1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_iram2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_iram3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_iram4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_iram5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_iram6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_iram7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_trace_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_dram0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_dram1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_dram2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_dram3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_fifo_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_iram0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_iram1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_iram2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_iram3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_iram4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_iram5_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_iram6_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_iram7_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_trace_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_dram0_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_dram1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_dram2_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_dram3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_fifo_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_iram0_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_iram1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_iram2_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_iram3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_iram4_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_iram5_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_iram6_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_iram7_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_trace_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_dram0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_dram1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_dram2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_dram3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_fifo_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_iram0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_iram1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_iram2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_iram3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_iram4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_iram5_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_iram6_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_iram7_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_trace_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_dram0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_dram1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_dram2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_dram3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_fifo_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_iram0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_iram1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_iram2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_iram3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_iram4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_iram5_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_iram6_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_iram7_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_trace_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fw_status_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_fw_version_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_iramh_pwr_mgmt_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_iraml_pwr_mgmt_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_nmi_icu_mux_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_tb_reg0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_tb_reg1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_tb_reg2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_tb_reg3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_tb_reg4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_tie_queue_pwr_mgmt_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_cpu_pm_cfg_tram_pwr_mgmt_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_acc_clr_en_attr == SERDES_SHIM_DSP_L0_CFG_ACC_CLR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_acc_clr_rst_attr == SERDES_SHIM_DSP_L0_CFG_ACC_CLR_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_agc_acc_clr_attr == SERDES_SHIM_DSP_L0_CFG_AGC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_agc_clr_en_attr == SERDES_SHIM_DSP_L0_CFG_AGC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_agc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_agc_coarse_det_en_attr == SERDES_SHIM_DSP_L0_CFG_AGC_COARSE_DET_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_agc_coarse_det_pol_attr == SERDES_SHIM_DSP_L0_CFG_AGC_COARSE_DET_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_agc_d_sign_attr == SERDES_SHIM_DSP_L0_CFG_AGC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_agc_en_attr == SERDES_SHIM_DSP_L0_CFG_AGC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_agc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_agc_event_sign_attr == SERDES_SHIM_DSP_L0_CFG_AGC_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_agc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_agc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_agc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_agc_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_bb_stable_attr == SERDES_SHIM_DSP_L0_CFG_BB_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ctle_hf_stable_attr == SERDES_SHIM_DSP_L0_CFG_CTLE_HF_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_d_dly_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_data_sel_mux_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_data_width_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe10_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe11_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe12_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe13_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe14_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe15_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe16_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe1_clr_en_attr == SERDES_SHIM_DSP_L0_CFG_DFE1_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe1_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe1_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe1_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe2_16_clr_en_attr == SERDES_SHIM_DSP_L0_CFG_DFE2_16_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe2_16_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe2_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe4_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe5_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe6_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe7_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe8_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe9_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_0_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_10_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_11_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_12_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_13_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_14_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_15_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_1_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_2_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_3_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_4_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_5_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_6_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_7_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_8_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_9_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_all_taps_en_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_ALL_TAPS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_0_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_10_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_11_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_12_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_13_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_14_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_15_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_1_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_2_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_3_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_4_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_5_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_6_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_7_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_8_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_9_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_common_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_common_th_en_attr == SERDES_SHIM_DSP_L0_CFG_DFE_COMMON_TH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_d_sign_attr == SERDES_SHIM_DSP_L0_CFG_DFE_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_event_sign_attr == SERDES_SHIM_DSP_L0_CFG_DFE_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_tap10_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_tap11_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_tap12_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_tap13_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_tap14_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_tap15_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_tap16_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_tap1_sel_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dfe_tap9_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dsp_bit_swz_attr == SERDES_SHIM_DSP_L0_CFG_DSP_BIT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dsp_d_swz_attr == SERDES_SHIM_DSP_L0_CFG_DSP_D_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dsp_en_attr == SERDES_SHIM_DSP_L0_CFG_DSP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dsp_inner_d_swz_attr == SERDES_SHIM_DSP_L0_CFG_DSP_INNER_D_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dsp_inner_m_swz_attr == SERDES_SHIM_DSP_L0_CFG_DSP_INNER_M_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dsp_latch_dis_attr == SERDES_SHIM_DSP_L0_CFG_DSP_LATCH_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dsp_m_swz_attr == SERDES_SHIM_DSP_L0_CFG_DSP_M_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_dsp_sticky_clr_attr == SERDES_SHIM_DSP_L0_CFG_DSP_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_e_dly_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ehm_acc_clr_attr == SERDES_SHIM_DSP_L0_CFG_EHM_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ehm_event_rate_lsb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ehm_event_rate_msb_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ehm_event_sign_attr == SERDES_SHIM_DSP_L0_CFG_EHM_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ehm_sym1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ehm_sym_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ehm_tap_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ehm_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_en_duration_cnt_trig_attr == SERDES_SHIM_DSP_L0_CFG_EN_DURATION_CNT_TRIG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_en_duration_val_attr == 16'd625
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_err_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_err_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_error_counter_clr_attr == SERDES_SHIM_DSP_L0_CFG_ERROR_COUNTER_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_error_counter_enable_attr == SERDES_SHIM_DSP_L0_CFG_ERROR_COUNTER_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_error_counter_even_odd_select_attr == SERDES_SHIM_DSP_L0_CFG_ERROR_COUNTER_EVEN_ODD_SELECT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_error_counter_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_error_counter_resetb_attr == SERDES_SHIM_DSP_L0_CFG_ERROR_COUNTER_RESETB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_error_sel_mux_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_fine_attr == SERDES_SHIM_DSP_L0_CFG_FINE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_acc_clr1_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_acc_clr2_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_acc_clr3_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_acc_clr4_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_acc_clr5_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_acc_clr6_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_acc_clr7_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_acc_clr8_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_en_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_gps_tap32_sel_attr == SERDES_SHIM_DSP_L0_CFG_GPS_TAP32_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_gps_tap64_sel_attr == SERDES_SHIM_DSP_L0_CFG_GPS_TAP64_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ingress_dsp_disable_chkn_bit_attr == SERDES_SHIM_DSP_L0_CFG_INGRESS_DSP_DISABLE_CHKN_BIT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_io_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_joint_dfe_en_attr == SERDES_SHIM_DSP_L0_CFG_JOINT_DFE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_acc_clr_attr == SERDES_SHIM_DSP_L0_CFG_OFC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_clr_en_attr == SERDES_SHIM_DSP_L0_CFG_OFC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_cnt_offset_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_d_sign_attr == SERDES_SHIM_DSP_L0_CFG_OFC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_en_attr == SERDES_SHIM_DSP_L0_CFG_OFC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_event_sign_attr == SERDES_SHIM_DSP_L0_CFG_OFC_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_acc_clr1_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_acc_clr2_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_acc_clr3_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_acc_clr4_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_acc_clr5_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_acc_clr6_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_acc_clr7_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_acc_clr8_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_en_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_acc_clr1_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_acc_clr2_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_acc_clr3_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_acc_clr4_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_acc_clr5_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_acc_clr6_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_acc_clr7_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_acc_clr8_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_en_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_lsb_inv_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_LSB_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_lsb_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_ofc_th_attr == 20'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_pam4_bit_flip_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_pam4_gray_enable_attr == SERDES_SHIM_DSP_L0_CFG_PAM4_GRAY_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_pam_4_en_attr == SERDES_SHIM_DSP_L0_CFG_PAM_4_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_phase_cnt_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_phase_mask0_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_phase_mask1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_phase_mask2_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_phase_mask3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_phase_num_mask_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_pol_invert_attr == SERDES_SHIM_DSP_L0_CFG_POL_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_power_save_en_attr == SERDES_SHIM_DSP_L0_CFG_POWER_SAVE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_regs2visa_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_regs2visa_en_attr == SERDES_SHIM_DSP_L0_CFG_REGS2VISA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_res_isi_mes_en_attr == SERDES_SHIM_DSP_L0_CFG_RES_ISI_MES_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_snr_div_facror_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_snr_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_snr_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_snr_meter_en_attr == SERDES_SHIM_DSP_L0_CFG_SNR_METER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_snr_smooth_bw_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_0_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_10_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_11_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_12_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_13_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_14_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_15_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_16_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_17_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_18_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_1_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_2_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_3_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_4_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_5_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_6_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_7_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_8_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_9_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_swap_bot_en_attr == SERDES_SHIM_DSP_L0_CFG_SWAP_BOT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_swap_top_en_attr == SERDES_SHIM_DSP_L0_CFG_SWAP_TOP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_timeout_counter_value_attr == 17'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_vga_acc_clr_attr == SERDES_SHIM_DSP_L0_CFG_VGA_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_vga_clr_en_attr == SERDES_SHIM_DSP_L0_CFG_VGA_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_vga_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_vga_en_attr == SERDES_SHIM_DSP_L0_CFG_VGA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_vga_range_detect_comp_const_h_attr == 7'd126
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_vga_range_detect_comp_const_l_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_vga_range_detect_sub_const_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_vga_shift_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_vga_sticky_clr_attr == SERDES_SHIM_DSP_L0_CFG_VGA_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_vga_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_vref_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_x3_acc_clr_attr == SERDES_SHIM_DSP_L0_CFG_X3_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_x3_en_attr == SERDES_SHIM_DSP_L0_CFG_X3_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_x3_sticky_clr_attr == SERDES_SHIM_DSP_L0_CFG_X3_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l0_cfg_x3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_acc_clr_en_attr == SERDES_SHIM_DSP_L1_CFG_ACC_CLR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_acc_clr_rst_attr == SERDES_SHIM_DSP_L1_CFG_ACC_CLR_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_agc_acc_clr_attr == SERDES_SHIM_DSP_L1_CFG_AGC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_agc_clr_en_attr == SERDES_SHIM_DSP_L1_CFG_AGC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_agc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_agc_coarse_det_en_attr == SERDES_SHIM_DSP_L1_CFG_AGC_COARSE_DET_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_agc_coarse_det_pol_attr == SERDES_SHIM_DSP_L1_CFG_AGC_COARSE_DET_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_agc_d_sign_attr == SERDES_SHIM_DSP_L1_CFG_AGC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_agc_en_attr == SERDES_SHIM_DSP_L1_CFG_AGC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_agc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_agc_event_sign_attr == SERDES_SHIM_DSP_L1_CFG_AGC_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_agc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_agc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_agc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_agc_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_bb_stable_attr == SERDES_SHIM_DSP_L1_CFG_BB_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ctle_hf_stable_attr == SERDES_SHIM_DSP_L1_CFG_CTLE_HF_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_d_dly_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_data_sel_mux_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_data_width_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe10_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe11_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe12_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe13_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe14_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe15_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe16_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe1_clr_en_attr == SERDES_SHIM_DSP_L1_CFG_DFE1_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe1_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe1_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe1_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe2_16_clr_en_attr == SERDES_SHIM_DSP_L1_CFG_DFE2_16_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe2_16_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe2_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe4_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe5_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe6_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe7_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe8_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe9_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_0_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_10_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_11_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_12_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_13_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_14_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_15_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_1_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_2_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_3_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_4_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_5_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_6_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_7_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_8_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_9_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_all_taps_en_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_ALL_TAPS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_0_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_10_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_11_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_12_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_13_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_14_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_15_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_1_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_2_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_3_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_4_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_5_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_6_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_7_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_8_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_9_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_common_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_common_th_en_attr == SERDES_SHIM_DSP_L1_CFG_DFE_COMMON_TH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_d_sign_attr == SERDES_SHIM_DSP_L1_CFG_DFE_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_event_sign_attr == SERDES_SHIM_DSP_L1_CFG_DFE_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_tap10_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_tap11_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_tap12_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_tap13_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_tap14_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_tap15_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_tap16_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_tap1_sel_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dfe_tap9_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dsp_bit_swz_attr == SERDES_SHIM_DSP_L1_CFG_DSP_BIT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dsp_d_swz_attr == SERDES_SHIM_DSP_L1_CFG_DSP_D_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dsp_en_attr == SERDES_SHIM_DSP_L1_CFG_DSP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dsp_inner_d_swz_attr == SERDES_SHIM_DSP_L1_CFG_DSP_INNER_D_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dsp_inner_m_swz_attr == SERDES_SHIM_DSP_L1_CFG_DSP_INNER_M_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dsp_latch_dis_attr == SERDES_SHIM_DSP_L1_CFG_DSP_LATCH_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dsp_m_swz_attr == SERDES_SHIM_DSP_L1_CFG_DSP_M_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_dsp_sticky_clr_attr == SERDES_SHIM_DSP_L1_CFG_DSP_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_e_dly_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ehm_acc_clr_attr == SERDES_SHIM_DSP_L1_CFG_EHM_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ehm_event_rate_lsb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ehm_event_rate_msb_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ehm_event_sign_attr == SERDES_SHIM_DSP_L1_CFG_EHM_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ehm_sym1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ehm_sym_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ehm_tap_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ehm_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_en_duration_cnt_trig_attr == SERDES_SHIM_DSP_L1_CFG_EN_DURATION_CNT_TRIG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_en_duration_val_attr == 16'd625
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_err_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_err_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_error_counter_clr_attr == SERDES_SHIM_DSP_L1_CFG_ERROR_COUNTER_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_error_counter_enable_attr == SERDES_SHIM_DSP_L1_CFG_ERROR_COUNTER_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_error_counter_even_odd_select_attr == SERDES_SHIM_DSP_L1_CFG_ERROR_COUNTER_EVEN_ODD_SELECT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_error_counter_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_error_counter_resetb_attr == SERDES_SHIM_DSP_L1_CFG_ERROR_COUNTER_RESETB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_error_sel_mux_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_fine_attr == SERDES_SHIM_DSP_L1_CFG_FINE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_acc_clr1_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_acc_clr2_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_acc_clr3_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_acc_clr4_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_acc_clr5_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_acc_clr6_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_acc_clr7_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_acc_clr8_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_en_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_gps_tap32_sel_attr == SERDES_SHIM_DSP_L1_CFG_GPS_TAP32_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_gps_tap64_sel_attr == SERDES_SHIM_DSP_L1_CFG_GPS_TAP64_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ingress_dsp_disable_chkn_bit_attr == SERDES_SHIM_DSP_L1_CFG_INGRESS_DSP_DISABLE_CHKN_BIT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_io_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_joint_dfe_en_attr == SERDES_SHIM_DSP_L1_CFG_JOINT_DFE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_acc_clr_attr == SERDES_SHIM_DSP_L1_CFG_OFC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_clr_en_attr == SERDES_SHIM_DSP_L1_CFG_OFC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_cnt_offset_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_d_sign_attr == SERDES_SHIM_DSP_L1_CFG_OFC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_en_attr == SERDES_SHIM_DSP_L1_CFG_OFC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_event_sign_attr == SERDES_SHIM_DSP_L1_CFG_OFC_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_acc_clr1_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_acc_clr2_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_acc_clr3_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_acc_clr4_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_acc_clr5_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_acc_clr6_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_acc_clr7_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_acc_clr8_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_en_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_acc_clr1_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_acc_clr2_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_acc_clr3_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_acc_clr4_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_acc_clr5_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_acc_clr6_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_acc_clr7_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_acc_clr8_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_en_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_lsb_inv_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_LSB_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_lsb_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_ofc_th_attr == 20'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_pam4_bit_flip_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_pam4_gray_enable_attr == SERDES_SHIM_DSP_L1_CFG_PAM4_GRAY_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_pam_4_en_attr == SERDES_SHIM_DSP_L1_CFG_PAM_4_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_phase_cnt_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_phase_mask0_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_phase_mask1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_phase_mask2_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_phase_mask3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_phase_num_mask_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_pol_invert_attr == SERDES_SHIM_DSP_L1_CFG_POL_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_power_save_en_attr == SERDES_SHIM_DSP_L1_CFG_POWER_SAVE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_regs2visa_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_regs2visa_en_attr == SERDES_SHIM_DSP_L1_CFG_REGS2VISA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_res_isi_mes_en_attr == SERDES_SHIM_DSP_L1_CFG_RES_ISI_MES_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_snr_div_facror_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_snr_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_snr_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_snr_meter_en_attr == SERDES_SHIM_DSP_L1_CFG_SNR_METER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_snr_smooth_bw_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_0_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_10_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_11_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_12_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_13_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_14_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_15_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_16_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_17_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_18_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_1_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_2_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_3_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_4_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_5_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_6_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_7_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_8_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_9_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_swap_bot_en_attr == SERDES_SHIM_DSP_L1_CFG_SWAP_BOT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_swap_top_en_attr == SERDES_SHIM_DSP_L1_CFG_SWAP_TOP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_timeout_counter_value_attr == 17'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_vga_acc_clr_attr == SERDES_SHIM_DSP_L1_CFG_VGA_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_vga_clr_en_attr == SERDES_SHIM_DSP_L1_CFG_VGA_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_vga_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_vga_en_attr == SERDES_SHIM_DSP_L1_CFG_VGA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_vga_range_detect_comp_const_h_attr == 7'd126
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_vga_range_detect_comp_const_l_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_vga_range_detect_sub_const_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_vga_shift_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_vga_sticky_clr_attr == SERDES_SHIM_DSP_L1_CFG_VGA_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_vga_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_vref_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_x3_acc_clr_attr == SERDES_SHIM_DSP_L1_CFG_X3_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_x3_en_attr == SERDES_SHIM_DSP_L1_CFG_X3_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_x3_sticky_clr_attr == SERDES_SHIM_DSP_L1_CFG_X3_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l1_cfg_x3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_acc_clr_en_attr == SERDES_SHIM_DSP_L2_CFG_ACC_CLR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_acc_clr_rst_attr == SERDES_SHIM_DSP_L2_CFG_ACC_CLR_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_agc_acc_clr_attr == SERDES_SHIM_DSP_L2_CFG_AGC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_agc_clr_en_attr == SERDES_SHIM_DSP_L2_CFG_AGC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_agc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_agc_coarse_det_en_attr == SERDES_SHIM_DSP_L2_CFG_AGC_COARSE_DET_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_agc_coarse_det_pol_attr == SERDES_SHIM_DSP_L2_CFG_AGC_COARSE_DET_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_agc_d_sign_attr == SERDES_SHIM_DSP_L2_CFG_AGC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_agc_en_attr == SERDES_SHIM_DSP_L2_CFG_AGC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_agc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_agc_event_sign_attr == SERDES_SHIM_DSP_L2_CFG_AGC_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_agc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_agc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_agc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_agc_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_bb_stable_attr == SERDES_SHIM_DSP_L2_CFG_BB_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ctle_hf_stable_attr == SERDES_SHIM_DSP_L2_CFG_CTLE_HF_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_d_dly_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_data_sel_mux_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_data_width_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe10_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe11_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe12_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe13_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe14_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe15_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe16_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe1_clr_en_attr == SERDES_SHIM_DSP_L2_CFG_DFE1_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe1_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe1_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe1_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe2_16_clr_en_attr == SERDES_SHIM_DSP_L2_CFG_DFE2_16_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe2_16_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe2_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe4_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe5_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe6_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe7_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe8_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe9_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_0_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_10_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_11_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_12_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_13_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_14_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_15_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_1_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_2_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_3_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_4_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_5_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_6_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_7_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_8_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_9_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_all_taps_en_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_ALL_TAPS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_0_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_10_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_11_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_12_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_13_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_14_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_15_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_1_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_2_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_3_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_4_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_5_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_6_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_7_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_8_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_9_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_common_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_common_th_en_attr == SERDES_SHIM_DSP_L2_CFG_DFE_COMMON_TH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_d_sign_attr == SERDES_SHIM_DSP_L2_CFG_DFE_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_event_sign_attr == SERDES_SHIM_DSP_L2_CFG_DFE_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_tap10_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_tap11_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_tap12_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_tap13_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_tap14_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_tap15_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_tap16_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_tap1_sel_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dfe_tap9_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dsp_bit_swz_attr == SERDES_SHIM_DSP_L2_CFG_DSP_BIT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dsp_d_swz_attr == SERDES_SHIM_DSP_L2_CFG_DSP_D_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dsp_en_attr == SERDES_SHIM_DSP_L2_CFG_DSP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dsp_inner_d_swz_attr == SERDES_SHIM_DSP_L2_CFG_DSP_INNER_D_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dsp_inner_m_swz_attr == SERDES_SHIM_DSP_L2_CFG_DSP_INNER_M_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dsp_latch_dis_attr == SERDES_SHIM_DSP_L2_CFG_DSP_LATCH_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dsp_m_swz_attr == SERDES_SHIM_DSP_L2_CFG_DSP_M_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_dsp_sticky_clr_attr == SERDES_SHIM_DSP_L2_CFG_DSP_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_e_dly_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ehm_acc_clr_attr == SERDES_SHIM_DSP_L2_CFG_EHM_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ehm_event_rate_lsb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ehm_event_rate_msb_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ehm_event_sign_attr == SERDES_SHIM_DSP_L2_CFG_EHM_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ehm_sym1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ehm_sym_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ehm_tap_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ehm_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_en_duration_cnt_trig_attr == SERDES_SHIM_DSP_L2_CFG_EN_DURATION_CNT_TRIG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_en_duration_val_attr == 16'd625
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_err_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_err_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_error_counter_clr_attr == SERDES_SHIM_DSP_L2_CFG_ERROR_COUNTER_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_error_counter_enable_attr == SERDES_SHIM_DSP_L2_CFG_ERROR_COUNTER_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_error_counter_even_odd_select_attr == SERDES_SHIM_DSP_L2_CFG_ERROR_COUNTER_EVEN_ODD_SELECT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_error_counter_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_error_counter_resetb_attr == SERDES_SHIM_DSP_L2_CFG_ERROR_COUNTER_RESETB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_error_sel_mux_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_fine_attr == SERDES_SHIM_DSP_L2_CFG_FINE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_acc_clr1_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_acc_clr2_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_acc_clr3_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_acc_clr4_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_acc_clr5_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_acc_clr6_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_acc_clr7_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_acc_clr8_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_en_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_gps_tap32_sel_attr == SERDES_SHIM_DSP_L2_CFG_GPS_TAP32_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_gps_tap64_sel_attr == SERDES_SHIM_DSP_L2_CFG_GPS_TAP64_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ingress_dsp_disable_chkn_bit_attr == SERDES_SHIM_DSP_L2_CFG_INGRESS_DSP_DISABLE_CHKN_BIT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_io_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_joint_dfe_en_attr == SERDES_SHIM_DSP_L2_CFG_JOINT_DFE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_acc_clr_attr == SERDES_SHIM_DSP_L2_CFG_OFC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_clr_en_attr == SERDES_SHIM_DSP_L2_CFG_OFC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_cnt_offset_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_d_sign_attr == SERDES_SHIM_DSP_L2_CFG_OFC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_en_attr == SERDES_SHIM_DSP_L2_CFG_OFC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_event_sign_attr == SERDES_SHIM_DSP_L2_CFG_OFC_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_acc_clr1_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_acc_clr2_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_acc_clr3_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_acc_clr4_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_acc_clr5_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_acc_clr6_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_acc_clr7_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_acc_clr8_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_en_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_acc_clr1_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_acc_clr2_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_acc_clr3_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_acc_clr4_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_acc_clr5_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_acc_clr6_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_acc_clr7_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_acc_clr8_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_en_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_lsb_inv_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_LSB_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_lsb_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_ofc_th_attr == 20'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_pam4_bit_flip_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_pam4_gray_enable_attr == SERDES_SHIM_DSP_L2_CFG_PAM4_GRAY_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_pam_4_en_attr == SERDES_SHIM_DSP_L2_CFG_PAM_4_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_phase_cnt_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_phase_mask0_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_phase_mask1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_phase_mask2_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_phase_mask3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_phase_num_mask_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_pol_invert_attr == SERDES_SHIM_DSP_L2_CFG_POL_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_power_save_en_attr == SERDES_SHIM_DSP_L2_CFG_POWER_SAVE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_regs2visa_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_regs2visa_en_attr == SERDES_SHIM_DSP_L2_CFG_REGS2VISA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_res_isi_mes_en_attr == SERDES_SHIM_DSP_L2_CFG_RES_ISI_MES_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_snr_div_facror_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_snr_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_snr_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_snr_meter_en_attr == SERDES_SHIM_DSP_L2_CFG_SNR_METER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_snr_smooth_bw_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_0_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_10_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_11_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_12_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_13_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_14_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_15_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_16_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_17_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_18_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_1_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_2_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_3_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_4_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_5_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_6_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_7_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_8_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_9_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_swap_bot_en_attr == SERDES_SHIM_DSP_L2_CFG_SWAP_BOT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_swap_top_en_attr == SERDES_SHIM_DSP_L2_CFG_SWAP_TOP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_timeout_counter_value_attr == 17'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_vga_acc_clr_attr == SERDES_SHIM_DSP_L2_CFG_VGA_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_vga_clr_en_attr == SERDES_SHIM_DSP_L2_CFG_VGA_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_vga_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_vga_en_attr == SERDES_SHIM_DSP_L2_CFG_VGA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_vga_range_detect_comp_const_h_attr == 7'd126
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_vga_range_detect_comp_const_l_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_vga_range_detect_sub_const_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_vga_shift_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_vga_sticky_clr_attr == SERDES_SHIM_DSP_L2_CFG_VGA_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_vga_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_vref_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_x3_acc_clr_attr == SERDES_SHIM_DSP_L2_CFG_X3_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_x3_en_attr == SERDES_SHIM_DSP_L2_CFG_X3_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_x3_sticky_clr_attr == SERDES_SHIM_DSP_L2_CFG_X3_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l2_cfg_x3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_acc_clr_en_attr == SERDES_SHIM_DSP_L3_CFG_ACC_CLR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_acc_clr_rst_attr == SERDES_SHIM_DSP_L3_CFG_ACC_CLR_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_agc_acc_clr_attr == SERDES_SHIM_DSP_L3_CFG_AGC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_agc_clr_en_attr == SERDES_SHIM_DSP_L3_CFG_AGC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_agc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_agc_coarse_det_en_attr == SERDES_SHIM_DSP_L3_CFG_AGC_COARSE_DET_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_agc_coarse_det_pol_attr == SERDES_SHIM_DSP_L3_CFG_AGC_COARSE_DET_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_agc_d_sign_attr == SERDES_SHIM_DSP_L3_CFG_AGC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_agc_en_attr == SERDES_SHIM_DSP_L3_CFG_AGC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_agc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_agc_event_sign_attr == SERDES_SHIM_DSP_L3_CFG_AGC_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_agc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_agc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_agc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_agc_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_bb_stable_attr == SERDES_SHIM_DSP_L3_CFG_BB_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ctle_hf_stable_attr == SERDES_SHIM_DSP_L3_CFG_CTLE_HF_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_d_dly_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_data_sel_mux_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_data_width_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe10_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe11_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe12_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe13_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe14_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe15_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe16_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe1_clr_en_attr == SERDES_SHIM_DSP_L3_CFG_DFE1_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe1_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe1_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe1_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe2_16_clr_en_attr == SERDES_SHIM_DSP_L3_CFG_DFE2_16_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe2_16_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe2_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe4_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe5_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe6_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe7_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe8_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe9_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_0_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_10_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_11_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_12_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_13_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_14_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_15_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_1_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_2_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_3_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_4_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_5_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_6_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_7_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_8_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_9_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_all_taps_en_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_ALL_TAPS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_0_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_10_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_11_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_12_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_13_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_14_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_15_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_1_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_2_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_3_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_4_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_5_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_6_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_7_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_8_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_9_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_common_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_common_th_en_attr == SERDES_SHIM_DSP_L3_CFG_DFE_COMMON_TH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_d_sign_attr == SERDES_SHIM_DSP_L3_CFG_DFE_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_event_sign_attr == SERDES_SHIM_DSP_L3_CFG_DFE_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_tap10_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_tap11_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_tap12_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_tap13_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_tap14_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_tap15_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_tap16_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_tap1_sel_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dfe_tap9_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dsp_bit_swz_attr == SERDES_SHIM_DSP_L3_CFG_DSP_BIT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dsp_d_swz_attr == SERDES_SHIM_DSP_L3_CFG_DSP_D_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dsp_en_attr == SERDES_SHIM_DSP_L3_CFG_DSP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dsp_inner_d_swz_attr == SERDES_SHIM_DSP_L3_CFG_DSP_INNER_D_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dsp_inner_m_swz_attr == SERDES_SHIM_DSP_L3_CFG_DSP_INNER_M_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dsp_latch_dis_attr == SERDES_SHIM_DSP_L3_CFG_DSP_LATCH_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dsp_m_swz_attr == SERDES_SHIM_DSP_L3_CFG_DSP_M_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_dsp_sticky_clr_attr == SERDES_SHIM_DSP_L3_CFG_DSP_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_e_dly_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ehm_acc_clr_attr == SERDES_SHIM_DSP_L3_CFG_EHM_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ehm_event_rate_lsb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ehm_event_rate_msb_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ehm_event_sign_attr == SERDES_SHIM_DSP_L3_CFG_EHM_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ehm_sym1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ehm_sym_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ehm_tap_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ehm_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_en_duration_cnt_trig_attr == SERDES_SHIM_DSP_L3_CFG_EN_DURATION_CNT_TRIG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_en_duration_val_attr == 16'd625
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_err_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_err_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_error_counter_clr_attr == SERDES_SHIM_DSP_L3_CFG_ERROR_COUNTER_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_error_counter_enable_attr == SERDES_SHIM_DSP_L3_CFG_ERROR_COUNTER_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_error_counter_even_odd_select_attr == SERDES_SHIM_DSP_L3_CFG_ERROR_COUNTER_EVEN_ODD_SELECT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_error_counter_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_error_counter_resetb_attr == SERDES_SHIM_DSP_L3_CFG_ERROR_COUNTER_RESETB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_error_sel_mux_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_fine_attr == SERDES_SHIM_DSP_L3_CFG_FINE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_acc_clr1_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_acc_clr2_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_acc_clr3_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_acc_clr4_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_acc_clr5_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_acc_clr6_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_acc_clr7_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_acc_clr8_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_en_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_gps_tap32_sel_attr == SERDES_SHIM_DSP_L3_CFG_GPS_TAP32_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_gps_tap64_sel_attr == SERDES_SHIM_DSP_L3_CFG_GPS_TAP64_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ingress_dsp_disable_chkn_bit_attr == SERDES_SHIM_DSP_L3_CFG_INGRESS_DSP_DISABLE_CHKN_BIT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_io_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_joint_dfe_en_attr == SERDES_SHIM_DSP_L3_CFG_JOINT_DFE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_acc_clr_attr == SERDES_SHIM_DSP_L3_CFG_OFC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_clr_en_attr == SERDES_SHIM_DSP_L3_CFG_OFC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_cnt_offset_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_d_sign_attr == SERDES_SHIM_DSP_L3_CFG_OFC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_en_attr == SERDES_SHIM_DSP_L3_CFG_OFC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_event_sign_attr == SERDES_SHIM_DSP_L3_CFG_OFC_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_acc_clr1_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_acc_clr2_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_acc_clr3_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_acc_clr4_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_acc_clr5_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_acc_clr6_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_acc_clr7_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_acc_clr8_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_en_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_acc_clr1_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_acc_clr2_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_acc_clr3_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_acc_clr4_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_acc_clr5_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_acc_clr6_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_acc_clr7_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_acc_clr8_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_en_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_lsb_inv_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_LSB_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_lsb_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_ofc_th_attr == 20'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_pam4_bit_flip_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_pam4_gray_enable_attr == SERDES_SHIM_DSP_L3_CFG_PAM4_GRAY_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_pam_4_en_attr == SERDES_SHIM_DSP_L3_CFG_PAM_4_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_phase_cnt_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_phase_mask0_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_phase_mask1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_phase_mask2_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_phase_mask3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_phase_num_mask_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_pol_invert_attr == SERDES_SHIM_DSP_L3_CFG_POL_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_power_save_en_attr == SERDES_SHIM_DSP_L3_CFG_POWER_SAVE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_regs2visa_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_regs2visa_en_attr == SERDES_SHIM_DSP_L3_CFG_REGS2VISA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_res_isi_mes_en_attr == SERDES_SHIM_DSP_L3_CFG_RES_ISI_MES_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_snr_div_facror_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_snr_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_snr_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_snr_meter_en_attr == SERDES_SHIM_DSP_L3_CFG_SNR_METER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_snr_smooth_bw_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_0_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_10_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_11_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_12_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_13_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_14_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_15_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_16_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_17_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_18_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_1_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_2_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_3_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_4_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_5_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_6_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_7_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_8_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_9_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_swap_bot_en_attr == SERDES_SHIM_DSP_L3_CFG_SWAP_BOT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_swap_top_en_attr == SERDES_SHIM_DSP_L3_CFG_SWAP_TOP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_timeout_counter_value_attr == 17'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_vga_acc_clr_attr == SERDES_SHIM_DSP_L3_CFG_VGA_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_vga_clr_en_attr == SERDES_SHIM_DSP_L3_CFG_VGA_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_vga_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_vga_en_attr == SERDES_SHIM_DSP_L3_CFG_VGA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_vga_range_detect_comp_const_h_attr == 7'd126
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_vga_range_detect_comp_const_l_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_vga_range_detect_sub_const_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_vga_shift_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_vga_sticky_clr_attr == SERDES_SHIM_DSP_L3_CFG_VGA_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_vga_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_vref_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_x3_acc_clr_attr == SERDES_SHIM_DSP_L3_CFG_X3_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_x3_en_attr == SERDES_SHIM_DSP_L3_CFG_X3_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_x3_sticky_clr_attr == SERDES_SHIM_DSP_L3_CFG_X3_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_dsp_l3_cfg_x3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_cfg_prbs13_seed_2_attr == 13'd7571
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_cfg_prbs13_seed_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_cfg_tfl_prbs11_en_attr == SERDES_SHIM_TFL_L0_CFG_CFG_TFL_PRBS11_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_cl136_ctrl_field_11_10_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_cl136_ctrl_field_13_12_init_cond_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_cl136_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_cl136_ctrl_field_1_0_coeff_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_cl136_ctrl_field_4_2_coeff_select_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_cl136_ctrl_field_7_5_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_cl136_ctrl_field_9_8_mod_precode_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_cl136_frame_cycle_to_lock_attr == 10'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_cl136_prbs_encoder_select_even_attr == SERDES_SHIM_TFL_L0_CFG_CL136_PRBS_ENCODER_SELECT_EVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_cl136_precoder_out_swz_attr == SERDES_SHIM_TFL_L0_CFG_CL136_PRECODER_OUT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_cl136_precoder_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_cl136_stts_field_11_10_mod_precode_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_cl136_stts_field_14_12_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_cl136_stts_field_15_rx_ready_attr == SERDES_SHIM_TFL_L0_CFG_CL136_STTS_FIELD_15_RX_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_cl136_stts_field_2_0_coeff_stts_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_cl136_stts_field_5_3_coeff_sel_echo_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_cl136_stts_field_6_rsvd_attr == SERDES_SHIM_TFL_L0_CFG_CL136_STTS_FIELD_6_RSVD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_cl136_stts_field_7_parity_attr == SERDES_SHIM_TFL_L0_CFG_CL136_STTS_FIELD_7_PARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_cl136_stts_field_8_init_cond_stts_attr == SERDES_SHIM_TFL_L0_CFG_CL136_STTS_FIELD_8_INIT_COND_STTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_cl136_stts_field_9_rx_frame_lock_attr == SERDES_SHIM_TFL_L0_CFG_CL136_STTS_FIELD_9_RX_FRAME_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_cl72_ctrl_field_11_6_rsvd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_cl72_ctrl_field_12_initialize_attr == SERDES_SHIM_TFL_L0_CFG_CL72_CTRL_FIELD_12_INITIALIZE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_cl72_ctrl_field_13_preset_attr == SERDES_SHIM_TFL_L0_CFG_CL72_CTRL_FIELD_13_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_cl72_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_cl72_ctrl_field_1_0_coef_m1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_cl72_ctrl_field_3_2_coef_0_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_cl72_ctrl_field_5_4_coef_p1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_cl72_frame_cycle_to_lock_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_cl72_stts_field_14_6_rsvd_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_cl72_stts_field_15_rcv_ready_attr == SERDES_SHIM_TFL_L0_CFG_CL72_STTS_FIELD_15_RCV_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_cl72_stts_field_1_0_coef_m1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_cl72_stts_field_3_2_coef_0_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_cl72_stts_field_5_4_coef_p1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_frame_boundary_early_attr == SERDES_SHIM_TFL_L0_CFG_FRAME_BOUNDARY_EARLY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_gb_128_80_en_attr == SERDES_SHIM_TFL_L0_CFG_GB_128_80_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_ignore_tfl_en_to_avoid_cut_frame_attr == SERDES_SHIM_TFL_L0_CFG_IGNORE_TFL_EN_TO_AVOID_CUT_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_polynomial_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_prbs11_seed_2_attr == 11'd977
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_prbs11_seed_attr == 11'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_ber_count_snap_lock_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL136_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_ber_counter_clear_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL136_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_clear_one_marker_seen_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL136_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL136_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL136_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL136_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_pam4_modulation_select_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_prbs_ber_en_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL136_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_prbs_seed_force_en_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL136_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_prbs_seed_force_val_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_ber_count_snap_lock_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL72_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_ber_counter_clear_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL72_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_clear_one_marker_seen_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL72_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL72_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL72_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL72_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_prbs_ber_en_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL72_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_prbs_seed_force_en_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL72_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_prbs_seed_force_val_attr == 13'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_gb_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_rx_sync_pulse_attr == SERDES_SHIM_TFL_L0_CFG_RX_SYNC_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_scrambler_force_init_at_each_frame_attr == SERDES_SHIM_TFL_L0_CFG_SCRAMBLER_FORCE_INIT_AT_EACH_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_send_data_attr == SERDES_SHIM_TFL_L0_CFG_SEND_DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_sync_ctrl_stts_word_pulse_attr == SERDES_SHIM_TFL_L0_CFG_SYNC_CTRL_STTS_WORD_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_tfl_prbs13_en_attr == SERDES_SHIM_TFL_L0_CFG_TFL_PRBS13_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_tfl_pulse_sync_attr == SERDES_SHIM_TFL_L0_CFG_TFL_PULSE_SYNC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_tfl_training_enable_rx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_tfl_training_enable_tx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l0_cfg_tx_gb_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_cfg_prbs13_seed_2_attr == 13'd7571
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_cfg_prbs13_seed_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_cfg_tfl_prbs11_en_attr == SERDES_SHIM_TFL_L1_CFG_CFG_TFL_PRBS11_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_cl136_ctrl_field_11_10_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_cl136_ctrl_field_13_12_init_cond_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_cl136_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_cl136_ctrl_field_1_0_coeff_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_cl136_ctrl_field_4_2_coeff_select_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_cl136_ctrl_field_7_5_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_cl136_ctrl_field_9_8_mod_precode_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_cl136_frame_cycle_to_lock_attr == 10'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_cl136_prbs_encoder_select_even_attr == SERDES_SHIM_TFL_L1_CFG_CL136_PRBS_ENCODER_SELECT_EVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_cl136_precoder_out_swz_attr == SERDES_SHIM_TFL_L1_CFG_CL136_PRECODER_OUT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_cl136_precoder_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_cl136_stts_field_11_10_mod_precode_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_cl136_stts_field_14_12_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_cl136_stts_field_15_rx_ready_attr == SERDES_SHIM_TFL_L1_CFG_CL136_STTS_FIELD_15_RX_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_cl136_stts_field_2_0_coeff_stts_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_cl136_stts_field_5_3_coeff_sel_echo_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_cl136_stts_field_6_rsvd_attr == SERDES_SHIM_TFL_L1_CFG_CL136_STTS_FIELD_6_RSVD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_cl136_stts_field_7_parity_attr == SERDES_SHIM_TFL_L1_CFG_CL136_STTS_FIELD_7_PARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_cl136_stts_field_8_init_cond_stts_attr == SERDES_SHIM_TFL_L1_CFG_CL136_STTS_FIELD_8_INIT_COND_STTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_cl136_stts_field_9_rx_frame_lock_attr == SERDES_SHIM_TFL_L1_CFG_CL136_STTS_FIELD_9_RX_FRAME_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_cl72_ctrl_field_11_6_rsvd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_cl72_ctrl_field_12_initialize_attr == SERDES_SHIM_TFL_L1_CFG_CL72_CTRL_FIELD_12_INITIALIZE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_cl72_ctrl_field_13_preset_attr == SERDES_SHIM_TFL_L1_CFG_CL72_CTRL_FIELD_13_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_cl72_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_cl72_ctrl_field_1_0_coef_m1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_cl72_ctrl_field_3_2_coef_0_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_cl72_ctrl_field_5_4_coef_p1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_cl72_frame_cycle_to_lock_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_cl72_stts_field_14_6_rsvd_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_cl72_stts_field_15_rcv_ready_attr == SERDES_SHIM_TFL_L1_CFG_CL72_STTS_FIELD_15_RCV_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_cl72_stts_field_1_0_coef_m1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_cl72_stts_field_3_2_coef_0_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_cl72_stts_field_5_4_coef_p1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_frame_boundary_early_attr == SERDES_SHIM_TFL_L1_CFG_FRAME_BOUNDARY_EARLY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_gb_128_80_en_attr == SERDES_SHIM_TFL_L1_CFG_GB_128_80_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_ignore_tfl_en_to_avoid_cut_frame_attr == SERDES_SHIM_TFL_L1_CFG_IGNORE_TFL_EN_TO_AVOID_CUT_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_polynomial_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_prbs11_seed_2_attr == 11'd977
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_prbs11_seed_attr == 11'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_ber_count_snap_lock_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL136_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_ber_counter_clear_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL136_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_clear_one_marker_seen_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL136_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL136_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL136_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL136_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_pam4_modulation_select_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_prbs_ber_en_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL136_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_prbs_seed_force_en_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL136_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_prbs_seed_force_val_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_ber_count_snap_lock_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL72_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_ber_counter_clear_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL72_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_clear_one_marker_seen_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL72_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL72_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL72_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL72_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_prbs_ber_en_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL72_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_prbs_seed_force_en_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL72_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_prbs_seed_force_val_attr == 13'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_gb_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_rx_sync_pulse_attr == SERDES_SHIM_TFL_L1_CFG_RX_SYNC_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_scrambler_force_init_at_each_frame_attr == SERDES_SHIM_TFL_L1_CFG_SCRAMBLER_FORCE_INIT_AT_EACH_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_send_data_attr == SERDES_SHIM_TFL_L1_CFG_SEND_DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_sync_ctrl_stts_word_pulse_attr == SERDES_SHIM_TFL_L1_CFG_SYNC_CTRL_STTS_WORD_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_tfl_prbs13_en_attr == SERDES_SHIM_TFL_L1_CFG_TFL_PRBS13_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_tfl_pulse_sync_attr == SERDES_SHIM_TFL_L1_CFG_TFL_PULSE_SYNC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_tfl_training_enable_rx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_tfl_training_enable_tx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l1_cfg_tx_gb_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_cfg_prbs13_seed_2_attr == 13'd7571
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_cfg_prbs13_seed_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_cfg_tfl_prbs11_en_attr == SERDES_SHIM_TFL_L2_CFG_CFG_TFL_PRBS11_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_cl136_ctrl_field_11_10_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_cl136_ctrl_field_13_12_init_cond_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_cl136_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_cl136_ctrl_field_1_0_coeff_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_cl136_ctrl_field_4_2_coeff_select_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_cl136_ctrl_field_7_5_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_cl136_ctrl_field_9_8_mod_precode_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_cl136_frame_cycle_to_lock_attr == 10'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_cl136_prbs_encoder_select_even_attr == SERDES_SHIM_TFL_L2_CFG_CL136_PRBS_ENCODER_SELECT_EVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_cl136_precoder_out_swz_attr == SERDES_SHIM_TFL_L2_CFG_CL136_PRECODER_OUT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_cl136_precoder_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_cl136_stts_field_11_10_mod_precode_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_cl136_stts_field_14_12_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_cl136_stts_field_15_rx_ready_attr == SERDES_SHIM_TFL_L2_CFG_CL136_STTS_FIELD_15_RX_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_cl136_stts_field_2_0_coeff_stts_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_cl136_stts_field_5_3_coeff_sel_echo_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_cl136_stts_field_6_rsvd_attr == SERDES_SHIM_TFL_L2_CFG_CL136_STTS_FIELD_6_RSVD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_cl136_stts_field_7_parity_attr == SERDES_SHIM_TFL_L2_CFG_CL136_STTS_FIELD_7_PARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_cl136_stts_field_8_init_cond_stts_attr == SERDES_SHIM_TFL_L2_CFG_CL136_STTS_FIELD_8_INIT_COND_STTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_cl136_stts_field_9_rx_frame_lock_attr == SERDES_SHIM_TFL_L2_CFG_CL136_STTS_FIELD_9_RX_FRAME_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_cl72_ctrl_field_11_6_rsvd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_cl72_ctrl_field_12_initialize_attr == SERDES_SHIM_TFL_L2_CFG_CL72_CTRL_FIELD_12_INITIALIZE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_cl72_ctrl_field_13_preset_attr == SERDES_SHIM_TFL_L2_CFG_CL72_CTRL_FIELD_13_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_cl72_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_cl72_ctrl_field_1_0_coef_m1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_cl72_ctrl_field_3_2_coef_0_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_cl72_ctrl_field_5_4_coef_p1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_cl72_frame_cycle_to_lock_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_cl72_stts_field_14_6_rsvd_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_cl72_stts_field_15_rcv_ready_attr == SERDES_SHIM_TFL_L2_CFG_CL72_STTS_FIELD_15_RCV_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_cl72_stts_field_1_0_coef_m1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_cl72_stts_field_3_2_coef_0_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_cl72_stts_field_5_4_coef_p1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_frame_boundary_early_attr == SERDES_SHIM_TFL_L2_CFG_FRAME_BOUNDARY_EARLY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_gb_128_80_en_attr == SERDES_SHIM_TFL_L2_CFG_GB_128_80_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_ignore_tfl_en_to_avoid_cut_frame_attr == SERDES_SHIM_TFL_L2_CFG_IGNORE_TFL_EN_TO_AVOID_CUT_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_polynomial_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_prbs11_seed_2_attr == 11'd977
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_prbs11_seed_attr == 11'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_ber_count_snap_lock_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL136_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_ber_counter_clear_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL136_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_clear_one_marker_seen_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL136_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL136_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL136_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL136_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_pam4_modulation_select_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_prbs_ber_en_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL136_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_prbs_seed_force_en_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL136_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_prbs_seed_force_val_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_ber_count_snap_lock_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL72_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_ber_counter_clear_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL72_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_clear_one_marker_seen_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL72_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL72_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL72_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL72_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_prbs_ber_en_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL72_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_prbs_seed_force_en_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL72_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_prbs_seed_force_val_attr == 13'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_gb_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_rx_sync_pulse_attr == SERDES_SHIM_TFL_L2_CFG_RX_SYNC_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_scrambler_force_init_at_each_frame_attr == SERDES_SHIM_TFL_L2_CFG_SCRAMBLER_FORCE_INIT_AT_EACH_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_send_data_attr == SERDES_SHIM_TFL_L2_CFG_SEND_DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_sync_ctrl_stts_word_pulse_attr == SERDES_SHIM_TFL_L2_CFG_SYNC_CTRL_STTS_WORD_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_tfl_prbs13_en_attr == SERDES_SHIM_TFL_L2_CFG_TFL_PRBS13_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_tfl_pulse_sync_attr == SERDES_SHIM_TFL_L2_CFG_TFL_PULSE_SYNC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_tfl_training_enable_rx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_tfl_training_enable_tx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l2_cfg_tx_gb_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_cfg_prbs13_seed_2_attr == 13'd7571
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_cfg_prbs13_seed_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_cfg_tfl_prbs11_en_attr == SERDES_SHIM_TFL_L3_CFG_CFG_TFL_PRBS11_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_cl136_ctrl_field_11_10_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_cl136_ctrl_field_13_12_init_cond_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_cl136_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_cl136_ctrl_field_1_0_coeff_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_cl136_ctrl_field_4_2_coeff_select_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_cl136_ctrl_field_7_5_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_cl136_ctrl_field_9_8_mod_precode_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_cl136_frame_cycle_to_lock_attr == 10'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_cl136_prbs_encoder_select_even_attr == SERDES_SHIM_TFL_L3_CFG_CL136_PRBS_ENCODER_SELECT_EVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_cl136_precoder_out_swz_attr == SERDES_SHIM_TFL_L3_CFG_CL136_PRECODER_OUT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_cl136_precoder_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_cl136_stts_field_11_10_mod_precode_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_cl136_stts_field_14_12_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_cl136_stts_field_15_rx_ready_attr == SERDES_SHIM_TFL_L3_CFG_CL136_STTS_FIELD_15_RX_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_cl136_stts_field_2_0_coeff_stts_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_cl136_stts_field_5_3_coeff_sel_echo_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_cl136_stts_field_6_rsvd_attr == SERDES_SHIM_TFL_L3_CFG_CL136_STTS_FIELD_6_RSVD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_cl136_stts_field_7_parity_attr == SERDES_SHIM_TFL_L3_CFG_CL136_STTS_FIELD_7_PARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_cl136_stts_field_8_init_cond_stts_attr == SERDES_SHIM_TFL_L3_CFG_CL136_STTS_FIELD_8_INIT_COND_STTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_cl136_stts_field_9_rx_frame_lock_attr == SERDES_SHIM_TFL_L3_CFG_CL136_STTS_FIELD_9_RX_FRAME_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_cl72_ctrl_field_11_6_rsvd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_cl72_ctrl_field_12_initialize_attr == SERDES_SHIM_TFL_L3_CFG_CL72_CTRL_FIELD_12_INITIALIZE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_cl72_ctrl_field_13_preset_attr == SERDES_SHIM_TFL_L3_CFG_CL72_CTRL_FIELD_13_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_cl72_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_cl72_ctrl_field_1_0_coef_m1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_cl72_ctrl_field_3_2_coef_0_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_cl72_ctrl_field_5_4_coef_p1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_cl72_frame_cycle_to_lock_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_cl72_stts_field_14_6_rsvd_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_cl72_stts_field_15_rcv_ready_attr == SERDES_SHIM_TFL_L3_CFG_CL72_STTS_FIELD_15_RCV_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_cl72_stts_field_1_0_coef_m1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_cl72_stts_field_3_2_coef_0_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_cl72_stts_field_5_4_coef_p1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_frame_boundary_early_attr == SERDES_SHIM_TFL_L3_CFG_FRAME_BOUNDARY_EARLY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_gb_128_80_en_attr == SERDES_SHIM_TFL_L3_CFG_GB_128_80_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_ignore_tfl_en_to_avoid_cut_frame_attr == SERDES_SHIM_TFL_L3_CFG_IGNORE_TFL_EN_TO_AVOID_CUT_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_polynomial_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_prbs11_seed_2_attr == 11'd977
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_prbs11_seed_attr == 11'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_ber_count_snap_lock_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL136_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_ber_counter_clear_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL136_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_clear_one_marker_seen_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL136_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL136_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL136_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL136_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_pam4_modulation_select_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_prbs_ber_en_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL136_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_prbs_seed_force_en_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL136_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_prbs_seed_force_val_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_ber_count_snap_lock_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL72_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_ber_counter_clear_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL72_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_clear_one_marker_seen_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL72_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL72_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL72_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL72_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_prbs_ber_en_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL72_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_prbs_seed_force_en_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL72_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_prbs_seed_force_val_attr == 13'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_gb_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_rx_sync_pulse_attr == SERDES_SHIM_TFL_L3_CFG_RX_SYNC_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_scrambler_force_init_at_each_frame_attr == SERDES_SHIM_TFL_L3_CFG_SCRAMBLER_FORCE_INIT_AT_EACH_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_send_data_attr == SERDES_SHIM_TFL_L3_CFG_SEND_DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_sync_ctrl_stts_word_pulse_attr == SERDES_SHIM_TFL_L3_CFG_SYNC_CTRL_STTS_WORD_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_tfl_prbs13_en_attr == SERDES_SHIM_TFL_L3_CFG_TFL_PRBS13_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_tfl_pulse_sync_attr == SERDES_SHIM_TFL_L3_CFG_TFL_PULSE_SYNC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_tfl_training_enable_rx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_tfl_training_enable_tx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_tfl_l3_cfg_tx_gb_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_top_cfg_broadcast_feature_en_attr == SERDES_SHIM_TOP_CFG_BROADCAST_FEATURE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_top_cfg_broadcast_type_attr == SERDES_SHIM_TOP_CFG_BROADCAST_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_top_cfg_fabric_wd_counter_max_attr == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_top_cfg_fec_ber_datawidth_sel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_top_cfg_fec_ber_en_attr == SERDES_SHIM_TOP_CFG_FEC_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_top_cfg_fec_ber_mask8_attr == 8'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_top_cfg_fec_ber_packet_sel_attr == SERDES_SHIM_TOP_CFG_FEC_BER_PACKET_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_top_cfg_fec_ber_poly_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_top_cfg_fec_ber_rs_type_sel_attr == SERDES_SHIM_TOP_CFG_FEC_BER_RS_TYPE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_top_cfg_fec_ber_statistic_en_attr == SERDES_SHIM_TOP_CFG_FEC_BER_STATISTIC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_top_cfg_serdes_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_top_cfg_serdes_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_top_cfg_serdes_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_top_cfg_wdt_clr_attr == SERDES_SHIM_TOP_CFG_WDT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_top_cfg_wdt_en_attr == SERDES_SHIM_TOP_CFG_WDT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_top_cfg_wdt_pre_scale_attr == 32'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_top_cfg_wdt_rst_after_irq_mode_attr == SERDES_SHIM_TOP_CFG_WDT_RST_AFTER_IRQ_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_top_cfg_wdt_swrst_en_attr == SERDES_SHIM_TOP_CFG_WDT_SWRST_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_top_cfg_wdt_time_val_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_apb_cfg_presetn_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_CFG_PRESETN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_apb_lgc_rstn_serdes_ux_lane0_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_LGC_RSTN_SERDES_UX_LANE0_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_apb_lgc_rstn_serdes_ux_lane1_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_LGC_RSTN_SERDES_UX_LANE1_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_apb_lgc_rstn_serdes_ux_lane2_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_LGC_RSTN_SERDES_UX_LANE2_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_apb_lgc_rstn_serdes_ux_lane3_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_LGC_RSTN_SERDES_UX_LANE3_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_apb_mem_rstn_serdes_ux_lane0_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_MEM_RSTN_SERDES_UX_LANE0_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_apb_mem_rstn_serdes_ux_lane1_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_MEM_RSTN_SERDES_UX_LANE1_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_apb_mem_rstn_serdes_ux_lane2_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_MEM_RSTN_SERDES_UX_LANE2_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_apb_mem_rstn_serdes_ux_lane3_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_MEM_RSTN_SERDES_UX_LANE3_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_clkrx_bot_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_CLKRX_BOT_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_clkrx_top_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_CLKRX_TOP_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_lane0_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_LANE0_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_lane1_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_LANE1_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_lane2_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_LANE2_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_lane3_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_LANE3_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_scmng_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_SCMNG_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_srds_ctrl_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_SRDS_CTRL_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_srds_ux_lane0_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_SRDS_UX_LANE0_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_srds_ux_lane1_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_SRDS_UX_LANE1_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_srds_ux_lane2_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_SRDS_UX_LANE2_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_srds_ux_lane3_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_SRDS_UX_LANE3_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_clkrx_bot_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_CLKRX_BOT_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_clkrx_top_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_CLKRX_TOP_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_lane0_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_LANE0_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_lane1_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_LANE1_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_lane2_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_LANE2_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_lane3_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_LANE3_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_scmng_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_SCMNG_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_srds_ctrl_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_SRDS_CTRL_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_srds_ux_lane0_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_SRDS_UX_LANE0_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_srds_ux_lane1_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_SRDS_UX_LANE1_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_srds_ux_lane2_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_SRDS_UX_LANE2_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_srds_ux_lane3_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_SRDS_UX_LANE3_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_car_ux_lane_rst_src_sel_lane0_attr == SERDES_SHIM_WRAP_CAR_CFG_CAR_UX_LANE_RST_SRC_SEL_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_car_ux_lane_rst_src_sel_lane1_attr == SERDES_SHIM_WRAP_CAR_CFG_CAR_UX_LANE_RST_SRC_SEL_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_car_ux_lane_rst_src_sel_lane2_attr == SERDES_SHIM_WRAP_CAR_CFG_CAR_UX_LANE_RST_SRC_SEL_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_car_ux_lane_rst_src_sel_lane3_attr == SERDES_SHIM_WRAP_CAR_CFG_CAR_UX_LANE_RST_SRC_SEL_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_clkrx_ref_clk_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_cpu_apb_clocks_ratio_attr == SERDES_SHIM_WRAP_CAR_CFG_CPU_APB_CLOCKS_RATIO_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_cpu_clk_sel_attr == SERDES_SHIM_WRAP_CAR_CFG_CPU_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_cpu_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_CPU_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_cpu_runstall_attr == SERDES_SHIM_WRAP_CAR_CFG_CPU_RUNSTALL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_cpu_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_CPU_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_fast_clk_divn_en_attr == SERDES_SHIM_WRAP_CAR_CFG_FAST_CLK_DIVN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_fast_clk_divn_val_attr == 8'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_fast_clk_lane_sel_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_fb_cpu_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_FB_CPU_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_fb_cpu_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_FB_CPU_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_fb_rx_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_FB_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_fb_rx_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_FB_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_fec_ber_lane_select_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_hwrstn_clkrx_bot_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_CLKRX_BOT_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_hwrstn_clkrx_top_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_CLKRX_TOP_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_hwrstn_lane0_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_LANE0_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_hwrstn_lane1_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_LANE1_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_hwrstn_lane2_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_LANE2_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_hwrstn_lane3_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_LANE3_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_hwrstn_scmng_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_SCMNG_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_hwrstn_serdes_ctrl_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_SERDES_CTRL_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_hwrstn_serdes_ux_lane0_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_SERDES_UX_LANE0_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_hwrstn_serdes_ux_lane1_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_SERDES_UX_LANE1_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_hwrstn_serdes_ux_lane2_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_SERDES_UX_LANE2_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_hwrstn_serdes_ux_lane3_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_SERDES_UX_LANE3_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_lane_car_apb_cfg_presetn_swrstn_lane0_attr == SERDES_SHIM_WRAP_CAR_CFG_LANE_CAR_APB_CFG_PRESETN_SWRSTN_LANE0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_lane_car_apb_cfg_presetn_swrstn_lane1_attr == SERDES_SHIM_WRAP_CAR_CFG_LANE_CAR_APB_CFG_PRESETN_SWRSTN_LANE1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_lane_car_apb_cfg_presetn_swrstn_lane2_attr == SERDES_SHIM_WRAP_CAR_CFG_LANE_CAR_APB_CFG_PRESETN_SWRSTN_LANE2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_lane_car_apb_cfg_presetn_swrstn_lane3_attr == SERDES_SHIM_WRAP_CAR_CFG_LANE_CAR_APB_CFG_PRESETN_SWRSTN_LANE3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.serdes_shim_wrap_car_cfg_wrap_car_apb_cfg_presetn_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_WRAP_CAR_APB_CFG_PRESETN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.top_f_fastest_reconfig_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.top_refclk_reconfig_span == TOP_REFCLK_RECONFIG_SPAN_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.top_syspll_refclk_output_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_0_rx_synth_select == UX0_0_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_0_tx_synth_select == UX0_0_TX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_1_rx_synth_select == UX0_1_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_1_tx_synth_select == UX0_1_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_2_rx_synth_select == UX0_2_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_2_tx_synth_select == UX0_2_TX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_3_rx_synth_select == UX0_3_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_3_tx_synth_select == UX0_3_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_4_rx_synth_select == UX0_4_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_4_tx_synth_select == UX0_4_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_0_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_0_hscount == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_0_m_counter_physical == 9'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_0_meascount == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_0_mod_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_0_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_0_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_0_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_0_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_0_refclk_type_select == UX0_CDR_0_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_0_watchdogtmr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_1_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_1_hscount == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_1_m_counter_physical == 9'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_1_meascount == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_1_mod_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_1_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_1_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_1_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_1_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_1_refclk_type_select == UX0_CDR_1_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_1_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_2_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_2_hscount == 8'd180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_2_m_counter_physical == 9'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_2_meascount == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_2_mod_counter == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_2_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_2_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_2_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_2_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_2_refclk_type_select == UX0_CDR_2_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_2_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_3_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_3_hscount == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_3_m_counter_physical == 9'd66
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_3_meascount == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_3_mod_counter == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_3_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_3_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_3_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_3_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_3_refclk_type_select == UX0_CDR_3_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_3_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_4_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_4_hscount == 8'd206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_4_m_counter_physical == 9'd210
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_4_meascount == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_4_mod_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_4_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_4_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_4_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_4_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_4_refclk_type_select == UX0_CDR_4_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_4_watchdogtmr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_bw_sel == UX0_CDR_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_f_mod_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_f_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_hscount_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_is_cascaded == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_is_fractional == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_l_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_l_counter_physical == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_m_counter == 9'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_meascount_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_mod_counter_scratch == 40'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_ppm_driftcount == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_ppm_driftmax == 16'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_ppm_driftmax_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_ppm_driftmax_scratch_denominator == 47'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_ppm_driftmax_scratch_numerator == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_ppm_tolerance == 16'd7600
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_refclk_mux_select == UX0_CDR_REFCLK_MUX_SELECT_REGIONAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_refclk_select == UX0_CDR_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_squelch_sample_count == 10'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_squelch_sample_scratch == 40'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cdr_watchdogtmr_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cmn_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cmn_rx_cdr_refclk_mux_select == UX0_CMN_RX_CDR_REFCLK_MUX_SELECT_REGIONAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cmnrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cmnrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cmnrpu_evdn_delay_lut_entry3 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cmnrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cmnrpu_evup_delay_lut_entry2 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cmnrpu_evup_delay_lut_entry3 == 50'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cmnrpu_evup_delay_lut_entry4 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cmnrpu_evup_delay_lut_entry5 == 50'd62
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cmnrpu_evup_delay_lut_entry6 == 50'd390
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_cmnrpu_evup_delay_lut_entry7 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_core_pll == UX0_CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_core_pll_bw_sel == UX0_CORE_PLL_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_core_pll_refclk_select == UX0_CORE_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_dpma_f_out_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_dpma_n_counter == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_dpma_n_counter_physical == UX0_DPMA_N_COUNTER_PHYSICAL_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_dpma_n_counter_scratch == 40'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_dpma_refclk_source == UX0_DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_dts_ssdiv_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_duplex_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_enable_med_lc_0_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_enable_med_lc_1_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_enable_med_lc_2_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_enable_med_lc_3_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_enable_med_lc_4_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_enable_port_control_of_cdr_ltr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_enable_slow_lc_0_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_enable_slow_lc_1_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_enable_slow_lc_2_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_enable_slow_lc_3_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_enable_slow_lc_4_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_ethernet_source == UX0_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_expose_pcie_gen1_gen6_critical_signals == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_f_cascade_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_feed_forward_gain_scratch == 47'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_feed_forward_temp_one == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_feed_forward_temp_two == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_flux_mode == UX0_FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_kvcc_settle_maxcnt_scratch == 40'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_lane_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_loopback_mode == UX0_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_master_sup_mode == UX0_MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_oversampling_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_primary_use == UX0_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_ref_clk_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_refclk_in_1us_scratch == 40'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rx_adapt_mode == UX0_RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rx_bond_size == UX0_RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rx_cal_dutymeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rx_master_bond_chnl == UX0_RX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rx_o_usr_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rx_o_usr_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rx_onchip_termination == UX0_RX_ONCHIP_TERMINATION_R_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rx_over_sample == UX0_RX_OVER_SAMPLE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rx_protocol == UX0_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rx_term_mode_select == UX0_RX_TERM_MODE_SELECT_GROUNDED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rx_tuning_hint == UX0_RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rx_which_lane_to_copy == UX0_RX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rx_width == UX0_RX_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxeq_ctle_bias_adj == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxeq_ctle_biasboost == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxeq_ctle_lf_gain == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxeq_ctle_midband_zero == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxeq_ctle_stage_1_dcgain == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxeq_ctle_stage_1_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxeq_ctle_stage_2_cap == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxeq_ctle_stage_2_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxeq_ctle_stage_2_reszero == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxeq_ctle_stage_3_dcgain == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxeq_ctle_stage_3_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxeq_dfe_data_tap_10 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxeq_dfe_data_tap_11 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxeq_dfe_data_tap_12 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxeq_dfe_data_tap_13 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxeq_dfe_data_tap_14 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxeq_dfe_data_tap_15 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxeq_dfe_data_tap_16 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxeq_dfe_data_tap_2 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxeq_dfe_data_tap_3 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxeq_dfe_data_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxeq_dfe_data_tap_5 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxeq_dfe_data_tap_6 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxeq_dfe_data_tap_7 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxeq_dfe_data_tap_8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxeq_dfe_data_tap_9 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxeq_dfe_edge_tap_2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxeq_dfe_edge_tap_3 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxeq_dfe_edge_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxeq_iq_clk == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxeq_targ_0_hi == 9'd149
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxeq_targ_0_lo == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxeq_vga_gain == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxratewidth_pd_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxrpu_evup_delay_lut_entry2 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxrpu_evup_delay_lut_entry4 == 50'd78
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxrpu_evup_delay_lut_entry5 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxrpu_evup_delay_lut_entry6 == 50'd1406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_rxrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_select_lc_0_tx_path == UX0_SELECT_LC_0_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_select_lc_1_tx_path == UX0_SELECT_LC_1_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_select_lc_2_tx_path == UX0_SELECT_LC_2_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_select_lc_3_tx_path == UX0_SELECT_LC_3_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_select_lc_4_tx_path == UX0_SELECT_LC_4_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_sup_mode == UX0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_afc_range == UX0_SYNTH_LC_0_AFC_RANGE_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_afc_refclk_count == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_dtr_prop_coeff == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_f_max_vco_hz == 40'd10500000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_f_min_vco_hz == 40'd8000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_fast_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_fast_tx_postdiv_counter == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_feed_forward_gain == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_fine_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_fine_int_coeff_tmp == 4'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_fine_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_fine_prop_coeff_tmp == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_kvcc_settle_maxcnt == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_m_counter == 9'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_med_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_med_tx_postdiv_counter == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_refclk_in_1us == 8'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_slow_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_slow_tx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_tdc_fine_res_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_tdc_target_count == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_0_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_afc_range == UX0_SYNTH_LC_1_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_feed_forward_gain == 8'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_m_counter == 9'd45
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_1_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_afc_range == UX0_SYNTH_LC_2_AFC_RANGE_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_dtr_int_coeff == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_feed_forward_gain == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_m_counter == 9'd27
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_2_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_afc_range == UX0_SYNTH_LC_3_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_feed_forward_gain == 8'd23
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_m_counter == 9'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_3_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_afc_range == UX0_SYNTH_LC_4_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_afc_refclk_count == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_dtr_int_coeff == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_feed_forward_gain == 8'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_fine_int_coeff == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_kvcc_settle_maxcnt == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_m_counter == 9'd216
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_med_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_refclk_in_1us == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_tdc_refclk_count == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_tdc_target_count == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_4_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_fast_bw_sel == UX0_SYNTH_LC_FAST_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_fast_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_fast_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_fast_primary_use == UX0_SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_fast_refclk_mux_select == UX0_SYNTH_LC_FAST_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_fast_refclk_type_select == UX0_SYNTH_LC_FAST_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_fast_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_fb_div_emb_mult_counter == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_l_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_l_counter_physical == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_med_bw_sel == UX0_SYNTH_LC_MED_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_med_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_med_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_med_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_med_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_med_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_med_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_med_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_med_primary_use == UX0_SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_med_refclk_mux_select == UX0_SYNTH_LC_MED_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_med_refclk_type_select == UX0_SYNTH_LC_MED_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_med_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_slow_bw_sel == UX0_SYNTH_LC_SLOW_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_slow_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_slow_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_slow_primary_use == UX0_SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_slow_refclk_mux_select == UX0_SYNTH_LC_SLOW_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_slow_refclk_type_select == UX0_SYNTH_LC_SLOW_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synth_lc_slow_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlc_0_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlc_0_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlc_0_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlc_0_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlc_1_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlc_1_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlc_1_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlc_1_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlc_2_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlc_2_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlc_2_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlc_2_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlc_3_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlc_3_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlc_3_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlc_3_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlc_4_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlc_4_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlc_4_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlc_4_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlc_dcdmeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlcfastratewidth_pd_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlcfastrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlcfastrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlcfastrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlcfastrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlcfastrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlcfastrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlcfastrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlcfastrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlcfastrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlcfastrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlcfastrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlcmedrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlcmedrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlcmedrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlcmedrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlcmedrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlcmedrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlcmedrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlcmedrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlcmedrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlcmedrpu_evup_delay_lut_entry7 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlcslowrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlcslowrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlcslowrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlcslowrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlcslowrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlcslowrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlcslowrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlcslowrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlcslowrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_synthlcslowrpu_evup_delay_lut_entry7 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tdc_refclk_count_divisor == 40'd850000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tdc_refclk_count_scratch == 40'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tdc_target_count_scratch == 40'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tx_bond_size == UX0_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tx_cal_dutymeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tx_i_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tx_i_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tx_i_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tx_master_bond_chnl == UX0_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tx_o_usr_clk_1_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tx_o_usr_clk_1_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tx_o_usr_clk_2_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tx_over_sample == UX0_TX_OVER_SAMPLE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tx_pll == UX0_TX_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tx_pll_bw_sel == UX0_TX_PLL_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tx_pll_is_downstream_pll == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tx_pll_refclk_mux_select == UX0_TX_PLL_REFCLK_MUX_SELECT_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tx_pll_refclk_select == UX0_TX_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tx_protocol == UX0_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tx_tuning_hint == UX0_TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tx_user_clk1_mux == UX0_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tx_user_clk2_mux == UX0_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tx_user_clk_slow_med_mux == UX0_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tx_which_lane_to_copy == UX0_TX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_tx_width == UX0_TX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_txeq_main_tap == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_txratewidth_rst_b0_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_txrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_txrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_txrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_txrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_txrpu_evup_delay_lut_entry2 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_txrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_txrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_txrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_txrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_txrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_txrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_txrx_channel_operation == UX0_TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_txrx_line_encoding_type == UX0_TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_txrx_xcvr_speed_bucket == UX0_TXRX_XCVR_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux0_vreg_loopen_maxcnt_scratch == 40'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_0_rx_synth_select == UX1_0_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_0_tx_synth_select == UX1_0_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_1_rx_synth_select == UX1_1_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_1_tx_synth_select == UX1_1_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_2_rx_synth_select == UX1_2_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_2_tx_synth_select == UX1_2_TX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_3_rx_synth_select == UX1_3_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_3_tx_synth_select == UX1_3_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_4_rx_synth_select == UX1_4_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_4_tx_synth_select == UX1_4_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_0_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_0_hscount == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_0_m_counter_physical == 9'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_0_meascount == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_0_mod_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_0_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_0_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_0_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_0_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_0_refclk_type_select == UX1_CDR_0_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_0_watchdogtmr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_1_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_1_hscount == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_1_m_counter_physical == 9'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_1_meascount == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_1_mod_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_1_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_1_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_1_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_1_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_1_refclk_type_select == UX1_CDR_1_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_1_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_2_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_2_hscount == 8'd180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_2_m_counter_physical == 9'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_2_meascount == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_2_mod_counter == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_2_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_2_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_2_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_2_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_2_refclk_type_select == UX1_CDR_2_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_2_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_3_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_3_hscount == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_3_m_counter_physical == 9'd66
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_3_meascount == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_3_mod_counter == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_3_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_3_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_3_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_3_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_3_refclk_type_select == UX1_CDR_3_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_3_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_4_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_4_hscount == 8'd206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_4_m_counter_physical == 9'd210
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_4_meascount == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_4_mod_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_4_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_4_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_4_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_4_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_4_refclk_type_select == UX1_CDR_4_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_4_watchdogtmr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_bw_sel == UX1_CDR_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_f_mod_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_f_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_hscount_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_is_cascaded == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_is_fractional == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_l_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_l_counter_physical == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_m_counter == 9'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_meascount_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_mod_counter_scratch == 40'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_ppm_driftcount == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_ppm_driftmax == 16'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_ppm_driftmax_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_ppm_driftmax_scratch_denominator == 47'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_ppm_driftmax_scratch_numerator == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_ppm_tolerance == 16'd7600
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_refclk_mux_select == UX1_CDR_REFCLK_MUX_SELECT_REGIONAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_refclk_select == UX1_CDR_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_squelch_sample_count == 10'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_squelch_sample_scratch == 40'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cdr_watchdogtmr_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cmn_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cmn_rx_cdr_refclk_mux_select == UX1_CMN_RX_CDR_REFCLK_MUX_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cmnrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cmnrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cmnrpu_evdn_delay_lut_entry3 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cmnrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cmnrpu_evup_delay_lut_entry2 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cmnrpu_evup_delay_lut_entry3 == 50'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cmnrpu_evup_delay_lut_entry4 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cmnrpu_evup_delay_lut_entry5 == 50'd62
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cmnrpu_evup_delay_lut_entry6 == 50'd390
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_cmnrpu_evup_delay_lut_entry7 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_core_pll == UX1_CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_core_pll_bw_sel == UX1_CORE_PLL_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_core_pll_refclk_select == UX1_CORE_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_dpma_f_out_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_dpma_n_counter == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_dpma_n_counter_physical == UX1_DPMA_N_COUNTER_PHYSICAL_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_dpma_n_counter_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_dpma_refclk_source == UX1_DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_dts_ssdiv_scratch == 40'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_duplex_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_enable_med_lc_0_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_enable_med_lc_1_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_enable_med_lc_2_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_enable_med_lc_3_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_enable_med_lc_4_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_enable_port_control_of_cdr_ltr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_enable_slow_lc_0_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_enable_slow_lc_1_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_enable_slow_lc_2_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_enable_slow_lc_3_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_enable_slow_lc_4_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_ethernet_source == UX1_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_expose_pcie_gen1_gen6_critical_signals == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_f_cascade_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_feed_forward_gain_scratch == 47'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_feed_forward_temp_one == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_feed_forward_temp_two == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_flux_mode == UX1_FLUX_MODE_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_kvcc_settle_maxcnt_scratch == 40'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_lane_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_loopback_mode == UX1_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_master_sup_mode == UX1_MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_oversampling_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_prbs_mon_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_primary_use == UX1_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_ref_clk_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_refclk_in_1us_scratch == 40'd148
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rx_adapt_mode == UX1_RX_ADAPT_MODE_STATIC_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rx_bond_size == UX1_RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rx_cal_dutymeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rx_master_bond_chnl == UX1_RX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rx_o_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rx_o_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rx_o_usr_clk_e2_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rx_o_usr_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rx_onchip_termination == UX1_RX_ONCHIP_TERMINATION_R_4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rx_over_sample == UX1_RX_OVER_SAMPLE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rx_protocol == UX1_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rx_protocol_hard_pcie_lowloss == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rx_term_mode_select == UX1_RX_TERM_MODE_SELECT_GROUNDED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rx_tuning_hint == UX1_RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rx_user_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rx_which_lane_to_copy == UX1_RX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rx_width == UX1_RX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxeq_ctle_bias_adj == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxeq_ctle_biasboost == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxeq_ctle_lf_gain == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxeq_ctle_midband_zero == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxeq_ctle_stage_1_dcgain == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxeq_ctle_stage_1_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxeq_ctle_stage_2_cap == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxeq_ctle_stage_2_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxeq_ctle_stage_2_reszero == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxeq_ctle_stage_3_dcgain == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxeq_ctle_stage_3_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxeq_dfe_data_tap_10 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxeq_dfe_data_tap_11 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxeq_dfe_data_tap_12 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxeq_dfe_data_tap_13 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxeq_dfe_data_tap_14 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxeq_dfe_data_tap_15 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxeq_dfe_data_tap_16 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxeq_dfe_data_tap_2 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxeq_dfe_data_tap_3 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxeq_dfe_data_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxeq_dfe_data_tap_5 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxeq_dfe_data_tap_6 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxeq_dfe_data_tap_7 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxeq_dfe_data_tap_8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxeq_dfe_data_tap_9 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxeq_dfe_edge_tap_2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxeq_dfe_edge_tap_3 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxeq_dfe_edge_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxeq_iq_clk == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxeq_targ_0_hi == 9'd130
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxeq_targ_0_lo == 9'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxeq_vga_gain == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxratewidth_pd_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxrpu_evup_delay_lut_entry4 == 50'd78
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxrpu_evup_delay_lut_entry5 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxrpu_evup_delay_lut_entry6 == 50'd1406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_rxrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_select_lc_0_tx_path == UX1_SELECT_LC_0_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_select_lc_1_tx_path == UX1_SELECT_LC_1_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_select_lc_2_tx_path == UX1_SELECT_LC_2_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_select_lc_3_tx_path == UX1_SELECT_LC_3_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_select_lc_4_tx_path == UX1_SELECT_LC_4_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_squelch_detect == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_sup_mode == UX1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_afc_range == UX1_SYNTH_LC_0_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_dtr_int_coeff == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_dtr_prop_coeff == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_f_max_vco_hz == 40'd12500000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_f_min_vco_hz == 40'd10500000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_f_out_hz == 40'd5940000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_f_pfd_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_f_ref_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_f_vco_hz == 40'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_fast_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_fast_tx_postdiv_counter == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_feed_forward_gain == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_fine_int_coeff == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_fine_int_coeff_tmp == 4'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_fine_prop_coeff == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_fine_prop_coeff_tmp == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_kvcc_settle_maxcnt == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_m_counter == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_med_f_tx_postdiv_hz == 40'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_med_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_med_tx_postdiv_counter == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_med_tx_postdiv_counter_physical == 7'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_med_tx_postdiv_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_refclk_in_1us == 8'd148
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_slow_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_slow_tx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_tdc_fine_res_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_tdc_target_count == 8'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_0_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_afc_range == UX1_SYNTH_LC_1_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_feed_forward_gain == 8'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_m_counter == 9'd90
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_1_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_afc_range == UX1_SYNTH_LC_2_AFC_RANGE_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_dtr_int_coeff == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_feed_forward_gain == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_m_counter == 9'd54
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_2_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_afc_range == UX1_SYNTH_LC_3_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_feed_forward_gain == 8'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_m_counter == 9'd72
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_3_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_afc_range == UX1_SYNTH_LC_4_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_afc_refclk_count == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_dtr_int_coeff == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_feed_forward_gain == 8'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_fine_int_coeff == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_kvcc_settle_maxcnt == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_m_counter == 9'd432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_med_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_refclk_in_1us == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_tdc_refclk_count == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_tdc_target_count == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_4_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_fast_bw_sel == UX1_SYNTH_LC_FAST_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_fast_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_fast_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_fast_primary_use == UX1_SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_fast_refclk_mux_select == UX1_SYNTH_LC_FAST_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_fast_refclk_type_select == UX1_SYNTH_LC_FAST_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_fast_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_fb_div_emb_mult_counter == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_fb_div_n_frac_mode == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_l_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_l_counter_physical == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_med_bw_sel == UX1_SYNTH_LC_MED_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_med_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_med_f_out_hz == 40'd5940000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_med_f_ref_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_med_f_tx_postdiv_hz == 40'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_med_f_vco_hz == 40'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_med_l_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_med_m_counter == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_med_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_med_primary_use == UX1_SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_med_refclk_mux_select == UX1_SYNTH_LC_MED_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_med_refclk_type_select == UX1_SYNTH_LC_MED_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_med_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_med_tx_postdiv_counter == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_med_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_slow_bw_sel == UX1_SYNTH_LC_SLOW_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_slow_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_slow_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_slow_primary_use == UX1_SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_slow_refclk_mux_select == UX1_SYNTH_LC_SLOW_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_slow_refclk_type_select == UX1_SYNTH_LC_SLOW_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synth_lc_slow_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlc_0_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlc_0_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlc_0_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlc_0_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlc_1_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlc_1_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlc_1_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlc_1_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlc_2_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlc_2_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlc_2_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlc_2_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlc_3_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlc_3_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlc_3_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlc_3_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlc_4_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlc_4_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlc_4_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlc_4_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlc_dcdmeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlcfastratewidth_pd_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlcfastrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlcfastrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlcfastrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlcfastrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlcfastrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlcfastrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlcfastrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlcfastrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlcfastrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlcfastrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlcfastrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlcmedrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlcmedrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlcmedrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlcmedrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlcmedrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlcmedrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlcmedrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlcmedrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlcmedrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlcmedrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlcslowrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlcslowrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlcslowrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlcslowrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlcslowrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlcslowrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlcslowrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlcslowrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlcslowrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_synthlcslowrpu_evup_delay_lut_entry7 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tdc_refclk_count_divisor == 40'd850000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tdc_refclk_count_scratch == 40'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tdc_target_count_scratch == 40'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tx_bond_size == UX1_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tx_cal_dutymeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tx_datarate == 40'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tx_i_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tx_i_clk_e4_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tx_i_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tx_line_rate_bps == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tx_master_bond_chnl == UX1_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tx_o_clk_e2_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tx_o_clk_e4_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tx_o_usr_clk_1_e2_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tx_o_usr_clk_1_e4_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tx_o_usr_clk_2_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tx_over_sample == UX1_TX_OVER_SAMPLE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tx_pll == UX1_TX_PLL_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tx_pll_bw_sel == UX1_TX_PLL_BW_SEL_MEDIUM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tx_pll_is_downstream_pll == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tx_pll_refclk_mux_select == UX1_TX_PLL_REFCLK_MUX_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tx_pll_refclk_select == UX1_TX_PLL_REFCLK_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tx_protocol == UX1_TX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tx_tuning_hint == UX1_TX_TUNING_HINT_SDI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tx_user_clk1_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tx_user_clk1_mux == UX1_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tx_user_clk2_mux == UX1_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tx_user_clk_slow_med_mux == UX1_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tx_which_lane_to_copy == UX1_TX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_tx_width == UX1_TX_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_txeq_main_tap == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_txratewidth_rst_b0_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_txrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_txrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_txrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_txrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_txrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_txrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_txrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_txrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_txrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_txrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_txrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_txrx_channel_operation == UX1_TXRX_CHANNEL_OPERATION_DUAL_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_txrx_line_encoding_type == UX1_TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_txrx_xcvr_speed_bucket == UX1_TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux1_vreg_loopen_maxcnt_scratch == 40'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_0_rx_synth_select == UX2_0_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_0_tx_synth_select == UX2_0_TX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_1_rx_synth_select == UX2_1_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_1_tx_synth_select == UX2_1_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_2_rx_synth_select == UX2_2_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_2_tx_synth_select == UX2_2_TX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_3_rx_synth_select == UX2_3_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_3_tx_synth_select == UX2_3_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_4_rx_synth_select == UX2_4_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_4_tx_synth_select == UX2_4_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_0_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_0_hscount == 8'd181
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_0_m_counter_physical == 9'd194
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_0_meascount == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_0_mod_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_0_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_0_postdiv_counter_physical == 7'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_0_postdiv_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_0_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_0_refclk_type_select == UX2_CDR_0_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_0_watchdogtmr == 16'd1188
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_1_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_1_hscount == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_1_m_counter_physical == 9'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_1_meascount == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_1_mod_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_1_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_1_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_1_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_1_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_1_refclk_type_select == UX2_CDR_1_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_1_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_2_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_2_hscount == 8'd180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_2_m_counter_physical == 9'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_2_meascount == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_2_mod_counter == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_2_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_2_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_2_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_2_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_2_refclk_type_select == UX2_CDR_2_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_2_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_3_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_3_hscount == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_3_m_counter_physical == 9'd66
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_3_meascount == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_3_mod_counter == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_3_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_3_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_3_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_3_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_3_refclk_type_select == UX2_CDR_3_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_3_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_4_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_4_hscount == 8'd206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_4_m_counter_physical == 9'd210
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_4_meascount == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_4_mod_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_4_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_4_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_4_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_4_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_4_refclk_type_select == UX2_CDR_4_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_4_watchdogtmr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_bw_sel == UX2_CDR_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_f_mod_hz == 40'd990000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_f_out_hz == 40'd5940000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_f_pfd_hz == 40'd29700000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_f_postdiv_hz == 40'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_f_ref_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_f_vco_hz == 40'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_hscount_scratch == 40'd181
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_is_cascaded == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_is_fractional == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_l_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_l_counter_physical == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_m_counter == 9'd200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_meascount_scratch == 40'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_mod_counter_scratch == 40'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_postdiv_counter == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_ppm_driftcount == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_ppm_driftmax == 16'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_ppm_driftmax_scratch == 47'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_ppm_driftmax_scratch_denominator == 47'd1015257760000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_ppm_driftmax_scratch_numerator == 47'd31129600000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_ppm_tolerance == 16'd7600
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_refclk_mux_select == UX2_CDR_REFCLK_MUX_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_refclk_select == UX2_CDR_REFCLK_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_squelch_sample_count == 10'd144
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_squelch_sample_scratch == 40'd144
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cdr_watchdogtmr_scratch == 40'd1188
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cmn_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cmn_rx_cdr_refclk_mux_select == UX2_CMN_RX_CDR_REFCLK_MUX_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cmnrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cmnrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cmnrpu_evdn_delay_lut_entry3 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cmnrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cmnrpu_evup_delay_lut_entry2 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cmnrpu_evup_delay_lut_entry3 == 50'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cmnrpu_evup_delay_lut_entry4 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cmnrpu_evup_delay_lut_entry5 == 50'd62
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cmnrpu_evup_delay_lut_entry6 == 50'd390
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_cmnrpu_evup_delay_lut_entry7 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_core_pll == UX2_CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_core_pll_bw_sel == UX2_CORE_PLL_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_core_pll_refclk_select == UX2_CORE_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_dpma_f_out_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_dpma_n_counter == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_dpma_n_counter_physical == UX2_DPMA_N_COUNTER_PHYSICAL_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_dpma_n_counter_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_dpma_refclk_source == UX2_DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_dts_ssdiv_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_duplex_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_enable_med_lc_0_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_enable_med_lc_1_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_enable_med_lc_2_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_enable_med_lc_3_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_enable_med_lc_4_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_enable_port_control_of_cdr_ltr_ltd == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_enable_slow_lc_0_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_enable_slow_lc_1_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_enable_slow_lc_2_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_enable_slow_lc_3_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_enable_slow_lc_4_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_ethernet_source == UX2_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_expose_pcie_gen1_gen6_critical_signals == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_f_cascade_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_feed_forward_gain_scratch == 47'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_feed_forward_temp_one == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_feed_forward_temp_two == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_flux_mode == UX2_FLUX_MODE_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_kvcc_settle_maxcnt_scratch == 40'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_lane_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_loopback_mode == UX2_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_master_sup_mode == UX2_MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_oversampling_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_prbs_gen_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_primary_use == UX2_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_ref_clk_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_refclk_in_1us_scratch == 40'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rx_adapt_mode == UX2_RX_ADAPT_MODE_UX_RX_ADAPT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rx_bond_size == UX2_RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rx_cal_dutymeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rx_datarate == 40'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rx_line_rate_bps == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rx_master_bond_chnl == UX2_RX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rx_o_clk_e2_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rx_o_clk_e4_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rx_o_usr_clk_e2_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rx_o_usr_clk_e4_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rx_onchip_termination == UX2_RX_ONCHIP_TERMINATION_R_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rx_over_sample == UX2_RX_OVER_SAMPLE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rx_protocol == UX2_RX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rx_term_mode_select == UX2_RX_TERM_MODE_SELECT_DIFFERENTIAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rx_tuning_hint == UX2_RX_TUNING_HINT_SDI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rx_user_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rx_which_lane_to_copy == UX2_RX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rx_width == UX2_RX_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxeq_ctle_bias_adj == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxeq_ctle_biasboost == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxeq_ctle_lf_gain == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxeq_ctle_midband_zero == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxeq_ctle_stage_1_dcgain == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxeq_ctle_stage_1_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxeq_ctle_stage_2_cap == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxeq_ctle_stage_2_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxeq_ctle_stage_2_reszero == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxeq_ctle_stage_3_dcgain == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxeq_ctle_stage_3_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxeq_dfe_data_tap_10 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxeq_dfe_data_tap_11 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxeq_dfe_data_tap_12 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxeq_dfe_data_tap_13 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxeq_dfe_data_tap_14 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxeq_dfe_data_tap_15 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxeq_dfe_data_tap_16 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxeq_dfe_data_tap_2 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxeq_dfe_data_tap_3 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxeq_dfe_data_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxeq_dfe_data_tap_5 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxeq_dfe_data_tap_6 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxeq_dfe_data_tap_7 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxeq_dfe_data_tap_8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxeq_dfe_data_tap_9 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxeq_dfe_edge_tap_2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxeq_dfe_edge_tap_3 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxeq_dfe_edge_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxeq_iq_clk == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxeq_targ_0_hi == 9'd160
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxeq_targ_0_lo == 9'd140
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxeq_vga_gain == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxratewidth_pd_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxrpu_evup_delay_lut_entry4 == 50'd78
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxrpu_evup_delay_lut_entry5 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxrpu_evup_delay_lut_entry6 == 50'd1406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_rxrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_select_lc_0_tx_path == UX2_SELECT_LC_0_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_select_lc_1_tx_path == UX2_SELECT_LC_1_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_select_lc_2_tx_path == UX2_SELECT_LC_2_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_select_lc_3_tx_path == UX2_SELECT_LC_3_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_select_lc_4_tx_path == UX2_SELECT_LC_4_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_sup_mode == UX2_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_afc_range == UX2_SYNTH_LC_0_AFC_RANGE_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_afc_refclk_count == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_dtr_prop_coeff == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_f_max_vco_hz == 40'd10500000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_f_min_vco_hz == 40'd8000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_fast_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_fast_tx_postdiv_counter == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_feed_forward_gain == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_fine_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_fine_int_coeff_tmp == 4'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_fine_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_fine_prop_coeff_tmp == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_kvcc_settle_maxcnt == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_m_counter == 9'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_med_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_med_tx_postdiv_counter == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_refclk_in_1us == 8'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_slow_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_slow_tx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_tdc_fine_res_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_tdc_target_count == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_0_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_afc_range == UX2_SYNTH_LC_1_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_feed_forward_gain == 8'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_m_counter == 9'd90
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_1_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_afc_range == UX2_SYNTH_LC_2_AFC_RANGE_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_dtr_int_coeff == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_feed_forward_gain == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_m_counter == 9'd54
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_2_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_afc_range == UX2_SYNTH_LC_3_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_feed_forward_gain == 8'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_m_counter == 9'd72
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_3_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_afc_range == UX2_SYNTH_LC_4_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_afc_refclk_count == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_dtr_int_coeff == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_feed_forward_gain == 8'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_fine_int_coeff == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_kvcc_settle_maxcnt == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_m_counter == 9'd432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_med_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_refclk_in_1us == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_tdc_refclk_count == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_tdc_target_count == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_4_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_fast_bw_sel == UX2_SYNTH_LC_FAST_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_fast_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_fast_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_fast_primary_use == UX2_SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_fast_refclk_mux_select == UX2_SYNTH_LC_FAST_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_fast_refclk_type_select == UX2_SYNTH_LC_FAST_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_fast_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_fb_div_emb_mult_counter == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_fb_div_n_frac_mode == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_l_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_l_counter_physical == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_med_bw_sel == UX2_SYNTH_LC_MED_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_med_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_med_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_med_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_med_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_med_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_med_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_med_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_med_primary_use == UX2_SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_med_refclk_mux_select == UX2_SYNTH_LC_MED_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_med_refclk_type_select == UX2_SYNTH_LC_MED_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_med_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_slow_bw_sel == UX2_SYNTH_LC_SLOW_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_slow_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_slow_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_slow_primary_use == UX2_SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_slow_refclk_mux_select == UX2_SYNTH_LC_SLOW_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_slow_refclk_type_select == UX2_SYNTH_LC_SLOW_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synth_lc_slow_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlc_0_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlc_0_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlc_0_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlc_0_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlc_1_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlc_1_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlc_1_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlc_1_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlc_2_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlc_2_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlc_2_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlc_2_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlc_3_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlc_3_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlc_3_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlc_3_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlc_4_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlc_4_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlc_4_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlc_4_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlc_dcdmeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlcfastratewidth_pd_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlcfastrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlcfastrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlcfastrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlcfastrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlcfastrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlcfastrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlcfastrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlcfastrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlcfastrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlcfastrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlcfastrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlcmedrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlcmedrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlcmedrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlcmedrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlcmedrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlcmedrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlcmedrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlcmedrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlcmedrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlcmedrpu_evup_delay_lut_entry7 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlcslowrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlcslowrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlcslowrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlcslowrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlcslowrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlcslowrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlcslowrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlcslowrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlcslowrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_synthlcslowrpu_evup_delay_lut_entry7 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tdc_refclk_count_divisor == 40'd850000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tdc_refclk_count_scratch == 40'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tdc_target_count_scratch == 40'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tx_bond_size == UX2_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tx_cal_dutymeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tx_i_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tx_i_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tx_i_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tx_master_bond_chnl == UX2_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tx_o_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tx_o_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tx_o_usr_clk_1_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tx_o_usr_clk_1_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tx_o_usr_clk_2_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tx_over_sample == UX2_TX_OVER_SAMPLE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tx_pll == UX2_TX_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tx_pll_bw_sel == UX2_TX_PLL_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tx_pll_is_downstream_pll == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tx_pll_refclk_mux_select == UX2_TX_PLL_REFCLK_MUX_SELECT_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tx_pll_refclk_select == UX2_TX_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tx_protocol == UX2_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tx_protocol_hard_pcie_lowloss == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tx_tuning_hint == UX2_TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tx_user_clk1_mux == UX2_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tx_user_clk2_mux == UX2_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tx_user_clk_slow_med_mux == UX2_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tx_which_lane_to_copy == UX2_TX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_tx_width == UX2_TX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_txeq_main_tap == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_txratewidth_rst_b0_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_txrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_txrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_txrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_txrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_txrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_txrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_txrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_txrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_txrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_txrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_txrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_txrx_channel_operation == UX2_TXRX_CHANNEL_OPERATION_DUAL_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_txrx_line_encoding_type == UX2_TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_txrx_xcvr_speed_bucket == UX2_TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux2_vreg_loopen_maxcnt_scratch == 40'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_0_rx_synth_select == UX3_0_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_0_tx_synth_select == UX3_0_TX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_1_rx_synth_select == UX3_1_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_1_tx_synth_select == UX3_1_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_2_rx_synth_select == UX3_2_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_2_tx_synth_select == UX3_2_TX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_3_rx_synth_select == UX3_3_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_3_tx_synth_select == UX3_3_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_4_rx_synth_select == UX3_4_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_4_tx_synth_select == UX3_4_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_0_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_0_hscount == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_0_m_counter_physical == 9'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_0_meascount == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_0_mod_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_0_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_0_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_0_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_0_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_0_refclk_type_select == UX3_CDR_0_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_0_watchdogtmr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_1_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_1_hscount == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_1_m_counter_physical == 9'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_1_meascount == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_1_mod_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_1_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_1_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_1_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_1_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_1_refclk_type_select == UX3_CDR_1_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_1_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_2_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_2_hscount == 8'd180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_2_m_counter_physical == 9'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_2_meascount == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_2_mod_counter == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_2_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_2_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_2_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_2_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_2_refclk_type_select == UX3_CDR_2_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_2_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_3_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_3_hscount == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_3_m_counter_physical == 9'd66
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_3_meascount == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_3_mod_counter == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_3_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_3_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_3_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_3_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_3_refclk_type_select == UX3_CDR_3_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_3_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_4_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_4_hscount == 8'd206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_4_m_counter_physical == 9'd210
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_4_meascount == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_4_mod_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_4_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_4_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_4_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_4_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_4_refclk_type_select == UX3_CDR_4_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_4_watchdogtmr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_bw_sel == UX3_CDR_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_f_mod_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_f_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_hscount_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_is_cascaded == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_is_fractional == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_l_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_l_counter_physical == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_m_counter == 9'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_meascount_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_mod_counter_scratch == 40'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_ppm_driftcount == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_ppm_driftmax == 16'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_ppm_driftmax_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_ppm_driftmax_scratch_denominator == 47'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_ppm_driftmax_scratch_numerator == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_ppm_tolerance == 16'd7600
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_refclk_mux_select == UX3_CDR_REFCLK_MUX_SELECT_REGIONAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_refclk_select == UX3_CDR_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_squelch_sample_count == 10'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_squelch_sample_scratch == 40'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cdr_watchdogtmr_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cmn_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cmn_rx_cdr_refclk_mux_select == UX3_CMN_RX_CDR_REFCLK_MUX_SELECT_REGIONAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cmnrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cmnrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cmnrpu_evdn_delay_lut_entry3 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cmnrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cmnrpu_evup_delay_lut_entry2 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cmnrpu_evup_delay_lut_entry3 == 50'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cmnrpu_evup_delay_lut_entry4 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cmnrpu_evup_delay_lut_entry5 == 50'd62
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cmnrpu_evup_delay_lut_entry6 == 50'd390
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_cmnrpu_evup_delay_lut_entry7 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_core_pll == UX3_CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_core_pll_bw_sel == UX3_CORE_PLL_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_core_pll_refclk_select == UX3_CORE_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_dpma_f_out_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_dpma_n_counter == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_dpma_n_counter_physical == UX3_DPMA_N_COUNTER_PHYSICAL_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_dpma_n_counter_scratch == 40'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_dpma_refclk_source == UX3_DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_dts_ssdiv_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_duplex_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_enable_med_lc_0_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_enable_med_lc_1_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_enable_med_lc_2_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_enable_med_lc_3_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_enable_med_lc_4_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_enable_port_control_of_cdr_ltr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_enable_slow_lc_0_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_enable_slow_lc_1_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_enable_slow_lc_2_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_enable_slow_lc_3_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_enable_slow_lc_4_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_ethernet_source == UX3_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_expose_pcie_gen1_gen6_critical_signals == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_f_cascade_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_feed_forward_gain_scratch == 47'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_feed_forward_temp_one == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_feed_forward_temp_two == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_flux_mode == UX3_FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_kvcc_settle_maxcnt_scratch == 40'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_lane_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_loopback_mode == UX3_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_master_sup_mode == UX3_MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_oversampling_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_primary_use == UX3_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_ref_clk_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_refclk_in_1us_scratch == 40'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rx_adapt_mode == UX3_RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rx_bond_size == UX3_RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rx_cal_dutymeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rx_master_bond_chnl == UX3_RX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rx_o_usr_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rx_o_usr_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rx_onchip_termination == UX3_RX_ONCHIP_TERMINATION_R_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rx_over_sample == UX3_RX_OVER_SAMPLE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rx_protocol == UX3_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rx_term_mode_select == UX3_RX_TERM_MODE_SELECT_GROUNDED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rx_tuning_hint == UX3_RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rx_which_lane_to_copy == UX3_RX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rx_width == UX3_RX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxeq_ctle_bias_adj == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxeq_ctle_biasboost == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxeq_ctle_lf_gain == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxeq_ctle_midband_zero == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxeq_ctle_stage_1_dcgain == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxeq_ctle_stage_1_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxeq_ctle_stage_2_cap == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxeq_ctle_stage_2_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxeq_ctle_stage_2_reszero == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxeq_ctle_stage_3_dcgain == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxeq_ctle_stage_3_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxeq_dfe_data_tap_10 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxeq_dfe_data_tap_11 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxeq_dfe_data_tap_12 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxeq_dfe_data_tap_13 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxeq_dfe_data_tap_14 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxeq_dfe_data_tap_15 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxeq_dfe_data_tap_16 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxeq_dfe_data_tap_2 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxeq_dfe_data_tap_3 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxeq_dfe_data_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxeq_dfe_data_tap_5 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxeq_dfe_data_tap_6 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxeq_dfe_data_tap_7 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxeq_dfe_data_tap_8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxeq_dfe_data_tap_9 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxeq_dfe_edge_tap_2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxeq_dfe_edge_tap_3 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxeq_dfe_edge_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxeq_iq_clk == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxeq_targ_0_hi == 9'd149
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxeq_targ_0_lo == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxeq_vga_gain == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxratewidth_pd_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxrpu_evup_delay_lut_entry2 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxrpu_evup_delay_lut_entry4 == 50'd78
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxrpu_evup_delay_lut_entry5 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxrpu_evup_delay_lut_entry6 == 50'd1406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_rxrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_select_lc_0_tx_path == UX3_SELECT_LC_0_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_select_lc_1_tx_path == UX3_SELECT_LC_1_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_select_lc_2_tx_path == UX3_SELECT_LC_2_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_select_lc_3_tx_path == UX3_SELECT_LC_3_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_select_lc_4_tx_path == UX3_SELECT_LC_4_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_sup_mode == UX3_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_afc_range == UX3_SYNTH_LC_0_AFC_RANGE_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_afc_refclk_count == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_dtr_prop_coeff == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_f_max_vco_hz == 40'd10500000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_f_min_vco_hz == 40'd8000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_fast_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_fast_tx_postdiv_counter == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_feed_forward_gain == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_fine_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_fine_int_coeff_tmp == 4'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_fine_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_fine_prop_coeff_tmp == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_kvcc_settle_maxcnt == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_m_counter == 9'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_med_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_med_tx_postdiv_counter == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_refclk_in_1us == 8'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_slow_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_slow_tx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_tdc_fine_res_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_tdc_target_count == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_0_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_afc_range == UX3_SYNTH_LC_1_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_feed_forward_gain == 8'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_m_counter == 9'd45
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_1_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_afc_range == UX3_SYNTH_LC_2_AFC_RANGE_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_dtr_int_coeff == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_feed_forward_gain == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_m_counter == 9'd27
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_2_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_afc_range == UX3_SYNTH_LC_3_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_feed_forward_gain == 8'd23
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_m_counter == 9'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_3_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_afc_range == UX3_SYNTH_LC_4_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_afc_refclk_count == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_dtr_int_coeff == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_feed_forward_gain == 8'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_fine_int_coeff == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_kvcc_settle_maxcnt == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_m_counter == 9'd216
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_med_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_refclk_in_1us == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_tdc_refclk_count == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_tdc_target_count == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_4_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_fast_bw_sel == UX3_SYNTH_LC_FAST_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_fast_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_fast_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_fast_primary_use == UX3_SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_fast_refclk_mux_select == UX3_SYNTH_LC_FAST_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_fast_refclk_type_select == UX3_SYNTH_LC_FAST_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_fast_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_fb_div_emb_mult_counter == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_l_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_l_counter_physical == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_med_bw_sel == UX3_SYNTH_LC_MED_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_med_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_med_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_med_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_med_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_med_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_med_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_med_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_med_primary_use == UX3_SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_med_refclk_mux_select == UX3_SYNTH_LC_MED_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_med_refclk_type_select == UX3_SYNTH_LC_MED_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_med_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_slow_bw_sel == UX3_SYNTH_LC_SLOW_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_slow_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_slow_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_slow_primary_use == UX3_SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_slow_refclk_mux_select == UX3_SYNTH_LC_SLOW_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_slow_refclk_type_select == UX3_SYNTH_LC_SLOW_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synth_lc_slow_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlc_0_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlc_0_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlc_0_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlc_0_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlc_1_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlc_1_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlc_1_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlc_1_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlc_2_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlc_2_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlc_2_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlc_2_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlc_3_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlc_3_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlc_3_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlc_3_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlc_4_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlc_4_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlc_4_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlc_4_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlc_dcdmeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlcfastratewidth_pd_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlcfastrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlcfastrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlcfastrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlcfastrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlcfastrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlcfastrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlcfastrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlcfastrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlcfastrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlcfastrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlcfastrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlcmedrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlcmedrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlcmedrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlcmedrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlcmedrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlcmedrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlcmedrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlcmedrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlcmedrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlcmedrpu_evup_delay_lut_entry7 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlcslowrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlcslowrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlcslowrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlcslowrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlcslowrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlcslowrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlcslowrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlcslowrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlcslowrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_synthlcslowrpu_evup_delay_lut_entry7 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tdc_refclk_count_divisor == 40'd850000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tdc_refclk_count_scratch == 40'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tdc_target_count_scratch == 40'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tx_bond_size == UX3_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tx_cal_dutymeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tx_i_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tx_i_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tx_i_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tx_master_bond_chnl == UX3_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tx_o_usr_clk_1_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tx_o_usr_clk_1_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tx_o_usr_clk_2_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tx_over_sample == UX3_TX_OVER_SAMPLE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tx_pll == UX3_TX_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tx_pll_bw_sel == UX3_TX_PLL_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tx_pll_is_downstream_pll == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tx_pll_refclk_mux_select == UX3_TX_PLL_REFCLK_MUX_SELECT_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tx_pll_refclk_select == UX3_TX_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tx_protocol == UX3_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tx_tuning_hint == UX3_TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tx_user_clk1_mux == UX3_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tx_user_clk2_mux == UX3_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tx_user_clk_slow_med_mux == UX3_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tx_which_lane_to_copy == UX3_TX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_tx_width == UX3_TX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_txeq_main_tap == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_txratewidth_rst_b0_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_txrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_txrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_txrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_txrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_txrpu_evup_delay_lut_entry2 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_txrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_txrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_txrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_txrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_txrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_txrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_txrx_channel_operation == UX3_TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_txrx_line_encoding_type == UX3_TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_txrx_xcvr_speed_bucket == UX3_TXRX_XCVR_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux3_vreg_loopen_maxcnt_scratch == 40'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux_quad_instance == UX_QUAD_INSTANCE_ONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.flux_top.ux_speed_grade == UX_SPEED_GRADE_DASH2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.all_enabled_refclks_always_running == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.all_ux_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.hard_all_ux_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.refclk0_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.refclk1_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.refclk2_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.refclk3_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.refclk4_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.refclk5_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.refclk6_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.refclk7_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.refclk8_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.refclk9_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_01_st_pt == 6'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_10_st_pt == 6'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_bonding_size_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_bonding_size_cfg_reserved_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ethernet_source == UX0_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_external_dpma_refclk_source == UX0_EXTERNAL_DPMA_REFCLK_SOURCE_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_flux_mode == UX0_FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_loopback_mode == UX0_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_q_dl_cfg_latpls_bw_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_q_dl_cfg_rst_rxbit_cntr_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_q_dl_cfg_sel_rxbit_adder_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_rx_adapt_mode == UX0_RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_rx_protocol == UX0_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_rx_rst_value_pre_user_mode_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_rx_tuning_hint == UX0_RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_standalone_core_clk_mux == UX0_STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_0_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_0_31 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_1_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_2_16to15 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_syspll0_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_syspll1_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_syspll2_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_tx_bond_size == UX0_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_tx_master_bond_chnl == UX0_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_tx_protocol == UX0_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_tx_rst_value_pre_user_mode_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_tx_tuning_hint == UX0_TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_tx_user_clk1_mux == UX0_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_tx_user_clk2_mux == UX0_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_tx_user_clk_slow_med_mux == UX0_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_tx_width == UX0_TX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_0_23 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_0_31 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_1_1 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_2_16to15 == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxeiosdetectstat_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxeq_clr_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxeq_precal_code_sel_lx_nt_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxeq_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxeq_static_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxeyediag_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxovrcdrlock2dataen_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxterm_hiz_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txbeacon_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txclkdivrate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txdetectrx_req_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txdrv_levn_lx_5to0 == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txdrv_levnm1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txdrv_levnp1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txdrv_levnp2_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txdrv_spare_l0_1to0 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txdrv_spare_l0_3to2 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txdrv_spare_l0_5to4 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txdrv_spare_l0_9to6 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txelecidle_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_0_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_0_31 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_1_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_2_16to15 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux0_vsr_mode == UX0_VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_01_st_pt == 6'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_10_st_pt == 6'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_bonding_size_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_bonding_size_cfg_reserved_attr == 25'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ethernet_source == UX1_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_external_dpma_refclk_source == UX1_EXTERNAL_DPMA_REFCLK_SOURCE_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_fec_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_flux_mode == UX1_FLUX_MODE_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_loopback_mode == UX1_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_q_dl_cfg_latpls_bw_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_q_dl_cfg_rst_rxbit_cntr_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_q_dl_cfg_sel_rxbit_adder_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_rx_adapt_mode == UX1_RX_ADAPT_MODE_STATIC_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_rx_protocol == UX1_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_rx_rst_value_pre_user_mode_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_rx_tuning_hint == UX1_RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_rx_user_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_standalone_core_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_standalone_core_clk_mux == UX1_STANDALONE_CORE_CLK_MUX_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_0_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_0_31 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_1_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_2_16to15 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_syspll0_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_syspll1_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_syspll2_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_tx_bond_size == UX1_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_tx_master_bond_chnl == UX1_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_tx_protocol == UX1_TX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_tx_rst_value_pre_user_mode_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_tx_tuning_hint == UX1_TX_TUNING_HINT_SDI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_tx_user_clk1_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_tx_user_clk1_mux == UX1_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_tx_user_clk2_mux == UX1_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_tx_user_clk_slow_med_mux == UX1_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_tx_width == UX1_TX_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_0_23 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_0_31 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_1_1 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_2_16to15 == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxeiosdetectstat_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxeq_clr_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxeq_precal_code_sel_lx_nt_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxeq_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxeq_static_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxeyediag_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxovrcdrlock2dataen_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxterm_hiz_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txbeacon_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txclkdivrate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txdetectrx_req_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txdrv_levn_lx_5to0 == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txdrv_levnm1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txdrv_levnp1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txdrv_levnp2_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txdrv_spare_l0_1to0 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txdrv_spare_l0_3to2 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txdrv_spare_l0_5to4 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txdrv_spare_l0_9to6 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txelecidle_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_0_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_0_31 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_1_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_2_16to15 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux1_vsr_mode == UX1_VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_01_st_pt == 6'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_10_st_pt == 6'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_bonding_size_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_bonding_size_cfg_reserved_attr == 25'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ethernet_source == UX2_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_external_dpma_refclk_source == UX2_EXTERNAL_DPMA_REFCLK_SOURCE_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_fec_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_flux_mode == UX2_FLUX_MODE_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_loopback_mode == UX2_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_q_dl_cfg_latpls_bw_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_q_dl_cfg_rst_rxbit_cntr_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_q_dl_cfg_sel_rxbit_adder_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_rx_adapt_mode == UX2_RX_ADAPT_MODE_UX_RX_ADAPT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_rx_protocol == UX2_RX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_rx_rst_value_pre_user_mode_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_rx_tuning_hint == UX2_RX_TUNING_HINT_SDI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_rx_user_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_standalone_core_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_standalone_core_clk_mux == UX2_STANDALONE_CORE_CLK_MUX_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_0_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_0_31 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_1_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_2_16to15 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_syspll0_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_syspll1_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_syspll2_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_tx_bond_size == UX2_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_tx_master_bond_chnl == UX2_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_tx_protocol == UX2_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_tx_rst_value_pre_user_mode_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_tx_tuning_hint == UX2_TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_tx_user_clk1_mux == UX2_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_tx_user_clk2_mux == UX2_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_tx_user_clk_slow_med_mux == UX2_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_tx_width == UX2_TX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_0_23 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_0_31 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_1_1 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_2_16to15 == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxeiosdetectstat_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxeq_clr_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxeq_precal_code_sel_lx_nt_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxeq_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxeq_static_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxeyediag_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxovrcdrlock2dataen_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxterm_hiz_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txbeacon_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txclkdivrate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txdetectrx_req_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txdrv_levn_lx_5to0 == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txdrv_levnm1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txdrv_levnp1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txdrv_levnp2_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txdrv_spare_l0_1to0 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txdrv_spare_l0_3to2 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txdrv_spare_l0_5to4 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txdrv_spare_l0_9to6 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txelecidle_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_0_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_0_31 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_1_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_2_16to15 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux2_vsr_mode == UX2_VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_01_st_pt == 6'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_10_st_pt == 6'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_bonding_size_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_bonding_size_cfg_reserved_attr == 25'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ethernet_source == UX3_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_external_dpma_refclk_source == UX3_EXTERNAL_DPMA_REFCLK_SOURCE_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_flux_mode == UX3_FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_loopback_mode == UX3_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_q_dl_cfg_latpls_bw_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_q_dl_cfg_rst_rxbit_cntr_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_q_dl_cfg_sel_rxbit_adder_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_rx_adapt_mode == UX3_RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_rx_protocol == UX3_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_rx_rst_value_pre_user_mode_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_rx_tuning_hint == UX3_RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_standalone_core_clk_mux == UX3_STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_0_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_0_31 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_1_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_2_16to15 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_syspll0_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_syspll1_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_syspll2_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_tx_bond_size == UX3_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_tx_master_bond_chnl == UX3_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_tx_protocol == UX3_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_tx_rst_value_pre_user_mode_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_tx_tuning_hint == UX3_TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_tx_user_clk1_mux == UX3_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_tx_user_clk2_mux == UX3_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_tx_user_clk_slow_med_mux == UX3_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_tx_width == UX3_TX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_0_23 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_0_31 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_1_1 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_2_16to15 == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxeiosdetectstat_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxeq_clr_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxeq_precal_code_sel_lx_nt_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxeq_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxeq_static_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxeyediag_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxovrcdrlock2dataen_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxterm_hiz_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txbeacon_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txclkdivrate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txdetectrx_req_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txdrv_levn_lx_5to0 == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txdrv_levnm1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txdrv_levnp1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txdrv_levnp2_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txdrv_spare_l0_1to0 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txdrv_spare_l0_3to2 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txdrv_spare_l0_5to4 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txdrv_spare_l0_9to6 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txelecidle_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_0_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_0_31 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_1_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_2_16to15 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux3_vsr_mode == UX3_VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_cpi_cmn2_st_pt == 11'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_cpi_lm_addr == 30'd589884
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_cpi_phy_addr == 30'd589888
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_cpi_reserved == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_cpi_seq_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_cpi_timer_max == 16'd500
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_end_pt == 11'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_flux_cpu_freq == 36'd250
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_bonding_ctrl_cfg_bonding_ctrl_l0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_bonding_ctrl_cfg_bonding_ctrl_l1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_bonding_ctrl_cfg_bonding_ctrl_l2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_bonding_ctrl_cfg_bonding_ctrl_l3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_bonding_ctrl_cfg_bonding_enable_l0_attr == BONDING_L0_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_bonding_ctrl_cfg_bonding_enable_l1_attr == BONDING_L1_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_bonding_ctrl_cfg_bonding_enable_l2_attr == BONDING_L2_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_bonding_ctrl_cfg_bonding_enable_l3_attr == BONDING_L3_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_ckmux_cpu_attr == CKMUX_CPU_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_cpi_seq_ctrl_cfg_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_datapath_loopback_en_cfg_datapath_loopback_en_l0_attr == LB_L0_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_datapath_loopback_en_cfg_datapath_loopback_en_l1_attr == LB_L1_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_datapath_loopback_en_cfg_datapath_loopback_en_l2_attr == LB_L2_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_datapath_loopback_en_cfg_datapath_loopback_en_l3_attr == LB_L3_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_a_cfg_clk_en_dfd_clk_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_a_cfg_dfd_clk_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_a_cfg_dfd_extrig_muxsel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_a_cfg_dfd_mux_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_a_cfg_dfd_rsvd_muxsel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_a_cfg_pattern_cntr_data_sel_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_a_cfg_pattern_cntr_inc_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_a_cfg_pattern_cntr_rst_b_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_b_cfg_apb_rdata_sel_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_b_cfg_rst_dfd_extrig_cntr_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_dl_ctrl_a_l2_cfg_ctrl_reserved_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_dl_ctrl_a_l3_cfg_ctrl_reserved_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_dpma_clk_mux_reserved_attr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e200_rxclk_en_l0_attr == E200_RXCLK_EN_L0_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e200_rxclk_en_l1_attr == E200_RXCLK_EN_L1_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e200_rxclk_en_l2_attr == E200_RXCLK_EN_L2_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e200_rxclk_en_l3_attr == E200_RXCLK_EN_L3_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e200_txclk_en_l0_attr == E200_TXCLK_EN_L0_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e200_txclk_en_l1_attr == E200_TXCLK_EN_L1_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e200_txclk_en_l2_attr == E200_TXCLK_EN_L2_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e200_txclk_en_l3_attr == E200_TXCLK_EN_L3_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_slow_med_l0_attr == E400_CKMUX_SLOW_MED_L0_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_slow_med_l1_attr == E400_CKMUX_SLOW_MED_L1_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_slow_med_l2_attr == E400_CKMUX_SLOW_MED_L2_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_slow_med_l3_attr == E400_CKMUX_SLOW_MED_L3_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser0_l0_attr == E400_CKMUX_TXUSER0_L0_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser0_l1_attr == E400_CKMUX_TXUSER0_L1_NON_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser0_l2_attr == E400_CKMUX_TXUSER0_L2_NON_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser0_l3_attr == E400_CKMUX_TXUSER0_L3_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser1_l0_attr == E400_CKMUX_TXUSER1_L0_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser1_l1_attr == E400_CKMUX_TXUSER1_L1_NON_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser1_l2_attr == E400_CKMUX_TXUSER1_L2_NON_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser1_l3_attr == E400_CKMUX_TXUSER1_L3_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser2_l0_attr == E400_CKMUX_TXUSER2_L0_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser2_l1_attr == E400_CKMUX_TXUSER2_L1_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser2_l2_attr == E400_CKMUX_TXUSER2_L2_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser2_l3_attr == E400_CKMUX_TXUSER2_L3_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_rxclk_en_l0_attr == E400_RXCLK_EN_L0_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_rxclk_en_l1_attr == E400_RXCLK_EN_L1_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_rxclk_en_l2_attr == E400_RXCLK_EN_L2_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_rxclk_en_l3_attr == E400_RXCLK_EN_L3_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_rxusrclk_en_l0_attr == E400_RXUSRCLK_EN_L0_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_rxusrclk_en_l1_attr == E400_RXUSRCLK_EN_L1_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_rxusrclk_en_l2_attr == E400_RXUSRCLK_EN_L2_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_rxusrclk_en_l3_attr == E400_RXUSRCLK_EN_L3_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_txclk_en_l0_attr == E400_TXCLK_EN_L0_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_txclk_en_l1_attr == E400_TXCLK_EN_L1_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_txclk_en_l2_attr == E400_TXCLK_EN_L2_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_txclk_en_l3_attr == E400_TXCLK_EN_L3_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk0_en_l0_attr == E400_USRCLK0_EN_L0_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk0_en_l1_attr == E400_USRCLK0_EN_L1_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk0_en_l2_attr == E400_USRCLK0_EN_L2_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk0_en_l3_attr == E400_USRCLK0_EN_L3_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk1_en_l0_attr == E400_USRCLK1_EN_L0_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk1_en_l1_attr == E400_USRCLK1_EN_L1_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk1_en_l2_attr == E400_USRCLK1_EN_L2_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk1_en_l3_attr == E400_USRCLK1_EN_L3_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk2_en_l0_attr == E400_USRCLK2_EN_L0_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk2_en_l1_attr == E400_USRCLK2_EN_L1_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk2_en_l2_attr == E400_USRCLK2_EN_L2_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk2_en_l3_attr == E400_USRCLK2_EN_L3_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e_rx_dp_pipe_l0_attr == E_RX_DP_PIPE_L0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e_rx_dp_pipe_l1_attr == E_RX_DP_PIPE_L1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e_rx_dp_pipe_l2_attr == E_RX_DP_PIPE_L2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e_rx_dp_pipe_l3_attr == E_RX_DP_PIPE_L3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e_tx_dp_pipe_l0_attr == E_TX_DP_PIPE_L0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e_tx_dp_pipe_l1_attr == E_TX_DP_PIPE_L1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e_tx_dp_pipe_l2_attr == E_TX_DP_PIPE_L2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_e_tx_dp_pipe_l3_attr == E_TX_DP_PIPE_L3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_fw_load_base_l0_cfg_value_attr == 32'd277792
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_fw_load_base_l1_cfg_value_attr == 32'd310560
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_fw_load_base_l2_cfg_value_attr == 32'd343328
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_fw_load_base_l3_cfg_value_attr == 32'd376096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_i_pll0_hz == 36'd250000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_i_pll1_hz == 36'd250000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_i_pll2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_indirect_access_ctrl_cfg_fw_load_disable_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_indirect_access_ctrl_cfg_fw_load_mode_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_indirect_access_ctrl_cfg_mapped_base_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_indirect_access_ctrl_cfg_reserved_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_indirect_access_ctrl_cfg_unmapped_base_attr == 18'd16384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_mode_ctrl_cfg_func_mode_l0_attr == FUNC_MODE_E400_L0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_mode_ctrl_cfg_func_mode_l1_attr == FUNC_MODE_E400_L1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_mode_ctrl_cfg_func_mode_l2_attr == FUNC_MODE_E400_L2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_mode_ctrl_cfg_func_mode_l3_attr == FUNC_MODE_E400_L3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_medclk_en_l0_attr == PCIE_MEDCLK_EN_L0_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_medclk_en_l1_attr == PCIE_MEDCLK_EN_L1_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_medclk_en_l2_attr == PCIE_MEDCLK_EN_L2_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_medclk_en_l3_attr == PCIE_MEDCLK_EN_L3_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_pclk_en_l0_attr == PCIE_PCLK_EN_L0_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_pclk_en_l1_attr == PCIE_PCLK_EN_L1_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_pclk_en_l2_attr == PCIE_PCLK_EN_L2_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_pclk_en_l3_attr == PCIE_PCLK_EN_L3_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_refclk_en_l0_attr == PCIE_REFCLK_EN_L0_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_refclk_en_l1_attr == PCIE_REFCLK_EN_L1_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_refclk_en_l2_attr == PCIE_REFCLK_EN_L2_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_refclk_en_l3_attr == PCIE_REFCLK_EN_L3_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_rxclk_en_l0_attr == PCIE_RXCLK_EN_L0_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_rxclk_en_l1_attr == PCIE_RXCLK_EN_L1_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_rxclk_en_l2_attr == PCIE_RXCLK_EN_L2_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_rxclk_en_l3_attr == PCIE_RXCLK_EN_L3_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_slowclk_en_l0_attr == PCIE_SLOWCLK_EN_L0_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_slowclk_en_l1_attr == PCIE_SLOWCLK_EN_L1_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_slowclk_en_l2_attr == PCIE_SLOWCLK_EN_L2_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_slowclk_en_l3_attr == PCIE_SLOWCLK_EN_L3_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_reserved0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_10_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_11_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_12_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_13_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_14_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_15_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_16_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_17_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_18_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_19_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_20_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_21_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_22_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_23_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_24_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_25_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_26_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_27_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_28_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_29_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_30_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_31_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_32_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_33_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_34_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_35_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_36_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_37_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_38_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_39_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_40_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_41_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_42_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_43_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_44_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_45_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_46_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_47_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_48_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_49_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_50_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_51_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_52_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_53_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_54_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_55_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_56_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_57_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_58_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_59_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_5_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_60_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_61_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_62_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_63_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_6_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_7_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_8_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_9_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_ctrl_0_cfg_restart_seq_sm_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_ctrl_0_cfg_skip_rd_seq_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_ctrl_1_cfg_seqen_0to31_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_ctrl_2_cfg_seqen_32to63_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_ctrl_3_cfg_seq_rdwrb_0to31_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_ctrl_4_cfg_seq_rdwrb_32to63_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_0_attr == 32'd32874599
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_10_attr == 32'd41731
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_11_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_12_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_13_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_14_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_15_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_16_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_17_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_18_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_19_attr == 32'd41200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_1_attr == 32'd41138
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_20_attr == 32'd41456
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_21_attr == 32'd41712
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_22_attr == 32'd41968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_23_attr == 32'd41060
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_24_attr == 32'd41316
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_25_attr == 32'd41572
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_26_attr == 32'd41828
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_27_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_28_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_29_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_2_attr == 32'd134258864
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_30_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_31_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_32_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_33_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_34_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_35_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_36_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_37_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_38_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_39_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_3_attr == 32'd16359439
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_40_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_41_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_42_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_43_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_44_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_45_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_46_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_47_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_48_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_49_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_4_attr == 32'd40963
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_50_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_51_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_52_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_53_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_54_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_55_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_56_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_57_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_58_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_59_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_5_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_60_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_61_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_62_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_63_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_6_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_7_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_8_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_9_attr == 32'd16360207
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_0_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_10_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_11_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_12_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_13_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_14_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_15_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_16_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_17_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_18_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_19_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_1_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_20_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_21_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_22_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_23_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_24_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_25_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_26_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_27_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_28_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_29_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_2_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_30_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_31_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_32_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_33_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_34_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_35_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_36_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_37_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_38_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_39_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_3_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_40_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_41_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_42_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_43_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_44_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_45_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_46_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_47_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_48_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_49_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_4_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_50_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_51_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_52_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_53_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_54_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_55_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_56_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_57_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_58_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_59_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_5_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_60_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_61_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_62_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_63_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_6_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_7_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_8_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_9_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_quad_instance == UX_QUAD_INSTANCE_ONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_1.gdr_ux_quad_avmm_cfgcsr.ux_rst_value_pre_user_mode_reserved_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.all_enabled_refclks_always_running == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.all_ux_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.bot_f_fastest_reconfig_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.bot_refclk_reconfig_span == BOT_REFCLK_RECONFIG_SPAN_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.bot_syspll_refclk_output_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ch1_ch0_master_pll_pair_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ch3_ch2_master_pll_pair_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.clkrx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.f_avmm_clk_hz == 40'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.f_bot_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.f_bot_syspll_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.f_fastest_reconfig_refclk_global_refclk_0_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.f_fastest_reconfig_refclk_global_refclk_1_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.f_fastest_reconfig_refclk_global_refclk_2_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.f_fastest_reconfig_refclk_global_refclk_3_hz == 40'd800000001
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.f_fastest_reconfig_refclk_regional_refclk_0_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.f_fastest_reconfig_refclk_regional_refclk_1_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.f_global_refclk_0_bot_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.f_global_refclk_0_bot_right_top_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.f_global_refclk_1_bot_right_top_left_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.f_global_refclk_1_top_right_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.f_global_refclk_2_bot_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.f_global_refclk_2_bot_right_top_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.f_global_refclk_3_bot_right_top_left_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.f_global_refclk_3_top_right_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.f_local_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.f_regional_refclk_0_bot_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.f_regional_refclk_0_bot_right_top_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.f_regional_refclk_1_bot_right_top_left_hz == 40'd800000001
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.f_regional_refclk_1_top_right_hz == 40'd800000001
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.f_top_refclk_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.f_top_syspll_refclk_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.global_refclk_0_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.global_refclk_0_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.global_refclk_1_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.global_refclk_1_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.global_refclk_2_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.global_refclk_2_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.global_refclk_3_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.global_refclk_3_right_adjacent_active == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.hard_all_ux_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_avmm == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_bot_clkrx_base == POWERMODE_AC_MODE_BOT_CLKRX_BASE_NON_PIN_PRIMARY_DRIVER_HIGH_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_bot_cmos_driver == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_flux == POWERMODE_AC_MODE_FLUX_FLUX_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_global_refclk_0_bot == POWERMODE_AC_MODE_GLOBAL_REFCLK_0_BOT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_global_refclk_0_top == POWERMODE_AC_MODE_GLOBAL_REFCLK_0_TOP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_global_refclk_1_bot == POWERMODE_AC_MODE_GLOBAL_REFCLK_1_BOT_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_global_refclk_1_top == POWERMODE_AC_MODE_GLOBAL_REFCLK_1_TOP_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_global_refclk_2_bot == POWERMODE_AC_MODE_GLOBAL_REFCLK_2_BOT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_global_refclk_2_top == POWERMODE_AC_MODE_GLOBAL_REFCLK_2_TOP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_global_refclk_3_bot == POWERMODE_AC_MODE_GLOBAL_REFCLK_3_BOT_HIGH_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_global_refclk_3_top == POWERMODE_AC_MODE_GLOBAL_REFCLK_3_TOP_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_regional_refclk_0_bot == POWERMODE_AC_MODE_REGIONAL_REFCLK_0_BOT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_regional_refclk_0_top == POWERMODE_AC_MODE_REGIONAL_REFCLK_0_TOP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_regional_refclk_1_bot == POWERMODE_AC_MODE_REGIONAL_REFCLK_1_BOT_HIGH_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_regional_refclk_1_top == POWERMODE_AC_MODE_REGIONAL_REFCLK_1_TOP_HIGH_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_rx_ux0 == UX0_POWERMODE_AC_MODE_RX_NRZ_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_rx_ux1 == UX1_POWERMODE_AC_MODE_RX_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_rx_ux2 == UX2_POWERMODE_AC_MODE_RX_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_rx_ux3 == UX3_POWERMODE_AC_MODE_RX_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_synth_lc_fast_ux0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_synth_lc_fast_ux1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_synth_lc_fast_ux2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_synth_lc_fast_ux3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_synth_lc_med_ux0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_synth_lc_med_ux1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_synth_lc_med_ux2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_synth_lc_med_ux3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_synth_lc_slow_ux0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_synth_lc_slow_ux1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_synth_lc_slow_ux2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_synth_lc_slow_ux3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_top_clkrx_base == POWERMODE_AC_MODE_TOP_CLKRX_BASE_PIN_TO_CLKRX_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_top_cmos_driver == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_tx_ux0 == UX0_POWERMODE_AC_MODE_TX_NRZ_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_tx_ux1 == UX1_POWERMODE_AC_MODE_TX_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_tx_ux2 == UX2_POWERMODE_AC_MODE_TX_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_ac_mode_tx_ux3 == UX3_POWERMODE_AC_MODE_TX_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_avmm == 40'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_bot_clkrx_base == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_bot_cmos_driver == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_flux == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_global_refclk_0_bot == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_global_refclk_0_top == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_global_refclk_1_bot == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_global_refclk_1_top == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_global_refclk_2_bot == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_global_refclk_2_top == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_global_refclk_3_bot == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_global_refclk_3_top == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_regional_refclk_0_bot == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_regional_refclk_0_top == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_regional_refclk_1_bot == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_regional_refclk_1_top == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_rx_parallel_ux0 == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_rx_parallel_ux1 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_rx_parallel_ux2 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_rx_parallel_ux3 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_rx_ux0 == 36'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_rx_ux1 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_rx_ux2 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_rx_ux3 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_synth_lc_fast_ux0 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_synth_lc_fast_ux1 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_synth_lc_fast_ux2 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_synth_lc_fast_ux3 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_synth_lc_med_ux0 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_synth_lc_med_ux1 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_synth_lc_med_ux2 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_synth_lc_med_ux3 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_synth_lc_slow_ux0 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_synth_lc_slow_ux1 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_synth_lc_slow_ux2 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_synth_lc_slow_ux3 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_top_clkrx_base == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_top_cmos_driver == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_tx_parallel_ux0 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_tx_parallel_ux1 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_tx_parallel_ux2 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_tx_parallel_ux3 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_tx_ux0 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_tx_ux1 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_tx_ux2 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.powermode_freq_hz_tx_ux3 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.refclk0_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.refclk1_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.refclk2_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.refclk3_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.refclk4_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.refclk5_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.refclk6_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.refclk7_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.refclk8_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.refclk9_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.regional_refclk_0_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.regional_refclk_0_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.regional_refclk_1_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.regional_refclk_1_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.top_f_fastest_reconfig_refclk_hz == 40'd800000001
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.top_refclk_reconfig_span == TOP_REFCLK_RECONFIG_SPAN_TWO_RIGHT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.top_syspll_refclk_output_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_cdr_bw_sel == UX0_CDR_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_cdr_f_mod_hz == 40'd990000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_cdr_f_out_hz == 40'd5940000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_cdr_f_pfd_hz == 40'd29700000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_cdr_f_postdiv_hz == 40'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_cdr_f_ref_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_cdr_f_vco_hz == 40'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_cdr_is_cascaded == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_cdr_l_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_cdr_m_counter == 9'd200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_cdr_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_cdr_postdiv_counter == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_cdr_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_cdr_ppm_driftcount == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_cdr_refclk_mux_select == UX0_CDR_REFCLK_MUX_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_cdr_refclk_select == UX0_CDR_REFCLK_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_cmn_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_core_pll == UX0_CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_core_pll_refclk_select == UX0_CORE_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_dpma_refclk_source == UX0_DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_duplex_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_enable_port_control_of_cdr_ltr_ltd == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ethernet_source == UX0_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_expose_pcie_gen1_gen6_critical_signals == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_external_dpma_refclk_source == UX0_EXTERNAL_DPMA_REFCLK_SOURCE_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_fec_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_flux_mode == UX0_FLUX_MODE_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_lane_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_loopback_mode == UX0_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_master_sup_mode == UX0_MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_prbs_gen_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_primary_use == UX0_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ref_clk_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_rx_adapt_mode == UX0_RX_ADAPT_MODE_UX_RX_ADAPT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_rx_bond_size == UX0_RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_rx_datarate == 40'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_rx_line_rate_bps == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_rx_master_bond_chnl == UX0_RX_MASTER_BOND_CHNL_CH15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_rx_o_clk_e2_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_rx_o_clk_e4_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_rx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_rx_o_usr_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_rx_o_usr_clk_e4_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_rx_onchip_termination == UX0_RX_ONCHIP_TERMINATION_R_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_rx_protocol == UX0_RX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_rx_term_mode_select == UX0_RX_TERM_MODE_SELECT_DIFFERENTIAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_rx_tuning_hint == UX0_RX_TUNING_HINT_SDI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_rx_user_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_rx_width == UX0_RX_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_rxeq_vga_gain == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_standalone_core_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_standalone_core_clk_mux == UX0_STANDALONE_CORE_CLK_MUX_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sup_mode == UX0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sv_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sv_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sv_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sv_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sv_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sv_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sv_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sv_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sv_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sv_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sv_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sv_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sv_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sv_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sv_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sv_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_sv_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_0_feed_forward_gain == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_0_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_fast_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_fast_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_fast_primary_use == UX0_SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_fb_div_emb_mult_counter == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_fb_div_n_frac_mode == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_med_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_med_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_med_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_med_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_med_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_med_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_med_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_med_primary_use == UX0_SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_slow_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_slow_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_slow_primary_use == UX0_SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_syspll0_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_syspll1_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_syspll2_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_tx_bond_size == UX0_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_tx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_tx_i_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_tx_i_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_tx_i_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_tx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_tx_master_bond_chnl == UX0_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_tx_o_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_tx_o_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_tx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_tx_o_usr_clk_1_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_tx_o_usr_clk_1_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_tx_o_usr_clk_2_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_tx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_tx_pll == UX0_TX_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_tx_pll_bw_sel == UX0_TX_PLL_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_tx_pll_refclk_mux_select == UX0_TX_PLL_REFCLK_MUX_SELECT_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_tx_pll_refclk_select == UX0_TX_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_tx_protocol == UX0_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_tx_protocol_hard_pcie_lowloss == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_tx_tuning_hint == UX0_TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_tx_user_clk1_mux == UX0_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_tx_user_clk2_mux == UX0_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_tx_user_clk_slow_med_mux == UX0_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_tx_width == UX0_TX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_txeq_main_tap == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_txrx_channel_operation == UX0_TXRX_CHANNEL_OPERATION_DUAL_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_txrx_line_encoding_type == UX0_TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_txrx_xcvr_speed_bucket == UX0_TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_en_rxbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_en_rxeiosdetectstat_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_en_rxeq_clr_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_en_rxeq_precal_code_sel_lx_nt_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_en_rxeq_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_en_rxeq_static_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_en_rxeyediag_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_en_rxovrcdrlock2dataen_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_en_rxpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_en_rxrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_en_rxterm_hiz_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_en_rxwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_en_txbeacon_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_en_txbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_en_txclkdivrate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_en_txdetectrx_req_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_en_txdrv_levn_lx_5to0 == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_en_txdrv_levnm1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_en_txdrv_levnp1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_en_txdrv_levnp2_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_en_txdrv_spare_l0_1to0 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_en_txdrv_spare_l0_3to2 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_en_txdrv_spare_l0_5to4 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_en_txdrv_spare_l0_9to6 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_en_txelecidle_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_en_txpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_en_txrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_en_txwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_ovr_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_ovr_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_ovr_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_ovr_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_ovr_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_ovr_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_ovr_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_ovr_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_ovr_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_ovr_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_ovr_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_ovr_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_ovr_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_ovr_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_ovr_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_ovr_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_ur_ovr_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux0_vsr_mode == UX0_VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_cdr_bw_sel == UX1_CDR_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_cdr_f_mod_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_cdr_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_cdr_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_cdr_f_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_cdr_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_cdr_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_cdr_is_cascaded == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_cdr_l_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_cdr_m_counter == 9'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_cdr_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_cdr_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_cdr_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_cdr_ppm_driftcount == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_cdr_refclk_mux_select == UX1_CDR_REFCLK_MUX_SELECT_REGIONAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_cdr_refclk_select == UX1_CDR_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_cmn_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_core_pll == UX1_CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_core_pll_refclk_select == UX1_CORE_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_dpma_refclk_source == UX1_DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_duplex_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_enable_port_control_of_cdr_ltr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ethernet_source == UX1_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_expose_pcie_gen1_gen6_critical_signals == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_external_dpma_refclk_source == UX1_EXTERNAL_DPMA_REFCLK_SOURCE_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_flux_mode == UX1_FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_lane_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_loopback_mode == UX1_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_master_sup_mode == UX1_MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_primary_use == UX1_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ref_clk_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_rx_adapt_mode == UX1_RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_rx_bond_size == UX1_RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_rx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_rx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_rx_master_bond_chnl == UX1_RX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_rx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_rx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_rx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_rx_o_usr_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_rx_o_usr_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_rx_onchip_termination == UX1_RX_ONCHIP_TERMINATION_R_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_rx_protocol == UX1_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_rx_term_mode_select == UX1_RX_TERM_MODE_SELECT_GROUNDED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_rx_tuning_hint == UX1_RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_rx_width == UX1_RX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_rxeq_vga_gain == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_standalone_core_clk_mux == UX1_STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sup_mode == UX1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sv_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sv_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sv_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sv_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sv_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sv_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sv_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sv_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sv_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sv_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sv_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sv_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sv_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sv_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sv_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sv_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_sv_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_0_feed_forward_gain == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_0_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_fast_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_fast_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_fast_primary_use == UX1_SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_fb_div_emb_mult_counter == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_med_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_med_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_med_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_med_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_med_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_med_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_med_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_med_primary_use == UX1_SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_slow_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_slow_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_slow_primary_use == UX1_SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_syspll0_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_syspll1_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_syspll2_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_tx_bond_size == UX1_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_tx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_tx_i_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_tx_i_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_tx_i_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_tx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_tx_master_bond_chnl == UX1_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_tx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_tx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_tx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_tx_o_usr_clk_1_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_tx_o_usr_clk_1_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_tx_o_usr_clk_2_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_tx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_tx_pll == UX1_TX_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_tx_pll_bw_sel == UX1_TX_PLL_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_tx_pll_refclk_mux_select == UX1_TX_PLL_REFCLK_MUX_SELECT_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_tx_pll_refclk_select == UX1_TX_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_tx_protocol == UX1_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_tx_tuning_hint == UX1_TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_tx_user_clk1_mux == UX1_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_tx_user_clk2_mux == UX1_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_tx_user_clk_slow_med_mux == UX1_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_tx_width == UX1_TX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_txeq_main_tap == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_txrx_channel_operation == UX1_TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_txrx_line_encoding_type == UX1_TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_txrx_xcvr_speed_bucket == UX1_TXRX_XCVR_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_en_rxbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_en_rxeiosdetectstat_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_en_rxeq_clr_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_en_rxeq_precal_code_sel_lx_nt_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_en_rxeq_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_en_rxeq_static_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_en_rxeyediag_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_en_rxovrcdrlock2dataen_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_en_rxpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_en_rxrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_en_rxterm_hiz_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_en_rxwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_en_txbeacon_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_en_txbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_en_txclkdivrate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_en_txdetectrx_req_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_en_txdrv_levn_lx_5to0 == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_en_txdrv_levnm1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_en_txdrv_levnp1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_en_txdrv_levnp2_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_en_txdrv_spare_l0_1to0 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_en_txdrv_spare_l0_3to2 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_en_txdrv_spare_l0_5to4 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_en_txdrv_spare_l0_9to6 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_en_txelecidle_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_en_txpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_en_txrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_en_txwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_ovr_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_ovr_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_ovr_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_ovr_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_ovr_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_ovr_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_ovr_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_ovr_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_ovr_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_ovr_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_ovr_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_ovr_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_ovr_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_ovr_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_ovr_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_ovr_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_ur_ovr_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux1_vsr_mode == UX1_VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_cdr_bw_sel == UX2_CDR_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_cdr_f_mod_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_cdr_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_cdr_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_cdr_f_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_cdr_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_cdr_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_cdr_is_cascaded == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_cdr_l_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_cdr_m_counter == 9'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_cdr_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_cdr_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_cdr_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_cdr_ppm_driftcount == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_cdr_refclk_mux_select == UX2_CDR_REFCLK_MUX_SELECT_REGIONAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_cdr_refclk_select == UX2_CDR_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_cmn_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_core_pll == UX2_CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_core_pll_refclk_select == UX2_CORE_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_dpma_refclk_source == UX2_DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_duplex_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_enable_port_control_of_cdr_ltr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ethernet_source == UX2_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_expose_pcie_gen1_gen6_critical_signals == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_external_dpma_refclk_source == UX2_EXTERNAL_DPMA_REFCLK_SOURCE_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_flux_mode == UX2_FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_lane_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_loopback_mode == UX2_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_master_sup_mode == UX2_MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_primary_use == UX2_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ref_clk_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_rx_adapt_mode == UX2_RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_rx_bond_size == UX2_RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_rx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_rx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_rx_master_bond_chnl == UX2_RX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_rx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_rx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_rx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_rx_o_usr_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_rx_o_usr_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_rx_onchip_termination == UX2_RX_ONCHIP_TERMINATION_R_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_rx_protocol == UX2_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_rx_term_mode_select == UX2_RX_TERM_MODE_SELECT_GROUNDED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_rx_tuning_hint == UX2_RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_rx_width == UX2_RX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_rxeq_vga_gain == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_standalone_core_clk_mux == UX2_STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sup_mode == UX2_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sv_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sv_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sv_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sv_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sv_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sv_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sv_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sv_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sv_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sv_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sv_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sv_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sv_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sv_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sv_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sv_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_sv_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_0_feed_forward_gain == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_0_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_fast_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_fast_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_fast_primary_use == UX2_SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_fb_div_emb_mult_counter == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_med_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_med_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_med_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_med_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_med_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_med_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_med_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_med_primary_use == UX2_SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_slow_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_slow_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_slow_primary_use == UX2_SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_syspll0_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_syspll1_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_syspll2_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_tx_bond_size == UX2_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_tx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_tx_i_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_tx_i_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_tx_i_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_tx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_tx_master_bond_chnl == UX2_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_tx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_tx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_tx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_tx_o_usr_clk_1_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_tx_o_usr_clk_1_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_tx_o_usr_clk_2_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_tx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_tx_pll == UX2_TX_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_tx_pll_bw_sel == UX2_TX_PLL_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_tx_pll_refclk_mux_select == UX2_TX_PLL_REFCLK_MUX_SELECT_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_tx_pll_refclk_select == UX2_TX_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_tx_protocol == UX2_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_tx_tuning_hint == UX2_TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_tx_user_clk1_mux == UX2_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_tx_user_clk2_mux == UX2_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_tx_user_clk_slow_med_mux == UX2_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_tx_width == UX2_TX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_txeq_main_tap == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_txrx_channel_operation == UX2_TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_txrx_line_encoding_type == UX2_TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_txrx_xcvr_speed_bucket == UX2_TXRX_XCVR_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_en_rxbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_en_rxeiosdetectstat_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_en_rxeq_clr_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_en_rxeq_precal_code_sel_lx_nt_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_en_rxeq_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_en_rxeq_static_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_en_rxeyediag_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_en_rxovrcdrlock2dataen_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_en_rxpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_en_rxrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_en_rxterm_hiz_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_en_rxwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_en_txbeacon_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_en_txbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_en_txclkdivrate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_en_txdetectrx_req_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_en_txdrv_levn_lx_5to0 == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_en_txdrv_levnm1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_en_txdrv_levnp1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_en_txdrv_levnp2_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_en_txdrv_spare_l0_1to0 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_en_txdrv_spare_l0_3to2 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_en_txdrv_spare_l0_5to4 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_en_txdrv_spare_l0_9to6 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_en_txelecidle_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_en_txpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_en_txrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_en_txwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_ovr_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_ovr_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_ovr_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_ovr_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_ovr_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_ovr_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_ovr_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_ovr_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_ovr_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_ovr_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_ovr_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_ovr_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_ovr_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_ovr_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_ovr_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_ovr_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_ur_ovr_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux2_vsr_mode == UX2_VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_cdr_bw_sel == UX3_CDR_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_cdr_f_mod_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_cdr_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_cdr_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_cdr_f_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_cdr_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_cdr_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_cdr_is_cascaded == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_cdr_l_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_cdr_m_counter == 9'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_cdr_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_cdr_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_cdr_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_cdr_ppm_driftcount == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_cdr_refclk_mux_select == UX3_CDR_REFCLK_MUX_SELECT_REGIONAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_cdr_refclk_select == UX3_CDR_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_cmn_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_core_pll == UX3_CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_core_pll_refclk_select == UX3_CORE_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_dpma_refclk_source == UX3_DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_duplex_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_enable_port_control_of_cdr_ltr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ethernet_source == UX3_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_expose_pcie_gen1_gen6_critical_signals == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_external_dpma_refclk_source == UX3_EXTERNAL_DPMA_REFCLK_SOURCE_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_flux_mode == UX3_FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_lane_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_loopback_mode == UX3_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_master_sup_mode == UX3_MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_primary_use == UX3_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ref_clk_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_rx_adapt_mode == UX3_RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_rx_bond_size == UX3_RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_rx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_rx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_rx_master_bond_chnl == UX3_RX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_rx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_rx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_rx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_rx_o_usr_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_rx_o_usr_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_rx_onchip_termination == UX3_RX_ONCHIP_TERMINATION_R_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_rx_protocol == UX3_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_rx_term_mode_select == UX3_RX_TERM_MODE_SELECT_GROUNDED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_rx_tuning_hint == UX3_RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_rx_width == UX3_RX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_rxeq_vga_gain == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_standalone_core_clk_mux == UX3_STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sup_mode == UX3_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sv_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sv_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sv_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sv_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sv_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sv_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sv_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sv_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sv_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sv_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sv_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sv_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sv_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sv_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sv_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sv_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_sv_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_0_feed_forward_gain == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_0_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_fast_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_fast_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_fast_primary_use == UX3_SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_fb_div_emb_mult_counter == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_med_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_med_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_med_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_med_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_med_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_med_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_med_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_med_primary_use == UX3_SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_slow_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_slow_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_slow_primary_use == UX3_SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_syspll0_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_syspll1_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_syspll2_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_tx_bond_size == UX3_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_tx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_tx_i_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_tx_i_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_tx_i_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_tx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_tx_master_bond_chnl == UX3_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_tx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_tx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_tx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_tx_o_usr_clk_1_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_tx_o_usr_clk_1_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_tx_o_usr_clk_2_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_tx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_tx_pll == UX3_TX_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_tx_pll_bw_sel == UX3_TX_PLL_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_tx_pll_refclk_mux_select == UX3_TX_PLL_REFCLK_MUX_SELECT_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_tx_pll_refclk_select == UX3_TX_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_tx_protocol == UX3_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_tx_tuning_hint == UX3_TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_tx_user_clk1_mux == UX3_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_tx_user_clk2_mux == UX3_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_tx_user_clk_slow_med_mux == UX3_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_tx_width == UX3_TX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_txeq_main_tap == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_txrx_channel_operation == UX3_TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_txrx_line_encoding_type == UX3_TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_txrx_xcvr_speed_bucket == UX3_TXRX_XCVR_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_en_rxbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_en_rxeiosdetectstat_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_en_rxeq_clr_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_en_rxeq_precal_code_sel_lx_nt_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_en_rxeq_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_en_rxeq_static_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_en_rxeyediag_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_en_rxovrcdrlock2dataen_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_en_rxpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_en_rxrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_en_rxterm_hiz_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_en_rxwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_en_txbeacon_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_en_txbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_en_txclkdivrate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_en_txdetectrx_req_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_en_txdrv_levn_lx_5to0 == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_en_txdrv_levnm1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_en_txdrv_levnp1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_en_txdrv_levnp2_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_en_txdrv_spare_l0_1to0 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_en_txdrv_spare_l0_3to2 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_en_txdrv_spare_l0_5to4 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_en_txdrv_spare_l0_9to6 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_en_txelecidle_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_en_txpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_en_txrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_en_txwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_ovr_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_ovr_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_ovr_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_ovr_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_ovr_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_ovr_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_ovr_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_ovr_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_ovr_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_ovr_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_ovr_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_ovr_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_ovr_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_ovr_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_ovr_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_ovr_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_ur_ovr_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux3_vsr_mode == UX3_VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK1_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux_q_ckmux_cpu_attr == CKMUX_CPU_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux_q_i_pll0_hz == 36'd250000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux_q_i_pll1_hz == 36'd250000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux_q_i_pll2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux_quad_instance == UX_QUAD_INSTANCE_TWO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.ux_speed_grade == UX_SPEED_GRADE_DASH2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.all_ux_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.bot_f_fastest_reconfig_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.bot_refclk_reconfig_span == BOT_REFCLK_RECONFIG_SPAN_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.bot_syspll_refclk_output_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.cdrdiv_offchip_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ch1_ch0_master_pll_pair_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ch3_ch2_master_pll_pair_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.clkrx_bot_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.clkrx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.clkrx_top_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_bot_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_bot_syspll_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_ch1_ch0_master_pll_pair_cascade_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_ch3_ch2_master_pll_pair_cascade_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_fastest_reconfig_refclk_global_refclk_0_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_fastest_reconfig_refclk_global_refclk_1_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_fastest_reconfig_refclk_global_refclk_2_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_fastest_reconfig_refclk_global_refclk_3_hz == 40'd800000001
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_fastest_reconfig_refclk_regional_refclk_0_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_fastest_reconfig_refclk_regional_refclk_1_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_full_quad_master_pll_cascade_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_global_refclk_0_bot_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_global_refclk_0_bot_right_top_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_global_refclk_0_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_global_refclk_0_top_right_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_global_refclk_1_bot_left_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_global_refclk_1_bot_right_top_left_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_global_refclk_1_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_global_refclk_1_top_right_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_global_refclk_2_bot_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_global_refclk_2_bot_right_top_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_global_refclk_2_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_global_refclk_2_top_right_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_global_refclk_3_bot_left_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_global_refclk_3_bot_right_top_left_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_global_refclk_3_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_global_refclk_3_top_right_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_local_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_regional_refclk_0_bot_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_regional_refclk_0_bot_right_top_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_regional_refclk_0_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_regional_refclk_0_top_right_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_regional_refclk_1_bot_left_hz == 40'd800000001
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_regional_refclk_1_bot_right_top_left_hz == 40'd800000001
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_regional_refclk_1_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_regional_refclk_1_top_right_hz == 40'd800000001
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_regional_refclk_2_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_regional_refclk_3_hz == 40'd800000001
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_top_refclk_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.f_top_syspll_refclk_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.fabric_iram_fabric_iram_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.global_refclk_0_bot_control == GLOBAL_REFCLK_0_BOT_CONTROL_ENABLE_T2R_B2L_NO_PASS_THRU
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.global_refclk_0_bot_power_mode == GLOBAL_REFCLK_0_BOT_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.global_refclk_0_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.global_refclk_0_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.global_refclk_0_top_control == GLOBAL_REFCLK_0_TOP_CONTROL_ENABLE_T2R_B2L_NO_PASS_THRU
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.global_refclk_0_top_power_mode == GLOBAL_REFCLK_0_TOP_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.global_refclk_1_bot_control == GLOBAL_REFCLK_1_BOT_CONTROL_ENABLE_R2L_L2B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.global_refclk_1_bot_power_mode == GLOBAL_REFCLK_1_BOT_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.global_refclk_1_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.global_refclk_1_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.global_refclk_1_top_control == GLOBAL_REFCLK_1_TOP_CONTROL_ENABLE_R2L_L2B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.global_refclk_1_top_power_mode == GLOBAL_REFCLK_1_TOP_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.global_refclk_2_bot_control == GLOBAL_REFCLK_2_BOT_CONTROL_ENABLE_T2R_B2L_NO_PASS_THRU
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.global_refclk_2_bot_power_mode == GLOBAL_REFCLK_2_BOT_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.global_refclk_2_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.global_refclk_2_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.global_refclk_2_top_control == GLOBAL_REFCLK_2_TOP_CONTROL_ENABLE_T2R_B2L_NO_PASS_THRU
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.global_refclk_2_top_power_mode == GLOBAL_REFCLK_2_TOP_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.global_refclk_3_bot_control == GLOBAL_REFCLK_3_BOT_CONTROL_ENABLE_R2L_L2B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.global_refclk_3_bot_power_mode == GLOBAL_REFCLK_3_BOT_POWER_MODE_HIGH_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.global_refclk_3_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.global_refclk_3_right_adjacent_active == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.global_refclk_3_top_control == GLOBAL_REFCLK_3_TOP_CONTROL_ENABLE_P2L_L2B_P2R_R2T
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.global_refclk_3_top_power_mode == GLOBAL_REFCLK_3_TOP_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.hard_all_ux_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.local_clock_line_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.quad_global_refclk_0_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.quad_global_refclk_1_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.quad_global_refclk_2_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.quad_global_refclk_3_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.quad_regional_refclk_0_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.quad_regional_refclk_1_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.regional_refclk_0_bot_control == REGIONAL_REFCLK_0_BOT_CONTROL_ENABLE_T2R_B2L_NO_PASS_THRU
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.regional_refclk_0_bot_power_mode == REGIONAL_REFCLK_0_BOT_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.regional_refclk_0_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.regional_refclk_0_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.regional_refclk_0_top_control == REGIONAL_REFCLK_0_TOP_CONTROL_ENABLE_T2R_B2L_NO_PASS_THRU
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.regional_refclk_0_top_power_mode == REGIONAL_REFCLK_0_TOP_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.regional_refclk_1_bot_control == REGIONAL_REFCLK_1_BOT_CONTROL_ENABLE_R2L_L2B
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.regional_refclk_1_bot_power_mode == REGIONAL_REFCLK_1_BOT_POWER_MODE_HIGH_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.regional_refclk_1_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.regional_refclk_1_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.regional_refclk_1_top_control == REGIONAL_REFCLK_1_TOP_CONTROL_ENABLE_L2R_R2T
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.regional_refclk_1_top_power_mode == REGIONAL_REFCLK_1_TOP_POWER_MODE_HIGH_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_fw_loader_cfg_data_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_fw_loader_cfg_fw_loader_en_attr == SCMNG_FW_LOADER_CFG_FW_LOADER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_fw_loader_cfg_offset_addr_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_fw_loader_cfg_single_mode_en_attr == SCMNG_FW_LOADER_CFG_SINGLE_MODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_ahb_non_posted_write_attr == SCMNG_PM_CFG_AHB_NON_POSTED_WRITE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_an_done_lane0_attr == SCMNG_PM_CFG_AN_DONE_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_an_done_lane1_attr == SCMNG_PM_CFG_AN_DONE_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_an_done_lane2_attr == SCMNG_PM_CFG_AN_DONE_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_an_done_lane3_attr == SCMNG_PM_CFG_AN_DONE_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_apb_broadcast_feature_en_attr == SCMNG_PM_CFG_APB_BROADCAST_FEATURE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_apb_broadcast_type_attr == SCMNG_PM_CFG_APB_BROADCAST_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_apb_security_check_en_attr == SCMNG_PM_CFG_APB_SECURITY_CHECK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_cfg_top_head_visactl0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_cfg_top_head_visactl1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_cfg_top_head_visactl2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_cfg_top_head_visactl3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_cfg_top_head_visaenable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_cpi_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_cpi_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_cpi_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_ecc_double_attr == SCMNG_PM_CFG_ECC_DOUBLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_error_l0_attr == SCMNG_PM_CFG_ERROR_L0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_error_l1_attr == SCMNG_PM_CFG_ERROR_L1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_error_l2_attr == SCMNG_PM_CFG_ERROR_L2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_error_l3_attr == SCMNG_PM_CFG_ERROR_L3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_fabric_wd_counter_max_attr == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_link_mng_cpi_cmd_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_link_mng_cpi_data_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_one_bit_error_corrected_attr == SCMNG_PM_CFG_ONE_BIT_ERROR_CORRECTED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_phy_cpi_cmd_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_phy_cpi_data_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_phy_owner_cpi_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_probe_addr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_rx_ready_lane0_attr == SCMNG_PM_CFG_RX_READY_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_rx_ready_lane1_attr == SCMNG_PM_CFG_RX_READY_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_rx_ready_lane2_attr == SCMNG_PM_CFG_RX_READY_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_rx_ready_lane3_attr == SCMNG_PM_CFG_RX_READY_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_sw_reserved_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_trn_done_lane0_attr == SCMNG_PM_CFG_TRN_DONE_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_trn_done_lane1_attr == SCMNG_PM_CFG_TRN_DONE_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_trn_done_lane2_attr == SCMNG_PM_CFG_TRN_DONE_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_trn_done_lane3_attr == SCMNG_PM_CFG_TRN_DONE_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_tx_ready_lane0_attr == SCMNG_PM_CFG_TX_READY_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_tx_ready_lane1_attr == SCMNG_PM_CFG_TX_READY_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_tx_ready_lane2_attr == SCMNG_PM_CFG_TX_READY_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_tx_ready_lane3_attr == SCMNG_PM_CFG_TX_READY_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_visa_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_visa_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.scmng_pm_cfg_visa_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_aon_cfg_ckgate_disable_attr == SERDES_IP_CLKRX_BOT_AON_CFG_CKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_aon_cfg_cmn_powerup_attr == SERDES_IP_CLKRX_BOT_AON_CFG_CMN_POWERUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_aon_cfg_cmn_powerup_override_en_attr == SERDES_IP_CLKRX_BOT_AON_CFG_CMN_POWERUP_OVERRIDE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_aon_cfg_cmntstbus_addr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_aon_cfg_synth_force_pup_attr == SERDES_IP_CLKRX_BOT_AON_CFG_SYNTH_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_aon_cfg_synth_force_pup_en_attr == SERDES_IP_CLKRX_BOT_AON_CFG_SYNTH_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_aprobe_bot_en_attr == SERDES_IP_CLKRX_BOT_CFG_APROBE_BOT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_aprobe_left_en_attr == SERDES_IP_CLKRX_BOT_CFG_APROBE_LEFT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_aprobe_right_en_attr == SERDES_IP_CLKRX_BOT_CFG_APROBE_RIGHT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_aprobe_top_en_attr == SERDES_IP_CLKRX_BOT_CFG_APROBE_TOP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmn_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmn_pg_disable_attr == SERDES_IP_CLKRX_BOT_CFG_CMN_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmn_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnaprobeclkrx_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnbs_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnbshihyst_attr == SERDES_IP_CLKRX_BOT_CFG_CMNBSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalptr_pstate_refckregopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalptr_pstate_swfabricregopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalptr_quad_refckregopampoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalptr_quad_swfabricregopampoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffset_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREFCKREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffsetfsm_clear_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREFCKREGOPAMPOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffsetfsm_init_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREFCKREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffsetfsm_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREFCKREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffsetfsm_req_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREFCKREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREFCKREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffsetfsmout_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREFCKREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffsetmeas_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREFCKREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffsetmeas_req_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREFCKREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_finish_side_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_invert_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_round_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_runcount_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_signmagen_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetmeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetmeas_validdlycount_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffset_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALSWFABRICREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffsetfsm_clear_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffsetfsm_init_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffsetfsm_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffsetfsm_req_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffsetfsmout_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffsetmeas_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALSWFABRICREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffsetmeas_req_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALSWFABRICREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrx_bypass_en_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRX_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxcdrdiv_bot_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXCDRDIV_BOT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxcdrdiv_input_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxcdrdiv_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXCDRDIV_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxcdrdiv_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXCDRDIV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxcdrdiv_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXCDRDIV_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxcdrdiv_top_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXCDRDIV_TOP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbuf_buf2dpma_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXREFCKBUF_BUF2DPMA_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbuf_cml_ena_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXREFCKBUF_CML_ENA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbuf_core_cmos_ena_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXREFCKBUF_CORE_CMOS_ENA_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbuf_hs_cmos_ena_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXREFCKBUF_HS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbuf_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXREFCKBUF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbuf_powersave_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXREFCKBUF_POWERSAVE_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbuf_termcal_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbuf_termhiz_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXREFCKBUF_TERMHIZ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbufsel_hs_ls_b_path_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXREFCKBUFSEL_HS_LS_B_PATH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbufsel_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXREFCKBUFSEL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxspare_attr == 16'd61440
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxsynthdiv_bot_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXSYNTHDIV_BOT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxsynthdiv_input_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxsynthdiv_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXSYNTHDIV_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxsynthdiv_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXSYNTHDIV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxsynthdiv_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXSYNTHDIV_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxsynthdiv_top_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXSYNTHDIV_TOP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmndprobe_addr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnfsm_cken_ovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnfsm_cken_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_changeref_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_REFCK_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_changeref_val_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_REFCK_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_en_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_REFCK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_smpltime_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refckm_charge_up_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_REFCKM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refckm_pull_dn_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_REFCKM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refckm_sense_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_REFCKM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refckp_charge_up_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_REFCKP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refckp_pull_dn_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_REFCKP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refckp_sense_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_REFCKP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_cdrdivsel_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_hsrefsel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_hsrefsel_powersave_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_HSREFSEL_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_lcrefsel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_lcrefsel_powersave_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_LCREFSEL_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_pad2cmos_ana_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_PAD2CMOS_ANA_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_pad2cmos_dig_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_PAD2CMOS_DIG_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel0_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel0_powersave_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_REFSEL0_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel1_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel1_powersave_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_REFSEL1_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel2_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel2_powersave_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_REFSEL2_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel3_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel3_powersave_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_REFSEL3_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel4_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel4_powersave_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_REFSEL4_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel5_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel5_powersave_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_REFSEL5_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_synthdivsel_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_termhiz_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_TERMHIZ_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrefckctrl_auto_powerdown_en_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREFCKCTRL_AUTO_POWERDOWN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrefckctrl_cml_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREFCKCTRL_CML_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrefckctrl_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREFCKCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrefckreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s0q0_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s0q1_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s0q2_attr == 10'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s0q3_attr == 10'd250
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s0q4_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s0q5_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s0q6_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s0q7_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s1q0_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s1q1_attr == 10'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s1q2_attr == 10'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s1q3_attr == 10'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s1q4_attr == 10'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s1q5_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s1q6_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s1q7_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s2q0_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s2q1_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s2q2_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s2q3_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s2q4_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s2q5_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s2q6_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s2q7_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_en_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_dn_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_up_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_up_ptr1_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_dn_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_up_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_up_ptr1_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_aetrcmn_refckregpwrupacc_ovr_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_AETRCMN_REFCKREGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_aetrcmn_refckregpwrupacc_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_AETRCMN_REFCKREGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_aetrcmn_swfabricregpwrupacc_ovr_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_AETRCMN_SWFABRICREGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_aetrcmn_swfabricregpwrupacc_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_AETRCMN_SWFABRICREGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdcmn_refckbuf_ovr_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdcmn_refckbuf_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdcmn_refckreg_ovr_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDCMN_REFCKREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdcmn_refckreg_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDCMN_REFCKREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdcmn_swfabric_ovr_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDCMN_SWFABRIC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdcmn_swfabric_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDCMN_SWFABRIC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdcmn_swfabricreg_ovr_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDCMN_SWFABRICREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdcmn_swfabricreg_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDCMN_SWFABRICREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdrefck_ntl_b_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDREFCK_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdrefck_ntl_ovr_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDREFCK_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_arstcmn_refckregreset_ovr_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_ARSTCMN_REFCKREGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_arstcmn_refckregreset_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_ARSTCMN_REFCKREGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_arstcmn_swfabricregreset_ovr_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_ARSTCMN_SWFABRICREGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_arstcmn_swfabricregreset_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_ARSTCMN_SWFABRICREGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref0_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF0_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref0_powersave_b_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF0_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref0_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF0_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref0_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref1_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF1_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref1_powersave_b_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF1_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref1_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF1_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref1_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref2_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF2_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref2_powersave_b_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF2_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref2_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF2_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref2_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref3_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF3_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref3_powersave_b_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF3_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref3_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF3_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref3_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref4_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF4_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref4_powersave_b_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF4_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref4_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF4_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref4_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref5_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF5_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref5_powersave_b_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF5_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref5_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF5_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref5_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref6_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF6_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref6_powersave_b_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF6_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref6_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF6_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref6_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref7_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF7_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref7_powersave_b_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF7_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref7_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF7_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref7_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabricreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_egress_override_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_EGRESS_OVERRIDE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_egress_override_val_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_p_vdd_pwrgood_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_P_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_p_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_P_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_pa_vdd_ehv_pwrgood_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_pa_vdd_ehv_pwrgood_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_pa_vdd_pwrgood_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_PA_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_pa_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_PA_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_burnin_mode_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_BURNIN_MODE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_burnin_mode_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_BURNIN_MODE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_cdrdivsel_nt_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_cdrdivsel_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_CDRDIVSEL_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_cmnclkrxrefckbufsel_hs_ls_b_path_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_CMNCLKRXREFCKBUFSEL_HS_LS_B_PATH_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_cmnclkrxrefckbufsel_hs_ls_b_path_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_CMNCLKRXREFCKBUFSEL_HS_LS_B_PATH_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_hsrefsel_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_hsrefsel_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_HSREFSEL_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_hsrefsel_powersave_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_HSREFSEL_POWERSAVE_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_hsrefsel_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_HSREFSEL_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_jtagid_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_JTAGID_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_jtagslvid_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_JTAGSLVID_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_pad2cmos_ana_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_PAD2CMOS_ANA_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_pad2cmos_ana_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_PAD2CMOS_ANA_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_pad2cmos_dig_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_PAD2CMOS_DIG_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_pad2cmos_dig_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_PAD2CMOS_DIG_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_powerup_a_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_POWERUP_A_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_powerup_a_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_POWERUP_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel0_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel0_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel0_powersave_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL0_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel0_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL0_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel1_nt_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel1_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL1_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel1_powersave_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL1_POWERSAVE_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel1_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL1_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel2_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel2_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL2_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel2_powersave_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL2_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel2_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL2_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel3_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel3_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL3_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel3_powersave_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL3_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel3_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL3_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel4_nt_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel4_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL4_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel4_powersave_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL4_POWERSAVE_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel4_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL4_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel5_nt_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel5_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL5_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel5_powersave_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL5_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel5_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL5_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_synthdivsel_nt_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_synthdivsel_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_SYNTHDIVSEL_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_termhiz_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_TERMHIZ_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_termhiz_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_TERMHIZ_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_vdd_ehv_sel_nt_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_vdd_ehv_sel_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_VDD_EHV_SEL_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_spare_nt_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_spare_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_SPARE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_idat_txbscan_n_attr == SERDES_IP_CLKRX_BOT_IF_CFG_IDAT_TXBSCAN_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_idat_txbscan_n_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_IDAT_TXBSCAN_N_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_idat_txbscan_p_attr == SERDES_IP_CLKRX_BOT_IF_CFG_IDAT_TXBSCAN_P_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_idat_txbscan_p_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_IDAT_TXBSCAN_P_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_irst_ref_por_b_a_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_IRST_REF_POR_B_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_irst_ref_tstbus_b_a_attr == SERDES_IP_CLKRX_BOT_IF_CFG_IRST_REF_TSTBUS_B_A_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_bot_if_cfg_irst_ref_tstbus_b_a_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_IRST_REF_TSTBUS_B_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_aon_cfg_ckgate_disable_attr == SERDES_IP_CLKRX_TOP_AON_CFG_CKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_aon_cfg_cmn_powerup_attr == SERDES_IP_CLKRX_TOP_AON_CFG_CMN_POWERUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_aon_cfg_cmn_powerup_override_en_attr == SERDES_IP_CLKRX_TOP_AON_CFG_CMN_POWERUP_OVERRIDE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_aon_cfg_cmntstbus_addr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_aon_cfg_synth_force_pup_attr == SERDES_IP_CLKRX_TOP_AON_CFG_SYNTH_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_aon_cfg_synth_force_pup_en_attr == SERDES_IP_CLKRX_TOP_AON_CFG_SYNTH_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_aprobe_bot_en_attr == SERDES_IP_CLKRX_TOP_CFG_APROBE_BOT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_aprobe_left_en_attr == SERDES_IP_CLKRX_TOP_CFG_APROBE_LEFT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_aprobe_right_en_attr == SERDES_IP_CLKRX_TOP_CFG_APROBE_RIGHT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_aprobe_top_en_attr == SERDES_IP_CLKRX_TOP_CFG_APROBE_TOP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmn_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmn_pg_disable_attr == SERDES_IP_CLKRX_TOP_CFG_CMN_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmn_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnaprobeclkrx_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnbs_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnbshihyst_attr == SERDES_IP_CLKRX_TOP_CFG_CMNBSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalptr_pstate_refckregopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalptr_pstate_swfabricregopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalptr_quad_refckregopampoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalptr_quad_swfabricregopampoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffset_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREFCKREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffsetfsm_clear_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREFCKREGOPAMPOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffsetfsm_init_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREFCKREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffsetfsm_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREFCKREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffsetfsm_req_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREFCKREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREFCKREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffsetfsmout_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREFCKREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffsetmeas_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREFCKREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffsetmeas_req_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREFCKREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_finish_side_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_invert_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_round_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_runcount_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_signmagen_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetmeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetmeas_validdlycount_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffset_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALSWFABRICREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffsetfsm_clear_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffsetfsm_init_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffsetfsm_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffsetfsm_req_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffsetfsmout_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffsetmeas_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALSWFABRICREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffsetmeas_req_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALSWFABRICREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrx_bypass_en_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRX_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxcdrdiv_bot_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXCDRDIV_BOT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxcdrdiv_input_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxcdrdiv_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXCDRDIV_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxcdrdiv_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXCDRDIV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxcdrdiv_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXCDRDIV_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxcdrdiv_top_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXCDRDIV_TOP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbuf_buf2dpma_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXREFCKBUF_BUF2DPMA_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbuf_cml_ena_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXREFCKBUF_CML_ENA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbuf_core_cmos_ena_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXREFCKBUF_CORE_CMOS_ENA_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbuf_hs_cmos_ena_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXREFCKBUF_HS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbuf_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXREFCKBUF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbuf_powersave_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXREFCKBUF_POWERSAVE_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbuf_termcal_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbuf_termhiz_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXREFCKBUF_TERMHIZ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbufsel_hs_ls_b_path_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXREFCKBUFSEL_HS_LS_B_PATH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbufsel_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXREFCKBUFSEL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxspare_attr == 16'd61440
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxsynthdiv_bot_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXSYNTHDIV_BOT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxsynthdiv_input_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxsynthdiv_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXSYNTHDIV_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxsynthdiv_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXSYNTHDIV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxsynthdiv_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXSYNTHDIV_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxsynthdiv_top_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXSYNTHDIV_TOP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmndprobe_addr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnfsm_cken_ovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnfsm_cken_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_changeref_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_REFCK_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_changeref_val_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_REFCK_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_en_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_REFCK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_smpltime_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refckm_charge_up_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_REFCKM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refckm_pull_dn_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_REFCKM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refckm_sense_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_REFCKM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refckp_charge_up_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_REFCKP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refckp_pull_dn_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_REFCKP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refckp_sense_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_REFCKP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnref_cdrdivsel_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnref_hsrefsel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnref_hsrefsel_powersave_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_HSREFSEL_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnref_lcrefsel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnref_lcrefsel_powersave_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_LCREFSEL_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnref_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnref_pad2cmos_ana_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_PAD2CMOS_ANA_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnref_pad2cmos_dig_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_PAD2CMOS_DIG_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel0_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel0_powersave_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_REFSEL0_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel1_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel1_powersave_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_REFSEL1_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel2_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel2_powersave_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_REFSEL2_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel3_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel3_powersave_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_REFSEL3_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel4_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel4_powersave_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_REFSEL4_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel5_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel5_powersave_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_REFSEL5_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnref_synthdivsel_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnref_termhiz_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_TERMHIZ_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrefckctrl_auto_powerdown_en_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREFCKCTRL_AUTO_POWERDOWN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrefckctrl_cml_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREFCKCTRL_CML_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrefckctrl_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREFCKCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrefckreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s0q0_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s0q1_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s0q2_attr == 10'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s0q3_attr == 10'd250
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s0q4_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s0q5_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s0q6_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s0q7_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s1q0_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s1q1_attr == 10'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s1q2_attr == 10'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s1q3_attr == 10'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s1q4_attr == 10'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s1q5_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s1q6_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s1q7_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s2q0_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s2q1_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s2q2_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s2q3_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s2q4_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s2q5_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s2q6_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s2q7_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_en_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_dn_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_up_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_up_ptr1_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_dn_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_up_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_up_ptr1_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_aetrcmn_refckregpwrupacc_ovr_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_AETRCMN_REFCKREGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_aetrcmn_refckregpwrupacc_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_AETRCMN_REFCKREGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_aetrcmn_swfabricregpwrupacc_ovr_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_AETRCMN_SWFABRICREGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_aetrcmn_swfabricregpwrupacc_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_AETRCMN_SWFABRICREGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdcmn_refckbuf_ovr_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdcmn_refckbuf_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdcmn_refckreg_ovr_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDCMN_REFCKREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdcmn_refckreg_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDCMN_REFCKREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdcmn_swfabric_ovr_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDCMN_SWFABRIC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdcmn_swfabric_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDCMN_SWFABRIC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdcmn_swfabricreg_ovr_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDCMN_SWFABRICREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdcmn_swfabricreg_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDCMN_SWFABRICREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdrefck_ntl_b_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDREFCK_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdrefck_ntl_ovr_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDREFCK_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_arstcmn_refckregreset_ovr_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_ARSTCMN_REFCKREGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_arstcmn_refckregreset_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_ARSTCMN_REFCKREGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_arstcmn_swfabricregreset_ovr_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_ARSTCMN_SWFABRICREGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_arstcmn_swfabricregreset_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_ARSTCMN_SWFABRICREGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref0_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF0_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref0_powersave_b_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF0_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref0_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF0_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref0_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref1_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF1_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref1_powersave_b_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF1_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref1_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF1_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref1_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref2_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF2_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref2_powersave_b_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF2_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref2_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF2_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref2_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref3_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF3_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref3_powersave_b_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF3_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref3_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF3_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref3_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref4_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF4_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref4_powersave_b_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF4_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref4_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF4_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref4_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref5_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF5_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref5_powersave_b_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF5_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref5_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF5_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref5_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref6_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF6_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref6_powersave_b_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF6_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref6_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF6_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref6_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref7_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF7_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref7_powersave_b_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF7_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref7_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF7_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref7_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabricreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_egress_override_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_EGRESS_OVERRIDE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_egress_override_val_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_p_vdd_pwrgood_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_P_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_p_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_P_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_pa_vdd_ehv_pwrgood_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_pa_vdd_ehv_pwrgood_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_pa_vdd_pwrgood_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_PA_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_pa_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_PA_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_burnin_mode_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_BURNIN_MODE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_burnin_mode_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_BURNIN_MODE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_cdrdivsel_nt_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_cdrdivsel_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_CDRDIVSEL_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_cmnclkrxrefckbufsel_hs_ls_b_path_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_CMNCLKRXREFCKBUFSEL_HS_LS_B_PATH_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_cmnclkrxrefckbufsel_hs_ls_b_path_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_CMNCLKRXREFCKBUFSEL_HS_LS_B_PATH_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_hsrefsel_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_hsrefsel_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_HSREFSEL_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_hsrefsel_powersave_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_HSREFSEL_POWERSAVE_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_hsrefsel_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_HSREFSEL_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_jtagid_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_JTAGID_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_jtagslvid_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_JTAGSLVID_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_pad2cmos_ana_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_PAD2CMOS_ANA_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_pad2cmos_ana_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_PAD2CMOS_ANA_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_pad2cmos_dig_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_PAD2CMOS_DIG_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_pad2cmos_dig_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_PAD2CMOS_DIG_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_powerup_a_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_POWERUP_A_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_powerup_a_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_POWERUP_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel0_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel0_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel0_powersave_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL0_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel0_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL0_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel1_nt_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel1_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL1_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel1_powersave_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL1_POWERSAVE_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel1_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL1_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel2_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel2_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL2_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel2_powersave_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL2_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel2_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL2_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel3_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel3_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL3_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel3_powersave_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL3_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel3_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL3_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel4_nt_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel4_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL4_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel4_powersave_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL4_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel4_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL4_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel5_nt_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel5_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL5_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel5_powersave_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL5_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel5_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL5_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_synthdivsel_nt_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_synthdivsel_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_SYNTHDIVSEL_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_termhiz_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_TERMHIZ_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_termhiz_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_TERMHIZ_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_vdd_ehv_sel_nt_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_vdd_ehv_sel_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_VDD_EHV_SEL_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_spare_nt_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_spare_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_SPARE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_idat_txbscan_n_attr == SERDES_IP_CLKRX_TOP_IF_CFG_IDAT_TXBSCAN_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_idat_txbscan_n_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_IDAT_TXBSCAN_N_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_idat_txbscan_p_attr == SERDES_IP_CLKRX_TOP_IF_CFG_IDAT_TXBSCAN_P_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_idat_txbscan_p_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_IDAT_TXBSCAN_P_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_irst_ref_por_b_a_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_IRST_REF_POR_B_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_irst_ref_tstbus_b_a_attr == SERDES_IP_CLKRX_TOP_IF_CFG_IRST_REF_TSTBUS_B_A_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_clkrx_top_if_cfg_irst_ref_tstbus_b_a_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_IRST_REF_TSTBUS_B_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l0_cfg_ckgate_disable_attr == SERDES_IP_CMN_AON_L0_CFG_CKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l0_cfg_cmn_force_pup_attr == SERDES_IP_CMN_AON_L0_CFG_CMN_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l0_cfg_cmn_force_pup_en_attr == SERDES_IP_CMN_AON_L0_CFG_CMN_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l0_cfg_cmn_rst_b_attr == SERDES_IP_CMN_AON_L0_CFG_CMN_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l0_cfg_cmn_rst_en_attr == SERDES_IP_CMN_AON_L0_CFG_CMN_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l0_cfg_cmnclk_ctrl_attr == SERDES_IP_CMN_AON_L0_CFG_CMNCLK_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l0_cfg_cmnclkdiv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l0_cfg_cmnfsm_pmu_req_attr == SERDES_IP_CMN_AON_L0_CFG_CMNFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l0_cfg_cmnfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L0_CFG_CMNFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l0_cfg_cmntstbus_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcfast_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcfast_force_pup_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCFAST_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcfast_force_pup_en_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCFAST_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcfast_ignore_mode_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCFAST_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcfast_rst_b_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCFAST_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcfast_rst_en_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCFAST_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcfastfsm_pmu_req_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCFASTFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcfastfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCFASTFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcmed_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcmed_force_pup_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCMED_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcmed_force_pup_en_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCMED_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcmed_ignore_mode_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCMED_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcmed_rst_b_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCMED_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcmed_rst_en_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCMED_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcmedfsm_pmu_req_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCMEDFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcmedfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCMEDFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcslow_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcslow_force_pup_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCSLOW_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcslow_force_pup_en_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCSLOW_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcslow_ignore_mode_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCSLOW_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcslow_rst_b_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCSLOW_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcslow_rst_en_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCSLOW_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcslowfsm_pmu_req_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCSLOWFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcslowfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCSLOWFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l0_cfg_tstbus_rst_bypass_attr == SERDES_IP_CMN_AON_L0_CFG_TSTBUS_RST_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l0_cfg_tstbus_rst_bypass_en_attr == SERDES_IP_CMN_AON_L0_CFG_TSTBUS_RST_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l1_cfg_ckgate_disable_attr == SERDES_IP_CMN_AON_L1_CFG_CKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l1_cfg_cmn_force_pup_attr == SERDES_IP_CMN_AON_L1_CFG_CMN_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l1_cfg_cmn_force_pup_en_attr == SERDES_IP_CMN_AON_L1_CFG_CMN_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l1_cfg_cmn_rst_b_attr == SERDES_IP_CMN_AON_L1_CFG_CMN_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l1_cfg_cmn_rst_en_attr == SERDES_IP_CMN_AON_L1_CFG_CMN_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l1_cfg_cmnclk_ctrl_attr == SERDES_IP_CMN_AON_L1_CFG_CMNCLK_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l1_cfg_cmnclkdiv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l1_cfg_cmnfsm_pmu_req_attr == SERDES_IP_CMN_AON_L1_CFG_CMNFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l1_cfg_cmnfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L1_CFG_CMNFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l1_cfg_cmntstbus_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcfast_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcfast_force_pup_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCFAST_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcfast_force_pup_en_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCFAST_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcfast_ignore_mode_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCFAST_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcfast_rst_b_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCFAST_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcfast_rst_en_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCFAST_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcfastfsm_pmu_req_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCFASTFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcfastfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCFASTFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcmed_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcmed_force_pup_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCMED_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcmed_force_pup_en_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCMED_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcmed_ignore_mode_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCMED_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcmed_rst_b_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCMED_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcmed_rst_en_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCMED_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcmedfsm_pmu_req_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCMEDFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcmedfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCMEDFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcslow_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcslow_force_pup_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCSLOW_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcslow_force_pup_en_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCSLOW_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcslow_ignore_mode_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCSLOW_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcslow_rst_b_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCSLOW_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcslow_rst_en_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCSLOW_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcslowfsm_pmu_req_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCSLOWFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcslowfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCSLOWFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l1_cfg_tstbus_rst_bypass_attr == SERDES_IP_CMN_AON_L1_CFG_TSTBUS_RST_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l1_cfg_tstbus_rst_bypass_en_attr == SERDES_IP_CMN_AON_L1_CFG_TSTBUS_RST_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l2_cfg_ckgate_disable_attr == SERDES_IP_CMN_AON_L2_CFG_CKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l2_cfg_cmn_force_pup_attr == SERDES_IP_CMN_AON_L2_CFG_CMN_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l2_cfg_cmn_force_pup_en_attr == SERDES_IP_CMN_AON_L2_CFG_CMN_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l2_cfg_cmn_rst_b_attr == SERDES_IP_CMN_AON_L2_CFG_CMN_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l2_cfg_cmn_rst_en_attr == SERDES_IP_CMN_AON_L2_CFG_CMN_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l2_cfg_cmnclk_ctrl_attr == SERDES_IP_CMN_AON_L2_CFG_CMNCLK_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l2_cfg_cmnclkdiv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l2_cfg_cmnfsm_pmu_req_attr == SERDES_IP_CMN_AON_L2_CFG_CMNFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l2_cfg_cmnfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L2_CFG_CMNFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l2_cfg_cmntstbus_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcfast_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcfast_force_pup_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCFAST_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcfast_force_pup_en_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCFAST_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcfast_ignore_mode_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCFAST_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcfast_rst_b_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCFAST_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcfast_rst_en_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCFAST_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcfastfsm_pmu_req_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCFASTFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcfastfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCFASTFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcmed_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcmed_force_pup_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCMED_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcmed_force_pup_en_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCMED_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcmed_ignore_mode_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCMED_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcmed_rst_b_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCMED_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcmed_rst_en_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCMED_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcmedfsm_pmu_req_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCMEDFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcmedfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCMEDFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcslow_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcslow_force_pup_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCSLOW_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcslow_force_pup_en_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCSLOW_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcslow_ignore_mode_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCSLOW_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcslow_rst_b_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCSLOW_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcslow_rst_en_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCSLOW_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcslowfsm_pmu_req_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCSLOWFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcslowfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCSLOWFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l2_cfg_tstbus_rst_bypass_attr == SERDES_IP_CMN_AON_L2_CFG_TSTBUS_RST_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l2_cfg_tstbus_rst_bypass_en_attr == SERDES_IP_CMN_AON_L2_CFG_TSTBUS_RST_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l3_cfg_ckgate_disable_attr == SERDES_IP_CMN_AON_L3_CFG_CKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l3_cfg_cmn_force_pup_attr == SERDES_IP_CMN_AON_L3_CFG_CMN_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l3_cfg_cmn_force_pup_en_attr == SERDES_IP_CMN_AON_L3_CFG_CMN_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l3_cfg_cmn_rst_b_attr == SERDES_IP_CMN_AON_L3_CFG_CMN_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l3_cfg_cmn_rst_en_attr == SERDES_IP_CMN_AON_L3_CFG_CMN_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l3_cfg_cmnclk_ctrl_attr == SERDES_IP_CMN_AON_L3_CFG_CMNCLK_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l3_cfg_cmnclkdiv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l3_cfg_cmnfsm_pmu_req_attr == SERDES_IP_CMN_AON_L3_CFG_CMNFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l3_cfg_cmnfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L3_CFG_CMNFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l3_cfg_cmntstbus_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcfast_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcfast_force_pup_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCFAST_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcfast_force_pup_en_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCFAST_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcfast_ignore_mode_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCFAST_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcfast_rst_b_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCFAST_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcfast_rst_en_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCFAST_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcfastfsm_pmu_req_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCFASTFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcfastfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCFASTFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcmed_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcmed_force_pup_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCMED_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcmed_force_pup_en_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCMED_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcmed_ignore_mode_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCMED_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcmed_rst_b_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCMED_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcmed_rst_en_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCMED_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcmedfsm_pmu_req_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCMEDFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcmedfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCMEDFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcslow_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcslow_force_pup_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCSLOW_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcslow_force_pup_en_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCSLOW_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcslow_ignore_mode_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCSLOW_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcslow_rst_b_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCSLOW_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcslow_rst_en_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCSLOW_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcslowfsm_pmu_req_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCSLOWFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcslowfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCSLOWFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l3_cfg_tstbus_rst_bypass_attr == SERDES_IP_CMN_AON_L3_CFG_TSTBUS_RST_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_aon_l3_cfg_tstbus_rst_bypass_en_attr == SERDES_IP_CMN_AON_L3_CFG_TSTBUS_RST_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_bti_div_attr == 7'd54
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_bti_div_rst_attr == SERDES_IP_CMN_L0_CFG_BTI_DIV_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_bti_en_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_bti_static_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmn_pg_disable_attr == SERDES_IP_CMN_L0_CFG_CMN_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmn_scratch_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnadc_req_attr == SERDES_IP_CMN_L0_CFG_CMNADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnapb2strbbridgecfg_acc_ctrl_field_mask_write_en_attr == SERDES_IP_CMN_L0_CFG_CMNAPB2STRBBRIDGECFG_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnapb2strbbridgecfg_force_state_en_attr == SERDES_IP_CMN_L0_CFG_CMNAPB2STRBBRIDGECFG_FORCE_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnapb2strbbridgecfg_force_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnapb2strbbridgecfg_stbl_time_aftr_strb_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnapb2strbbridgecfg_stbl_time_bfr_strb_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnapb2strbbridgecfg_strb_pulse_width_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnapbmaster_timeout_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobe_addr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobe_lastmux_isolate_attr == SERDES_IP_CMN_L0_CFG_CMNAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobeadc_current_direction_attr == SERDES_IP_CMN_L0_CFG_CMNAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobeadc_resistor_enable_attr == SERDES_IP_CMN_L0_CFG_CMNAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobedac_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobedac_en_attr == SERDES_IP_CMN_L0_CFG_CMNAPROBEDAC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobedacctrl_block_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobedacctrl_en_attr == SERDES_IP_CMN_L0_CFG_CMNAPROBEDACCTRL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobedacctrl_mask_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobedacctrl_rotate_left_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobedacctrl_tstbus_clkdiv_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnbias_icc20uadj_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnbias_icc80uadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnbias_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnbias_termcal_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnbscan_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnbshihyst_attr == SERDES_IP_CMN_L0_CFG_CMNBSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_bg_en_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_bg_one_step_cal_en_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_fg_inc_cal_en_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_fg_one_step_cal_en_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_finish_side_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_initval_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_invert_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_restore_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_round_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_runcount_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_signmagen_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetmeas_req_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_SYNTHDUTYOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncaldacbg_abort_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncaldacbg_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncaldacbg_ready_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncaldacfsm_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncaldacfsm_synthdutyoffsetfsm_clear_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncaldacfsm_synthdutyoffsetfsm_init_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncaldacfsm_synthdutyoffsetfsm_req_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncaldacsynthdutyoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALDACSYNTHDUTYOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncaldacsynthdutyoffsetfsmout_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALDACSYNTHDUTYOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalptr_pstate_rcomp_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalptr_pstate_synthdutyoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalptr_quad_rcomp_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalptr_quad_regopampoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalptr_quad_synthdutyoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_biastrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_cap_tune_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_divrate_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_mode_select_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_ref_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMP_REF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_rx_term_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMP_RX_TERM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_tfr_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMP_TFR_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_tx_term_pd_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMP_TX_TERM_PD_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_tx_term_pu_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMP_TX_TERM_PU_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_txterm_nmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_txterm_pmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_clear_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_code_delay_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_init_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rcomp_tfr_init_cal_value_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rcomp_tfr_max_value_attr == 4'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rcomp_tfr_min_value_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rcomp_txpd_valid_code_lut_vf00_attr == 32'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rcomp_txpd_valid_code_lut_vf01_attr == 32'd4246868100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rcomp_txpu_valid_code_lut_vf00_attr == 32'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rcomp_txpu_valid_code_lut_vf01_attr == 32'd4246868100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_req_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rx_comp_inv_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_RX_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rx_init_cal_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rx_initval_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rx_step_sign_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_RX_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rx_termcode_delta_lut_attr == 31'd24084352
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tfr_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tfr_comp_inv_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_TFR_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tfr_initval_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tfr_step_sign_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_TFR_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tfr_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_time_comp_config_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_time_lpfsetup_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_time_mode_setup_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_time_reset_release_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_time_sample_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tx_pd_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tx_pd_init_cal_value_attr == 6'd49
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tx_pd_max_value_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tx_pd_min_value_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tx_pu_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tx_pu_init_cal_value_attr == 6'd49
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tx_pu_max_value_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tx_pu_min_value_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_txpd_comp_inv_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_TXPD_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_txpd_initval_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_txpd_step_sign_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_TXPD_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_txpd_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_txpu_comp_inv_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_TXPU_COMP_INV_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_txpu_initval_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_txpu_step_sign_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_TXPU_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_txpu_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_txterm_pmos_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmaster_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPMASTER_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmaster_rx_locovr_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmaster_tfr_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmaster_txpd_locovr_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmaster_txpu_locovr_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmaster_valid_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPMASTER_VALID_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmeas_dlycount_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffset_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_clear_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_finish_side_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_init_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_invert_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_req_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_runcount_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsmout_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetmeas_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetmeas_req_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_avg_en_attr == SERDES_IP_CMN_L0_CFG_CMNCKM_AVG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_clk_en_attr == SERDES_IP_CMN_L0_CFG_CMNCKM_CLK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_continuous_attr == SERDES_IP_CMN_L0_CFG_CMNCKM_CONTINUOUS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_dig_meas_en_attr == SERDES_IP_CMN_L0_CFG_CMNCKM_DIG_MEAS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_dig_meas_err_clr_attr == SERDES_IP_CMN_L0_CFG_CMNCKM_DIG_MEAS_ERR_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_en_attr == SERDES_IP_CMN_L0_CFG_CMNCKM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_max_thr_attr == 25'd33554431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_meas_ck_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_ref_ck_div_ratio_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_result_clr_attr == SERDES_IP_CMN_L0_CFG_CMNCKM_RESULT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_start_attr == SERDES_IP_CMN_L0_CFG_CMNCKM_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_wdt_interval_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_win_thr_ref_attr == 25'd16777215
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnclk_keepalive_en_b_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnclk_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmndmondac_en_attr == SERDES_IP_CMN_L0_CFG_CMNDMONDAC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnfsm_cken_ovr_attr == SERDES_IP_CMN_L0_CFG_CMNFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnfsm_cken_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_aprobe1_charge_up_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_APROBE1_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_aprobe1_pull_dn_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_APROBE1_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_aprobe1_sense_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_APROBE1_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_aprobe2_charge_up_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_APROBE2_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_aprobe2_pull_dn_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_APROBE2_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_aprobe2_sense_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_APROBE2_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_changeref_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_changeref_val_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_en_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_CMN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_ntl_sel_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_CMN_NTL_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_refckm_charge_up_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_REFCKM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_refckm_pull_dn_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_REFCKM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_refckm_sense_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_REFCKM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_refckp_charge_up_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_REFCKP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_refckp_pull_dn_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_REFCKP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_refckp_sense_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_REFCKP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnpcs_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnpcs_ref_sel_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnpcs_ref_sel_tx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnperfmon_compare_val_start_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnperfmon_compare_val_stop_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnperfmon_en_attr == SERDES_IP_CMN_L0_CFG_CMNPERFMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnperfmon_mask_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprefckbufprelut_delta_attr == 15'd32767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprefckbufprelut_init_termcal_rx_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprefckbufprelut_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNRCOMPREFCKBUFPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprefckbufprelut_termcal_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprefcktxdrvprelut_delta_attr == 15'd4672
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprefcktxdrvprelut_init_termcal_rx_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprefcktxdrvprelut_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNRCOMPREFCKTXDRVPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprefcktxdrvprelut_termcal_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprxdfeprelut_delta_attr == 15'd32767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprxdfeprelut_init_termcal_tfr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprxdfeprelut_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNRCOMPRXDFEPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprxdfeprelut_termcal_tfr_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckbuf_cml_ena_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKBUF_CML_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckbuf_hs_cmos_ena_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKBUF_HS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckbuf_hs_ls_b_path_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKBUF_HS_LS_B_PATH_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckbuf_hs_ref_to_cdrdiv_ena_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKBUF_HS_REF_TO_CDRDIV_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckbuf_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKBUF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckbuf_ls_cmos_ena_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKBUF_LS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckbuf_powersave_b_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKBUF_POWERSAVE_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckbuf_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckbuf_termhiz_b_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKBUF_TERMHIZ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckdrv_powersave_en_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKDRV_POWERSAVE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrefcktxdrv_cdrdiv_en_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKTXDRV_CDRDIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrefcktxdrv_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKTXDRV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrefcktxdrv_termcal_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_en_b_attr == SERDES_IP_CMN_L0_CFG_CMNRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_entry3_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s0q2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s0q3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s1q4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s1q5_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s1q6_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s1q7_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s2q0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_entry2_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_entry3_attr == 13'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_entry4_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_entry5_attr == 13'd62
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_entry6_attr == 13'd390
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_entry7_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s0q2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s0q3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s1q1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s1q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s1q5_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s1q7_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s2q0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_term_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_term_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_term_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_term_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_term_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_term_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_term_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_term_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_keepalive_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_keepalive_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_bias_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_bias_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_refckbuf_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_refckbuf_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_refckbuf_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_refckbuf_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_rxref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_rxref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_rxref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_rxref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_synthdutycomp_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_synthdutycomp_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_synthdutycomp_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_synthdutycomp_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_synthlcslowref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_synthlcslowref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_synthlcslowref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_synthlcslowref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_txref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_txref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_txref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_txref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpurst_regreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpurst_regreset_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpurst_regreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrpurst_regreset_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_aetrcmn_regpwrupacc_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_AETRCMN_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_aetrcmn_regpwrupacc_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_AETRCMN_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_adc_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_adc_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_ADC_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_biasicc_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_biasicc_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_ntl_b_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_ntl_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_refckbuf_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_refckbuf_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_reg_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_reg_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_rxref_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_RXREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_rxref_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_RXREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_synthlcslowref_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_SYNTHLCSLOWREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_synthlcslowref_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_SYNTHLCSLOWREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_txref_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_TXREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_txref_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_TXREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_arstcmn_adc_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_ARSTCMN_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_arstcmn_adc_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_ARSTCMN_ADC_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_arstcmn_aprobedac_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_ARSTCMN_APROBEDAC_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_arstcmn_refcktxdrv_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_ARSTCMN_REFCKTXDRV_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_arstcmn_refcktxdrv_hiz_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_ARSTCMN_REFCKTXDRV_HIZ_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_arstcmn_regreset_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_ARSTCMN_REGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_arstcmn_regreset_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_ARSTCMN_REGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_synthdutycomp_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_SYNTHDUTYCOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_synthdutycomp_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_SYNTHDUTYCOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrxref_dpma_en_attr == SERDES_IP_CMN_L0_CFG_CMNRXREF_DPMA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrxref_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNRXREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnrxref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnspare0_attr == 32'd163
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnspare_attr == 9'd384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_rxlane0_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_rxlane1_timer_attr == 12'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_rxlane2_timer_attr == 12'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_rxlane3_timer_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_synthlcfast_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_synthlcmed_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_synthlcslow_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_txlane0_timer_attr == 12'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_txlane1_timer_attr == 12'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_txlane2_timer_attr == 12'd70
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_txlane3_timer_attr == 12'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthdiv_cdrdiv_en_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHDIV_CDRDIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthdiv_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHDIV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthdiv_slowmed_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHDIV_SLOWMED_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthdutyoffsetcal_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHDUTYOFFSETCAL_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthdutyoffsetcal_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHDUTYOFFSETCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthdutysel_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHDUTYSEL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthdutysel_mux_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlccaldac_currentdacdcdmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlccaldac_currentdacdcdmeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlccaldac_currentdacdcdmeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlccaldac_currentdacdcdmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlccaldac_synthdutyoffsetmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlccaldac_tx_disable_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHLCCALDAC_TX_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlccaldacerr_calsynthdutyerr_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHLCCALDACERR_CALSYNTHDUTYERR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlccaldacerr_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHLCCALDACERR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlcslowref_dpma_en_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHLCSLOWREF_DPMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlcslowref_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHLCSLOWREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlcslowref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmntxref_dpma_en_attr == SERDES_IP_CMN_L0_CFG_CMNTXREF_DPMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmntxref_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNTXREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmntxref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_cmnynthdutyselpolarity_attr == SERDES_IP_CMN_L0_CFG_CMNYNTHDUTYSELPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_lbcmn_locovren_attr == SERDES_IP_CMN_L0_CFG_LBCMN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_lbcmn_synthlcslowmedpostdivclk2cdrrefclken_locovr_attr == SERDES_IP_CMN_L0_CFG_LBCMN_SYNTHLCSLOWMEDPOSTDIVCLK2CDRREFCLKEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_rcompmaster_en_locovr_attr == SERDES_IP_CMN_L0_CFG_RCOMPMASTER_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_rcompmaster_locovren_attr == SERDES_IP_CMN_L0_CFG_RCOMPMASTER_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_rcompslave_locovr_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_rcompslave_locovren_attr == SERDES_IP_CMN_L0_CFG_RCOMPSLAVE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_rcompslave_valid_locovr_attr == SERDES_IP_CMN_L0_CFG_RCOMPSLAVE_VALID_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_rcompterm_rx_termcode_base_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_rcompterm_tfr_termcode_base_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_rcompterm_txpd_termcode_base_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_rcompterm_txpu_termcode_base_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmed_locovren_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMED_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmed_txbitclkselect_locovr_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMED_TXBITCLKSELECT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedcaldac_locovren_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMEDCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedcalregopampoffset_locovren_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedcalregopampoffsetfsmout_locovren_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedpcs_locovren_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMEDPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedpcs_postdiv2clk0_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedpcs_postdiv2clk0en_locovr_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMEDPCS_POSTDIV2CLK0EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedpcs_postdivclk0en_locovr_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMEDPCS_POSTDIVCLK0EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedreg_lev_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedreg_locovren_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMEDREG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_bti_div_attr == 7'd54
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_bti_div_rst_attr == SERDES_IP_CMN_L1_CFG_BTI_DIV_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_bti_en_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_bti_static_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmn_pg_disable_attr == SERDES_IP_CMN_L1_CFG_CMN_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmn_scratch_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnadc_req_attr == SERDES_IP_CMN_L1_CFG_CMNADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnapb2strbbridgecfg_acc_ctrl_field_mask_write_en_attr == SERDES_IP_CMN_L1_CFG_CMNAPB2STRBBRIDGECFG_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnapb2strbbridgecfg_force_state_en_attr == SERDES_IP_CMN_L1_CFG_CMNAPB2STRBBRIDGECFG_FORCE_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnapb2strbbridgecfg_force_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnapb2strbbridgecfg_stbl_time_aftr_strb_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnapb2strbbridgecfg_stbl_time_bfr_strb_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnapb2strbbridgecfg_strb_pulse_width_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnapbmaster_timeout_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobe_addr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobe_lastmux_isolate_attr == SERDES_IP_CMN_L1_CFG_CMNAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobeadc_current_direction_attr == SERDES_IP_CMN_L1_CFG_CMNAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobeadc_resistor_enable_attr == SERDES_IP_CMN_L1_CFG_CMNAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobedac_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobedac_en_attr == SERDES_IP_CMN_L1_CFG_CMNAPROBEDAC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobedacctrl_block_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobedacctrl_en_attr == SERDES_IP_CMN_L1_CFG_CMNAPROBEDACCTRL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobedacctrl_mask_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobedacctrl_rotate_left_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobedacctrl_tstbus_clkdiv_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnbias_icc20uadj_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnbias_icc80uadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnbias_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnbias_termcal_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnbscan_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnbshihyst_attr == SERDES_IP_CMN_L1_CFG_CMNBSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_bg_en_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_bg_one_step_cal_en_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_fg_inc_cal_en_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_fg_one_step_cal_en_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_finish_side_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_initval_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_invert_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_restore_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_round_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_runcount_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_signmagen_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetmeas_req_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_SYNTHDUTYOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncaldacbg_abort_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncaldacbg_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncaldacbg_ready_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncaldacfsm_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncaldacfsm_synthdutyoffsetfsm_clear_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncaldacfsm_synthdutyoffsetfsm_init_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncaldacfsm_synthdutyoffsetfsm_req_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncaldacsynthdutyoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALDACSYNTHDUTYOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncaldacsynthdutyoffsetfsmout_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALDACSYNTHDUTYOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalptr_pstate_rcomp_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalptr_pstate_synthdutyoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalptr_quad_rcomp_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalptr_quad_regopampoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalptr_quad_synthdutyoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_biastrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_cap_tune_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_divrate_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_mode_select_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_ref_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMP_REF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_rx_term_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMP_RX_TERM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_tfr_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMP_TFR_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_tx_term_pd_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMP_TX_TERM_PD_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_tx_term_pu_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMP_TX_TERM_PU_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_txterm_nmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_txterm_pmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_clear_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_code_delay_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_init_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rcomp_tfr_init_cal_value_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rcomp_tfr_max_value_attr == 4'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rcomp_tfr_min_value_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rcomp_txpd_valid_code_lut_vf00_attr == 32'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rcomp_txpd_valid_code_lut_vf01_attr == 32'd4246868100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rcomp_txpu_valid_code_lut_vf00_attr == 32'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rcomp_txpu_valid_code_lut_vf01_attr == 32'd4246868100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_req_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rx_comp_inv_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_RX_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rx_init_cal_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rx_initval_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rx_step_sign_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_RX_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rx_termcode_delta_lut_attr == 31'd24084352
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tfr_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tfr_comp_inv_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_TFR_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tfr_initval_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tfr_step_sign_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_TFR_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tfr_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_time_comp_config_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_time_lpfsetup_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_time_mode_setup_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_time_reset_release_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_time_sample_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tx_pd_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tx_pd_init_cal_value_attr == 6'd49
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tx_pd_max_value_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tx_pd_min_value_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tx_pu_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tx_pu_init_cal_value_attr == 6'd49
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tx_pu_max_value_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tx_pu_min_value_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_txpd_comp_inv_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_TXPD_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_txpd_initval_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_txpd_step_sign_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_TXPD_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_txpd_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_txpu_comp_inv_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_TXPU_COMP_INV_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_txpu_initval_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_txpu_step_sign_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_TXPU_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_txpu_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_txterm_pmos_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmaster_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPMASTER_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmaster_rx_locovr_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmaster_tfr_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmaster_txpd_locovr_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmaster_txpu_locovr_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmaster_valid_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPMASTER_VALID_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmeas_dlycount_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffset_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_clear_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_finish_side_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_init_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_invert_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_req_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_runcount_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsmout_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetmeas_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetmeas_req_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_avg_en_attr == SERDES_IP_CMN_L1_CFG_CMNCKM_AVG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_clk_en_attr == SERDES_IP_CMN_L1_CFG_CMNCKM_CLK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_continuous_attr == SERDES_IP_CMN_L1_CFG_CMNCKM_CONTINUOUS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_dig_meas_en_attr == SERDES_IP_CMN_L1_CFG_CMNCKM_DIG_MEAS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_dig_meas_err_clr_attr == SERDES_IP_CMN_L1_CFG_CMNCKM_DIG_MEAS_ERR_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_en_attr == SERDES_IP_CMN_L1_CFG_CMNCKM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_max_thr_attr == 25'd33554431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_meas_ck_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_ref_ck_div_ratio_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_result_clr_attr == SERDES_IP_CMN_L1_CFG_CMNCKM_RESULT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_start_attr == SERDES_IP_CMN_L1_CFG_CMNCKM_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_wdt_interval_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_win_thr_ref_attr == 25'd16777215
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnclk_keepalive_en_b_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnclk_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmndmondac_en_attr == SERDES_IP_CMN_L1_CFG_CMNDMONDAC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnfsm_cken_ovr_attr == SERDES_IP_CMN_L1_CFG_CMNFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnfsm_cken_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_aprobe1_charge_up_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_APROBE1_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_aprobe1_pull_dn_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_APROBE1_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_aprobe1_sense_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_APROBE1_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_aprobe2_charge_up_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_APROBE2_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_aprobe2_pull_dn_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_APROBE2_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_aprobe2_sense_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_APROBE2_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_changeref_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_changeref_val_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_en_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_CMN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_ntl_sel_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_CMN_NTL_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_refckm_charge_up_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_REFCKM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_refckm_pull_dn_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_REFCKM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_refckm_sense_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_REFCKM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_refckp_charge_up_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_REFCKP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_refckp_pull_dn_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_REFCKP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_refckp_sense_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_REFCKP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnpcs_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnpcs_ref_sel_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnpcs_ref_sel_tx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnperfmon_compare_val_start_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnperfmon_compare_val_stop_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnperfmon_en_attr == SERDES_IP_CMN_L1_CFG_CMNPERFMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnperfmon_mask_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprefckbufprelut_delta_attr == 15'd32767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprefckbufprelut_init_termcal_rx_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprefckbufprelut_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNRCOMPREFCKBUFPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprefckbufprelut_termcal_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprefcktxdrvprelut_delta_attr == 15'd4672
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprefcktxdrvprelut_init_termcal_rx_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprefcktxdrvprelut_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNRCOMPREFCKTXDRVPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprefcktxdrvprelut_termcal_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprxdfeprelut_delta_attr == 15'd32767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprxdfeprelut_init_termcal_tfr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprxdfeprelut_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNRCOMPRXDFEPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprxdfeprelut_termcal_tfr_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckbuf_cml_ena_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKBUF_CML_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckbuf_hs_cmos_ena_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKBUF_HS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckbuf_hs_ls_b_path_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKBUF_HS_LS_B_PATH_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckbuf_hs_ref_to_cdrdiv_ena_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKBUF_HS_REF_TO_CDRDIV_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckbuf_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKBUF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckbuf_ls_cmos_ena_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKBUF_LS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckbuf_powersave_b_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKBUF_POWERSAVE_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckbuf_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckbuf_termhiz_b_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKBUF_TERMHIZ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckdrv_powersave_en_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKDRV_POWERSAVE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrefcktxdrv_cdrdiv_en_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKTXDRV_CDRDIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrefcktxdrv_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKTXDRV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrefcktxdrv_termcal_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_en_b_attr == SERDES_IP_CMN_L1_CFG_CMNRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_entry3_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s0q2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s0q3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s1q4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s1q5_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s1q6_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s1q7_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s2q0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_entry2_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_entry3_attr == 13'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_entry4_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_entry5_attr == 13'd62
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_entry6_attr == 13'd390
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_entry7_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s0q2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s0q3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s1q1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s1q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s1q5_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s1q7_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s2q0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_term_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_term_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_term_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_term_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_term_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_term_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_term_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_term_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_keepalive_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_keepalive_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_bias_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_bias_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_refckbuf_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_refckbuf_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_refckbuf_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_refckbuf_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_rxref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_rxref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_rxref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_rxref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_synthdutycomp_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_synthdutycomp_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_synthdutycomp_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_synthdutycomp_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_synthlcslowref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_synthlcslowref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_synthlcslowref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_synthlcslowref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_txref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_txref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_txref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_txref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpurst_regreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpurst_regreset_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpurst_regreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrpurst_regreset_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_aetrcmn_regpwrupacc_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_AETRCMN_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_aetrcmn_regpwrupacc_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_AETRCMN_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_adc_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_adc_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_ADC_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_biasicc_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_biasicc_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_ntl_b_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_ntl_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_refckbuf_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_refckbuf_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_reg_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_reg_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_rxref_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_RXREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_rxref_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_RXREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_synthlcslowref_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_SYNTHLCSLOWREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_synthlcslowref_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_SYNTHLCSLOWREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_txref_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_TXREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_txref_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_TXREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_arstcmn_adc_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_ARSTCMN_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_arstcmn_adc_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_ARSTCMN_ADC_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_arstcmn_aprobedac_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_ARSTCMN_APROBEDAC_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_arstcmn_refcktxdrv_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_ARSTCMN_REFCKTXDRV_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_arstcmn_refcktxdrv_hiz_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_ARSTCMN_REFCKTXDRV_HIZ_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_arstcmn_regreset_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_ARSTCMN_REGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_arstcmn_regreset_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_ARSTCMN_REGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_synthdutycomp_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_SYNTHDUTYCOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_synthdutycomp_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_SYNTHDUTYCOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrxref_dpma_en_attr == SERDES_IP_CMN_L1_CFG_CMNRXREF_DPMA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrxref_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNRXREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnrxref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnspare0_attr == 32'd163
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnspare_attr == 9'd384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_rxlane0_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_rxlane1_timer_attr == 12'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_rxlane2_timer_attr == 12'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_rxlane3_timer_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_synthlcfast_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_synthlcmed_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_synthlcslow_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_txlane0_timer_attr == 12'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_txlane1_timer_attr == 12'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_txlane2_timer_attr == 12'd70
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_txlane3_timer_attr == 12'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthdiv_cdrdiv_en_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHDIV_CDRDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthdiv_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHDIV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthdiv_slowmed_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHDIV_SLOWMED_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthdutyoffsetcal_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHDUTYOFFSETCAL_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthdutyoffsetcal_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHDUTYOFFSETCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthdutysel_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHDUTYSEL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthdutysel_mux_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlccaldac_currentdacdcdmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlccaldac_currentdacdcdmeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlccaldac_currentdacdcdmeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlccaldac_currentdacdcdmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlccaldac_synthdutyoffsetmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlccaldac_tx_disable_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHLCCALDAC_TX_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlccaldacerr_calsynthdutyerr_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHLCCALDACERR_CALSYNTHDUTYERR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlccaldacerr_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHLCCALDACERR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlcslowref_dpma_en_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHLCSLOWREF_DPMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlcslowref_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHLCSLOWREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlcslowref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmntxref_dpma_en_attr == SERDES_IP_CMN_L1_CFG_CMNTXREF_DPMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmntxref_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNTXREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmntxref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_cmnynthdutyselpolarity_attr == SERDES_IP_CMN_L1_CFG_CMNYNTHDUTYSELPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_lbcmn_locovren_attr == SERDES_IP_CMN_L1_CFG_LBCMN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_lbcmn_synthlcslowmedpostdivclk2cdrrefclken_locovr_attr == SERDES_IP_CMN_L1_CFG_LBCMN_SYNTHLCSLOWMEDPOSTDIVCLK2CDRREFCLKEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_rcompmaster_en_locovr_attr == SERDES_IP_CMN_L1_CFG_RCOMPMASTER_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_rcompmaster_locovren_attr == SERDES_IP_CMN_L1_CFG_RCOMPMASTER_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_rcompslave_locovr_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_rcompslave_locovren_attr == SERDES_IP_CMN_L1_CFG_RCOMPSLAVE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_rcompslave_valid_locovr_attr == SERDES_IP_CMN_L1_CFG_RCOMPSLAVE_VALID_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_rcompterm_rx_termcode_base_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_rcompterm_tfr_termcode_base_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_rcompterm_txpd_termcode_base_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_rcompterm_txpu_termcode_base_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmed_locovren_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMED_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmed_txbitclkselect_locovr_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMED_TXBITCLKSELECT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedcaldac_locovren_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMEDCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedcalregopampoffset_locovren_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedcalregopampoffsetfsmout_locovren_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedpcs_locovren_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMEDPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedpcs_postdiv2clk0_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedpcs_postdiv2clk0en_locovr_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMEDPCS_POSTDIV2CLK0EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedpcs_postdivclk0en_locovr_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMEDPCS_POSTDIVCLK0EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedreg_lev_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedreg_locovren_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMEDREG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_bti_div_attr == 7'd54
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_bti_div_rst_attr == SERDES_IP_CMN_L2_CFG_BTI_DIV_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_bti_en_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_bti_static_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmn_pg_disable_attr == SERDES_IP_CMN_L2_CFG_CMN_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmn_scratch_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnadc_req_attr == SERDES_IP_CMN_L2_CFG_CMNADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnapb2strbbridgecfg_acc_ctrl_field_mask_write_en_attr == SERDES_IP_CMN_L2_CFG_CMNAPB2STRBBRIDGECFG_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnapb2strbbridgecfg_force_state_en_attr == SERDES_IP_CMN_L2_CFG_CMNAPB2STRBBRIDGECFG_FORCE_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnapb2strbbridgecfg_force_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnapb2strbbridgecfg_stbl_time_aftr_strb_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnapb2strbbridgecfg_stbl_time_bfr_strb_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnapb2strbbridgecfg_strb_pulse_width_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnapbmaster_timeout_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobe_addr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobe_lastmux_isolate_attr == SERDES_IP_CMN_L2_CFG_CMNAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobeadc_current_direction_attr == SERDES_IP_CMN_L2_CFG_CMNAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobeadc_resistor_enable_attr == SERDES_IP_CMN_L2_CFG_CMNAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobedac_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobedac_en_attr == SERDES_IP_CMN_L2_CFG_CMNAPROBEDAC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobedacctrl_block_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobedacctrl_en_attr == SERDES_IP_CMN_L2_CFG_CMNAPROBEDACCTRL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobedacctrl_mask_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobedacctrl_rotate_left_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobedacctrl_tstbus_clkdiv_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnbias_icc20uadj_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnbias_icc80uadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnbias_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnbias_termcal_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnbscan_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnbshihyst_attr == SERDES_IP_CMN_L2_CFG_CMNBSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_bg_en_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_bg_one_step_cal_en_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_fg_inc_cal_en_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_fg_one_step_cal_en_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_finish_side_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_initval_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_invert_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_restore_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_round_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_runcount_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_signmagen_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetmeas_req_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_SYNTHDUTYOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncaldacbg_abort_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncaldacbg_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncaldacbg_ready_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncaldacfsm_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncaldacfsm_synthdutyoffsetfsm_clear_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncaldacfsm_synthdutyoffsetfsm_init_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncaldacfsm_synthdutyoffsetfsm_req_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncaldacsynthdutyoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALDACSYNTHDUTYOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncaldacsynthdutyoffsetfsmout_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALDACSYNTHDUTYOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalptr_pstate_rcomp_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalptr_pstate_synthdutyoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalptr_quad_rcomp_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalptr_quad_regopampoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalptr_quad_synthdutyoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_biastrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_cap_tune_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_divrate_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_mode_select_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_ref_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMP_REF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_rx_term_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMP_RX_TERM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_tfr_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMP_TFR_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_tx_term_pd_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMP_TX_TERM_PD_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_tx_term_pu_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMP_TX_TERM_PU_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_txterm_nmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_txterm_pmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_clear_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_code_delay_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_init_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rcomp_tfr_init_cal_value_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rcomp_tfr_max_value_attr == 4'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rcomp_tfr_min_value_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rcomp_txpd_valid_code_lut_vf00_attr == 32'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rcomp_txpd_valid_code_lut_vf01_attr == 32'd4246868100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rcomp_txpu_valid_code_lut_vf00_attr == 32'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rcomp_txpu_valid_code_lut_vf01_attr == 32'd4246868100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_req_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rx_comp_inv_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_RX_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rx_init_cal_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rx_initval_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rx_step_sign_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_RX_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rx_termcode_delta_lut_attr == 31'd24084352
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tfr_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tfr_comp_inv_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_TFR_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tfr_initval_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tfr_step_sign_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_TFR_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tfr_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_time_comp_config_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_time_lpfsetup_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_time_mode_setup_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_time_reset_release_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_time_sample_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tx_pd_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tx_pd_init_cal_value_attr == 6'd49
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tx_pd_max_value_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tx_pd_min_value_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tx_pu_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tx_pu_init_cal_value_attr == 6'd49
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tx_pu_max_value_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tx_pu_min_value_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_txpd_comp_inv_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_TXPD_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_txpd_initval_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_txpd_step_sign_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_TXPD_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_txpd_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_txpu_comp_inv_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_TXPU_COMP_INV_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_txpu_initval_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_txpu_step_sign_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_TXPU_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_txpu_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_txterm_pmos_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmaster_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPMASTER_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmaster_rx_locovr_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmaster_tfr_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmaster_txpd_locovr_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmaster_txpu_locovr_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmaster_valid_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPMASTER_VALID_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmeas_dlycount_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffset_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_clear_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_finish_side_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_init_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_invert_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_req_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_runcount_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsmout_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetmeas_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetmeas_req_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_avg_en_attr == SERDES_IP_CMN_L2_CFG_CMNCKM_AVG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_clk_en_attr == SERDES_IP_CMN_L2_CFG_CMNCKM_CLK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_continuous_attr == SERDES_IP_CMN_L2_CFG_CMNCKM_CONTINUOUS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_dig_meas_en_attr == SERDES_IP_CMN_L2_CFG_CMNCKM_DIG_MEAS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_dig_meas_err_clr_attr == SERDES_IP_CMN_L2_CFG_CMNCKM_DIG_MEAS_ERR_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_en_attr == SERDES_IP_CMN_L2_CFG_CMNCKM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_max_thr_attr == 25'd33554431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_meas_ck_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_ref_ck_div_ratio_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_result_clr_attr == SERDES_IP_CMN_L2_CFG_CMNCKM_RESULT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_start_attr == SERDES_IP_CMN_L2_CFG_CMNCKM_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_wdt_interval_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_win_thr_ref_attr == 25'd16777215
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnclk_keepalive_en_b_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnclk_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmndmondac_en_attr == SERDES_IP_CMN_L2_CFG_CMNDMONDAC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnfsm_cken_ovr_attr == SERDES_IP_CMN_L2_CFG_CMNFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnfsm_cken_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_aprobe1_charge_up_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_APROBE1_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_aprobe1_pull_dn_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_APROBE1_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_aprobe1_sense_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_APROBE1_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_aprobe2_charge_up_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_APROBE2_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_aprobe2_pull_dn_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_APROBE2_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_aprobe2_sense_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_APROBE2_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_changeref_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_changeref_val_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_en_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_CMN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_ntl_sel_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_CMN_NTL_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_refckm_charge_up_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_REFCKM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_refckm_pull_dn_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_REFCKM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_refckm_sense_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_REFCKM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_refckp_charge_up_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_REFCKP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_refckp_pull_dn_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_REFCKP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_refckp_sense_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_REFCKP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnpcs_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnpcs_ref_sel_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnpcs_ref_sel_tx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnperfmon_compare_val_start_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnperfmon_compare_val_stop_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnperfmon_en_attr == SERDES_IP_CMN_L2_CFG_CMNPERFMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnperfmon_mask_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprefckbufprelut_delta_attr == 15'd32767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprefckbufprelut_init_termcal_rx_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprefckbufprelut_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNRCOMPREFCKBUFPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprefckbufprelut_termcal_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprefcktxdrvprelut_delta_attr == 15'd4672
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprefcktxdrvprelut_init_termcal_rx_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprefcktxdrvprelut_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNRCOMPREFCKTXDRVPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprefcktxdrvprelut_termcal_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprxdfeprelut_delta_attr == 15'd32767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprxdfeprelut_init_termcal_tfr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprxdfeprelut_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNRCOMPRXDFEPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprxdfeprelut_termcal_tfr_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckbuf_cml_ena_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKBUF_CML_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckbuf_hs_cmos_ena_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKBUF_HS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckbuf_hs_ls_b_path_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKBUF_HS_LS_B_PATH_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckbuf_hs_ref_to_cdrdiv_ena_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKBUF_HS_REF_TO_CDRDIV_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckbuf_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKBUF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckbuf_ls_cmos_ena_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKBUF_LS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckbuf_powersave_b_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKBUF_POWERSAVE_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckbuf_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckbuf_termhiz_b_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKBUF_TERMHIZ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckdrv_powersave_en_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKDRV_POWERSAVE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrefcktxdrv_cdrdiv_en_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKTXDRV_CDRDIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrefcktxdrv_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKTXDRV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrefcktxdrv_termcal_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_en_b_attr == SERDES_IP_CMN_L2_CFG_CMNRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_entry3_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s0q2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s0q3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s1q4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s1q5_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s1q6_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s1q7_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s2q0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_entry2_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_entry3_attr == 13'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_entry4_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_entry5_attr == 13'd62
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_entry6_attr == 13'd390
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_entry7_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s0q2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s0q3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s1q1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s1q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s1q5_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s1q7_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s2q0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_term_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_term_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_term_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_term_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_term_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_term_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_term_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_term_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_keepalive_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_keepalive_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_bias_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_bias_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_refckbuf_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_refckbuf_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_refckbuf_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_refckbuf_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_rxref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_rxref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_rxref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_rxref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_synthdutycomp_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_synthdutycomp_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_synthdutycomp_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_synthdutycomp_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_synthlcslowref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_synthlcslowref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_synthlcslowref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_synthlcslowref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_txref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_txref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_txref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_txref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpurst_regreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpurst_regreset_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpurst_regreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrpurst_regreset_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_aetrcmn_regpwrupacc_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_AETRCMN_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_aetrcmn_regpwrupacc_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_AETRCMN_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_adc_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_adc_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_ADC_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_biasicc_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_biasicc_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_ntl_b_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_ntl_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_refckbuf_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_refckbuf_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_reg_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_reg_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_rxref_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_RXREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_rxref_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_RXREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_synthlcslowref_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_SYNTHLCSLOWREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_synthlcslowref_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_SYNTHLCSLOWREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_txref_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_TXREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_txref_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_TXREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_arstcmn_adc_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_ARSTCMN_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_arstcmn_adc_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_ARSTCMN_ADC_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_arstcmn_aprobedac_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_ARSTCMN_APROBEDAC_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_arstcmn_refcktxdrv_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_ARSTCMN_REFCKTXDRV_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_arstcmn_refcktxdrv_hiz_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_ARSTCMN_REFCKTXDRV_HIZ_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_arstcmn_regreset_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_ARSTCMN_REGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_arstcmn_regreset_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_ARSTCMN_REGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_synthdutycomp_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_SYNTHDUTYCOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_synthdutycomp_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_SYNTHDUTYCOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrxref_dpma_en_attr == SERDES_IP_CMN_L2_CFG_CMNRXREF_DPMA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrxref_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNRXREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnrxref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnspare0_attr == 32'd163
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnspare_attr == 9'd384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_rxlane0_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_rxlane1_timer_attr == 12'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_rxlane2_timer_attr == 12'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_rxlane3_timer_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_synthlcfast_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_synthlcmed_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_synthlcslow_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_txlane0_timer_attr == 12'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_txlane1_timer_attr == 12'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_txlane2_timer_attr == 12'd70
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_txlane3_timer_attr == 12'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthdiv_cdrdiv_en_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHDIV_CDRDIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthdiv_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHDIV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthdiv_slowmed_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHDIV_SLOWMED_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthdutyoffsetcal_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHDUTYOFFSETCAL_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthdutyoffsetcal_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHDUTYOFFSETCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthdutysel_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHDUTYSEL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthdutysel_mux_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlccaldac_currentdacdcdmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlccaldac_currentdacdcdmeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlccaldac_currentdacdcdmeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlccaldac_currentdacdcdmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlccaldac_synthdutyoffsetmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlccaldac_tx_disable_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHLCCALDAC_TX_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlccaldacerr_calsynthdutyerr_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHLCCALDACERR_CALSYNTHDUTYERR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlccaldacerr_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHLCCALDACERR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlcslowref_dpma_en_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHLCSLOWREF_DPMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlcslowref_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHLCSLOWREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlcslowref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmntxref_dpma_en_attr == SERDES_IP_CMN_L2_CFG_CMNTXREF_DPMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmntxref_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNTXREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmntxref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_cmnynthdutyselpolarity_attr == SERDES_IP_CMN_L2_CFG_CMNYNTHDUTYSELPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_lbcmn_locovren_attr == SERDES_IP_CMN_L2_CFG_LBCMN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_lbcmn_synthlcslowmedpostdivclk2cdrrefclken_locovr_attr == SERDES_IP_CMN_L2_CFG_LBCMN_SYNTHLCSLOWMEDPOSTDIVCLK2CDRREFCLKEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_rcompmaster_en_locovr_attr == SERDES_IP_CMN_L2_CFG_RCOMPMASTER_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_rcompmaster_locovren_attr == SERDES_IP_CMN_L2_CFG_RCOMPMASTER_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_rcompslave_locovr_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_rcompslave_locovren_attr == SERDES_IP_CMN_L2_CFG_RCOMPSLAVE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_rcompslave_valid_locovr_attr == SERDES_IP_CMN_L2_CFG_RCOMPSLAVE_VALID_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_rcompterm_rx_termcode_base_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_rcompterm_tfr_termcode_base_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_rcompterm_txpd_termcode_base_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_rcompterm_txpu_termcode_base_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmed_locovren_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMED_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmed_txbitclkselect_locovr_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMED_TXBITCLKSELECT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedcaldac_locovren_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMEDCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedcalregopampoffset_locovren_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedcalregopampoffsetfsmout_locovren_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedpcs_locovren_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMEDPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedpcs_postdiv2clk0_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedpcs_postdiv2clk0en_locovr_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMEDPCS_POSTDIV2CLK0EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedpcs_postdivclk0en_locovr_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMEDPCS_POSTDIVCLK0EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedreg_lev_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedreg_locovren_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMEDREG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_bti_div_attr == 7'd54
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_bti_div_rst_attr == SERDES_IP_CMN_L3_CFG_BTI_DIV_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_bti_en_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_bti_static_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmn_pg_disable_attr == SERDES_IP_CMN_L3_CFG_CMN_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmn_scratch_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnadc_req_attr == SERDES_IP_CMN_L3_CFG_CMNADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnapb2strbbridgecfg_acc_ctrl_field_mask_write_en_attr == SERDES_IP_CMN_L3_CFG_CMNAPB2STRBBRIDGECFG_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnapb2strbbridgecfg_force_state_en_attr == SERDES_IP_CMN_L3_CFG_CMNAPB2STRBBRIDGECFG_FORCE_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnapb2strbbridgecfg_force_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnapb2strbbridgecfg_stbl_time_aftr_strb_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnapb2strbbridgecfg_stbl_time_bfr_strb_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnapb2strbbridgecfg_strb_pulse_width_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnapbmaster_timeout_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobe_addr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobe_lastmux_isolate_attr == SERDES_IP_CMN_L3_CFG_CMNAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobeadc_current_direction_attr == SERDES_IP_CMN_L3_CFG_CMNAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobeadc_resistor_enable_attr == SERDES_IP_CMN_L3_CFG_CMNAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobedac_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobedac_en_attr == SERDES_IP_CMN_L3_CFG_CMNAPROBEDAC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobedacctrl_block_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobedacctrl_en_attr == SERDES_IP_CMN_L3_CFG_CMNAPROBEDACCTRL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobedacctrl_mask_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobedacctrl_rotate_left_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobedacctrl_tstbus_clkdiv_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnbias_icc20uadj_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnbias_icc80uadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnbias_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnbias_termcal_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnbscan_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnbshihyst_attr == SERDES_IP_CMN_L3_CFG_CMNBSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_bg_en_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_bg_one_step_cal_en_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_fg_inc_cal_en_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_fg_one_step_cal_en_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_finish_side_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_initval_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_invert_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_restore_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_round_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_runcount_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_signmagen_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetmeas_req_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_SYNTHDUTYOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncaldacbg_abort_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncaldacbg_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncaldacbg_ready_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncaldacfsm_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncaldacfsm_synthdutyoffsetfsm_clear_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncaldacfsm_synthdutyoffsetfsm_init_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncaldacfsm_synthdutyoffsetfsm_req_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncaldacsynthdutyoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALDACSYNTHDUTYOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncaldacsynthdutyoffsetfsmout_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALDACSYNTHDUTYOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalptr_pstate_rcomp_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalptr_pstate_synthdutyoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalptr_quad_rcomp_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalptr_quad_regopampoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalptr_quad_synthdutyoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_biastrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_cap_tune_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_divrate_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_mode_select_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_ref_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMP_REF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_rx_term_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMP_RX_TERM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_tfr_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMP_TFR_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_tx_term_pd_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMP_TX_TERM_PD_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_tx_term_pu_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMP_TX_TERM_PU_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_txterm_nmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_txterm_pmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_clear_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_code_delay_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_init_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rcomp_tfr_init_cal_value_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rcomp_tfr_max_value_attr == 4'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rcomp_tfr_min_value_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rcomp_txpd_valid_code_lut_vf00_attr == 32'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rcomp_txpd_valid_code_lut_vf01_attr == 32'd4246868100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rcomp_txpu_valid_code_lut_vf00_attr == 32'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rcomp_txpu_valid_code_lut_vf01_attr == 32'd4246868100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_req_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rx_comp_inv_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_RX_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rx_init_cal_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rx_initval_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rx_step_sign_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_RX_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rx_termcode_delta_lut_attr == 31'd24084352
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tfr_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tfr_comp_inv_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_TFR_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tfr_initval_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tfr_step_sign_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_TFR_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tfr_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_time_comp_config_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_time_lpfsetup_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_time_mode_setup_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_time_reset_release_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_time_sample_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tx_pd_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tx_pd_init_cal_value_attr == 6'd49
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tx_pd_max_value_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tx_pd_min_value_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tx_pu_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tx_pu_init_cal_value_attr == 6'd49
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tx_pu_max_value_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tx_pu_min_value_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_txpd_comp_inv_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_TXPD_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_txpd_initval_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_txpd_step_sign_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_TXPD_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_txpd_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_txpu_comp_inv_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_TXPU_COMP_INV_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_txpu_initval_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_txpu_step_sign_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_TXPU_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_txpu_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_txterm_pmos_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmaster_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPMASTER_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmaster_rx_locovr_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmaster_tfr_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmaster_txpd_locovr_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmaster_txpu_locovr_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmaster_valid_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPMASTER_VALID_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmeas_dlycount_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffset_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_clear_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_finish_side_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_init_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_invert_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_req_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_runcount_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsmout_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetmeas_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetmeas_req_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_avg_en_attr == SERDES_IP_CMN_L3_CFG_CMNCKM_AVG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_clk_en_attr == SERDES_IP_CMN_L3_CFG_CMNCKM_CLK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_continuous_attr == SERDES_IP_CMN_L3_CFG_CMNCKM_CONTINUOUS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_dig_meas_en_attr == SERDES_IP_CMN_L3_CFG_CMNCKM_DIG_MEAS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_dig_meas_err_clr_attr == SERDES_IP_CMN_L3_CFG_CMNCKM_DIG_MEAS_ERR_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_en_attr == SERDES_IP_CMN_L3_CFG_CMNCKM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_max_thr_attr == 25'd33554431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_meas_ck_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_ref_ck_div_ratio_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_result_clr_attr == SERDES_IP_CMN_L3_CFG_CMNCKM_RESULT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_start_attr == SERDES_IP_CMN_L3_CFG_CMNCKM_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_wdt_interval_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_win_thr_ref_attr == 25'd16777215
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnclk_keepalive_en_b_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnclk_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmndmondac_en_attr == SERDES_IP_CMN_L3_CFG_CMNDMONDAC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnfsm_cken_ovr_attr == SERDES_IP_CMN_L3_CFG_CMNFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnfsm_cken_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_aprobe1_charge_up_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_APROBE1_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_aprobe1_pull_dn_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_APROBE1_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_aprobe1_sense_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_APROBE1_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_aprobe2_charge_up_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_APROBE2_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_aprobe2_pull_dn_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_APROBE2_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_aprobe2_sense_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_APROBE2_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_changeref_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_changeref_val_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_en_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_CMN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_ntl_sel_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_CMN_NTL_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_refckm_charge_up_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_REFCKM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_refckm_pull_dn_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_REFCKM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_refckm_sense_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_REFCKM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_refckp_charge_up_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_REFCKP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_refckp_pull_dn_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_REFCKP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_refckp_sense_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_REFCKP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnpcs_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnpcs_ref_sel_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnpcs_ref_sel_tx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnperfmon_compare_val_start_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnperfmon_compare_val_stop_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnperfmon_en_attr == SERDES_IP_CMN_L3_CFG_CMNPERFMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnperfmon_mask_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprefckbufprelut_delta_attr == 15'd32767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprefckbufprelut_init_termcal_rx_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprefckbufprelut_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNRCOMPREFCKBUFPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprefckbufprelut_termcal_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprefcktxdrvprelut_delta_attr == 15'd4672
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprefcktxdrvprelut_init_termcal_rx_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprefcktxdrvprelut_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNRCOMPREFCKTXDRVPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprefcktxdrvprelut_termcal_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprxdfeprelut_delta_attr == 15'd32767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprxdfeprelut_init_termcal_tfr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprxdfeprelut_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNRCOMPRXDFEPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprxdfeprelut_termcal_tfr_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckbuf_cml_ena_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKBUF_CML_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckbuf_hs_cmos_ena_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKBUF_HS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckbuf_hs_ls_b_path_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKBUF_HS_LS_B_PATH_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckbuf_hs_ref_to_cdrdiv_ena_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKBUF_HS_REF_TO_CDRDIV_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckbuf_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKBUF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckbuf_ls_cmos_ena_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKBUF_LS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckbuf_powersave_b_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKBUF_POWERSAVE_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckbuf_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckbuf_termhiz_b_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKBUF_TERMHIZ_B_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckdrv_powersave_en_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKDRV_POWERSAVE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrefcktxdrv_cdrdiv_en_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKTXDRV_CDRDIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrefcktxdrv_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKTXDRV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrefcktxdrv_termcal_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_en_b_attr == SERDES_IP_CMN_L3_CFG_CMNRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_entry3_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s0q2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s0q3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s1q4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s1q5_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s1q6_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s1q7_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s2q0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_entry2_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_entry3_attr == 13'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_entry4_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_entry5_attr == 13'd62
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_entry6_attr == 13'd390
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_entry7_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s0q2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s0q3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s1q1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s1q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s1q5_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s1q7_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s2q0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_term_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_term_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_term_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_term_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_term_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_term_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_term_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_term_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_keepalive_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_keepalive_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_bias_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_bias_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_refckbuf_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_refckbuf_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_refckbuf_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_refckbuf_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_rxref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_rxref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_rxref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_rxref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_synthdutycomp_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_synthdutycomp_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_synthdutycomp_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_synthdutycomp_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_synthlcslowref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_synthlcslowref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_synthlcslowref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_synthlcslowref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_txref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_txref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_txref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_txref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpurst_regreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpurst_regreset_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpurst_regreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrpurst_regreset_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_aetrcmn_regpwrupacc_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_AETRCMN_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_aetrcmn_regpwrupacc_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_AETRCMN_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_adc_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_adc_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_ADC_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_biasicc_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_biasicc_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_ntl_b_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_ntl_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_refckbuf_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_refckbuf_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_reg_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_reg_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_rxref_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_RXREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_rxref_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_RXREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_synthlcslowref_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_SYNTHLCSLOWREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_synthlcslowref_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_SYNTHLCSLOWREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_txref_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_TXREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_txref_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_TXREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_arstcmn_adc_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_ARSTCMN_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_arstcmn_adc_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_ARSTCMN_ADC_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_arstcmn_aprobedac_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_ARSTCMN_APROBEDAC_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_arstcmn_refcktxdrv_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_ARSTCMN_REFCKTXDRV_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_arstcmn_refcktxdrv_hiz_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_ARSTCMN_REFCKTXDRV_HIZ_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_arstcmn_regreset_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_ARSTCMN_REGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_arstcmn_regreset_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_ARSTCMN_REGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_synthdutycomp_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_SYNTHDUTYCOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_synthdutycomp_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_SYNTHDUTYCOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrxref_dpma_en_attr == SERDES_IP_CMN_L3_CFG_CMNRXREF_DPMA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrxref_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNRXREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnrxref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnspare0_attr == 32'd163
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnspare_attr == 9'd384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_rxlane0_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_rxlane1_timer_attr == 12'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_rxlane2_timer_attr == 12'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_rxlane3_timer_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_synthlcfast_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_synthlcmed_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_synthlcslow_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_txlane0_timer_attr == 12'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_txlane1_timer_attr == 12'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_txlane2_timer_attr == 12'd70
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_txlane3_timer_attr == 12'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthdiv_cdrdiv_en_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHDIV_CDRDIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthdiv_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHDIV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthdiv_slowmed_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHDIV_SLOWMED_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthdutyoffsetcal_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHDUTYOFFSETCAL_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthdutyoffsetcal_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHDUTYOFFSETCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthdutysel_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHDUTYSEL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthdutysel_mux_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlccaldac_currentdacdcdmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlccaldac_currentdacdcdmeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlccaldac_currentdacdcdmeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlccaldac_currentdacdcdmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlccaldac_synthdutyoffsetmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlccaldac_tx_disable_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHLCCALDAC_TX_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlccaldacerr_calsynthdutyerr_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHLCCALDACERR_CALSYNTHDUTYERR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlccaldacerr_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHLCCALDACERR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlcslowref_dpma_en_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHLCSLOWREF_DPMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlcslowref_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHLCSLOWREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlcslowref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmntxref_dpma_en_attr == SERDES_IP_CMN_L3_CFG_CMNTXREF_DPMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmntxref_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNTXREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmntxref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_cmnynthdutyselpolarity_attr == SERDES_IP_CMN_L3_CFG_CMNYNTHDUTYSELPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_lbcmn_locovren_attr == SERDES_IP_CMN_L3_CFG_LBCMN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_lbcmn_synthlcslowmedpostdivclk2cdrrefclken_locovr_attr == SERDES_IP_CMN_L3_CFG_LBCMN_SYNTHLCSLOWMEDPOSTDIVCLK2CDRREFCLKEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_rcompmaster_en_locovr_attr == SERDES_IP_CMN_L3_CFG_RCOMPMASTER_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_rcompmaster_locovren_attr == SERDES_IP_CMN_L3_CFG_RCOMPMASTER_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_rcompslave_locovr_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_rcompslave_locovren_attr == SERDES_IP_CMN_L3_CFG_RCOMPSLAVE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_rcompslave_valid_locovr_attr == SERDES_IP_CMN_L3_CFG_RCOMPSLAVE_VALID_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_rcompterm_rx_termcode_base_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_rcompterm_tfr_termcode_base_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_rcompterm_txpd_termcode_base_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_rcompterm_txpu_termcode_base_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmed_locovren_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMED_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmed_txbitclkselect_locovr_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMED_TXBITCLKSELECT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedcaldac_locovren_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMEDCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedcalregopampoffset_locovren_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedcalregopampoffsetfsmout_locovren_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedpcs_locovren_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMEDPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedpcs_postdiv2clk0_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedpcs_postdiv2clk0en_locovr_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMEDPCS_POSTDIV2CLK0EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedpcs_postdivclk0en_locovr_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMEDPCS_POSTDIVCLK0EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedreg_lev_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedreg_locovren_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMEDREG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_clock_ratio_cnt_max_timer_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_clock_ratio_cnt_min_timer_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_enable_flex_override_en_attr == SERDES_IP_FLEX_FW_LOADER_L0_CFG_CFG_ENABLE_FLEX_OVERRIDE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_enable_flex_override_value_attr == SERDES_IP_FLEX_FW_LOADER_L0_CFG_CFG_ENABLE_FLEX_OVERRIDE_VALUE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_flex_gpi_attr == 17'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_gp_lvl_attr == SERDES_IP_FLEX_FW_LOADER_L0_CFG_CFG_GP_LVL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_gp_pls_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_lms_cont_dis_attr == SERDES_IP_FLEX_FW_LOADER_L0_CFG_CFG_LMS_CONT_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_local_tp_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_periodical_rst_dis_attr == SERDES_IP_FLEX_FW_LOADER_L0_CFG_CFG_PERIODICAL_RST_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_spa_sat_dir_attr == SERDES_IP_FLEX_FW_LOADER_L0_CFG_CFG_SPA_SAT_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_vg_inv_cb_attr == SERDES_IP_FLEX_FW_LOADER_L0_CFG_CFG_VG_INV_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l0_cfg_data_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l0_cfg_fw_loader_en_attr == SERDES_IP_FLEX_FW_LOADER_L0_CFG_FW_LOADER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l0_cfg_offset_addr_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l0_cfg_single_mode_en_attr == SERDES_IP_FLEX_FW_LOADER_L0_CFG_SINGLE_MODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_clock_ratio_cnt_max_timer_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_clock_ratio_cnt_min_timer_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_enable_flex_override_en_attr == SERDES_IP_FLEX_FW_LOADER_L1_CFG_CFG_ENABLE_FLEX_OVERRIDE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_enable_flex_override_value_attr == SERDES_IP_FLEX_FW_LOADER_L1_CFG_CFG_ENABLE_FLEX_OVERRIDE_VALUE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_flex_gpi_attr == 17'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_gp_lvl_attr == SERDES_IP_FLEX_FW_LOADER_L1_CFG_CFG_GP_LVL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_gp_pls_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_lms_cont_dis_attr == SERDES_IP_FLEX_FW_LOADER_L1_CFG_CFG_LMS_CONT_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_local_tp_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_periodical_rst_dis_attr == SERDES_IP_FLEX_FW_LOADER_L1_CFG_CFG_PERIODICAL_RST_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_spa_sat_dir_attr == SERDES_IP_FLEX_FW_LOADER_L1_CFG_CFG_SPA_SAT_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_vg_inv_cb_attr == SERDES_IP_FLEX_FW_LOADER_L1_CFG_CFG_VG_INV_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l1_cfg_data_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l1_cfg_fw_loader_en_attr == SERDES_IP_FLEX_FW_LOADER_L1_CFG_FW_LOADER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l1_cfg_offset_addr_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l1_cfg_single_mode_en_attr == SERDES_IP_FLEX_FW_LOADER_L1_CFG_SINGLE_MODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_clock_ratio_cnt_max_timer_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_clock_ratio_cnt_min_timer_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_enable_flex_override_en_attr == SERDES_IP_FLEX_FW_LOADER_L2_CFG_CFG_ENABLE_FLEX_OVERRIDE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_enable_flex_override_value_attr == SERDES_IP_FLEX_FW_LOADER_L2_CFG_CFG_ENABLE_FLEX_OVERRIDE_VALUE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_flex_gpi_attr == 17'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_gp_lvl_attr == SERDES_IP_FLEX_FW_LOADER_L2_CFG_CFG_GP_LVL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_gp_pls_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_lms_cont_dis_attr == SERDES_IP_FLEX_FW_LOADER_L2_CFG_CFG_LMS_CONT_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_local_tp_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_periodical_rst_dis_attr == SERDES_IP_FLEX_FW_LOADER_L2_CFG_CFG_PERIODICAL_RST_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_spa_sat_dir_attr == SERDES_IP_FLEX_FW_LOADER_L2_CFG_CFG_SPA_SAT_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_vg_inv_cb_attr == SERDES_IP_FLEX_FW_LOADER_L2_CFG_CFG_VG_INV_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l2_cfg_data_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l2_cfg_fw_loader_en_attr == SERDES_IP_FLEX_FW_LOADER_L2_CFG_FW_LOADER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l2_cfg_offset_addr_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l2_cfg_single_mode_en_attr == SERDES_IP_FLEX_FW_LOADER_L2_CFG_SINGLE_MODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_clock_ratio_cnt_max_timer_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_clock_ratio_cnt_min_timer_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_enable_flex_override_en_attr == SERDES_IP_FLEX_FW_LOADER_L3_CFG_CFG_ENABLE_FLEX_OVERRIDE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_enable_flex_override_value_attr == SERDES_IP_FLEX_FW_LOADER_L3_CFG_CFG_ENABLE_FLEX_OVERRIDE_VALUE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_flex_gpi_attr == 17'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_gp_lvl_attr == SERDES_IP_FLEX_FW_LOADER_L3_CFG_CFG_GP_LVL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_gp_pls_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_lms_cont_dis_attr == SERDES_IP_FLEX_FW_LOADER_L3_CFG_CFG_LMS_CONT_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_local_tp_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_periodical_rst_dis_attr == SERDES_IP_FLEX_FW_LOADER_L3_CFG_CFG_PERIODICAL_RST_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_spa_sat_dir_attr == SERDES_IP_FLEX_FW_LOADER_L3_CFG_CFG_SPA_SAT_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_vg_inv_cb_attr == SERDES_IP_FLEX_FW_LOADER_L3_CFG_CFG_VG_INV_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l3_cfg_data_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l3_cfg_fw_loader_en_attr == SERDES_IP_FLEX_FW_LOADER_L3_CFG_FW_LOADER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l3_cfg_offset_addr_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_flex_fw_loader_l3_cfg_single_mode_en_attr == SERDES_IP_FLEX_FW_LOADER_L3_CFG_SINGLE_MODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_cpi_port_mode_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_dfx_secure_visa_nt_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_dfx_secure_visa_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_DFX_SECURE_VISA_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_p_vdd_pwrgood_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_P_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_p_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_P_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pa_vdd_ehv_pwrgood_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pa_vdd_ehv_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pa_vdd_pwrgood_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PA_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pa_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PA_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_andme_en_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_ANDME_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_andme_en_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_ANDME_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bist_modesel_l0_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bist_modesel_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BIST_MODESEL_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_capturedr_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_CAPTUREDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_clamp_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_CLAMP_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_exit1dr_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_EXIT1DR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_exit2dr_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_EXIT2DR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_extest_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_EXTEST_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_extestpulse_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_EXTESTPULSE_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_extesttrain_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_EXTESTTRAIN_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_highz_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_HIGHZ_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_mode_en_nt_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_MODE_EN_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_preload_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_PRELOAD_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_runtestidle_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_RUNTESTIDLE_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_shiftdr_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_SHIFTDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_txinvert_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_TXINVERT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_updatedr_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_UPDATEDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_cmn_force_pup_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_CMN_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_cmn_force_pup_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_CMN_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_disconnect_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_DISCONNECT_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_disconnect_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_DISCONNECT_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_isolate_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_ISOLATE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_isolate_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_ISOLATE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_jtagid_nt_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_JTAGID_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_jtagslvid_nt_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_JTAGSLVID_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_lb_cdrclk2txen_l0_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_LB_CDRCLK2TXEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_lb_cdrclk2txen_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_LB_CDRCLK2TXEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_lb_parrx2txtimeden_l0_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_LB_PARRX2TXTIMEDEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_lb_parrx2txtimeden_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_LB_PARRX2TXTIMEDEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_lb_tx2rxbuftimeden_l0_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_LB_TX2RXBUFTIMEDEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_lb_tx2rxbuftimeden_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_LB_TX2RXBUFTIMEDEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_lfps_en_l0_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_LFPS_EN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_lfps_en_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_LFPS_EN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_mode_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_MODE_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_mode_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_MODE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_pcie_l1d1_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_PCIE_L1D1_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_pcie_l1d1_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_PCIE_L1D1_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_pcie_l1d2_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_PCIE_L1D2_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_pcie_l1d2_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_PCIE_L1D2_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rcomp_slave_en_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RCOMP_SLAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rcomp_slave_en_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RCOMP_SLAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rcomp_slave_nt_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rcomp_slave_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RCOMP_SLAVE_NT_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rcomp_slave_valid_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RCOMP_SLAVE_VALID_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rcomp_slave_valid_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RCOMP_SLAVE_VALID_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_ref_sel_rx_nt_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_ref_sel_rx_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_REF_SEL_RX_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_ref_sel_tx_nt_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_ref_sel_tx_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_REF_SEL_TX_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_ref_term_hiz_en_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_REF_TERM_HIZ_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_ref_term_hiz_en_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_REF_TERM_HIZ_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxbist_en_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXBIST_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxbist_en_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXBIST_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxbitslip_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXBITSLIP_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxbitslip_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXBITSLIP_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeiosdetectstat_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEIOSDETECTSTAT_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeiosdetectstat_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEIOSDETECTSTAT_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeq_clr_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEQ_CLR_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeq_clr_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEQ_CLR_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeq_precal_code_sel_l0_nt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeq_precal_code_sel_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEQ_PRECAL_CODE_SEL_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeq_start_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEQ_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeq_start_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEQ_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeq_static_en_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEQ_STATIC_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeq_static_en_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEQ_STATIC_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeyediag_start_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEYEDIAG_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeyediag_start_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEYEDIAG_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_direction_l0_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXMARGIN_DIRECTION_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_direction_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXMARGIN_DIRECTION_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_mode_l0_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXMARGIN_MODE_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_mode_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXMARGIN_MODE_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_offset_change_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXMARGIN_OFFSET_CHANGE_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_offset_change_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXMARGIN_OFFSET_CHANGE_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_offset_l0_nt_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_offset_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXMARGIN_OFFSET_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_start_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXMARGIN_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_start_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXMARGIN_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxpam_gray_en_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXPAM_GRAY_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxpam_gray_en_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXPAM_GRAY_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxpam_precode_en_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXPAM_PRECODE_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxpam_precode_en_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXPAM_PRECODE_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxrate_l0_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxrate_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxterm_hiz_en_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXTERM_HIZ_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxterm_hiz_en_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXTERM_HIZ_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxwidth_l0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxwidth_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXWIDTH_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_spare_nt_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_spare_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SPARE_NT_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcfast_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcfast_divrate_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SYNTHLCFAST_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcfast_force_pup_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SYNTHLCFAST_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcfast_force_pup_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SYNTHLCFAST_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcmed_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcmed_divrate_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SYNTHLCMED_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcmed_force_pup_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SYNTHLCMED_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcmed_force_pup_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SYNTHLCMED_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcslow_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcslow_divrate_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SYNTHLCSLOW_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcslow_force_pup_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SYNTHLCSLOW_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcslow_force_pup_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SYNTHLCSLOW_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txbeacon_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXBEACON_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txbeacon_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXBEACON_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txbist_en_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXBIST_EN_L0_A_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txbist_en_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXBIST_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txclkdivrate_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txclkdivrate_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXCLKDIVRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdetectrx_req_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXDETECTRX_REQ_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdetectrx_req_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXDETECTRX_REQ_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_levn_l0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_levn_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXDRV_LEVN_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_levnm1_l0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_levnm1_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXDRV_LEVNM1_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_levnm2_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_levnm2_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXDRV_LEVNM2_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_levnp1_l0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_levnp1_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXDRV_LEVNP1_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_slew_l0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_slew_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXDRV_SLEW_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_spare_l0_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_spare_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXDRV_SPARE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txenable_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXENABLE_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txenable_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXENABLE_L0_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txpam_gray_en_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXPAM_GRAY_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txpam_gray_en_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXPAM_GRAY_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txpam_precode_en_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXPAM_PRECODE_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txpam_precode_en_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXPAM_PRECODE_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txrate_l0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txrate_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txwidth_l0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txwidth_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXWIDTH_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_visa_unit_id_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_ictl_visa_unit_id_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_VISA_UNIT_ID_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_idat_dfx_obs_dig_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_idat_visa_serial_cfg_in_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_irst_apb_mem_b_attr == SERDES_IP_IF_L0_CFG_IRST_APB_MEM_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_irst_apb_mem_b_reg_en_attr == SERDES_IP_IF_L0_CFG_IRST_APB_MEM_B_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_irst_pcs_rx_l0_b_a_attr == SERDES_IP_IF_L0_CFG_IRST_PCS_RX_L0_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_irst_pcs_rx_l0_b_a_reg_en_attr == SERDES_IP_IF_L0_CFG_IRST_PCS_RX_L0_B_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_irst_pcs_tstbus_b_a_attr == SERDES_IP_IF_L0_CFG_IRST_PCS_TSTBUS_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_irst_pcs_tx_l0_b_a_attr == SERDES_IP_IF_L0_CFG_IRST_PCS_TX_L0_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_irst_pcs_tx_l0_b_a_reg_en_attr == SERDES_IP_IF_L0_CFG_IRST_PCS_TX_L0_B_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l0_cfg_irst_visa_reset_b_a_attr == SERDES_IP_IF_L0_CFG_IRST_VISA_RESET_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_cpi_port_mode_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_dfx_secure_visa_nt_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_dfx_secure_visa_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_DFX_SECURE_VISA_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_p_vdd_pwrgood_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_P_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_p_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_P_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pa_vdd_ehv_pwrgood_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pa_vdd_ehv_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pa_vdd_pwrgood_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PA_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pa_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PA_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_andme_en_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_ANDME_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_andme_en_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_ANDME_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bist_modesel_l0_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bist_modesel_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BIST_MODESEL_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_capturedr_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_CAPTUREDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_clamp_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_CLAMP_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_exit1dr_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_EXIT1DR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_exit2dr_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_EXIT2DR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_extest_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_EXTEST_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_extestpulse_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_EXTESTPULSE_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_extesttrain_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_EXTESTTRAIN_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_highz_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_HIGHZ_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_mode_en_nt_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_MODE_EN_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_preload_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_PRELOAD_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_runtestidle_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_RUNTESTIDLE_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_shiftdr_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_SHIFTDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_txinvert_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_TXINVERT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_updatedr_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_UPDATEDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_cmn_force_pup_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_CMN_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_cmn_force_pup_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_CMN_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_disconnect_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_DISCONNECT_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_disconnect_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_DISCONNECT_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_isolate_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_ISOLATE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_isolate_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_ISOLATE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_jtagid_nt_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_JTAGID_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_jtagslvid_nt_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_JTAGSLVID_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_lb_cdrclk2txen_l0_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_LB_CDRCLK2TXEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_lb_cdrclk2txen_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_LB_CDRCLK2TXEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_lb_parrx2txtimeden_l0_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_LB_PARRX2TXTIMEDEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_lb_parrx2txtimeden_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_LB_PARRX2TXTIMEDEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_lb_tx2rxbuftimeden_l0_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_LB_TX2RXBUFTIMEDEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_lb_tx2rxbuftimeden_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_LB_TX2RXBUFTIMEDEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_lfps_en_l0_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_LFPS_EN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_lfps_en_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_LFPS_EN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_mode_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_MODE_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_mode_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_MODE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_pcie_l1d1_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_PCIE_L1D1_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_pcie_l1d1_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_PCIE_L1D1_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_pcie_l1d2_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_PCIE_L1D2_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_pcie_l1d2_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_PCIE_L1D2_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rcomp_slave_en_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RCOMP_SLAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rcomp_slave_en_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RCOMP_SLAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rcomp_slave_nt_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rcomp_slave_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RCOMP_SLAVE_NT_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rcomp_slave_valid_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RCOMP_SLAVE_VALID_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rcomp_slave_valid_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RCOMP_SLAVE_VALID_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_ref_sel_rx_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_ref_sel_rx_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_REF_SEL_RX_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_ref_sel_tx_nt_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_ref_sel_tx_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_REF_SEL_TX_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_ref_term_hiz_en_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_REF_TERM_HIZ_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_ref_term_hiz_en_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_REF_TERM_HIZ_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxbist_en_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXBIST_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxbist_en_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXBIST_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxbitslip_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXBITSLIP_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxbitslip_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXBITSLIP_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeiosdetectstat_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEIOSDETECTSTAT_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeiosdetectstat_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEIOSDETECTSTAT_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeq_clr_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEQ_CLR_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeq_clr_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEQ_CLR_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeq_precal_code_sel_l0_nt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeq_precal_code_sel_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEQ_PRECAL_CODE_SEL_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeq_start_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEQ_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeq_start_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEQ_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeq_static_en_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEQ_STATIC_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeq_static_en_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEQ_STATIC_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeyediag_start_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEYEDIAG_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeyediag_start_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEYEDIAG_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_direction_l0_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXMARGIN_DIRECTION_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_direction_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXMARGIN_DIRECTION_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_mode_l0_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXMARGIN_MODE_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_mode_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXMARGIN_MODE_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_offset_change_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXMARGIN_OFFSET_CHANGE_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_offset_change_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXMARGIN_OFFSET_CHANGE_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_offset_l0_nt_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_offset_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXMARGIN_OFFSET_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_start_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXMARGIN_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_start_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXMARGIN_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxpam_gray_en_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXPAM_GRAY_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxpam_gray_en_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXPAM_GRAY_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxpam_precode_en_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXPAM_PRECODE_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxpam_precode_en_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXPAM_PRECODE_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxrate_l0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxrate_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxterm_hiz_en_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXTERM_HIZ_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxterm_hiz_en_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXTERM_HIZ_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxwidth_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxwidth_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXWIDTH_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_spare_nt_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_spare_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SPARE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcfast_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcfast_divrate_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SYNTHLCFAST_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcfast_force_pup_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SYNTHLCFAST_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcfast_force_pup_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SYNTHLCFAST_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcmed_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcmed_divrate_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SYNTHLCMED_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcmed_force_pup_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SYNTHLCMED_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcmed_force_pup_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SYNTHLCMED_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcslow_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcslow_divrate_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SYNTHLCSLOW_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcslow_force_pup_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SYNTHLCSLOW_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcslow_force_pup_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SYNTHLCSLOW_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txbeacon_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXBEACON_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txbeacon_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXBEACON_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txbist_en_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXBIST_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txbist_en_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXBIST_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txclkdivrate_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txclkdivrate_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXCLKDIVRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdetectrx_req_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXDETECTRX_REQ_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdetectrx_req_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXDETECTRX_REQ_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_levn_l0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_levn_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXDRV_LEVN_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_levnm1_l0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_levnm1_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXDRV_LEVNM1_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_levnm2_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_levnm2_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXDRV_LEVNM2_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_levnp1_l0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_levnp1_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXDRV_LEVNP1_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_slew_l0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_slew_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXDRV_SLEW_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_spare_l0_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_spare_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXDRV_SPARE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txenable_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXENABLE_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txenable_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXENABLE_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txpam_gray_en_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXPAM_GRAY_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txpam_gray_en_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXPAM_GRAY_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txpam_precode_en_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXPAM_PRECODE_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txpam_precode_en_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXPAM_PRECODE_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txrate_l0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txrate_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txwidth_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txwidth_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXWIDTH_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_visa_unit_id_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_ictl_visa_unit_id_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_VISA_UNIT_ID_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_idat_dfx_obs_dig_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_idat_visa_serial_cfg_in_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_irst_apb_mem_b_attr == SERDES_IP_IF_L1_CFG_IRST_APB_MEM_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_irst_apb_mem_b_reg_en_attr == SERDES_IP_IF_L1_CFG_IRST_APB_MEM_B_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_irst_pcs_rx_l0_b_a_attr == SERDES_IP_IF_L1_CFG_IRST_PCS_RX_L0_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_irst_pcs_rx_l0_b_a_reg_en_attr == SERDES_IP_IF_L1_CFG_IRST_PCS_RX_L0_B_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_irst_pcs_tstbus_b_a_attr == SERDES_IP_IF_L1_CFG_IRST_PCS_TSTBUS_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_irst_pcs_tx_l0_b_a_attr == SERDES_IP_IF_L1_CFG_IRST_PCS_TX_L0_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_irst_pcs_tx_l0_b_a_reg_en_attr == SERDES_IP_IF_L1_CFG_IRST_PCS_TX_L0_B_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l1_cfg_irst_visa_reset_b_a_attr == SERDES_IP_IF_L1_CFG_IRST_VISA_RESET_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_cpi_port_mode_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_dfx_secure_visa_nt_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_dfx_secure_visa_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_DFX_SECURE_VISA_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_p_vdd_pwrgood_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_P_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_p_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_P_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pa_vdd_ehv_pwrgood_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pa_vdd_ehv_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pa_vdd_pwrgood_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PA_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pa_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PA_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_andme_en_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_ANDME_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_andme_en_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_ANDME_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bist_modesel_l0_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bist_modesel_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BIST_MODESEL_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_capturedr_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_CAPTUREDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_clamp_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_CLAMP_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_exit1dr_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_EXIT1DR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_exit2dr_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_EXIT2DR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_extest_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_EXTEST_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_extestpulse_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_EXTESTPULSE_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_extesttrain_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_EXTESTTRAIN_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_highz_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_HIGHZ_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_mode_en_nt_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_MODE_EN_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_preload_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_PRELOAD_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_runtestidle_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_RUNTESTIDLE_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_shiftdr_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_SHIFTDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_txinvert_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_TXINVERT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_updatedr_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_UPDATEDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_cmn_force_pup_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_CMN_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_cmn_force_pup_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_CMN_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_disconnect_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_DISCONNECT_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_disconnect_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_DISCONNECT_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_isolate_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_ISOLATE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_isolate_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_ISOLATE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_jtagid_nt_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_JTAGID_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_jtagslvid_nt_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_JTAGSLVID_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_lb_cdrclk2txen_l0_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_LB_CDRCLK2TXEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_lb_cdrclk2txen_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_LB_CDRCLK2TXEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_lb_parrx2txtimeden_l0_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_LB_PARRX2TXTIMEDEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_lb_parrx2txtimeden_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_LB_PARRX2TXTIMEDEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_lb_tx2rxbuftimeden_l0_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_LB_TX2RXBUFTIMEDEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_lb_tx2rxbuftimeden_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_LB_TX2RXBUFTIMEDEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_lfps_en_l0_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_LFPS_EN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_lfps_en_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_LFPS_EN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_mode_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_MODE_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_mode_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_MODE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_pcie_l1d1_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_PCIE_L1D1_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_pcie_l1d1_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_PCIE_L1D1_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_pcie_l1d2_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_PCIE_L1D2_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_pcie_l1d2_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_PCIE_L1D2_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rcomp_slave_en_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RCOMP_SLAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rcomp_slave_en_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RCOMP_SLAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rcomp_slave_nt_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rcomp_slave_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RCOMP_SLAVE_NT_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rcomp_slave_valid_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RCOMP_SLAVE_VALID_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rcomp_slave_valid_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RCOMP_SLAVE_VALID_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_ref_sel_rx_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_ref_sel_rx_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_REF_SEL_RX_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_ref_sel_tx_nt_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_ref_sel_tx_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_REF_SEL_TX_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_ref_term_hiz_en_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_REF_TERM_HIZ_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_ref_term_hiz_en_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_REF_TERM_HIZ_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxbist_en_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXBIST_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxbist_en_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXBIST_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxbitslip_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXBITSLIP_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxbitslip_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXBITSLIP_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeiosdetectstat_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEIOSDETECTSTAT_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeiosdetectstat_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEIOSDETECTSTAT_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeq_clr_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEQ_CLR_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeq_clr_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEQ_CLR_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeq_precal_code_sel_l0_nt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeq_precal_code_sel_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEQ_PRECAL_CODE_SEL_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeq_start_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEQ_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeq_start_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEQ_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeq_static_en_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEQ_STATIC_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeq_static_en_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEQ_STATIC_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeyediag_start_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEYEDIAG_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeyediag_start_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEYEDIAG_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_direction_l0_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXMARGIN_DIRECTION_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_direction_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXMARGIN_DIRECTION_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_mode_l0_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXMARGIN_MODE_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_mode_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXMARGIN_MODE_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_offset_change_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXMARGIN_OFFSET_CHANGE_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_offset_change_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXMARGIN_OFFSET_CHANGE_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_offset_l0_nt_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_offset_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXMARGIN_OFFSET_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_start_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXMARGIN_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_start_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXMARGIN_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxpam_gray_en_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXPAM_GRAY_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxpam_gray_en_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXPAM_GRAY_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxpam_precode_en_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXPAM_PRECODE_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxpam_precode_en_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXPAM_PRECODE_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxrate_l0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxrate_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxterm_hiz_en_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXTERM_HIZ_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxterm_hiz_en_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXTERM_HIZ_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxwidth_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxwidth_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXWIDTH_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_spare_nt_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_spare_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SPARE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcfast_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcfast_divrate_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SYNTHLCFAST_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcfast_force_pup_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SYNTHLCFAST_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcfast_force_pup_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SYNTHLCFAST_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcmed_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcmed_divrate_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SYNTHLCMED_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcmed_force_pup_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SYNTHLCMED_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcmed_force_pup_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SYNTHLCMED_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcslow_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcslow_divrate_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SYNTHLCSLOW_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcslow_force_pup_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SYNTHLCSLOW_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcslow_force_pup_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SYNTHLCSLOW_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txbeacon_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXBEACON_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txbeacon_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXBEACON_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txbist_en_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXBIST_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txbist_en_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXBIST_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txclkdivrate_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txclkdivrate_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXCLKDIVRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdetectrx_req_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXDETECTRX_REQ_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdetectrx_req_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXDETECTRX_REQ_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_levn_l0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_levn_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXDRV_LEVN_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_levnm1_l0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_levnm1_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXDRV_LEVNM1_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_levnm2_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_levnm2_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXDRV_LEVNM2_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_levnp1_l0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_levnp1_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXDRV_LEVNP1_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_slew_l0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_slew_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXDRV_SLEW_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_spare_l0_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_spare_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXDRV_SPARE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txenable_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXENABLE_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txenable_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXENABLE_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txpam_gray_en_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXPAM_GRAY_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txpam_gray_en_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXPAM_GRAY_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txpam_precode_en_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXPAM_PRECODE_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txpam_precode_en_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXPAM_PRECODE_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txrate_l0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txrate_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txwidth_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txwidth_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXWIDTH_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_visa_unit_id_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_ictl_visa_unit_id_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_VISA_UNIT_ID_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_idat_dfx_obs_dig_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_idat_visa_serial_cfg_in_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_irst_apb_mem_b_attr == SERDES_IP_IF_L2_CFG_IRST_APB_MEM_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_irst_apb_mem_b_reg_en_attr == SERDES_IP_IF_L2_CFG_IRST_APB_MEM_B_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_irst_pcs_rx_l0_b_a_attr == SERDES_IP_IF_L2_CFG_IRST_PCS_RX_L0_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_irst_pcs_rx_l0_b_a_reg_en_attr == SERDES_IP_IF_L2_CFG_IRST_PCS_RX_L0_B_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_irst_pcs_tstbus_b_a_attr == SERDES_IP_IF_L2_CFG_IRST_PCS_TSTBUS_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_irst_pcs_tx_l0_b_a_attr == SERDES_IP_IF_L2_CFG_IRST_PCS_TX_L0_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_irst_pcs_tx_l0_b_a_reg_en_attr == SERDES_IP_IF_L2_CFG_IRST_PCS_TX_L0_B_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l2_cfg_irst_visa_reset_b_a_attr == SERDES_IP_IF_L2_CFG_IRST_VISA_RESET_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_cpi_port_mode_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_dfx_secure_visa_nt_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_dfx_secure_visa_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_DFX_SECURE_VISA_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_p_vdd_pwrgood_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_P_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_p_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_P_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pa_vdd_ehv_pwrgood_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pa_vdd_ehv_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pa_vdd_pwrgood_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PA_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pa_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PA_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_andme_en_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_ANDME_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_andme_en_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_ANDME_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bist_modesel_l0_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bist_modesel_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BIST_MODESEL_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_capturedr_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_CAPTUREDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_clamp_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_CLAMP_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_exit1dr_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_EXIT1DR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_exit2dr_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_EXIT2DR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_extest_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_EXTEST_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_extestpulse_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_EXTESTPULSE_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_extesttrain_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_EXTESTTRAIN_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_highz_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_HIGHZ_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_mode_en_nt_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_MODE_EN_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_preload_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_PRELOAD_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_runtestidle_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_RUNTESTIDLE_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_shiftdr_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_SHIFTDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_txinvert_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_TXINVERT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_updatedr_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_UPDATEDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_cmn_force_pup_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_CMN_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_cmn_force_pup_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_CMN_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_disconnect_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_DISCONNECT_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_disconnect_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_DISCONNECT_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_isolate_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_ISOLATE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_isolate_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_ISOLATE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_jtagid_nt_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_JTAGID_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_jtagslvid_nt_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_JTAGSLVID_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_lb_cdrclk2txen_l0_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_LB_CDRCLK2TXEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_lb_cdrclk2txen_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_LB_CDRCLK2TXEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_lb_parrx2txtimeden_l0_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_LB_PARRX2TXTIMEDEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_lb_parrx2txtimeden_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_LB_PARRX2TXTIMEDEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_lb_tx2rxbuftimeden_l0_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_LB_TX2RXBUFTIMEDEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_lb_tx2rxbuftimeden_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_LB_TX2RXBUFTIMEDEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_lfps_en_l0_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_LFPS_EN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_lfps_en_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_LFPS_EN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_mode_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_MODE_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_mode_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_MODE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_pcie_l1d1_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_PCIE_L1D1_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_pcie_l1d1_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_PCIE_L1D1_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_pcie_l1d2_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_PCIE_L1D2_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_pcie_l1d2_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_PCIE_L1D2_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rcomp_slave_en_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RCOMP_SLAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rcomp_slave_en_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RCOMP_SLAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rcomp_slave_nt_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rcomp_slave_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RCOMP_SLAVE_NT_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rcomp_slave_valid_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RCOMP_SLAVE_VALID_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rcomp_slave_valid_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RCOMP_SLAVE_VALID_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_ref_sel_rx_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_ref_sel_rx_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_REF_SEL_RX_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_ref_sel_tx_nt_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_ref_sel_tx_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_REF_SEL_TX_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_ref_term_hiz_en_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_REF_TERM_HIZ_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_ref_term_hiz_en_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_REF_TERM_HIZ_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxbist_en_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXBIST_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxbist_en_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXBIST_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxbitslip_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXBITSLIP_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxbitslip_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXBITSLIP_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeiosdetectstat_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEIOSDETECTSTAT_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeiosdetectstat_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEIOSDETECTSTAT_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeq_clr_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEQ_CLR_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeq_clr_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEQ_CLR_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeq_precal_code_sel_l0_nt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeq_precal_code_sel_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEQ_PRECAL_CODE_SEL_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeq_start_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEQ_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeq_start_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEQ_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeq_static_en_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEQ_STATIC_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeq_static_en_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEQ_STATIC_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeyediag_start_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEYEDIAG_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeyediag_start_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEYEDIAG_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_direction_l0_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXMARGIN_DIRECTION_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_direction_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXMARGIN_DIRECTION_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_mode_l0_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXMARGIN_MODE_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_mode_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXMARGIN_MODE_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_offset_change_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXMARGIN_OFFSET_CHANGE_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_offset_change_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXMARGIN_OFFSET_CHANGE_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_offset_l0_nt_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_offset_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXMARGIN_OFFSET_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_start_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXMARGIN_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_start_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXMARGIN_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxpam_gray_en_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXPAM_GRAY_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxpam_gray_en_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXPAM_GRAY_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxpam_precode_en_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXPAM_PRECODE_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxpam_precode_en_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXPAM_PRECODE_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxrate_l0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxrate_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxterm_hiz_en_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXTERM_HIZ_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxterm_hiz_en_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXTERM_HIZ_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxwidth_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxwidth_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXWIDTH_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_spare_nt_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_spare_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SPARE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcfast_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcfast_divrate_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SYNTHLCFAST_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcfast_force_pup_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SYNTHLCFAST_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcfast_force_pup_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SYNTHLCFAST_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcmed_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcmed_divrate_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SYNTHLCMED_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcmed_force_pup_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SYNTHLCMED_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcmed_force_pup_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SYNTHLCMED_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcslow_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcslow_divrate_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SYNTHLCSLOW_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcslow_force_pup_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SYNTHLCSLOW_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcslow_force_pup_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SYNTHLCSLOW_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txbeacon_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXBEACON_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txbeacon_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXBEACON_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txbist_en_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXBIST_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txbist_en_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXBIST_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txclkdivrate_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txclkdivrate_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXCLKDIVRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdetectrx_req_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXDETECTRX_REQ_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdetectrx_req_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXDETECTRX_REQ_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_levn_l0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_levn_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXDRV_LEVN_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_levnm1_l0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_levnm1_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXDRV_LEVNM1_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_levnm2_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_levnm2_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXDRV_LEVNM2_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_levnp1_l0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_levnp1_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXDRV_LEVNP1_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_slew_l0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_slew_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXDRV_SLEW_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_spare_l0_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_spare_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXDRV_SPARE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txenable_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXENABLE_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txenable_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXENABLE_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txpam_gray_en_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXPAM_GRAY_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txpam_gray_en_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXPAM_GRAY_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txpam_precode_en_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXPAM_PRECODE_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txpam_precode_en_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXPAM_PRECODE_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txrate_l0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txrate_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txwidth_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txwidth_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXWIDTH_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_visa_unit_id_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_ictl_visa_unit_id_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_VISA_UNIT_ID_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_idat_dfx_obs_dig_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_idat_visa_serial_cfg_in_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_irst_apb_mem_b_attr == SERDES_IP_IF_L3_CFG_IRST_APB_MEM_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_irst_apb_mem_b_reg_en_attr == SERDES_IP_IF_L3_CFG_IRST_APB_MEM_B_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_irst_pcs_rx_l0_b_a_attr == SERDES_IP_IF_L3_CFG_IRST_PCS_RX_L0_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_irst_pcs_rx_l0_b_a_reg_en_attr == SERDES_IP_IF_L3_CFG_IRST_PCS_RX_L0_B_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_irst_pcs_tstbus_b_a_attr == SERDES_IP_IF_L3_CFG_IRST_PCS_TSTBUS_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_irst_pcs_tx_l0_b_a_attr == SERDES_IP_IF_L3_CFG_IRST_PCS_TX_L0_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_irst_pcs_tx_l0_b_a_reg_en_attr == SERDES_IP_IF_L3_CFG_IRST_PCS_TX_L0_B_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_if_l3_cfg_irst_visa_reset_b_a_attr == SERDES_IP_IF_L3_CFG_IRST_VISA_RESET_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l0_cfg_laneclk_ctrl_attr == SERDES_IP_LANE_AON_L0_CFG_LANECLK_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l0_cfg_lanefsm_pmu_req_attr == SERDES_IP_LANE_AON_L0_CFG_LANEFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l0_cfg_lanefsm_pmu_req_en_attr == SERDES_IP_LANE_AON_L0_CFG_LANEFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l0_cfg_lanetstbus_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l0_cfg_rxmem_clr_attr == SERDES_IP_LANE_AON_L0_CFG_RXMEM_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l0_cfg_rxmem_en_attr == SERDES_IP_LANE_AON_L0_CFG_RXMEM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l0_cfg_rxmem_pstate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l0_cfg_rxmem_rate_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l0_cfg_rxmem_req_attr == SERDES_IP_LANE_AON_L0_CFG_RXMEM_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l0_cfg_rxmem_rst_b_attr == SERDES_IP_LANE_AON_L0_CFG_RXMEM_RST_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l0_cfg_rxmem_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l0_cfg_rxrstpdovr_apdrx_sqlch_ovr_b_attr == SERDES_IP_LANE_AON_L0_CFG_RXRSTPDOVR_APDRX_SQLCH_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l0_cfg_rxrstpdovr_apdrx_sqlch_ovren_attr == SERDES_IP_LANE_AON_L0_CFG_RXRSTPDOVR_APDRX_SQLCH_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l0_cfg_rxsussigdetout_ovr_attr == SERDES_IP_LANE_AON_L0_CFG_RXSUSSIGDETOUT_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l0_cfg_rxsussigdetout_ovr_en_attr == SERDES_IP_LANE_AON_L0_CFG_RXSUSSIGDETOUT_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l0_cfg_rxsussqlch_enable_attr == SERDES_IP_LANE_AON_L0_CFG_RXSUSSQLCH_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l0_cfg_txmem_clr_attr == SERDES_IP_LANE_AON_L0_CFG_TXMEM_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l0_cfg_txmem_en_attr == SERDES_IP_LANE_AON_L0_CFG_TXMEM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l0_cfg_txmem_pstate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l0_cfg_txmem_rate_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l0_cfg_txmem_req_attr == SERDES_IP_LANE_AON_L0_CFG_TXMEM_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l0_cfg_txmem_rst_b_attr == SERDES_IP_LANE_AON_L0_CFG_TXMEM_RST_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l0_cfg_txmem_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l0_cfg_txpcs_pciel1d1_ovr_attr == SERDES_IP_LANE_AON_L0_CFG_TXPCS_PCIEL1D1_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l0_cfg_txpcs_pciel1d1_ovren_attr == SERDES_IP_LANE_AON_L0_CFG_TXPCS_PCIEL1D1_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l0_cfg_txpcs_pciel1d2_ovr_attr == SERDES_IP_LANE_AON_L0_CFG_TXPCS_PCIEL1D2_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l0_cfg_txpcs_pciel1d2_ovren_attr == SERDES_IP_LANE_AON_L0_CFG_TXPCS_PCIEL1D2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l0_cfg_txrstpdovr_apdtx_bias_ovr_b_attr == SERDES_IP_LANE_AON_L0_CFG_TXRSTPDOVR_APDTX_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l0_cfg_txrstpdovr_apdtx_bias_ovren_attr == SERDES_IP_LANE_AON_L0_CFG_TXRSTPDOVR_APDTX_BIAS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l0_cfg_txrstpdovr_apdtx_drv_ovr_b_attr == SERDES_IP_LANE_AON_L0_CFG_TXRSTPDOVR_APDTX_DRV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l0_cfg_txrstpdovr_apdtx_drv_ovren_attr == SERDES_IP_LANE_AON_L0_CFG_TXRSTPDOVR_APDTX_DRV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l1_cfg_laneclk_ctrl_attr == SERDES_IP_LANE_AON_L1_CFG_LANECLK_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l1_cfg_lanefsm_pmu_req_attr == SERDES_IP_LANE_AON_L1_CFG_LANEFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l1_cfg_lanefsm_pmu_req_en_attr == SERDES_IP_LANE_AON_L1_CFG_LANEFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l1_cfg_lanetstbus_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l1_cfg_rxmem_clr_attr == SERDES_IP_LANE_AON_L1_CFG_RXMEM_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l1_cfg_rxmem_en_attr == SERDES_IP_LANE_AON_L1_CFG_RXMEM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l1_cfg_rxmem_pstate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l1_cfg_rxmem_rate_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l1_cfg_rxmem_req_attr == SERDES_IP_LANE_AON_L1_CFG_RXMEM_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l1_cfg_rxmem_rst_b_attr == SERDES_IP_LANE_AON_L1_CFG_RXMEM_RST_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l1_cfg_rxmem_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l1_cfg_rxrstpdovr_apdrx_sqlch_ovr_b_attr == SERDES_IP_LANE_AON_L1_CFG_RXRSTPDOVR_APDRX_SQLCH_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l1_cfg_rxrstpdovr_apdrx_sqlch_ovren_attr == SERDES_IP_LANE_AON_L1_CFG_RXRSTPDOVR_APDRX_SQLCH_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l1_cfg_rxsussigdetout_ovr_attr == SERDES_IP_LANE_AON_L1_CFG_RXSUSSIGDETOUT_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l1_cfg_rxsussigdetout_ovr_en_attr == SERDES_IP_LANE_AON_L1_CFG_RXSUSSIGDETOUT_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l1_cfg_rxsussqlch_enable_attr == SERDES_IP_LANE_AON_L1_CFG_RXSUSSQLCH_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l1_cfg_txmem_clr_attr == SERDES_IP_LANE_AON_L1_CFG_TXMEM_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l1_cfg_txmem_en_attr == SERDES_IP_LANE_AON_L1_CFG_TXMEM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l1_cfg_txmem_pstate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l1_cfg_txmem_rate_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l1_cfg_txmem_req_attr == SERDES_IP_LANE_AON_L1_CFG_TXMEM_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l1_cfg_txmem_rst_b_attr == SERDES_IP_LANE_AON_L1_CFG_TXMEM_RST_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l1_cfg_txmem_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l1_cfg_txpcs_pciel1d1_ovr_attr == SERDES_IP_LANE_AON_L1_CFG_TXPCS_PCIEL1D1_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l1_cfg_txpcs_pciel1d1_ovren_attr == SERDES_IP_LANE_AON_L1_CFG_TXPCS_PCIEL1D1_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l1_cfg_txpcs_pciel1d2_ovr_attr == SERDES_IP_LANE_AON_L1_CFG_TXPCS_PCIEL1D2_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l1_cfg_txpcs_pciel1d2_ovren_attr == SERDES_IP_LANE_AON_L1_CFG_TXPCS_PCIEL1D2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l1_cfg_txrstpdovr_apdtx_bias_ovr_b_attr == SERDES_IP_LANE_AON_L1_CFG_TXRSTPDOVR_APDTX_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l1_cfg_txrstpdovr_apdtx_bias_ovren_attr == SERDES_IP_LANE_AON_L1_CFG_TXRSTPDOVR_APDTX_BIAS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l1_cfg_txrstpdovr_apdtx_drv_ovr_b_attr == SERDES_IP_LANE_AON_L1_CFG_TXRSTPDOVR_APDTX_DRV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l1_cfg_txrstpdovr_apdtx_drv_ovren_attr == SERDES_IP_LANE_AON_L1_CFG_TXRSTPDOVR_APDTX_DRV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l2_cfg_laneclk_ctrl_attr == SERDES_IP_LANE_AON_L2_CFG_LANECLK_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l2_cfg_lanefsm_pmu_req_attr == SERDES_IP_LANE_AON_L2_CFG_LANEFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l2_cfg_lanefsm_pmu_req_en_attr == SERDES_IP_LANE_AON_L2_CFG_LANEFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l2_cfg_lanetstbus_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l2_cfg_rxmem_clr_attr == SERDES_IP_LANE_AON_L2_CFG_RXMEM_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l2_cfg_rxmem_en_attr == SERDES_IP_LANE_AON_L2_CFG_RXMEM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l2_cfg_rxmem_pstate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l2_cfg_rxmem_rate_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l2_cfg_rxmem_req_attr == SERDES_IP_LANE_AON_L2_CFG_RXMEM_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l2_cfg_rxmem_rst_b_attr == SERDES_IP_LANE_AON_L2_CFG_RXMEM_RST_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l2_cfg_rxmem_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l2_cfg_rxrstpdovr_apdrx_sqlch_ovr_b_attr == SERDES_IP_LANE_AON_L2_CFG_RXRSTPDOVR_APDRX_SQLCH_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l2_cfg_rxrstpdovr_apdrx_sqlch_ovren_attr == SERDES_IP_LANE_AON_L2_CFG_RXRSTPDOVR_APDRX_SQLCH_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l2_cfg_rxsussigdetout_ovr_attr == SERDES_IP_LANE_AON_L2_CFG_RXSUSSIGDETOUT_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l2_cfg_rxsussigdetout_ovr_en_attr == SERDES_IP_LANE_AON_L2_CFG_RXSUSSIGDETOUT_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l2_cfg_rxsussqlch_enable_attr == SERDES_IP_LANE_AON_L2_CFG_RXSUSSQLCH_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l2_cfg_txmem_clr_attr == SERDES_IP_LANE_AON_L2_CFG_TXMEM_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l2_cfg_txmem_en_attr == SERDES_IP_LANE_AON_L2_CFG_TXMEM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l2_cfg_txmem_pstate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l2_cfg_txmem_rate_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l2_cfg_txmem_req_attr == SERDES_IP_LANE_AON_L2_CFG_TXMEM_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l2_cfg_txmem_rst_b_attr == SERDES_IP_LANE_AON_L2_CFG_TXMEM_RST_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l2_cfg_txmem_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l2_cfg_txpcs_pciel1d1_ovr_attr == SERDES_IP_LANE_AON_L2_CFG_TXPCS_PCIEL1D1_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l2_cfg_txpcs_pciel1d1_ovren_attr == SERDES_IP_LANE_AON_L2_CFG_TXPCS_PCIEL1D1_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l2_cfg_txpcs_pciel1d2_ovr_attr == SERDES_IP_LANE_AON_L2_CFG_TXPCS_PCIEL1D2_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l2_cfg_txpcs_pciel1d2_ovren_attr == SERDES_IP_LANE_AON_L2_CFG_TXPCS_PCIEL1D2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l2_cfg_txrstpdovr_apdtx_bias_ovr_b_attr == SERDES_IP_LANE_AON_L2_CFG_TXRSTPDOVR_APDTX_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l2_cfg_txrstpdovr_apdtx_bias_ovren_attr == SERDES_IP_LANE_AON_L2_CFG_TXRSTPDOVR_APDTX_BIAS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l2_cfg_txrstpdovr_apdtx_drv_ovr_b_attr == SERDES_IP_LANE_AON_L2_CFG_TXRSTPDOVR_APDTX_DRV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l2_cfg_txrstpdovr_apdtx_drv_ovren_attr == SERDES_IP_LANE_AON_L2_CFG_TXRSTPDOVR_APDTX_DRV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l3_cfg_laneclk_ctrl_attr == SERDES_IP_LANE_AON_L3_CFG_LANECLK_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l3_cfg_lanefsm_pmu_req_attr == SERDES_IP_LANE_AON_L3_CFG_LANEFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l3_cfg_lanefsm_pmu_req_en_attr == SERDES_IP_LANE_AON_L3_CFG_LANEFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l3_cfg_lanetstbus_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l3_cfg_rxmem_clr_attr == SERDES_IP_LANE_AON_L3_CFG_RXMEM_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l3_cfg_rxmem_en_attr == SERDES_IP_LANE_AON_L3_CFG_RXMEM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l3_cfg_rxmem_pstate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l3_cfg_rxmem_rate_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l3_cfg_rxmem_req_attr == SERDES_IP_LANE_AON_L3_CFG_RXMEM_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l3_cfg_rxmem_rst_b_attr == SERDES_IP_LANE_AON_L3_CFG_RXMEM_RST_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l3_cfg_rxmem_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l3_cfg_rxrstpdovr_apdrx_sqlch_ovr_b_attr == SERDES_IP_LANE_AON_L3_CFG_RXRSTPDOVR_APDRX_SQLCH_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l3_cfg_rxrstpdovr_apdrx_sqlch_ovren_attr == SERDES_IP_LANE_AON_L3_CFG_RXRSTPDOVR_APDRX_SQLCH_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l3_cfg_rxsussigdetout_ovr_attr == SERDES_IP_LANE_AON_L3_CFG_RXSUSSIGDETOUT_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l3_cfg_rxsussigdetout_ovr_en_attr == SERDES_IP_LANE_AON_L3_CFG_RXSUSSIGDETOUT_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l3_cfg_rxsussqlch_enable_attr == SERDES_IP_LANE_AON_L3_CFG_RXSUSSQLCH_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l3_cfg_txmem_clr_attr == SERDES_IP_LANE_AON_L3_CFG_TXMEM_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l3_cfg_txmem_en_attr == SERDES_IP_LANE_AON_L3_CFG_TXMEM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l3_cfg_txmem_pstate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l3_cfg_txmem_rate_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l3_cfg_txmem_req_attr == SERDES_IP_LANE_AON_L3_CFG_TXMEM_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l3_cfg_txmem_rst_b_attr == SERDES_IP_LANE_AON_L3_CFG_TXMEM_RST_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l3_cfg_txmem_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l3_cfg_txpcs_pciel1d1_ovr_attr == SERDES_IP_LANE_AON_L3_CFG_TXPCS_PCIEL1D1_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l3_cfg_txpcs_pciel1d1_ovren_attr == SERDES_IP_LANE_AON_L3_CFG_TXPCS_PCIEL1D1_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l3_cfg_txpcs_pciel1d2_ovr_attr == SERDES_IP_LANE_AON_L3_CFG_TXPCS_PCIEL1D2_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l3_cfg_txpcs_pciel1d2_ovren_attr == SERDES_IP_LANE_AON_L3_CFG_TXPCS_PCIEL1D2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l3_cfg_txrstpdovr_apdtx_bias_ovr_b_attr == SERDES_IP_LANE_AON_L3_CFG_TXRSTPDOVR_APDTX_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l3_cfg_txrstpdovr_apdtx_bias_ovren_attr == SERDES_IP_LANE_AON_L3_CFG_TXRSTPDOVR_APDTX_BIAS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l3_cfg_txrstpdovr_apdtx_drv_ovr_b_attr == SERDES_IP_LANE_AON_L3_CFG_TXRSTPDOVR_APDTX_DRV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_aon_l3_cfg_txrstpdovr_apdtx_drv_ovren_attr == SERDES_IP_LANE_AON_L3_CFG_TXRSTPDOVR_APDTX_DRV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_bshihyst_attr == SERDES_IP_LANE_L0_CFG_BSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_bstxdrv_levn_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_bstxdrv_levnm1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_bstxdrv_levnp1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_bstxdrv_levnp2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_calsqlchosc_locovren_attr == SERDES_IP_LANE_L0_CFG_CALSQLCHOSC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_calsqlchosc_trimcode_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_cdrclkstat_locovren_attr == SERDES_IP_LANE_L0_CFG_CDRCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_cdrclkstat_ready_locovr_attr == SERDES_IP_LANE_L0_CFG_CDRCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_etrregrxcdrclk_ready_attr == SERDES_IP_LANE_L0_CFG_ETRREGRXCDRCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_laneckm_avg_en_attr == SERDES_IP_LANE_L0_CFG_LANECKM_AVG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_laneckm_clk_en_attr == SERDES_IP_LANE_L0_CFG_LANECKM_CLK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_laneckm_continuous_attr == SERDES_IP_LANE_L0_CFG_LANECKM_CONTINUOUS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_laneckm_dig_meas_en_attr == SERDES_IP_LANE_L0_CFG_LANECKM_DIG_MEAS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_laneckm_dig_meas_err_clr_attr == SERDES_IP_LANE_L0_CFG_LANECKM_DIG_MEAS_ERR_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_laneckm_en_attr == SERDES_IP_LANE_L0_CFG_LANECKM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_laneckm_max_thr_attr == 25'd33554431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_laneckm_meas_ck_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_laneckm_ref_ck_div_ratio_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_laneckm_result_clr_attr == SERDES_IP_LANE_L0_CFG_LANECKM_RESULT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_laneckm_start_attr == SERDES_IP_LANE_L0_CFG_LANECKM_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_laneckm_wdt_interval_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_laneckm_win_thr_ref_attr == 25'd16777215
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_lanepcs_locovren_attr == SERDES_IP_LANE_L0_CFG_LANEPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_lanepcs_mode_locovr_attr == SERDES_IP_LANE_L0_CFG_LANEPCS_MODE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_laneperfmon_compare_val_start_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_laneperfmon_compare_val_stop_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_laneperfmon_en_attr == SERDES_IP_LANE_L0_CFG_LANEPERFMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_laneperfmon_mask_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_lanepmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_lanepmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_lanepmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_lanepmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_lanepmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_lanepmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_lb_cdrclk2txen_locovr_attr == SERDES_IP_LANE_L0_CFG_LB_CDRCLK2TXEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_lb_cdrclkdiven_attr == SERDES_IP_LANE_L0_CFG_LB_CDRCLKDIVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_lb_cdrdivclk2exten_attr == SERDES_IP_LANE_L0_CFG_LB_CDRDIVCLK2EXTEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_lb_cdrdivclk2txen_attr == SERDES_IP_LANE_L0_CFG_LB_CDRDIVCLK2TXEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_lb_hsclk2cdrdiven_attr == SERDES_IP_LANE_L0_CFG_LB_HSCLK2CDRDIVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_lb_locovren_attr == SERDES_IP_LANE_L0_CFG_LB_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_lb_parrx2txtimeden_locovr_attr == SERDES_IP_LANE_L0_CFG_LB_PARRX2TXTIMEDEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_lb_pllfbclk2cdrrefclken_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_lb_pllfbclk2cdrrefclken_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_lb_pllfbclk2cdrrefclken_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_lb_pllfbclk2cdrrefclken_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_lb_pllfbclk2cdrrefclken_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_lb_rx2txuntimeden_attr == SERDES_IP_LANE_L0_CFG_LB_RX2TXUNTIMEDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_lb_rxwordck2pcstxwordcken_attr == SERDES_IP_LANE_L0_CFG_LB_RXWORDCK2PCSTXWORDCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_lb_tx2rxbuftimeden_lsb_locovr_attr == SERDES_IP_LANE_L0_CFG_LB_TX2RXBUFTIMEDEN_LSB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_lb_tx2rxbuftimeden_msb_locovr_attr == SERDES_IP_LANE_L0_CFG_LB_TX2RXBUFTIMEDEN_MSB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_lb_tx2rxiotimeden_attr == SERDES_IP_LANE_L0_CFG_LB_TX2RXIOTIMEDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_lfps_det_locovr_attr == SERDES_IP_LANE_L0_CFG_LFPS_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_lfps_locovren_attr == SERDES_IP_LANE_L0_CFG_LFPS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_lfps_out_en_attr == SERDES_IP_LANE_L0_CFG_LFPS_OUT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_pcslfps_en_locovr_attr == SERDES_IP_LANE_L0_CFG_PCSLFPS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_pcslfps_locovren_attr == SERDES_IP_LANE_L0_CFG_PCSLFPS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_pcsrx_dme_en_locovr_attr == SERDES_IP_LANE_L0_CFG_PCSRX_DME_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_pcsrx_locovren_attr == SERDES_IP_LANE_L0_CFG_PCSRX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_pcsrxbist_locovren_attr == SERDES_IP_LANE_L0_CFG_PCSRXBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_pcsrxbist_modesel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_pcstx_beaconen_locovr_attr == SERDES_IP_LANE_L0_CFG_PCSTX_BEACONEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_pcstx_locovren_attr == SERDES_IP_LANE_L0_CFG_PCSTX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_polarity_rx_attr == SERDES_IP_LANE_L0_CFG_POLARITY_RX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_polarity_tx_attr == SERDES_IP_LANE_L0_CFG_POLARITY_TX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rx_cmn_on_state_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rx_fastregpwrup_en_attr == SERDES_IP_LANE_L0_CFG_RX_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rx_frac_mode_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rx_on_state_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rx_pg_disable_attr == SERDES_IP_LANE_L0_CFG_RX_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rx_synth_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rx_synth_sel_amode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rx_synth_sel_bmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rx_synth_sel_cmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rx_synth_sel_dmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rx_synth_sel_emode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxadc_req_attr == SERDES_IP_LANE_L0_CFG_RXADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxagc_dccoupleen_attr == SERDES_IP_LANE_L0_CFG_RXAGC_DCCOUPLEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxaprobe_addr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxaprobe_lastmux_isolate_attr == SERDES_IP_LANE_L0_CFG_RXAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxaprobeadc_current_direction_attr == SERDES_IP_LANE_L0_CFG_RXAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxaprobeadc_resistor_enable_attr == SERDES_IP_LANE_L0_CFG_RXAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxbias_iccadj_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxbias_icvadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxbias_locovren_attr == SERDES_IP_LANE_L0_CFG_RXBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxbias_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxbist_burst_four_errtype_attr == SERDES_IP_LANE_L0_CFG_RXBIST_BURST_FOUR_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxbist_burst_one_errtype_attr == SERDES_IP_LANE_L0_CFG_RXBIST_BURST_ONE_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxbist_burst_three_errtype_attr == SERDES_IP_LANE_L0_CFG_RXBIST_BURST_THREE_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxbist_burst_two_errtype_attr == SERDES_IP_LANE_L0_CFG_RXBIST_BURST_TWO_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxbist_cdrlock2data_bypass_attr == SERDES_IP_LANE_L0_CFG_RXBIST_CDRLOCK2DATA_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxbist_cdrlock2data_postamble_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxbist_clear_errcount_attr == SERDES_IP_LANE_L0_CFG_RXBIST_CLEAR_ERRCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxbist_err_en_attr == SERDES_IP_LANE_L0_CFG_RXBIST_ERR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxbist_err_trig_type_attr == SERDES_IP_LANE_L0_CFG_RXBIST_ERR_TRIG_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxbist_errmask_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxbist_errtype_attr == SERDES_IP_LANE_L0_CFG_RXBIST_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxbist_firsterr_type_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxbist_lockchk_count_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxbist_maxbitcnt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxbist_mostrecent_err_attr == SERDES_IP_LANE_L0_CFG_RXBIST_MOSTRECENT_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxbist_relock_itercount_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxbist_seed_attr == 31'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxbist_status_hold_attr == SERDES_IP_LANE_L0_CFG_RXBIST_STATUS_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxbitslip_locovr_attr == SERDES_IP_LANE_L0_CFG_RXBITSLIP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxbitslip_locovren_attr == SERDES_IP_LANE_L0_CFG_RXBITSLIP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxbscan_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxbshicm_attr == SERDES_IP_LANE_L0_CFG_RXBSHICM_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalcdrfbdiv_div2_bypass_muxd0_attr == SERDES_IP_LANE_L0_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalcdrfbdiv_div2_bypass_muxd1_attr == SERDES_IP_LANE_L0_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalcdrfbdiv_div2_bypass_muxd2_attr == SERDES_IP_LANE_L0_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalcdrfbdiv_div2_bypass_muxd3_attr == SERDES_IP_LANE_L0_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalcdrfbdiv_div2_bypass_muxd4_attr == SERDES_IP_LANE_L0_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalduty_iclk_gray_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalduty_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTY_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalduty_qclk_gray_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalduty_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutybg_abort_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutybg_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutybg_ready_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycomp_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycomp_offset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_finish_side_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_init_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_initval_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_invert_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_round_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_runcount_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_signmagen_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsmout_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsmout_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_disable_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCTRL_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_i_div1_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_i_div2_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_i_div4_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_i_div8_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_q_div1_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_q_div2_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_q_div4_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_q_div8_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_bg_en_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_bg_one_step_cal_en_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_finish_side_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_i_polarity_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_I_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_i_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_I_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_init_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_q_polarity_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_Q_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_q_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_Q_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_round_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_runcount_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_signmagen_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_comp_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEAS_COMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_comp_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEAS_COMP_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_i_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEAS_I_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_i_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEAS_I_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_q_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEAS_Q_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_q_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEAS_Q_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeasout_comp_ack_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEASOUT_COMP_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeasout_comp_erravg_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEASOUT_COMP_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeasout_i_ack_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEASOUT_I_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeasout_i_erravg_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEASOUT_I_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeasout_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeasout_q_ack_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEASOUT_Q_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeasout_q_erravg_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEASOUT_Q_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutystat_done_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaldutystat_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_centerfreq_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_end_delay_attr == 9'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_hscount_muxd0_attr == 8'd181
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_hscount_muxd1_attr == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_hscount_muxd2_attr == 8'd180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_hscount_muxd3_attr == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_hscount_muxd4_attr == 8'd206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_initval_centerfreq_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_initval_fosc_attr == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_centerfreq_finish_side_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_CENTERFREQ_FINISH_SIDE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_centerfreq_to_fosc_offset_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_centerfreqen_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_CENTERFREQEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_centerfreqoffset_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_fosc_finishside_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_FOSC_FINISHSIDE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_foscen_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_FOSCEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_foscoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_init_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_invert_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_lpfax_calfosccoarse_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_lpfax_calfoscfine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_lpfax_centerfreqcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_lpfax_centerfreqfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_runcount_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_signmagen_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_vcorepen_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_VCOREPEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsmout_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsmout_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_count_muxd0_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_count_muxd1_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_count_muxd2_attr == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_count_muxd3_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_count_muxd4_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_dlycount_attr == 9'd68
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeasout_clear_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCMEASOUT_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeasout_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeasout_start_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCMEASOUT_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscval_int_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscval_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalintsval_int_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalintsval_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALINTSVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaloffsetfsm_init_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaloffsetfsm_init_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaloffsetfsm_init_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALOFFSETFSM_INIT_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaloffsetfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcaloffsetfsmout_input_en_attr == SERDES_IP_LANE_L0_CFG_RXCALOFFSETFSMOUT_INPUT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_duty_i_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_duty_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_dutycomp_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_foscfsm_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_offsetfsm_init_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_regopampoffset_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_rxppm_lockstatus_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_sqlch_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_sqlchosc_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_synthppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_voscregopampoffset_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_duty_i_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_duty_q_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_dutycomp_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_foscfsm_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_offsetfsm_init_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_rxppm_lockstatus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_sqlch_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_sqlchosc_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_synthppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_voscregopampoffset_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffset_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_finish_side_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_round_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_runcount_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_signmagen_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchfsm_clear_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchfsm_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchfsmout_caldone_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHFSMOUT_CALDONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchfsmout_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_codeoffset_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_finish_side_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHOSCFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_init_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHOSCFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_initval_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_invert_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHOSCFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHOSCFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHOSCFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_round_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHOSCFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_runcount_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHOSCFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscmeas_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHOSCMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscmeas_ref_cnt_attr == 10'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscmeas_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHOSCMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscmeas_settle_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscmeas_smpl_cnt_attr == 10'd144
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvbiascap_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALVBIASCAP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvbiascap_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALVBIASCAP_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvcoopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvcoopampoffsetmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvcoopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvcoopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffset_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffset_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_codeoffset_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_finish_side_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_initval_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_invert_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_lpfaxcoarse_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_round_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_runcount_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETFSM_RUNCOUNT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_signmagen_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsmout_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsmout_runcount_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETFSMOUT_RUNCOUNT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetmeas_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffset_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALVOSCREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALVOSCREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L0_CFG_RXCALVOSCREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALVOSCREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALVOSCREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALVOSCREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALVOSCREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALVOSCREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALVOSCREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrdiv_local_en_attr == SERDES_IP_LANE_L0_CFG_RXCDRDIV_LOCAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdiv_moddiv_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdiv_moddiv_muxd1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdiv_moddiv_muxd2_attr == 4'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdiv_moddiv_muxd3_attr == 4'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdiv_moddiv_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdivslip_mdiv_muxd0_attr == 9'd194
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdivslip_mdiv_muxd1_attr == 9'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdivslip_mdiv_muxd2_attr == 9'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdivslip_mdiv_muxd3_attr == 9'd66
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdivslip_mdiv_muxd4_attr == 9'd210
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrpfd_forcedn_attr == SERDES_IP_LANE_L0_CFG_RXCDRPFD_FORCEDN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrpfd_forceen_attr == SERDES_IP_LANE_L0_CFG_RXCDRPFD_FORCEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrpfd_forceup_attr == SERDES_IP_LANE_L0_CFG_RXCDRPFD_FORCEUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrpfd_propgain_attr == SERDES_IP_LANE_L0_CFG_RXCDRPFD_PROPGAIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrpfd_pulsewidth_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrphd_asym_override_ignore_attr == SERDES_IP_LANE_L0_CFG_RXCDRPHD_ASYM_OVERRIDE_IGNORE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrphd_bitshift_en_attr == SERDES_IP_LANE_L0_CFG_RXCDRPHD_BITSHIFT_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrphd_forcedn_attr == SERDES_IP_LANE_L0_CFG_RXCDRPHD_FORCEDN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrphd_forceen_attr == SERDES_IP_LANE_L0_CFG_RXCDRPHD_FORCEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrphd_forceup_attr == SERDES_IP_LANE_L0_CFG_RXCDRPHD_FORCEUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrphdrate_doublerate2s2p_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCDRPHDRATE_DOUBLERATE2S2P_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrphdrate_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCDRPHDRATE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrrefck_refdiv_muxd0_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrrefck_refdiv_muxd1_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrrefck_refdiv_muxd2_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrrefck_refdiv_muxd3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrrefck_refdiv_muxd4_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_biastop_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_biastopbypass_attr == SERDES_IP_LANE_L0_CFG_RXCDRVCO_BIASTOPBYPASS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_datapropgain_high_attr == 5'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_datapropgain_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_datapropgain_low_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_ff_ovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_ff_ovr_en_attr == SERDES_IP_LANE_L0_CFG_RXCDRVCO_FF_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_fil_short_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_flickerdegen_attr == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_gmfoscshort_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCDRVCO_GMFOSCSHORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_intf_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_intf_fil_short_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_intrj_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCDRVCO_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_refpropgain_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_refpropgain_nom_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxclk_cdrfb_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCLK_CDRFB_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxclk_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxclk_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdat_nrz_64b80b_bcword_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdata_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXDATA_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdata_locovren_attr == SERDES_IP_LANE_L0_CFG_RXDATA_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdatapath_locovren_attr == SERDES_IP_LANE_L0_CFG_RXDATAPATH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdatapath_on_state_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdatapath_ready_locovr_attr == SERDES_IP_LANE_L0_CFG_RXDATAPATH_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdfe_datatap_vcasc_attr == 4'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdfe_dfebiasadj_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdfe_nbiasctle_en_attr == SERDES_IP_LANE_L0_CFG_RXDFE_NBIASCTLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdfe_vcasc_sel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdfeterm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXDFETERM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdfeterm_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdfeyadjdac_datamid_edge_coarse_en_attr == SERDES_IP_LANE_L0_CFG_RXDFEYADJDAC_DATAMID_EDGE_COARSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdfeyadjdac_datatopbot_aux_coarse_en_attr == SERDES_IP_LANE_L0_CFG_RXDFEYADJDAC_DATATOPBOT_AUX_COARSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_accum_mon_en_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_ACCUM_MON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_accum_mon_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_bypasscdrpdetupdnsmpl_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_bypassenfosc_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_BYPASSENFOSC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_bypassenints_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_BYPASSENINTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_bypassenupdnsmpl_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_BYPASSENUPDNSMPL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_bypassfosc_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_bypasspllpfdupdnsmpl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_bypassrxints_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_data2pll_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_deltasigmode_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_DELTASIGMODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_fastref_muxd0_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_FASTREF_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_fastref_muxd1_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_FASTREF_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_fastref_muxd2_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_FASTREF_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_fastref_muxd3_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_FASTREF_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_fastref_muxd4_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_FASTREF_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_fosc_mod_bypass_en_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_FOSC_MOD_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_fosc_sample_pedge_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_FOSC_SAMPLE_PEDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gain_step_on_lock_recovery_en_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_GAIN_STEP_ON_LOCK_RECOVERY_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gaindelaycount_init_attr == 9'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gaindelaycount_pow2_muxd0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gaindelaycount_pow2_muxd1_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gaindelaycount_pow2_muxd2_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gaindelaycount_pow2_muxd3_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gaindelaycount_pow2_muxd4_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2ref_pow2_muxd0_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2ref_pow2_muxd1_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2ref_pow2_muxd2_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2ref_pow2_muxd3_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2ref_pow2_muxd4_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainunlocked_pow2_muxd0_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainunlocked_pow2_muxd1_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainunlocked_pow2_muxd2_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainunlocked_pow2_muxd3_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainunlocked_pow2_muxd4_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_initintegrator_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_INITINTEGRATOR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_initmodulator_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_INITMODULATOR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_deltasig_mode_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_INTS_DELTASIG_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_freeze_en_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_INTS_FREEZE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gaindelaycount_pow2_muxd0_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gaindelaycount_pow2_muxd1_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gaindelaycount_pow2_muxd2_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gaindelaycount_pow2_muxd3_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gaindelaycount_pow2_muxd4_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd0_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd1_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd2_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd3_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd4_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd0_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd1_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd2_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd3_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd4_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainunlocked_pow2_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainunlocked_pow2_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainunlocked_pow2_muxd2_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainunlocked_pow2_muxd3_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainunlocked_pow2_muxd4_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_guardband_hi_attr == 8'd200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_guardband_lo_attr == 8'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_loop_sel_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_INTS_LOOP_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_mod_bypass_en_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_INTS_MOD_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_mod_load_pedge_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_INTS_MOD_LOAD_PEDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_step_to_integer_en_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_INTS_STEP_TO_INTEGER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_jit_length_attr == 18'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_jit_mode_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_JIT_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_modck_ctrl_en_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_MODCK_CTRL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_pll2data_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_restore_cntr_attr == 9'd258
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_store_cntr_attr == 16'd258
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpif_trnsfrdelay_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpiffreeze_inten_attr == SERDES_IP_LANE_L0_CFG_RXDPIFFREEZE_INTEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdpiffreeze_moden_attr == SERDES_IP_LANE_L0_CFG_RXDPIFFREEZE_MODEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxdutyselpolarity_attr == SERDES_IP_LANE_L0_CFG_RXDUTYSELPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxflxgate_force_rxeq_gate_locovr_attr == SERDES_IP_LANE_L0_CFG_RXFLXGATE_FORCE_RXEQ_GATE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxflxgate_locovren_attr == SERDES_IP_LANE_L0_CFG_RXFLXGATE_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxfoscstat_done_locovr_attr == SERDES_IP_LANE_L0_CFG_RXFOSCSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxfoscstat_locovren_attr == SERDES_IP_LANE_L0_CFG_RXFOSCSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxfsm_cken_ovr_attr == SERDES_IP_LANE_L0_CFG_RXFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxfsm_cken_ovren_attr == SERDES_IP_LANE_L0_CFG_RXFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxints_prev_votes_hold_en_attr == SERDES_IP_LANE_L0_CFG_RXINTS_PREV_VOTES_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxlanepam_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXLANEPAM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxlanepam_locovren_attr == SERDES_IP_LANE_L0_CFG_RXLANEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxlock2datatmr_attr == 8'd240
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxlock2datatmr_short_attr == 8'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxntl_changeref_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxntl_changeref_val_locovr_attr == SERDES_IP_LANE_L0_CFG_RXNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxntl_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxntl_en_attr == SERDES_IP_LANE_L0_CFG_RXNTL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxntl_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxntl_locovren_attr == SERDES_IP_LANE_L0_CFG_RXNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxntl_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxntl_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxntl_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxntl_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxntl_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxntl_rxm_charge_up_locovr_attr == SERDES_IP_LANE_L0_CFG_RXNTL_RXM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxntl_rxm_pull_dn_locovr_attr == SERDES_IP_LANE_L0_CFG_RXNTL_RXM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxntl_rxm_sense_locovr_attr == SERDES_IP_LANE_L0_CFG_RXNTL_RXM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxntl_rxp_charge_up_locovr_attr == SERDES_IP_LANE_L0_CFG_RXNTL_RXP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxntl_rxp_pull_dn_locovr_attr == SERDES_IP_LANE_L0_CFG_RXNTL_RXP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxntl_rxp_sense_locovr_attr == SERDES_IP_LANE_L0_CFG_RXNTL_RXP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxntl_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_acc_freeze_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_ACC_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_cdrlock2data_gater_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_cdrlock2data_gater_hold_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_cdrlock2data_gater_ovrd_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_cdrlock2datatmr_optcl_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_cdrlock2datatmr_optcl_sel_ovrd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_enter_lock2data_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_ENTER_LOCK2DATA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_enter_lock2data_hold_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_ENTER_LOCK2DATA_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_exit_lock2data_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_EXIT_LOCK2DATA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_exit_lock2data_hold_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_EXIT_LOCK2DATA_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_force_lock2data_ovrd_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_FORCE_LOCK2DATA_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_force_lock2ref_ovrd_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_FORCE_LOCK2REF_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_hold_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_hold_timer_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_intf_ovrd_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_INTF_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_intf_ovrd_type_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_INTF_OVRD_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_mod_freeze_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_MOD_FREEZE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_ovrd_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_ppm_detect_freeze_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_PPM_DETECT_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_ppm_detect_freeze_ovrd_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_PPM_DETECT_FREEZE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_ppm_detect_hold_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_PPM_DETECT_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_prop_freeze_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_PROP_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_prop_freeze_ovrd_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_PROP_FREEZE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_rxdata_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_RXDATA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_skip_init_lock2data_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_SKIP_INIT_LOCK2DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxpam_bitorder_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxpam_gray_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXPAM_GRAY_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxpam_locovren_attr == SERDES_IP_LANE_L0_CFG_RXPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxpam_precode_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXPAM_PRECODE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_muxd0_attr == 7'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_p5_muxd0_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIV_P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_p5_muxd1_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIV_P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_p5_muxd2_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIV_P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_p5_muxd3_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIV_P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_p5_muxd4_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIV_P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdivclken_muxd0_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIVCLKEN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdivclken_muxd1_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIVCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdivclken_muxd2_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIVCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdivclken_muxd3_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIVCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdivclken_muxd4_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIVCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxpcsbist_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXPCSBIST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxpcsbist_locovren_attr == SERDES_IP_LANE_L0_CFG_RXPCSBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxphd_gain_hold_en_attr == SERDES_IP_LANE_L0_CFG_RXPHD_GAIN_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxphd_gain_zero_locovr_attr == SERDES_IP_LANE_L0_CFG_RXPHD_GAIN_ZERO_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxphd_locovren_attr == SERDES_IP_LANE_L0_CFG_RXPHD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxphd_majvote_basegain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxphd_majvote_en_attr == SERDES_IP_LANE_L0_CFG_RXPHD_MAJVOTE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxphd_mute_cntr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxphd_nrz8b10b_pam16b20b_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxphd_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxphd_pam_transition_sel_attr == SERDES_IP_LANE_L0_CFG_RXPHD_PAM_TRANSITION_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxphd_sign_invert_attr == SERDES_IP_LANE_L0_CFG_RXPHD_SIGN_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxpostdiv_wait_for_lock_disable_attr == SERDES_IP_LANE_L0_CFG_RXPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxppm_freq_max_offset_h_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxppm_freq_max_offset_l_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxppm_freq_ref_cnt_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxppm_lockstatus_locovr_attr == SERDES_IP_LANE_L0_CFG_RXPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxppm_lockstatus_synthlcfast_en_attr == SERDES_IP_LANE_L0_CFG_RXPPM_LOCKSTATUS_SYNTHLCFAST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxppm_lockstatus_synthlcmed_en_attr == SERDES_IP_LANE_L0_CFG_RXPPM_LOCKSTATUS_SYNTHLCMED_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxppm_lockstatus_synthlcslow_en_attr == SERDES_IP_LANE_L0_CFG_RXPPM_LOCKSTATUS_SYNTHLCSLOW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxppm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxppm_ppmdriftcount_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxppm_ppmdriftmax_attr == 16'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxppm_status_hold_attr == SERDES_IP_LANE_L0_CFG_RXPPM_STATUS_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxppm_unlock_clear_attr == SERDES_IP_LANE_L0_CFG_RXPPM_UNLOCK_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_fast_muxd0_attr == 16'd1188
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_fast_muxd1_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_fast_muxd2_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_fast_muxd3_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_fast_muxd4_attr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_muxd0_attr == 16'd1188
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_muxd1_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_muxd2_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_muxd3_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_muxd4_attr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxppmctrl_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXPPMCTRL_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxppmctrl_locovren_attr == SERDES_IP_LANE_L0_CFG_RXPPMCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxppmlockstat_locovren_attr == SERDES_IP_LANE_L0_CFG_RXPPMLOCKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxppmlockstat_sticky_locovr_attr == SERDES_IP_LANE_L0_CFG_RXPPMLOCKSTAT_STICKY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxppmtmr_locovren_attr == SERDES_IP_LANE_L0_CFG_RXPPMTMR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxppmtmr_watchdogtmr_sel_locovr_attr == SERDES_IP_LANE_L0_CFG_RXPPMTMR_WATCHDOGTMR_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_cal_clear_delay_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_clk_chk_disable_attr == SERDES_IP_LANE_L0_CFG_RXRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_clk_delay_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_etr_on_delay_attr == 12'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_locovren_attr == SERDES_IP_LANE_L0_CFG_RXRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxreg_lev_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxreg_toggle_reset_on_rate_change_en_attr == SERDES_IP_LANE_L0_CFG_RXREG_TOGGLE_RESET_ON_RATE_CHANGE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxreg_vreg_bypass_attr == SERDES_IP_LANE_L0_CFG_RXREG_VREG_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_en_b_attr == SERDES_IP_LANE_L0_CFG_RXRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s0q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s0q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s2q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s2q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s2q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s2q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s2q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s2q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s2q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s3q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s3q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s3q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s3q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s3q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s3q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s3q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s3q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s4q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s4q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s5q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_entry4_attr == 13'd78
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_entry5_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_entry6_attr == 13'd1406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s0q2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s0q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s1q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s1q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s1q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s1q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s1q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s1q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s2q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s2q2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s2q3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s2q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s2q5_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s2q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s2q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s3q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s3q1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s3q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s3q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s3q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s3q5_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s3q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s3q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s4q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s4q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s5q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_aetrrx_cdrfbdivcken_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_AETRRX_CDRFBDIVCKEN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_aetrrx_cdrfbdivcken_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_AETRRX_CDRFBDIVCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_aetrrx_cdrmoddivcken_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_AETRRX_CDRMODDIVCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_aetrrx_cdrmoddivcken_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_AETRRX_CDRMODDIVCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_aetrrx_termhiz_en_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_AETRRX_TERMHIZ_EN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_aetrrx_termhiz_en_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_AETRRX_TERMHIZ_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_aetrsynth_pcspostdivclksel_ovr_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_AETRSYNTH_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_aetrsynth_pcspostdivclksel_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_AETRSYNTH_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_adc_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_adc_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_auxcomp_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_AUXCOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_auxcomp_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_AUXCOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_bias_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_bias_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_BIAS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_ctlecomp_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_CTLECOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_ctlecomp_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_CTLECOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_datfbdiv_b_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DATFBDIV_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_datfbdiv_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DATFBDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_dfe_bias_b_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DFE_BIAS_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_dfe_bias_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DFE_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_dfe_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DFE_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_dfe_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DFE_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_dfe_yadj_b_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DFE_YADJ_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_dfe_yadj_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DFE_YADJ_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_duty_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DUTY_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_duty_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DUTY_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_hifreqagc_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_HIFREQAGC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_hifreqagc_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_HIFREQAGC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_ntl_b_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_ntl_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_reg_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_reg_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_vco_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_VCO_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_vco_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_VCO_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_voscreg_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_VOSCREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_voscreg_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_VOSCREG_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_adc_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_adc_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_cdrfbdiv_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_CDRFBDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_cdrfbdiv_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_CDRFBDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_pdet_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_PDET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_pdet_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_PDET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_pfd_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_PFD_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_pfd_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_PFD_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_refdiv_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_refdiv_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_reg_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_reg_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_s2pa_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_S2PA_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_s2pa_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_S2PA_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_s2pb_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_S2PB_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_s2pb_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_S2PB_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_vco_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_VCO_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_vco_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_VCO_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_voscreg_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_VOSCREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_voscreg_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_VOSCREG_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstsynth_postdiv_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTSYNTH_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstsynth_postdiv_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTSYNTH_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_drstrx_dpif_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_DRSTRX_DPIF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_drstrx_dpif_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_DRSTRX_DPIF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_drstrx_ppm_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_DRSTRX_PPM_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_drstrx_ppm_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_DRSTRX_PPM_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_cdrlock2data_locovr_attr == SERDES_IP_LANE_L0_CFG_RXSIGDET_CDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_diglfpsdeten_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_diglfpsdeten_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_diglfpsdeten_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_diglfpsdeten_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_diglfpsdeten_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrancnten_muxd0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrancnten_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrancnten_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrancnten_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrancnten_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrancnten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrandeten_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrandeten_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrandeten_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrandeten_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrandeten_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrandeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_eiosdeten_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_eiosdeten_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_eiosdeten_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_eiosdeten_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_eiosdeten_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_eiosdeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_enable_attr == SERDES_IP_LANE_L0_CFG_RXSIGDET_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_fastlock_winsize_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_leveldeten_muxd0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_leveldeten_muxd1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_leveldeten_muxd2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_leveldeten_muxd3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_leveldeten_muxd4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_leveldeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_lfpsexit_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_locovren_attr == SERDES_IP_LANE_L0_CFG_RXSIGDET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_ppmdeten_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_ppmdeten_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_ppmdeten_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_ppmdeten_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_ppmdeten_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_ppmdeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_rxeq_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_rxeqen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_rxeqen_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_rxleveldet_debounce_dncount_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_rxleveldet_debounce_flush_en_attr == SERDES_IP_LANE_L0_CFG_RXSIGDET_RXLEVELDET_DEBOUNCE_FLUSH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_rxleveldet_debounce_upcount_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_sigdet_debounce_attr == SERDES_IP_LANE_L0_CFG_RXSIGDET_SIGDET_DEBOUNCE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_tmr_clksel_attr == SERDES_IP_LANE_L0_CFG_RXSIGDET_TMR_CLKSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_toggle_count_en_attr == SERDES_IP_LANE_L0_CFG_RXSIGDET_TOGGLE_COUNT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_toggle_count_pause_attr == SERDES_IP_LANE_L0_CFG_RXSIGDET_TOGGLE_COUNT_PAUSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_toggle_monitor_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdetin_eiosdetectstat_locovr_attr == SERDES_IP_LANE_L0_CFG_RXSIGDETIN_EIOSDETECTSTAT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdetin_locovren_attr == SERDES_IP_LANE_L0_CFG_RXSIGDETIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdetin_ovrcdrlock2data_locovr_attr == SERDES_IP_LANE_L0_CFG_RXSIGDETIN_OVRCDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdetin_ovrencdrlock2data_locovr_attr == SERDES_IP_LANE_L0_CFG_RXSIGDETIN_OVRENCDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdetout_lock2data_noforce_ltr_locovr_attr == SERDES_IP_LANE_L0_CFG_RXSIGDETOUT_LOCK2DATA_NOFORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsigdetout_locovren_attr == SERDES_IP_LANE_L0_CFG_RXSIGDETOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxspare0_attr == 32'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxspare_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsqlchlfps_consec_one_thresh_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsqlchlfps_consec_zero_thresh_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsqlchlfps_cycle_thresh_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsqlchlfps_dat_bitorder_attr == SERDES_IP_LANE_L0_CFG_RXSQLCHLFPS_DAT_BITORDER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsqlchlfps_debounce_type_attr == SERDES_IP_LANE_L0_CFG_RXSQLCHLFPS_DEBOUNCE_TYPE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsqlchlfps_one_run_length_thresh_attr == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsqlchlfps_one_run_length_timeout_attr == 8'd103
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsqlchlfps_zero_run_length_thresh_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsqlchlfps_zero_run_length_timeout_attr == 8'd103
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsynthdiv_slowmed_en_muxd0_attr == SERDES_IP_LANE_L0_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsynthdiv_slowmed_en_muxd1_attr == SERDES_IP_LANE_L0_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsynthdiv_slowmed_en_muxd2_attr == SERDES_IP_LANE_L0_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsynthdiv_slowmed_en_muxd3_attr == SERDES_IP_LANE_L0_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxsynthdiv_slowmed_en_muxd4_attr == SERDES_IP_LANE_L0_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxterm_cal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxterm_coarse_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxterm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXTERM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxterm_modeselect_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxtermhiz_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXTERMHIZ_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxtermhiz_locovren_attr == SERDES_IP_LANE_L0_CFG_RXTERMHIZ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxvoscreg_bypass_vosc_attr == SERDES_IP_LANE_L0_CFG_RXVOSCREG_BYPASS_VOSC_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxvoscregopampoffsetctrl_sel_attr == SERDES_IP_LANE_L0_CFG_RXVOSCREGOPAMPOFFSETCTRL_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxvoscregopampoffseterr_locovren_attr == SERDES_IP_LANE_L0_CFG_RXVOSCREGOPAMPOFFSETERR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxvoscregopampoffseterr_sel_locovr_attr == SERDES_IP_LANE_L0_CFG_RXVOSCREGOPAMPOFFSETERR_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxvoscregvref_locovren_attr == SERDES_IP_LANE_L0_CFG_RXVOSCREGVREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_rxvoscregvref_sel_locovr_attr == SERDES_IP_LANE_L0_CFG_RXVOSCREGVREF_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlch_acqgain_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlch_acqtime_attr == 13'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlch_cal_quiet_locovr_attr == SERDES_IP_LANE_L0_CFG_SQLCH_CAL_QUIET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlch_cal_sel_locovr_attr == SERDES_IP_LANE_L0_CFG_SQLCH_CAL_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlch_calctrl_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlch_calen_locovr_attr == SERDES_IP_LANE_L0_CFG_SQLCH_CALEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlch_caltimer_attr == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlch_clkgate_locovr_attr == SERDES_IP_LANE_L0_CFG_SQLCH_CLKGATE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlch_cmshiften_attr == SERDES_IP_LANE_L0_CFG_SQLCH_CMSHIFTEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_acq_gain_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_acq_pct_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_cal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_clr_errlog_attr == SERDES_IP_LANE_L0_CFG_SQLCH_CONT_CLR_ERRLOG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_controller_mode_attr == SERDES_IP_LANE_L0_CFG_SQLCH_CONT_CONTROLLER_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_dis_attr == SERDES_IP_LANE_L0_CFG_SQLCH_CONT_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_pause_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_postcal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_precal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_quiet_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlch_lfps_en_attr == SERDES_IP_LANE_L0_CFG_SQLCH_LFPS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlch_locovren_attr == SERDES_IP_LANE_L0_CFG_SQLCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlch_ovrd_val_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlch_pkdet_freqsel_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlch_polarity_attr == SERDES_IP_LANE_L0_CFG_SQLCH_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlch_rdacen_attr == SERDES_IP_LANE_L0_CFG_SQLCH_RDACEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlch_thresh_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlch_time_out_attr == 16'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlch_vrefsel0_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlch_vrefsel1_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlch_vrefsel_ovr_en_attr == SERDES_IP_LANE_L0_CFG_SQLCH_VREFSEL_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlchdeb_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlchdeb_deb_cnt_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlchdeb_deb_status_cnt_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlchdeb_en_attr == SERDES_IP_LANE_L0_CFG_SQLCHDEB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlchdeb_ign_cnt_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlchdeb_sigdet_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlchdeb_thresh_cnt_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlchdebout_exit_good_debounced_locovr_attr == SERDES_IP_LANE_L0_CFG_SQLCHDEBOUT_EXIT_GOOD_DEBOUNCED_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlchdebout_exit_good_debounced_status_locovr_attr == SERDES_IP_LANE_L0_CFG_SQLCHDEBOUT_EXIT_GOOD_DEBOUNCED_STATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlchdebout_exit_good_locovr_attr == SERDES_IP_LANE_L0_CFG_SQLCHDEBOUT_EXIT_GOOD_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_sqlchdebout_locovren_attr == SERDES_IP_LANE_L0_CFG_SQLCHDEBOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_trancnt_off_attr == 10'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_trancnt_on_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_trancntout_det_locovr_attr == SERDES_IP_LANE_L0_CFG_TRANCNTOUT_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_trancntout_locovren_attr == SERDES_IP_LANE_L0_CFG_TRANCNTOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_trandet_ax_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_trandet_ay_attr == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_trandet_off_h_attr == 6'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_trandet_off_l_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_trandet_on_h_attr == 6'd39
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_trandet_on_l_attr == 6'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_trandetout_det_locovr_attr == SERDES_IP_LANE_L0_CFG_TRANDETOUT_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_trandetout_locovren_attr == SERDES_IP_LANE_L0_CFG_TRANDETOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_tx2rxlb_en_attr == SERDES_IP_LANE_L0_CFG_TX2RXLB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_tx2rxlb_init_offset_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_tx_cmn_on_state_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_tx_fastregpwrup_en_attr == SERDES_IP_LANE_L0_CFG_TX_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_tx_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_tx_pg_disable_attr == SERDES_IP_LANE_L0_CFG_TX_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_tx_synth_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_tx_synth_sel_amode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_tx_synth_sel_bmode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_tx_synth_sel_cmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_tx_synth_sel_dmode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_tx_synth_sel_emode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_tx_txdetrx_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txadc_req_attr == SERDES_IP_LANE_L0_CFG_TXADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txaprobe_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txaprobe_lastmux_isolate_attr == SERDES_IP_LANE_L0_CFG_TXAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txaprobeadc_current_direction_attr == SERDES_IP_LANE_L0_CFG_TXAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txaprobeadc_resistor_enable_attr == SERDES_IP_LANE_L0_CFG_TXAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txbdvdr_pma2pcstxworden_attr == SERDES_IP_LANE_L0_CFG_TXBDVDR_PMA2PCSTXWORDEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txbeacon_div_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txbeacon_sel_attr == SERDES_IP_LANE_L0_CFG_TXBEACON_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txbias_icc20uadj_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txbias_icc80uadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txbias_locovren_attr == SERDES_IP_LANE_L0_CFG_TXBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txbias_termcal_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txbist_biterror_en_attr == SERDES_IP_LANE_L0_CFG_TXBIST_BITERROR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txbist_locovren_attr == SERDES_IP_LANE_L0_CFG_TXBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txbist_modesel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txbist_oobmode_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txbist_oobtburst_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txbist_oobtcomrstinit_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txbist_oobtcomsas_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txbist_oobtcomwake_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txbist_seed_attr == 31'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_size_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf00_attr == 32'd1985229328
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf01_attr == 32'd4275878552
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf02_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf03_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf04_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf05_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf06_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf07_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf08_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf09_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txbit_select_muxd0_attr == SERDES_IP_LANE_L0_CFG_TXBIT_SELECT_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txbit_select_muxd1_attr == SERDES_IP_LANE_L0_CFG_TXBIT_SELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txbit_select_muxd2_attr == SERDES_IP_LANE_L0_CFG_TXBIT_SELECT_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txbit_select_muxd3_attr == SERDES_IP_LANE_L0_CFG_TXBIT_SELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txbit_select_muxd4_attr == SERDES_IP_LANE_L0_CFG_TXBIT_SELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txbti_data_replication_attr == SERDES_IP_LANE_L0_CFG_TXBTI_DATA_REPLICATION_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txbti_tx_idle_data_en_attr == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcal_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcal_tclkduty_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalduty_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalduty_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTY_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalduty_sel_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutybg_abort_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutybg_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutybg_ready_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutycomp_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutycomp_offset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_finish_side_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_init_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_initval_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_invert_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_req_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_round_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_runcount_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_signmagen_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsmout_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsmout_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompmeas_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompmeas_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompmeas_req_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompmeasout_ack_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPMEASOUT_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompmeasout_erravg_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPMEASOUT_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompmeasout_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_bg_en_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_bg_one_step_cal_en_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_finish_side_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_init_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_invert_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_req_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_round_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_runcount_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_signmagen_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeas_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeas_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeas_req_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeasout_ack_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYMEASOUT_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeasout_erravg_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYMEASOUT_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeasout_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutystat_done_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaldutystat_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalptr_pstate_duty_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalptr_pstate_dutycomp_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalptr_pstate_regopampoffset_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_duty_muxd0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_duty_muxd1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_duty_muxd2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_duty_muxd3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_duty_muxd4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_dutycomp_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_dutycomp_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_dutycomp_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_dutycomp_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_dutycomp_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_regopampoffset_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffset_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_finish_side_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_round_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_runcount_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_signmagen_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcaltclkdutyforce_div1_attr == SERDES_IP_LANE_L0_CFG_TXCALTCLKDUTYFORCE_DIV1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txcdrdiv_local_en_attr == SERDES_IP_LANE_L0_CFG_TXCDRDIV_LOCAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txclk_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txclk_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txclkgenmuxsel_txinternal_attr == SERDES_IP_LANE_L0_CFG_TXCLKGENMUXSEL_TXINTERNAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txdetectrx_thr_attr == 5'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeas_count_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeas_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXDETECTRXMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeas_locovren_attr == SERDES_IP_LANE_L0_CFG_TXDETECTRXMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeas_validdlycount_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeasin_locovren_attr == SERDES_IP_LANE_L0_CFG_TXDETECTRXMEASIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeasin_start_locovr_attr == SERDES_IP_LANE_L0_CFG_TXDETECTRXMEASIN_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeaspcs_locovren_attr == SERDES_IP_LANE_L0_CFG_TXDETECTRXMEASPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeaspcs_req_locovr_attr == SERDES_IP_LANE_L0_CFG_TXDETECTRXMEASPCS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeasval_locovren_attr == SERDES_IP_LANE_L0_CFG_TXDETECTRXMEASVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeasval_stat_locovr_attr == SERDES_IP_LANE_L0_CFG_TXDETECTRXMEASVAL_STAT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txdetrx_levn_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txdetrx_levnm1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txdetrx_levnp1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txdetrx_levnp2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txdrv_hizen_locovr_attr == SERDES_IP_LANE_L0_CFG_TXDRV_HIZEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txdrv_levn_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txdrv_levnm1_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txdrv_levnp1_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txdrv_levnp2_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txdrv_locovren_attr == SERDES_IP_LANE_L0_CFG_TXDRV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txdrv_refcken_attr == SERDES_IP_LANE_L0_CFG_TXDRV_REFCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txdrv_termref_attr == SERDES_IP_LANE_L0_CFG_TXDRV_TERMREF_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txdrvmute_locovr_attr == SERDES_IP_LANE_L0_CFG_TXDRVMUTE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txdrvmute_locovren_attr == SERDES_IP_LANE_L0_CFG_TXDRVMUTE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txduty_ctrl_disable_attr == SERDES_IP_LANE_L0_CFG_TXDUTY_CTRL_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txduty_pad_sense_en_attr == SERDES_IP_LANE_L0_CFG_TXDUTY_PAD_SENSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txdutycal_div16_en_attr == SERDES_IP_LANE_L0_CFG_TXDUTYCAL_DIV16_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txdutycal_div1_en_attr == SERDES_IP_LANE_L0_CFG_TXDUTYCAL_DIV1_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txdutycal_div2_en_attr == SERDES_IP_LANE_L0_CFG_TXDUTYCAL_DIV2_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txdutycal_div4_en_attr == SERDES_IP_LANE_L0_CFG_TXDUTYCAL_DIV4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txdutycal_div8_en_attr == SERDES_IP_LANE_L0_CFG_TXDUTYCAL_DIV8_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txfifo_elecidle_deskew_en_attr == SERDES_IP_LANE_L0_CFG_TXFIFO_ELECIDLE_DESKEW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txfifo_force_txidlebit1_zero_disable_attr == SERDES_IP_LANE_L0_CFG_TXFIFO_FORCE_TXIDLEBIT1_ZERO_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txfifo_kill_dly_10b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txfifo_kill_dly_16b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txfifo_kill_dly_20b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txfifo_kill_dly_32b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txfifo_kill_dly_40b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txfifo_kill_dly_64b_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txfifo_kill_dly_80b_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txfifo_kill_dly_8b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txfifo_kill_en_attr == SERDES_IP_LANE_L0_CFG_TXFIFO_KILL_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txfsm_cken_ovr_attr == SERDES_IP_LANE_L0_CFG_TXFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txfsm_cken_ovren_attr == SERDES_IP_LANE_L0_CFG_TXFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txfsm_main_on_state_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txl1d1_doze_ctrl_attr == SERDES_IP_LANE_L0_CFG_TXL1D1_DOZE_CTRL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txl1d1_txbias_ctrl_attr == SERDES_IP_LANE_L0_CFG_TXL1D1_TXBIAS_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txlanepam_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXLANEPAM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txlanepam_locovren_attr == SERDES_IP_LANE_L0_CFG_TXLANEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txmeaslatovrhd_meas_sel_attr == SERDES_IP_LANE_L0_CFG_TXMEASLATOVRHD_MEAS_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txmute_delay_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txntl_changeref_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txntl_changeref_val_locovr_attr == SERDES_IP_LANE_L0_CFG_TXNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txntl_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txntl_en_attr == SERDES_IP_LANE_L0_CFG_TXNTL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txntl_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txntl_locovren_attr == SERDES_IP_LANE_L0_CFG_TXNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txntl_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txntl_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txntl_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txntl_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txntl_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txntl_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txntl_txm_charge_up_locovr_attr == SERDES_IP_LANE_L0_CFG_TXNTL_TXM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txntl_txm_pull_dn_locovr_attr == SERDES_IP_LANE_L0_CFG_TXNTL_TXM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txntl_txm_sense_locovr_attr == SERDES_IP_LANE_L0_CFG_TXNTL_TXM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txntl_txp_charge_up_locovr_attr == SERDES_IP_LANE_L0_CFG_TXNTL_TXP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txntl_txp_pull_dn_locovr_attr == SERDES_IP_LANE_L0_CFG_TXNTL_TXP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txntl_txp_sense_locovr_attr == SERDES_IP_LANE_L0_CFG_TXNTL_TXP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txp2s_txwordsyncbypen_attr == SERDES_IP_LANE_L0_CFG_TXP2S_TXWORDSYNCBYPEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txpam_bitorder_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txpam_gray_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXPAM_GRAY_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txpam_locovren_attr == SERDES_IP_LANE_L0_CFG_TXPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txpam_precode_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXPAM_PRECODE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txpcs_locovren_attr == SERDES_IP_LANE_L0_CFG_TXPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txpcs_txenable_locovr_attr == SERDES_IP_LANE_L0_CFG_TXPCS_TXENABLE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txpcsbist_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXPCSBIST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txpcsbist_locovren_attr == SERDES_IP_LANE_L0_CFG_TXPCSBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txratewidth_clk_chk_disable_attr == SERDES_IP_LANE_L0_CFG_TXRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txratewidth_etr_on_delay_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txratewidth_locovren_attr == SERDES_IP_LANE_L0_CFG_TXRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txreg_toggle_pwrupacc_on_rate_change_en_attr == SERDES_IP_LANE_L0_CFG_TXREG_TOGGLE_PWRUPACC_ON_RATE_CHANGE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txreg_toggle_reset_on_rate_change_en_attr == SERDES_IP_LANE_L0_CFG_TXREG_TOGGLE_RESET_ON_RATE_CHANGE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txresetdel_sel_attr == SERDES_IP_LANE_L0_CFG_TXRESETDEL_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_en_b_attr == SERDES_IP_LANE_L0_CFG_TXRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s0q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s0q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s1q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s1q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s2q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s2q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s2q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s2q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s2q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s2q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s2q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s3q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s3q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s3q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s3q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s3q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s3q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s3q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s3q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s4q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s4q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s5q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s0q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s0q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s1q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s1q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s1q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s1q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s1q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s1q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s2q0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s2q1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s2q2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s2q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s2q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s2q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s2q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s2q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s3q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s3q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s3q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s3q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s3q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s3q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s3q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s3q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s4q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s4q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s5q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_dn_ptr0_s_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_up_ptr0_s_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_aetrtx_bitckdvdrcken_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_AETRTX_BITCKDVDRCKEN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_aetrtx_bitckdvdrcken_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_AETRTX_BITCKDVDRCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_aetrtx_regpwrupacc_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_AETRTX_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_aetrtx_regpwrupacc_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_AETRTX_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_adc_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_adc_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_drvdoze_b_ovr_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_DRVDOZE_B_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_drvdoze_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_DRVDOZE_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_duty_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_DUTY_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_duty_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_DUTY_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_ntl_b_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_ntl_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_p2s_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_P2S_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_p2s_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_P2S_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_reg_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_reg_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_arsttx_adc_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_ARSTTX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_arsttx_adc_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_ARSTTX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_arsttx_pma2pcstxword_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_ARSTTX_PMA2PCSTXWORD_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_arsttx_pma2pcstxword_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_ARSTTX_PMA2PCSTXWORD_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_arsttx_regreset_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_ARSTTX_REGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_arsttx_regreset_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_ARSTTX_REGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_arsttx_txdetectrx_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_ARSTTX_TXDETECTRX_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_arsttx_txdetectrx_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_ARSTTX_TXDETECTRX_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txrststate_hiz_en_attr == SERDES_IP_LANE_L0_CFG_TXRSTSTATE_HIZ_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txspare0_attr == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txspare_attr == 10'd384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txterm_coarse_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txtermtrim_locovren_attr == SERDES_IP_LANE_L0_CFG_TXTERMTRIM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txtermtrim_nmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txtermtrim_pmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txwclk_div_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txwclk_div_en_attr == SERDES_IP_LANE_L0_CFG_TXWCLK_DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txwclk_div_smpl_attr == SERDES_IP_LANE_L0_CFG_TXWCLK_DIV_SMPL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txwptr_init01_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txwptr_init02_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txwptr_init04_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txwptr_init08_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txwptr_init16_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txwptr_init32_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l0_cfg_txwptr_init_rx2txparlb_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_bshihyst_attr == SERDES_IP_LANE_L1_CFG_BSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_bstxdrv_levn_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_bstxdrv_levnm1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_bstxdrv_levnp1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_bstxdrv_levnp2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_calsqlchosc_locovren_attr == SERDES_IP_LANE_L1_CFG_CALSQLCHOSC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_calsqlchosc_trimcode_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_cdrclkstat_locovren_attr == SERDES_IP_LANE_L1_CFG_CDRCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_cdrclkstat_ready_locovr_attr == SERDES_IP_LANE_L1_CFG_CDRCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_etrregrxcdrclk_ready_attr == SERDES_IP_LANE_L1_CFG_ETRREGRXCDRCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_laneckm_avg_en_attr == SERDES_IP_LANE_L1_CFG_LANECKM_AVG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_laneckm_clk_en_attr == SERDES_IP_LANE_L1_CFG_LANECKM_CLK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_laneckm_continuous_attr == SERDES_IP_LANE_L1_CFG_LANECKM_CONTINUOUS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_laneckm_dig_meas_en_attr == SERDES_IP_LANE_L1_CFG_LANECKM_DIG_MEAS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_laneckm_dig_meas_err_clr_attr == SERDES_IP_LANE_L1_CFG_LANECKM_DIG_MEAS_ERR_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_laneckm_en_attr == SERDES_IP_LANE_L1_CFG_LANECKM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_laneckm_max_thr_attr == 25'd33554431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_laneckm_meas_ck_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_laneckm_ref_ck_div_ratio_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_laneckm_result_clr_attr == SERDES_IP_LANE_L1_CFG_LANECKM_RESULT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_laneckm_start_attr == SERDES_IP_LANE_L1_CFG_LANECKM_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_laneckm_wdt_interval_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_laneckm_win_thr_ref_attr == 25'd16777215
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_lanepcs_locovren_attr == SERDES_IP_LANE_L1_CFG_LANEPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_lanepcs_mode_locovr_attr == SERDES_IP_LANE_L1_CFG_LANEPCS_MODE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_laneperfmon_compare_val_start_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_laneperfmon_compare_val_stop_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_laneperfmon_en_attr == SERDES_IP_LANE_L1_CFG_LANEPERFMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_laneperfmon_mask_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_lanepmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_lanepmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_lanepmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_lanepmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_lanepmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_lanepmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_lb_cdrclk2txen_locovr_attr == SERDES_IP_LANE_L1_CFG_LB_CDRCLK2TXEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_lb_cdrclkdiven_attr == SERDES_IP_LANE_L1_CFG_LB_CDRCLKDIVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_lb_cdrdivclk2exten_attr == SERDES_IP_LANE_L1_CFG_LB_CDRDIVCLK2EXTEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_lb_cdrdivclk2txen_attr == SERDES_IP_LANE_L1_CFG_LB_CDRDIVCLK2TXEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_lb_hsclk2cdrdiven_attr == SERDES_IP_LANE_L1_CFG_LB_HSCLK2CDRDIVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_lb_locovren_attr == SERDES_IP_LANE_L1_CFG_LB_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_lb_parrx2txtimeden_locovr_attr == SERDES_IP_LANE_L1_CFG_LB_PARRX2TXTIMEDEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_lb_pllfbclk2cdrrefclken_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_lb_pllfbclk2cdrrefclken_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_lb_pllfbclk2cdrrefclken_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_lb_pllfbclk2cdrrefclken_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_lb_pllfbclk2cdrrefclken_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_lb_rx2txuntimeden_attr == SERDES_IP_LANE_L1_CFG_LB_RX2TXUNTIMEDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_lb_rxwordck2pcstxwordcken_attr == SERDES_IP_LANE_L1_CFG_LB_RXWORDCK2PCSTXWORDCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_lb_tx2rxbuftimeden_lsb_locovr_attr == SERDES_IP_LANE_L1_CFG_LB_TX2RXBUFTIMEDEN_LSB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_lb_tx2rxbuftimeden_msb_locovr_attr == SERDES_IP_LANE_L1_CFG_LB_TX2RXBUFTIMEDEN_MSB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_lb_tx2rxiotimeden_attr == SERDES_IP_LANE_L1_CFG_LB_TX2RXIOTIMEDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_lfps_det_locovr_attr == SERDES_IP_LANE_L1_CFG_LFPS_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_lfps_locovren_attr == SERDES_IP_LANE_L1_CFG_LFPS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_lfps_out_en_attr == SERDES_IP_LANE_L1_CFG_LFPS_OUT_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_pcslfps_en_locovr_attr == SERDES_IP_LANE_L1_CFG_PCSLFPS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_pcslfps_locovren_attr == SERDES_IP_LANE_L1_CFG_PCSLFPS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_pcsrx_dme_en_locovr_attr == SERDES_IP_LANE_L1_CFG_PCSRX_DME_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_pcsrx_locovren_attr == SERDES_IP_LANE_L1_CFG_PCSRX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_pcsrxbist_locovren_attr == SERDES_IP_LANE_L1_CFG_PCSRXBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_pcsrxbist_modesel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_pcstx_beaconen_locovr_attr == SERDES_IP_LANE_L1_CFG_PCSTX_BEACONEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_pcstx_locovren_attr == SERDES_IP_LANE_L1_CFG_PCSTX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_polarity_rx_attr == SERDES_IP_LANE_L1_CFG_POLARITY_RX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_polarity_tx_attr == SERDES_IP_LANE_L1_CFG_POLARITY_TX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rx_cmn_on_state_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rx_fastregpwrup_en_attr == SERDES_IP_LANE_L1_CFG_RX_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rx_frac_mode_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rx_on_state_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rx_pg_disable_attr == SERDES_IP_LANE_L1_CFG_RX_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rx_synth_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rx_synth_sel_amode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rx_synth_sel_bmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rx_synth_sel_cmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rx_synth_sel_dmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rx_synth_sel_emode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxadc_req_attr == SERDES_IP_LANE_L1_CFG_RXADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxagc_dccoupleen_attr == SERDES_IP_LANE_L1_CFG_RXAGC_DCCOUPLEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxaprobe_addr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxaprobe_lastmux_isolate_attr == SERDES_IP_LANE_L1_CFG_RXAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxaprobeadc_current_direction_attr == SERDES_IP_LANE_L1_CFG_RXAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxaprobeadc_resistor_enable_attr == SERDES_IP_LANE_L1_CFG_RXAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxbias_iccadj_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxbias_icvadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxbias_locovren_attr == SERDES_IP_LANE_L1_CFG_RXBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxbias_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxbist_burst_four_errtype_attr == SERDES_IP_LANE_L1_CFG_RXBIST_BURST_FOUR_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxbist_burst_one_errtype_attr == SERDES_IP_LANE_L1_CFG_RXBIST_BURST_ONE_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxbist_burst_three_errtype_attr == SERDES_IP_LANE_L1_CFG_RXBIST_BURST_THREE_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxbist_burst_two_errtype_attr == SERDES_IP_LANE_L1_CFG_RXBIST_BURST_TWO_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxbist_cdrlock2data_bypass_attr == SERDES_IP_LANE_L1_CFG_RXBIST_CDRLOCK2DATA_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxbist_cdrlock2data_postamble_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxbist_clear_errcount_attr == SERDES_IP_LANE_L1_CFG_RXBIST_CLEAR_ERRCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxbist_err_en_attr == SERDES_IP_LANE_L1_CFG_RXBIST_ERR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxbist_err_trig_type_attr == SERDES_IP_LANE_L1_CFG_RXBIST_ERR_TRIG_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxbist_errmask_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxbist_errtype_attr == SERDES_IP_LANE_L1_CFG_RXBIST_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxbist_firsterr_type_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxbist_lockchk_count_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxbist_maxbitcnt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxbist_mostrecent_err_attr == SERDES_IP_LANE_L1_CFG_RXBIST_MOSTRECENT_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxbist_relock_itercount_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxbist_seed_attr == 31'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxbist_status_hold_attr == SERDES_IP_LANE_L1_CFG_RXBIST_STATUS_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxbitslip_locovr_attr == SERDES_IP_LANE_L1_CFG_RXBITSLIP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxbitslip_locovren_attr == SERDES_IP_LANE_L1_CFG_RXBITSLIP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxbscan_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxbshicm_attr == SERDES_IP_LANE_L1_CFG_RXBSHICM_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalcdrfbdiv_div2_bypass_muxd0_attr == SERDES_IP_LANE_L1_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalcdrfbdiv_div2_bypass_muxd1_attr == SERDES_IP_LANE_L1_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalcdrfbdiv_div2_bypass_muxd2_attr == SERDES_IP_LANE_L1_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalcdrfbdiv_div2_bypass_muxd3_attr == SERDES_IP_LANE_L1_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalcdrfbdiv_div2_bypass_muxd4_attr == SERDES_IP_LANE_L1_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalduty_iclk_gray_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalduty_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTY_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalduty_qclk_gray_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalduty_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutybg_abort_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutybg_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutybg_ready_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycomp_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycomp_offset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_finish_side_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_init_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_initval_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_invert_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_round_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_runcount_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_signmagen_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsmout_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsmout_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_disable_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCTRL_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_i_div1_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_i_div2_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_i_div4_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_i_div8_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_q_div1_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_q_div2_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_q_div4_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_q_div8_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_bg_en_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_bg_one_step_cal_en_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_finish_side_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_i_polarity_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_I_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_i_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_I_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_init_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_q_polarity_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_Q_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_q_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_Q_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_round_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_runcount_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_signmagen_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_comp_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEAS_COMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_comp_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEAS_COMP_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_i_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEAS_I_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_i_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEAS_I_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_q_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEAS_Q_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_q_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEAS_Q_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeasout_comp_ack_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEASOUT_COMP_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeasout_comp_erravg_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEASOUT_COMP_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeasout_i_ack_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEASOUT_I_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeasout_i_erravg_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEASOUT_I_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeasout_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeasout_q_ack_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEASOUT_Q_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeasout_q_erravg_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEASOUT_Q_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutystat_done_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaldutystat_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_centerfreq_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_end_delay_attr == 9'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_hscount_muxd0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_hscount_muxd1_attr == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_hscount_muxd2_attr == 8'd180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_hscount_muxd3_attr == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_hscount_muxd4_attr == 8'd206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_initval_centerfreq_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_initval_fosc_attr == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_centerfreq_finish_side_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_CENTERFREQ_FINISH_SIDE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_centerfreq_to_fosc_offset_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_centerfreqen_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_CENTERFREQEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_centerfreqoffset_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_fosc_finishside_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_FOSC_FINISHSIDE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_foscen_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_FOSCEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_foscoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_init_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_invert_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_lpfax_calfosccoarse_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_lpfax_calfoscfine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_lpfax_centerfreqcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_lpfax_centerfreqfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_runcount_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_signmagen_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_vcorepen_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_VCOREPEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsmout_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsmout_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_count_muxd0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_count_muxd1_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_count_muxd2_attr == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_count_muxd3_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_count_muxd4_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_dlycount_attr == 9'd68
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeasout_clear_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCMEASOUT_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeasout_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeasout_start_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCMEASOUT_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscval_int_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscval_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalintsval_int_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalintsval_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALINTSVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaloffsetfsm_init_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaloffsetfsm_init_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaloffsetfsm_init_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALOFFSETFSM_INIT_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaloffsetfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcaloffsetfsmout_input_en_attr == SERDES_IP_LANE_L1_CFG_RXCALOFFSETFSMOUT_INPUT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_duty_i_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_duty_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_dutycomp_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_foscfsm_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_offsetfsm_init_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_regopampoffset_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_rxppm_lockstatus_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_sqlch_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_sqlchosc_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_synthppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_voscregopampoffset_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_duty_i_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_duty_q_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_dutycomp_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_foscfsm_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_offsetfsm_init_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_rxppm_lockstatus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_sqlch_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_sqlchosc_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_synthppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_voscregopampoffset_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffset_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_finish_side_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_round_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_runcount_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_signmagen_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchfsm_clear_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchfsm_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchfsmout_caldone_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHFSMOUT_CALDONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchfsmout_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_codeoffset_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_finish_side_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHOSCFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_init_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHOSCFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_initval_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_invert_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHOSCFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHOSCFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHOSCFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_round_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHOSCFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_runcount_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHOSCFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscmeas_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHOSCMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscmeas_ref_cnt_attr == 10'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscmeas_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHOSCMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscmeas_settle_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscmeas_smpl_cnt_attr == 10'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvbiascap_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALVBIASCAP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvbiascap_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALVBIASCAP_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvcoopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvcoopampoffsetmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvcoopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvcoopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffset_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffset_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_codeoffset_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_finish_side_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_initval_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_invert_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_lpfaxcoarse_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_round_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_runcount_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETFSM_RUNCOUNT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_signmagen_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsmout_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsmout_runcount_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETFSMOUT_RUNCOUNT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetmeas_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffset_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALVOSCREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALVOSCREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L1_CFG_RXCALVOSCREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALVOSCREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALVOSCREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALVOSCREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALVOSCREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALVOSCREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALVOSCREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrdiv_local_en_attr == SERDES_IP_LANE_L1_CFG_RXCDRDIV_LOCAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdiv_moddiv_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdiv_moddiv_muxd1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdiv_moddiv_muxd2_attr == 4'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdiv_moddiv_muxd3_attr == 4'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdiv_moddiv_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdivslip_mdiv_muxd0_attr == 9'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdivslip_mdiv_muxd1_attr == 9'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdivslip_mdiv_muxd2_attr == 9'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdivslip_mdiv_muxd3_attr == 9'd66
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdivslip_mdiv_muxd4_attr == 9'd210
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrpfd_forcedn_attr == SERDES_IP_LANE_L1_CFG_RXCDRPFD_FORCEDN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrpfd_forceen_attr == SERDES_IP_LANE_L1_CFG_RXCDRPFD_FORCEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrpfd_forceup_attr == SERDES_IP_LANE_L1_CFG_RXCDRPFD_FORCEUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrpfd_propgain_attr == SERDES_IP_LANE_L1_CFG_RXCDRPFD_PROPGAIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrpfd_pulsewidth_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrphd_asym_override_ignore_attr == SERDES_IP_LANE_L1_CFG_RXCDRPHD_ASYM_OVERRIDE_IGNORE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrphd_bitshift_en_attr == SERDES_IP_LANE_L1_CFG_RXCDRPHD_BITSHIFT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrphd_forcedn_attr == SERDES_IP_LANE_L1_CFG_RXCDRPHD_FORCEDN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrphd_forceen_attr == SERDES_IP_LANE_L1_CFG_RXCDRPHD_FORCEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrphd_forceup_attr == SERDES_IP_LANE_L1_CFG_RXCDRPHD_FORCEUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrphdrate_doublerate2s2p_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCDRPHDRATE_DOUBLERATE2S2P_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrphdrate_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCDRPHDRATE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrrefck_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrrefck_refdiv_muxd1_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrrefck_refdiv_muxd2_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrrefck_refdiv_muxd3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrrefck_refdiv_muxd4_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_biastop_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_biastopbypass_attr == SERDES_IP_LANE_L1_CFG_RXCDRVCO_BIASTOPBYPASS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_datapropgain_high_attr == 5'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_datapropgain_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_datapropgain_low_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_ff_ovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_ff_ovr_en_attr == SERDES_IP_LANE_L1_CFG_RXCDRVCO_FF_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_fil_short_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_flickerdegen_attr == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_gmfoscshort_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCDRVCO_GMFOSCSHORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_intf_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_intf_fil_short_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_intrj_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCDRVCO_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_refpropgain_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_refpropgain_nom_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxclk_cdrfb_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCLK_CDRFB_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxclk_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxclk_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdat_nrz_64b80b_bcword_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdata_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXDATA_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdata_locovren_attr == SERDES_IP_LANE_L1_CFG_RXDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdatapath_locovren_attr == SERDES_IP_LANE_L1_CFG_RXDATAPATH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdatapath_on_state_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdatapath_ready_locovr_attr == SERDES_IP_LANE_L1_CFG_RXDATAPATH_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdfe_datatap_vcasc_attr == 4'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdfe_dfebiasadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdfe_nbiasctle_en_attr == SERDES_IP_LANE_L1_CFG_RXDFE_NBIASCTLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdfe_vcasc_sel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdfeterm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXDFETERM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdfeterm_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdfeyadjdac_datamid_edge_coarse_en_attr == SERDES_IP_LANE_L1_CFG_RXDFEYADJDAC_DATAMID_EDGE_COARSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdfeyadjdac_datatopbot_aux_coarse_en_attr == SERDES_IP_LANE_L1_CFG_RXDFEYADJDAC_DATATOPBOT_AUX_COARSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_accum_mon_en_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_ACCUM_MON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_accum_mon_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_bypasscdrpdetupdnsmpl_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_bypassenfosc_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_BYPASSENFOSC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_bypassenints_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_BYPASSENINTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_bypassenupdnsmpl_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_BYPASSENUPDNSMPL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_bypassfosc_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_bypasspllpfdupdnsmpl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_bypassrxints_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_data2pll_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_deltasigmode_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_DELTASIGMODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_fastref_muxd0_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_FASTREF_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_fastref_muxd1_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_FASTREF_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_fastref_muxd2_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_FASTREF_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_fastref_muxd3_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_FASTREF_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_fastref_muxd4_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_FASTREF_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_fosc_mod_bypass_en_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_FOSC_MOD_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_fosc_sample_pedge_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_FOSC_SAMPLE_PEDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gain_step_on_lock_recovery_en_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_GAIN_STEP_ON_LOCK_RECOVERY_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gaindelaycount_init_attr == 9'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gaindelaycount_pow2_muxd0_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gaindelaycount_pow2_muxd1_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gaindelaycount_pow2_muxd2_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gaindelaycount_pow2_muxd3_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gaindelaycount_pow2_muxd4_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2ref_pow2_muxd0_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2ref_pow2_muxd1_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2ref_pow2_muxd2_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2ref_pow2_muxd3_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2ref_pow2_muxd4_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainunlocked_pow2_muxd0_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainunlocked_pow2_muxd1_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainunlocked_pow2_muxd2_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainunlocked_pow2_muxd3_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainunlocked_pow2_muxd4_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_initintegrator_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_INITINTEGRATOR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_initmodulator_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_INITMODULATOR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_deltasig_mode_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_INTS_DELTASIG_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_freeze_en_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_INTS_FREEZE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gaindelaycount_pow2_muxd0_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gaindelaycount_pow2_muxd1_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gaindelaycount_pow2_muxd2_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gaindelaycount_pow2_muxd3_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gaindelaycount_pow2_muxd4_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd0_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd1_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd2_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd3_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd4_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd0_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd1_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd2_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd3_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd4_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainunlocked_pow2_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainunlocked_pow2_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainunlocked_pow2_muxd2_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainunlocked_pow2_muxd3_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainunlocked_pow2_muxd4_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_guardband_hi_attr == 8'd200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_guardband_lo_attr == 8'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_loop_sel_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_INTS_LOOP_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_mod_bypass_en_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_INTS_MOD_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_mod_load_pedge_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_INTS_MOD_LOAD_PEDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_step_to_integer_en_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_INTS_STEP_TO_INTEGER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_jit_length_attr == 18'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_jit_mode_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_JIT_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_modck_ctrl_en_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_MODCK_CTRL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_pll2data_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_restore_cntr_attr == 9'd258
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_store_cntr_attr == 16'd258
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpif_trnsfrdelay_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpiffreeze_inten_attr == SERDES_IP_LANE_L1_CFG_RXDPIFFREEZE_INTEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdpiffreeze_moden_attr == SERDES_IP_LANE_L1_CFG_RXDPIFFREEZE_MODEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxdutyselpolarity_attr == SERDES_IP_LANE_L1_CFG_RXDUTYSELPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxflxgate_force_rxeq_gate_locovr_attr == SERDES_IP_LANE_L1_CFG_RXFLXGATE_FORCE_RXEQ_GATE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxflxgate_locovren_attr == SERDES_IP_LANE_L1_CFG_RXFLXGATE_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxfoscstat_done_locovr_attr == SERDES_IP_LANE_L1_CFG_RXFOSCSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxfoscstat_locovren_attr == SERDES_IP_LANE_L1_CFG_RXFOSCSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxfsm_cken_ovr_attr == SERDES_IP_LANE_L1_CFG_RXFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxfsm_cken_ovren_attr == SERDES_IP_LANE_L1_CFG_RXFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxints_prev_votes_hold_en_attr == SERDES_IP_LANE_L1_CFG_RXINTS_PREV_VOTES_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxlanepam_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXLANEPAM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxlanepam_locovren_attr == SERDES_IP_LANE_L1_CFG_RXLANEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxlock2datatmr_attr == 8'd240
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxlock2datatmr_short_attr == 8'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxntl_changeref_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxntl_changeref_val_locovr_attr == SERDES_IP_LANE_L1_CFG_RXNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxntl_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxntl_en_attr == SERDES_IP_LANE_L1_CFG_RXNTL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxntl_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxntl_locovren_attr == SERDES_IP_LANE_L1_CFG_RXNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxntl_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxntl_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxntl_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxntl_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxntl_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxntl_rxm_charge_up_locovr_attr == SERDES_IP_LANE_L1_CFG_RXNTL_RXM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxntl_rxm_pull_dn_locovr_attr == SERDES_IP_LANE_L1_CFG_RXNTL_RXM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxntl_rxm_sense_locovr_attr == SERDES_IP_LANE_L1_CFG_RXNTL_RXM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxntl_rxp_charge_up_locovr_attr == SERDES_IP_LANE_L1_CFG_RXNTL_RXP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxntl_rxp_pull_dn_locovr_attr == SERDES_IP_LANE_L1_CFG_RXNTL_RXP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxntl_rxp_sense_locovr_attr == SERDES_IP_LANE_L1_CFG_RXNTL_RXP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxntl_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_acc_freeze_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_ACC_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_cdrlock2data_gater_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_cdrlock2data_gater_hold_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_cdrlock2data_gater_ovrd_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_cdrlock2datatmr_optcl_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_cdrlock2datatmr_optcl_sel_ovrd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_enter_lock2data_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_ENTER_LOCK2DATA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_enter_lock2data_hold_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_ENTER_LOCK2DATA_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_exit_lock2data_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_EXIT_LOCK2DATA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_exit_lock2data_hold_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_EXIT_LOCK2DATA_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_force_lock2data_ovrd_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_FORCE_LOCK2DATA_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_force_lock2ref_ovrd_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_FORCE_LOCK2REF_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_hold_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_hold_timer_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_intf_ovrd_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_INTF_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_intf_ovrd_type_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_INTF_OVRD_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_mod_freeze_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_MOD_FREEZE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_ovrd_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_ppm_detect_freeze_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_PPM_DETECT_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_ppm_detect_freeze_ovrd_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_PPM_DETECT_FREEZE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_ppm_detect_hold_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_PPM_DETECT_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_prop_freeze_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_PROP_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_prop_freeze_ovrd_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_PROP_FREEZE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_rxdata_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_RXDATA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_skip_init_lock2data_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_SKIP_INIT_LOCK2DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxpam_bitorder_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxpam_gray_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXPAM_GRAY_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxpam_locovren_attr == SERDES_IP_LANE_L1_CFG_RXPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxpam_precode_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXPAM_PRECODE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_p5_muxd0_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIV_P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_p5_muxd1_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIV_P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_p5_muxd2_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIV_P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_p5_muxd3_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIV_P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_p5_muxd4_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIV_P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdivclken_muxd0_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIVCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdivclken_muxd1_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIVCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdivclken_muxd2_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIVCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdivclken_muxd3_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIVCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdivclken_muxd4_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIVCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxpcsbist_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXPCSBIST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxpcsbist_locovren_attr == SERDES_IP_LANE_L1_CFG_RXPCSBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxphd_gain_hold_en_attr == SERDES_IP_LANE_L1_CFG_RXPHD_GAIN_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxphd_gain_zero_locovr_attr == SERDES_IP_LANE_L1_CFG_RXPHD_GAIN_ZERO_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxphd_locovren_attr == SERDES_IP_LANE_L1_CFG_RXPHD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxphd_majvote_basegain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxphd_majvote_en_attr == SERDES_IP_LANE_L1_CFG_RXPHD_MAJVOTE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxphd_mute_cntr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxphd_nrz8b10b_pam16b20b_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxphd_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxphd_pam_transition_sel_attr == SERDES_IP_LANE_L1_CFG_RXPHD_PAM_TRANSITION_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxphd_sign_invert_attr == SERDES_IP_LANE_L1_CFG_RXPHD_SIGN_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxpostdiv_wait_for_lock_disable_attr == SERDES_IP_LANE_L1_CFG_RXPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxppm_freq_max_offset_h_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxppm_freq_max_offset_l_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxppm_freq_ref_cnt_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxppm_lockstatus_locovr_attr == SERDES_IP_LANE_L1_CFG_RXPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxppm_lockstatus_synthlcfast_en_attr == SERDES_IP_LANE_L1_CFG_RXPPM_LOCKSTATUS_SYNTHLCFAST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxppm_lockstatus_synthlcmed_en_attr == SERDES_IP_LANE_L1_CFG_RXPPM_LOCKSTATUS_SYNTHLCMED_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxppm_lockstatus_synthlcslow_en_attr == SERDES_IP_LANE_L1_CFG_RXPPM_LOCKSTATUS_SYNTHLCSLOW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxppm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxppm_ppmdriftcount_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxppm_ppmdriftmax_attr == 16'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxppm_status_hold_attr == SERDES_IP_LANE_L1_CFG_RXPPM_STATUS_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxppm_unlock_clear_attr == SERDES_IP_LANE_L1_CFG_RXPPM_UNLOCK_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_fast_muxd0_attr == 16'd666
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_fast_muxd1_attr == 16'd4000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_fast_muxd2_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_fast_muxd3_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_fast_muxd4_attr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_muxd0_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_muxd1_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_muxd2_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_muxd3_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_muxd4_attr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxppmctrl_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXPPMCTRL_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxppmctrl_locovren_attr == SERDES_IP_LANE_L1_CFG_RXPPMCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxppmlockstat_locovren_attr == SERDES_IP_LANE_L1_CFG_RXPPMLOCKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxppmlockstat_sticky_locovr_attr == SERDES_IP_LANE_L1_CFG_RXPPMLOCKSTAT_STICKY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxppmtmr_locovren_attr == SERDES_IP_LANE_L1_CFG_RXPPMTMR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxppmtmr_watchdogtmr_sel_locovr_attr == SERDES_IP_LANE_L1_CFG_RXPPMTMR_WATCHDOGTMR_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_cal_clear_delay_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_clk_chk_disable_attr == SERDES_IP_LANE_L1_CFG_RXRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_clk_delay_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_etr_on_delay_attr == 12'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_locovren_attr == SERDES_IP_LANE_L1_CFG_RXRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxreg_lev_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxreg_toggle_reset_on_rate_change_en_attr == SERDES_IP_LANE_L1_CFG_RXREG_TOGGLE_RESET_ON_RATE_CHANGE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxreg_vreg_bypass_attr == SERDES_IP_LANE_L1_CFG_RXREG_VREG_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_en_b_attr == SERDES_IP_LANE_L1_CFG_RXRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s0q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s0q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s2q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s2q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s2q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s2q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s2q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s2q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s2q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s3q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s3q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s3q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s3q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s3q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s3q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s3q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s3q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s4q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s4q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s5q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_entry2_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_entry4_attr == 13'd78
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_entry5_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_entry6_attr == 13'd1406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s0q2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s0q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s1q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s1q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s1q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s1q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s1q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s1q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s2q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s2q2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s2q3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s2q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s2q5_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s2q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s2q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s3q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s3q1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s3q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s3q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s3q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s3q5_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s3q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s3q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s4q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s4q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s5q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_aetrrx_cdrfbdivcken_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_AETRRX_CDRFBDIVCKEN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_aetrrx_cdrfbdivcken_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_AETRRX_CDRFBDIVCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_aetrrx_cdrmoddivcken_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_AETRRX_CDRMODDIVCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_aetrrx_cdrmoddivcken_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_AETRRX_CDRMODDIVCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_aetrrx_termhiz_en_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_AETRRX_TERMHIZ_EN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_aetrrx_termhiz_en_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_AETRRX_TERMHIZ_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_aetrsynth_pcspostdivclksel_ovr_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_AETRSYNTH_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_aetrsynth_pcspostdivclksel_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_AETRSYNTH_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_adc_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_adc_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_auxcomp_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_AUXCOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_auxcomp_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_AUXCOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_bias_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_bias_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_BIAS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_ctlecomp_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_CTLECOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_ctlecomp_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_CTLECOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_datfbdiv_b_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DATFBDIV_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_datfbdiv_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DATFBDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_dfe_bias_b_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DFE_BIAS_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_dfe_bias_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DFE_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_dfe_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DFE_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_dfe_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DFE_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_dfe_yadj_b_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DFE_YADJ_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_dfe_yadj_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DFE_YADJ_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_duty_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DUTY_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_duty_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DUTY_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_hifreqagc_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_HIFREQAGC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_hifreqagc_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_HIFREQAGC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_ntl_b_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_ntl_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_reg_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_reg_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_vco_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_VCO_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_vco_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_VCO_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_voscreg_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_VOSCREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_voscreg_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_VOSCREG_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_adc_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_adc_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_cdrfbdiv_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_CDRFBDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_cdrfbdiv_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_CDRFBDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_pdet_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_PDET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_pdet_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_PDET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_pfd_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_PFD_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_pfd_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_PFD_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_refdiv_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_refdiv_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_reg_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_reg_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_s2pa_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_S2PA_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_s2pa_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_S2PA_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_s2pb_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_S2PB_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_s2pb_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_S2PB_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_vco_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_VCO_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_vco_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_VCO_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_voscreg_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_VOSCREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_voscreg_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_VOSCREG_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstsynth_postdiv_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTSYNTH_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstsynth_postdiv_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTSYNTH_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_drstrx_dpif_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_DRSTRX_DPIF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_drstrx_dpif_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_DRSTRX_DPIF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_drstrx_ppm_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_DRSTRX_PPM_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_drstrx_ppm_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_DRSTRX_PPM_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_cdrlock2data_locovr_attr == SERDES_IP_LANE_L1_CFG_RXSIGDET_CDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_diglfpsdeten_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_diglfpsdeten_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_diglfpsdeten_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_diglfpsdeten_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_diglfpsdeten_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrancnten_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrancnten_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrancnten_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrancnten_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrancnten_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrancnten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrandeten_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrandeten_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrandeten_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrandeten_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrandeten_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrandeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_eiosdeten_muxd0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_eiosdeten_muxd1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_eiosdeten_muxd2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_eiosdeten_muxd3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_eiosdeten_muxd4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_eiosdeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_enable_attr == SERDES_IP_LANE_L1_CFG_RXSIGDET_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_fastlock_winsize_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_leveldeten_muxd0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_leveldeten_muxd1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_leveldeten_muxd2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_leveldeten_muxd3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_leveldeten_muxd4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_leveldeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_lfpsexit_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_locovren_attr == SERDES_IP_LANE_L1_CFG_RXSIGDET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_ppmdeten_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_ppmdeten_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_ppmdeten_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_ppmdeten_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_ppmdeten_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_ppmdeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_rxeq_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_rxeqen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_rxeqen_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_rxleveldet_debounce_dncount_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_rxleveldet_debounce_flush_en_attr == SERDES_IP_LANE_L1_CFG_RXSIGDET_RXLEVELDET_DEBOUNCE_FLUSH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_rxleveldet_debounce_upcount_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_sigdet_debounce_attr == SERDES_IP_LANE_L1_CFG_RXSIGDET_SIGDET_DEBOUNCE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_tmr_clksel_attr == SERDES_IP_LANE_L1_CFG_RXSIGDET_TMR_CLKSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_toggle_count_en_attr == SERDES_IP_LANE_L1_CFG_RXSIGDET_TOGGLE_COUNT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_toggle_count_pause_attr == SERDES_IP_LANE_L1_CFG_RXSIGDET_TOGGLE_COUNT_PAUSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_toggle_monitor_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdetin_eiosdetectstat_locovr_attr == SERDES_IP_LANE_L1_CFG_RXSIGDETIN_EIOSDETECTSTAT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdetin_locovren_attr == SERDES_IP_LANE_L1_CFG_RXSIGDETIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdetin_ovrcdrlock2data_locovr_attr == SERDES_IP_LANE_L1_CFG_RXSIGDETIN_OVRCDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdetin_ovrencdrlock2data_locovr_attr == SERDES_IP_LANE_L1_CFG_RXSIGDETIN_OVRENCDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdetout_lock2data_noforce_ltr_locovr_attr == SERDES_IP_LANE_L1_CFG_RXSIGDETOUT_LOCK2DATA_NOFORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsigdetout_locovren_attr == SERDES_IP_LANE_L1_CFG_RXSIGDETOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxspare0_attr == 32'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxspare_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsqlchlfps_consec_one_thresh_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsqlchlfps_consec_zero_thresh_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsqlchlfps_cycle_thresh_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsqlchlfps_dat_bitorder_attr == SERDES_IP_LANE_L1_CFG_RXSQLCHLFPS_DAT_BITORDER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsqlchlfps_debounce_type_attr == SERDES_IP_LANE_L1_CFG_RXSQLCHLFPS_DEBOUNCE_TYPE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsqlchlfps_one_run_length_thresh_attr == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsqlchlfps_one_run_length_timeout_attr == 8'd103
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsqlchlfps_zero_run_length_thresh_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsqlchlfps_zero_run_length_timeout_attr == 8'd103
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsynthdiv_slowmed_en_muxd0_attr == SERDES_IP_LANE_L1_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsynthdiv_slowmed_en_muxd1_attr == SERDES_IP_LANE_L1_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsynthdiv_slowmed_en_muxd2_attr == SERDES_IP_LANE_L1_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsynthdiv_slowmed_en_muxd3_attr == SERDES_IP_LANE_L1_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxsynthdiv_slowmed_en_muxd4_attr == SERDES_IP_LANE_L1_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxterm_cal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxterm_coarse_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxterm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXTERM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxterm_modeselect_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxtermhiz_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXTERMHIZ_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxtermhiz_locovren_attr == SERDES_IP_LANE_L1_CFG_RXTERMHIZ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxvoscreg_bypass_vosc_attr == SERDES_IP_LANE_L1_CFG_RXVOSCREG_BYPASS_VOSC_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxvoscregopampoffsetctrl_sel_attr == SERDES_IP_LANE_L1_CFG_RXVOSCREGOPAMPOFFSETCTRL_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxvoscregopampoffseterr_locovren_attr == SERDES_IP_LANE_L1_CFG_RXVOSCREGOPAMPOFFSETERR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxvoscregopampoffseterr_sel_locovr_attr == SERDES_IP_LANE_L1_CFG_RXVOSCREGOPAMPOFFSETERR_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxvoscregvref_locovren_attr == SERDES_IP_LANE_L1_CFG_RXVOSCREGVREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_rxvoscregvref_sel_locovr_attr == SERDES_IP_LANE_L1_CFG_RXVOSCREGVREF_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlch_acqgain_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlch_acqtime_attr == 13'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlch_cal_quiet_locovr_attr == SERDES_IP_LANE_L1_CFG_SQLCH_CAL_QUIET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlch_cal_sel_locovr_attr == SERDES_IP_LANE_L1_CFG_SQLCH_CAL_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlch_calctrl_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlch_calen_locovr_attr == SERDES_IP_LANE_L1_CFG_SQLCH_CALEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlch_caltimer_attr == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlch_clkgate_locovr_attr == SERDES_IP_LANE_L1_CFG_SQLCH_CLKGATE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlch_cmshiften_attr == SERDES_IP_LANE_L1_CFG_SQLCH_CMSHIFTEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_acq_gain_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_acq_pct_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_cal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_clr_errlog_attr == SERDES_IP_LANE_L1_CFG_SQLCH_CONT_CLR_ERRLOG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_controller_mode_attr == SERDES_IP_LANE_L1_CFG_SQLCH_CONT_CONTROLLER_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_dis_attr == SERDES_IP_LANE_L1_CFG_SQLCH_CONT_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_pause_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_postcal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_precal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_quiet_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlch_lfps_en_attr == SERDES_IP_LANE_L1_CFG_SQLCH_LFPS_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlch_locovren_attr == SERDES_IP_LANE_L1_CFG_SQLCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlch_ovrd_val_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlch_pkdet_freqsel_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlch_polarity_attr == SERDES_IP_LANE_L1_CFG_SQLCH_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlch_rdacen_attr == SERDES_IP_LANE_L1_CFG_SQLCH_RDACEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlch_thresh_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlch_time_out_attr == 16'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlch_vrefsel0_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlch_vrefsel1_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlch_vrefsel_ovr_en_attr == SERDES_IP_LANE_L1_CFG_SQLCH_VREFSEL_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlchdeb_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlchdeb_deb_cnt_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlchdeb_deb_status_cnt_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlchdeb_en_attr == SERDES_IP_LANE_L1_CFG_SQLCHDEB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlchdeb_ign_cnt_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlchdeb_sigdet_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlchdeb_thresh_cnt_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlchdebout_exit_good_debounced_locovr_attr == SERDES_IP_LANE_L1_CFG_SQLCHDEBOUT_EXIT_GOOD_DEBOUNCED_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlchdebout_exit_good_debounced_status_locovr_attr == SERDES_IP_LANE_L1_CFG_SQLCHDEBOUT_EXIT_GOOD_DEBOUNCED_STATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlchdebout_exit_good_locovr_attr == SERDES_IP_LANE_L1_CFG_SQLCHDEBOUT_EXIT_GOOD_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_sqlchdebout_locovren_attr == SERDES_IP_LANE_L1_CFG_SQLCHDEBOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_trancnt_off_attr == 10'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_trancnt_on_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_trancntout_det_locovr_attr == SERDES_IP_LANE_L1_CFG_TRANCNTOUT_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_trancntout_locovren_attr == SERDES_IP_LANE_L1_CFG_TRANCNTOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_trandet_ax_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_trandet_ay_attr == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_trandet_off_h_attr == 6'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_trandet_off_l_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_trandet_on_h_attr == 6'd39
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_trandet_on_l_attr == 6'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_trandetout_det_locovr_attr == SERDES_IP_LANE_L1_CFG_TRANDETOUT_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_trandetout_locovren_attr == SERDES_IP_LANE_L1_CFG_TRANDETOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_tx2rxlb_en_attr == SERDES_IP_LANE_L1_CFG_TX2RXLB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_tx2rxlb_init_offset_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_tx_cmn_on_state_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_tx_fastregpwrup_en_attr == SERDES_IP_LANE_L1_CFG_TX_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_tx_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_tx_pg_disable_attr == SERDES_IP_LANE_L1_CFG_TX_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_tx_synth_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_tx_synth_sel_amode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_tx_synth_sel_bmode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_tx_synth_sel_cmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_tx_synth_sel_dmode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_tx_synth_sel_emode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_tx_txdetrx_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txadc_req_attr == SERDES_IP_LANE_L1_CFG_TXADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txaprobe_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txaprobe_lastmux_isolate_attr == SERDES_IP_LANE_L1_CFG_TXAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txaprobeadc_current_direction_attr == SERDES_IP_LANE_L1_CFG_TXAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txaprobeadc_resistor_enable_attr == SERDES_IP_LANE_L1_CFG_TXAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txbdvdr_pma2pcstxworden_attr == SERDES_IP_LANE_L1_CFG_TXBDVDR_PMA2PCSTXWORDEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txbeacon_div_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txbeacon_sel_attr == SERDES_IP_LANE_L1_CFG_TXBEACON_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txbias_icc20uadj_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txbias_icc80uadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txbias_locovren_attr == SERDES_IP_LANE_L1_CFG_TXBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txbias_termcal_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txbist_biterror_en_attr == SERDES_IP_LANE_L1_CFG_TXBIST_BITERROR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txbist_locovren_attr == SERDES_IP_LANE_L1_CFG_TXBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txbist_modesel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txbist_oobmode_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txbist_oobtburst_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txbist_oobtcomrstinit_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txbist_oobtcomsas_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txbist_oobtcomwake_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txbist_seed_attr == 31'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_size_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf00_attr == 32'd1985229328
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf01_attr == 32'd4275878552
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf02_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf03_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf04_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf05_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf06_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf07_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf08_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf09_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txbit_select_muxd0_attr == SERDES_IP_LANE_L1_CFG_TXBIT_SELECT_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txbit_select_muxd1_attr == SERDES_IP_LANE_L1_CFG_TXBIT_SELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txbit_select_muxd2_attr == SERDES_IP_LANE_L1_CFG_TXBIT_SELECT_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txbit_select_muxd3_attr == SERDES_IP_LANE_L1_CFG_TXBIT_SELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txbit_select_muxd4_attr == SERDES_IP_LANE_L1_CFG_TXBIT_SELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txbti_data_replication_attr == SERDES_IP_LANE_L1_CFG_TXBTI_DATA_REPLICATION_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txbti_tx_idle_data_en_attr == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcal_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcal_tclkduty_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalduty_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalduty_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTY_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalduty_sel_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutybg_abort_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutybg_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutybg_ready_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutycomp_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutycomp_offset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_finish_side_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_init_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_initval_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_invert_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_req_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_round_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_runcount_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_signmagen_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsmout_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsmout_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompmeas_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompmeas_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompmeas_req_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompmeasout_ack_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPMEASOUT_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompmeasout_erravg_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPMEASOUT_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompmeasout_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_bg_en_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_bg_one_step_cal_en_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_finish_side_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_init_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_invert_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_req_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_round_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_runcount_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_signmagen_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeas_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeas_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeas_req_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeasout_ack_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYMEASOUT_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeasout_erravg_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYMEASOUT_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeasout_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutystat_done_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaldutystat_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalptr_pstate_duty_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalptr_pstate_dutycomp_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalptr_pstate_regopampoffset_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_duty_muxd0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_duty_muxd1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_duty_muxd2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_duty_muxd3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_duty_muxd4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_dutycomp_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_dutycomp_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_dutycomp_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_dutycomp_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_dutycomp_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_regopampoffset_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffset_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_finish_side_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_round_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_runcount_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_signmagen_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcaltclkdutyforce_div1_attr == SERDES_IP_LANE_L1_CFG_TXCALTCLKDUTYFORCE_DIV1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txcdrdiv_local_en_attr == SERDES_IP_LANE_L1_CFG_TXCDRDIV_LOCAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txclk_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txclk_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txclkgenmuxsel_txinternal_attr == SERDES_IP_LANE_L1_CFG_TXCLKGENMUXSEL_TXINTERNAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txdetectrx_thr_attr == 5'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeas_count_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeas_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXDETECTRXMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeas_locovren_attr == SERDES_IP_LANE_L1_CFG_TXDETECTRXMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeas_validdlycount_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeasin_locovren_attr == SERDES_IP_LANE_L1_CFG_TXDETECTRXMEASIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeasin_start_locovr_attr == SERDES_IP_LANE_L1_CFG_TXDETECTRXMEASIN_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeaspcs_locovren_attr == SERDES_IP_LANE_L1_CFG_TXDETECTRXMEASPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeaspcs_req_locovr_attr == SERDES_IP_LANE_L1_CFG_TXDETECTRXMEASPCS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeasval_locovren_attr == SERDES_IP_LANE_L1_CFG_TXDETECTRXMEASVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeasval_stat_locovr_attr == SERDES_IP_LANE_L1_CFG_TXDETECTRXMEASVAL_STAT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txdetrx_levn_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txdetrx_levnm1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txdetrx_levnp1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txdetrx_levnp2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txdrv_hizen_locovr_attr == SERDES_IP_LANE_L1_CFG_TXDRV_HIZEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txdrv_levn_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txdrv_levnm1_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txdrv_levnp1_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txdrv_levnp2_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txdrv_locovren_attr == SERDES_IP_LANE_L1_CFG_TXDRV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txdrv_refcken_attr == SERDES_IP_LANE_L1_CFG_TXDRV_REFCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txdrv_termref_attr == SERDES_IP_LANE_L1_CFG_TXDRV_TERMREF_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txdrvmute_locovr_attr == SERDES_IP_LANE_L1_CFG_TXDRVMUTE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txdrvmute_locovren_attr == SERDES_IP_LANE_L1_CFG_TXDRVMUTE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txduty_ctrl_disable_attr == SERDES_IP_LANE_L1_CFG_TXDUTY_CTRL_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txduty_pad_sense_en_attr == SERDES_IP_LANE_L1_CFG_TXDUTY_PAD_SENSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txdutycal_div16_en_attr == SERDES_IP_LANE_L1_CFG_TXDUTYCAL_DIV16_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txdutycal_div1_en_attr == SERDES_IP_LANE_L1_CFG_TXDUTYCAL_DIV1_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txdutycal_div2_en_attr == SERDES_IP_LANE_L1_CFG_TXDUTYCAL_DIV2_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txdutycal_div4_en_attr == SERDES_IP_LANE_L1_CFG_TXDUTYCAL_DIV4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txdutycal_div8_en_attr == SERDES_IP_LANE_L1_CFG_TXDUTYCAL_DIV8_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txfifo_elecidle_deskew_en_attr == SERDES_IP_LANE_L1_CFG_TXFIFO_ELECIDLE_DESKEW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txfifo_force_txidlebit1_zero_disable_attr == SERDES_IP_LANE_L1_CFG_TXFIFO_FORCE_TXIDLEBIT1_ZERO_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txfifo_kill_dly_10b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txfifo_kill_dly_16b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txfifo_kill_dly_20b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txfifo_kill_dly_32b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txfifo_kill_dly_40b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txfifo_kill_dly_64b_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txfifo_kill_dly_80b_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txfifo_kill_dly_8b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txfifo_kill_en_attr == SERDES_IP_LANE_L1_CFG_TXFIFO_KILL_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txfsm_cken_ovr_attr == SERDES_IP_LANE_L1_CFG_TXFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txfsm_cken_ovren_attr == SERDES_IP_LANE_L1_CFG_TXFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txfsm_main_on_state_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txl1d1_doze_ctrl_attr == SERDES_IP_LANE_L1_CFG_TXL1D1_DOZE_CTRL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txl1d1_txbias_ctrl_attr == SERDES_IP_LANE_L1_CFG_TXL1D1_TXBIAS_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txlanepam_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXLANEPAM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txlanepam_locovren_attr == SERDES_IP_LANE_L1_CFG_TXLANEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txmeaslatovrhd_meas_sel_attr == SERDES_IP_LANE_L1_CFG_TXMEASLATOVRHD_MEAS_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txmute_delay_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txntl_changeref_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txntl_changeref_val_locovr_attr == SERDES_IP_LANE_L1_CFG_TXNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txntl_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txntl_en_attr == SERDES_IP_LANE_L1_CFG_TXNTL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txntl_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txntl_locovren_attr == SERDES_IP_LANE_L1_CFG_TXNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txntl_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txntl_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txntl_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txntl_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txntl_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txntl_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txntl_txm_charge_up_locovr_attr == SERDES_IP_LANE_L1_CFG_TXNTL_TXM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txntl_txm_pull_dn_locovr_attr == SERDES_IP_LANE_L1_CFG_TXNTL_TXM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txntl_txm_sense_locovr_attr == SERDES_IP_LANE_L1_CFG_TXNTL_TXM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txntl_txp_charge_up_locovr_attr == SERDES_IP_LANE_L1_CFG_TXNTL_TXP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txntl_txp_pull_dn_locovr_attr == SERDES_IP_LANE_L1_CFG_TXNTL_TXP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txntl_txp_sense_locovr_attr == SERDES_IP_LANE_L1_CFG_TXNTL_TXP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txp2s_txwordsyncbypen_attr == SERDES_IP_LANE_L1_CFG_TXP2S_TXWORDSYNCBYPEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txpam_bitorder_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txpam_gray_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXPAM_GRAY_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txpam_locovren_attr == SERDES_IP_LANE_L1_CFG_TXPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txpam_precode_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXPAM_PRECODE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txpcs_locovren_attr == SERDES_IP_LANE_L1_CFG_TXPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txpcs_txenable_locovr_attr == SERDES_IP_LANE_L1_CFG_TXPCS_TXENABLE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txpcsbist_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXPCSBIST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txpcsbist_locovren_attr == SERDES_IP_LANE_L1_CFG_TXPCSBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txratewidth_clk_chk_disable_attr == SERDES_IP_LANE_L1_CFG_TXRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txratewidth_etr_on_delay_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txratewidth_locovren_attr == SERDES_IP_LANE_L1_CFG_TXRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txreg_toggle_pwrupacc_on_rate_change_en_attr == SERDES_IP_LANE_L1_CFG_TXREG_TOGGLE_PWRUPACC_ON_RATE_CHANGE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txreg_toggle_reset_on_rate_change_en_attr == SERDES_IP_LANE_L1_CFG_TXREG_TOGGLE_RESET_ON_RATE_CHANGE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txresetdel_sel_attr == SERDES_IP_LANE_L1_CFG_TXRESETDEL_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_en_b_attr == SERDES_IP_LANE_L1_CFG_TXRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s0q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s0q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s1q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s1q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s2q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s2q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s2q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s2q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s2q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s2q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s2q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s3q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s3q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s3q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s3q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s3q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s3q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s3q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s3q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s4q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s4q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s5q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_entry2_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s0q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s0q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s1q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s1q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s1q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s1q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s1q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s1q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s2q0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s2q1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s2q2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s2q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s2q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s2q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s2q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s2q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s3q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s3q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s3q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s3q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s3q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s3q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s3q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s3q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s4q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s4q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s5q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_dn_ptr0_s_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_up_ptr0_s_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_aetrtx_bitckdvdrcken_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_AETRTX_BITCKDVDRCKEN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_aetrtx_bitckdvdrcken_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_AETRTX_BITCKDVDRCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_aetrtx_regpwrupacc_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_AETRTX_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_aetrtx_regpwrupacc_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_AETRTX_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_adc_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_adc_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_drvdoze_b_ovr_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_DRVDOZE_B_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_drvdoze_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_DRVDOZE_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_duty_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_DUTY_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_duty_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_DUTY_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_ntl_b_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_ntl_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_p2s_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_P2S_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_p2s_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_P2S_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_reg_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_reg_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_arsttx_adc_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_ARSTTX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_arsttx_adc_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_ARSTTX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_arsttx_pma2pcstxword_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_ARSTTX_PMA2PCSTXWORD_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_arsttx_pma2pcstxword_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_ARSTTX_PMA2PCSTXWORD_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_arsttx_regreset_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_ARSTTX_REGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_arsttx_regreset_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_ARSTTX_REGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_arsttx_txdetectrx_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_ARSTTX_TXDETECTRX_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_arsttx_txdetectrx_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_ARSTTX_TXDETECTRX_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txrststate_hiz_en_attr == SERDES_IP_LANE_L1_CFG_TXRSTSTATE_HIZ_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txspare0_attr == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txspare_attr == 10'd384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txterm_coarse_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txtermtrim_locovren_attr == SERDES_IP_LANE_L1_CFG_TXTERMTRIM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txtermtrim_nmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txtermtrim_pmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txwclk_div_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txwclk_div_en_attr == SERDES_IP_LANE_L1_CFG_TXWCLK_DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txwclk_div_smpl_attr == SERDES_IP_LANE_L1_CFG_TXWCLK_DIV_SMPL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txwptr_init01_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txwptr_init02_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txwptr_init04_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txwptr_init08_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txwptr_init16_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txwptr_init32_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l1_cfg_txwptr_init_rx2txparlb_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_bshihyst_attr == SERDES_IP_LANE_L2_CFG_BSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_bstxdrv_levn_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_bstxdrv_levnm1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_bstxdrv_levnp1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_bstxdrv_levnp2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_calsqlchosc_locovren_attr == SERDES_IP_LANE_L2_CFG_CALSQLCHOSC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_calsqlchosc_trimcode_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_cdrclkstat_locovren_attr == SERDES_IP_LANE_L2_CFG_CDRCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_cdrclkstat_ready_locovr_attr == SERDES_IP_LANE_L2_CFG_CDRCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_etrregrxcdrclk_ready_attr == SERDES_IP_LANE_L2_CFG_ETRREGRXCDRCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_laneckm_avg_en_attr == SERDES_IP_LANE_L2_CFG_LANECKM_AVG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_laneckm_clk_en_attr == SERDES_IP_LANE_L2_CFG_LANECKM_CLK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_laneckm_continuous_attr == SERDES_IP_LANE_L2_CFG_LANECKM_CONTINUOUS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_laneckm_dig_meas_en_attr == SERDES_IP_LANE_L2_CFG_LANECKM_DIG_MEAS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_laneckm_dig_meas_err_clr_attr == SERDES_IP_LANE_L2_CFG_LANECKM_DIG_MEAS_ERR_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_laneckm_en_attr == SERDES_IP_LANE_L2_CFG_LANECKM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_laneckm_max_thr_attr == 25'd33554431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_laneckm_meas_ck_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_laneckm_ref_ck_div_ratio_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_laneckm_result_clr_attr == SERDES_IP_LANE_L2_CFG_LANECKM_RESULT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_laneckm_start_attr == SERDES_IP_LANE_L2_CFG_LANECKM_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_laneckm_wdt_interval_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_laneckm_win_thr_ref_attr == 25'd16777215
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_lanepcs_locovren_attr == SERDES_IP_LANE_L2_CFG_LANEPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_lanepcs_mode_locovr_attr == SERDES_IP_LANE_L2_CFG_LANEPCS_MODE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_laneperfmon_compare_val_start_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_laneperfmon_compare_val_stop_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_laneperfmon_en_attr == SERDES_IP_LANE_L2_CFG_LANEPERFMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_laneperfmon_mask_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_lanepmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_lanepmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_lanepmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_lanepmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_lanepmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_lanepmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_lb_cdrclk2txen_locovr_attr == SERDES_IP_LANE_L2_CFG_LB_CDRCLK2TXEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_lb_cdrclkdiven_attr == SERDES_IP_LANE_L2_CFG_LB_CDRCLKDIVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_lb_cdrdivclk2exten_attr == SERDES_IP_LANE_L2_CFG_LB_CDRDIVCLK2EXTEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_lb_cdrdivclk2txen_attr == SERDES_IP_LANE_L2_CFG_LB_CDRDIVCLK2TXEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_lb_hsclk2cdrdiven_attr == SERDES_IP_LANE_L2_CFG_LB_HSCLK2CDRDIVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_lb_locovren_attr == SERDES_IP_LANE_L2_CFG_LB_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_lb_parrx2txtimeden_locovr_attr == SERDES_IP_LANE_L2_CFG_LB_PARRX2TXTIMEDEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_lb_pllfbclk2cdrrefclken_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_lb_pllfbclk2cdrrefclken_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_lb_pllfbclk2cdrrefclken_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_lb_pllfbclk2cdrrefclken_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_lb_pllfbclk2cdrrefclken_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_lb_rx2txuntimeden_attr == SERDES_IP_LANE_L2_CFG_LB_RX2TXUNTIMEDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_lb_rxwordck2pcstxwordcken_attr == SERDES_IP_LANE_L2_CFG_LB_RXWORDCK2PCSTXWORDCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_lb_tx2rxbuftimeden_lsb_locovr_attr == SERDES_IP_LANE_L2_CFG_LB_TX2RXBUFTIMEDEN_LSB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_lb_tx2rxbuftimeden_msb_locovr_attr == SERDES_IP_LANE_L2_CFG_LB_TX2RXBUFTIMEDEN_MSB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_lb_tx2rxiotimeden_attr == SERDES_IP_LANE_L2_CFG_LB_TX2RXIOTIMEDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_lfps_det_locovr_attr == SERDES_IP_LANE_L2_CFG_LFPS_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_lfps_locovren_attr == SERDES_IP_LANE_L2_CFG_LFPS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_lfps_out_en_attr == SERDES_IP_LANE_L2_CFG_LFPS_OUT_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_pcslfps_en_locovr_attr == SERDES_IP_LANE_L2_CFG_PCSLFPS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_pcslfps_locovren_attr == SERDES_IP_LANE_L2_CFG_PCSLFPS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_pcsrx_dme_en_locovr_attr == SERDES_IP_LANE_L2_CFG_PCSRX_DME_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_pcsrx_locovren_attr == SERDES_IP_LANE_L2_CFG_PCSRX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_pcsrxbist_locovren_attr == SERDES_IP_LANE_L2_CFG_PCSRXBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_pcsrxbist_modesel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_pcstx_beaconen_locovr_attr == SERDES_IP_LANE_L2_CFG_PCSTX_BEACONEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_pcstx_locovren_attr == SERDES_IP_LANE_L2_CFG_PCSTX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_polarity_rx_attr == SERDES_IP_LANE_L2_CFG_POLARITY_RX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_polarity_tx_attr == SERDES_IP_LANE_L2_CFG_POLARITY_TX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rx_cmn_on_state_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rx_fastregpwrup_en_attr == SERDES_IP_LANE_L2_CFG_RX_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rx_frac_mode_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rx_on_state_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rx_pg_disable_attr == SERDES_IP_LANE_L2_CFG_RX_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rx_synth_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rx_synth_sel_amode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rx_synth_sel_bmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rx_synth_sel_cmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rx_synth_sel_dmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rx_synth_sel_emode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxadc_req_attr == SERDES_IP_LANE_L2_CFG_RXADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxagc_dccoupleen_attr == SERDES_IP_LANE_L2_CFG_RXAGC_DCCOUPLEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxaprobe_addr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxaprobe_lastmux_isolate_attr == SERDES_IP_LANE_L2_CFG_RXAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxaprobeadc_current_direction_attr == SERDES_IP_LANE_L2_CFG_RXAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxaprobeadc_resistor_enable_attr == SERDES_IP_LANE_L2_CFG_RXAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxbias_iccadj_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxbias_icvadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxbias_locovren_attr == SERDES_IP_LANE_L2_CFG_RXBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxbias_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxbist_burst_four_errtype_attr == SERDES_IP_LANE_L2_CFG_RXBIST_BURST_FOUR_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxbist_burst_one_errtype_attr == SERDES_IP_LANE_L2_CFG_RXBIST_BURST_ONE_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxbist_burst_three_errtype_attr == SERDES_IP_LANE_L2_CFG_RXBIST_BURST_THREE_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxbist_burst_two_errtype_attr == SERDES_IP_LANE_L2_CFG_RXBIST_BURST_TWO_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxbist_cdrlock2data_bypass_attr == SERDES_IP_LANE_L2_CFG_RXBIST_CDRLOCK2DATA_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxbist_cdrlock2data_postamble_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxbist_clear_errcount_attr == SERDES_IP_LANE_L2_CFG_RXBIST_CLEAR_ERRCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxbist_err_en_attr == SERDES_IP_LANE_L2_CFG_RXBIST_ERR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxbist_err_trig_type_attr == SERDES_IP_LANE_L2_CFG_RXBIST_ERR_TRIG_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxbist_errmask_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxbist_errtype_attr == SERDES_IP_LANE_L2_CFG_RXBIST_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxbist_firsterr_type_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxbist_lockchk_count_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxbist_maxbitcnt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxbist_mostrecent_err_attr == SERDES_IP_LANE_L2_CFG_RXBIST_MOSTRECENT_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxbist_relock_itercount_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxbist_seed_attr == 31'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxbist_status_hold_attr == SERDES_IP_LANE_L2_CFG_RXBIST_STATUS_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxbitslip_locovr_attr == SERDES_IP_LANE_L2_CFG_RXBITSLIP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxbitslip_locovren_attr == SERDES_IP_LANE_L2_CFG_RXBITSLIP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxbscan_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxbshicm_attr == SERDES_IP_LANE_L2_CFG_RXBSHICM_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalcdrfbdiv_div2_bypass_muxd0_attr == SERDES_IP_LANE_L2_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalcdrfbdiv_div2_bypass_muxd1_attr == SERDES_IP_LANE_L2_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalcdrfbdiv_div2_bypass_muxd2_attr == SERDES_IP_LANE_L2_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalcdrfbdiv_div2_bypass_muxd3_attr == SERDES_IP_LANE_L2_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalcdrfbdiv_div2_bypass_muxd4_attr == SERDES_IP_LANE_L2_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalduty_iclk_gray_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalduty_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTY_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalduty_qclk_gray_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalduty_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutybg_abort_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutybg_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutybg_ready_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycomp_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycomp_offset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_finish_side_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_init_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_initval_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_invert_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_round_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_runcount_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_signmagen_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsmout_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsmout_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_disable_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCTRL_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_i_div1_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_i_div2_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_i_div4_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_i_div8_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_q_div1_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_q_div2_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_q_div4_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_q_div8_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_bg_en_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_bg_one_step_cal_en_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_finish_side_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_i_polarity_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_I_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_i_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_I_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_init_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_q_polarity_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_Q_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_q_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_Q_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_round_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_runcount_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_signmagen_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_comp_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEAS_COMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_comp_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEAS_COMP_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_i_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEAS_I_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_i_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEAS_I_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_q_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEAS_Q_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_q_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEAS_Q_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeasout_comp_ack_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEASOUT_COMP_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeasout_comp_erravg_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEASOUT_COMP_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeasout_i_ack_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEASOUT_I_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeasout_i_erravg_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEASOUT_I_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeasout_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeasout_q_ack_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEASOUT_Q_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeasout_q_erravg_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEASOUT_Q_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutystat_done_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaldutystat_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_centerfreq_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_end_delay_attr == 9'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_hscount_muxd0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_hscount_muxd1_attr == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_hscount_muxd2_attr == 8'd180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_hscount_muxd3_attr == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_hscount_muxd4_attr == 8'd206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_initval_centerfreq_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_initval_fosc_attr == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_centerfreq_finish_side_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_CENTERFREQ_FINISH_SIDE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_centerfreq_to_fosc_offset_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_centerfreqen_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_CENTERFREQEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_centerfreqoffset_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_fosc_finishside_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_FOSC_FINISHSIDE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_foscen_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_FOSCEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_foscoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_init_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_invert_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_lpfax_calfosccoarse_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_lpfax_calfoscfine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_lpfax_centerfreqcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_lpfax_centerfreqfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_runcount_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_signmagen_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_vcorepen_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_VCOREPEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsmout_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsmout_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_count_muxd0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_count_muxd1_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_count_muxd2_attr == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_count_muxd3_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_count_muxd4_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_dlycount_attr == 9'd68
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeasout_clear_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCMEASOUT_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeasout_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeasout_start_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCMEASOUT_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscval_int_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscval_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalintsval_int_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalintsval_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALINTSVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaloffsetfsm_init_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaloffsetfsm_init_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaloffsetfsm_init_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALOFFSETFSM_INIT_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaloffsetfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcaloffsetfsmout_input_en_attr == SERDES_IP_LANE_L2_CFG_RXCALOFFSETFSMOUT_INPUT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_duty_i_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_duty_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_dutycomp_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_foscfsm_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_offsetfsm_init_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_regopampoffset_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_rxppm_lockstatus_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_sqlch_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_sqlchosc_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_synthppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_voscregopampoffset_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_duty_i_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_duty_q_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_dutycomp_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_foscfsm_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_offsetfsm_init_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_rxppm_lockstatus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_sqlch_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_sqlchosc_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_synthppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_voscregopampoffset_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffset_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_finish_side_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_round_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_runcount_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_signmagen_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchfsm_clear_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchfsm_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchfsmout_caldone_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHFSMOUT_CALDONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchfsmout_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_codeoffset_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_finish_side_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHOSCFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_init_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHOSCFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_initval_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_invert_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHOSCFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHOSCFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHOSCFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_round_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHOSCFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_runcount_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHOSCFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscmeas_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHOSCMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscmeas_ref_cnt_attr == 10'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscmeas_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHOSCMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscmeas_settle_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscmeas_smpl_cnt_attr == 10'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvbiascap_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALVBIASCAP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvbiascap_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALVBIASCAP_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvcoopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvcoopampoffsetmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvcoopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvcoopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffset_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffset_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_codeoffset_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_finish_side_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_initval_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_invert_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_lpfaxcoarse_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_round_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_runcount_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETFSM_RUNCOUNT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_signmagen_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsmout_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsmout_runcount_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETFSMOUT_RUNCOUNT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetmeas_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffset_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALVOSCREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALVOSCREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L2_CFG_RXCALVOSCREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALVOSCREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALVOSCREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALVOSCREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALVOSCREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALVOSCREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALVOSCREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrdiv_local_en_attr == SERDES_IP_LANE_L2_CFG_RXCDRDIV_LOCAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdiv_moddiv_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdiv_moddiv_muxd1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdiv_moddiv_muxd2_attr == 4'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdiv_moddiv_muxd3_attr == 4'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdiv_moddiv_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdivslip_mdiv_muxd0_attr == 9'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdivslip_mdiv_muxd1_attr == 9'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdivslip_mdiv_muxd2_attr == 9'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdivslip_mdiv_muxd3_attr == 9'd66
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdivslip_mdiv_muxd4_attr == 9'd210
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrpfd_forcedn_attr == SERDES_IP_LANE_L2_CFG_RXCDRPFD_FORCEDN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrpfd_forceen_attr == SERDES_IP_LANE_L2_CFG_RXCDRPFD_FORCEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrpfd_forceup_attr == SERDES_IP_LANE_L2_CFG_RXCDRPFD_FORCEUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrpfd_propgain_attr == SERDES_IP_LANE_L2_CFG_RXCDRPFD_PROPGAIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrpfd_pulsewidth_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrphd_asym_override_ignore_attr == SERDES_IP_LANE_L2_CFG_RXCDRPHD_ASYM_OVERRIDE_IGNORE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrphd_bitshift_en_attr == SERDES_IP_LANE_L2_CFG_RXCDRPHD_BITSHIFT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrphd_forcedn_attr == SERDES_IP_LANE_L2_CFG_RXCDRPHD_FORCEDN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrphd_forceen_attr == SERDES_IP_LANE_L2_CFG_RXCDRPHD_FORCEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrphd_forceup_attr == SERDES_IP_LANE_L2_CFG_RXCDRPHD_FORCEUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrphdrate_doublerate2s2p_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCDRPHDRATE_DOUBLERATE2S2P_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrphdrate_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCDRPHDRATE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrrefck_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrrefck_refdiv_muxd1_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrrefck_refdiv_muxd2_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrrefck_refdiv_muxd3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrrefck_refdiv_muxd4_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_biastop_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_biastopbypass_attr == SERDES_IP_LANE_L2_CFG_RXCDRVCO_BIASTOPBYPASS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_datapropgain_high_attr == 5'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_datapropgain_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_datapropgain_low_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_ff_ovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_ff_ovr_en_attr == SERDES_IP_LANE_L2_CFG_RXCDRVCO_FF_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_fil_short_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_flickerdegen_attr == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_gmfoscshort_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCDRVCO_GMFOSCSHORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_intf_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_intf_fil_short_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_intrj_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCDRVCO_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_refpropgain_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_refpropgain_nom_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxclk_cdrfb_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCLK_CDRFB_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxclk_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxclk_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdat_nrz_64b80b_bcword_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdata_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXDATA_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdata_locovren_attr == SERDES_IP_LANE_L2_CFG_RXDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdatapath_locovren_attr == SERDES_IP_LANE_L2_CFG_RXDATAPATH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdatapath_on_state_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdatapath_ready_locovr_attr == SERDES_IP_LANE_L2_CFG_RXDATAPATH_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdfe_datatap_vcasc_attr == 4'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdfe_dfebiasadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdfe_nbiasctle_en_attr == SERDES_IP_LANE_L2_CFG_RXDFE_NBIASCTLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdfe_vcasc_sel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdfeterm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXDFETERM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdfeterm_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdfeyadjdac_datamid_edge_coarse_en_attr == SERDES_IP_LANE_L2_CFG_RXDFEYADJDAC_DATAMID_EDGE_COARSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdfeyadjdac_datatopbot_aux_coarse_en_attr == SERDES_IP_LANE_L2_CFG_RXDFEYADJDAC_DATATOPBOT_AUX_COARSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_accum_mon_en_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_ACCUM_MON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_accum_mon_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_bypasscdrpdetupdnsmpl_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_bypassenfosc_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_BYPASSENFOSC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_bypassenints_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_BYPASSENINTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_bypassenupdnsmpl_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_BYPASSENUPDNSMPL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_bypassfosc_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_bypasspllpfdupdnsmpl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_bypassrxints_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_data2pll_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_deltasigmode_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_DELTASIGMODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_fastref_muxd0_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_FASTREF_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_fastref_muxd1_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_FASTREF_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_fastref_muxd2_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_FASTREF_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_fastref_muxd3_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_FASTREF_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_fastref_muxd4_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_FASTREF_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_fosc_mod_bypass_en_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_FOSC_MOD_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_fosc_sample_pedge_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_FOSC_SAMPLE_PEDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gain_step_on_lock_recovery_en_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_GAIN_STEP_ON_LOCK_RECOVERY_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gaindelaycount_init_attr == 9'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gaindelaycount_pow2_muxd0_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gaindelaycount_pow2_muxd1_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gaindelaycount_pow2_muxd2_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gaindelaycount_pow2_muxd3_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gaindelaycount_pow2_muxd4_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2ref_pow2_muxd0_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2ref_pow2_muxd1_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2ref_pow2_muxd2_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2ref_pow2_muxd3_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2ref_pow2_muxd4_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainunlocked_pow2_muxd0_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainunlocked_pow2_muxd1_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainunlocked_pow2_muxd2_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainunlocked_pow2_muxd3_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainunlocked_pow2_muxd4_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_initintegrator_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_INITINTEGRATOR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_initmodulator_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_INITMODULATOR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_deltasig_mode_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_INTS_DELTASIG_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_freeze_en_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_INTS_FREEZE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gaindelaycount_pow2_muxd0_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gaindelaycount_pow2_muxd1_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gaindelaycount_pow2_muxd2_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gaindelaycount_pow2_muxd3_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gaindelaycount_pow2_muxd4_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd0_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd1_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd2_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd3_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd4_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd0_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd1_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd2_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd3_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd4_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainunlocked_pow2_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainunlocked_pow2_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainunlocked_pow2_muxd2_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainunlocked_pow2_muxd3_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainunlocked_pow2_muxd4_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_guardband_hi_attr == 8'd200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_guardband_lo_attr == 8'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_loop_sel_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_INTS_LOOP_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_mod_bypass_en_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_INTS_MOD_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_mod_load_pedge_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_INTS_MOD_LOAD_PEDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_step_to_integer_en_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_INTS_STEP_TO_INTEGER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_jit_length_attr == 18'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_jit_mode_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_JIT_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_modck_ctrl_en_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_MODCK_CTRL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_pll2data_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_restore_cntr_attr == 9'd258
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_store_cntr_attr == 16'd258
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpif_trnsfrdelay_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpiffreeze_inten_attr == SERDES_IP_LANE_L2_CFG_RXDPIFFREEZE_INTEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdpiffreeze_moden_attr == SERDES_IP_LANE_L2_CFG_RXDPIFFREEZE_MODEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxdutyselpolarity_attr == SERDES_IP_LANE_L2_CFG_RXDUTYSELPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxflxgate_force_rxeq_gate_locovr_attr == SERDES_IP_LANE_L2_CFG_RXFLXGATE_FORCE_RXEQ_GATE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxflxgate_locovren_attr == SERDES_IP_LANE_L2_CFG_RXFLXGATE_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxfoscstat_done_locovr_attr == SERDES_IP_LANE_L2_CFG_RXFOSCSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxfoscstat_locovren_attr == SERDES_IP_LANE_L2_CFG_RXFOSCSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxfsm_cken_ovr_attr == SERDES_IP_LANE_L2_CFG_RXFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxfsm_cken_ovren_attr == SERDES_IP_LANE_L2_CFG_RXFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxints_prev_votes_hold_en_attr == SERDES_IP_LANE_L2_CFG_RXINTS_PREV_VOTES_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxlanepam_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXLANEPAM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxlanepam_locovren_attr == SERDES_IP_LANE_L2_CFG_RXLANEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxlock2datatmr_attr == 8'd240
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxlock2datatmr_short_attr == 8'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxntl_changeref_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxntl_changeref_val_locovr_attr == SERDES_IP_LANE_L2_CFG_RXNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxntl_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxntl_en_attr == SERDES_IP_LANE_L2_CFG_RXNTL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxntl_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxntl_locovren_attr == SERDES_IP_LANE_L2_CFG_RXNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxntl_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxntl_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxntl_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxntl_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxntl_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxntl_rxm_charge_up_locovr_attr == SERDES_IP_LANE_L2_CFG_RXNTL_RXM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxntl_rxm_pull_dn_locovr_attr == SERDES_IP_LANE_L2_CFG_RXNTL_RXM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxntl_rxm_sense_locovr_attr == SERDES_IP_LANE_L2_CFG_RXNTL_RXM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxntl_rxp_charge_up_locovr_attr == SERDES_IP_LANE_L2_CFG_RXNTL_RXP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxntl_rxp_pull_dn_locovr_attr == SERDES_IP_LANE_L2_CFG_RXNTL_RXP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxntl_rxp_sense_locovr_attr == SERDES_IP_LANE_L2_CFG_RXNTL_RXP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxntl_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_acc_freeze_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_ACC_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_cdrlock2data_gater_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_cdrlock2data_gater_hold_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_cdrlock2data_gater_ovrd_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_cdrlock2datatmr_optcl_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_cdrlock2datatmr_optcl_sel_ovrd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_enter_lock2data_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_ENTER_LOCK2DATA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_enter_lock2data_hold_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_ENTER_LOCK2DATA_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_exit_lock2data_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_EXIT_LOCK2DATA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_exit_lock2data_hold_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_EXIT_LOCK2DATA_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_force_lock2data_ovrd_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_FORCE_LOCK2DATA_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_force_lock2ref_ovrd_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_FORCE_LOCK2REF_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_hold_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_hold_timer_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_intf_ovrd_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_INTF_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_intf_ovrd_type_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_INTF_OVRD_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_mod_freeze_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_MOD_FREEZE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_ovrd_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_ppm_detect_freeze_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_PPM_DETECT_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_ppm_detect_freeze_ovrd_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_PPM_DETECT_FREEZE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_ppm_detect_hold_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_PPM_DETECT_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_prop_freeze_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_PROP_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_prop_freeze_ovrd_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_PROP_FREEZE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_rxdata_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_RXDATA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_skip_init_lock2data_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_SKIP_INIT_LOCK2DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxpam_bitorder_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxpam_gray_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXPAM_GRAY_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxpam_locovren_attr == SERDES_IP_LANE_L2_CFG_RXPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxpam_precode_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXPAM_PRECODE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_p5_muxd0_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIV_P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_p5_muxd1_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIV_P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_p5_muxd2_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIV_P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_p5_muxd3_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIV_P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_p5_muxd4_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIV_P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdivclken_muxd0_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIVCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdivclken_muxd1_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIVCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdivclken_muxd2_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIVCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdivclken_muxd3_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIVCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdivclken_muxd4_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIVCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxpcsbist_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXPCSBIST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxpcsbist_locovren_attr == SERDES_IP_LANE_L2_CFG_RXPCSBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxphd_gain_hold_en_attr == SERDES_IP_LANE_L2_CFG_RXPHD_GAIN_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxphd_gain_zero_locovr_attr == SERDES_IP_LANE_L2_CFG_RXPHD_GAIN_ZERO_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxphd_locovren_attr == SERDES_IP_LANE_L2_CFG_RXPHD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxphd_majvote_basegain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxphd_majvote_en_attr == SERDES_IP_LANE_L2_CFG_RXPHD_MAJVOTE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxphd_mute_cntr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxphd_nrz8b10b_pam16b20b_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxphd_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxphd_pam_transition_sel_attr == SERDES_IP_LANE_L2_CFG_RXPHD_PAM_TRANSITION_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxphd_sign_invert_attr == SERDES_IP_LANE_L2_CFG_RXPHD_SIGN_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxpostdiv_wait_for_lock_disable_attr == SERDES_IP_LANE_L2_CFG_RXPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxppm_freq_max_offset_h_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxppm_freq_max_offset_l_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxppm_freq_ref_cnt_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxppm_lockstatus_locovr_attr == SERDES_IP_LANE_L2_CFG_RXPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxppm_lockstatus_synthlcfast_en_attr == SERDES_IP_LANE_L2_CFG_RXPPM_LOCKSTATUS_SYNTHLCFAST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxppm_lockstatus_synthlcmed_en_attr == SERDES_IP_LANE_L2_CFG_RXPPM_LOCKSTATUS_SYNTHLCMED_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxppm_lockstatus_synthlcslow_en_attr == SERDES_IP_LANE_L2_CFG_RXPPM_LOCKSTATUS_SYNTHLCSLOW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxppm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxppm_ppmdriftcount_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxppm_ppmdriftmax_attr == 16'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxppm_status_hold_attr == SERDES_IP_LANE_L2_CFG_RXPPM_STATUS_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxppm_unlock_clear_attr == SERDES_IP_LANE_L2_CFG_RXPPM_UNLOCK_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_fast_muxd0_attr == 16'd666
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_fast_muxd1_attr == 16'd4000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_fast_muxd2_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_fast_muxd3_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_fast_muxd4_attr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_muxd0_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_muxd1_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_muxd2_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_muxd3_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_muxd4_attr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxppmctrl_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXPPMCTRL_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxppmctrl_locovren_attr == SERDES_IP_LANE_L2_CFG_RXPPMCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxppmlockstat_locovren_attr == SERDES_IP_LANE_L2_CFG_RXPPMLOCKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxppmlockstat_sticky_locovr_attr == SERDES_IP_LANE_L2_CFG_RXPPMLOCKSTAT_STICKY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxppmtmr_locovren_attr == SERDES_IP_LANE_L2_CFG_RXPPMTMR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxppmtmr_watchdogtmr_sel_locovr_attr == SERDES_IP_LANE_L2_CFG_RXPPMTMR_WATCHDOGTMR_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_cal_clear_delay_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_clk_chk_disable_attr == SERDES_IP_LANE_L2_CFG_RXRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_clk_delay_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_etr_on_delay_attr == 12'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_locovren_attr == SERDES_IP_LANE_L2_CFG_RXRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxreg_lev_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxreg_toggle_reset_on_rate_change_en_attr == SERDES_IP_LANE_L2_CFG_RXREG_TOGGLE_RESET_ON_RATE_CHANGE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxreg_vreg_bypass_attr == SERDES_IP_LANE_L2_CFG_RXREG_VREG_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_en_b_attr == SERDES_IP_LANE_L2_CFG_RXRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s0q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s0q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s2q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s2q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s2q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s2q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s2q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s2q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s2q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s3q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s3q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s3q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s3q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s3q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s3q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s3q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s3q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s4q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s4q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s5q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_entry2_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_entry4_attr == 13'd78
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_entry5_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_entry6_attr == 13'd1406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s0q2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s0q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s1q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s1q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s1q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s1q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s1q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s1q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s2q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s2q2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s2q3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s2q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s2q5_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s2q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s2q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s3q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s3q1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s3q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s3q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s3q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s3q5_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s3q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s3q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s4q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s4q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s5q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_aetrrx_cdrfbdivcken_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_AETRRX_CDRFBDIVCKEN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_aetrrx_cdrfbdivcken_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_AETRRX_CDRFBDIVCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_aetrrx_cdrmoddivcken_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_AETRRX_CDRMODDIVCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_aetrrx_cdrmoddivcken_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_AETRRX_CDRMODDIVCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_aetrrx_termhiz_en_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_AETRRX_TERMHIZ_EN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_aetrrx_termhiz_en_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_AETRRX_TERMHIZ_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_aetrsynth_pcspostdivclksel_ovr_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_AETRSYNTH_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_aetrsynth_pcspostdivclksel_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_AETRSYNTH_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_adc_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_adc_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_auxcomp_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_AUXCOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_auxcomp_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_AUXCOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_bias_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_bias_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_BIAS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_ctlecomp_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_CTLECOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_ctlecomp_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_CTLECOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_datfbdiv_b_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DATFBDIV_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_datfbdiv_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DATFBDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_dfe_bias_b_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DFE_BIAS_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_dfe_bias_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DFE_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_dfe_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DFE_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_dfe_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DFE_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_dfe_yadj_b_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DFE_YADJ_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_dfe_yadj_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DFE_YADJ_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_duty_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DUTY_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_duty_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DUTY_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_hifreqagc_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_HIFREQAGC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_hifreqagc_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_HIFREQAGC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_ntl_b_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_ntl_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_reg_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_reg_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_vco_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_VCO_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_vco_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_VCO_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_voscreg_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_VOSCREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_voscreg_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_VOSCREG_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_adc_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_adc_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_cdrfbdiv_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_CDRFBDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_cdrfbdiv_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_CDRFBDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_pdet_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_PDET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_pdet_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_PDET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_pfd_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_PFD_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_pfd_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_PFD_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_refdiv_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_refdiv_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_reg_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_reg_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_s2pa_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_S2PA_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_s2pa_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_S2PA_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_s2pb_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_S2PB_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_s2pb_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_S2PB_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_vco_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_VCO_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_vco_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_VCO_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_voscreg_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_VOSCREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_voscreg_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_VOSCREG_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstsynth_postdiv_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTSYNTH_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstsynth_postdiv_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTSYNTH_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_drstrx_dpif_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_DRSTRX_DPIF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_drstrx_dpif_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_DRSTRX_DPIF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_drstrx_ppm_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_DRSTRX_PPM_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_drstrx_ppm_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_DRSTRX_PPM_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_cdrlock2data_locovr_attr == SERDES_IP_LANE_L2_CFG_RXSIGDET_CDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_diglfpsdeten_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_diglfpsdeten_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_diglfpsdeten_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_diglfpsdeten_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_diglfpsdeten_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrancnten_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrancnten_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrancnten_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrancnten_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrancnten_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrancnten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrandeten_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrandeten_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrandeten_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrandeten_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrandeten_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrandeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_eiosdeten_muxd0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_eiosdeten_muxd1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_eiosdeten_muxd2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_eiosdeten_muxd3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_eiosdeten_muxd4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_eiosdeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_enable_attr == SERDES_IP_LANE_L2_CFG_RXSIGDET_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_fastlock_winsize_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_leveldeten_muxd0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_leveldeten_muxd1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_leveldeten_muxd2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_leveldeten_muxd3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_leveldeten_muxd4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_leveldeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_lfpsexit_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_locovren_attr == SERDES_IP_LANE_L2_CFG_RXSIGDET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_ppmdeten_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_ppmdeten_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_ppmdeten_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_ppmdeten_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_ppmdeten_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_ppmdeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_rxeq_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_rxeqen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_rxeqen_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_rxleveldet_debounce_dncount_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_rxleveldet_debounce_flush_en_attr == SERDES_IP_LANE_L2_CFG_RXSIGDET_RXLEVELDET_DEBOUNCE_FLUSH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_rxleveldet_debounce_upcount_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_sigdet_debounce_attr == SERDES_IP_LANE_L2_CFG_RXSIGDET_SIGDET_DEBOUNCE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_tmr_clksel_attr == SERDES_IP_LANE_L2_CFG_RXSIGDET_TMR_CLKSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_toggle_count_en_attr == SERDES_IP_LANE_L2_CFG_RXSIGDET_TOGGLE_COUNT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_toggle_count_pause_attr == SERDES_IP_LANE_L2_CFG_RXSIGDET_TOGGLE_COUNT_PAUSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_toggle_monitor_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdetin_eiosdetectstat_locovr_attr == SERDES_IP_LANE_L2_CFG_RXSIGDETIN_EIOSDETECTSTAT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdetin_locovren_attr == SERDES_IP_LANE_L2_CFG_RXSIGDETIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdetin_ovrcdrlock2data_locovr_attr == SERDES_IP_LANE_L2_CFG_RXSIGDETIN_OVRCDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdetin_ovrencdrlock2data_locovr_attr == SERDES_IP_LANE_L2_CFG_RXSIGDETIN_OVRENCDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdetout_lock2data_noforce_ltr_locovr_attr == SERDES_IP_LANE_L2_CFG_RXSIGDETOUT_LOCK2DATA_NOFORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsigdetout_locovren_attr == SERDES_IP_LANE_L2_CFG_RXSIGDETOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxspare0_attr == 32'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxspare_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsqlchlfps_consec_one_thresh_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsqlchlfps_consec_zero_thresh_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsqlchlfps_cycle_thresh_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsqlchlfps_dat_bitorder_attr == SERDES_IP_LANE_L2_CFG_RXSQLCHLFPS_DAT_BITORDER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsqlchlfps_debounce_type_attr == SERDES_IP_LANE_L2_CFG_RXSQLCHLFPS_DEBOUNCE_TYPE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsqlchlfps_one_run_length_thresh_attr == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsqlchlfps_one_run_length_timeout_attr == 8'd103
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsqlchlfps_zero_run_length_thresh_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsqlchlfps_zero_run_length_timeout_attr == 8'd103
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsynthdiv_slowmed_en_muxd0_attr == SERDES_IP_LANE_L2_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsynthdiv_slowmed_en_muxd1_attr == SERDES_IP_LANE_L2_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsynthdiv_slowmed_en_muxd2_attr == SERDES_IP_LANE_L2_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsynthdiv_slowmed_en_muxd3_attr == SERDES_IP_LANE_L2_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxsynthdiv_slowmed_en_muxd4_attr == SERDES_IP_LANE_L2_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxterm_cal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxterm_coarse_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxterm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXTERM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxterm_modeselect_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxtermhiz_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXTERMHIZ_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxtermhiz_locovren_attr == SERDES_IP_LANE_L2_CFG_RXTERMHIZ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxvoscreg_bypass_vosc_attr == SERDES_IP_LANE_L2_CFG_RXVOSCREG_BYPASS_VOSC_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxvoscregopampoffsetctrl_sel_attr == SERDES_IP_LANE_L2_CFG_RXVOSCREGOPAMPOFFSETCTRL_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxvoscregopampoffseterr_locovren_attr == SERDES_IP_LANE_L2_CFG_RXVOSCREGOPAMPOFFSETERR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxvoscregopampoffseterr_sel_locovr_attr == SERDES_IP_LANE_L2_CFG_RXVOSCREGOPAMPOFFSETERR_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxvoscregvref_locovren_attr == SERDES_IP_LANE_L2_CFG_RXVOSCREGVREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_rxvoscregvref_sel_locovr_attr == SERDES_IP_LANE_L2_CFG_RXVOSCREGVREF_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlch_acqgain_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlch_acqtime_attr == 13'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlch_cal_quiet_locovr_attr == SERDES_IP_LANE_L2_CFG_SQLCH_CAL_QUIET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlch_cal_sel_locovr_attr == SERDES_IP_LANE_L2_CFG_SQLCH_CAL_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlch_calctrl_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlch_calen_locovr_attr == SERDES_IP_LANE_L2_CFG_SQLCH_CALEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlch_caltimer_attr == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlch_clkgate_locovr_attr == SERDES_IP_LANE_L2_CFG_SQLCH_CLKGATE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlch_cmshiften_attr == SERDES_IP_LANE_L2_CFG_SQLCH_CMSHIFTEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_acq_gain_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_acq_pct_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_cal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_clr_errlog_attr == SERDES_IP_LANE_L2_CFG_SQLCH_CONT_CLR_ERRLOG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_controller_mode_attr == SERDES_IP_LANE_L2_CFG_SQLCH_CONT_CONTROLLER_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_dis_attr == SERDES_IP_LANE_L2_CFG_SQLCH_CONT_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_pause_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_postcal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_precal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_quiet_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlch_lfps_en_attr == SERDES_IP_LANE_L2_CFG_SQLCH_LFPS_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlch_locovren_attr == SERDES_IP_LANE_L2_CFG_SQLCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlch_ovrd_val_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlch_pkdet_freqsel_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlch_polarity_attr == SERDES_IP_LANE_L2_CFG_SQLCH_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlch_rdacen_attr == SERDES_IP_LANE_L2_CFG_SQLCH_RDACEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlch_thresh_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlch_time_out_attr == 16'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlch_vrefsel0_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlch_vrefsel1_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlch_vrefsel_ovr_en_attr == SERDES_IP_LANE_L2_CFG_SQLCH_VREFSEL_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlchdeb_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlchdeb_deb_cnt_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlchdeb_deb_status_cnt_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlchdeb_en_attr == SERDES_IP_LANE_L2_CFG_SQLCHDEB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlchdeb_ign_cnt_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlchdeb_sigdet_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlchdeb_thresh_cnt_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlchdebout_exit_good_debounced_locovr_attr == SERDES_IP_LANE_L2_CFG_SQLCHDEBOUT_EXIT_GOOD_DEBOUNCED_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlchdebout_exit_good_debounced_status_locovr_attr == SERDES_IP_LANE_L2_CFG_SQLCHDEBOUT_EXIT_GOOD_DEBOUNCED_STATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlchdebout_exit_good_locovr_attr == SERDES_IP_LANE_L2_CFG_SQLCHDEBOUT_EXIT_GOOD_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_sqlchdebout_locovren_attr == SERDES_IP_LANE_L2_CFG_SQLCHDEBOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_trancnt_off_attr == 10'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_trancnt_on_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_trancntout_det_locovr_attr == SERDES_IP_LANE_L2_CFG_TRANCNTOUT_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_trancntout_locovren_attr == SERDES_IP_LANE_L2_CFG_TRANCNTOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_trandet_ax_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_trandet_ay_attr == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_trandet_off_h_attr == 6'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_trandet_off_l_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_trandet_on_h_attr == 6'd39
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_trandet_on_l_attr == 6'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_trandetout_det_locovr_attr == SERDES_IP_LANE_L2_CFG_TRANDETOUT_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_trandetout_locovren_attr == SERDES_IP_LANE_L2_CFG_TRANDETOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_tx2rxlb_en_attr == SERDES_IP_LANE_L2_CFG_TX2RXLB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_tx2rxlb_init_offset_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_tx_cmn_on_state_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_tx_fastregpwrup_en_attr == SERDES_IP_LANE_L2_CFG_TX_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_tx_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_tx_pg_disable_attr == SERDES_IP_LANE_L2_CFG_TX_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_tx_synth_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_tx_synth_sel_amode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_tx_synth_sel_bmode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_tx_synth_sel_cmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_tx_synth_sel_dmode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_tx_synth_sel_emode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_tx_txdetrx_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txadc_req_attr == SERDES_IP_LANE_L2_CFG_TXADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txaprobe_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txaprobe_lastmux_isolate_attr == SERDES_IP_LANE_L2_CFG_TXAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txaprobeadc_current_direction_attr == SERDES_IP_LANE_L2_CFG_TXAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txaprobeadc_resistor_enable_attr == SERDES_IP_LANE_L2_CFG_TXAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txbdvdr_pma2pcstxworden_attr == SERDES_IP_LANE_L2_CFG_TXBDVDR_PMA2PCSTXWORDEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txbeacon_div_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txbeacon_sel_attr == SERDES_IP_LANE_L2_CFG_TXBEACON_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txbias_icc20uadj_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txbias_icc80uadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txbias_locovren_attr == SERDES_IP_LANE_L2_CFG_TXBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txbias_termcal_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txbist_biterror_en_attr == SERDES_IP_LANE_L2_CFG_TXBIST_BITERROR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txbist_locovren_attr == SERDES_IP_LANE_L2_CFG_TXBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txbist_modesel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txbist_oobmode_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txbist_oobtburst_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txbist_oobtcomrstinit_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txbist_oobtcomsas_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txbist_oobtcomwake_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txbist_seed_attr == 31'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_size_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf00_attr == 32'd1985229328
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf01_attr == 32'd4275878552
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf02_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf03_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf04_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf05_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf06_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf07_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf08_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf09_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txbit_select_muxd0_attr == SERDES_IP_LANE_L2_CFG_TXBIT_SELECT_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txbit_select_muxd1_attr == SERDES_IP_LANE_L2_CFG_TXBIT_SELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txbit_select_muxd2_attr == SERDES_IP_LANE_L2_CFG_TXBIT_SELECT_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txbit_select_muxd3_attr == SERDES_IP_LANE_L2_CFG_TXBIT_SELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txbit_select_muxd4_attr == SERDES_IP_LANE_L2_CFG_TXBIT_SELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txbti_data_replication_attr == SERDES_IP_LANE_L2_CFG_TXBTI_DATA_REPLICATION_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txbti_tx_idle_data_en_attr == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcal_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcal_tclkduty_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalduty_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalduty_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTY_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalduty_sel_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutybg_abort_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutybg_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutybg_ready_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutycomp_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutycomp_offset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_finish_side_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_init_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_initval_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_invert_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_req_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_round_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_runcount_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_signmagen_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsmout_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsmout_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompmeas_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompmeas_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompmeas_req_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompmeasout_ack_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPMEASOUT_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompmeasout_erravg_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPMEASOUT_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompmeasout_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_bg_en_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_bg_one_step_cal_en_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_finish_side_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_init_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_invert_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_req_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_round_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_runcount_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_signmagen_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeas_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeas_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeas_req_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeasout_ack_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYMEASOUT_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeasout_erravg_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYMEASOUT_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeasout_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutystat_done_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaldutystat_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalptr_pstate_duty_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalptr_pstate_dutycomp_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalptr_pstate_regopampoffset_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_duty_muxd0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_duty_muxd1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_duty_muxd2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_duty_muxd3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_duty_muxd4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_dutycomp_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_dutycomp_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_dutycomp_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_dutycomp_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_dutycomp_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_regopampoffset_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffset_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_finish_side_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_round_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_runcount_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_signmagen_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcaltclkdutyforce_div1_attr == SERDES_IP_LANE_L2_CFG_TXCALTCLKDUTYFORCE_DIV1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txcdrdiv_local_en_attr == SERDES_IP_LANE_L2_CFG_TXCDRDIV_LOCAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txclk_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txclk_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txclkgenmuxsel_txinternal_attr == SERDES_IP_LANE_L2_CFG_TXCLKGENMUXSEL_TXINTERNAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txdetectrx_thr_attr == 5'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeas_count_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeas_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXDETECTRXMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeas_locovren_attr == SERDES_IP_LANE_L2_CFG_TXDETECTRXMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeas_validdlycount_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeasin_locovren_attr == SERDES_IP_LANE_L2_CFG_TXDETECTRXMEASIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeasin_start_locovr_attr == SERDES_IP_LANE_L2_CFG_TXDETECTRXMEASIN_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeaspcs_locovren_attr == SERDES_IP_LANE_L2_CFG_TXDETECTRXMEASPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeaspcs_req_locovr_attr == SERDES_IP_LANE_L2_CFG_TXDETECTRXMEASPCS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeasval_locovren_attr == SERDES_IP_LANE_L2_CFG_TXDETECTRXMEASVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeasval_stat_locovr_attr == SERDES_IP_LANE_L2_CFG_TXDETECTRXMEASVAL_STAT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txdetrx_levn_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txdetrx_levnm1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txdetrx_levnp1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txdetrx_levnp2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txdrv_hizen_locovr_attr == SERDES_IP_LANE_L2_CFG_TXDRV_HIZEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txdrv_levn_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txdrv_levnm1_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txdrv_levnp1_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txdrv_levnp2_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txdrv_locovren_attr == SERDES_IP_LANE_L2_CFG_TXDRV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txdrv_refcken_attr == SERDES_IP_LANE_L2_CFG_TXDRV_REFCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txdrv_termref_attr == SERDES_IP_LANE_L2_CFG_TXDRV_TERMREF_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txdrvmute_locovr_attr == SERDES_IP_LANE_L2_CFG_TXDRVMUTE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txdrvmute_locovren_attr == SERDES_IP_LANE_L2_CFG_TXDRVMUTE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txduty_ctrl_disable_attr == SERDES_IP_LANE_L2_CFG_TXDUTY_CTRL_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txduty_pad_sense_en_attr == SERDES_IP_LANE_L2_CFG_TXDUTY_PAD_SENSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txdutycal_div16_en_attr == SERDES_IP_LANE_L2_CFG_TXDUTYCAL_DIV16_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txdutycal_div1_en_attr == SERDES_IP_LANE_L2_CFG_TXDUTYCAL_DIV1_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txdutycal_div2_en_attr == SERDES_IP_LANE_L2_CFG_TXDUTYCAL_DIV2_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txdutycal_div4_en_attr == SERDES_IP_LANE_L2_CFG_TXDUTYCAL_DIV4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txdutycal_div8_en_attr == SERDES_IP_LANE_L2_CFG_TXDUTYCAL_DIV8_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txfifo_elecidle_deskew_en_attr == SERDES_IP_LANE_L2_CFG_TXFIFO_ELECIDLE_DESKEW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txfifo_force_txidlebit1_zero_disable_attr == SERDES_IP_LANE_L2_CFG_TXFIFO_FORCE_TXIDLEBIT1_ZERO_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txfifo_kill_dly_10b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txfifo_kill_dly_16b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txfifo_kill_dly_20b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txfifo_kill_dly_32b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txfifo_kill_dly_40b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txfifo_kill_dly_64b_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txfifo_kill_dly_80b_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txfifo_kill_dly_8b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txfifo_kill_en_attr == SERDES_IP_LANE_L2_CFG_TXFIFO_KILL_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txfsm_cken_ovr_attr == SERDES_IP_LANE_L2_CFG_TXFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txfsm_cken_ovren_attr == SERDES_IP_LANE_L2_CFG_TXFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txfsm_main_on_state_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txl1d1_doze_ctrl_attr == SERDES_IP_LANE_L2_CFG_TXL1D1_DOZE_CTRL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txl1d1_txbias_ctrl_attr == SERDES_IP_LANE_L2_CFG_TXL1D1_TXBIAS_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txlanepam_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXLANEPAM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txlanepam_locovren_attr == SERDES_IP_LANE_L2_CFG_TXLANEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txmeaslatovrhd_meas_sel_attr == SERDES_IP_LANE_L2_CFG_TXMEASLATOVRHD_MEAS_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txmute_delay_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txntl_changeref_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txntl_changeref_val_locovr_attr == SERDES_IP_LANE_L2_CFG_TXNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txntl_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txntl_en_attr == SERDES_IP_LANE_L2_CFG_TXNTL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txntl_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txntl_locovren_attr == SERDES_IP_LANE_L2_CFG_TXNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txntl_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txntl_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txntl_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txntl_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txntl_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txntl_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txntl_txm_charge_up_locovr_attr == SERDES_IP_LANE_L2_CFG_TXNTL_TXM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txntl_txm_pull_dn_locovr_attr == SERDES_IP_LANE_L2_CFG_TXNTL_TXM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txntl_txm_sense_locovr_attr == SERDES_IP_LANE_L2_CFG_TXNTL_TXM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txntl_txp_charge_up_locovr_attr == SERDES_IP_LANE_L2_CFG_TXNTL_TXP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txntl_txp_pull_dn_locovr_attr == SERDES_IP_LANE_L2_CFG_TXNTL_TXP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txntl_txp_sense_locovr_attr == SERDES_IP_LANE_L2_CFG_TXNTL_TXP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txp2s_txwordsyncbypen_attr == SERDES_IP_LANE_L2_CFG_TXP2S_TXWORDSYNCBYPEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txpam_bitorder_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txpam_gray_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXPAM_GRAY_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txpam_locovren_attr == SERDES_IP_LANE_L2_CFG_TXPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txpam_precode_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXPAM_PRECODE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txpcs_locovren_attr == SERDES_IP_LANE_L2_CFG_TXPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txpcs_txenable_locovr_attr == SERDES_IP_LANE_L2_CFG_TXPCS_TXENABLE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txpcsbist_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXPCSBIST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txpcsbist_locovren_attr == SERDES_IP_LANE_L2_CFG_TXPCSBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txratewidth_clk_chk_disable_attr == SERDES_IP_LANE_L2_CFG_TXRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txratewidth_etr_on_delay_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txratewidth_locovren_attr == SERDES_IP_LANE_L2_CFG_TXRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txreg_toggle_pwrupacc_on_rate_change_en_attr == SERDES_IP_LANE_L2_CFG_TXREG_TOGGLE_PWRUPACC_ON_RATE_CHANGE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txreg_toggle_reset_on_rate_change_en_attr == SERDES_IP_LANE_L2_CFG_TXREG_TOGGLE_RESET_ON_RATE_CHANGE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txresetdel_sel_attr == SERDES_IP_LANE_L2_CFG_TXRESETDEL_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_en_b_attr == SERDES_IP_LANE_L2_CFG_TXRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s0q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s0q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s1q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s1q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s2q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s2q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s2q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s2q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s2q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s2q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s2q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s3q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s3q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s3q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s3q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s3q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s3q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s3q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s3q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s4q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s4q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s5q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_entry2_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s0q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s0q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s1q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s1q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s1q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s1q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s1q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s1q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s2q0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s2q1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s2q2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s2q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s2q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s2q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s2q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s2q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s3q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s3q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s3q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s3q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s3q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s3q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s3q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s3q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s4q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s4q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s5q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_dn_ptr0_s_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_up_ptr0_s_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_aetrtx_bitckdvdrcken_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_AETRTX_BITCKDVDRCKEN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_aetrtx_bitckdvdrcken_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_AETRTX_BITCKDVDRCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_aetrtx_regpwrupacc_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_AETRTX_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_aetrtx_regpwrupacc_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_AETRTX_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_adc_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_adc_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_drvdoze_b_ovr_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_DRVDOZE_B_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_drvdoze_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_DRVDOZE_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_duty_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_DUTY_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_duty_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_DUTY_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_ntl_b_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_ntl_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_p2s_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_P2S_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_p2s_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_P2S_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_reg_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_reg_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_arsttx_adc_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_ARSTTX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_arsttx_adc_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_ARSTTX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_arsttx_pma2pcstxword_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_ARSTTX_PMA2PCSTXWORD_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_arsttx_pma2pcstxword_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_ARSTTX_PMA2PCSTXWORD_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_arsttx_regreset_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_ARSTTX_REGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_arsttx_regreset_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_ARSTTX_REGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_arsttx_txdetectrx_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_ARSTTX_TXDETECTRX_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_arsttx_txdetectrx_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_ARSTTX_TXDETECTRX_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txrststate_hiz_en_attr == SERDES_IP_LANE_L2_CFG_TXRSTSTATE_HIZ_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txspare0_attr == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txspare_attr == 10'd384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txterm_coarse_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txtermtrim_locovren_attr == SERDES_IP_LANE_L2_CFG_TXTERMTRIM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txtermtrim_nmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txtermtrim_pmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txwclk_div_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txwclk_div_en_attr == SERDES_IP_LANE_L2_CFG_TXWCLK_DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txwclk_div_smpl_attr == SERDES_IP_LANE_L2_CFG_TXWCLK_DIV_SMPL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txwptr_init01_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txwptr_init02_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txwptr_init04_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txwptr_init08_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txwptr_init16_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txwptr_init32_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l2_cfg_txwptr_init_rx2txparlb_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_bshihyst_attr == SERDES_IP_LANE_L3_CFG_BSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_bstxdrv_levn_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_bstxdrv_levnm1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_bstxdrv_levnp1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_bstxdrv_levnp2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_calsqlchosc_locovren_attr == SERDES_IP_LANE_L3_CFG_CALSQLCHOSC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_calsqlchosc_trimcode_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_cdrclkstat_locovren_attr == SERDES_IP_LANE_L3_CFG_CDRCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_cdrclkstat_ready_locovr_attr == SERDES_IP_LANE_L3_CFG_CDRCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_etrregrxcdrclk_ready_attr == SERDES_IP_LANE_L3_CFG_ETRREGRXCDRCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_laneckm_avg_en_attr == SERDES_IP_LANE_L3_CFG_LANECKM_AVG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_laneckm_clk_en_attr == SERDES_IP_LANE_L3_CFG_LANECKM_CLK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_laneckm_continuous_attr == SERDES_IP_LANE_L3_CFG_LANECKM_CONTINUOUS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_laneckm_dig_meas_en_attr == SERDES_IP_LANE_L3_CFG_LANECKM_DIG_MEAS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_laneckm_dig_meas_err_clr_attr == SERDES_IP_LANE_L3_CFG_LANECKM_DIG_MEAS_ERR_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_laneckm_en_attr == SERDES_IP_LANE_L3_CFG_LANECKM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_laneckm_max_thr_attr == 25'd33554431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_laneckm_meas_ck_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_laneckm_ref_ck_div_ratio_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_laneckm_result_clr_attr == SERDES_IP_LANE_L3_CFG_LANECKM_RESULT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_laneckm_start_attr == SERDES_IP_LANE_L3_CFG_LANECKM_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_laneckm_wdt_interval_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_laneckm_win_thr_ref_attr == 25'd16777215
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_lanepcs_locovren_attr == SERDES_IP_LANE_L3_CFG_LANEPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_lanepcs_mode_locovr_attr == SERDES_IP_LANE_L3_CFG_LANEPCS_MODE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_laneperfmon_compare_val_start_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_laneperfmon_compare_val_stop_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_laneperfmon_en_attr == SERDES_IP_LANE_L3_CFG_LANEPERFMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_laneperfmon_mask_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_lanepmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_lanepmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_lanepmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_lanepmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_lanepmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_lanepmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_lb_cdrclk2txen_locovr_attr == SERDES_IP_LANE_L3_CFG_LB_CDRCLK2TXEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_lb_cdrclkdiven_attr == SERDES_IP_LANE_L3_CFG_LB_CDRCLKDIVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_lb_cdrdivclk2exten_attr == SERDES_IP_LANE_L3_CFG_LB_CDRDIVCLK2EXTEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_lb_cdrdivclk2txen_attr == SERDES_IP_LANE_L3_CFG_LB_CDRDIVCLK2TXEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_lb_hsclk2cdrdiven_attr == SERDES_IP_LANE_L3_CFG_LB_HSCLK2CDRDIVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_lb_locovren_attr == SERDES_IP_LANE_L3_CFG_LB_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_lb_parrx2txtimeden_locovr_attr == SERDES_IP_LANE_L3_CFG_LB_PARRX2TXTIMEDEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_lb_pllfbclk2cdrrefclken_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_lb_pllfbclk2cdrrefclken_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_lb_pllfbclk2cdrrefclken_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_lb_pllfbclk2cdrrefclken_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_lb_pllfbclk2cdrrefclken_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_lb_rx2txuntimeden_attr == SERDES_IP_LANE_L3_CFG_LB_RX2TXUNTIMEDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_lb_rxwordck2pcstxwordcken_attr == SERDES_IP_LANE_L3_CFG_LB_RXWORDCK2PCSTXWORDCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_lb_tx2rxbuftimeden_lsb_locovr_attr == SERDES_IP_LANE_L3_CFG_LB_TX2RXBUFTIMEDEN_LSB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_lb_tx2rxbuftimeden_msb_locovr_attr == SERDES_IP_LANE_L3_CFG_LB_TX2RXBUFTIMEDEN_MSB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_lb_tx2rxiotimeden_attr == SERDES_IP_LANE_L3_CFG_LB_TX2RXIOTIMEDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_lfps_det_locovr_attr == SERDES_IP_LANE_L3_CFG_LFPS_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_lfps_locovren_attr == SERDES_IP_LANE_L3_CFG_LFPS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_lfps_out_en_attr == SERDES_IP_LANE_L3_CFG_LFPS_OUT_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_pcslfps_en_locovr_attr == SERDES_IP_LANE_L3_CFG_PCSLFPS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_pcslfps_locovren_attr == SERDES_IP_LANE_L3_CFG_PCSLFPS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_pcsrx_dme_en_locovr_attr == SERDES_IP_LANE_L3_CFG_PCSRX_DME_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_pcsrx_locovren_attr == SERDES_IP_LANE_L3_CFG_PCSRX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_pcsrxbist_locovren_attr == SERDES_IP_LANE_L3_CFG_PCSRXBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_pcsrxbist_modesel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_pcstx_beaconen_locovr_attr == SERDES_IP_LANE_L3_CFG_PCSTX_BEACONEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_pcstx_locovren_attr == SERDES_IP_LANE_L3_CFG_PCSTX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_polarity_rx_attr == SERDES_IP_LANE_L3_CFG_POLARITY_RX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_polarity_tx_attr == SERDES_IP_LANE_L3_CFG_POLARITY_TX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rx_cmn_on_state_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rx_fastregpwrup_en_attr == SERDES_IP_LANE_L3_CFG_RX_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rx_frac_mode_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rx_on_state_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rx_pg_disable_attr == SERDES_IP_LANE_L3_CFG_RX_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rx_synth_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rx_synth_sel_amode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rx_synth_sel_bmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rx_synth_sel_cmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rx_synth_sel_dmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rx_synth_sel_emode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxadc_req_attr == SERDES_IP_LANE_L3_CFG_RXADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxagc_dccoupleen_attr == SERDES_IP_LANE_L3_CFG_RXAGC_DCCOUPLEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxaprobe_addr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxaprobe_lastmux_isolate_attr == SERDES_IP_LANE_L3_CFG_RXAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxaprobeadc_current_direction_attr == SERDES_IP_LANE_L3_CFG_RXAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxaprobeadc_resistor_enable_attr == SERDES_IP_LANE_L3_CFG_RXAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxbias_iccadj_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxbias_icvadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxbias_locovren_attr == SERDES_IP_LANE_L3_CFG_RXBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxbias_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxbist_burst_four_errtype_attr == SERDES_IP_LANE_L3_CFG_RXBIST_BURST_FOUR_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxbist_burst_one_errtype_attr == SERDES_IP_LANE_L3_CFG_RXBIST_BURST_ONE_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxbist_burst_three_errtype_attr == SERDES_IP_LANE_L3_CFG_RXBIST_BURST_THREE_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxbist_burst_two_errtype_attr == SERDES_IP_LANE_L3_CFG_RXBIST_BURST_TWO_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxbist_cdrlock2data_bypass_attr == SERDES_IP_LANE_L3_CFG_RXBIST_CDRLOCK2DATA_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxbist_cdrlock2data_postamble_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxbist_clear_errcount_attr == SERDES_IP_LANE_L3_CFG_RXBIST_CLEAR_ERRCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxbist_err_en_attr == SERDES_IP_LANE_L3_CFG_RXBIST_ERR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxbist_err_trig_type_attr == SERDES_IP_LANE_L3_CFG_RXBIST_ERR_TRIG_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxbist_errmask_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxbist_errtype_attr == SERDES_IP_LANE_L3_CFG_RXBIST_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxbist_firsterr_type_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxbist_lockchk_count_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxbist_maxbitcnt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxbist_mostrecent_err_attr == SERDES_IP_LANE_L3_CFG_RXBIST_MOSTRECENT_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxbist_relock_itercount_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxbist_seed_attr == 31'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxbist_status_hold_attr == SERDES_IP_LANE_L3_CFG_RXBIST_STATUS_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxbitslip_locovr_attr == SERDES_IP_LANE_L3_CFG_RXBITSLIP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxbitslip_locovren_attr == SERDES_IP_LANE_L3_CFG_RXBITSLIP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxbscan_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxbshicm_attr == SERDES_IP_LANE_L3_CFG_RXBSHICM_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalcdrfbdiv_div2_bypass_muxd0_attr == SERDES_IP_LANE_L3_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalcdrfbdiv_div2_bypass_muxd1_attr == SERDES_IP_LANE_L3_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalcdrfbdiv_div2_bypass_muxd2_attr == SERDES_IP_LANE_L3_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalcdrfbdiv_div2_bypass_muxd3_attr == SERDES_IP_LANE_L3_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalcdrfbdiv_div2_bypass_muxd4_attr == SERDES_IP_LANE_L3_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalduty_iclk_gray_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalduty_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTY_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalduty_qclk_gray_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalduty_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutybg_abort_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutybg_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutybg_ready_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycomp_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycomp_offset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_finish_side_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_init_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_initval_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_invert_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_round_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_runcount_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_signmagen_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsmout_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsmout_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_disable_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCTRL_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_i_div1_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_i_div2_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_i_div4_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_i_div8_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_q_div1_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_q_div2_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_q_div4_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_q_div8_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_bg_en_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_bg_one_step_cal_en_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_finish_side_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_i_polarity_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_I_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_i_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_I_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_init_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_q_polarity_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_Q_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_q_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_Q_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_round_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_runcount_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_signmagen_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_comp_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEAS_COMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_comp_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEAS_COMP_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_i_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEAS_I_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_i_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEAS_I_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_q_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEAS_Q_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_q_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEAS_Q_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeasout_comp_ack_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEASOUT_COMP_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeasout_comp_erravg_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEASOUT_COMP_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeasout_i_ack_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEASOUT_I_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeasout_i_erravg_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEASOUT_I_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeasout_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeasout_q_ack_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEASOUT_Q_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeasout_q_erravg_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEASOUT_Q_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutystat_done_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaldutystat_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_centerfreq_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_end_delay_attr == 9'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_hscount_muxd0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_hscount_muxd1_attr == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_hscount_muxd2_attr == 8'd180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_hscount_muxd3_attr == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_hscount_muxd4_attr == 8'd206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_initval_centerfreq_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_initval_fosc_attr == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_centerfreq_finish_side_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_CENTERFREQ_FINISH_SIDE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_centerfreq_to_fosc_offset_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_centerfreqen_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_CENTERFREQEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_centerfreqoffset_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_fosc_finishside_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_FOSC_FINISHSIDE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_foscen_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_FOSCEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_foscoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_init_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_invert_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_lpfax_calfosccoarse_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_lpfax_calfoscfine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_lpfax_centerfreqcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_lpfax_centerfreqfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_runcount_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_signmagen_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_vcorepen_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_VCOREPEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsmout_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsmout_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_count_muxd0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_count_muxd1_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_count_muxd2_attr == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_count_muxd3_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_count_muxd4_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_dlycount_attr == 9'd68
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeasout_clear_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCMEASOUT_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeasout_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeasout_start_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCMEASOUT_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscval_int_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscval_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalintsval_int_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalintsval_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALINTSVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaloffsetfsm_init_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaloffsetfsm_init_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaloffsetfsm_init_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALOFFSETFSM_INIT_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaloffsetfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcaloffsetfsmout_input_en_attr == SERDES_IP_LANE_L3_CFG_RXCALOFFSETFSMOUT_INPUT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_duty_i_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_duty_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_dutycomp_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_foscfsm_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_offsetfsm_init_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_regopampoffset_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_rxppm_lockstatus_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_sqlch_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_sqlchosc_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_synthppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_voscregopampoffset_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_duty_i_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_duty_q_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_dutycomp_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_foscfsm_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_offsetfsm_init_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_rxppm_lockstatus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_sqlch_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_sqlchosc_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_synthppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_voscregopampoffset_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffset_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_finish_side_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_round_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_runcount_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_signmagen_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchfsm_clear_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchfsm_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchfsmout_caldone_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHFSMOUT_CALDONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchfsmout_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_codeoffset_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_finish_side_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHOSCFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_init_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHOSCFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_initval_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_invert_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHOSCFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHOSCFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHOSCFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_round_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHOSCFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_runcount_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHOSCFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscmeas_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHOSCMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscmeas_ref_cnt_attr == 10'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscmeas_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHOSCMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscmeas_settle_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscmeas_smpl_cnt_attr == 10'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvbiascap_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALVBIASCAP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvbiascap_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALVBIASCAP_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvcoopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvcoopampoffsetmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvcoopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvcoopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffset_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffset_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_codeoffset_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_finish_side_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_initval_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_invert_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_lpfaxcoarse_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_round_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_runcount_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETFSM_RUNCOUNT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_signmagen_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsmout_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsmout_runcount_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETFSMOUT_RUNCOUNT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetmeas_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffset_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALVOSCREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALVOSCREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L3_CFG_RXCALVOSCREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALVOSCREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALVOSCREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALVOSCREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALVOSCREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALVOSCREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALVOSCREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrdiv_local_en_attr == SERDES_IP_LANE_L3_CFG_RXCDRDIV_LOCAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdiv_moddiv_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdiv_moddiv_muxd1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdiv_moddiv_muxd2_attr == 4'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdiv_moddiv_muxd3_attr == 4'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdiv_moddiv_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdivslip_mdiv_muxd0_attr == 9'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdivslip_mdiv_muxd1_attr == 9'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdivslip_mdiv_muxd2_attr == 9'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdivslip_mdiv_muxd3_attr == 9'd66
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdivslip_mdiv_muxd4_attr == 9'd210
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrpfd_forcedn_attr == SERDES_IP_LANE_L3_CFG_RXCDRPFD_FORCEDN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrpfd_forceen_attr == SERDES_IP_LANE_L3_CFG_RXCDRPFD_FORCEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrpfd_forceup_attr == SERDES_IP_LANE_L3_CFG_RXCDRPFD_FORCEUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrpfd_propgain_attr == SERDES_IP_LANE_L3_CFG_RXCDRPFD_PROPGAIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrpfd_pulsewidth_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrphd_asym_override_ignore_attr == SERDES_IP_LANE_L3_CFG_RXCDRPHD_ASYM_OVERRIDE_IGNORE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrphd_bitshift_en_attr == SERDES_IP_LANE_L3_CFG_RXCDRPHD_BITSHIFT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrphd_forcedn_attr == SERDES_IP_LANE_L3_CFG_RXCDRPHD_FORCEDN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrphd_forceen_attr == SERDES_IP_LANE_L3_CFG_RXCDRPHD_FORCEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrphd_forceup_attr == SERDES_IP_LANE_L3_CFG_RXCDRPHD_FORCEUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrphdrate_doublerate2s2p_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCDRPHDRATE_DOUBLERATE2S2P_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrphdrate_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCDRPHDRATE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrrefck_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrrefck_refdiv_muxd1_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrrefck_refdiv_muxd2_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrrefck_refdiv_muxd3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrrefck_refdiv_muxd4_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_biastop_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_biastopbypass_attr == SERDES_IP_LANE_L3_CFG_RXCDRVCO_BIASTOPBYPASS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_datapropgain_high_attr == 5'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_datapropgain_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_datapropgain_low_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_ff_ovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_ff_ovr_en_attr == SERDES_IP_LANE_L3_CFG_RXCDRVCO_FF_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_fil_short_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_flickerdegen_attr == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_gmfoscshort_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCDRVCO_GMFOSCSHORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_intf_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_intf_fil_short_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_intrj_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCDRVCO_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_refpropgain_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_refpropgain_nom_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxclk_cdrfb_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCLK_CDRFB_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxclk_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxclk_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdat_nrz_64b80b_bcword_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdata_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXDATA_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdata_locovren_attr == SERDES_IP_LANE_L3_CFG_RXDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdatapath_locovren_attr == SERDES_IP_LANE_L3_CFG_RXDATAPATH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdatapath_on_state_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdatapath_ready_locovr_attr == SERDES_IP_LANE_L3_CFG_RXDATAPATH_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdfe_datatap_vcasc_attr == 4'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdfe_dfebiasadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdfe_nbiasctle_en_attr == SERDES_IP_LANE_L3_CFG_RXDFE_NBIASCTLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdfe_vcasc_sel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdfeterm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXDFETERM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdfeterm_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdfeyadjdac_datamid_edge_coarse_en_attr == SERDES_IP_LANE_L3_CFG_RXDFEYADJDAC_DATAMID_EDGE_COARSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdfeyadjdac_datatopbot_aux_coarse_en_attr == SERDES_IP_LANE_L3_CFG_RXDFEYADJDAC_DATATOPBOT_AUX_COARSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_accum_mon_en_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_ACCUM_MON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_accum_mon_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_bypasscdrpdetupdnsmpl_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_bypassenfosc_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_BYPASSENFOSC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_bypassenints_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_BYPASSENINTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_bypassenupdnsmpl_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_BYPASSENUPDNSMPL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_bypassfosc_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_bypasspllpfdupdnsmpl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_bypassrxints_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_data2pll_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_deltasigmode_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_DELTASIGMODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_fastref_muxd0_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_FASTREF_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_fastref_muxd1_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_FASTREF_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_fastref_muxd2_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_FASTREF_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_fastref_muxd3_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_FASTREF_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_fastref_muxd4_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_FASTREF_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_fosc_mod_bypass_en_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_FOSC_MOD_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_fosc_sample_pedge_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_FOSC_SAMPLE_PEDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gain_step_on_lock_recovery_en_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_GAIN_STEP_ON_LOCK_RECOVERY_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gaindelaycount_init_attr == 9'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gaindelaycount_pow2_muxd0_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gaindelaycount_pow2_muxd1_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gaindelaycount_pow2_muxd2_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gaindelaycount_pow2_muxd3_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gaindelaycount_pow2_muxd4_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2ref_pow2_muxd0_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2ref_pow2_muxd1_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2ref_pow2_muxd2_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2ref_pow2_muxd3_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2ref_pow2_muxd4_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainunlocked_pow2_muxd0_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainunlocked_pow2_muxd1_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainunlocked_pow2_muxd2_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainunlocked_pow2_muxd3_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainunlocked_pow2_muxd4_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_initintegrator_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_INITINTEGRATOR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_initmodulator_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_INITMODULATOR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_deltasig_mode_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_INTS_DELTASIG_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_freeze_en_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_INTS_FREEZE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gaindelaycount_pow2_muxd0_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gaindelaycount_pow2_muxd1_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gaindelaycount_pow2_muxd2_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gaindelaycount_pow2_muxd3_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gaindelaycount_pow2_muxd4_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd0_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd1_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd2_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd3_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd4_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd0_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd1_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd2_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd3_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd4_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainunlocked_pow2_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainunlocked_pow2_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainunlocked_pow2_muxd2_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainunlocked_pow2_muxd3_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainunlocked_pow2_muxd4_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_guardband_hi_attr == 8'd200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_guardband_lo_attr == 8'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_loop_sel_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_INTS_LOOP_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_mod_bypass_en_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_INTS_MOD_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_mod_load_pedge_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_INTS_MOD_LOAD_PEDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_step_to_integer_en_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_INTS_STEP_TO_INTEGER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_jit_length_attr == 18'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_jit_mode_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_JIT_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_modck_ctrl_en_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_MODCK_CTRL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_pll2data_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_restore_cntr_attr == 9'd258
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_store_cntr_attr == 16'd258
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpif_trnsfrdelay_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpiffreeze_inten_attr == SERDES_IP_LANE_L3_CFG_RXDPIFFREEZE_INTEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdpiffreeze_moden_attr == SERDES_IP_LANE_L3_CFG_RXDPIFFREEZE_MODEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxdutyselpolarity_attr == SERDES_IP_LANE_L3_CFG_RXDUTYSELPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxflxgate_force_rxeq_gate_locovr_attr == SERDES_IP_LANE_L3_CFG_RXFLXGATE_FORCE_RXEQ_GATE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxflxgate_locovren_attr == SERDES_IP_LANE_L3_CFG_RXFLXGATE_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxfoscstat_done_locovr_attr == SERDES_IP_LANE_L3_CFG_RXFOSCSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxfoscstat_locovren_attr == SERDES_IP_LANE_L3_CFG_RXFOSCSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxfsm_cken_ovr_attr == SERDES_IP_LANE_L3_CFG_RXFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxfsm_cken_ovren_attr == SERDES_IP_LANE_L3_CFG_RXFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxints_prev_votes_hold_en_attr == SERDES_IP_LANE_L3_CFG_RXINTS_PREV_VOTES_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxlanepam_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXLANEPAM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxlanepam_locovren_attr == SERDES_IP_LANE_L3_CFG_RXLANEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxlock2datatmr_attr == 8'd240
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxlock2datatmr_short_attr == 8'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxntl_changeref_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxntl_changeref_val_locovr_attr == SERDES_IP_LANE_L3_CFG_RXNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxntl_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxntl_en_attr == SERDES_IP_LANE_L3_CFG_RXNTL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxntl_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxntl_locovren_attr == SERDES_IP_LANE_L3_CFG_RXNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxntl_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxntl_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxntl_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxntl_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxntl_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxntl_rxm_charge_up_locovr_attr == SERDES_IP_LANE_L3_CFG_RXNTL_RXM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxntl_rxm_pull_dn_locovr_attr == SERDES_IP_LANE_L3_CFG_RXNTL_RXM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxntl_rxm_sense_locovr_attr == SERDES_IP_LANE_L3_CFG_RXNTL_RXM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxntl_rxp_charge_up_locovr_attr == SERDES_IP_LANE_L3_CFG_RXNTL_RXP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxntl_rxp_pull_dn_locovr_attr == SERDES_IP_LANE_L3_CFG_RXNTL_RXP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxntl_rxp_sense_locovr_attr == SERDES_IP_LANE_L3_CFG_RXNTL_RXP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxntl_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_acc_freeze_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_ACC_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_cdrlock2data_gater_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_cdrlock2data_gater_hold_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_cdrlock2data_gater_ovrd_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_cdrlock2datatmr_optcl_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_cdrlock2datatmr_optcl_sel_ovrd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_enter_lock2data_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_ENTER_LOCK2DATA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_enter_lock2data_hold_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_ENTER_LOCK2DATA_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_exit_lock2data_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_EXIT_LOCK2DATA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_exit_lock2data_hold_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_EXIT_LOCK2DATA_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_force_lock2data_ovrd_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_FORCE_LOCK2DATA_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_force_lock2ref_ovrd_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_FORCE_LOCK2REF_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_hold_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_hold_timer_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_intf_ovrd_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_INTF_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_intf_ovrd_type_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_INTF_OVRD_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_mod_freeze_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_MOD_FREEZE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_ovrd_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_ppm_detect_freeze_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_PPM_DETECT_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_ppm_detect_freeze_ovrd_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_PPM_DETECT_FREEZE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_ppm_detect_hold_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_PPM_DETECT_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_prop_freeze_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_PROP_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_prop_freeze_ovrd_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_PROP_FREEZE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_rxdata_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_RXDATA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_skip_init_lock2data_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_SKIP_INIT_LOCK2DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxpam_bitorder_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxpam_gray_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXPAM_GRAY_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxpam_locovren_attr == SERDES_IP_LANE_L3_CFG_RXPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxpam_precode_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXPAM_PRECODE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_p5_muxd0_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIV_P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_p5_muxd1_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIV_P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_p5_muxd2_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIV_P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_p5_muxd3_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIV_P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_p5_muxd4_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIV_P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdivclken_muxd0_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIVCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdivclken_muxd1_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIVCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdivclken_muxd2_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIVCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdivclken_muxd3_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIVCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdivclken_muxd4_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIVCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxpcsbist_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXPCSBIST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxpcsbist_locovren_attr == SERDES_IP_LANE_L3_CFG_RXPCSBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxphd_gain_hold_en_attr == SERDES_IP_LANE_L3_CFG_RXPHD_GAIN_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxphd_gain_zero_locovr_attr == SERDES_IP_LANE_L3_CFG_RXPHD_GAIN_ZERO_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxphd_locovren_attr == SERDES_IP_LANE_L3_CFG_RXPHD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxphd_majvote_basegain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxphd_majvote_en_attr == SERDES_IP_LANE_L3_CFG_RXPHD_MAJVOTE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxphd_mute_cntr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxphd_nrz8b10b_pam16b20b_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxphd_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxphd_pam_transition_sel_attr == SERDES_IP_LANE_L3_CFG_RXPHD_PAM_TRANSITION_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxphd_sign_invert_attr == SERDES_IP_LANE_L3_CFG_RXPHD_SIGN_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxpostdiv_wait_for_lock_disable_attr == SERDES_IP_LANE_L3_CFG_RXPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxppm_freq_max_offset_h_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxppm_freq_max_offset_l_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxppm_freq_ref_cnt_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxppm_lockstatus_locovr_attr == SERDES_IP_LANE_L3_CFG_RXPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxppm_lockstatus_synthlcfast_en_attr == SERDES_IP_LANE_L3_CFG_RXPPM_LOCKSTATUS_SYNTHLCFAST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxppm_lockstatus_synthlcmed_en_attr == SERDES_IP_LANE_L3_CFG_RXPPM_LOCKSTATUS_SYNTHLCMED_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxppm_lockstatus_synthlcslow_en_attr == SERDES_IP_LANE_L3_CFG_RXPPM_LOCKSTATUS_SYNTHLCSLOW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxppm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxppm_ppmdriftcount_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxppm_ppmdriftmax_attr == 16'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxppm_status_hold_attr == SERDES_IP_LANE_L3_CFG_RXPPM_STATUS_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxppm_unlock_clear_attr == SERDES_IP_LANE_L3_CFG_RXPPM_UNLOCK_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_fast_muxd0_attr == 16'd666
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_fast_muxd1_attr == 16'd4000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_fast_muxd2_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_fast_muxd3_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_fast_muxd4_attr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_muxd0_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_muxd1_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_muxd2_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_muxd3_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_muxd4_attr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxppmctrl_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXPPMCTRL_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxppmctrl_locovren_attr == SERDES_IP_LANE_L3_CFG_RXPPMCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxppmlockstat_locovren_attr == SERDES_IP_LANE_L3_CFG_RXPPMLOCKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxppmlockstat_sticky_locovr_attr == SERDES_IP_LANE_L3_CFG_RXPPMLOCKSTAT_STICKY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxppmtmr_locovren_attr == SERDES_IP_LANE_L3_CFG_RXPPMTMR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxppmtmr_watchdogtmr_sel_locovr_attr == SERDES_IP_LANE_L3_CFG_RXPPMTMR_WATCHDOGTMR_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_cal_clear_delay_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_clk_chk_disable_attr == SERDES_IP_LANE_L3_CFG_RXRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_clk_delay_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_etr_on_delay_attr == 12'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_locovren_attr == SERDES_IP_LANE_L3_CFG_RXRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxreg_lev_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxreg_toggle_reset_on_rate_change_en_attr == SERDES_IP_LANE_L3_CFG_RXREG_TOGGLE_RESET_ON_RATE_CHANGE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxreg_vreg_bypass_attr == SERDES_IP_LANE_L3_CFG_RXREG_VREG_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_en_b_attr == SERDES_IP_LANE_L3_CFG_RXRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s0q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s0q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s2q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s2q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s2q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s2q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s2q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s2q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s2q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s3q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s3q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s3q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s3q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s3q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s3q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s3q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s3q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s4q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s4q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s5q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_entry2_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_entry4_attr == 13'd78
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_entry5_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_entry6_attr == 13'd1406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s0q2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s0q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s1q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s1q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s1q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s1q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s1q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s1q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s2q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s2q2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s2q3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s2q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s2q5_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s2q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s2q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s3q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s3q1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s3q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s3q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s3q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s3q5_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s3q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s3q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s4q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s4q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s5q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_aetrrx_cdrfbdivcken_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_AETRRX_CDRFBDIVCKEN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_aetrrx_cdrfbdivcken_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_AETRRX_CDRFBDIVCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_aetrrx_cdrmoddivcken_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_AETRRX_CDRMODDIVCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_aetrrx_cdrmoddivcken_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_AETRRX_CDRMODDIVCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_aetrrx_termhiz_en_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_AETRRX_TERMHIZ_EN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_aetrrx_termhiz_en_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_AETRRX_TERMHIZ_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_aetrsynth_pcspostdivclksel_ovr_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_AETRSYNTH_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_aetrsynth_pcspostdivclksel_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_AETRSYNTH_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_adc_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_adc_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_auxcomp_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_AUXCOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_auxcomp_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_AUXCOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_bias_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_bias_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_BIAS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_ctlecomp_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_CTLECOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_ctlecomp_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_CTLECOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_datfbdiv_b_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DATFBDIV_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_datfbdiv_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DATFBDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_dfe_bias_b_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DFE_BIAS_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_dfe_bias_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DFE_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_dfe_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DFE_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_dfe_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DFE_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_dfe_yadj_b_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DFE_YADJ_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_dfe_yadj_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DFE_YADJ_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_duty_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DUTY_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_duty_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DUTY_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_hifreqagc_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_HIFREQAGC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_hifreqagc_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_HIFREQAGC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_ntl_b_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_ntl_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_reg_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_reg_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_vco_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_VCO_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_vco_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_VCO_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_voscreg_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_VOSCREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_voscreg_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_VOSCREG_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_adc_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_adc_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_cdrfbdiv_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_CDRFBDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_cdrfbdiv_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_CDRFBDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_pdet_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_PDET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_pdet_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_PDET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_pfd_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_PFD_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_pfd_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_PFD_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_refdiv_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_refdiv_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_reg_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_reg_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_s2pa_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_S2PA_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_s2pa_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_S2PA_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_s2pb_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_S2PB_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_s2pb_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_S2PB_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_vco_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_VCO_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_vco_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_VCO_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_voscreg_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_VOSCREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_voscreg_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_VOSCREG_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstsynth_postdiv_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTSYNTH_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstsynth_postdiv_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTSYNTH_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_drstrx_dpif_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_DRSTRX_DPIF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_drstrx_dpif_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_DRSTRX_DPIF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_drstrx_ppm_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_DRSTRX_PPM_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_drstrx_ppm_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_DRSTRX_PPM_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_cdrlock2data_locovr_attr == SERDES_IP_LANE_L3_CFG_RXSIGDET_CDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_diglfpsdeten_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_diglfpsdeten_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_diglfpsdeten_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_diglfpsdeten_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_diglfpsdeten_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrancnten_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrancnten_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrancnten_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrancnten_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrancnten_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrancnten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrandeten_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrandeten_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrandeten_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrandeten_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrandeten_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrandeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_eiosdeten_muxd0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_eiosdeten_muxd1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_eiosdeten_muxd2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_eiosdeten_muxd3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_eiosdeten_muxd4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_eiosdeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_enable_attr == SERDES_IP_LANE_L3_CFG_RXSIGDET_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_fastlock_winsize_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_leveldeten_muxd0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_leveldeten_muxd1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_leveldeten_muxd2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_leveldeten_muxd3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_leveldeten_muxd4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_leveldeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_lfpsexit_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_locovren_attr == SERDES_IP_LANE_L3_CFG_RXSIGDET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_ppmdeten_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_ppmdeten_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_ppmdeten_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_ppmdeten_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_ppmdeten_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_ppmdeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_rxeq_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_rxeqen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_rxeqen_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_rxleveldet_debounce_dncount_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_rxleveldet_debounce_flush_en_attr == SERDES_IP_LANE_L3_CFG_RXSIGDET_RXLEVELDET_DEBOUNCE_FLUSH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_rxleveldet_debounce_upcount_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_sigdet_debounce_attr == SERDES_IP_LANE_L3_CFG_RXSIGDET_SIGDET_DEBOUNCE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_tmr_clksel_attr == SERDES_IP_LANE_L3_CFG_RXSIGDET_TMR_CLKSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_toggle_count_en_attr == SERDES_IP_LANE_L3_CFG_RXSIGDET_TOGGLE_COUNT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_toggle_count_pause_attr == SERDES_IP_LANE_L3_CFG_RXSIGDET_TOGGLE_COUNT_PAUSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_toggle_monitor_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdetin_eiosdetectstat_locovr_attr == SERDES_IP_LANE_L3_CFG_RXSIGDETIN_EIOSDETECTSTAT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdetin_locovren_attr == SERDES_IP_LANE_L3_CFG_RXSIGDETIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdetin_ovrcdrlock2data_locovr_attr == SERDES_IP_LANE_L3_CFG_RXSIGDETIN_OVRCDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdetin_ovrencdrlock2data_locovr_attr == SERDES_IP_LANE_L3_CFG_RXSIGDETIN_OVRENCDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdetout_lock2data_noforce_ltr_locovr_attr == SERDES_IP_LANE_L3_CFG_RXSIGDETOUT_LOCK2DATA_NOFORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsigdetout_locovren_attr == SERDES_IP_LANE_L3_CFG_RXSIGDETOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxspare0_attr == 32'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxspare_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsqlchlfps_consec_one_thresh_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsqlchlfps_consec_zero_thresh_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsqlchlfps_cycle_thresh_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsqlchlfps_dat_bitorder_attr == SERDES_IP_LANE_L3_CFG_RXSQLCHLFPS_DAT_BITORDER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsqlchlfps_debounce_type_attr == SERDES_IP_LANE_L3_CFG_RXSQLCHLFPS_DEBOUNCE_TYPE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsqlchlfps_one_run_length_thresh_attr == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsqlchlfps_one_run_length_timeout_attr == 8'd103
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsqlchlfps_zero_run_length_thresh_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsqlchlfps_zero_run_length_timeout_attr == 8'd103
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsynthdiv_slowmed_en_muxd0_attr == SERDES_IP_LANE_L3_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsynthdiv_slowmed_en_muxd1_attr == SERDES_IP_LANE_L3_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsynthdiv_slowmed_en_muxd2_attr == SERDES_IP_LANE_L3_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsynthdiv_slowmed_en_muxd3_attr == SERDES_IP_LANE_L3_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxsynthdiv_slowmed_en_muxd4_attr == SERDES_IP_LANE_L3_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxterm_cal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxterm_coarse_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxterm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXTERM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxterm_modeselect_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxtermhiz_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXTERMHIZ_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxtermhiz_locovren_attr == SERDES_IP_LANE_L3_CFG_RXTERMHIZ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxvoscreg_bypass_vosc_attr == SERDES_IP_LANE_L3_CFG_RXVOSCREG_BYPASS_VOSC_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxvoscregopampoffsetctrl_sel_attr == SERDES_IP_LANE_L3_CFG_RXVOSCREGOPAMPOFFSETCTRL_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxvoscregopampoffseterr_locovren_attr == SERDES_IP_LANE_L3_CFG_RXVOSCREGOPAMPOFFSETERR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxvoscregopampoffseterr_sel_locovr_attr == SERDES_IP_LANE_L3_CFG_RXVOSCREGOPAMPOFFSETERR_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxvoscregvref_locovren_attr == SERDES_IP_LANE_L3_CFG_RXVOSCREGVREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_rxvoscregvref_sel_locovr_attr == SERDES_IP_LANE_L3_CFG_RXVOSCREGVREF_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlch_acqgain_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlch_acqtime_attr == 13'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlch_cal_quiet_locovr_attr == SERDES_IP_LANE_L3_CFG_SQLCH_CAL_QUIET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlch_cal_sel_locovr_attr == SERDES_IP_LANE_L3_CFG_SQLCH_CAL_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlch_calctrl_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlch_calen_locovr_attr == SERDES_IP_LANE_L3_CFG_SQLCH_CALEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlch_caltimer_attr == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlch_clkgate_locovr_attr == SERDES_IP_LANE_L3_CFG_SQLCH_CLKGATE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlch_cmshiften_attr == SERDES_IP_LANE_L3_CFG_SQLCH_CMSHIFTEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_acq_gain_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_acq_pct_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_cal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_clr_errlog_attr == SERDES_IP_LANE_L3_CFG_SQLCH_CONT_CLR_ERRLOG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_controller_mode_attr == SERDES_IP_LANE_L3_CFG_SQLCH_CONT_CONTROLLER_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_dis_attr == SERDES_IP_LANE_L3_CFG_SQLCH_CONT_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_pause_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_postcal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_precal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_quiet_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlch_lfps_en_attr == SERDES_IP_LANE_L3_CFG_SQLCH_LFPS_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlch_locovren_attr == SERDES_IP_LANE_L3_CFG_SQLCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlch_ovrd_val_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlch_pkdet_freqsel_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlch_polarity_attr == SERDES_IP_LANE_L3_CFG_SQLCH_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlch_rdacen_attr == SERDES_IP_LANE_L3_CFG_SQLCH_RDACEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlch_thresh_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlch_time_out_attr == 16'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlch_vrefsel0_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlch_vrefsel1_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlch_vrefsel_ovr_en_attr == SERDES_IP_LANE_L3_CFG_SQLCH_VREFSEL_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlchdeb_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlchdeb_deb_cnt_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlchdeb_deb_status_cnt_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlchdeb_en_attr == SERDES_IP_LANE_L3_CFG_SQLCHDEB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlchdeb_ign_cnt_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlchdeb_sigdet_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlchdeb_thresh_cnt_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlchdebout_exit_good_debounced_locovr_attr == SERDES_IP_LANE_L3_CFG_SQLCHDEBOUT_EXIT_GOOD_DEBOUNCED_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlchdebout_exit_good_debounced_status_locovr_attr == SERDES_IP_LANE_L3_CFG_SQLCHDEBOUT_EXIT_GOOD_DEBOUNCED_STATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlchdebout_exit_good_locovr_attr == SERDES_IP_LANE_L3_CFG_SQLCHDEBOUT_EXIT_GOOD_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_sqlchdebout_locovren_attr == SERDES_IP_LANE_L3_CFG_SQLCHDEBOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_trancnt_off_attr == 10'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_trancnt_on_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_trancntout_det_locovr_attr == SERDES_IP_LANE_L3_CFG_TRANCNTOUT_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_trancntout_locovren_attr == SERDES_IP_LANE_L3_CFG_TRANCNTOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_trandet_ax_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_trandet_ay_attr == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_trandet_off_h_attr == 6'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_trandet_off_l_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_trandet_on_h_attr == 6'd39
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_trandet_on_l_attr == 6'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_trandetout_det_locovr_attr == SERDES_IP_LANE_L3_CFG_TRANDETOUT_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_trandetout_locovren_attr == SERDES_IP_LANE_L3_CFG_TRANDETOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_tx2rxlb_en_attr == SERDES_IP_LANE_L3_CFG_TX2RXLB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_tx2rxlb_init_offset_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_tx_cmn_on_state_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_tx_fastregpwrup_en_attr == SERDES_IP_LANE_L3_CFG_TX_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_tx_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_tx_pg_disable_attr == SERDES_IP_LANE_L3_CFG_TX_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_tx_synth_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_tx_synth_sel_amode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_tx_synth_sel_bmode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_tx_synth_sel_cmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_tx_synth_sel_dmode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_tx_synth_sel_emode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_tx_txdetrx_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txadc_req_attr == SERDES_IP_LANE_L3_CFG_TXADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txaprobe_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txaprobe_lastmux_isolate_attr == SERDES_IP_LANE_L3_CFG_TXAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txaprobeadc_current_direction_attr == SERDES_IP_LANE_L3_CFG_TXAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txaprobeadc_resistor_enable_attr == SERDES_IP_LANE_L3_CFG_TXAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txbdvdr_pma2pcstxworden_attr == SERDES_IP_LANE_L3_CFG_TXBDVDR_PMA2PCSTXWORDEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txbeacon_div_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txbeacon_sel_attr == SERDES_IP_LANE_L3_CFG_TXBEACON_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txbias_icc20uadj_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txbias_icc80uadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txbias_locovren_attr == SERDES_IP_LANE_L3_CFG_TXBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txbias_termcal_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txbist_biterror_en_attr == SERDES_IP_LANE_L3_CFG_TXBIST_BITERROR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txbist_locovren_attr == SERDES_IP_LANE_L3_CFG_TXBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txbist_modesel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txbist_oobmode_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txbist_oobtburst_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txbist_oobtcomrstinit_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txbist_oobtcomsas_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txbist_oobtcomwake_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txbist_seed_attr == 31'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_size_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf00_attr == 32'd1985229328
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf01_attr == 32'd4275878552
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf02_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf03_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf04_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf05_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf06_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf07_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf08_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf09_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txbit_select_muxd0_attr == SERDES_IP_LANE_L3_CFG_TXBIT_SELECT_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txbit_select_muxd1_attr == SERDES_IP_LANE_L3_CFG_TXBIT_SELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txbit_select_muxd2_attr == SERDES_IP_LANE_L3_CFG_TXBIT_SELECT_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txbit_select_muxd3_attr == SERDES_IP_LANE_L3_CFG_TXBIT_SELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txbit_select_muxd4_attr == SERDES_IP_LANE_L3_CFG_TXBIT_SELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txbti_data_replication_attr == SERDES_IP_LANE_L3_CFG_TXBTI_DATA_REPLICATION_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txbti_tx_idle_data_en_attr == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcal_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcal_tclkduty_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalduty_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalduty_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTY_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalduty_sel_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutybg_abort_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutybg_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutybg_ready_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutycomp_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutycomp_offset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_finish_side_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_init_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_initval_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_invert_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_req_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_round_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_runcount_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_signmagen_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsmout_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsmout_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompmeas_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompmeas_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompmeas_req_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompmeasout_ack_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPMEASOUT_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompmeasout_erravg_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPMEASOUT_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompmeasout_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_bg_en_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_bg_one_step_cal_en_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_finish_side_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_init_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_invert_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_req_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_round_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_runcount_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_signmagen_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeas_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeas_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeas_req_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeasout_ack_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYMEASOUT_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeasout_erravg_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYMEASOUT_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeasout_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutystat_done_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaldutystat_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalptr_pstate_duty_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalptr_pstate_dutycomp_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalptr_pstate_regopampoffset_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_duty_muxd0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_duty_muxd1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_duty_muxd2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_duty_muxd3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_duty_muxd4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_dutycomp_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_dutycomp_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_dutycomp_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_dutycomp_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_dutycomp_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_regopampoffset_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffset_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_finish_side_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_round_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_runcount_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_signmagen_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcaltclkdutyforce_div1_attr == SERDES_IP_LANE_L3_CFG_TXCALTCLKDUTYFORCE_DIV1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txcdrdiv_local_en_attr == SERDES_IP_LANE_L3_CFG_TXCDRDIV_LOCAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txclk_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txclk_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txclkgenmuxsel_txinternal_attr == SERDES_IP_LANE_L3_CFG_TXCLKGENMUXSEL_TXINTERNAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txdetectrx_thr_attr == 5'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeas_count_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeas_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXDETECTRXMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeas_locovren_attr == SERDES_IP_LANE_L3_CFG_TXDETECTRXMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeas_validdlycount_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeasin_locovren_attr == SERDES_IP_LANE_L3_CFG_TXDETECTRXMEASIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeasin_start_locovr_attr == SERDES_IP_LANE_L3_CFG_TXDETECTRXMEASIN_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeaspcs_locovren_attr == SERDES_IP_LANE_L3_CFG_TXDETECTRXMEASPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeaspcs_req_locovr_attr == SERDES_IP_LANE_L3_CFG_TXDETECTRXMEASPCS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeasval_locovren_attr == SERDES_IP_LANE_L3_CFG_TXDETECTRXMEASVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeasval_stat_locovr_attr == SERDES_IP_LANE_L3_CFG_TXDETECTRXMEASVAL_STAT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txdetrx_levn_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txdetrx_levnm1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txdetrx_levnp1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txdetrx_levnp2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txdrv_hizen_locovr_attr == SERDES_IP_LANE_L3_CFG_TXDRV_HIZEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txdrv_levn_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txdrv_levnm1_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txdrv_levnp1_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txdrv_levnp2_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txdrv_locovren_attr == SERDES_IP_LANE_L3_CFG_TXDRV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txdrv_refcken_attr == SERDES_IP_LANE_L3_CFG_TXDRV_REFCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txdrv_termref_attr == SERDES_IP_LANE_L3_CFG_TXDRV_TERMREF_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txdrvmute_locovr_attr == SERDES_IP_LANE_L3_CFG_TXDRVMUTE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txdrvmute_locovren_attr == SERDES_IP_LANE_L3_CFG_TXDRVMUTE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txduty_ctrl_disable_attr == SERDES_IP_LANE_L3_CFG_TXDUTY_CTRL_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txduty_pad_sense_en_attr == SERDES_IP_LANE_L3_CFG_TXDUTY_PAD_SENSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txdutycal_div16_en_attr == SERDES_IP_LANE_L3_CFG_TXDUTYCAL_DIV16_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txdutycal_div1_en_attr == SERDES_IP_LANE_L3_CFG_TXDUTYCAL_DIV1_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txdutycal_div2_en_attr == SERDES_IP_LANE_L3_CFG_TXDUTYCAL_DIV2_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txdutycal_div4_en_attr == SERDES_IP_LANE_L3_CFG_TXDUTYCAL_DIV4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txdutycal_div8_en_attr == SERDES_IP_LANE_L3_CFG_TXDUTYCAL_DIV8_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txfifo_elecidle_deskew_en_attr == SERDES_IP_LANE_L3_CFG_TXFIFO_ELECIDLE_DESKEW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txfifo_force_txidlebit1_zero_disable_attr == SERDES_IP_LANE_L3_CFG_TXFIFO_FORCE_TXIDLEBIT1_ZERO_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txfifo_kill_dly_10b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txfifo_kill_dly_16b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txfifo_kill_dly_20b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txfifo_kill_dly_32b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txfifo_kill_dly_40b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txfifo_kill_dly_64b_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txfifo_kill_dly_80b_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txfifo_kill_dly_8b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txfifo_kill_en_attr == SERDES_IP_LANE_L3_CFG_TXFIFO_KILL_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txfsm_cken_ovr_attr == SERDES_IP_LANE_L3_CFG_TXFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txfsm_cken_ovren_attr == SERDES_IP_LANE_L3_CFG_TXFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txfsm_main_on_state_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txl1d1_doze_ctrl_attr == SERDES_IP_LANE_L3_CFG_TXL1D1_DOZE_CTRL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txl1d1_txbias_ctrl_attr == SERDES_IP_LANE_L3_CFG_TXL1D1_TXBIAS_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txlanepam_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXLANEPAM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txlanepam_locovren_attr == SERDES_IP_LANE_L3_CFG_TXLANEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txmeaslatovrhd_meas_sel_attr == SERDES_IP_LANE_L3_CFG_TXMEASLATOVRHD_MEAS_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txmute_delay_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txntl_changeref_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txntl_changeref_val_locovr_attr == SERDES_IP_LANE_L3_CFG_TXNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txntl_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txntl_en_attr == SERDES_IP_LANE_L3_CFG_TXNTL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txntl_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txntl_locovren_attr == SERDES_IP_LANE_L3_CFG_TXNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txntl_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txntl_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txntl_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txntl_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txntl_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txntl_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txntl_txm_charge_up_locovr_attr == SERDES_IP_LANE_L3_CFG_TXNTL_TXM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txntl_txm_pull_dn_locovr_attr == SERDES_IP_LANE_L3_CFG_TXNTL_TXM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txntl_txm_sense_locovr_attr == SERDES_IP_LANE_L3_CFG_TXNTL_TXM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txntl_txp_charge_up_locovr_attr == SERDES_IP_LANE_L3_CFG_TXNTL_TXP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txntl_txp_pull_dn_locovr_attr == SERDES_IP_LANE_L3_CFG_TXNTL_TXP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txntl_txp_sense_locovr_attr == SERDES_IP_LANE_L3_CFG_TXNTL_TXP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txp2s_txwordsyncbypen_attr == SERDES_IP_LANE_L3_CFG_TXP2S_TXWORDSYNCBYPEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txpam_bitorder_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txpam_gray_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXPAM_GRAY_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txpam_locovren_attr == SERDES_IP_LANE_L3_CFG_TXPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txpam_precode_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXPAM_PRECODE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txpcs_locovren_attr == SERDES_IP_LANE_L3_CFG_TXPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txpcs_txenable_locovr_attr == SERDES_IP_LANE_L3_CFG_TXPCS_TXENABLE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txpcsbist_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXPCSBIST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txpcsbist_locovren_attr == SERDES_IP_LANE_L3_CFG_TXPCSBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txratewidth_clk_chk_disable_attr == SERDES_IP_LANE_L3_CFG_TXRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txratewidth_etr_on_delay_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txratewidth_locovren_attr == SERDES_IP_LANE_L3_CFG_TXRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txreg_toggle_pwrupacc_on_rate_change_en_attr == SERDES_IP_LANE_L3_CFG_TXREG_TOGGLE_PWRUPACC_ON_RATE_CHANGE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txreg_toggle_reset_on_rate_change_en_attr == SERDES_IP_LANE_L3_CFG_TXREG_TOGGLE_RESET_ON_RATE_CHANGE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txresetdel_sel_attr == SERDES_IP_LANE_L3_CFG_TXRESETDEL_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_en_b_attr == SERDES_IP_LANE_L3_CFG_TXRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s0q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s0q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s1q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s1q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s2q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s2q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s2q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s2q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s2q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s2q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s2q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s3q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s3q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s3q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s3q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s3q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s3q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s3q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s3q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s4q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s4q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s5q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_entry2_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s0q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s0q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s1q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s1q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s1q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s1q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s1q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s1q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s2q0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s2q1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s2q2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s2q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s2q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s2q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s2q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s2q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s3q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s3q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s3q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s3q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s3q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s3q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s3q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s3q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s4q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s4q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s5q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_dn_ptr0_s_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_up_ptr0_s_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_aetrtx_bitckdvdrcken_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_AETRTX_BITCKDVDRCKEN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_aetrtx_bitckdvdrcken_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_AETRTX_BITCKDVDRCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_aetrtx_regpwrupacc_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_AETRTX_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_aetrtx_regpwrupacc_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_AETRTX_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_adc_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_adc_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_drvdoze_b_ovr_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_DRVDOZE_B_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_drvdoze_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_DRVDOZE_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_duty_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_DUTY_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_duty_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_DUTY_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_ntl_b_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_ntl_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_p2s_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_P2S_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_p2s_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_P2S_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_reg_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_reg_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_arsttx_adc_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_ARSTTX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_arsttx_adc_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_ARSTTX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_arsttx_pma2pcstxword_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_ARSTTX_PMA2PCSTXWORD_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_arsttx_pma2pcstxword_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_ARSTTX_PMA2PCSTXWORD_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_arsttx_regreset_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_ARSTTX_REGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_arsttx_regreset_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_ARSTTX_REGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_arsttx_txdetectrx_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_ARSTTX_TXDETECTRX_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_arsttx_txdetectrx_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_ARSTTX_TXDETECTRX_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txrststate_hiz_en_attr == SERDES_IP_LANE_L3_CFG_TXRSTSTATE_HIZ_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txspare0_attr == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txspare_attr == 10'd384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txterm_coarse_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txtermtrim_locovren_attr == SERDES_IP_LANE_L3_CFG_TXTERMTRIM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txtermtrim_nmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txtermtrim_pmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txwclk_div_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txwclk_div_en_attr == SERDES_IP_LANE_L3_CFG_TXWCLK_DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txwclk_div_smpl_attr == SERDES_IP_LANE_L3_CFG_TXWCLK_DIV_SMPL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txwptr_init01_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txwptr_init02_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txwptr_init04_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txwptr_init08_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txwptr_init16_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txwptr_init32_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_l3_cfg_txwptr_init_rx2txparlb_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_dfeyadj_aging_cdrlock2data_loc_ov_attr == SERDES_IP_LANE_RXEQ_L0_CFG_DFEYADJ_AGING_CDRLOCK2DATA_LOC_OV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_dfeyadj_aging_cdrlock2data_loc_ov_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_DFEYADJ_AGING_CDRLOCK2DATA_LOC_OV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_dfeyadj_aging_div_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_dfeyadj_aging_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_DFEYADJ_AGING_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxagc_ctlecomp_filterbypass_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXAGC_CTLECOMP_FILTERBYPASS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxagc_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXAGC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxbgcal_calfsmmeas_dlycount_attr == 10'd392
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxbgcal_clear_mask_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxbgcal_fsmmaxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxbgcal_lpfax_coarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxbgcal_lpfax_fine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxbgcalorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxbgcalorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxbgcalorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_calbiasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_calbiasboost_use_lut_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_CALBIASBOOST_USE_LUT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_callbbiasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_callbbiasboost_use_lut_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_CALLBBIASBOOST_USE_LUT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlecomp_filterbypass_smplrcal_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_CTLECOMP_FILTERBYPASS_SMPLRCAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg1_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg2_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg3_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctleinput_probe_mux_smplrcal_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg1_probe_mux_en_smplrcal_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg1_state_en_smplrcal_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg1_state_en_tfrcal_stg1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg1_state_en_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg1_state_en_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg1_use_stg2code_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_CTLESTG1_USE_STG2CODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg2_probe_mux_en_smplrcal_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg2_state_en_smplrcal_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg2_state_en_tfrcal_stg1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg2_state_en_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg2_state_en_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg3_probe_mux_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg3_state_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg3_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg3_state_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg3_state_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_hifreqagc_n5targin_sel_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_HIFREQAGC_N5TARGIN_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_inputcmadjust_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_inputcmadjust_stg1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_inputcmadjust_stg2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_inputcmadjust_stg3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_sdimode_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_SDIMODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_smplroffset_aux0_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_smplroffset_aux1_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_smplroffset_d0_bot_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_smplroffset_d0_mid_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_smplroffset_d0_top_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_smplroffset_d1_bot_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_smplroffset_d1_mid_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_smplroffset_d1_top_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_tfrtrim_outen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_tfrtrim_outen_tfrcal_stg1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_tfrtrim_outen_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_tfrtrim_outen_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalalign_iqclk_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalalign_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALALIGN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctl_cal_abort_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALCTL_CAL_ABORT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctl_cal_type_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctl_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALCTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctl_post_delay_pow2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctl_pre_delay_pow2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecalctrl_input_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecalctrl_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALCTLECALCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecalctrl_stg1_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecalctrl_stg1_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecalctrl_stg2_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecalctrl_stg2_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecalctrl_stg3_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecalctrl_stg3_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecompoffset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecompoffset_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALCTLECOMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecompoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALCTLECOMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecompoffsetfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALCTLECOMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecompoffsetfsmout_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaldutybkgnd_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALDUTYBKGND_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaldutybkgnd_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALDUTYBKGND_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_biasboost_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_hf1deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_hf1resdcgain_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_hf2cap_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_hf2deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_hf2reszero_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_hf3deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_hf3resdcgain_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_hf4deq_gray_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALEQ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_ctlecmnmode_stg1_finish_side_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALFSM_CTLECMNMODE_STG1_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_ctlecmnmode_stg1_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_ctlecmnmode_stg2_finish_side_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALFSM_CTLECMNMODE_STG2_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_ctlecmnmode_stg2_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_ctlecmnmode_stg3_finish_side_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALFSM_CTLECMNMODE_STG3_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_ctlecmnmode_stg3_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_runcount_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_smplroffset_finish_side_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALFSM_SMPLROFFSET_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_smplroffset_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsmmeas_ctlecmnmode_stg1_invert_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALFSMMEAS_CTLECMNMODE_STG1_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsmmeas_ctlecmnmode_stg2_invert_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALFSMMEAS_CTLECMNMODE_STG2_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsmmeas_ctlecmnmode_stg3_invert_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALFSMMEAS_CTLECMNMODE_STG3_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsmmeas_smplroffset_invert_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALFSMMEAS_SMPLROFFSET_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_ctlecmnmode_stg1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_ctlecmnmode_stg2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_ctlecmnmode_stg3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_aux0_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_aux1_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_d0_bot_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_d0_mid_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_d0_top_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_d1_bot_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_d1_mid_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_d1_top_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_e0_lo_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_e1_lo_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeas_pow2count_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasin_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasin_req_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASIN_REQ_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasin_req_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASIN_REQ_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasin_req_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASIN_REQ_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasout_ack_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASOUT_ACK_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasout_ack_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASOUT_ACK_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasout_ack_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASOUT_ACK_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasout_avg_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASOUT_AVG_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasout_avg_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASOUT_AVG_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasout_avg_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASOUT_AVG_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasout_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaloffsetfsmout_auxdatacomp_offset_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALOFFSETFSMOUT_AUXDATACOMP_OFFSET_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaloffsetfsmout_boost_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALOFFSETFSMOUT_BOOST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaloffsetfsmout_edgecomp_offset_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALOFFSETFSMOUT_EDGECOMP_OFFSET_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaloffsetfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalset_cal_clear_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalset_cal_mode_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALSET_CAL_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalset_cal_req_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALSET_CAL_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalset_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalstat_cal_ack_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALSTAT_CAL_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalstat_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalsummerfsmout_comp_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALSUMMERFSMOUT_COMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalsummerfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALSUMMERFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcdrphd_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCDRPHD_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcdrphd_override_ignore_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCDRPHD_OVERRIDE_IGNORE_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_caloffset_range_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_calstg1offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_calstg1offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_calstg2offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_calstg2offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_calstg3offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_calstg3offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_dccouple_sigpath_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCTLE_DCCOUPLE_SIGPATH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_lbbiasboost_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCTLE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_stg1tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_stg2tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_stg3tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_tfrtrim_outmem_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCTLE_TFRTRIM_OUTMEM_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_tfrtrim_outpen_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCTLE_TFRTRIM_OUTPEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctledc_dccouple_tgate_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCTLEDC_DCCOUPLE_TGATE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctledc_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCTLEDC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxdfe_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXDFE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxdfe_tapgain_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxdfepam_enable_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXDFEPAM_ENABLE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxdfepam_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXDFEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxdpifjit_enb_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXDPIFJIT_ENB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxdpifjit_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXDPIFJIT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxdpifjit_offset_locovr_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqadj_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQADJ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqadj_yadjust_aux0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqadj_yadjust_aux1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqadj_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqadj_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqadj_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqadj_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqadj_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqadj_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqauxxor_amux_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqauxxor_dmux_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqauxxor_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQAUXXOR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcal2flx_pstate_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCAL2FLX_PSTATE_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcal2flx_rate_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCAL2FLX_RATE_MASK_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_16a_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_16b_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_16c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_16d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_16e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_1a_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_1b_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_1c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_1d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_1e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_2a_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_2b_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_2c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_2d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_2e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_4a_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_4b_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_4c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_4d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_4e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_8a_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_8b_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_8c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_8d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_8e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_16a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_16b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_16c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_16d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_16e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_1a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_1b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_1c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_1d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_1e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_2a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_2b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_2c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_2d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_2e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_4a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_4b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_4c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_4d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_4e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_8a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_8b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_8c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_8d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_8e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_16a_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_16b_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_16c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_16d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_16e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_1a_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_1b_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_1c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_1d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_1e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_2a_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_2b_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_2c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_2d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_2e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_4a_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_4b_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_4c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_4d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_4e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_8a_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_8b_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_8c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_8d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_8e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcals_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCALS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcals_offset_datasummer0_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcals_offset_datasummer0_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcals_offset_datasummer1_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcals_offset_datasummer1_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcals_offset_edgesummer0_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcals_offset_edgesummer0_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcals_offset_edgesummer1_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcals_offset_edgesummer1_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcdr_force_ltr_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCDR_FORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcdr_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCDR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqctl_clear_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCTL_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqctl_fg_run_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCTL_FG_RUN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqctlelut_hifreqagcres_ovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCTLELUT_HIFREQAGCRES_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqctlelut_hifreqvgagain_ovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCTLELUT_HIFREQVGAGAIN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqctls_oddeven_tapgain_sel_inv_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCTLS_ODDEVEN_TAPGAIN_SEL_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqctls_static_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCTLS_STATIC_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqdat_aux_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQDAT_AUX_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqdat_edge_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQDAT_EDGE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqdatactl_auxswap_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqdatactl_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQDATACTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqdatarate_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQDATARATE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqdatarate_rx_rate_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqdfeyadj_agingl2r_delay_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqdfeyadj_agingl2r_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQDFEYADJ_AGINGL2R_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqedgeadj_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEDGEADJ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqedgeadj_yadjust_edge0lo_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqedgeadj_yadjust_edge1lo_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm2flx_ehm_done_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHM2FLX_EHM_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm2flx_ehm_done_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHM2FLX_EHM_DONE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm2flx_ehm_err_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHM2FLX_EHM_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm2flx_ehm_err_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHM2FLX_EHM_ERR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm2flx_ehm_fom_locovr_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHM2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_data_extshift_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHM_DATA_EXTSHIFT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_distance_th_50p_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_distance_th_rate_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_err_mask_vf00_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_err_mask_vf01_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_event_rate_vf00_attr == 32'd67108864
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_event_rate_vf01_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_general_in_vf00_attr == 32'd5521424
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_general_in_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_lms_th_50p_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_lms_th_rate_attr == 20'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_mask_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_no_change_th_50p_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_no_change_th_rate_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_reflections_num_50p_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_reflections_num_rate_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_slicer_swap_cb_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHM_SLICER_SWAP_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_sym_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_sym_dly_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_tap_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_test_aux_slicer_val_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_test_hits_th_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjaux_ehm_yadjust_aux0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjaux_ehm_yadjust_aux1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjaux_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJAUX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjauxen_ehm_aux_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJAUXEN_EHM_AUX_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjauxen_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJAUXEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjauxltch_aux_yadj_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJAUXLTCH_AUX_YADJ_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjauxltch_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJAUXLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdata_ehm_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdata_ehm_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdata_ehm_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdata_ehm_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdata_ehm_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdata_ehm_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdata_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdataen_ehm_data_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJDATAEN_EHM_DATA_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdataen_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJDATAEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdataltch_data_yadj_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJDATALTCH_DATA_YADJ_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdataltch_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJDATALTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2ehm_ehm_run_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2EHM_EHM_RUN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2ehm_ehm_run_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2EHM_EHM_RUN_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2lms_coarse_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2LMS_COARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2lms_ctrl_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2LMS_CTRL_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2lms_dfecore_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2LMS_DFECORE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2lms_force_evrefupd_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2LMS_FORCE_EVREFUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2lms_freeze_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2LMS_FREEZE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2lms_incr_decr_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2LMS_INCR_DECR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2lms_mu_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2LMS_MU_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2lms_rst_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2LMS_RST_OVRDEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2ofc_ofc_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2OFC_OFC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2ofc_ofc_en_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2OFC_OFC_EN_OVRDEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx_pcs_rxeq_clr_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX_PCS_RXEQ_CLR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx_pcs_rxeq_start_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX_PCS_RXEQ_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx_pcs_rxeq_static_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX_PCS_RXEQ_STATIC_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx_rxrate2pcie1_map_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx_rxrate2pcie2_map_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx_rxrate2pcie3_map_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx_rxrate2pcie4_map_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxehmdata_ehm_data_slc_sel_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXEHMDATA_EHM_DATA_SLC_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxehmdata_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXEHMDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxfsm_generalpurpose_reg_in_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxfsm_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXFSM_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxfsm_pause_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXFSM_PAUSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxfsm_state_obs_hold_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXFSM_STATE_OBS_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxfsm_state_obs_sel_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXFSM_STATE_OBS_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxltr_force_ltr_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXLTR_FORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxltr_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXLTR_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxpcsrxeyediag_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXPCSRXEYEDIAG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxpcsrxeyediag_start_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXPCSRXEYEDIAG_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxsigdet_sel_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXSIGDET_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqfsm2ofc_ofc_cal_req_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFSM2OFC_OFC_CAL_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqfsm2ofc_ofc_cal_req_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFSM2OFC_OFC_CAL_REQ_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_16a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_16b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_16c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_16d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_16e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_1a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_1b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_1c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_1d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_1e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_2a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_2b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_2c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_2d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_2e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_4a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_4b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_4c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_4d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_4e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_8a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_8b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_8c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_8d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_8e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_done_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmax_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmax_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_SATMAX_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmax_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmax_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmax_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_SATMAX_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmax_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_SATMAX_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmax_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_SATMAX_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmin_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmin_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_SATMIN_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmin_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmin_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmin_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_SATMIN_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmin_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_SATMIN_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmin_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_SATMIN_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_stable_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_stable_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_STABLE_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_stable_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_stable_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_stable_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_STABLE_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_stable_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_STABLE_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_stable_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_STABLE_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsupd_chng_ack_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSUPD_CHNG_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsupd_chng_req_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSUPD_CHNG_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsupd_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSUPD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjaux_lms_vref0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjaux_lms_vref1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjaux_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJAUX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjauxen_lms_aux_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJAUXEN_LMS_AUX_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjauxen_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJAUXEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjauxltch_lms_aux_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJAUXLTCH_LMS_AUX_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjauxltch_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJAUXLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdata_lms_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdata_lms_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdata_lms_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdata_lms_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdata_lms_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdata_lms_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdata_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdataen_lms_data_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJDATAEN_LMS_DATA_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdataen_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJDATAEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdataltch_lms_data_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJDATALTCH_LMS_DATA_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdataltch_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJDATALTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjedge_lms_yadjust_edge0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjedge_lms_yadjust_edge1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjedge_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJEDGE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjedgeen_lms_edge_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJEDGEEN_LMS_EDGE_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjedgeen_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJEDGEEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjedgeltch_lms_edge_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJEDGELTCH_LMS_EDGE_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjedgeltch_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJEDGELTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqltch_dfe_aux_yadj_b_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLTCH_DFE_AUX_YADJ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqltch_dfe_b_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLTCH_DFE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqltch_dfe_data_yadj_b_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLTCH_DFE_DATA_YADJ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqltch_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqltchc_auxswap_b_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLTCHC_AUXSWAP_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqltchc_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLTCHC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofc2flx_ofc_cal_done_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQOFC2FLX_OFC_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofc2flx_ofc_cal_done_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQOFC2FLX_OFC_CAL_DONE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_ctle_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_ctle_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_ctle_rxstg1probemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_ctle_rxstg2_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_ctle_rxstg2probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_ctle_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_ctle_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_summer_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_summer_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_summer_rxstg1probemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_summer_rxstg2_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_summer_rxstg2probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_summer_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_summer_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_time_h_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_time_l_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_ctle_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_ctle_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_ctle_rxstg1probemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_ctle_rxstg2_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_ctle_rxstg2probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_ctle_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_ctle_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_summer_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_summer_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_summer_rxstg1probemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_summer_rxstg2_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_summer_rxstg2probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_summer_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_summer_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_time_l_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_compsel_ctle_st1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_compsel_ctle_st2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_compsel_ctle_st3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_compsel_idle_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_compsel_sa_d0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_compsel_sa_d1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_compsel_sa_e0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_compsel_sa_e1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_invert_comp_fb_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_lpexitcal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_lpexitcal_time_l_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_adapt_en_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_adapt_thr_sel_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_cal_en_attr == 8'd249
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_cal_thr_sel_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_data_disp_sticky_clr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQOFCCFG_OFC_DATA_DISP_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_disparity_disable_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQOFCCFG_OFC_DISPARITY_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_disparity_leak_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_disparity_thr_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_lpexitcal_en_attr == 8'd249
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_lpf_bypass_en_cb_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQOFCCFG_OFC_LPF_BYPASS_EN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_ratechangecal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_pre_timer_setting_pow2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ratechangecal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ratechangecal_time_l_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_rxinpprobemuxen_idle_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_rxstg1_stateen_idle_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_rxstg1probemuxen_idle_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_rxstg2_stateen_idle_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_rxstg2probemuxen_idle_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_rxstg3_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_rxstg3probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqout_init_restore_avail_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQOUT_INIT_RESTORE_AVAIL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqprecal_code_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqprecal_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQPRECAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_hf1deq_dir_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_BOOSTLUT_HF1DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_hf2deq_dir_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_BOOSTLUT_HF2DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_hf2reszero_dir_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_BOOSTLUT_HF2RESZERO_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_hf3deq_dir_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_BOOSTLUT_HF3DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_idx_hf1deq_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_idx_hf1deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_idx_hf2deq_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_idx_hf2deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_idx_hf2reszero_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_idx_hf2reszero_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_idx_hf3deq_vf00_attr == 32'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_idx_hf3deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_init_hf1deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_init_hf2deq_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_init_hf2reszero_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_init_hf3deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_cal_hifreqagcres_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_cal_hifreqvgagain_attr == 7'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_cal_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_cal_yadjust_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_biasboost_dir_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_GAINLUT_BIASBOOST_DIR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_hf1resdcgain_dir_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_GAINLUT_HF1RESDCGAIN_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_hf3resdcgain_dir_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_GAINLUT_HF3RESDCGAIN_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_biasboost_vf00_attr == 32'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_biasboost_vf01_attr == 32'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_biasboost_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_lbbiasboost_vf00_attr == 32'd268435454
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_lbbiasboost_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_lbbiasboost_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_init_biasboost_attr == 5'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_init_hf1resdcgain_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_init_hf3resdcgain_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_init_lbbiasboost_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_lbbiasboost_dir_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_GAINLUT_LBBIASBOOST_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_latch_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref0_initval_attr == 9'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref1_initval_attr == 9'd191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref2_initval_attr == 9'd321
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref3_initval_attr == 9'd451
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_decr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_AUXVREF_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_frac_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_AUXVREF_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_frac_reset_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_incr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_AUXVREF_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_incr_decr_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_pam4adj_swizzle_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_AUXVREF_PAM4ADJ_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_AUXVREF_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_pol_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_single_step_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_AUXVREF_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_stable_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_AUXVREF_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_AUXVREF_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_targ_0_hi_attr == 9'd160
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_targ_0_lo_attr == 9'd140
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_auxvref_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_auxvref_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_dfe_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_dfe_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_edge_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_edge_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_edgevref_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_edgevref_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_iqalign_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_iqalign_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_level_vga_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_vga_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_vga_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_blockcount_fast_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_BLOCKCOUNT_FAST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_coarse_detect_clear_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_COARSE_DETECT_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_coarse_detect_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_COARSE_DETECT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_continuous_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_CONTINUOUS_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_datastats_incr_decr_swizzle_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_DATASTATS_INCR_DECR_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_datastats_pol_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_DATASTATS_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_datastats_thres_attr == 16'd1023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe1_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe2_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe3_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe4p_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_core_sel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_decr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_DFE_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_frac_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_DFE_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_frac_reset_mask_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_incr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_DFE_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_incr_decr_mask_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_inner_lvl_filter_en_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_DFE_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_pol_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_single_step_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_DFE_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_stable_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_DFE_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_DFE_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_targtap1_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_targtap2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_targtap3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_targtap4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_decr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGE_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_frac_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGE_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_frac_reset_mask_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_incr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGE_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_incr_decr_mask_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGE_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_pol_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_single_step_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGE_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_stable_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGE_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGE_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_decr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGEVREF_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_frac_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGEVREF_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGEVREF_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_incr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGEVREF_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_initval_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGEVREF_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_pol_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGEVREF_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_single_step_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGEVREF_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_stable_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGEVREF_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGEVREF_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_fast_blockcnt_attr == 16'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_filter_mode_auxvref_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_filter_mode_dfe_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_filter_mode_edge_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_filter_mode_edgevref_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_filter_mode_iqalign_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_filter_mode_vga_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_freeze_auxvrefupd_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_freeze_dfeupd_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_freeze_edgeupd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_freeze_edgevrefupd_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_FREEZE_EDGEVREFUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_freeze_forcebg_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_FREEZE_FORCEBG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_freeze_hifreqagcupd_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_FREEZE_HIFREQAGCUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_freeze_iqalignupd_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_FREEZE_IQALIGNUPD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_freeze_lofreqagcupd_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_FREEZE_LOFREQAGCUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_freeze_vgaupd_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_FREEZE_VGAUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_gated_update_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_GATED_UPDATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_accum_count_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_accum_level_en_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_decr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_HIFREQAGC_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_frac_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_HIFREQAGC_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_HIFREQAGC_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_incr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_HIFREQAGC_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_n1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_n2_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_n3_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_n4_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_n5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_HIFREQAGC_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_pol_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_HIFREQAGC_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_single_step_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_HIFREQAGC_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_stable_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_HIFREQAGC_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_HIFREQAGC_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_init_adapt_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_INIT_ADAPT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_decr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_IQALIGN_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_frac_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_IQALIGN_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_IQALIGN_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_incr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_IQALIGN_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_IQALIGN_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_pol_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_IQALIGN_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_single_step_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_IQALIGN_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_stable_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_IQALIGN_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_IQALIGN_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_targ_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_itercount_attr == 10'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_latch_delay_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_latch_prepost_delay_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_decr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOFREQAGC_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_frac_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOFREQAGC_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOFREQAGC_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_incr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOFREQAGC_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOFREQAGC_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_pol_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOFREQAGC_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_single_step_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOFREQAGC_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_stable_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOFREQAGC_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOFREQAGC_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_logain_auxvref_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOGAIN_AUXVREF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_logain_dfe_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_logain_edge_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_logain_edgevref_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOGAIN_EDGEVREF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_logain_hifreqagc_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOGAIN_HIFREQAGC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_logain_iqalign_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOGAIN_IQALIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_logain_lofreqagc_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOGAIN_LOFREQAGC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_logain_vga_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOGAIN_VGA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_auxvref_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_dfe1_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_dfe23_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_dfe4p_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_edge2_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_edge3_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_edge4_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_edgevref_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_hifreqagc_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_iqalign_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_lofreqagc_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_vga_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_nrz_to_pam4_mode_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_NRZ_TO_PAM4_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_slow_blockcnt_attr == 16'd96
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_start_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_tsettle_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_accum_count_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_accum_level_en_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_decr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_frac_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_incr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_mode_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_pol_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_single_step_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_stable_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_yadjdata_mid_clamp_zero_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_YADJDATA_MID_CLAMP_ZERO_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lofreqagcgain_sel_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LOFREQAGCGAIN_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_caldfedatatap1gain_attr == 6'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_caldfedatatap2gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_caldfedatatap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_caldfedatatap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_caldfeedgetap2gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_caldfeedgetap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_caldfeedgetap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_hifreqagcres_attr == 6'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_hifreqvgagain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_caldfedatatap1gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_caldfedatatap1gain_attr == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_caldfedatatap1gain_attr == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_shift_auxshft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_shift_capture_trigger_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_SHIFT_CAPTURE_TRIGGER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_shift_clear_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_SHIFT_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_shift_dat_bitsel_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_SHIFT_DAT_BITSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_shift_datashft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_shift_edgeshft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_shift_edgeshft_nrz8b10b_pam16b20b_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_shift_polarity_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_SHIFT_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap10gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap11gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap12gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap13gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap14gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap15gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap16gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap1gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap2gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap5gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap6gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap7gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap8gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap9gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfeedgetap2gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfeedgetap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfeedgetap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_hifreqvgagain_attr == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_auxvref0_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_auxvref1_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_auxvref2_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_auxvref3_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_caldfedatatap1gain_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_caldfeedgetap2gain_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_calhifreqagcres_attr == 6'd38
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_callofreqagcgain_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_edgevref_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_hifreqvgagain_attr == 7'd45
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_iqalign_attr == 6'd45
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_auxvref0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_auxvref1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_auxvref2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_auxvref3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_caldfedatatap1gain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_caldfeedgetap2gain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_calhifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_callofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_edgevref_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_iqalign_attr == 6'd21
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqsetnrztopam4_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSETNRZTOPAM4_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqsetnrztopam4_switch_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSETNRZTOPAM4_SWITCH_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqsigdet_pause_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSIGDET_PAUSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqspare0_attr == 32'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqspare1_attr == 32'd15871
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqspare2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqsync2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSYNC2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqsync2flx_rxdatapath_ready_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSYNC2FLX_RXDATAPATH_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqtapctrl_data_tap13to16_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQTAPCTRL_DATA_TAP13TO16_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqtapctrl_data_tap1to4_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQTAPCTRL_DATA_TAP1TO4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqtapctrl_data_tap5to8_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQTAPCTRL_DATA_TAP5TO8_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqtapctrl_data_tap9to12_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQTAPCTRL_DATA_TAP9TO12_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqtapctrl_edge_tap_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQTAPCTRL_EDGE_TAP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqtapctrl_tap1to4gain_dbl_res_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQTAPCTRL_TAP1TO4GAIN_DBL_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqtapctrl_tap5to16gain_dbl_res_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQTAPCTRL_TAP5TO16GAIN_DBL_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvalc_hifreqagcbiasadjust_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvalc_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQVALC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvalc_midbandzero_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvalcl_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQVALCL_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvalcl_lofreqagcgain_locovr_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap01gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap02gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap03gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap04gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap05gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap06gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap07gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap08gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap09gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap10gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap11gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap12gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap13gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap14gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap15gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap16gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQVALD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvale_caldfeedgetap02gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvale_caldfeedgetap03gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvale_caldfeedgetap04gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvale_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQVALE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1cal_clear_mask_attr == 13'd8184
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_aux0_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_aux1_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_d0_bot_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_d0_mid_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_d0_top_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_d1_bot_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_d1_mid_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_d1_top_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_e0_lo_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_e1_lo_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2cal_clear_mask_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_aux0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_aux1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_d0_bot_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_d0_mid_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_d0_top_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_d1_bot_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_d1_mid_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_d1_top_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_e0_lo_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_e1_lo_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfgcal_calfsmmeas_dlycount_attr == 10'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfgcal_fsmmaxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfgcal_lpfax_coarse_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfgcal_lpfax_fine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxhifreqagc_inputcmadjust_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxhifreqagc_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXHIFREQAGC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcal_clear_mask_attr == 13'd8191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_ctlecmnmode_stg3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_aux0_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_aux1_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_d0_bot_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_d0_mid_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_d0_top_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_d1_bot_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_d1_mid_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_d1_top_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_e0_lo_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_e1_lo_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmargin_flx_jit_offset_shift_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmargin_jit_disable_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmargin_jit_enable_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmargin_jit_offset_shift_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmargin_jit_setup_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmargin_volt_comp_mask_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmargin_volt_forcel2d_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXMARGIN_VOLT_FORCEL2D_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmargin_volt_offset_shift_d0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmargin_volt_offset_shift_d1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmarginin_direction_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXMARGININ_DIRECTION_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmarginin_flx_jit_offset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmarginin_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXMARGININ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmarginin_mode_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXMARGININ_MODE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmarginin_offset_change_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXMARGININ_OFFSET_CHANGE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmarginin_offset_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmarginin_start_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXMARGININ_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxsum_cm_vref_attr == 9'd75
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxsum_summer_cmfb_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXSUM_SUMMER_CMFB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxsum_summer_cmfb_ibias_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_dfeyadj_aging_cdrlock2data_loc_ov_attr == SERDES_IP_LANE_RXEQ_L1_CFG_DFEYADJ_AGING_CDRLOCK2DATA_LOC_OV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_dfeyadj_aging_cdrlock2data_loc_ov_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_DFEYADJ_AGING_CDRLOCK2DATA_LOC_OV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_dfeyadj_aging_div_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_dfeyadj_aging_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_DFEYADJ_AGING_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxagc_ctlecomp_filterbypass_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXAGC_CTLECOMP_FILTERBYPASS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxagc_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXAGC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxbgcal_calfsmmeas_dlycount_attr == 10'd392
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxbgcal_clear_mask_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxbgcal_fsmmaxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxbgcal_lpfax_coarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxbgcal_lpfax_fine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxbgcalorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxbgcalorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxbgcalorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_calbiasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_calbiasboost_use_lut_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_CALBIASBOOST_USE_LUT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_callbbiasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_callbbiasboost_use_lut_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_CALLBBIASBOOST_USE_LUT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlecomp_filterbypass_smplrcal_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_CTLECOMP_FILTERBYPASS_SMPLRCAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg1_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg2_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg3_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctleinput_probe_mux_smplrcal_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg1_probe_mux_en_smplrcal_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg1_state_en_smplrcal_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg1_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg1_state_en_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg1_state_en_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg1_use_stg2code_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_CTLESTG1_USE_STG2CODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg2_probe_mux_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg2_state_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg2_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg2_state_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg2_state_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg3_probe_mux_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg3_state_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg3_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg3_state_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg3_state_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_hifreqagc_n5targin_sel_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_HIFREQAGC_N5TARGIN_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_inputcmadjust_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_inputcmadjust_stg1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_inputcmadjust_stg2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_inputcmadjust_stg3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_sdimode_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_SDIMODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_smplroffset_aux0_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_smplroffset_aux1_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_smplroffset_d0_bot_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_smplroffset_d0_mid_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_smplroffset_d0_top_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_smplroffset_d1_bot_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_smplroffset_d1_mid_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_smplroffset_d1_top_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_tfrtrim_outen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_tfrtrim_outen_tfrcal_stg1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_tfrtrim_outen_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_tfrtrim_outen_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalalign_iqclk_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalalign_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALALIGN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctl_cal_abort_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALCTL_CAL_ABORT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctl_cal_type_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctl_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALCTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctl_post_delay_pow2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctl_pre_delay_pow2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecalctrl_input_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecalctrl_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALCTLECALCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecalctrl_stg1_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecalctrl_stg1_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecalctrl_stg2_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecalctrl_stg2_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecalctrl_stg3_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecalctrl_stg3_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecompoffset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecompoffset_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALCTLECOMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecompoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALCTLECOMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecompoffsetfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALCTLECOMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecompoffsetfsmout_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaldutybkgnd_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALDUTYBKGND_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaldutybkgnd_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALDUTYBKGND_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_biasboost_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_hf1deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_hf1resdcgain_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_hf2cap_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_hf2deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_hf2reszero_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_hf3deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_hf3resdcgain_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_hf4deq_gray_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALEQ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_ctlecmnmode_stg1_finish_side_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALFSM_CTLECMNMODE_STG1_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_ctlecmnmode_stg1_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_ctlecmnmode_stg2_finish_side_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALFSM_CTLECMNMODE_STG2_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_ctlecmnmode_stg2_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_ctlecmnmode_stg3_finish_side_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALFSM_CTLECMNMODE_STG3_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_ctlecmnmode_stg3_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_runcount_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_smplroffset_finish_side_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALFSM_SMPLROFFSET_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_smplroffset_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsmmeas_ctlecmnmode_stg1_invert_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALFSMMEAS_CTLECMNMODE_STG1_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsmmeas_ctlecmnmode_stg2_invert_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALFSMMEAS_CTLECMNMODE_STG2_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsmmeas_ctlecmnmode_stg3_invert_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALFSMMEAS_CTLECMNMODE_STG3_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsmmeas_smplroffset_invert_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALFSMMEAS_SMPLROFFSET_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_ctlecmnmode_stg1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_ctlecmnmode_stg2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_ctlecmnmode_stg3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_aux0_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_aux1_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_d0_bot_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_d0_mid_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_d0_top_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_d1_bot_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_d1_mid_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_d1_top_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_e0_lo_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_e1_lo_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeas_pow2count_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasin_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasin_req_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASIN_REQ_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasin_req_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASIN_REQ_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasin_req_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASIN_REQ_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasout_ack_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASOUT_ACK_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasout_ack_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASOUT_ACK_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasout_ack_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASOUT_ACK_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasout_avg_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASOUT_AVG_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasout_avg_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASOUT_AVG_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasout_avg_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASOUT_AVG_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasout_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaloffsetfsmout_auxdatacomp_offset_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALOFFSETFSMOUT_AUXDATACOMP_OFFSET_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaloffsetfsmout_boost_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALOFFSETFSMOUT_BOOST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaloffsetfsmout_edgecomp_offset_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALOFFSETFSMOUT_EDGECOMP_OFFSET_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaloffsetfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalset_cal_clear_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalset_cal_mode_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALSET_CAL_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalset_cal_req_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALSET_CAL_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalset_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalstat_cal_ack_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALSTAT_CAL_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalstat_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalsummerfsmout_comp_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALSUMMERFSMOUT_COMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalsummerfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALSUMMERFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcdrphd_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCDRPHD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcdrphd_override_ignore_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCDRPHD_OVERRIDE_IGNORE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_caloffset_range_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_calstg1offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_calstg1offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_calstg2offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_calstg2offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_calstg3offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_calstg3offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_dccouple_sigpath_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCTLE_DCCOUPLE_SIGPATH_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_lbbiasboost_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCTLE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_stg1tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_stg2tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_stg3tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_tfrtrim_outmem_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCTLE_TFRTRIM_OUTMEM_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_tfrtrim_outpen_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCTLE_TFRTRIM_OUTPEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctledc_dccouple_tgate_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCTLEDC_DCCOUPLE_TGATE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctledc_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCTLEDC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxdfe_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXDFE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxdfe_tapgain_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxdfepam_enable_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXDFEPAM_ENABLE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxdfepam_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXDFEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxdpifjit_enb_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXDPIFJIT_ENB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxdpifjit_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXDPIFJIT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxdpifjit_offset_locovr_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqadj_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQADJ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqadj_yadjust_aux0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqadj_yadjust_aux1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqadj_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqadj_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqadj_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqadj_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqadj_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqadj_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqauxxor_amux_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqauxxor_dmux_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqauxxor_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQAUXXOR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcal2flx_pstate_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCAL2FLX_PSTATE_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcal2flx_rate_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCAL2FLX_RATE_MASK_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_16a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_16b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_16c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_16d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_16e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_1a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_1b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_1c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_1d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_1e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_2a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_2b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_2c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_2d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_2e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_4a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_4b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_4c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_4d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_4e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_8a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_8b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_8c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_8d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_8e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_16a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_16b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_16c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_16d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_16e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_1a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_1b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_1c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_1d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_1e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_2a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_2b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_2c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_2d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_2e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_4a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_4b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_4c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_4d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_4e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_8a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_8b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_8c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_8d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_8e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_16a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_16b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_16c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_16d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_16e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_1a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_1b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_1c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_1d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_1e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_2a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_2b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_2c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_2d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_2e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_4a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_4b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_4c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_4d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_4e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_8a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_8b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_8c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_8d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_8e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcals_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCALS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcals_offset_datasummer0_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcals_offset_datasummer0_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcals_offset_datasummer1_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcals_offset_datasummer1_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcals_offset_edgesummer0_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcals_offset_edgesummer0_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcals_offset_edgesummer1_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcals_offset_edgesummer1_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcdr_force_ltr_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCDR_FORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcdr_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCDR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqctl_clear_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCTL_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqctl_fg_run_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCTL_FG_RUN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqctlelut_hifreqagcres_ovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCTLELUT_HIFREQAGCRES_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqctlelut_hifreqvgagain_ovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCTLELUT_HIFREQVGAGAIN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqctls_oddeven_tapgain_sel_inv_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCTLS_ODDEVEN_TAPGAIN_SEL_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqctls_static_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCTLS_STATIC_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqdat_aux_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQDAT_AUX_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqdat_edge_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQDAT_EDGE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqdatactl_auxswap_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqdatactl_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQDATACTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqdatarate_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQDATARATE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqdatarate_rx_rate_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqdfeyadj_agingl2r_delay_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqdfeyadj_agingl2r_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQDFEYADJ_AGINGL2R_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqedgeadj_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEDGEADJ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqedgeadj_yadjust_edge0lo_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqedgeadj_yadjust_edge1lo_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm2flx_ehm_done_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHM2FLX_EHM_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm2flx_ehm_done_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHM2FLX_EHM_DONE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm2flx_ehm_err_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHM2FLX_EHM_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm2flx_ehm_err_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHM2FLX_EHM_ERR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm2flx_ehm_fom_locovr_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHM2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_data_extshift_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHM_DATA_EXTSHIFT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_distance_th_50p_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_distance_th_rate_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_err_mask_vf00_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_err_mask_vf01_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_event_rate_vf00_attr == 32'd67108864
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_event_rate_vf01_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_general_in_vf00_attr == 32'd5505024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_general_in_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_lms_th_50p_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_lms_th_rate_attr == 20'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_mask_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_no_change_th_50p_attr == 12'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_no_change_th_rate_attr == 12'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_reflections_num_50p_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_reflections_num_rate_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_slicer_swap_cb_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHM_SLICER_SWAP_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_sym_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_sym_dly_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_tap_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_test_aux_slicer_val_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_test_hits_th_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjaux_ehm_yadjust_aux0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjaux_ehm_yadjust_aux1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjaux_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJAUX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjauxen_ehm_aux_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJAUXEN_EHM_AUX_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjauxen_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJAUXEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjauxltch_aux_yadj_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJAUXLTCH_AUX_YADJ_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjauxltch_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJAUXLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdata_ehm_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdata_ehm_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdata_ehm_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdata_ehm_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdata_ehm_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdata_ehm_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdata_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdataen_ehm_data_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJDATAEN_EHM_DATA_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdataen_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJDATAEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdataltch_data_yadj_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJDATALTCH_DATA_YADJ_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdataltch_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJDATALTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2ehm_ehm_run_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2EHM_EHM_RUN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2ehm_ehm_run_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2EHM_EHM_RUN_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2lms_coarse_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2LMS_COARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2lms_ctrl_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2LMS_CTRL_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2lms_dfecore_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2LMS_DFECORE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2lms_force_evrefupd_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2LMS_FORCE_EVREFUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2lms_freeze_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2LMS_FREEZE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2lms_incr_decr_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2LMS_INCR_DECR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2lms_mu_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2LMS_MU_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2lms_rst_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2LMS_RST_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2ofc_ofc_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2OFC_OFC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2ofc_ofc_en_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2OFC_OFC_EN_OVRDEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx_pcs_rxeq_clr_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX_PCS_RXEQ_CLR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx_pcs_rxeq_start_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX_PCS_RXEQ_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx_pcs_rxeq_static_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX_PCS_RXEQ_STATIC_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx_rxrate2pcie1_map_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx_rxrate2pcie2_map_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx_rxrate2pcie3_map_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx_rxrate2pcie4_map_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxehmdata_ehm_data_slc_sel_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXEHMDATA_EHM_DATA_SLC_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxehmdata_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXEHMDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxfsm_generalpurpose_reg_in_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxfsm_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXFSM_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxfsm_pause_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXFSM_PAUSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxfsm_state_obs_hold_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXFSM_STATE_OBS_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxfsm_state_obs_sel_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXFSM_STATE_OBS_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxltr_force_ltr_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXLTR_FORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxltr_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXLTR_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxpcsrxeyediag_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXPCSRXEYEDIAG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxpcsrxeyediag_start_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXPCSRXEYEDIAG_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxsigdet_sel_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXSIGDET_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqfsm2ofc_ofc_cal_req_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFSM2OFC_OFC_CAL_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqfsm2ofc_ofc_cal_req_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFSM2OFC_OFC_CAL_REQ_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_16a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_16b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_16c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_16d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_16e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_1a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_1b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_1c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_1d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_1e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_2a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_2b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_2c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_2d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_2e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_4a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_4b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_4c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_4d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_4e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_8a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_8b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_8c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_8d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_8e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_done_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmax_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmax_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_SATMAX_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmax_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmax_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmax_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_SATMAX_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmax_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_SATMAX_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmax_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_SATMAX_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmin_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmin_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_SATMIN_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmin_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmin_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmin_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_SATMIN_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmin_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_SATMIN_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmin_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_SATMIN_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_stable_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_stable_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_STABLE_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_stable_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_stable_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_stable_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_STABLE_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_stable_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_STABLE_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_stable_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_STABLE_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsupd_chng_ack_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSUPD_CHNG_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsupd_chng_req_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSUPD_CHNG_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsupd_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSUPD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjaux_lms_vref0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjaux_lms_vref1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjaux_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJAUX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjauxen_lms_aux_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJAUXEN_LMS_AUX_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjauxen_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJAUXEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjauxltch_lms_aux_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJAUXLTCH_LMS_AUX_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjauxltch_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJAUXLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdata_lms_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdata_lms_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdata_lms_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdata_lms_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdata_lms_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdata_lms_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdata_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdataen_lms_data_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJDATAEN_LMS_DATA_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdataen_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJDATAEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdataltch_lms_data_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJDATALTCH_LMS_DATA_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdataltch_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJDATALTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjedge_lms_yadjust_edge0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjedge_lms_yadjust_edge1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjedge_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJEDGE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjedgeen_lms_edge_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJEDGEEN_LMS_EDGE_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjedgeen_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJEDGEEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjedgeltch_lms_edge_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJEDGELTCH_LMS_EDGE_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjedgeltch_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJEDGELTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqltch_dfe_aux_yadj_b_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLTCH_DFE_AUX_YADJ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqltch_dfe_b_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLTCH_DFE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqltch_dfe_data_yadj_b_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLTCH_DFE_DATA_YADJ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqltch_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqltchc_auxswap_b_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLTCHC_AUXSWAP_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqltchc_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLTCHC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofc2flx_ofc_cal_done_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQOFC2FLX_OFC_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofc2flx_ofc_cal_done_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQOFC2FLX_OFC_CAL_DONE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_ctle_rxinpprobemuxen_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_ctle_rxstg1_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_ctle_rxstg1probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_ctle_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_ctle_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_ctle_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_ctle_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_summer_rxinpprobemuxen_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_summer_rxstg1_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_summer_rxstg1probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_summer_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_summer_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_summer_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_summer_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_time_h_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_time_l_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_ctle_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_ctle_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_ctle_rxstg1probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_ctle_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_ctle_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_ctle_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_ctle_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_summer_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_summer_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_summer_rxstg1probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_summer_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_summer_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_summer_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_summer_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_time_l_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_compsel_ctle_st1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_compsel_ctle_st2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_compsel_ctle_st3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_compsel_idle_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_compsel_sa_d0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_compsel_sa_d1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_compsel_sa_e0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_compsel_sa_e1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_invert_comp_fb_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_lpexitcal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_lpexitcal_time_l_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_adapt_en_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_adapt_thr_sel_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_cal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_cal_thr_sel_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_data_disp_sticky_clr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQOFCCFG_OFC_DATA_DISP_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_disparity_disable_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQOFCCFG_OFC_DISPARITY_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_disparity_leak_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_disparity_thr_sel_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_lpexitcal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_lpf_bypass_en_cb_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQOFCCFG_OFC_LPF_BYPASS_EN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_ratechangecal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_pre_timer_setting_pow2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ratechangecal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ratechangecal_time_l_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_rxinpprobemuxen_idle_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_rxstg1_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_rxstg1probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_rxstg2_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_rxstg2probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_rxstg3_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_rxstg3probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqout_init_restore_avail_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQOUT_INIT_RESTORE_AVAIL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqprecal_code_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqprecal_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQPRECAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_hf1deq_dir_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_BOOSTLUT_HF1DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_hf2deq_dir_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_BOOSTLUT_HF2DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_hf2reszero_dir_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_BOOSTLUT_HF2RESZERO_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_hf3deq_dir_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_BOOSTLUT_HF3DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_idx_hf1deq_vf00_attr == 32'd599186
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_idx_hf1deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_idx_hf2deq_vf00_attr == 32'd1198372
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_idx_hf2deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_idx_hf2reszero_vf00_attr == 32'd4290772992
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_idx_hf2reszero_vf01_attr == 21'd2097151
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_idx_hf3deq_vf00_attr == 32'd2396744
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_idx_hf3deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_init_hf1deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_init_hf2deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_init_hf2reszero_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_init_hf3deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_cal_hifreqagcres_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_cal_hifreqvgagain_attr == 7'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_cal_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_cal_yadjust_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_biasboost_dir_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_GAINLUT_BIASBOOST_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_hf1resdcgain_dir_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_GAINLUT_HF1RESDCGAIN_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_hf3resdcgain_dir_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_GAINLUT_HF3RESDCGAIN_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_biasboost_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_biasboost_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_biasboost_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf00_attr == 32'd2863311530
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf01_attr == 32'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf00_attr == 32'd1431655764
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf01_attr == 32'd1431655765
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_lbbiasboost_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_lbbiasboost_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_lbbiasboost_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_init_biasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_init_hf1resdcgain_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_init_hf3resdcgain_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_init_lbbiasboost_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_lbbiasboost_dir_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_GAINLUT_LBBIASBOOST_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_latch_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref0_initval_attr == 9'd61
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref1_initval_attr == 9'd191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref2_initval_attr == 9'd321
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref3_initval_attr == 9'd451
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_decr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_AUXVREF_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_frac_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_AUXVREF_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_frac_reset_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_incr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_AUXVREF_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_incr_decr_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_pam4adj_swizzle_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_AUXVREF_PAM4ADJ_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_AUXVREF_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_pol_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_single_step_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_AUXVREF_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_stable_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_AUXVREF_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_AUXVREF_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_targ_0_hi_attr == 9'd149
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_targ_0_lo_attr == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_auxvref_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_auxvref_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_dfe_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_dfe_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_edge_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_edge_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_edgevref_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_edgevref_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_iqalign_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_iqalign_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_level_vga_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_vga_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_vga_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_blockcount_fast_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_BLOCKCOUNT_FAST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_coarse_detect_clear_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_COARSE_DETECT_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_coarse_detect_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_COARSE_DETECT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_continuous_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_CONTINUOUS_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_datastats_incr_decr_swizzle_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_DATASTATS_INCR_DECR_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_datastats_pol_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_DATASTATS_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_datastats_thres_attr == 16'd1023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe1_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe2_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe3_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe4p_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_core_sel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_decr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_DFE_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_frac_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_DFE_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_frac_reset_mask_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_incr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_DFE_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_incr_decr_mask_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_inner_lvl_filter_en_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_DFE_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_pol_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_single_step_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_DFE_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_stable_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_DFE_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_DFE_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_targtap1_attr == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_targtap2_attr == 7'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_targtap3_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_targtap4_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_decr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGE_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_frac_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGE_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_frac_reset_mask_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_incr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGE_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_incr_decr_mask_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGE_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_pol_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_single_step_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGE_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_stable_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGE_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGE_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_decr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGEVREF_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_frac_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGEVREF_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGEVREF_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_incr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGEVREF_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_initval_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGEVREF_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_pol_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGEVREF_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_single_step_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGEVREF_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_stable_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGEVREF_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGEVREF_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_fast_blockcnt_attr == 16'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_filter_mode_auxvref_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_filter_mode_dfe_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_filter_mode_edge_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_filter_mode_edgevref_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_filter_mode_iqalign_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_filter_mode_vga_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_freeze_auxvrefupd_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_freeze_dfeupd_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_freeze_edgeupd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_freeze_edgevrefupd_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_FREEZE_EDGEVREFUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_freeze_forcebg_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_FREEZE_FORCEBG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_freeze_hifreqagcupd_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_FREEZE_HIFREQAGCUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_freeze_iqalignupd_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_FREEZE_IQALIGNUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_freeze_lofreqagcupd_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_FREEZE_LOFREQAGCUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_freeze_vgaupd_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_FREEZE_VGAUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_gated_update_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_GATED_UPDATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_accum_count_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_accum_level_en_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_decr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_HIFREQAGC_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_frac_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_HIFREQAGC_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_HIFREQAGC_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_incr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_HIFREQAGC_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_n1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_n2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_n3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_n4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_n5_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_HIFREQAGC_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_pol_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_HIFREQAGC_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_single_step_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_HIFREQAGC_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_stable_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_HIFREQAGC_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_HIFREQAGC_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_init_adapt_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_INIT_ADAPT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_decr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_IQALIGN_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_frac_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_IQALIGN_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_IQALIGN_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_incr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_IQALIGN_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_IQALIGN_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_pol_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_IQALIGN_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_single_step_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_IQALIGN_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_stable_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_IQALIGN_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_IQALIGN_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_targ_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_itercount_attr == 10'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_latch_delay_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_latch_prepost_delay_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_decr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOFREQAGC_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_frac_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOFREQAGC_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOFREQAGC_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_incr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOFREQAGC_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOFREQAGC_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_pol_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOFREQAGC_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_single_step_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOFREQAGC_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_stable_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOFREQAGC_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOFREQAGC_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_logain_auxvref_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOGAIN_AUXVREF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_logain_dfe_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_logain_edge_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_logain_edgevref_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOGAIN_EDGEVREF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_logain_hifreqagc_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOGAIN_HIFREQAGC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_logain_iqalign_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOGAIN_IQALIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_logain_lofreqagc_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOGAIN_LOFREQAGC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_logain_vga_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOGAIN_VGA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_auxvref_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_dfe1_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_dfe23_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_dfe4p_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_edge2_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_edge3_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_edge4_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_edgevref_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_hifreqagc_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_iqalign_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_lofreqagc_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_vga_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_nrz_to_pam4_mode_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_NRZ_TO_PAM4_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_slow_blockcnt_attr == 16'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_start_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_tsettle_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_accum_count_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_accum_level_en_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_decr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_frac_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_incr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_mode_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_pol_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_single_step_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_stable_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_yadjdata_mid_clamp_zero_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_YADJDATA_MID_CLAMP_ZERO_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lofreqagcgain_sel_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LOFREQAGCGAIN_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_caldfedatatap1gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_caldfedatatap2gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_caldfedatatap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_caldfedatatap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_caldfeedgetap2gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_caldfeedgetap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_caldfeedgetap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_lofreqagcgain_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_caldfedatatap1gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_caldfedatatap1gain_attr == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_caldfedatatap1gain_attr == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_shift_auxshft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_shift_capture_trigger_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_SHIFT_CAPTURE_TRIGGER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_shift_clear_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_SHIFT_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_shift_dat_bitsel_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_SHIFT_DAT_BITSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_shift_datashft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_shift_edgeshft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_shift_edgeshft_nrz8b10b_pam16b20b_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_shift_polarity_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_SHIFT_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap10gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap11gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap12gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap13gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap14gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap15gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap16gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap1gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap2gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap5gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap6gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap7gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap8gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap9gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfeedgetap2gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfeedgetap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfeedgetap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_hifreqvgagain_attr == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_auxvref0_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_auxvref1_attr == 9'd223
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_auxvref2_attr == 9'd339
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_auxvref3_attr == 9'd456
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_caldfedatatap1gain_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_caldfeedgetap2gain_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_calhifreqagcres_attr == 6'd52
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_callofreqagcgain_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_edgevref_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_hifreqvgagain_attr == 7'd77
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_iqalign_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_auxvref0_attr == 9'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_auxvref1_attr == 9'd173
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_auxvref2_attr == 9'd289
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_auxvref3_attr == 9'd356
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_caldfedatatap1gain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_caldfeedgetap2gain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_calhifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_callofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_edgevref_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_iqalign_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqsetnrztopam4_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSETNRZTOPAM4_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqsetnrztopam4_switch_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSETNRZTOPAM4_SWITCH_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqsigdet_pause_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSIGDET_PAUSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqspare0_attr == 32'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqspare1_attr == 32'd15871
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqspare2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqsync2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSYNC2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqsync2flx_rxdatapath_ready_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSYNC2FLX_RXDATAPATH_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqtapctrl_data_tap13to16_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQTAPCTRL_DATA_TAP13TO16_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqtapctrl_data_tap1to4_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQTAPCTRL_DATA_TAP1TO4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqtapctrl_data_tap5to8_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQTAPCTRL_DATA_TAP5TO8_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqtapctrl_data_tap9to12_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQTAPCTRL_DATA_TAP9TO12_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqtapctrl_edge_tap_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQTAPCTRL_EDGE_TAP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqtapctrl_tap1to4gain_dbl_res_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQTAPCTRL_TAP1TO4GAIN_DBL_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqtapctrl_tap5to16gain_dbl_res_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQTAPCTRL_TAP5TO16GAIN_DBL_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvalc_hifreqagcbiasadjust_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvalc_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQVALC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvalc_midbandzero_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvalcl_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQVALCL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvalcl_lofreqagcgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap01gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap02gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap03gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap04gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap05gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap06gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap07gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap08gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap09gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap10gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap11gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap12gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap13gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap14gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap15gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap16gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQVALD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvale_caldfeedgetap02gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvale_caldfeedgetap03gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvale_caldfeedgetap04gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvale_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQVALE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1cal_clear_mask_attr == 13'd8184
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_aux0_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_aux1_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_d0_bot_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_d0_mid_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_d0_top_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_d1_bot_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_d1_mid_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_d1_top_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_e0_lo_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_e1_lo_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2cal_clear_mask_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_aux0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_aux1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_d0_bot_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_d0_mid_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_d0_top_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_d1_bot_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_d1_mid_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_d1_top_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_e0_lo_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_e1_lo_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfgcal_calfsmmeas_dlycount_attr == 10'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfgcal_fsmmaxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfgcal_lpfax_coarse_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfgcal_lpfax_fine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxhifreqagc_inputcmadjust_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxhifreqagc_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXHIFREQAGC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcal_clear_mask_attr == 13'd8191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_ctlecmnmode_stg1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_ctlecmnmode_stg2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_ctlecmnmode_stg3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_aux0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_aux1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_d0_bot_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_d0_mid_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_d0_top_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_d1_bot_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_d1_mid_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_d1_top_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_e0_lo_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_e1_lo_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmargin_flx_jit_offset_shift_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmargin_jit_disable_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmargin_jit_enable_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmargin_jit_offset_shift_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmargin_jit_setup_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmargin_volt_comp_mask_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmargin_volt_forcel2d_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXMARGIN_VOLT_FORCEL2D_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmargin_volt_offset_shift_d0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmargin_volt_offset_shift_d1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmarginin_direction_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXMARGININ_DIRECTION_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmarginin_flx_jit_offset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmarginin_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXMARGININ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmarginin_mode_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXMARGININ_MODE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmarginin_offset_change_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXMARGININ_OFFSET_CHANGE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmarginin_offset_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmarginin_start_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXMARGININ_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxsum_cm_vref_attr == 9'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxsum_summer_cmfb_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXSUM_SUMMER_CMFB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxsum_summer_cmfb_ibias_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_dfeyadj_aging_cdrlock2data_loc_ov_attr == SERDES_IP_LANE_RXEQ_L2_CFG_DFEYADJ_AGING_CDRLOCK2DATA_LOC_OV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_dfeyadj_aging_cdrlock2data_loc_ov_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_DFEYADJ_AGING_CDRLOCK2DATA_LOC_OV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_dfeyadj_aging_div_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_dfeyadj_aging_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_DFEYADJ_AGING_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxagc_ctlecomp_filterbypass_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXAGC_CTLECOMP_FILTERBYPASS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxagc_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXAGC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxbgcal_calfsmmeas_dlycount_attr == 10'd392
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxbgcal_clear_mask_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxbgcal_fsmmaxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxbgcal_lpfax_coarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxbgcal_lpfax_fine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxbgcalorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxbgcalorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxbgcalorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_calbiasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_calbiasboost_use_lut_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_CALBIASBOOST_USE_LUT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_callbbiasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_callbbiasboost_use_lut_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_CALLBBIASBOOST_USE_LUT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlecomp_filterbypass_smplrcal_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_CTLECOMP_FILTERBYPASS_SMPLRCAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg1_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg2_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg3_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctleinput_probe_mux_smplrcal_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg1_probe_mux_en_smplrcal_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg1_state_en_smplrcal_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg1_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg1_state_en_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg1_state_en_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg1_use_stg2code_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_CTLESTG1_USE_STG2CODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg2_probe_mux_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg2_state_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg2_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg2_state_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg2_state_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg3_probe_mux_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg3_state_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg3_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg3_state_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg3_state_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_hifreqagc_n5targin_sel_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_HIFREQAGC_N5TARGIN_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_inputcmadjust_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_inputcmadjust_stg1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_inputcmadjust_stg2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_inputcmadjust_stg3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_sdimode_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_SDIMODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_smplroffset_aux0_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_smplroffset_aux1_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_smplroffset_d0_bot_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_smplroffset_d0_mid_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_smplroffset_d0_top_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_smplroffset_d1_bot_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_smplroffset_d1_mid_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_smplroffset_d1_top_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_tfrtrim_outen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_tfrtrim_outen_tfrcal_stg1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_tfrtrim_outen_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_tfrtrim_outen_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalalign_iqclk_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalalign_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALALIGN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctl_cal_abort_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALCTL_CAL_ABORT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctl_cal_type_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctl_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALCTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctl_post_delay_pow2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctl_pre_delay_pow2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecalctrl_input_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecalctrl_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALCTLECALCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecalctrl_stg1_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecalctrl_stg1_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecalctrl_stg2_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecalctrl_stg2_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecalctrl_stg3_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecalctrl_stg3_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecompoffset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecompoffset_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALCTLECOMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecompoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALCTLECOMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecompoffsetfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALCTLECOMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecompoffsetfsmout_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaldutybkgnd_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALDUTYBKGND_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaldutybkgnd_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALDUTYBKGND_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_biasboost_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_hf1deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_hf1resdcgain_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_hf2cap_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_hf2deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_hf2reszero_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_hf3deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_hf3resdcgain_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_hf4deq_gray_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALEQ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_ctlecmnmode_stg1_finish_side_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALFSM_CTLECMNMODE_STG1_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_ctlecmnmode_stg1_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_ctlecmnmode_stg2_finish_side_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALFSM_CTLECMNMODE_STG2_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_ctlecmnmode_stg2_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_ctlecmnmode_stg3_finish_side_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALFSM_CTLECMNMODE_STG3_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_ctlecmnmode_stg3_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_runcount_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_smplroffset_finish_side_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALFSM_SMPLROFFSET_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_smplroffset_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsmmeas_ctlecmnmode_stg1_invert_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALFSMMEAS_CTLECMNMODE_STG1_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsmmeas_ctlecmnmode_stg2_invert_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALFSMMEAS_CTLECMNMODE_STG2_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsmmeas_ctlecmnmode_stg3_invert_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALFSMMEAS_CTLECMNMODE_STG3_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsmmeas_smplroffset_invert_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALFSMMEAS_SMPLROFFSET_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_ctlecmnmode_stg1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_ctlecmnmode_stg2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_ctlecmnmode_stg3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_aux0_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_aux1_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_d0_bot_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_d0_mid_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_d0_top_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_d1_bot_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_d1_mid_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_d1_top_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_e0_lo_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_e1_lo_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeas_pow2count_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasin_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasin_req_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASIN_REQ_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasin_req_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASIN_REQ_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasin_req_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASIN_REQ_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasout_ack_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASOUT_ACK_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasout_ack_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASOUT_ACK_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasout_ack_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASOUT_ACK_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasout_avg_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASOUT_AVG_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasout_avg_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASOUT_AVG_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasout_avg_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASOUT_AVG_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasout_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaloffsetfsmout_auxdatacomp_offset_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALOFFSETFSMOUT_AUXDATACOMP_OFFSET_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaloffsetfsmout_boost_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALOFFSETFSMOUT_BOOST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaloffsetfsmout_edgecomp_offset_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALOFFSETFSMOUT_EDGECOMP_OFFSET_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaloffsetfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalset_cal_clear_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalset_cal_mode_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALSET_CAL_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalset_cal_req_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALSET_CAL_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalset_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalstat_cal_ack_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALSTAT_CAL_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalstat_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalsummerfsmout_comp_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALSUMMERFSMOUT_COMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalsummerfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALSUMMERFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcdrphd_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCDRPHD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcdrphd_override_ignore_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCDRPHD_OVERRIDE_IGNORE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_caloffset_range_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_calstg1offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_calstg1offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_calstg2offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_calstg2offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_calstg3offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_calstg3offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_dccouple_sigpath_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCTLE_DCCOUPLE_SIGPATH_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_lbbiasboost_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCTLE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_stg1tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_stg2tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_stg3tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_tfrtrim_outmem_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCTLE_TFRTRIM_OUTMEM_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_tfrtrim_outpen_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCTLE_TFRTRIM_OUTPEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctledc_dccouple_tgate_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCTLEDC_DCCOUPLE_TGATE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctledc_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCTLEDC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxdfe_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXDFE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxdfe_tapgain_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxdfepam_enable_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXDFEPAM_ENABLE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxdfepam_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXDFEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxdpifjit_enb_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXDPIFJIT_ENB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxdpifjit_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXDPIFJIT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxdpifjit_offset_locovr_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqadj_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQADJ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqadj_yadjust_aux0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqadj_yadjust_aux1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqadj_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqadj_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqadj_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqadj_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqadj_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqadj_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqauxxor_amux_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqauxxor_dmux_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqauxxor_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQAUXXOR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcal2flx_pstate_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCAL2FLX_PSTATE_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcal2flx_rate_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCAL2FLX_RATE_MASK_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_16a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_16b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_16c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_16d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_16e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_1a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_1b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_1c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_1d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_1e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_2a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_2b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_2c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_2d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_2e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_4a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_4b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_4c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_4d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_4e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_8a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_8b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_8c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_8d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_8e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_16a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_16b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_16c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_16d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_16e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_1a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_1b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_1c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_1d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_1e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_2a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_2b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_2c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_2d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_2e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_4a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_4b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_4c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_4d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_4e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_8a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_8b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_8c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_8d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_8e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_16a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_16b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_16c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_16d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_16e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_1a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_1b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_1c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_1d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_1e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_2a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_2b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_2c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_2d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_2e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_4a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_4b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_4c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_4d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_4e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_8a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_8b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_8c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_8d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_8e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcals_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCALS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcals_offset_datasummer0_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcals_offset_datasummer0_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcals_offset_datasummer1_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcals_offset_datasummer1_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcals_offset_edgesummer0_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcals_offset_edgesummer0_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcals_offset_edgesummer1_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcals_offset_edgesummer1_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcdr_force_ltr_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCDR_FORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcdr_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCDR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqctl_clear_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCTL_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqctl_fg_run_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCTL_FG_RUN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqctlelut_hifreqagcres_ovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCTLELUT_HIFREQAGCRES_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqctlelut_hifreqvgagain_ovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCTLELUT_HIFREQVGAGAIN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqctls_oddeven_tapgain_sel_inv_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCTLS_ODDEVEN_TAPGAIN_SEL_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqctls_static_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCTLS_STATIC_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqdat_aux_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQDAT_AUX_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqdat_edge_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQDAT_EDGE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqdatactl_auxswap_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqdatactl_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQDATACTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqdatarate_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQDATARATE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqdatarate_rx_rate_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqdfeyadj_agingl2r_delay_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqdfeyadj_agingl2r_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQDFEYADJ_AGINGL2R_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqedgeadj_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEDGEADJ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqedgeadj_yadjust_edge0lo_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqedgeadj_yadjust_edge1lo_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm2flx_ehm_done_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHM2FLX_EHM_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm2flx_ehm_done_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHM2FLX_EHM_DONE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm2flx_ehm_err_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHM2FLX_EHM_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm2flx_ehm_err_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHM2FLX_EHM_ERR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm2flx_ehm_fom_locovr_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHM2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_data_extshift_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHM_DATA_EXTSHIFT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_distance_th_50p_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_distance_th_rate_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_err_mask_vf00_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_err_mask_vf01_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_event_rate_vf00_attr == 32'd67108864
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_event_rate_vf01_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_general_in_vf00_attr == 32'd5505024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_general_in_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_lms_th_50p_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_lms_th_rate_attr == 20'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_mask_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_no_change_th_50p_attr == 12'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_no_change_th_rate_attr == 12'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_reflections_num_50p_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_reflections_num_rate_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_slicer_swap_cb_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHM_SLICER_SWAP_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_sym_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_sym_dly_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_tap_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_test_aux_slicer_val_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_test_hits_th_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjaux_ehm_yadjust_aux0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjaux_ehm_yadjust_aux1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjaux_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJAUX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjauxen_ehm_aux_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJAUXEN_EHM_AUX_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjauxen_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJAUXEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjauxltch_aux_yadj_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJAUXLTCH_AUX_YADJ_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjauxltch_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJAUXLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdata_ehm_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdata_ehm_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdata_ehm_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdata_ehm_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdata_ehm_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdata_ehm_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdata_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdataen_ehm_data_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJDATAEN_EHM_DATA_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdataen_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJDATAEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdataltch_data_yadj_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJDATALTCH_DATA_YADJ_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdataltch_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJDATALTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2ehm_ehm_run_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2EHM_EHM_RUN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2ehm_ehm_run_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2EHM_EHM_RUN_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2lms_coarse_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2LMS_COARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2lms_ctrl_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2LMS_CTRL_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2lms_dfecore_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2LMS_DFECORE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2lms_force_evrefupd_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2LMS_FORCE_EVREFUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2lms_freeze_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2LMS_FREEZE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2lms_incr_decr_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2LMS_INCR_DECR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2lms_mu_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2LMS_MU_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2lms_rst_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2LMS_RST_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2ofc_ofc_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2OFC_OFC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2ofc_ofc_en_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2OFC_OFC_EN_OVRDEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx_pcs_rxeq_clr_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX_PCS_RXEQ_CLR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx_pcs_rxeq_start_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX_PCS_RXEQ_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx_pcs_rxeq_static_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX_PCS_RXEQ_STATIC_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx_rxrate2pcie1_map_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx_rxrate2pcie2_map_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx_rxrate2pcie3_map_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx_rxrate2pcie4_map_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxehmdata_ehm_data_slc_sel_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXEHMDATA_EHM_DATA_SLC_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxehmdata_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXEHMDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxfsm_generalpurpose_reg_in_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxfsm_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXFSM_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxfsm_pause_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXFSM_PAUSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxfsm_state_obs_hold_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXFSM_STATE_OBS_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxfsm_state_obs_sel_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXFSM_STATE_OBS_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxltr_force_ltr_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXLTR_FORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxltr_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXLTR_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxpcsrxeyediag_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXPCSRXEYEDIAG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxpcsrxeyediag_start_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXPCSRXEYEDIAG_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxsigdet_sel_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXSIGDET_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqfsm2ofc_ofc_cal_req_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFSM2OFC_OFC_CAL_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqfsm2ofc_ofc_cal_req_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFSM2OFC_OFC_CAL_REQ_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_16a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_16b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_16c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_16d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_16e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_1a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_1b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_1c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_1d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_1e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_2a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_2b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_2c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_2d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_2e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_4a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_4b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_4c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_4d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_4e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_8a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_8b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_8c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_8d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_8e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_done_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmax_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmax_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_SATMAX_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmax_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmax_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmax_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_SATMAX_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmax_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_SATMAX_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmax_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_SATMAX_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmin_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmin_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_SATMIN_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmin_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmin_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmin_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_SATMIN_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmin_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_SATMIN_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmin_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_SATMIN_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_stable_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_stable_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_STABLE_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_stable_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_stable_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_stable_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_STABLE_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_stable_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_STABLE_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_stable_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_STABLE_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsupd_chng_ack_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSUPD_CHNG_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsupd_chng_req_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSUPD_CHNG_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsupd_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSUPD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjaux_lms_vref0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjaux_lms_vref1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjaux_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJAUX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjauxen_lms_aux_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJAUXEN_LMS_AUX_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjauxen_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJAUXEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjauxltch_lms_aux_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJAUXLTCH_LMS_AUX_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjauxltch_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJAUXLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdata_lms_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdata_lms_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdata_lms_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdata_lms_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdata_lms_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdata_lms_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdata_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdataen_lms_data_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJDATAEN_LMS_DATA_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdataen_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJDATAEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdataltch_lms_data_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJDATALTCH_LMS_DATA_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdataltch_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJDATALTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjedge_lms_yadjust_edge0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjedge_lms_yadjust_edge1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjedge_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJEDGE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjedgeen_lms_edge_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJEDGEEN_LMS_EDGE_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjedgeen_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJEDGEEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjedgeltch_lms_edge_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJEDGELTCH_LMS_EDGE_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjedgeltch_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJEDGELTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqltch_dfe_aux_yadj_b_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLTCH_DFE_AUX_YADJ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqltch_dfe_b_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLTCH_DFE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqltch_dfe_data_yadj_b_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLTCH_DFE_DATA_YADJ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqltch_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqltchc_auxswap_b_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLTCHC_AUXSWAP_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqltchc_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLTCHC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofc2flx_ofc_cal_done_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQOFC2FLX_OFC_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofc2flx_ofc_cal_done_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQOFC2FLX_OFC_CAL_DONE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_ctle_rxinpprobemuxen_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_ctle_rxstg1_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_ctle_rxstg1probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_ctle_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_ctle_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_ctle_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_ctle_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_summer_rxinpprobemuxen_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_summer_rxstg1_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_summer_rxstg1probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_summer_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_summer_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_summer_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_summer_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_time_h_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_time_l_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_ctle_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_ctle_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_ctle_rxstg1probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_ctle_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_ctle_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_ctle_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_ctle_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_summer_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_summer_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_summer_rxstg1probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_summer_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_summer_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_summer_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_summer_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_time_l_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_compsel_ctle_st1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_compsel_ctle_st2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_compsel_ctle_st3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_compsel_idle_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_compsel_sa_d0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_compsel_sa_d1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_compsel_sa_e0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_compsel_sa_e1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_invert_comp_fb_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_lpexitcal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_lpexitcal_time_l_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_adapt_en_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_adapt_thr_sel_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_cal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_cal_thr_sel_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_data_disp_sticky_clr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQOFCCFG_OFC_DATA_DISP_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_disparity_disable_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQOFCCFG_OFC_DISPARITY_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_disparity_leak_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_disparity_thr_sel_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_lpexitcal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_lpf_bypass_en_cb_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQOFCCFG_OFC_LPF_BYPASS_EN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_ratechangecal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_pre_timer_setting_pow2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ratechangecal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ratechangecal_time_l_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_rxinpprobemuxen_idle_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_rxstg1_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_rxstg1probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_rxstg2_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_rxstg2probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_rxstg3_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_rxstg3probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqout_init_restore_avail_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQOUT_INIT_RESTORE_AVAIL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqprecal_code_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqprecal_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQPRECAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_hf1deq_dir_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_BOOSTLUT_HF1DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_hf2deq_dir_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_BOOSTLUT_HF2DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_hf2reszero_dir_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_BOOSTLUT_HF2RESZERO_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_hf3deq_dir_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_BOOSTLUT_HF3DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_idx_hf1deq_vf00_attr == 32'd599186
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_idx_hf1deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_idx_hf2deq_vf00_attr == 32'd1198372
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_idx_hf2deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_idx_hf2reszero_vf00_attr == 32'd4290772992
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_idx_hf2reszero_vf01_attr == 21'd2097151
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_idx_hf3deq_vf00_attr == 32'd2396744
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_idx_hf3deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_init_hf1deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_init_hf2deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_init_hf2reszero_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_init_hf3deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_cal_hifreqagcres_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_cal_hifreqvgagain_attr == 7'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_cal_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_cal_yadjust_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_biasboost_dir_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_GAINLUT_BIASBOOST_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_hf1resdcgain_dir_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_GAINLUT_HF1RESDCGAIN_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_hf3resdcgain_dir_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_GAINLUT_HF3RESDCGAIN_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_biasboost_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_biasboost_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_biasboost_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf00_attr == 32'd2863311530
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf01_attr == 32'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf00_attr == 32'd1431655764
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf01_attr == 32'd1431655765
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_lbbiasboost_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_lbbiasboost_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_lbbiasboost_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_init_biasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_init_hf1resdcgain_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_init_hf3resdcgain_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_init_lbbiasboost_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_lbbiasboost_dir_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_GAINLUT_LBBIASBOOST_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_latch_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref0_initval_attr == 9'd61
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref1_initval_attr == 9'd191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref2_initval_attr == 9'd321
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref3_initval_attr == 9'd451
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_decr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_AUXVREF_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_frac_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_AUXVREF_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_frac_reset_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_incr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_AUXVREF_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_incr_decr_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_pam4adj_swizzle_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_AUXVREF_PAM4ADJ_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_AUXVREF_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_pol_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_single_step_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_AUXVREF_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_stable_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_AUXVREF_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_AUXVREF_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_targ_0_hi_attr == 9'd149
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_targ_0_lo_attr == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_auxvref_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_auxvref_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_dfe_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_dfe_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_edge_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_edge_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_edgevref_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_edgevref_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_iqalign_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_iqalign_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_level_vga_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_vga_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_vga_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_blockcount_fast_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_BLOCKCOUNT_FAST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_coarse_detect_clear_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_COARSE_DETECT_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_coarse_detect_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_COARSE_DETECT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_continuous_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_CONTINUOUS_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_datastats_incr_decr_swizzle_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_DATASTATS_INCR_DECR_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_datastats_pol_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_DATASTATS_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_datastats_thres_attr == 16'd1023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe1_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe2_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe3_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe4p_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_core_sel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_decr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_DFE_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_frac_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_DFE_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_frac_reset_mask_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_incr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_DFE_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_incr_decr_mask_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_inner_lvl_filter_en_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_DFE_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_pol_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_single_step_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_DFE_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_stable_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_DFE_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_DFE_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_targtap1_attr == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_targtap2_attr == 7'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_targtap3_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_targtap4_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_decr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGE_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_frac_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGE_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_frac_reset_mask_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_incr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGE_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_incr_decr_mask_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGE_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_pol_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_single_step_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGE_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_stable_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGE_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGE_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_decr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGEVREF_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_frac_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGEVREF_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGEVREF_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_incr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGEVREF_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_initval_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGEVREF_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_pol_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGEVREF_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_single_step_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGEVREF_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_stable_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGEVREF_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGEVREF_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_fast_blockcnt_attr == 16'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_filter_mode_auxvref_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_filter_mode_dfe_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_filter_mode_edge_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_filter_mode_edgevref_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_filter_mode_iqalign_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_filter_mode_vga_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_freeze_auxvrefupd_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_freeze_dfeupd_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_freeze_edgeupd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_freeze_edgevrefupd_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_FREEZE_EDGEVREFUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_freeze_forcebg_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_FREEZE_FORCEBG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_freeze_hifreqagcupd_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_FREEZE_HIFREQAGCUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_freeze_iqalignupd_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_FREEZE_IQALIGNUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_freeze_lofreqagcupd_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_FREEZE_LOFREQAGCUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_freeze_vgaupd_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_FREEZE_VGAUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_gated_update_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_GATED_UPDATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_accum_count_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_accum_level_en_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_decr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_HIFREQAGC_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_frac_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_HIFREQAGC_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_HIFREQAGC_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_incr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_HIFREQAGC_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_n1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_n2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_n3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_n4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_n5_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_HIFREQAGC_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_pol_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_HIFREQAGC_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_single_step_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_HIFREQAGC_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_stable_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_HIFREQAGC_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_HIFREQAGC_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_init_adapt_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_INIT_ADAPT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_decr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_IQALIGN_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_frac_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_IQALIGN_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_IQALIGN_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_incr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_IQALIGN_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_IQALIGN_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_pol_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_IQALIGN_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_single_step_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_IQALIGN_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_stable_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_IQALIGN_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_IQALIGN_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_targ_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_itercount_attr == 10'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_latch_delay_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_latch_prepost_delay_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_decr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOFREQAGC_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_frac_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOFREQAGC_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOFREQAGC_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_incr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOFREQAGC_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOFREQAGC_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_pol_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOFREQAGC_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_single_step_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOFREQAGC_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_stable_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOFREQAGC_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOFREQAGC_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_logain_auxvref_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOGAIN_AUXVREF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_logain_dfe_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_logain_edge_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_logain_edgevref_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOGAIN_EDGEVREF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_logain_hifreqagc_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOGAIN_HIFREQAGC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_logain_iqalign_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOGAIN_IQALIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_logain_lofreqagc_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOGAIN_LOFREQAGC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_logain_vga_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOGAIN_VGA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_auxvref_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_dfe1_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_dfe23_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_dfe4p_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_edge2_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_edge3_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_edge4_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_edgevref_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_hifreqagc_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_iqalign_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_lofreqagc_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_vga_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_nrz_to_pam4_mode_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_NRZ_TO_PAM4_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_slow_blockcnt_attr == 16'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_start_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_tsettle_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_accum_count_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_accum_level_en_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_decr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_frac_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_incr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_mode_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_pol_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_single_step_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_stable_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_yadjdata_mid_clamp_zero_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_YADJDATA_MID_CLAMP_ZERO_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lofreqagcgain_sel_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LOFREQAGCGAIN_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_caldfedatatap1gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_caldfedatatap2gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_caldfedatatap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_caldfedatatap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_caldfeedgetap2gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_caldfeedgetap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_caldfeedgetap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_lofreqagcgain_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_caldfedatatap1gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_caldfedatatap1gain_attr == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_caldfedatatap1gain_attr == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_shift_auxshft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_shift_capture_trigger_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_SHIFT_CAPTURE_TRIGGER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_shift_clear_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_SHIFT_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_shift_dat_bitsel_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_SHIFT_DAT_BITSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_shift_datashft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_shift_edgeshft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_shift_edgeshft_nrz8b10b_pam16b20b_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_shift_polarity_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_SHIFT_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap10gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap11gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap12gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap13gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap14gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap15gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap16gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap1gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap2gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap5gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap6gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap7gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap8gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap9gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfeedgetap2gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfeedgetap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfeedgetap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_hifreqvgagain_attr == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_auxvref0_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_auxvref1_attr == 9'd223
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_auxvref2_attr == 9'd339
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_auxvref3_attr == 9'd456
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_caldfedatatap1gain_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_caldfeedgetap2gain_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_calhifreqagcres_attr == 6'd52
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_callofreqagcgain_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_edgevref_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_hifreqvgagain_attr == 7'd77
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_iqalign_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_auxvref0_attr == 9'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_auxvref1_attr == 9'd173
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_auxvref2_attr == 9'd289
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_auxvref3_attr == 9'd356
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_caldfedatatap1gain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_caldfeedgetap2gain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_calhifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_callofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_edgevref_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_iqalign_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqsetnrztopam4_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSETNRZTOPAM4_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqsetnrztopam4_switch_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSETNRZTOPAM4_SWITCH_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqsigdet_pause_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSIGDET_PAUSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqspare0_attr == 32'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqspare1_attr == 32'd15871
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqspare2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqsync2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSYNC2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqsync2flx_rxdatapath_ready_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSYNC2FLX_RXDATAPATH_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqtapctrl_data_tap13to16_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQTAPCTRL_DATA_TAP13TO16_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqtapctrl_data_tap1to4_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQTAPCTRL_DATA_TAP1TO4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqtapctrl_data_tap5to8_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQTAPCTRL_DATA_TAP5TO8_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqtapctrl_data_tap9to12_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQTAPCTRL_DATA_TAP9TO12_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqtapctrl_edge_tap_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQTAPCTRL_EDGE_TAP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqtapctrl_tap1to4gain_dbl_res_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQTAPCTRL_TAP1TO4GAIN_DBL_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqtapctrl_tap5to16gain_dbl_res_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQTAPCTRL_TAP5TO16GAIN_DBL_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvalc_hifreqagcbiasadjust_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvalc_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQVALC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvalc_midbandzero_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvalcl_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQVALCL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvalcl_lofreqagcgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap01gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap02gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap03gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap04gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap05gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap06gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap07gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap08gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap09gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap10gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap11gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap12gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap13gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap14gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap15gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap16gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQVALD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvale_caldfeedgetap02gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvale_caldfeedgetap03gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvale_caldfeedgetap04gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvale_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQVALE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1cal_clear_mask_attr == 13'd8184
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_aux0_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_aux1_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_d0_bot_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_d0_mid_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_d0_top_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_d1_bot_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_d1_mid_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_d1_top_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_e0_lo_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_e1_lo_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2cal_clear_mask_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_aux0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_aux1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_d0_bot_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_d0_mid_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_d0_top_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_d1_bot_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_d1_mid_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_d1_top_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_e0_lo_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_e1_lo_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfgcal_calfsmmeas_dlycount_attr == 10'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfgcal_fsmmaxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfgcal_lpfax_coarse_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfgcal_lpfax_fine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxhifreqagc_inputcmadjust_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxhifreqagc_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXHIFREQAGC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcal_clear_mask_attr == 13'd8191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_ctlecmnmode_stg1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_ctlecmnmode_stg2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_ctlecmnmode_stg3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_aux0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_aux1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_d0_bot_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_d0_mid_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_d0_top_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_d1_bot_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_d1_mid_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_d1_top_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_e0_lo_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_e1_lo_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmargin_flx_jit_offset_shift_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmargin_jit_disable_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmargin_jit_enable_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmargin_jit_offset_shift_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmargin_jit_setup_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmargin_volt_comp_mask_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmargin_volt_forcel2d_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXMARGIN_VOLT_FORCEL2D_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmargin_volt_offset_shift_d0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmargin_volt_offset_shift_d1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmarginin_direction_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXMARGININ_DIRECTION_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmarginin_flx_jit_offset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmarginin_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXMARGININ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmarginin_mode_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXMARGININ_MODE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmarginin_offset_change_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXMARGININ_OFFSET_CHANGE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmarginin_offset_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmarginin_start_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXMARGININ_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxsum_cm_vref_attr == 9'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxsum_summer_cmfb_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXSUM_SUMMER_CMFB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxsum_summer_cmfb_ibias_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_dfeyadj_aging_cdrlock2data_loc_ov_attr == SERDES_IP_LANE_RXEQ_L3_CFG_DFEYADJ_AGING_CDRLOCK2DATA_LOC_OV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_dfeyadj_aging_cdrlock2data_loc_ov_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_DFEYADJ_AGING_CDRLOCK2DATA_LOC_OV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_dfeyadj_aging_div_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_dfeyadj_aging_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_DFEYADJ_AGING_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxagc_ctlecomp_filterbypass_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXAGC_CTLECOMP_FILTERBYPASS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxagc_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXAGC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxbgcal_calfsmmeas_dlycount_attr == 10'd392
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxbgcal_clear_mask_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxbgcal_fsmmaxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxbgcal_lpfax_coarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxbgcal_lpfax_fine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxbgcalorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxbgcalorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxbgcalorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_calbiasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_calbiasboost_use_lut_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_CALBIASBOOST_USE_LUT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_callbbiasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_callbbiasboost_use_lut_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_CALLBBIASBOOST_USE_LUT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlecomp_filterbypass_smplrcal_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_CTLECOMP_FILTERBYPASS_SMPLRCAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg1_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg2_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg3_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctleinput_probe_mux_smplrcal_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg1_probe_mux_en_smplrcal_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg1_state_en_smplrcal_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg1_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg1_state_en_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg1_state_en_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg1_use_stg2code_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_CTLESTG1_USE_STG2CODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg2_probe_mux_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg2_state_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg2_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg2_state_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg2_state_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg3_probe_mux_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg3_state_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg3_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg3_state_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg3_state_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_hifreqagc_n5targin_sel_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_HIFREQAGC_N5TARGIN_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_inputcmadjust_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_inputcmadjust_stg1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_inputcmadjust_stg2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_inputcmadjust_stg3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_sdimode_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_SDIMODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_smplroffset_aux0_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_smplroffset_aux1_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_smplroffset_d0_bot_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_smplroffset_d0_mid_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_smplroffset_d0_top_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_smplroffset_d1_bot_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_smplroffset_d1_mid_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_smplroffset_d1_top_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_tfrtrim_outen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_tfrtrim_outen_tfrcal_stg1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_tfrtrim_outen_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_tfrtrim_outen_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalalign_iqclk_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalalign_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALALIGN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctl_cal_abort_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALCTL_CAL_ABORT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctl_cal_type_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctl_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALCTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctl_post_delay_pow2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctl_pre_delay_pow2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecalctrl_input_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecalctrl_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALCTLECALCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecalctrl_stg1_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecalctrl_stg1_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecalctrl_stg2_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecalctrl_stg2_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecalctrl_stg3_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecalctrl_stg3_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecompoffset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecompoffset_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALCTLECOMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecompoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALCTLECOMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecompoffsetfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALCTLECOMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecompoffsetfsmout_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaldutybkgnd_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALDUTYBKGND_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaldutybkgnd_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALDUTYBKGND_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_biasboost_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_hf1deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_hf1resdcgain_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_hf2cap_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_hf2deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_hf2reszero_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_hf3deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_hf3resdcgain_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_hf4deq_gray_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALEQ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_ctlecmnmode_stg1_finish_side_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALFSM_CTLECMNMODE_STG1_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_ctlecmnmode_stg1_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_ctlecmnmode_stg2_finish_side_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALFSM_CTLECMNMODE_STG2_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_ctlecmnmode_stg2_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_ctlecmnmode_stg3_finish_side_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALFSM_CTLECMNMODE_STG3_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_ctlecmnmode_stg3_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_runcount_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_smplroffset_finish_side_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALFSM_SMPLROFFSET_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_smplroffset_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsmmeas_ctlecmnmode_stg1_invert_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALFSMMEAS_CTLECMNMODE_STG1_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsmmeas_ctlecmnmode_stg2_invert_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALFSMMEAS_CTLECMNMODE_STG2_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsmmeas_ctlecmnmode_stg3_invert_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALFSMMEAS_CTLECMNMODE_STG3_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsmmeas_smplroffset_invert_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALFSMMEAS_SMPLROFFSET_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_ctlecmnmode_stg1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_ctlecmnmode_stg2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_ctlecmnmode_stg3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_aux0_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_aux1_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_d0_bot_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_d0_mid_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_d0_top_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_d1_bot_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_d1_mid_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_d1_top_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_e0_lo_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_e1_lo_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeas_pow2count_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasin_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasin_req_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASIN_REQ_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasin_req_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASIN_REQ_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasin_req_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASIN_REQ_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasout_ack_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASOUT_ACK_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasout_ack_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASOUT_ACK_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasout_ack_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASOUT_ACK_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasout_avg_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASOUT_AVG_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasout_avg_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASOUT_AVG_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasout_avg_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASOUT_AVG_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasout_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaloffsetfsmout_auxdatacomp_offset_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALOFFSETFSMOUT_AUXDATACOMP_OFFSET_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaloffsetfsmout_boost_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALOFFSETFSMOUT_BOOST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaloffsetfsmout_edgecomp_offset_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALOFFSETFSMOUT_EDGECOMP_OFFSET_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaloffsetfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalset_cal_clear_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalset_cal_mode_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALSET_CAL_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalset_cal_req_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALSET_CAL_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalset_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalstat_cal_ack_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALSTAT_CAL_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalstat_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalsummerfsmout_comp_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALSUMMERFSMOUT_COMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalsummerfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALSUMMERFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcdrphd_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCDRPHD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcdrphd_override_ignore_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCDRPHD_OVERRIDE_IGNORE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_caloffset_range_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_calstg1offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_calstg1offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_calstg2offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_calstg2offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_calstg3offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_calstg3offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_dccouple_sigpath_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCTLE_DCCOUPLE_SIGPATH_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_lbbiasboost_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCTLE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_stg1tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_stg2tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_stg3tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_tfrtrim_outmem_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCTLE_TFRTRIM_OUTMEM_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_tfrtrim_outpen_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCTLE_TFRTRIM_OUTPEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctledc_dccouple_tgate_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCTLEDC_DCCOUPLE_TGATE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctledc_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCTLEDC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxdfe_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXDFE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxdfe_tapgain_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxdfepam_enable_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXDFEPAM_ENABLE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxdfepam_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXDFEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxdpifjit_enb_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXDPIFJIT_ENB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxdpifjit_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXDPIFJIT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxdpifjit_offset_locovr_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqadj_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQADJ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqadj_yadjust_aux0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqadj_yadjust_aux1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqadj_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqadj_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqadj_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqadj_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqadj_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqadj_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqauxxor_amux_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqauxxor_dmux_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqauxxor_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQAUXXOR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcal2flx_pstate_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCAL2FLX_PSTATE_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcal2flx_rate_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCAL2FLX_RATE_MASK_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_16a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_16b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_16c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_16d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_16e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_1a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_1b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_1c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_1d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_1e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_2a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_2b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_2c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_2d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_2e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_4a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_4b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_4c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_4d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_4e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_8a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_8b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_8c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_8d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_8e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_16a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_16b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_16c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_16d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_16e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_1a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_1b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_1c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_1d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_1e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_2a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_2b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_2c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_2d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_2e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_4a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_4b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_4c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_4d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_4e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_8a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_8b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_8c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_8d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_8e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_16a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_16b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_16c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_16d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_16e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_1a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_1b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_1c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_1d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_1e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_2a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_2b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_2c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_2d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_2e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_4a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_4b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_4c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_4d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_4e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_8a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_8b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_8c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_8d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_8e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcals_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCALS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcals_offset_datasummer0_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcals_offset_datasummer0_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcals_offset_datasummer1_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcals_offset_datasummer1_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcals_offset_edgesummer0_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcals_offset_edgesummer0_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcals_offset_edgesummer1_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcals_offset_edgesummer1_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcdr_force_ltr_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCDR_FORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcdr_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCDR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqctl_clear_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCTL_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqctl_fg_run_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCTL_FG_RUN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqctlelut_hifreqagcres_ovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCTLELUT_HIFREQAGCRES_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqctlelut_hifreqvgagain_ovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCTLELUT_HIFREQVGAGAIN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqctls_oddeven_tapgain_sel_inv_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCTLS_ODDEVEN_TAPGAIN_SEL_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqctls_static_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCTLS_STATIC_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqdat_aux_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQDAT_AUX_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqdat_edge_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQDAT_EDGE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqdatactl_auxswap_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqdatactl_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQDATACTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqdatarate_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQDATARATE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqdatarate_rx_rate_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqdfeyadj_agingl2r_delay_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqdfeyadj_agingl2r_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQDFEYADJ_AGINGL2R_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqedgeadj_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEDGEADJ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqedgeadj_yadjust_edge0lo_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqedgeadj_yadjust_edge1lo_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm2flx_ehm_done_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHM2FLX_EHM_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm2flx_ehm_done_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHM2FLX_EHM_DONE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm2flx_ehm_err_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHM2FLX_EHM_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm2flx_ehm_err_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHM2FLX_EHM_ERR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm2flx_ehm_fom_locovr_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHM2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_data_extshift_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHM_DATA_EXTSHIFT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_distance_th_50p_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_distance_th_rate_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_err_mask_vf00_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_err_mask_vf01_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_event_rate_vf00_attr == 32'd67108864
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_event_rate_vf01_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_general_in_vf00_attr == 32'd5505024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_general_in_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_lms_th_50p_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_lms_th_rate_attr == 20'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_mask_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_no_change_th_50p_attr == 12'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_no_change_th_rate_attr == 12'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_reflections_num_50p_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_reflections_num_rate_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_slicer_swap_cb_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHM_SLICER_SWAP_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_sym_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_sym_dly_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_tap_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_test_aux_slicer_val_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_test_hits_th_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjaux_ehm_yadjust_aux0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjaux_ehm_yadjust_aux1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjaux_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJAUX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjauxen_ehm_aux_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJAUXEN_EHM_AUX_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjauxen_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJAUXEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjauxltch_aux_yadj_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJAUXLTCH_AUX_YADJ_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjauxltch_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJAUXLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdata_ehm_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdata_ehm_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdata_ehm_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdata_ehm_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdata_ehm_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdata_ehm_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdata_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdataen_ehm_data_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJDATAEN_EHM_DATA_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdataen_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJDATAEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdataltch_data_yadj_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJDATALTCH_DATA_YADJ_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdataltch_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJDATALTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2ehm_ehm_run_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2EHM_EHM_RUN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2ehm_ehm_run_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2EHM_EHM_RUN_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2lms_coarse_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2LMS_COARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2lms_ctrl_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2LMS_CTRL_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2lms_dfecore_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2LMS_DFECORE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2lms_force_evrefupd_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2LMS_FORCE_EVREFUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2lms_freeze_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2LMS_FREEZE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2lms_incr_decr_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2LMS_INCR_DECR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2lms_mu_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2LMS_MU_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2lms_rst_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2LMS_RST_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2ofc_ofc_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2OFC_OFC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2ofc_ofc_en_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2OFC_OFC_EN_OVRDEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx_pcs_rxeq_clr_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX_PCS_RXEQ_CLR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx_pcs_rxeq_start_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX_PCS_RXEQ_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx_pcs_rxeq_static_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX_PCS_RXEQ_STATIC_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx_rxrate2pcie1_map_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx_rxrate2pcie2_map_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx_rxrate2pcie3_map_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx_rxrate2pcie4_map_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxehmdata_ehm_data_slc_sel_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXEHMDATA_EHM_DATA_SLC_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxehmdata_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXEHMDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxfsm_generalpurpose_reg_in_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxfsm_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXFSM_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxfsm_pause_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXFSM_PAUSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxfsm_state_obs_hold_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXFSM_STATE_OBS_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxfsm_state_obs_sel_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXFSM_STATE_OBS_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxltr_force_ltr_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXLTR_FORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxltr_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXLTR_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxpcsrxeyediag_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXPCSRXEYEDIAG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxpcsrxeyediag_start_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXPCSRXEYEDIAG_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxsigdet_sel_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXSIGDET_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqfsm2ofc_ofc_cal_req_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFSM2OFC_OFC_CAL_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqfsm2ofc_ofc_cal_req_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFSM2OFC_OFC_CAL_REQ_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_16a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_16b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_16c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_16d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_16e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_1a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_1b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_1c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_1d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_1e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_2a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_2b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_2c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_2d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_2e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_4a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_4b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_4c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_4d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_4e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_8a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_8b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_8c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_8d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_8e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_done_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmax_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmax_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_SATMAX_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmax_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmax_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmax_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_SATMAX_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmax_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_SATMAX_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmax_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_SATMAX_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmin_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmin_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_SATMIN_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmin_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmin_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmin_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_SATMIN_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmin_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_SATMIN_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmin_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_SATMIN_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_stable_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_stable_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_STABLE_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_stable_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_stable_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_stable_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_STABLE_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_stable_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_STABLE_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_stable_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_STABLE_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsupd_chng_ack_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSUPD_CHNG_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsupd_chng_req_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSUPD_CHNG_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsupd_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSUPD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjaux_lms_vref0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjaux_lms_vref1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjaux_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJAUX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjauxen_lms_aux_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJAUXEN_LMS_AUX_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjauxen_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJAUXEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjauxltch_lms_aux_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJAUXLTCH_LMS_AUX_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjauxltch_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJAUXLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdata_lms_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdata_lms_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdata_lms_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdata_lms_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdata_lms_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdata_lms_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdata_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdataen_lms_data_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJDATAEN_LMS_DATA_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdataen_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJDATAEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdataltch_lms_data_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJDATALTCH_LMS_DATA_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdataltch_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJDATALTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjedge_lms_yadjust_edge0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjedge_lms_yadjust_edge1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjedge_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJEDGE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjedgeen_lms_edge_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJEDGEEN_LMS_EDGE_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjedgeen_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJEDGEEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjedgeltch_lms_edge_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJEDGELTCH_LMS_EDGE_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjedgeltch_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJEDGELTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqltch_dfe_aux_yadj_b_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLTCH_DFE_AUX_YADJ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqltch_dfe_b_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLTCH_DFE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqltch_dfe_data_yadj_b_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLTCH_DFE_DATA_YADJ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqltch_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqltchc_auxswap_b_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLTCHC_AUXSWAP_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqltchc_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLTCHC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofc2flx_ofc_cal_done_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQOFC2FLX_OFC_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofc2flx_ofc_cal_done_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQOFC2FLX_OFC_CAL_DONE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_ctle_rxinpprobemuxen_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_ctle_rxstg1_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_ctle_rxstg1probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_ctle_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_ctle_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_ctle_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_ctle_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_summer_rxinpprobemuxen_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_summer_rxstg1_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_summer_rxstg1probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_summer_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_summer_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_summer_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_summer_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_time_h_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_time_l_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_ctle_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_ctle_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_ctle_rxstg1probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_ctle_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_ctle_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_ctle_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_ctle_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_summer_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_summer_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_summer_rxstg1probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_summer_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_summer_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_summer_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_summer_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_time_l_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_compsel_ctle_st1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_compsel_ctle_st2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_compsel_ctle_st3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_compsel_idle_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_compsel_sa_d0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_compsel_sa_d1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_compsel_sa_e0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_compsel_sa_e1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_invert_comp_fb_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_lpexitcal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_lpexitcal_time_l_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_adapt_en_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_adapt_thr_sel_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_cal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_cal_thr_sel_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_data_disp_sticky_clr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQOFCCFG_OFC_DATA_DISP_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_disparity_disable_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQOFCCFG_OFC_DISPARITY_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_disparity_leak_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_disparity_thr_sel_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_lpexitcal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_lpf_bypass_en_cb_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQOFCCFG_OFC_LPF_BYPASS_EN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_ratechangecal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_pre_timer_setting_pow2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ratechangecal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ratechangecal_time_l_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_rxinpprobemuxen_idle_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_rxstg1_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_rxstg1probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_rxstg2_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_rxstg2probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_rxstg3_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_rxstg3probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqout_init_restore_avail_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQOUT_INIT_RESTORE_AVAIL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqprecal_code_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqprecal_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQPRECAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_hf1deq_dir_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_BOOSTLUT_HF1DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_hf2deq_dir_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_BOOSTLUT_HF2DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_hf2reszero_dir_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_BOOSTLUT_HF2RESZERO_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_hf3deq_dir_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_BOOSTLUT_HF3DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_idx_hf1deq_vf00_attr == 32'd599186
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_idx_hf1deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_idx_hf2deq_vf00_attr == 32'd1198372
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_idx_hf2deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_idx_hf2reszero_vf00_attr == 32'd4290772992
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_idx_hf2reszero_vf01_attr == 21'd2097151
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_idx_hf3deq_vf00_attr == 32'd2396744
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_idx_hf3deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_init_hf1deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_init_hf2deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_init_hf2reszero_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_init_hf3deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_cal_hifreqagcres_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_cal_hifreqvgagain_attr == 7'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_cal_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_cal_yadjust_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_biasboost_dir_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_GAINLUT_BIASBOOST_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_hf1resdcgain_dir_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_GAINLUT_HF1RESDCGAIN_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_hf3resdcgain_dir_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_GAINLUT_HF3RESDCGAIN_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_biasboost_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_biasboost_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_biasboost_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf00_attr == 32'd2863311530
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf01_attr == 32'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf00_attr == 32'd1431655764
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf01_attr == 32'd1431655765
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_lbbiasboost_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_lbbiasboost_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_lbbiasboost_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_init_biasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_init_hf1resdcgain_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_init_hf3resdcgain_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_init_lbbiasboost_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_lbbiasboost_dir_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_GAINLUT_LBBIASBOOST_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_latch_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref0_initval_attr == 9'd61
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref1_initval_attr == 9'd191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref2_initval_attr == 9'd321
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref3_initval_attr == 9'd451
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_decr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_AUXVREF_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_frac_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_AUXVREF_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_frac_reset_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_incr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_AUXVREF_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_incr_decr_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_pam4adj_swizzle_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_AUXVREF_PAM4ADJ_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_AUXVREF_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_pol_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_single_step_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_AUXVREF_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_stable_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_AUXVREF_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_AUXVREF_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_targ_0_hi_attr == 9'd149
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_targ_0_lo_attr == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_auxvref_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_auxvref_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_dfe_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_dfe_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_edge_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_edge_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_edgevref_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_edgevref_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_iqalign_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_iqalign_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_level_vga_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_vga_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_vga_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_blockcount_fast_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_BLOCKCOUNT_FAST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_coarse_detect_clear_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_COARSE_DETECT_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_coarse_detect_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_COARSE_DETECT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_continuous_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_CONTINUOUS_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_datastats_incr_decr_swizzle_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_DATASTATS_INCR_DECR_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_datastats_pol_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_DATASTATS_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_datastats_thres_attr == 16'd1023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe1_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe2_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe3_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe4p_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_core_sel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_decr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_DFE_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_frac_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_DFE_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_frac_reset_mask_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_incr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_DFE_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_incr_decr_mask_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_inner_lvl_filter_en_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_DFE_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_pol_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_single_step_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_DFE_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_stable_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_DFE_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_DFE_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_targtap1_attr == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_targtap2_attr == 7'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_targtap3_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_targtap4_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_decr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGE_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_frac_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGE_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_frac_reset_mask_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_incr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGE_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_incr_decr_mask_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGE_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_pol_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_single_step_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGE_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_stable_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGE_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGE_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_decr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGEVREF_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_frac_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGEVREF_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGEVREF_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_incr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGEVREF_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_initval_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGEVREF_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_pol_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGEVREF_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_single_step_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGEVREF_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_stable_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGEVREF_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGEVREF_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_fast_blockcnt_attr == 16'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_filter_mode_auxvref_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_filter_mode_dfe_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_filter_mode_edge_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_filter_mode_edgevref_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_filter_mode_iqalign_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_filter_mode_vga_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_freeze_auxvrefupd_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_freeze_dfeupd_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_freeze_edgeupd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_freeze_edgevrefupd_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_FREEZE_EDGEVREFUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_freeze_forcebg_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_FREEZE_FORCEBG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_freeze_hifreqagcupd_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_FREEZE_HIFREQAGCUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_freeze_iqalignupd_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_FREEZE_IQALIGNUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_freeze_lofreqagcupd_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_FREEZE_LOFREQAGCUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_freeze_vgaupd_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_FREEZE_VGAUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_gated_update_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_GATED_UPDATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_accum_count_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_accum_level_en_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_decr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_HIFREQAGC_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_frac_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_HIFREQAGC_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_HIFREQAGC_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_incr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_HIFREQAGC_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_n1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_n2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_n3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_n4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_n5_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_HIFREQAGC_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_pol_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_HIFREQAGC_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_single_step_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_HIFREQAGC_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_stable_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_HIFREQAGC_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_HIFREQAGC_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_init_adapt_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_INIT_ADAPT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_decr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_IQALIGN_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_frac_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_IQALIGN_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_IQALIGN_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_incr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_IQALIGN_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_IQALIGN_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_pol_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_IQALIGN_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_single_step_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_IQALIGN_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_stable_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_IQALIGN_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_IQALIGN_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_targ_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_itercount_attr == 10'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_latch_delay_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_latch_prepost_delay_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_decr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOFREQAGC_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_frac_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOFREQAGC_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOFREQAGC_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_incr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOFREQAGC_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOFREQAGC_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_pol_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOFREQAGC_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_single_step_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOFREQAGC_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_stable_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOFREQAGC_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOFREQAGC_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_logain_auxvref_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOGAIN_AUXVREF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_logain_dfe_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_logain_edge_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_logain_edgevref_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOGAIN_EDGEVREF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_logain_hifreqagc_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOGAIN_HIFREQAGC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_logain_iqalign_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOGAIN_IQALIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_logain_lofreqagc_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOGAIN_LOFREQAGC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_logain_vga_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOGAIN_VGA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_auxvref_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_dfe1_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_dfe23_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_dfe4p_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_edge2_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_edge3_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_edge4_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_edgevref_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_hifreqagc_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_iqalign_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_lofreqagc_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_vga_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_nrz_to_pam4_mode_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_NRZ_TO_PAM4_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_slow_blockcnt_attr == 16'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_start_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_tsettle_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_accum_count_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_accum_level_en_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_decr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_frac_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_incr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_mode_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_pol_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_single_step_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_stable_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_yadjdata_mid_clamp_zero_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_YADJDATA_MID_CLAMP_ZERO_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lofreqagcgain_sel_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LOFREQAGCGAIN_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_caldfedatatap1gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_caldfedatatap2gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_caldfedatatap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_caldfedatatap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_caldfeedgetap2gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_caldfeedgetap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_caldfeedgetap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_lofreqagcgain_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_caldfedatatap1gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_caldfedatatap1gain_attr == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_caldfedatatap1gain_attr == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_shift_auxshft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_shift_capture_trigger_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_SHIFT_CAPTURE_TRIGGER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_shift_clear_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_SHIFT_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_shift_dat_bitsel_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_SHIFT_DAT_BITSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_shift_datashft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_shift_edgeshft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_shift_edgeshft_nrz8b10b_pam16b20b_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_shift_polarity_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_SHIFT_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap10gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap11gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap12gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap13gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap14gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap15gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap16gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap1gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap2gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap5gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap6gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap7gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap8gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap9gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfeedgetap2gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfeedgetap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfeedgetap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_hifreqvgagain_attr == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_auxvref0_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_auxvref1_attr == 9'd223
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_auxvref2_attr == 9'd339
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_auxvref3_attr == 9'd456
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_caldfedatatap1gain_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_caldfeedgetap2gain_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_calhifreqagcres_attr == 6'd52
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_callofreqagcgain_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_edgevref_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_hifreqvgagain_attr == 7'd77
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_iqalign_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_auxvref0_attr == 9'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_auxvref1_attr == 9'd173
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_auxvref2_attr == 9'd289
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_auxvref3_attr == 9'd356
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_caldfedatatap1gain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_caldfeedgetap2gain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_calhifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_callofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_edgevref_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_iqalign_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqsetnrztopam4_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSETNRZTOPAM4_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqsetnrztopam4_switch_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSETNRZTOPAM4_SWITCH_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqsigdet_pause_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSIGDET_PAUSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqspare0_attr == 32'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqspare1_attr == 32'd15871
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqspare2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqsync2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSYNC2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqsync2flx_rxdatapath_ready_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSYNC2FLX_RXDATAPATH_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqtapctrl_data_tap13to16_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQTAPCTRL_DATA_TAP13TO16_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqtapctrl_data_tap1to4_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQTAPCTRL_DATA_TAP1TO4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqtapctrl_data_tap5to8_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQTAPCTRL_DATA_TAP5TO8_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqtapctrl_data_tap9to12_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQTAPCTRL_DATA_TAP9TO12_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqtapctrl_edge_tap_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQTAPCTRL_EDGE_TAP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqtapctrl_tap1to4gain_dbl_res_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQTAPCTRL_TAP1TO4GAIN_DBL_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqtapctrl_tap5to16gain_dbl_res_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQTAPCTRL_TAP5TO16GAIN_DBL_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvalc_hifreqagcbiasadjust_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvalc_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQVALC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvalc_midbandzero_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvalcl_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQVALCL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvalcl_lofreqagcgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap01gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap02gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap03gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap04gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap05gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap06gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap07gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap08gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap09gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap10gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap11gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap12gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap13gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap14gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap15gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap16gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQVALD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvale_caldfeedgetap02gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvale_caldfeedgetap03gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvale_caldfeedgetap04gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvale_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQVALE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1cal_clear_mask_attr == 13'd8184
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_aux0_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_aux1_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_d0_bot_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_d0_mid_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_d0_top_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_d1_bot_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_d1_mid_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_d1_top_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_e0_lo_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_e1_lo_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2cal_clear_mask_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_aux0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_aux1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_d0_bot_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_d0_mid_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_d0_top_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_d1_bot_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_d1_mid_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_d1_top_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_e0_lo_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_e1_lo_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfgcal_calfsmmeas_dlycount_attr == 10'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfgcal_fsmmaxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfgcal_lpfax_coarse_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfgcal_lpfax_fine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxhifreqagc_inputcmadjust_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxhifreqagc_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXHIFREQAGC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcal_clear_mask_attr == 13'd8191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_ctlecmnmode_stg1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_ctlecmnmode_stg2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_ctlecmnmode_stg3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_aux0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_aux1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_d0_bot_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_d0_mid_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_d0_top_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_d1_bot_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_d1_mid_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_d1_top_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_e0_lo_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_e1_lo_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmargin_flx_jit_offset_shift_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmargin_jit_disable_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmargin_jit_enable_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmargin_jit_offset_shift_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmargin_jit_setup_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmargin_volt_comp_mask_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmargin_volt_forcel2d_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXMARGIN_VOLT_FORCEL2D_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmargin_volt_offset_shift_d0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmargin_volt_offset_shift_d1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmarginin_direction_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXMARGININ_DIRECTION_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmarginin_flx_jit_offset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmarginin_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXMARGININ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmarginin_mode_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXMARGININ_MODE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmarginin_offset_change_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXMARGININ_OFFSET_CHANGE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmarginin_offset_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmarginin_start_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXMARGININ_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxsum_cm_vref_attr == 9'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxsum_summer_cmfb_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXSUM_SUMMER_CMFB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxsum_summer_cmfb_ibias_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_done_pwr2_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_apb_dwmask_muxd0_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_apb_dwmask_muxd1_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_apb_dwmask_muxd2_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_apb_dwmask_muxd3_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_apb_dwmask_muxd4_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_a2f_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_a2f_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_a2f_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_a2f_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_a2f_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd0_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd1_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd2_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd3_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd4_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd0_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd1_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd2_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd3_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd4_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd0_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd1_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd2_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd3_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd4_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd0_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd1_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd2_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd3_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd4_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd0_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd1_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd2_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd3_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd4_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_marker_muxd0_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_marker_muxd1_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_marker_muxd2_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_marker_muxd3_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_marker_muxd4_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd0_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd1_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd2_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd3_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd4_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd0_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd1_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd2_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd3_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd0_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd1_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd2_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd3_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd4_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd0_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd3_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd4_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd0_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd2_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd2_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd3_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd4_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd0_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd1_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd2_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd3_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd4_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd0_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd1_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd2_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd3_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd4_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd0_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd1_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd2_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd3_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd4_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd0_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd1_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd2_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd3_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd4_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd2_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd3_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd4_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd0_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd2_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd0_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd0_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd1_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd2_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd3_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd4_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd0_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd1_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd2_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd3_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd4_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd4_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd0_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd1_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd2_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd3_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd4_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd0_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd1_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd2_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd3_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd4_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_lock_thresh_muxd0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_lock_thresh_muxd1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_lock_thresh_muxd2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_lock_thresh_muxd3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_lock_thresh_muxd4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd0_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd1_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd2_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd3_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd4_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchn_offset_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchn_offset_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchn_offset_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchn_offset_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchn_offset_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchp_offset_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchp_offset_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchp_offset_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchp_offset_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchp_offset_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_bypass_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_bypass_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_bypass_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_bypass_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_bypass_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd4_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_step_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_step_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_step_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_step_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_step_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd0_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd1_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd2_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd3_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd4_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd2_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd0_attr == 8'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd1_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd2_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd3_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd4_attr == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd0_attr == 18'd14336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd1_attr == 18'd14336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd2_attr == 18'd14336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd3_attr == 18'd14336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd4_attr == 18'd14336
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd2_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd3_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd4_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_fll_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_fll_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_fll_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_fll_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_fll_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_pll_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_pll_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_pll_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_pll_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_pll_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd0_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd1_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd2_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd4_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd0_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd1_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd3_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd4_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_temp_track_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_temp_track_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_temp_track_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_temp_track_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_temp_track_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd0_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd1_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd2_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd3_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd4_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd0_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd1_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd2_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd3_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd4_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd0_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd1_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd2_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd3_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd4_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd0_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd1_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd2_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd3_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd4_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bb_gain_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bb_gain_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bb_gain_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bb_gain_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bb_gain_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbinlock_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbinlock_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbinlock_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbinlock_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbinlock_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbthresh_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbthresh_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbthresh_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbthresh_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbthresh_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrlhext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrlhext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrlhext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrlhext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrlhext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrllext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrllext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrllext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrllext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrllext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_muxd0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_muxd1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_muxd2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_muxd3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_muxd4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcoditheren_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcoditheren_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcoditheren_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcoditheren_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcoditheren_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofine_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofine_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofine_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofine_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofine_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofinedftsel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofinedftsel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofinedftsel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofinedftsel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofinedftsel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dither_value_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dither_value_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dither_value_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dither_value_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dither_value_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_earlylock_criteria_muxd0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_earlylock_criteria_muxd1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_earlylock_criteria_muxd2_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_earlylock_criteria_muxd3_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_earlylock_criteria_muxd4_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_frac_muxd0_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_frac_muxd1_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_frac_muxd2_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_frac_muxd3_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_frac_muxd4_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd0_attr == 9'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd1_attr == 9'd90
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd2_attr == 9'd54
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd3_attr == 9'd72
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd4_attr == 9'd432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdgain_muxd0_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdgain_muxd1_attr == 8'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdgain_muxd2_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdgain_muxd3_attr == 8'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdgain_muxd4_attr == 8'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fracnen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fracnen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fracnen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fracnen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fracnen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_lock_criteria_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_lock_criteria_muxd1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_lock_criteria_muxd2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_lock_criteria_muxd3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_lock_criteria_muxd4_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_regen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_regen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_regen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_regen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_regen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllock_sel_muxd0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllock_sel_muxd1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllock_sel_muxd2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllock_sel_muxd3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllock_sel_muxd4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdc_fine_res_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdc_fine_res_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdc_fine_res_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdc_fine_res_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdc_fine_res_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdccalexten_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdccalexten_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdccalexten_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdccalexten_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdccalexten_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcroen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcroen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcroen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcroen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcroen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcsel_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcsel_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcsel_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcsel_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcsel_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdctargetcnt_muxd0_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdctargetcnt_muxd1_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdctargetcnt_muxd2_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdctargetcnt_muxd3_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdctargetcnt_muxd4_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tribufctrlext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tribufctrlext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tribufctrlext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tribufctrlext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tribufctrlext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_done_pwr2_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_apb_dwmask_muxd0_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_apb_dwmask_muxd1_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_apb_dwmask_muxd2_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_apb_dwmask_muxd3_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_apb_dwmask_muxd4_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_a2f_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_a2f_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_a2f_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_a2f_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_a2f_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd0_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd1_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd2_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd3_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd4_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd0_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd1_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd2_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd3_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd4_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd0_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd1_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd2_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd3_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd4_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd0_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd1_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd2_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd3_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd4_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd0_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd1_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd2_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd3_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd4_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_marker_muxd0_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_marker_muxd1_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_marker_muxd2_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_marker_muxd3_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_marker_muxd4_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd0_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd1_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd2_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd3_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd4_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd0_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd1_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd2_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd3_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd0_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd1_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd2_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd3_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd4_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd0_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd3_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd4_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd0_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd2_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd2_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd3_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd4_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd0_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd1_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd2_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd3_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd4_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd0_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd1_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd2_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd3_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd4_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd0_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd1_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd2_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd3_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd4_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd0_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd1_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd2_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd3_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd4_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd2_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd3_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd4_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd0_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd2_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd0_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd0_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd1_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd2_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd3_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd4_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd0_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd1_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd2_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd3_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd4_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd4_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd0_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd1_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd2_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd3_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd4_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd0_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd1_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd2_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd3_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd4_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_lock_thresh_muxd0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_lock_thresh_muxd1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_lock_thresh_muxd2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_lock_thresh_muxd3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_lock_thresh_muxd4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd0_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd1_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd2_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd3_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd4_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchn_offset_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchn_offset_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchn_offset_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchn_offset_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchn_offset_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchp_offset_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchp_offset_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchp_offset_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchp_offset_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchp_offset_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_bypass_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_bypass_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_bypass_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_bypass_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_bypass_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd4_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_step_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_step_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_step_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_step_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_step_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd0_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd1_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd2_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd3_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd4_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd2_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd0_attr == 8'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd1_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd2_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd3_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd4_attr == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd0_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd1_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd2_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd3_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd4_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd2_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd3_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd4_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_fll_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_fll_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_fll_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_fll_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_fll_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_pll_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_pll_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_pll_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_pll_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_pll_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd0_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd1_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd2_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd4_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd0_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd1_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd3_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd4_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_temp_track_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_temp_track_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_temp_track_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_temp_track_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_temp_track_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd0_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd1_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd2_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd3_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd4_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd0_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd1_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd2_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd3_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd4_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd0_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd1_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd2_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd3_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd4_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd0_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd1_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd2_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd3_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd4_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bb_gain_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bb_gain_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bb_gain_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bb_gain_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bb_gain_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbinlock_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbinlock_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbinlock_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbinlock_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbinlock_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbthresh_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbthresh_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbthresh_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbthresh_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbthresh_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrlhext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrlhext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrlhext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrlhext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrlhext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrllext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrllext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrllext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrllext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrllext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_muxd0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_muxd1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_muxd2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_muxd3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_muxd4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcoditheren_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcoditheren_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcoditheren_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcoditheren_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcoditheren_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofine_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofine_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofine_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofine_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofine_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofinedftsel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofinedftsel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofinedftsel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofinedftsel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofinedftsel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dither_value_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dither_value_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dither_value_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dither_value_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dither_value_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_earlylock_criteria_muxd0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_earlylock_criteria_muxd1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_earlylock_criteria_muxd2_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_earlylock_criteria_muxd3_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_earlylock_criteria_muxd4_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_frac_muxd0_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_frac_muxd1_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_frac_muxd2_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_frac_muxd3_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_frac_muxd4_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd0_attr == 9'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd1_attr == 9'd45
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd2_attr == 9'd27
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd3_attr == 9'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd4_attr == 9'd216
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdgain_muxd0_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdgain_muxd1_attr == 8'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdgain_muxd2_attr == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdgain_muxd3_attr == 8'd23
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdgain_muxd4_attr == 8'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fracnen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fracnen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fracnen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fracnen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fracnen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_lock_criteria_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_lock_criteria_muxd1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_lock_criteria_muxd2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_lock_criteria_muxd3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_lock_criteria_muxd4_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_regen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_regen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_regen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_regen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_regen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllock_sel_muxd0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllock_sel_muxd1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllock_sel_muxd2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllock_sel_muxd3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllock_sel_muxd4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdc_fine_res_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdc_fine_res_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdc_fine_res_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdc_fine_res_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdc_fine_res_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdccalexten_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdccalexten_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdccalexten_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdccalexten_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdccalexten_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcroen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcroen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcroen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcroen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcroen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcsel_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcsel_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcsel_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcsel_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcsel_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdctargetcnt_muxd0_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdctargetcnt_muxd1_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdctargetcnt_muxd2_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdctargetcnt_muxd3_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdctargetcnt_muxd4_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tribufctrlext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tribufctrlext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tribufctrlext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tribufctrlext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tribufctrlext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_done_pwr2_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_apb_dwmask_muxd0_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_apb_dwmask_muxd1_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_apb_dwmask_muxd2_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_apb_dwmask_muxd3_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_apb_dwmask_muxd4_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_a2f_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_a2f_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_a2f_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_a2f_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_a2f_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd0_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd1_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd2_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd3_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd4_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd0_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd1_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd2_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd3_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd4_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd0_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd1_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd2_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd3_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd4_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd0_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd1_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd2_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd3_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd4_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd0_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd1_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd2_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd3_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd4_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_marker_muxd0_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_marker_muxd1_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_marker_muxd2_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_marker_muxd3_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_marker_muxd4_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd0_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd1_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd2_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd3_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd4_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd0_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd1_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd2_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd3_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd0_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd1_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd2_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd3_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd4_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd0_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd3_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd4_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd0_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd2_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd2_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd3_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd4_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd0_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd1_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd2_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd3_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd4_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd0_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd1_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd2_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd3_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd4_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd0_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd1_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd2_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd3_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd4_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd0_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd1_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd2_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd3_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd4_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd2_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd3_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd4_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd0_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd2_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd0_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd0_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd1_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd2_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd3_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd4_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd0_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd1_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd2_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd3_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd4_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd4_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd0_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd1_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd2_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd3_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd4_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd0_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd1_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd2_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd3_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd4_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_lock_thresh_muxd0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_lock_thresh_muxd1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_lock_thresh_muxd2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_lock_thresh_muxd3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_lock_thresh_muxd4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd0_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd1_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd2_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd3_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd4_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchn_offset_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchn_offset_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchn_offset_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchn_offset_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchn_offset_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchp_offset_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchp_offset_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchp_offset_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchp_offset_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchp_offset_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_bypass_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_bypass_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_bypass_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_bypass_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_bypass_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd4_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_step_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_step_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_step_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_step_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_step_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd0_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd1_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd2_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd3_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd4_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd2_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd0_attr == 8'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd1_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd2_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd3_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd4_attr == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd0_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd1_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd2_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd3_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd4_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd2_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd3_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd4_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_fll_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_fll_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_fll_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_fll_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_fll_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_pll_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_pll_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_pll_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_pll_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_pll_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd0_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd1_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd2_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd4_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd0_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd1_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd3_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd4_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_temp_track_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_temp_track_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_temp_track_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_temp_track_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_temp_track_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd0_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd1_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd2_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd3_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd4_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd0_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd1_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd2_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd3_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd4_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd0_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd1_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd2_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd3_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd4_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd0_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd1_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd2_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd3_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd4_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bb_gain_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bb_gain_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bb_gain_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bb_gain_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bb_gain_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbinlock_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbinlock_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbinlock_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbinlock_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbinlock_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbthresh_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbthresh_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbthresh_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbthresh_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbthresh_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrlhext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrlhext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrlhext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrlhext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrlhext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrllext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrllext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrllext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrllext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrllext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_muxd0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_muxd1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_muxd2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_muxd3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_muxd4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcoditheren_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcoditheren_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcoditheren_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcoditheren_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcoditheren_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofine_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofine_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofine_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofine_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofine_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofinedftsel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofinedftsel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofinedftsel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofinedftsel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofinedftsel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dither_value_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dither_value_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dither_value_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dither_value_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dither_value_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_earlylock_criteria_muxd0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_earlylock_criteria_muxd1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_earlylock_criteria_muxd2_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_earlylock_criteria_muxd3_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_earlylock_criteria_muxd4_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_frac_muxd0_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_frac_muxd1_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_frac_muxd2_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_frac_muxd3_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_frac_muxd4_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd0_attr == 9'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd1_attr == 9'd45
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd2_attr == 9'd27
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd3_attr == 9'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd4_attr == 9'd216
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdgain_muxd0_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdgain_muxd1_attr == 8'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdgain_muxd2_attr == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdgain_muxd3_attr == 8'd23
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdgain_muxd4_attr == 8'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fracnen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fracnen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fracnen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fracnen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fracnen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_lock_criteria_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_lock_criteria_muxd1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_lock_criteria_muxd2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_lock_criteria_muxd3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_lock_criteria_muxd4_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_regen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_regen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_regen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_regen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_regen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllock_sel_muxd0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllock_sel_muxd1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllock_sel_muxd2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllock_sel_muxd3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllock_sel_muxd4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdc_fine_res_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdc_fine_res_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdc_fine_res_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdc_fine_res_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdc_fine_res_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdccalexten_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdccalexten_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdccalexten_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdccalexten_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdccalexten_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcroen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcroen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcroen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcroen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcroen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcsel_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcsel_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcsel_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcsel_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcsel_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdctargetcnt_muxd0_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdctargetcnt_muxd1_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdctargetcnt_muxd2_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdctargetcnt_muxd3_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdctargetcnt_muxd4_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tribufctrlext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tribufctrlext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tribufctrlext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tribufctrlext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tribufctrlext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_done_pwr2_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_apb_dwmask_muxd0_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_apb_dwmask_muxd1_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_apb_dwmask_muxd2_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_apb_dwmask_muxd3_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_apb_dwmask_muxd4_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_a2f_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_a2f_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_a2f_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_a2f_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_a2f_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd0_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd1_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd2_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd3_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd4_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd0_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd1_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd2_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd3_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd4_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd0_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd1_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd2_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd3_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd4_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd0_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd1_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd2_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd3_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd4_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd0_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd1_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd2_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd3_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd4_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_marker_muxd0_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_marker_muxd1_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_marker_muxd2_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_marker_muxd3_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_marker_muxd4_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd0_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd1_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd2_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd3_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd4_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd0_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd1_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd2_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd3_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd0_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd1_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd2_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd3_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd4_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd0_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd3_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd4_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd0_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd2_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd2_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd3_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd4_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd0_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd1_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd2_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd3_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd4_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd0_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd1_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd2_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd3_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd4_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd0_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd1_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd2_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd3_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd4_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd0_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd1_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd2_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd3_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd4_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd2_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd3_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd4_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd0_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd2_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd0_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd0_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd1_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd2_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd3_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd4_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd0_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd1_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd2_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd3_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd4_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd4_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd0_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd1_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd2_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd3_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd4_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd0_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd1_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd2_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd3_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd4_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_lock_thresh_muxd0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_lock_thresh_muxd1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_lock_thresh_muxd2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_lock_thresh_muxd3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_lock_thresh_muxd4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd0_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd1_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd2_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd3_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd4_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchn_offset_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchn_offset_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchn_offset_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchn_offset_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchn_offset_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchp_offset_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchp_offset_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchp_offset_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchp_offset_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchp_offset_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_bypass_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_bypass_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_bypass_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_bypass_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_bypass_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd4_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_step_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_step_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_step_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_step_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_step_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd0_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd1_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd2_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd3_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd4_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd2_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd0_attr == 8'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd1_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd2_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd3_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd4_attr == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd0_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd1_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd2_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd3_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd4_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd2_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd3_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd4_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_fll_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_fll_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_fll_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_fll_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_fll_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_pll_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_pll_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_pll_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_pll_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_pll_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd0_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd1_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd2_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd4_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd0_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd1_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd3_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd4_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_temp_track_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_temp_track_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_temp_track_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_temp_track_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_temp_track_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd0_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd1_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd2_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd3_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd4_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd0_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd1_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd2_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd3_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd4_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd0_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd1_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd2_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd3_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd4_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd0_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd1_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd2_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd3_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd4_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bb_gain_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bb_gain_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bb_gain_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bb_gain_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bb_gain_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbinlock_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbinlock_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbinlock_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbinlock_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbinlock_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbthresh_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbthresh_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbthresh_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbthresh_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbthresh_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrlhext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrlhext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrlhext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrlhext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrlhext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrllext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrllext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrllext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrllext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrllext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_muxd0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_muxd1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_muxd2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_muxd3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_muxd4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcoditheren_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcoditheren_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcoditheren_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcoditheren_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcoditheren_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofine_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofine_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofine_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofine_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofine_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofinedftsel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofinedftsel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofinedftsel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofinedftsel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofinedftsel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dither_value_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dither_value_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dither_value_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dither_value_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dither_value_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_earlylock_criteria_muxd0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_earlylock_criteria_muxd1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_earlylock_criteria_muxd2_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_earlylock_criteria_muxd3_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_earlylock_criteria_muxd4_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_frac_muxd0_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_frac_muxd1_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_frac_muxd2_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_frac_muxd3_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_frac_muxd4_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd0_attr == 9'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd1_attr == 9'd45
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd2_attr == 9'd27
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd3_attr == 9'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd4_attr == 9'd216
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdgain_muxd0_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdgain_muxd1_attr == 8'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdgain_muxd2_attr == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdgain_muxd3_attr == 8'd23
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdgain_muxd4_attr == 8'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fracnen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fracnen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fracnen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fracnen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fracnen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_lock_criteria_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_lock_criteria_muxd1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_lock_criteria_muxd2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_lock_criteria_muxd3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_lock_criteria_muxd4_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_regen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_regen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_regen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_regen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_regen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllock_sel_muxd0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllock_sel_muxd1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllock_sel_muxd2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllock_sel_muxd3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllock_sel_muxd4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdc_fine_res_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdc_fine_res_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdc_fine_res_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdc_fine_res_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdc_fine_res_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdccalexten_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdccalexten_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdccalexten_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdccalexten_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdccalexten_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcroen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcroen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcroen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcroen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcroen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcsel_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcsel_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcsel_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcsel_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcsel_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdctargetcnt_muxd0_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdctargetcnt_muxd1_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdctargetcnt_muxd2_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdctargetcnt_muxd3_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdctargetcnt_muxd4_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tribufctrlext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tribufctrlext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tribufctrlext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tribufctrlext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tribufctrlext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_a2f_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_clkouten_cb_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_clkouten_lane_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_en_peak_sense_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_obsmux0_del_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_obsmux1_del_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_pcs40div_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_pll_bypass_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_refclk100div_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_refclk156div_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_sddiv_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_spare_dig2ana_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_ssc_track_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_stay_fll_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_stay_pll_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_temp_track_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_bbinlock_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_dcoditheren_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_fracnen_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_pll_reg_resetb_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_plllc_regen_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_tdc_fine_res_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_tdccalexten_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_tdcdc_en_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_tdcroen_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_a2f_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_clkouten_cb_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_clkouten_lane_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_en_peak_sense_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_obsmux0_del_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_obsmux1_del_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_pcs40div_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_pll_bypass_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_refclk100div_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_refclk156div_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_sddiv_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_spare_dig2ana_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_ssc_track_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_stay_fll_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_stay_pll_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_temp_track_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_bbinlock_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_dcoditheren_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_fracnen_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_pll_reg_resetb_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_plllc_regen_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_tdc_fine_res_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_tdccalexten_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_tdcdc_en_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_tdcroen_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_a2f_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_clkouten_cb_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_clkouten_lane_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_en_peak_sense_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_obsmux0_del_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_obsmux1_del_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_pcs40div_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_pll_bypass_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_refclk100div_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_refclk156div_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_sddiv_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_spare_dig2ana_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_ssc_track_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_stay_fll_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_stay_pll_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_temp_track_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_bbinlock_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_dcoditheren_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_fracnen_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_pll_reg_resetb_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_plllc_regen_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_tdc_fine_res_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_tdccalexten_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_tdcdc_en_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_tdcroen_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_a2f_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_clkouten_cb_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_clkouten_lane_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_en_peak_sense_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_obsmux0_del_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_obsmux1_del_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_pcs40div_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_pll_bypass_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_refclk100div_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_refclk156div_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_sddiv_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_spare_dig2ana_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_ssc_track_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_stay_fll_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_stay_pll_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_temp_track_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_bbinlock_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_dcoditheren_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_fracnen_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_pll_reg_resetb_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_plllc_regen_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_tdc_fine_res_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_tdccalexten_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_tdcdc_en_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_tdcroen_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_a2f_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_clkouten_cb_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_clkouten_lane_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_en_peak_sense_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_obsmux0_del_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_obsmux1_del_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_pcs40div_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_pll_bypass_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_refclk100div_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_refclk156div_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_sddiv_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_spare_dig2ana_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_ssc_track_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_stay_fll_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_stay_pll_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_temp_track_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_bbinlock_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_dcoditheren_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_fracnen_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_pll_reg_resetb_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_plllc_regen_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_tdc_fine_res_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_tdccalexten_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_tdcdc_en_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_tdcroen_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_a2f_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_clkouten_cb_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_clkouten_lane_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_en_peak_sense_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_obsmux0_del_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_obsmux1_del_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_pcs40div_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_pll_bypass_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_refclk100div_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_refclk156div_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_sddiv_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_spare_dig2ana_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_ssc_track_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_stay_fll_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_stay_pll_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_temp_track_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_bbinlock_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_dcoditheren_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_fracnen_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_pll_reg_resetb_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_plllc_regen_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_tdc_fine_res_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_tdccalexten_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_tdcdc_en_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_tdcroen_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_a2f_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_clkouten_cb_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_clkouten_lane_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_en_peak_sense_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_obsmux0_del_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_obsmux1_del_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_pcs40div_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_pll_bypass_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_refclk100div_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_refclk156div_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_sddiv_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_spare_dig2ana_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_ssc_track_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_stay_fll_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_stay_pll_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_temp_track_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_bbinlock_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_dcoditheren_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_fracnen_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_pll_reg_resetb_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_plllc_regen_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_tdc_fine_res_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_tdccalexten_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_tdcdc_en_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_tdcroen_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_a2f_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_clkouten_cb_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_clkouten_lane_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_en_peak_sense_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_obsmux0_del_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_obsmux1_del_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_pcs40div_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_pll_bypass_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_refclk100div_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_refclk156div_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_sddiv_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_spare_dig2ana_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_ssc_track_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_stay_fll_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_stay_pll_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_temp_track_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_bbinlock_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_dcoditheren_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_fracnen_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_pll_reg_resetb_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_plllc_regen_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_tdc_fine_res_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_tdccalexten_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_tdcdc_en_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_tdcroen_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_a2f_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_clkouten_cb_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_clkouten_lane_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_en_peak_sense_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_obsmux0_del_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_obsmux1_del_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_pcs40div_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_pll_bypass_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_refclk100div_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_refclk156div_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_sddiv_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_spare_dig2ana_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_ssc_track_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_stay_fll_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_stay_pll_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_temp_track_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_bbinlock_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_dcoditheren_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_fracnen_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_pll_reg_resetb_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_plllc_regen_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_tdc_fine_res_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_tdccalexten_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_tdcdc_en_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_tdcroen_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_a2f_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_clkouten_cb_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_clkouten_lane_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_en_peak_sense_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_obsmux0_del_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_obsmux1_del_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_pcs40div_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_pll_bypass_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_refclk100div_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_refclk156div_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_sddiv_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_spare_dig2ana_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_ssc_track_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_stay_fll_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_stay_pll_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_temp_track_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_bbinlock_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_dcoditheren_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_fracnen_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_pll_reg_resetb_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_plllc_regen_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_tdc_fine_res_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_tdccalexten_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_tdcdc_en_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_tdcroen_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_a2f_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_clkouten_cb_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_clkouten_lane_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_en_peak_sense_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_obsmux0_del_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_obsmux1_del_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_pcs40div_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_pll_bypass_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_refclk100div_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_refclk156div_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_sddiv_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_spare_dig2ana_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_ssc_track_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_stay_fll_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_stay_pll_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_temp_track_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_bbinlock_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_dcoditheren_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_fracnen_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_pll_reg_resetb_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_plllc_regen_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_tdc_fine_res_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_tdccalexten_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_tdcdc_en_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_tdcroen_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_a2f_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_clkouten_cb_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_clkouten_lane_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_en_peak_sense_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_obsmux0_del_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_obsmux1_del_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_pcs40div_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_pll_bypass_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_refclk100div_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_refclk156div_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_sddiv_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_spare_dig2ana_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_ssc_track_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_stay_fll_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_stay_pll_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_temp_track_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_bbinlock_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_dcoditheren_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_fracnen_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_pll_reg_resetb_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_plllc_regen_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_tdc_fine_res_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_tdccalexten_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_tdcdc_en_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_tdcroen_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_flavor_table_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_flavor_table_en_attr == SERDES_IP_RX_FLEX_L0_CFG_FLX_FLAVOR_TABLE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_force_frame_lock_attr == SERDES_IP_RX_FLEX_L0_CFG_FLX_FORCE_FRAME_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_freeze_in_state_attr == SERDES_IP_RX_FLEX_L0_CFG_FLX_FREEZE_IN_STATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_01_attr == 32'd65536
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_02_attr == 32'd2181070848
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_03_attr == 32'd2147491840
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_04_attr == 32'd2147483649
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_05_attr == 32'd2147483649
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_06_attr == 32'd2147483649
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_07_attr == 32'd2181038081
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_08_attr == 32'd16384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_09_attr == 32'd131072
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_10_attr == 32'd2147614720
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_11_attr == 32'd33554432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_12_attr == 32'd1075838976
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_13_attr == 32'd268435456
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_14_attr == 32'd2147491840
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_15_attr == 32'd2147614720
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_16_attr == 32'd268435457
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_17_attr == 32'd301989889
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_18_attr == 32'd33570816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_19_attr == 32'd33554432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_20_attr == 32'd33554432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_21_attr == 32'd2181054464
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_22_attr == 32'd2147484672
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_23_attr == 32'd33587200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_24_attr == 32'd2147614720
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_25_attr == 32'd33554432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_26_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_27_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_28_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_29_attr == 32'd33587200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_30_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_31_attr == 32'd1107296256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_02_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_03_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_04_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_05_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_06_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_07_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_10_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_12_attr == 5'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_13_attr == 5'd29
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_14_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_15_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_16_attr == 5'd29
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_17_attr == 5'd29
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_18_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_21_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_22_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_24_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_31_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_01_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_02_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_03_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_07_attr == 5'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_10_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_11_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_12_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_13_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_15_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_17_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_18_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_19_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_20_attr == 5'd21
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_21_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_23_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_25_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_29_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_31_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_one_state_inc_pulse_attr == SERDES_IP_RX_FLEX_L0_CFG_FLX_ONE_STATE_INC_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_00_attr == 32'd1187855
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_01_attr == 32'd9576479
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_02_attr == 32'd9437199
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_03_attr == 32'd9437199
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_04_attr == 32'd9554175
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_05_attr == 32'd9554943
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_06_attr == 32'd9554943
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_07_attr == 32'd9554943
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_08_attr == 32'd14680079
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_09_attr == 32'd25952527
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_10_attr == 32'd8651023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_11_attr == 32'd9437215
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_12_attr == 32'd8651023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_13_attr == 32'd8651023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_14_attr == 32'd8651023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_15_attr == 32'd25428239
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_16_attr == 32'd8735743
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_17_attr == 32'd8735487
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_18_attr == 32'd14942223
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_19_attr == 32'd12845071
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_20_attr == 32'd8392719
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_21_attr == 32'd14684175
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_22_attr == 32'd9519167
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_23_attr == 32'd9519119
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_24_attr == 32'd12582927
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_25_attr == 32'd12582927
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_26_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_27_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_28_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_29_attr == 32'd5505295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_30_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_31_attr == 32'd4456719
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_00_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_01_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_02_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_03_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_04_attr == 32'd4210819071
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_05_attr == 32'd4210771012
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_06_attr == 32'd2063305591
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_07_attr == 32'd2054911863
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_08_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_09_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_10_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_11_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_12_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_13_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_14_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_15_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_16_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_17_attr == 32'd1784366148
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_18_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_19_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_20_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_21_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_22_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_23_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_24_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_25_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_26_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_27_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_28_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_29_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_30_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_31_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_state_force_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_state_force_value_en_attr == SERDES_IP_RX_FLEX_L0_CFG_FLX_STATE_FORCE_VALUE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_flx_stop_tmr_in_handshake_attr == SERDES_IP_RX_FLEX_L0_CFG_FLX_STOP_TMR_IN_HANDSHAKE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_00_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_00_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_01_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_01_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_02_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_02_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_03_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_03_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_04_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_04_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_05_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_05_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_06_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_06_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_07_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_07_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_08_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_08_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_09_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_09_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_10_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_10_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_11_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_12_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_13_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_14_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_14_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_15_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_15_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_16_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_16_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_17_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_17_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_18_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_19_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_19_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_20_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_20_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_21_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_21_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_22_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_22_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_23_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_23_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_24_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_24_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_25_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_25_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_26_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_26_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_27_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_27_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_28_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_28_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_29_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_29_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_30_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_30_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_31_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_31_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_02_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_03_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_04_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_05_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_06_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_07_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_10_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_12_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_13_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_15_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_16_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_17_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_18_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_21_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_22_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_31_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_00_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_00_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_01_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_01_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_02_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_02_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_03_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_03_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_04_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_04_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_05_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_05_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_06_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_06_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_07_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_07_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_08_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_08_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_09_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_09_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_10_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_11_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_12_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_13_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_14_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_15_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_16_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_17_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_18_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_19_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_19_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_20_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_20_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_21_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_21_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_22_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_22_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_23_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_23_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_24_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_24_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_25_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_25_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_26_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_26_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_27_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_27_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_28_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_28_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_29_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_29_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_30_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_30_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_31_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_31_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_00_attr == 5'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_02_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_03_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_04_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_05_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_06_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_07_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_10_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_12_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_13_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_15_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_16_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_17_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_18_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_19_attr == 5'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_25_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_31_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_flavor_table_attr == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_flavor_table_en_attr == SERDES_IP_RX_FLEX_L1_CFG_FLX_FLAVOR_TABLE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_force_frame_lock_attr == SERDES_IP_RX_FLEX_L1_CFG_FLX_FORCE_FRAME_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_freeze_in_state_attr == SERDES_IP_RX_FLEX_L1_CFG_FLX_FREEZE_IN_STATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_01_attr == 32'd65537
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_02_attr == 32'd2147516416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_03_attr == 32'd2181169152
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_04_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_05_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_06_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_07_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_08_attr == 32'd16384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_09_attr == 32'd131072
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_10_attr == 32'd2416050176
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_11_attr == 32'd33554432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_12_attr == 32'd1075838976
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_13_attr == 32'd301989888
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_14_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_15_attr == 32'd2181169152
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_16_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_17_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_18_attr == 32'd302006272
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_19_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_20_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_21_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_22_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_23_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_24_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_25_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_26_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_27_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_28_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_29_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_30_attr == 32'd33587200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_31_attr == 32'd1107329024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_02_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_03_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_10_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_12_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_13_attr == 5'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_15_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_18_attr == 5'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_31_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_02_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_03_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_10_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_11_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_12_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_13_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_15_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_18_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_30_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_31_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_one_state_inc_pulse_attr == SERDES_IP_RX_FLEX_L1_CFG_FLX_ONE_STATE_INC_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_00_attr == 32'd1056783
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_01_attr == 32'd9510943
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_02_attr == 32'd9502735
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_03_attr == 32'd9437199
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_04_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_05_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_06_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_07_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_08_attr == 32'd14680079
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_09_attr == 32'd26017807
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_10_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_11_attr == 32'd9502735
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_12_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_13_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_14_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_15_attr == 32'd25493519
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_16_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_17_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_18_attr == 32'd14942223
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_19_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_20_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_21_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_22_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_23_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_24_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_25_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_26_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_27_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_28_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_29_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_30_attr == 32'd1376271
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_31_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_00_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_01_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_02_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_03_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_04_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_05_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_06_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_07_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_08_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_09_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_10_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_11_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_12_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_13_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_14_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_15_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_16_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_17_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_18_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_19_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_20_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_21_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_22_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_23_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_24_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_25_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_26_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_27_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_28_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_29_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_30_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_31_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_state_force_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_state_force_value_en_attr == SERDES_IP_RX_FLEX_L1_CFG_FLX_STATE_FORCE_VALUE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_flx_stop_tmr_in_handshake_attr == SERDES_IP_RX_FLEX_L1_CFG_FLX_STOP_TMR_IN_HANDSHAKE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_00_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_00_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_01_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_01_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_02_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_02_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_03_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_03_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_04_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_04_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_05_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_05_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_06_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_06_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_07_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_07_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_08_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_08_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_09_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_09_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_10_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_10_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_11_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_12_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_13_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_14_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_15_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_15_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_16_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_17_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_18_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_19_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_19_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_20_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_20_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_21_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_21_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_22_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_22_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_23_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_23_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_24_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_24_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_25_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_25_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_26_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_26_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_27_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_27_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_28_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_28_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_29_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_29_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_30_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_30_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_31_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_31_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_02_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_03_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_10_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_12_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_13_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_15_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_18_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_31_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_00_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_00_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_01_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_01_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_02_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_02_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_03_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_03_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_04_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_04_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_05_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_05_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_06_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_06_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_07_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_07_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_08_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_08_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_09_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_09_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_10_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_11_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_12_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_13_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_14_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_15_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_16_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_17_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_18_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_19_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_19_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_20_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_20_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_21_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_21_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_22_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_22_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_23_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_23_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_24_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_24_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_25_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_25_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_26_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_26_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_27_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_27_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_28_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_28_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_29_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_29_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_30_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_30_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_31_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_31_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_00_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_02_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_03_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_10_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_12_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_13_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_15_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_18_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_31_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_flavor_table_attr == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_flavor_table_en_attr == SERDES_IP_RX_FLEX_L2_CFG_FLX_FLAVOR_TABLE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_force_frame_lock_attr == SERDES_IP_RX_FLEX_L2_CFG_FLX_FORCE_FRAME_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_freeze_in_state_attr == SERDES_IP_RX_FLEX_L2_CFG_FLX_FREEZE_IN_STATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_01_attr == 32'd65537
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_02_attr == 32'd2147516416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_03_attr == 32'd2181169152
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_04_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_05_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_06_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_07_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_08_attr == 32'd16384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_09_attr == 32'd131072
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_10_attr == 32'd2416050176
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_11_attr == 32'd33554432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_12_attr == 32'd1075838976
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_13_attr == 32'd301989888
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_14_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_15_attr == 32'd2181169152
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_16_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_17_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_18_attr == 32'd302006272
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_19_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_20_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_21_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_22_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_23_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_24_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_25_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_26_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_27_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_28_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_29_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_30_attr == 32'd33587200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_31_attr == 32'd1107329024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_02_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_03_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_10_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_12_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_13_attr == 5'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_15_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_18_attr == 5'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_31_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_02_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_03_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_10_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_11_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_12_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_13_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_15_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_18_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_30_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_31_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_one_state_inc_pulse_attr == SERDES_IP_RX_FLEX_L2_CFG_FLX_ONE_STATE_INC_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_00_attr == 32'd1056783
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_01_attr == 32'd9510943
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_02_attr == 32'd9502735
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_03_attr == 32'd9437199
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_04_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_05_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_06_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_07_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_08_attr == 32'd14680079
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_09_attr == 32'd26017807
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_10_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_11_attr == 32'd9502735
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_12_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_13_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_14_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_15_attr == 32'd25493519
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_16_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_17_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_18_attr == 32'd14942223
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_19_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_20_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_21_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_22_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_23_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_24_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_25_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_26_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_27_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_28_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_29_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_30_attr == 32'd1376271
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_31_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_00_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_01_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_02_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_03_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_04_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_05_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_06_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_07_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_08_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_09_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_10_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_11_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_12_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_13_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_14_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_15_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_16_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_17_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_18_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_19_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_20_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_21_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_22_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_23_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_24_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_25_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_26_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_27_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_28_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_29_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_30_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_31_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_state_force_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_state_force_value_en_attr == SERDES_IP_RX_FLEX_L2_CFG_FLX_STATE_FORCE_VALUE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_flx_stop_tmr_in_handshake_attr == SERDES_IP_RX_FLEX_L2_CFG_FLX_STOP_TMR_IN_HANDSHAKE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_00_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_00_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_01_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_01_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_02_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_02_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_03_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_03_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_04_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_04_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_05_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_05_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_06_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_06_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_07_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_07_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_08_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_08_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_09_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_09_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_10_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_10_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_11_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_12_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_13_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_14_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_15_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_15_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_16_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_17_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_18_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_19_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_19_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_20_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_20_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_21_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_21_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_22_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_22_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_23_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_23_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_24_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_24_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_25_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_25_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_26_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_26_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_27_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_27_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_28_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_28_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_29_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_29_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_30_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_30_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_31_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_31_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_02_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_03_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_10_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_12_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_13_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_15_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_18_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_31_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_00_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_00_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_01_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_01_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_02_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_02_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_03_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_03_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_04_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_04_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_05_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_05_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_06_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_06_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_07_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_07_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_08_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_08_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_09_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_09_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_10_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_11_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_12_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_13_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_14_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_15_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_16_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_17_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_18_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_19_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_19_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_20_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_20_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_21_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_21_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_22_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_22_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_23_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_23_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_24_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_24_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_25_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_25_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_26_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_26_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_27_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_27_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_28_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_28_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_29_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_29_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_30_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_30_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_31_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_31_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_00_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_02_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_03_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_10_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_12_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_13_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_15_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_18_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_31_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_flavor_table_attr == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_flavor_table_en_attr == SERDES_IP_RX_FLEX_L3_CFG_FLX_FLAVOR_TABLE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_force_frame_lock_attr == SERDES_IP_RX_FLEX_L3_CFG_FLX_FORCE_FRAME_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_freeze_in_state_attr == SERDES_IP_RX_FLEX_L3_CFG_FLX_FREEZE_IN_STATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_01_attr == 32'd65537
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_02_attr == 32'd2147516416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_03_attr == 32'd2181169152
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_04_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_05_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_06_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_07_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_08_attr == 32'd16384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_09_attr == 32'd131072
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_10_attr == 32'd2416050176
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_11_attr == 32'd33554432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_12_attr == 32'd1075838976
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_13_attr == 32'd301989888
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_14_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_15_attr == 32'd2181169152
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_16_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_17_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_18_attr == 32'd302006272
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_19_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_20_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_21_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_22_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_23_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_24_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_25_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_26_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_27_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_28_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_29_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_30_attr == 32'd33587200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_31_attr == 32'd1107329024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_02_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_03_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_10_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_12_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_13_attr == 5'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_15_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_18_attr == 5'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_31_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_02_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_03_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_10_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_11_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_12_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_13_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_15_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_18_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_30_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_31_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_one_state_inc_pulse_attr == SERDES_IP_RX_FLEX_L3_CFG_FLX_ONE_STATE_INC_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_00_attr == 32'd1056783
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_01_attr == 32'd9510943
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_02_attr == 32'd9502735
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_03_attr == 32'd9437199
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_04_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_05_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_06_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_07_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_08_attr == 32'd14680079
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_09_attr == 32'd26017807
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_10_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_11_attr == 32'd9502735
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_12_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_13_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_14_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_15_attr == 32'd25493519
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_16_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_17_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_18_attr == 32'd14942223
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_19_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_20_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_21_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_22_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_23_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_24_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_25_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_26_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_27_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_28_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_29_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_30_attr == 32'd1376271
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_31_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_00_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_01_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_02_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_03_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_04_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_05_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_06_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_07_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_08_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_09_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_10_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_11_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_12_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_13_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_14_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_15_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_16_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_17_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_18_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_19_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_20_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_21_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_22_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_23_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_24_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_25_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_26_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_27_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_28_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_29_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_30_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_31_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_state_force_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_state_force_value_en_attr == SERDES_IP_RX_FLEX_L3_CFG_FLX_STATE_FORCE_VALUE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_flx_stop_tmr_in_handshake_attr == SERDES_IP_RX_FLEX_L3_CFG_FLX_STOP_TMR_IN_HANDSHAKE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_00_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_00_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_01_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_01_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_02_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_02_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_03_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_03_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_04_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_04_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_05_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_05_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_06_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_06_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_07_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_07_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_08_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_08_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_09_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_09_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_10_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_10_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_11_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_12_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_13_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_14_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_15_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_15_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_16_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_17_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_18_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_19_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_19_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_20_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_20_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_21_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_21_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_22_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_22_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_23_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_23_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_24_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_24_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_25_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_25_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_26_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_26_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_27_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_27_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_28_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_28_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_29_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_29_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_30_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_30_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_31_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_31_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_02_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_03_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_10_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_12_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_13_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_15_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_18_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_31_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_00_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_00_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_01_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_01_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_02_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_02_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_03_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_03_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_04_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_04_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_05_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_05_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_06_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_06_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_07_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_07_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_08_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_08_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_09_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_09_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_10_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_11_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_12_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_13_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_14_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_15_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_16_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_17_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_18_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_19_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_19_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_20_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_20_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_21_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_21_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_22_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_22_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_23_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_23_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_24_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_24_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_25_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_25_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_26_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_26_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_27_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_27_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_28_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_28_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_29_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_29_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_30_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_30_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_31_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_31_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_00_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_02_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_03_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_10_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_12_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_13_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_15_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_18_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_31_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_etrregsynthlcfastclk_ready2_attr == SERDES_IP_SYNTH_FAST_L0_CFG_ETRREGSYNTHLCFASTCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_etrregsynthlcfastclk_ready_attr == SERDES_IP_SYNTH_FAST_L0_CFG_ETRREGSYNTHLCFASTCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_FAST_L0_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_FAST_L0_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_FAST_L0_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_FAST_L0_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_FAST_L0_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_fastregpwrup_en_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFAST_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFAST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_pg_disable_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFAST_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_refdiv_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_refdiv_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_refdiv_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_refdiv_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_static_divrate_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFAST_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_used_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFAST_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastbias_icc400uadj_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldacbg_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldacfsm_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastclk_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastclkstat_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastclkstat_ready_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastdccrst_disable_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastearlylock_dig_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastearlylock_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastfsm_cken_ovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastfsm_cken_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_locovr_muxd0_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_locovr_muxd1_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_locovr_muxd2_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_locovr_muxd3_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_locovr_muxd4_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpllstatus_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastppm_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrecal_on_pd_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_en_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastspare1_attr == 32'd45078
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfaststartup_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfaststartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfasttimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfasttimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_etrregsynthlcfastclk_ready2_attr == SERDES_IP_SYNTH_FAST_L1_CFG_ETRREGSYNTHLCFASTCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_etrregsynthlcfastclk_ready_attr == SERDES_IP_SYNTH_FAST_L1_CFG_ETRREGSYNTHLCFASTCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_FAST_L1_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_FAST_L1_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_FAST_L1_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_FAST_L1_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_FAST_L1_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_fastregpwrup_en_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFAST_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFAST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_pg_disable_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFAST_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_refdiv_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_refdiv_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_refdiv_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_refdiv_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_static_divrate_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFAST_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_used_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFAST_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastbias_icc400uadj_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldacbg_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldacfsm_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastclk_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastclkstat_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastclkstat_ready_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastdccrst_disable_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastearlylock_dig_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastearlylock_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastfsm_cken_ovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastfsm_cken_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_locovr_muxd0_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_locovr_muxd1_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_locovr_muxd2_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_locovr_muxd3_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_locovr_muxd4_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpllstatus_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastppm_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrecal_on_pd_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_en_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastspare1_attr == 32'd45078
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfaststartup_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfaststartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfasttimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfasttimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_etrregsynthlcfastclk_ready2_attr == SERDES_IP_SYNTH_FAST_L2_CFG_ETRREGSYNTHLCFASTCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_etrregsynthlcfastclk_ready_attr == SERDES_IP_SYNTH_FAST_L2_CFG_ETRREGSYNTHLCFASTCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_FAST_L2_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_FAST_L2_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_FAST_L2_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_FAST_L2_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_FAST_L2_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_fastregpwrup_en_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFAST_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFAST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_pg_disable_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFAST_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_refdiv_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_refdiv_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_refdiv_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_refdiv_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_static_divrate_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFAST_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_used_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFAST_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastbias_icc400uadj_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldacbg_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldacfsm_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastclk_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastclkstat_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastclkstat_ready_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastdccrst_disable_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastearlylock_dig_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastearlylock_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastfsm_cken_ovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastfsm_cken_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_locovr_muxd0_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_locovr_muxd1_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_locovr_muxd2_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_locovr_muxd3_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_locovr_muxd4_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpllstatus_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastppm_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrecal_on_pd_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_en_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastspare1_attr == 32'd45078
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfaststartup_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfaststartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfasttimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfasttimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_etrregsynthlcfastclk_ready2_attr == SERDES_IP_SYNTH_FAST_L3_CFG_ETRREGSYNTHLCFASTCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_etrregsynthlcfastclk_ready_attr == SERDES_IP_SYNTH_FAST_L3_CFG_ETRREGSYNTHLCFASTCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_FAST_L3_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_FAST_L3_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_FAST_L3_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_FAST_L3_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_FAST_L3_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_fastregpwrup_en_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFAST_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFAST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_pg_disable_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFAST_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_refdiv_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_refdiv_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_refdiv_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_refdiv_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_static_divrate_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFAST_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_used_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFAST_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastbias_icc400uadj_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldacbg_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldacfsm_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastclk_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastclkstat_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastclkstat_ready_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastdccrst_disable_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastearlylock_dig_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastearlylock_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastfsm_cken_ovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastfsm_cken_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_locovr_muxd0_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_locovr_muxd1_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_locovr_muxd2_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_locovr_muxd3_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_locovr_muxd4_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpllstatus_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastppm_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrecal_on_pd_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_en_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastspare1_attr == 32'd45078
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfaststartup_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfaststartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfasttimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfasttimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_etrregsynthlcmedclk_ready2_attr == SERDES_IP_SYNTH_MED_L0_CFG_ETRREGSYNTHLCMEDCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_etrregsynthlcmedclk_ready_attr == SERDES_IP_SYNTH_MED_L0_CFG_ETRREGSYNTHLCMEDCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_MED_L0_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_MED_L0_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_MED_L0_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_MED_L0_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_MED_L0_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_fastregpwrup_en_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_pg_disable_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_refdiv_muxd1_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_refdiv_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_refdiv_muxd3_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_refdiv_muxd4_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_static_divrate_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_txbitclkselect_muxd0_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_txbitclkselect_muxd1_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_txbitclkselect_muxd2_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_txbitclkselect_muxd3_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_txbitclkselect_muxd4_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_used_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedbias_icc400uadj_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldacbg_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldacfsm_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedclk_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedclkstat_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedclkstat_ready_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmeddccrst_disable_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedearlylock_dig_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedearlylock_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedfsm_cken_ovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedfsm_cken_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_locovr_muxd0_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_locovr_muxd1_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_locovr_muxd2_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_locovr_muxd3_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_locovr_muxd4_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpllstatus_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedppm_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrecal_on_pd_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_en_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_entry7_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedstartup_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedstartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedtimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedtimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_etrregsynthlcmedclk_ready2_attr == SERDES_IP_SYNTH_MED_L1_CFG_ETRREGSYNTHLCMEDCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_etrregsynthlcmedclk_ready_attr == SERDES_IP_SYNTH_MED_L1_CFG_ETRREGSYNTHLCMEDCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_MED_L1_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_MED_L1_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_MED_L1_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_MED_L1_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_MED_L1_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_fastregpwrup_en_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_pg_disable_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_refdiv_muxd1_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_refdiv_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_refdiv_muxd3_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_refdiv_muxd4_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_static_divrate_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_txbitclkselect_muxd0_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_txbitclkselect_muxd1_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_txbitclkselect_muxd2_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_txbitclkselect_muxd3_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_txbitclkselect_muxd4_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_used_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedbias_icc400uadj_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldacbg_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldacfsm_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedclk_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedclkstat_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedclkstat_ready_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmeddccrst_disable_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedearlylock_dig_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedearlylock_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedfsm_cken_ovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedfsm_cken_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_locovr_muxd0_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_locovr_muxd1_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_locovr_muxd2_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_locovr_muxd3_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_locovr_muxd4_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpllstatus_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedppm_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrecal_on_pd_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_en_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_entry7_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedstartup_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedstartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedtimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedtimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_etrregsynthlcmedclk_ready2_attr == SERDES_IP_SYNTH_MED_L2_CFG_ETRREGSYNTHLCMEDCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_etrregsynthlcmedclk_ready_attr == SERDES_IP_SYNTH_MED_L2_CFG_ETRREGSYNTHLCMEDCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_MED_L2_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_MED_L2_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_MED_L2_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_MED_L2_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_MED_L2_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_fastregpwrup_en_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_pg_disable_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_refdiv_muxd1_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_refdiv_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_refdiv_muxd3_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_refdiv_muxd4_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_static_divrate_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_txbitclkselect_muxd0_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_txbitclkselect_muxd1_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_txbitclkselect_muxd2_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_txbitclkselect_muxd3_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_txbitclkselect_muxd4_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_used_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedbias_icc400uadj_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldacbg_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldacfsm_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedclk_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedclkstat_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedclkstat_ready_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmeddccrst_disable_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedearlylock_dig_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedearlylock_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedfsm_cken_ovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedfsm_cken_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_locovr_muxd0_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_locovr_muxd1_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_locovr_muxd2_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_locovr_muxd3_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_locovr_muxd4_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpllstatus_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedppm_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrecal_on_pd_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_en_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_entry7_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedstartup_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedstartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedtimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedtimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_etrregsynthlcmedclk_ready2_attr == SERDES_IP_SYNTH_MED_L3_CFG_ETRREGSYNTHLCMEDCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_etrregsynthlcmedclk_ready_attr == SERDES_IP_SYNTH_MED_L3_CFG_ETRREGSYNTHLCMEDCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_MED_L3_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_MED_L3_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_MED_L3_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_MED_L3_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_MED_L3_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_fastregpwrup_en_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_pg_disable_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_refdiv_muxd1_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_refdiv_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_refdiv_muxd3_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_refdiv_muxd4_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_static_divrate_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_txbitclkselect_muxd0_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_txbitclkselect_muxd1_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_txbitclkselect_muxd2_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_txbitclkselect_muxd3_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_txbitclkselect_muxd4_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_used_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedbias_icc400uadj_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldacbg_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldacfsm_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedclk_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedclkstat_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedclkstat_ready_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmeddccrst_disable_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedearlylock_dig_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedearlylock_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedfsm_cken_ovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedfsm_cken_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_locovr_muxd0_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_locovr_muxd1_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_locovr_muxd2_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_locovr_muxd3_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_locovr_muxd4_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpllstatus_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedppm_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrecal_on_pd_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_en_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_entry7_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedstartup_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedstartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedtimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedtimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_etrregsynthlcslowclk_ready2_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_ETRREGSYNTHLCSLOWCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_etrregsynthlcslowclk_ready_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_ETRREGSYNTHLCSLOWCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_fastregpwrup_en_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_pg_disable_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_refdiv_muxd0_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_refdiv_muxd1_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_refdiv_muxd2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_refdiv_muxd3_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_refdiv_muxd4_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_static_divrate_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_txbitclkselect_muxd0_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_txbitclkselect_muxd1_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_txbitclkselect_muxd2_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_txbitclkselect_muxd3_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_txbitclkselect_muxd4_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_used_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowbias_icc400uadj_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldacbg_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldacfsm_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowclk_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowclkstat_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowclkstat_ready_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowdccrst_disable_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowearlylock_dig_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowearlylock_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowfsm_cken_ovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowfsm_cken_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_locovr_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_locovr_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_locovr_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_locovr_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_locovr_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpllstatus_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowppm_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_clk_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrecal_on_pd_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_en_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_entry7_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowstartup_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowstartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowtimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowtimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_etrregsynthlcslowclk_ready2_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_ETRREGSYNTHLCSLOWCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_etrregsynthlcslowclk_ready_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_ETRREGSYNTHLCSLOWCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_fastregpwrup_en_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_pg_disable_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_refdiv_muxd0_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_refdiv_muxd1_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_refdiv_muxd2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_refdiv_muxd3_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_refdiv_muxd4_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_static_divrate_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_txbitclkselect_muxd0_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_txbitclkselect_muxd1_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_txbitclkselect_muxd2_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_txbitclkselect_muxd3_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_txbitclkselect_muxd4_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_used_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowbias_icc400uadj_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldacbg_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldacfsm_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowclk_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowclkstat_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowclkstat_ready_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowdccrst_disable_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowearlylock_dig_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowearlylock_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowfsm_cken_ovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowfsm_cken_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_locovr_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_locovr_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_locovr_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_locovr_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_locovr_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpllstatus_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowppm_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_clk_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrecal_on_pd_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_en_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_entry7_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowstartup_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowstartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowtimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowtimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_etrregsynthlcslowclk_ready2_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_ETRREGSYNTHLCSLOWCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_etrregsynthlcslowclk_ready_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_ETRREGSYNTHLCSLOWCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_fastregpwrup_en_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_pg_disable_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_refdiv_muxd0_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_refdiv_muxd1_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_refdiv_muxd2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_refdiv_muxd3_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_refdiv_muxd4_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_static_divrate_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_txbitclkselect_muxd0_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_txbitclkselect_muxd1_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_txbitclkselect_muxd2_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_txbitclkselect_muxd3_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_txbitclkselect_muxd4_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_used_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowbias_icc400uadj_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldacbg_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldacfsm_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowclk_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowclkstat_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowclkstat_ready_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowdccrst_disable_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowearlylock_dig_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowearlylock_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowfsm_cken_ovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowfsm_cken_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_locovr_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_locovr_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_locovr_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_locovr_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_locovr_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpllstatus_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowppm_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_clk_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrecal_on_pd_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_en_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_entry7_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowstartup_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowstartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowtimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowtimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_etrregsynthlcslowclk_ready2_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_ETRREGSYNTHLCSLOWCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_etrregsynthlcslowclk_ready_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_ETRREGSYNTHLCSLOWCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_fastregpwrup_en_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_pg_disable_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_refdiv_muxd0_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_refdiv_muxd1_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_refdiv_muxd2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_refdiv_muxd3_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_refdiv_muxd4_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_static_divrate_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_txbitclkselect_muxd0_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_txbitclkselect_muxd1_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_txbitclkselect_muxd2_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_txbitclkselect_muxd3_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_txbitclkselect_muxd4_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_used_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowbias_icc400uadj_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldacbg_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldacfsm_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowclk_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowclkstat_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowclkstat_ready_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowdccrst_disable_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowearlylock_dig_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowearlylock_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowfsm_cken_ovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowfsm_cken_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_locovr_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_locovr_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_locovr_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_locovr_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_locovr_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpllstatus_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowppm_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_clk_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrecal_on_pd_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_en_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_entry7_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowstartup_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowstartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowtimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowtimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_an_idle_stiky_clear_attr == SERDES_SHIM_AN_L0_CFG_AN_IDLE_STIKY_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_an_reserv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_debug_fw_reg1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_debug_fw_reg2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_debug_fw_reg3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_debug_fw_reg4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_dig_cdr_disable_attr == SERDES_SHIM_AN_L0_CFG_DIG_CDR_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_direct_control_bus0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_direct_control_bus1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_direct_control_bus2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_direct_control_bus3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_direct_control_bus4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_direct_control_bus5_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_direct_control_bus6_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_direct_control_bus_en_attr == SERDES_SHIM_AN_L0_CFG_DIRECT_CONTROL_BUS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_edge_too_long_disable_attr == SERDES_SHIM_AN_L0_CFG_EDGE_TOO_LONG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_edge_too_short_disable_attr == SERDES_SHIM_AN_L0_CFG_EDGE_TOO_SHORT_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_page_max_timer_disable_attr == SERDES_SHIM_AN_L0_CFG_PAGE_MAX_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_page_min_timer_disable_attr == SERDES_SHIM_AN_L0_CFG_PAGE_MIN_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_pcs_lock_attr == SERDES_SHIM_AN_L0_CFG_PCS_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_pcs_tx_bypass_sample_attr == SERDES_SHIM_AN_L0_CFG_PCS_TX_BYPASS_SAMPLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_rx_enable_m_attr == SERDES_SHIM_AN_L0_CFG_RX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_rx_lcw_re_attr == SERDES_SHIM_AN_L0_CFG_RX_LCW_RE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_rx_pma_en_attr == SERDES_SHIM_AN_L0_CFG_RX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_rx_unencoder_ctrl_en_attr == SERDES_SHIM_AN_L0_CFG_RX_UNENCODER_CTRL_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_rx_unencoder_gray_en_attr == SERDES_SHIM_AN_L0_CFG_RX_UNENCODER_GRAY_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_rx_unencoder_pam_bitorder_swz_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_rx_unencoder_pam_en_attr == SERDES_SHIM_AN_L0_CFG_RX_UNENCODER_PAM_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_rx_unencoder_polarity_swz_attr == SERDES_SHIM_AN_L0_CFG_RX_UNENCODER_POLARITY_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_rx_unencoder_precode_en_attr == SERDES_SHIM_AN_L0_CFG_RX_UNENCODER_PRECODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_rx_unencoder_width_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_serdes_irq_bus_sel_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_serdes_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_serdes_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_serdes_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_transmit_mode_scan_mode_dbg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_tx_complete_ack_attr == SERDES_SHIM_AN_L0_CFG_TX_COMPLETE_ACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_tx_enable_m_attr == SERDES_SHIM_AN_L0_CFG_TX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_tx_lcw_high_attr == 27'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_tx_lcw_low_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_tx_lcw_reserv_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_tx_lcw_we_attr == SERDES_SHIM_AN_L0_CFG_TX_LCW_WE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l0_cfg_tx_pma_en_attr == SERDES_SHIM_AN_L0_CFG_TX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_an_idle_stiky_clear_attr == SERDES_SHIM_AN_L1_CFG_AN_IDLE_STIKY_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_an_reserv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_debug_fw_reg1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_debug_fw_reg2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_debug_fw_reg3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_debug_fw_reg4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_dig_cdr_disable_attr == SERDES_SHIM_AN_L1_CFG_DIG_CDR_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_direct_control_bus0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_direct_control_bus1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_direct_control_bus2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_direct_control_bus3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_direct_control_bus4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_direct_control_bus5_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_direct_control_bus6_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_direct_control_bus_en_attr == SERDES_SHIM_AN_L1_CFG_DIRECT_CONTROL_BUS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_edge_too_long_disable_attr == SERDES_SHIM_AN_L1_CFG_EDGE_TOO_LONG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_edge_too_short_disable_attr == SERDES_SHIM_AN_L1_CFG_EDGE_TOO_SHORT_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_page_max_timer_disable_attr == SERDES_SHIM_AN_L1_CFG_PAGE_MAX_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_page_min_timer_disable_attr == SERDES_SHIM_AN_L1_CFG_PAGE_MIN_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_pcs_lock_attr == SERDES_SHIM_AN_L1_CFG_PCS_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_pcs_tx_bypass_sample_attr == SERDES_SHIM_AN_L1_CFG_PCS_TX_BYPASS_SAMPLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_rx_enable_m_attr == SERDES_SHIM_AN_L1_CFG_RX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_rx_lcw_re_attr == SERDES_SHIM_AN_L1_CFG_RX_LCW_RE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_rx_pma_en_attr == SERDES_SHIM_AN_L1_CFG_RX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_rx_unencoder_ctrl_en_attr == SERDES_SHIM_AN_L1_CFG_RX_UNENCODER_CTRL_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_rx_unencoder_gray_en_attr == SERDES_SHIM_AN_L1_CFG_RX_UNENCODER_GRAY_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_rx_unencoder_pam_bitorder_swz_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_rx_unencoder_pam_en_attr == SERDES_SHIM_AN_L1_CFG_RX_UNENCODER_PAM_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_rx_unencoder_polarity_swz_attr == SERDES_SHIM_AN_L1_CFG_RX_UNENCODER_POLARITY_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_rx_unencoder_precode_en_attr == SERDES_SHIM_AN_L1_CFG_RX_UNENCODER_PRECODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_rx_unencoder_width_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_serdes_irq_bus_sel_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_serdes_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_serdes_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_serdes_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_transmit_mode_scan_mode_dbg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_tx_complete_ack_attr == SERDES_SHIM_AN_L1_CFG_TX_COMPLETE_ACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_tx_enable_m_attr == SERDES_SHIM_AN_L1_CFG_TX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_tx_lcw_high_attr == 27'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_tx_lcw_low_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_tx_lcw_reserv_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_tx_lcw_we_attr == SERDES_SHIM_AN_L1_CFG_TX_LCW_WE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l1_cfg_tx_pma_en_attr == SERDES_SHIM_AN_L1_CFG_TX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_an_idle_stiky_clear_attr == SERDES_SHIM_AN_L2_CFG_AN_IDLE_STIKY_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_an_reserv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_debug_fw_reg1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_debug_fw_reg2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_debug_fw_reg3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_debug_fw_reg4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_dig_cdr_disable_attr == SERDES_SHIM_AN_L2_CFG_DIG_CDR_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_direct_control_bus0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_direct_control_bus1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_direct_control_bus2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_direct_control_bus3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_direct_control_bus4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_direct_control_bus5_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_direct_control_bus6_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_direct_control_bus_en_attr == SERDES_SHIM_AN_L2_CFG_DIRECT_CONTROL_BUS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_edge_too_long_disable_attr == SERDES_SHIM_AN_L2_CFG_EDGE_TOO_LONG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_edge_too_short_disable_attr == SERDES_SHIM_AN_L2_CFG_EDGE_TOO_SHORT_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_page_max_timer_disable_attr == SERDES_SHIM_AN_L2_CFG_PAGE_MAX_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_page_min_timer_disable_attr == SERDES_SHIM_AN_L2_CFG_PAGE_MIN_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_pcs_lock_attr == SERDES_SHIM_AN_L2_CFG_PCS_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_pcs_tx_bypass_sample_attr == SERDES_SHIM_AN_L2_CFG_PCS_TX_BYPASS_SAMPLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_rx_enable_m_attr == SERDES_SHIM_AN_L2_CFG_RX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_rx_lcw_re_attr == SERDES_SHIM_AN_L2_CFG_RX_LCW_RE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_rx_pma_en_attr == SERDES_SHIM_AN_L2_CFG_RX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_rx_unencoder_ctrl_en_attr == SERDES_SHIM_AN_L2_CFG_RX_UNENCODER_CTRL_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_rx_unencoder_gray_en_attr == SERDES_SHIM_AN_L2_CFG_RX_UNENCODER_GRAY_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_rx_unencoder_pam_bitorder_swz_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_rx_unencoder_pam_en_attr == SERDES_SHIM_AN_L2_CFG_RX_UNENCODER_PAM_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_rx_unencoder_polarity_swz_attr == SERDES_SHIM_AN_L2_CFG_RX_UNENCODER_POLARITY_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_rx_unencoder_precode_en_attr == SERDES_SHIM_AN_L2_CFG_RX_UNENCODER_PRECODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_rx_unencoder_width_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_serdes_irq_bus_sel_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_serdes_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_serdes_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_serdes_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_transmit_mode_scan_mode_dbg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_tx_complete_ack_attr == SERDES_SHIM_AN_L2_CFG_TX_COMPLETE_ACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_tx_enable_m_attr == SERDES_SHIM_AN_L2_CFG_TX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_tx_lcw_high_attr == 27'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_tx_lcw_low_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_tx_lcw_reserv_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_tx_lcw_we_attr == SERDES_SHIM_AN_L2_CFG_TX_LCW_WE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l2_cfg_tx_pma_en_attr == SERDES_SHIM_AN_L2_CFG_TX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_an_idle_stiky_clear_attr == SERDES_SHIM_AN_L3_CFG_AN_IDLE_STIKY_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_an_reserv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_debug_fw_reg1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_debug_fw_reg2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_debug_fw_reg3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_debug_fw_reg4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_dig_cdr_disable_attr == SERDES_SHIM_AN_L3_CFG_DIG_CDR_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_direct_control_bus0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_direct_control_bus1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_direct_control_bus2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_direct_control_bus3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_direct_control_bus4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_direct_control_bus5_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_direct_control_bus6_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_direct_control_bus_en_attr == SERDES_SHIM_AN_L3_CFG_DIRECT_CONTROL_BUS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_edge_too_long_disable_attr == SERDES_SHIM_AN_L3_CFG_EDGE_TOO_LONG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_edge_too_short_disable_attr == SERDES_SHIM_AN_L3_CFG_EDGE_TOO_SHORT_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_page_max_timer_disable_attr == SERDES_SHIM_AN_L3_CFG_PAGE_MAX_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_page_min_timer_disable_attr == SERDES_SHIM_AN_L3_CFG_PAGE_MIN_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_pcs_lock_attr == SERDES_SHIM_AN_L3_CFG_PCS_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_pcs_tx_bypass_sample_attr == SERDES_SHIM_AN_L3_CFG_PCS_TX_BYPASS_SAMPLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_rx_enable_m_attr == SERDES_SHIM_AN_L3_CFG_RX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_rx_lcw_re_attr == SERDES_SHIM_AN_L3_CFG_RX_LCW_RE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_rx_pma_en_attr == SERDES_SHIM_AN_L3_CFG_RX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_rx_unencoder_ctrl_en_attr == SERDES_SHIM_AN_L3_CFG_RX_UNENCODER_CTRL_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_rx_unencoder_gray_en_attr == SERDES_SHIM_AN_L3_CFG_RX_UNENCODER_GRAY_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_rx_unencoder_pam_bitorder_swz_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_rx_unencoder_pam_en_attr == SERDES_SHIM_AN_L3_CFG_RX_UNENCODER_PAM_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_rx_unencoder_polarity_swz_attr == SERDES_SHIM_AN_L3_CFG_RX_UNENCODER_POLARITY_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_rx_unencoder_precode_en_attr == SERDES_SHIM_AN_L3_CFG_RX_UNENCODER_PRECODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_rx_unencoder_width_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_serdes_irq_bus_sel_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_serdes_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_serdes_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_serdes_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_transmit_mode_scan_mode_dbg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_tx_complete_ack_attr == SERDES_SHIM_AN_L3_CFG_TX_COMPLETE_ACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_tx_enable_m_attr == SERDES_SHIM_AN_L3_CFG_TX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_tx_lcw_high_attr == 27'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_tx_lcw_low_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_tx_lcw_reserv_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_tx_lcw_we_attr == SERDES_SHIM_AN_L3_CFG_TX_LCW_WE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_an_l3_cfg_tx_pma_en_attr == SERDES_SHIM_AN_L3_CFG_TX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_apb_dsp_clk_sel_attr == SERDES_SHIM_CAR_L0_CFG_APB_DSP_CLK_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_apb_dsp_divn_en_attr == SERDES_SHIM_CAR_L0_CFG_APB_DSP_DIVN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_apb_dsp_divn_value_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_apb_dsp_pclken_attr == SERDES_SHIM_CAR_L0_CFG_APB_DSP_PCLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_apb_dsp_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_APB_DSP_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_dp_rx_80b_swz_attr == SERDES_SHIM_CAR_L0_CFG_DP_RX_80B_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_dp_tx_80b_swz_attr == SERDES_SHIM_CAR_L0_CFG_DP_TX_80B_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_eee_alert_force_en_attr == SERDES_SHIM_CAR_L0_CFG_EEE_ALERT_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_eee_alert_force_val_attr == SERDES_SHIM_CAR_L0_CFG_EEE_ALERT_FORCE_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_flux_srds_tx_divn_clken_attr == SERDES_SHIM_CAR_L0_CFG_FLUX_SRDS_TX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_iflux_tx_or_apb_clk_for_ux_ctrl_clk_sel_attr == SERDES_SHIM_CAR_L0_CFG_IFLUX_TX_OR_APB_CLK_FOR_UX_CTRL_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_oflux_srds_rx_clken_attr == SERDES_SHIM_CAR_L0_CFG_OFLUX_SRDS_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_oflux_srds_rx_divn_clken_attr == SERDES_SHIM_CAR_L0_CFG_OFLUX_SRDS_RX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_oflux_srds_tx_clken_attr == SERDES_SHIM_CAR_L0_CFG_OFLUX_SRDS_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_pcs_ick_ctrl_cmn_clk_sel_attr == SERDES_SHIM_CAR_L0_CFG_PCS_ICK_CTRL_CMN_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_pcs_ick_ctrl_l0_clk_sel_attr == SERDES_SHIM_CAR_L0_CFG_PCS_ICK_CTRL_L0_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_rxovrcdrlock2data_attr == SERDES_SHIM_CAR_L0_CFG_RXOVRCDRLOCK2DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_rxovrcdrlock2data_src_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_rxovrcdrlock2dataen_attr == SERDES_SHIM_CAR_L0_CFG_RXOVRCDRLOCK2DATAEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_rxovrcdrlock2dataen_src_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_rxpstate_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_rxpstate_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_srds_an_rx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_AN_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_srds_an_rx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_AN_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_srds_an_tx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_AN_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_srds_an_tx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_AN_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_srds_ctrl_rx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_CTRL_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_srds_ctrl_rx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_CTRL_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_srds_ctrl_tx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_CTRL_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_srds_ctrl_tx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_CTRL_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_srds_dfx_rx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_DFX_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_srds_dfx_rx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_DFX_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_srds_dfx_tx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_DFX_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_srds_dfx_tx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_DFX_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_srds_dsp_rx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_DSP_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_srds_dsp_rx_isi_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_DSP_RX_ISI_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_srds_dsp_rx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_DSP_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_srds_eee_rx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_EEE_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_srds_eee_rx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_EEE_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_srds_eee_tx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_EEE_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_srds_eee_tx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_EEE_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_srds_pcs_tx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_PCS_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_srds_pcs_tx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_PCS_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_srds_trn_rx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_TRN_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_srds_trn_rx_divn_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_TRN_RX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_srds_trn_rx_divn_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_TRN_RX_DIVN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_srds_trn_rx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_TRN_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_srds_trn_tx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_TRN_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_srds_trn_tx_divn_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_TRN_TX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_srds_trn_tx_divn_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_TRN_TX_DIVN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_srds_trn_tx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_TRN_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_srds_ux_ctrl_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_UX_CTRL_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_srds_ux_ctrl_cmn_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_UX_CTRL_CMN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_srds_ux_ctrl_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_UX_CTRL_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_srds_ux_tx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_UX_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_srds_ux_tx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_UX_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_timer_en_attr == SERDES_SHIM_CAR_L0_CFG_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_timer_value_attr == 8'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_transmit_mode_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_tx_postdiv_clk_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_txelecidle_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_txelecidle_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_txpstate_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l0_cfg_txpstate_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_apb_dsp_clk_sel_attr == SERDES_SHIM_CAR_L1_CFG_APB_DSP_CLK_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_apb_dsp_divn_en_attr == SERDES_SHIM_CAR_L1_CFG_APB_DSP_DIVN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_apb_dsp_divn_value_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_apb_dsp_pclken_attr == SERDES_SHIM_CAR_L1_CFG_APB_DSP_PCLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_apb_dsp_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_APB_DSP_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_dp_rx_80b_swz_attr == SERDES_SHIM_CAR_L1_CFG_DP_RX_80B_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_dp_tx_80b_swz_attr == SERDES_SHIM_CAR_L1_CFG_DP_TX_80B_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_eee_alert_force_en_attr == SERDES_SHIM_CAR_L1_CFG_EEE_ALERT_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_eee_alert_force_val_attr == SERDES_SHIM_CAR_L1_CFG_EEE_ALERT_FORCE_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_flux_srds_tx_divn_clken_attr == SERDES_SHIM_CAR_L1_CFG_FLUX_SRDS_TX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_iflux_tx_or_apb_clk_for_ux_ctrl_clk_sel_attr == SERDES_SHIM_CAR_L1_CFG_IFLUX_TX_OR_APB_CLK_FOR_UX_CTRL_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_oflux_srds_rx_clken_attr == SERDES_SHIM_CAR_L1_CFG_OFLUX_SRDS_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_oflux_srds_rx_divn_clken_attr == SERDES_SHIM_CAR_L1_CFG_OFLUX_SRDS_RX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_oflux_srds_tx_clken_attr == SERDES_SHIM_CAR_L1_CFG_OFLUX_SRDS_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_pcs_ick_ctrl_cmn_clk_sel_attr == SERDES_SHIM_CAR_L1_CFG_PCS_ICK_CTRL_CMN_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_pcs_ick_ctrl_l0_clk_sel_attr == SERDES_SHIM_CAR_L1_CFG_PCS_ICK_CTRL_L0_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_rxovrcdrlock2data_attr == SERDES_SHIM_CAR_L1_CFG_RXOVRCDRLOCK2DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_rxovrcdrlock2data_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_rxovrcdrlock2dataen_attr == SERDES_SHIM_CAR_L1_CFG_RXOVRCDRLOCK2DATAEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_rxovrcdrlock2dataen_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_rxpstate_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_rxpstate_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_srds_an_rx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_AN_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_srds_an_rx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_AN_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_srds_an_tx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_AN_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_srds_an_tx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_AN_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_srds_ctrl_rx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_CTRL_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_srds_ctrl_rx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_CTRL_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_srds_ctrl_tx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_CTRL_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_srds_ctrl_tx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_CTRL_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_srds_dfx_rx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_DFX_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_srds_dfx_rx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_DFX_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_srds_dfx_tx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_DFX_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_srds_dfx_tx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_DFX_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_srds_dsp_rx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_DSP_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_srds_dsp_rx_isi_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_DSP_RX_ISI_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_srds_dsp_rx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_DSP_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_srds_eee_rx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_EEE_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_srds_eee_rx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_EEE_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_srds_eee_tx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_EEE_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_srds_eee_tx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_EEE_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_srds_pcs_tx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_PCS_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_srds_pcs_tx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_PCS_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_srds_trn_rx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_TRN_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_srds_trn_rx_divn_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_TRN_RX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_srds_trn_rx_divn_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_TRN_RX_DIVN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_srds_trn_rx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_TRN_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_srds_trn_tx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_TRN_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_srds_trn_tx_divn_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_TRN_TX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_srds_trn_tx_divn_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_TRN_TX_DIVN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_srds_trn_tx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_TRN_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_srds_ux_ctrl_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_UX_CTRL_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_srds_ux_ctrl_cmn_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_UX_CTRL_CMN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_srds_ux_ctrl_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_UX_CTRL_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_srds_ux_tx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_UX_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_srds_ux_tx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_UX_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_timer_en_attr == SERDES_SHIM_CAR_L1_CFG_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_timer_value_attr == 8'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_transmit_mode_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_tx_postdiv_clk_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_txelecidle_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_txelecidle_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_txpstate_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l1_cfg_txpstate_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_apb_dsp_clk_sel_attr == SERDES_SHIM_CAR_L2_CFG_APB_DSP_CLK_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_apb_dsp_divn_en_attr == SERDES_SHIM_CAR_L2_CFG_APB_DSP_DIVN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_apb_dsp_divn_value_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_apb_dsp_pclken_attr == SERDES_SHIM_CAR_L2_CFG_APB_DSP_PCLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_apb_dsp_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_APB_DSP_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_dp_rx_80b_swz_attr == SERDES_SHIM_CAR_L2_CFG_DP_RX_80B_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_dp_tx_80b_swz_attr == SERDES_SHIM_CAR_L2_CFG_DP_TX_80B_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_eee_alert_force_en_attr == SERDES_SHIM_CAR_L2_CFG_EEE_ALERT_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_eee_alert_force_val_attr == SERDES_SHIM_CAR_L2_CFG_EEE_ALERT_FORCE_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_flux_srds_tx_divn_clken_attr == SERDES_SHIM_CAR_L2_CFG_FLUX_SRDS_TX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_iflux_tx_or_apb_clk_for_ux_ctrl_clk_sel_attr == SERDES_SHIM_CAR_L2_CFG_IFLUX_TX_OR_APB_CLK_FOR_UX_CTRL_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_oflux_srds_rx_clken_attr == SERDES_SHIM_CAR_L2_CFG_OFLUX_SRDS_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_oflux_srds_rx_divn_clken_attr == SERDES_SHIM_CAR_L2_CFG_OFLUX_SRDS_RX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_oflux_srds_tx_clken_attr == SERDES_SHIM_CAR_L2_CFG_OFLUX_SRDS_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_pcs_ick_ctrl_cmn_clk_sel_attr == SERDES_SHIM_CAR_L2_CFG_PCS_ICK_CTRL_CMN_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_pcs_ick_ctrl_l0_clk_sel_attr == SERDES_SHIM_CAR_L2_CFG_PCS_ICK_CTRL_L0_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_rxovrcdrlock2data_attr == SERDES_SHIM_CAR_L2_CFG_RXOVRCDRLOCK2DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_rxovrcdrlock2data_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_rxovrcdrlock2dataen_attr == SERDES_SHIM_CAR_L2_CFG_RXOVRCDRLOCK2DATAEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_rxovrcdrlock2dataen_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_rxpstate_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_rxpstate_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_srds_an_rx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_AN_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_srds_an_rx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_AN_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_srds_an_tx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_AN_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_srds_an_tx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_AN_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_srds_ctrl_rx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_CTRL_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_srds_ctrl_rx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_CTRL_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_srds_ctrl_tx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_CTRL_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_srds_ctrl_tx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_CTRL_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_srds_dfx_rx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_DFX_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_srds_dfx_rx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_DFX_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_srds_dfx_tx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_DFX_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_srds_dfx_tx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_DFX_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_srds_dsp_rx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_DSP_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_srds_dsp_rx_isi_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_DSP_RX_ISI_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_srds_dsp_rx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_DSP_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_srds_eee_rx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_EEE_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_srds_eee_rx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_EEE_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_srds_eee_tx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_EEE_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_srds_eee_tx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_EEE_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_srds_pcs_tx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_PCS_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_srds_pcs_tx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_PCS_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_srds_trn_rx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_TRN_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_srds_trn_rx_divn_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_TRN_RX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_srds_trn_rx_divn_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_TRN_RX_DIVN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_srds_trn_rx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_TRN_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_srds_trn_tx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_TRN_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_srds_trn_tx_divn_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_TRN_TX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_srds_trn_tx_divn_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_TRN_TX_DIVN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_srds_trn_tx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_TRN_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_srds_ux_ctrl_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_UX_CTRL_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_srds_ux_ctrl_cmn_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_UX_CTRL_CMN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_srds_ux_ctrl_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_UX_CTRL_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_srds_ux_tx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_UX_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_srds_ux_tx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_UX_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_timer_en_attr == SERDES_SHIM_CAR_L2_CFG_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_timer_value_attr == 8'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_transmit_mode_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_tx_postdiv_clk_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_txelecidle_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_txelecidle_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_txpstate_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l2_cfg_txpstate_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_apb_dsp_clk_sel_attr == SERDES_SHIM_CAR_L3_CFG_APB_DSP_CLK_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_apb_dsp_divn_en_attr == SERDES_SHIM_CAR_L3_CFG_APB_DSP_DIVN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_apb_dsp_divn_value_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_apb_dsp_pclken_attr == SERDES_SHIM_CAR_L3_CFG_APB_DSP_PCLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_apb_dsp_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_APB_DSP_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_dp_rx_80b_swz_attr == SERDES_SHIM_CAR_L3_CFG_DP_RX_80B_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_dp_tx_80b_swz_attr == SERDES_SHIM_CAR_L3_CFG_DP_TX_80B_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_eee_alert_force_en_attr == SERDES_SHIM_CAR_L3_CFG_EEE_ALERT_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_eee_alert_force_val_attr == SERDES_SHIM_CAR_L3_CFG_EEE_ALERT_FORCE_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_flux_srds_tx_divn_clken_attr == SERDES_SHIM_CAR_L3_CFG_FLUX_SRDS_TX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_iflux_tx_or_apb_clk_for_ux_ctrl_clk_sel_attr == SERDES_SHIM_CAR_L3_CFG_IFLUX_TX_OR_APB_CLK_FOR_UX_CTRL_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_oflux_srds_rx_clken_attr == SERDES_SHIM_CAR_L3_CFG_OFLUX_SRDS_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_oflux_srds_rx_divn_clken_attr == SERDES_SHIM_CAR_L3_CFG_OFLUX_SRDS_RX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_oflux_srds_tx_clken_attr == SERDES_SHIM_CAR_L3_CFG_OFLUX_SRDS_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_pcs_ick_ctrl_cmn_clk_sel_attr == SERDES_SHIM_CAR_L3_CFG_PCS_ICK_CTRL_CMN_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_pcs_ick_ctrl_l0_clk_sel_attr == SERDES_SHIM_CAR_L3_CFG_PCS_ICK_CTRL_L0_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_rxovrcdrlock2data_attr == SERDES_SHIM_CAR_L3_CFG_RXOVRCDRLOCK2DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_rxovrcdrlock2data_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_rxovrcdrlock2dataen_attr == SERDES_SHIM_CAR_L3_CFG_RXOVRCDRLOCK2DATAEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_rxovrcdrlock2dataen_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_rxpstate_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_rxpstate_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_srds_an_rx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_AN_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_srds_an_rx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_AN_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_srds_an_tx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_AN_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_srds_an_tx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_AN_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_srds_ctrl_rx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_CTRL_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_srds_ctrl_rx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_CTRL_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_srds_ctrl_tx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_CTRL_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_srds_ctrl_tx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_CTRL_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_srds_dfx_rx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_DFX_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_srds_dfx_rx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_DFX_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_srds_dfx_tx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_DFX_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_srds_dfx_tx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_DFX_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_srds_dsp_rx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_DSP_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_srds_dsp_rx_isi_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_DSP_RX_ISI_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_srds_dsp_rx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_DSP_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_srds_eee_rx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_EEE_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_srds_eee_rx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_EEE_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_srds_eee_tx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_EEE_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_srds_eee_tx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_EEE_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_srds_pcs_tx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_PCS_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_srds_pcs_tx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_PCS_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_srds_trn_rx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_TRN_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_srds_trn_rx_divn_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_TRN_RX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_srds_trn_rx_divn_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_TRN_RX_DIVN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_srds_trn_rx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_TRN_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_srds_trn_tx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_TRN_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_srds_trn_tx_divn_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_TRN_TX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_srds_trn_tx_divn_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_TRN_TX_DIVN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_srds_trn_tx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_TRN_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_srds_ux_ctrl_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_UX_CTRL_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_srds_ux_ctrl_cmn_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_UX_CTRL_CMN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_srds_ux_ctrl_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_UX_CTRL_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_srds_ux_tx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_UX_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_srds_ux_tx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_UX_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_timer_en_attr == SERDES_SHIM_CAR_L3_CFG_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_timer_value_attr == 8'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_transmit_mode_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_tx_postdiv_clk_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_txelecidle_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_txelecidle_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_txpstate_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_car_l3_cfg_txpstate_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_cpu_atresetn_attr == SERDES_SHIM_CPU_PM_CFG_CPU_ATRESETN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_cpu_breakin_attr == SERDES_SHIM_CPU_PM_CFG_CPU_BREAKIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_cpu_breakoutack_attr == SERDES_SHIM_CPU_PM_CFG_CPU_BREAKOUTACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_cpu_crosstriggerin_attr == SERDES_SHIM_CPU_PM_CFG_CPU_CROSSTRIGGERIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_cpu_crosstriggeroutack_attr == SERDES_SHIM_CPU_PM_CFG_CPU_CROSSTRIGGEROUTACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_cpu_ocdhaltonreset_attr == SERDES_SHIM_CPU_PM_CFG_CPU_OCDHALTONRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_cpu_pdebugenable_attr == SERDES_SHIM_CPU_PM_CFG_CPU_PDEBUGENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_cpu_prid_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_cpu_statvectorsel_attr == SERDES_SHIM_CPU_PM_CFG_CPU_STATVECTORSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_cpu_tmodeclkgateoverride_reserved_attr == SERDES_SHIM_CPU_PM_CFG_CPU_TMODECLKGATEOVERRIDE_RESERVED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_dram_pwr_mgmt_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_dram0_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_DRAM0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_dram1_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_DRAM1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_dram2_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_DRAM2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_dram3_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_DRAM3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_fifo_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_FIFO_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_iram0_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_IRAM0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_iram1_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_IRAM1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_iram2_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_IRAM2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_iram3_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_IRAM3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_iram4_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_IRAM4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_iram5_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_IRAM5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_iram6_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_IRAM6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_iram7_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_IRAM7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_trace_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_TRACE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_dram0_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_DRAM0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_dram1_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_DRAM1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_dram2_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_DRAM2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_dram3_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_DRAM3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_fifo_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_FIFO_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_iram0_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_IRAM0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_iram1_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_IRAM1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_iram2_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_IRAM2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_iram3_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_IRAM3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_iram4_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_IRAM4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_iram5_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_IRAM5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_iram6_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_IRAM6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_iram7_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_IRAM7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_trace_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_TRACE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_dram0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_dram1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_dram2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_dram3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_iram0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_iram1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_iram2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_iram3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_iram4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_iram5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_iram6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_iram7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_trace_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_dram0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_dram1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_dram2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_dram3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_fifo_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_iram0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_iram1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_iram2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_iram3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_iram4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_iram5_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_iram6_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_iram7_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_trace_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_dram0_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_dram1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_dram2_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_dram3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_fifo_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_iram0_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_iram1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_iram2_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_iram3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_iram4_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_iram5_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_iram6_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_iram7_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_trace_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_dram0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_dram1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_dram2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_dram3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_fifo_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_iram0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_iram1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_iram2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_iram3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_iram4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_iram5_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_iram6_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_iram7_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_trace_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_dram0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_dram1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_dram2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_dram3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_fifo_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_iram0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_iram1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_iram2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_iram3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_iram4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_iram5_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_iram6_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_iram7_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_trace_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fw_status_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_fw_version_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_iramh_pwr_mgmt_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_iraml_pwr_mgmt_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_nmi_icu_mux_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_tb_reg0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_tb_reg1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_tb_reg2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_tb_reg3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_tb_reg4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_tie_queue_pwr_mgmt_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_cpu_pm_cfg_tram_pwr_mgmt_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_acc_clr_en_attr == SERDES_SHIM_DSP_L0_CFG_ACC_CLR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_acc_clr_rst_attr == SERDES_SHIM_DSP_L0_CFG_ACC_CLR_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_agc_acc_clr_attr == SERDES_SHIM_DSP_L0_CFG_AGC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_agc_clr_en_attr == SERDES_SHIM_DSP_L0_CFG_AGC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_agc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_agc_coarse_det_en_attr == SERDES_SHIM_DSP_L0_CFG_AGC_COARSE_DET_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_agc_coarse_det_pol_attr == SERDES_SHIM_DSP_L0_CFG_AGC_COARSE_DET_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_agc_d_sign_attr == SERDES_SHIM_DSP_L0_CFG_AGC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_agc_en_attr == SERDES_SHIM_DSP_L0_CFG_AGC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_agc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_agc_event_sign_attr == SERDES_SHIM_DSP_L0_CFG_AGC_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_agc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_agc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_agc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_agc_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_bb_stable_attr == SERDES_SHIM_DSP_L0_CFG_BB_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ctle_hf_stable_attr == SERDES_SHIM_DSP_L0_CFG_CTLE_HF_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_d_dly_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_data_sel_mux_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_data_width_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe10_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe11_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe12_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe13_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe14_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe15_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe16_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe1_clr_en_attr == SERDES_SHIM_DSP_L0_CFG_DFE1_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe1_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe1_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe1_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe2_16_clr_en_attr == SERDES_SHIM_DSP_L0_CFG_DFE2_16_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe2_16_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe2_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe4_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe5_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe6_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe7_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe8_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe9_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_0_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_10_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_11_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_12_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_13_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_14_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_15_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_1_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_2_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_3_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_4_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_5_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_6_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_7_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_8_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_9_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_all_taps_en_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_ALL_TAPS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_0_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_10_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_11_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_12_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_13_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_14_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_15_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_1_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_2_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_3_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_4_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_5_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_6_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_7_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_8_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_9_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_common_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_common_th_en_attr == SERDES_SHIM_DSP_L0_CFG_DFE_COMMON_TH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_d_sign_attr == SERDES_SHIM_DSP_L0_CFG_DFE_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_event_sign_attr == SERDES_SHIM_DSP_L0_CFG_DFE_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_tap10_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_tap11_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_tap12_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_tap13_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_tap14_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_tap15_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_tap16_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_tap1_sel_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dfe_tap9_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dsp_bit_swz_attr == SERDES_SHIM_DSP_L0_CFG_DSP_BIT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dsp_d_swz_attr == SERDES_SHIM_DSP_L0_CFG_DSP_D_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dsp_en_attr == SERDES_SHIM_DSP_L0_CFG_DSP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dsp_inner_d_swz_attr == SERDES_SHIM_DSP_L0_CFG_DSP_INNER_D_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dsp_inner_m_swz_attr == SERDES_SHIM_DSP_L0_CFG_DSP_INNER_M_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dsp_latch_dis_attr == SERDES_SHIM_DSP_L0_CFG_DSP_LATCH_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dsp_m_swz_attr == SERDES_SHIM_DSP_L0_CFG_DSP_M_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_dsp_sticky_clr_attr == SERDES_SHIM_DSP_L0_CFG_DSP_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_e_dly_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ehm_acc_clr_attr == SERDES_SHIM_DSP_L0_CFG_EHM_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ehm_event_rate_lsb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ehm_event_rate_msb_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ehm_event_sign_attr == SERDES_SHIM_DSP_L0_CFG_EHM_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ehm_sym1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ehm_sym_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ehm_tap_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ehm_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_en_duration_cnt_trig_attr == SERDES_SHIM_DSP_L0_CFG_EN_DURATION_CNT_TRIG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_en_duration_val_attr == 16'd625
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_err_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_err_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_error_counter_clr_attr == SERDES_SHIM_DSP_L0_CFG_ERROR_COUNTER_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_error_counter_enable_attr == SERDES_SHIM_DSP_L0_CFG_ERROR_COUNTER_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_error_counter_even_odd_select_attr == SERDES_SHIM_DSP_L0_CFG_ERROR_COUNTER_EVEN_ODD_SELECT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_error_counter_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_error_counter_resetb_attr == SERDES_SHIM_DSP_L0_CFG_ERROR_COUNTER_RESETB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_error_sel_mux_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_fine_attr == SERDES_SHIM_DSP_L0_CFG_FINE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_acc_clr1_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_acc_clr2_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_acc_clr3_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_acc_clr4_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_acc_clr5_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_acc_clr6_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_acc_clr7_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_acc_clr8_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_en_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_gps_tap32_sel_attr == SERDES_SHIM_DSP_L0_CFG_GPS_TAP32_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_gps_tap64_sel_attr == SERDES_SHIM_DSP_L0_CFG_GPS_TAP64_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ingress_dsp_disable_chkn_bit_attr == SERDES_SHIM_DSP_L0_CFG_INGRESS_DSP_DISABLE_CHKN_BIT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_io_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_joint_dfe_en_attr == SERDES_SHIM_DSP_L0_CFG_JOINT_DFE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_acc_clr_attr == SERDES_SHIM_DSP_L0_CFG_OFC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_clr_en_attr == SERDES_SHIM_DSP_L0_CFG_OFC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_cnt_offset_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_d_sign_attr == SERDES_SHIM_DSP_L0_CFG_OFC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_en_attr == SERDES_SHIM_DSP_L0_CFG_OFC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_event_sign_attr == SERDES_SHIM_DSP_L0_CFG_OFC_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_acc_clr1_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_acc_clr2_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_acc_clr3_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_acc_clr4_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_acc_clr5_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_acc_clr6_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_acc_clr7_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_acc_clr8_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_en_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_acc_clr1_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_acc_clr2_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_acc_clr3_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_acc_clr4_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_acc_clr5_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_acc_clr6_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_acc_clr7_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_acc_clr8_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_en_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_lsb_inv_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_LSB_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_lsb_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_ofc_th_attr == 20'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_pam4_bit_flip_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_pam4_gray_enable_attr == SERDES_SHIM_DSP_L0_CFG_PAM4_GRAY_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_pam_4_en_attr == SERDES_SHIM_DSP_L0_CFG_PAM_4_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_phase_cnt_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_phase_mask0_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_phase_mask1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_phase_mask2_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_phase_mask3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_phase_num_mask_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_pol_invert_attr == SERDES_SHIM_DSP_L0_CFG_POL_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_power_save_en_attr == SERDES_SHIM_DSP_L0_CFG_POWER_SAVE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_regs2visa_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_regs2visa_en_attr == SERDES_SHIM_DSP_L0_CFG_REGS2VISA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_res_isi_mes_en_attr == SERDES_SHIM_DSP_L0_CFG_RES_ISI_MES_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_snr_div_facror_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_snr_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_snr_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_snr_meter_en_attr == SERDES_SHIM_DSP_L0_CFG_SNR_METER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_snr_smooth_bw_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_0_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_10_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_11_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_12_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_13_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_14_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_15_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_16_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_17_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_18_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_1_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_2_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_3_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_4_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_5_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_6_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_7_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_8_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_9_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_swap_bot_en_attr == SERDES_SHIM_DSP_L0_CFG_SWAP_BOT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_swap_top_en_attr == SERDES_SHIM_DSP_L0_CFG_SWAP_TOP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_timeout_counter_value_attr == 17'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_vga_acc_clr_attr == SERDES_SHIM_DSP_L0_CFG_VGA_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_vga_clr_en_attr == SERDES_SHIM_DSP_L0_CFG_VGA_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_vga_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_vga_en_attr == SERDES_SHIM_DSP_L0_CFG_VGA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_vga_range_detect_comp_const_h_attr == 7'd126
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_vga_range_detect_comp_const_l_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_vga_range_detect_sub_const_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_vga_shift_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_vga_sticky_clr_attr == SERDES_SHIM_DSP_L0_CFG_VGA_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_vga_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_vref_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_x3_acc_clr_attr == SERDES_SHIM_DSP_L0_CFG_X3_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_x3_en_attr == SERDES_SHIM_DSP_L0_CFG_X3_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_x3_sticky_clr_attr == SERDES_SHIM_DSP_L0_CFG_X3_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l0_cfg_x3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_acc_clr_en_attr == SERDES_SHIM_DSP_L1_CFG_ACC_CLR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_acc_clr_rst_attr == SERDES_SHIM_DSP_L1_CFG_ACC_CLR_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_agc_acc_clr_attr == SERDES_SHIM_DSP_L1_CFG_AGC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_agc_clr_en_attr == SERDES_SHIM_DSP_L1_CFG_AGC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_agc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_agc_coarse_det_en_attr == SERDES_SHIM_DSP_L1_CFG_AGC_COARSE_DET_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_agc_coarse_det_pol_attr == SERDES_SHIM_DSP_L1_CFG_AGC_COARSE_DET_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_agc_d_sign_attr == SERDES_SHIM_DSP_L1_CFG_AGC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_agc_en_attr == SERDES_SHIM_DSP_L1_CFG_AGC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_agc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_agc_event_sign_attr == SERDES_SHIM_DSP_L1_CFG_AGC_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_agc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_agc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_agc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_agc_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_bb_stable_attr == SERDES_SHIM_DSP_L1_CFG_BB_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ctle_hf_stable_attr == SERDES_SHIM_DSP_L1_CFG_CTLE_HF_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_d_dly_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_data_sel_mux_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_data_width_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe10_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe11_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe12_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe13_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe14_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe15_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe16_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe1_clr_en_attr == SERDES_SHIM_DSP_L1_CFG_DFE1_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe1_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe1_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe1_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe2_16_clr_en_attr == SERDES_SHIM_DSP_L1_CFG_DFE2_16_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe2_16_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe2_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe4_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe5_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe6_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe7_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe8_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe9_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_0_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_10_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_11_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_12_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_13_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_14_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_15_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_1_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_2_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_3_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_4_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_5_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_6_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_7_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_8_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_9_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_all_taps_en_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_ALL_TAPS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_0_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_10_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_11_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_12_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_13_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_14_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_15_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_1_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_2_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_3_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_4_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_5_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_6_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_7_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_8_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_9_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_common_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_common_th_en_attr == SERDES_SHIM_DSP_L1_CFG_DFE_COMMON_TH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_d_sign_attr == SERDES_SHIM_DSP_L1_CFG_DFE_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_event_sign_attr == SERDES_SHIM_DSP_L1_CFG_DFE_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_tap10_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_tap11_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_tap12_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_tap13_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_tap14_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_tap15_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_tap16_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_tap1_sel_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dfe_tap9_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dsp_bit_swz_attr == SERDES_SHIM_DSP_L1_CFG_DSP_BIT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dsp_d_swz_attr == SERDES_SHIM_DSP_L1_CFG_DSP_D_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dsp_en_attr == SERDES_SHIM_DSP_L1_CFG_DSP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dsp_inner_d_swz_attr == SERDES_SHIM_DSP_L1_CFG_DSP_INNER_D_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dsp_inner_m_swz_attr == SERDES_SHIM_DSP_L1_CFG_DSP_INNER_M_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dsp_latch_dis_attr == SERDES_SHIM_DSP_L1_CFG_DSP_LATCH_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dsp_m_swz_attr == SERDES_SHIM_DSP_L1_CFG_DSP_M_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_dsp_sticky_clr_attr == SERDES_SHIM_DSP_L1_CFG_DSP_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_e_dly_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ehm_acc_clr_attr == SERDES_SHIM_DSP_L1_CFG_EHM_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ehm_event_rate_lsb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ehm_event_rate_msb_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ehm_event_sign_attr == SERDES_SHIM_DSP_L1_CFG_EHM_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ehm_sym1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ehm_sym_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ehm_tap_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ehm_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_en_duration_cnt_trig_attr == SERDES_SHIM_DSP_L1_CFG_EN_DURATION_CNT_TRIG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_en_duration_val_attr == 16'd625
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_err_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_err_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_error_counter_clr_attr == SERDES_SHIM_DSP_L1_CFG_ERROR_COUNTER_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_error_counter_enable_attr == SERDES_SHIM_DSP_L1_CFG_ERROR_COUNTER_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_error_counter_even_odd_select_attr == SERDES_SHIM_DSP_L1_CFG_ERROR_COUNTER_EVEN_ODD_SELECT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_error_counter_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_error_counter_resetb_attr == SERDES_SHIM_DSP_L1_CFG_ERROR_COUNTER_RESETB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_error_sel_mux_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_fine_attr == SERDES_SHIM_DSP_L1_CFG_FINE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_acc_clr1_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_acc_clr2_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_acc_clr3_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_acc_clr4_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_acc_clr5_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_acc_clr6_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_acc_clr7_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_acc_clr8_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_en_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_gps_tap32_sel_attr == SERDES_SHIM_DSP_L1_CFG_GPS_TAP32_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_gps_tap64_sel_attr == SERDES_SHIM_DSP_L1_CFG_GPS_TAP64_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ingress_dsp_disable_chkn_bit_attr == SERDES_SHIM_DSP_L1_CFG_INGRESS_DSP_DISABLE_CHKN_BIT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_io_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_joint_dfe_en_attr == SERDES_SHIM_DSP_L1_CFG_JOINT_DFE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_acc_clr_attr == SERDES_SHIM_DSP_L1_CFG_OFC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_clr_en_attr == SERDES_SHIM_DSP_L1_CFG_OFC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_cnt_offset_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_d_sign_attr == SERDES_SHIM_DSP_L1_CFG_OFC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_en_attr == SERDES_SHIM_DSP_L1_CFG_OFC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_event_sign_attr == SERDES_SHIM_DSP_L1_CFG_OFC_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_acc_clr1_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_acc_clr2_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_acc_clr3_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_acc_clr4_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_acc_clr5_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_acc_clr6_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_acc_clr7_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_acc_clr8_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_en_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_acc_clr1_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_acc_clr2_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_acc_clr3_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_acc_clr4_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_acc_clr5_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_acc_clr6_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_acc_clr7_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_acc_clr8_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_en_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_lsb_inv_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_LSB_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_lsb_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_ofc_th_attr == 20'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_pam4_bit_flip_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_pam4_gray_enable_attr == SERDES_SHIM_DSP_L1_CFG_PAM4_GRAY_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_pam_4_en_attr == SERDES_SHIM_DSP_L1_CFG_PAM_4_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_phase_cnt_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_phase_mask0_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_phase_mask1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_phase_mask2_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_phase_mask3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_phase_num_mask_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_pol_invert_attr == SERDES_SHIM_DSP_L1_CFG_POL_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_power_save_en_attr == SERDES_SHIM_DSP_L1_CFG_POWER_SAVE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_regs2visa_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_regs2visa_en_attr == SERDES_SHIM_DSP_L1_CFG_REGS2VISA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_res_isi_mes_en_attr == SERDES_SHIM_DSP_L1_CFG_RES_ISI_MES_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_snr_div_facror_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_snr_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_snr_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_snr_meter_en_attr == SERDES_SHIM_DSP_L1_CFG_SNR_METER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_snr_smooth_bw_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_0_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_10_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_11_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_12_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_13_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_14_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_15_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_16_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_17_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_18_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_1_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_2_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_3_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_4_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_5_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_6_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_7_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_8_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_9_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_swap_bot_en_attr == SERDES_SHIM_DSP_L1_CFG_SWAP_BOT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_swap_top_en_attr == SERDES_SHIM_DSP_L1_CFG_SWAP_TOP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_timeout_counter_value_attr == 17'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_vga_acc_clr_attr == SERDES_SHIM_DSP_L1_CFG_VGA_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_vga_clr_en_attr == SERDES_SHIM_DSP_L1_CFG_VGA_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_vga_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_vga_en_attr == SERDES_SHIM_DSP_L1_CFG_VGA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_vga_range_detect_comp_const_h_attr == 7'd126
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_vga_range_detect_comp_const_l_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_vga_range_detect_sub_const_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_vga_shift_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_vga_sticky_clr_attr == SERDES_SHIM_DSP_L1_CFG_VGA_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_vga_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_vref_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_x3_acc_clr_attr == SERDES_SHIM_DSP_L1_CFG_X3_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_x3_en_attr == SERDES_SHIM_DSP_L1_CFG_X3_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_x3_sticky_clr_attr == SERDES_SHIM_DSP_L1_CFG_X3_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l1_cfg_x3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_acc_clr_en_attr == SERDES_SHIM_DSP_L2_CFG_ACC_CLR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_acc_clr_rst_attr == SERDES_SHIM_DSP_L2_CFG_ACC_CLR_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_agc_acc_clr_attr == SERDES_SHIM_DSP_L2_CFG_AGC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_agc_clr_en_attr == SERDES_SHIM_DSP_L2_CFG_AGC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_agc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_agc_coarse_det_en_attr == SERDES_SHIM_DSP_L2_CFG_AGC_COARSE_DET_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_agc_coarse_det_pol_attr == SERDES_SHIM_DSP_L2_CFG_AGC_COARSE_DET_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_agc_d_sign_attr == SERDES_SHIM_DSP_L2_CFG_AGC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_agc_en_attr == SERDES_SHIM_DSP_L2_CFG_AGC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_agc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_agc_event_sign_attr == SERDES_SHIM_DSP_L2_CFG_AGC_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_agc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_agc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_agc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_agc_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_bb_stable_attr == SERDES_SHIM_DSP_L2_CFG_BB_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ctle_hf_stable_attr == SERDES_SHIM_DSP_L2_CFG_CTLE_HF_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_d_dly_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_data_sel_mux_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_data_width_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe10_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe11_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe12_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe13_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe14_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe15_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe16_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe1_clr_en_attr == SERDES_SHIM_DSP_L2_CFG_DFE1_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe1_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe1_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe1_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe2_16_clr_en_attr == SERDES_SHIM_DSP_L2_CFG_DFE2_16_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe2_16_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe2_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe4_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe5_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe6_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe7_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe8_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe9_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_0_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_10_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_11_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_12_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_13_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_14_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_15_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_1_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_2_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_3_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_4_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_5_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_6_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_7_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_8_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_9_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_all_taps_en_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_ALL_TAPS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_0_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_10_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_11_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_12_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_13_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_14_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_15_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_1_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_2_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_3_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_4_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_5_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_6_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_7_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_8_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_9_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_common_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_common_th_en_attr == SERDES_SHIM_DSP_L2_CFG_DFE_COMMON_TH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_d_sign_attr == SERDES_SHIM_DSP_L2_CFG_DFE_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_event_sign_attr == SERDES_SHIM_DSP_L2_CFG_DFE_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_tap10_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_tap11_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_tap12_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_tap13_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_tap14_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_tap15_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_tap16_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_tap1_sel_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dfe_tap9_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dsp_bit_swz_attr == SERDES_SHIM_DSP_L2_CFG_DSP_BIT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dsp_d_swz_attr == SERDES_SHIM_DSP_L2_CFG_DSP_D_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dsp_en_attr == SERDES_SHIM_DSP_L2_CFG_DSP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dsp_inner_d_swz_attr == SERDES_SHIM_DSP_L2_CFG_DSP_INNER_D_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dsp_inner_m_swz_attr == SERDES_SHIM_DSP_L2_CFG_DSP_INNER_M_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dsp_latch_dis_attr == SERDES_SHIM_DSP_L2_CFG_DSP_LATCH_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dsp_m_swz_attr == SERDES_SHIM_DSP_L2_CFG_DSP_M_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_dsp_sticky_clr_attr == SERDES_SHIM_DSP_L2_CFG_DSP_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_e_dly_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ehm_acc_clr_attr == SERDES_SHIM_DSP_L2_CFG_EHM_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ehm_event_rate_lsb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ehm_event_rate_msb_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ehm_event_sign_attr == SERDES_SHIM_DSP_L2_CFG_EHM_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ehm_sym1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ehm_sym_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ehm_tap_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ehm_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_en_duration_cnt_trig_attr == SERDES_SHIM_DSP_L2_CFG_EN_DURATION_CNT_TRIG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_en_duration_val_attr == 16'd625
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_err_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_err_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_error_counter_clr_attr == SERDES_SHIM_DSP_L2_CFG_ERROR_COUNTER_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_error_counter_enable_attr == SERDES_SHIM_DSP_L2_CFG_ERROR_COUNTER_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_error_counter_even_odd_select_attr == SERDES_SHIM_DSP_L2_CFG_ERROR_COUNTER_EVEN_ODD_SELECT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_error_counter_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_error_counter_resetb_attr == SERDES_SHIM_DSP_L2_CFG_ERROR_COUNTER_RESETB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_error_sel_mux_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_fine_attr == SERDES_SHIM_DSP_L2_CFG_FINE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_acc_clr1_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_acc_clr2_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_acc_clr3_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_acc_clr4_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_acc_clr5_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_acc_clr6_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_acc_clr7_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_acc_clr8_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_en_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_gps_tap32_sel_attr == SERDES_SHIM_DSP_L2_CFG_GPS_TAP32_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_gps_tap64_sel_attr == SERDES_SHIM_DSP_L2_CFG_GPS_TAP64_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ingress_dsp_disable_chkn_bit_attr == SERDES_SHIM_DSP_L2_CFG_INGRESS_DSP_DISABLE_CHKN_BIT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_io_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_joint_dfe_en_attr == SERDES_SHIM_DSP_L2_CFG_JOINT_DFE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_acc_clr_attr == SERDES_SHIM_DSP_L2_CFG_OFC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_clr_en_attr == SERDES_SHIM_DSP_L2_CFG_OFC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_cnt_offset_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_d_sign_attr == SERDES_SHIM_DSP_L2_CFG_OFC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_en_attr == SERDES_SHIM_DSP_L2_CFG_OFC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_event_sign_attr == SERDES_SHIM_DSP_L2_CFG_OFC_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_acc_clr1_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_acc_clr2_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_acc_clr3_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_acc_clr4_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_acc_clr5_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_acc_clr6_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_acc_clr7_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_acc_clr8_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_en_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_acc_clr1_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_acc_clr2_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_acc_clr3_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_acc_clr4_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_acc_clr5_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_acc_clr6_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_acc_clr7_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_acc_clr8_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_en_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_lsb_inv_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_LSB_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_lsb_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_ofc_th_attr == 20'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_pam4_bit_flip_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_pam4_gray_enable_attr == SERDES_SHIM_DSP_L2_CFG_PAM4_GRAY_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_pam_4_en_attr == SERDES_SHIM_DSP_L2_CFG_PAM_4_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_phase_cnt_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_phase_mask0_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_phase_mask1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_phase_mask2_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_phase_mask3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_phase_num_mask_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_pol_invert_attr == SERDES_SHIM_DSP_L2_CFG_POL_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_power_save_en_attr == SERDES_SHIM_DSP_L2_CFG_POWER_SAVE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_regs2visa_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_regs2visa_en_attr == SERDES_SHIM_DSP_L2_CFG_REGS2VISA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_res_isi_mes_en_attr == SERDES_SHIM_DSP_L2_CFG_RES_ISI_MES_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_snr_div_facror_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_snr_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_snr_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_snr_meter_en_attr == SERDES_SHIM_DSP_L2_CFG_SNR_METER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_snr_smooth_bw_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_0_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_10_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_11_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_12_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_13_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_14_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_15_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_16_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_17_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_18_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_1_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_2_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_3_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_4_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_5_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_6_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_7_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_8_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_9_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_swap_bot_en_attr == SERDES_SHIM_DSP_L2_CFG_SWAP_BOT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_swap_top_en_attr == SERDES_SHIM_DSP_L2_CFG_SWAP_TOP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_timeout_counter_value_attr == 17'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_vga_acc_clr_attr == SERDES_SHIM_DSP_L2_CFG_VGA_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_vga_clr_en_attr == SERDES_SHIM_DSP_L2_CFG_VGA_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_vga_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_vga_en_attr == SERDES_SHIM_DSP_L2_CFG_VGA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_vga_range_detect_comp_const_h_attr == 7'd126
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_vga_range_detect_comp_const_l_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_vga_range_detect_sub_const_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_vga_shift_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_vga_sticky_clr_attr == SERDES_SHIM_DSP_L2_CFG_VGA_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_vga_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_vref_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_x3_acc_clr_attr == SERDES_SHIM_DSP_L2_CFG_X3_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_x3_en_attr == SERDES_SHIM_DSP_L2_CFG_X3_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_x3_sticky_clr_attr == SERDES_SHIM_DSP_L2_CFG_X3_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l2_cfg_x3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_acc_clr_en_attr == SERDES_SHIM_DSP_L3_CFG_ACC_CLR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_acc_clr_rst_attr == SERDES_SHIM_DSP_L3_CFG_ACC_CLR_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_agc_acc_clr_attr == SERDES_SHIM_DSP_L3_CFG_AGC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_agc_clr_en_attr == SERDES_SHIM_DSP_L3_CFG_AGC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_agc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_agc_coarse_det_en_attr == SERDES_SHIM_DSP_L3_CFG_AGC_COARSE_DET_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_agc_coarse_det_pol_attr == SERDES_SHIM_DSP_L3_CFG_AGC_COARSE_DET_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_agc_d_sign_attr == SERDES_SHIM_DSP_L3_CFG_AGC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_agc_en_attr == SERDES_SHIM_DSP_L3_CFG_AGC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_agc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_agc_event_sign_attr == SERDES_SHIM_DSP_L3_CFG_AGC_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_agc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_agc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_agc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_agc_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_bb_stable_attr == SERDES_SHIM_DSP_L3_CFG_BB_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ctle_hf_stable_attr == SERDES_SHIM_DSP_L3_CFG_CTLE_HF_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_d_dly_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_data_sel_mux_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_data_width_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe10_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe11_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe12_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe13_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe14_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe15_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe16_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe1_clr_en_attr == SERDES_SHIM_DSP_L3_CFG_DFE1_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe1_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe1_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe1_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe2_16_clr_en_attr == SERDES_SHIM_DSP_L3_CFG_DFE2_16_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe2_16_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe2_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe4_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe5_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe6_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe7_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe8_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe9_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_0_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_10_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_11_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_12_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_13_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_14_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_15_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_1_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_2_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_3_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_4_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_5_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_6_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_7_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_8_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_9_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_all_taps_en_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_ALL_TAPS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_0_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_10_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_11_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_12_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_13_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_14_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_15_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_1_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_2_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_3_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_4_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_5_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_6_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_7_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_8_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_9_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_common_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_common_th_en_attr == SERDES_SHIM_DSP_L3_CFG_DFE_COMMON_TH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_d_sign_attr == SERDES_SHIM_DSP_L3_CFG_DFE_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_event_sign_attr == SERDES_SHIM_DSP_L3_CFG_DFE_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_tap10_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_tap11_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_tap12_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_tap13_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_tap14_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_tap15_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_tap16_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_tap1_sel_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dfe_tap9_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dsp_bit_swz_attr == SERDES_SHIM_DSP_L3_CFG_DSP_BIT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dsp_d_swz_attr == SERDES_SHIM_DSP_L3_CFG_DSP_D_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dsp_en_attr == SERDES_SHIM_DSP_L3_CFG_DSP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dsp_inner_d_swz_attr == SERDES_SHIM_DSP_L3_CFG_DSP_INNER_D_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dsp_inner_m_swz_attr == SERDES_SHIM_DSP_L3_CFG_DSP_INNER_M_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dsp_latch_dis_attr == SERDES_SHIM_DSP_L3_CFG_DSP_LATCH_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dsp_m_swz_attr == SERDES_SHIM_DSP_L3_CFG_DSP_M_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_dsp_sticky_clr_attr == SERDES_SHIM_DSP_L3_CFG_DSP_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_e_dly_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ehm_acc_clr_attr == SERDES_SHIM_DSP_L3_CFG_EHM_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ehm_event_rate_lsb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ehm_event_rate_msb_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ehm_event_sign_attr == SERDES_SHIM_DSP_L3_CFG_EHM_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ehm_sym1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ehm_sym_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ehm_tap_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ehm_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_en_duration_cnt_trig_attr == SERDES_SHIM_DSP_L3_CFG_EN_DURATION_CNT_TRIG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_en_duration_val_attr == 16'd625
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_err_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_err_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_error_counter_clr_attr == SERDES_SHIM_DSP_L3_CFG_ERROR_COUNTER_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_error_counter_enable_attr == SERDES_SHIM_DSP_L3_CFG_ERROR_COUNTER_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_error_counter_even_odd_select_attr == SERDES_SHIM_DSP_L3_CFG_ERROR_COUNTER_EVEN_ODD_SELECT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_error_counter_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_error_counter_resetb_attr == SERDES_SHIM_DSP_L3_CFG_ERROR_COUNTER_RESETB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_error_sel_mux_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_fine_attr == SERDES_SHIM_DSP_L3_CFG_FINE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_acc_clr1_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_acc_clr2_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_acc_clr3_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_acc_clr4_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_acc_clr5_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_acc_clr6_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_acc_clr7_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_acc_clr8_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_en_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_gps_tap32_sel_attr == SERDES_SHIM_DSP_L3_CFG_GPS_TAP32_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_gps_tap64_sel_attr == SERDES_SHIM_DSP_L3_CFG_GPS_TAP64_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ingress_dsp_disable_chkn_bit_attr == SERDES_SHIM_DSP_L3_CFG_INGRESS_DSP_DISABLE_CHKN_BIT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_io_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_joint_dfe_en_attr == SERDES_SHIM_DSP_L3_CFG_JOINT_DFE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_acc_clr_attr == SERDES_SHIM_DSP_L3_CFG_OFC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_clr_en_attr == SERDES_SHIM_DSP_L3_CFG_OFC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_cnt_offset_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_d_sign_attr == SERDES_SHIM_DSP_L3_CFG_OFC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_en_attr == SERDES_SHIM_DSP_L3_CFG_OFC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_event_sign_attr == SERDES_SHIM_DSP_L3_CFG_OFC_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_acc_clr1_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_acc_clr2_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_acc_clr3_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_acc_clr4_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_acc_clr5_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_acc_clr6_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_acc_clr7_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_acc_clr8_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_en_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_acc_clr1_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_acc_clr2_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_acc_clr3_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_acc_clr4_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_acc_clr5_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_acc_clr6_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_acc_clr7_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_acc_clr8_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_en_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_lsb_inv_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_LSB_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_lsb_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_ofc_th_attr == 20'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_pam4_bit_flip_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_pam4_gray_enable_attr == SERDES_SHIM_DSP_L3_CFG_PAM4_GRAY_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_pam_4_en_attr == SERDES_SHIM_DSP_L3_CFG_PAM_4_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_phase_cnt_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_phase_mask0_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_phase_mask1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_phase_mask2_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_phase_mask3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_phase_num_mask_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_pol_invert_attr == SERDES_SHIM_DSP_L3_CFG_POL_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_power_save_en_attr == SERDES_SHIM_DSP_L3_CFG_POWER_SAVE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_regs2visa_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_regs2visa_en_attr == SERDES_SHIM_DSP_L3_CFG_REGS2VISA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_res_isi_mes_en_attr == SERDES_SHIM_DSP_L3_CFG_RES_ISI_MES_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_snr_div_facror_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_snr_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_snr_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_snr_meter_en_attr == SERDES_SHIM_DSP_L3_CFG_SNR_METER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_snr_smooth_bw_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_0_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_10_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_11_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_12_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_13_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_14_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_15_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_16_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_17_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_18_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_1_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_2_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_3_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_4_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_5_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_6_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_7_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_8_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_9_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_swap_bot_en_attr == SERDES_SHIM_DSP_L3_CFG_SWAP_BOT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_swap_top_en_attr == SERDES_SHIM_DSP_L3_CFG_SWAP_TOP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_timeout_counter_value_attr == 17'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_vga_acc_clr_attr == SERDES_SHIM_DSP_L3_CFG_VGA_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_vga_clr_en_attr == SERDES_SHIM_DSP_L3_CFG_VGA_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_vga_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_vga_en_attr == SERDES_SHIM_DSP_L3_CFG_VGA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_vga_range_detect_comp_const_h_attr == 7'd126
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_vga_range_detect_comp_const_l_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_vga_range_detect_sub_const_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_vga_shift_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_vga_sticky_clr_attr == SERDES_SHIM_DSP_L3_CFG_VGA_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_vga_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_vref_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_x3_acc_clr_attr == SERDES_SHIM_DSP_L3_CFG_X3_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_x3_en_attr == SERDES_SHIM_DSP_L3_CFG_X3_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_x3_sticky_clr_attr == SERDES_SHIM_DSP_L3_CFG_X3_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_dsp_l3_cfg_x3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_cfg_prbs13_seed_2_attr == 13'd7571
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_cfg_prbs13_seed_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_cfg_tfl_prbs11_en_attr == SERDES_SHIM_TFL_L0_CFG_CFG_TFL_PRBS11_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_cl136_ctrl_field_11_10_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_cl136_ctrl_field_13_12_init_cond_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_cl136_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_cl136_ctrl_field_1_0_coeff_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_cl136_ctrl_field_4_2_coeff_select_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_cl136_ctrl_field_7_5_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_cl136_ctrl_field_9_8_mod_precode_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_cl136_frame_cycle_to_lock_attr == 10'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_cl136_prbs_encoder_select_even_attr == SERDES_SHIM_TFL_L0_CFG_CL136_PRBS_ENCODER_SELECT_EVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_cl136_precoder_out_swz_attr == SERDES_SHIM_TFL_L0_CFG_CL136_PRECODER_OUT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_cl136_precoder_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_cl136_stts_field_11_10_mod_precode_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_cl136_stts_field_14_12_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_cl136_stts_field_15_rx_ready_attr == SERDES_SHIM_TFL_L0_CFG_CL136_STTS_FIELD_15_RX_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_cl136_stts_field_2_0_coeff_stts_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_cl136_stts_field_5_3_coeff_sel_echo_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_cl136_stts_field_6_rsvd_attr == SERDES_SHIM_TFL_L0_CFG_CL136_STTS_FIELD_6_RSVD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_cl136_stts_field_7_parity_attr == SERDES_SHIM_TFL_L0_CFG_CL136_STTS_FIELD_7_PARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_cl136_stts_field_8_init_cond_stts_attr == SERDES_SHIM_TFL_L0_CFG_CL136_STTS_FIELD_8_INIT_COND_STTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_cl136_stts_field_9_rx_frame_lock_attr == SERDES_SHIM_TFL_L0_CFG_CL136_STTS_FIELD_9_RX_FRAME_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_cl72_ctrl_field_11_6_rsvd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_cl72_ctrl_field_12_initialize_attr == SERDES_SHIM_TFL_L0_CFG_CL72_CTRL_FIELD_12_INITIALIZE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_cl72_ctrl_field_13_preset_attr == SERDES_SHIM_TFL_L0_CFG_CL72_CTRL_FIELD_13_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_cl72_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_cl72_ctrl_field_1_0_coef_m1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_cl72_ctrl_field_3_2_coef_0_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_cl72_ctrl_field_5_4_coef_p1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_cl72_frame_cycle_to_lock_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_cl72_stts_field_14_6_rsvd_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_cl72_stts_field_15_rcv_ready_attr == SERDES_SHIM_TFL_L0_CFG_CL72_STTS_FIELD_15_RCV_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_cl72_stts_field_1_0_coef_m1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_cl72_stts_field_3_2_coef_0_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_cl72_stts_field_5_4_coef_p1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_frame_boundary_early_attr == SERDES_SHIM_TFL_L0_CFG_FRAME_BOUNDARY_EARLY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_gb_128_80_en_attr == SERDES_SHIM_TFL_L0_CFG_GB_128_80_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_ignore_tfl_en_to_avoid_cut_frame_attr == SERDES_SHIM_TFL_L0_CFG_IGNORE_TFL_EN_TO_AVOID_CUT_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_polynomial_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_prbs11_seed_2_attr == 11'd977
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_prbs11_seed_attr == 11'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_ber_count_snap_lock_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL136_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_ber_counter_clear_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL136_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_clear_one_marker_seen_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL136_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL136_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL136_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL136_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_pam4_modulation_select_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_prbs_ber_en_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL136_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_prbs_seed_force_en_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL136_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_prbs_seed_force_val_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_ber_count_snap_lock_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL72_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_ber_counter_clear_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL72_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_clear_one_marker_seen_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL72_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL72_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL72_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL72_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_prbs_ber_en_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL72_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_prbs_seed_force_en_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL72_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_prbs_seed_force_val_attr == 13'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_gb_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_rx_sync_pulse_attr == SERDES_SHIM_TFL_L0_CFG_RX_SYNC_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_scrambler_force_init_at_each_frame_attr == SERDES_SHIM_TFL_L0_CFG_SCRAMBLER_FORCE_INIT_AT_EACH_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_send_data_attr == SERDES_SHIM_TFL_L0_CFG_SEND_DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_sync_ctrl_stts_word_pulse_attr == SERDES_SHIM_TFL_L0_CFG_SYNC_CTRL_STTS_WORD_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_tfl_prbs13_en_attr == SERDES_SHIM_TFL_L0_CFG_TFL_PRBS13_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_tfl_pulse_sync_attr == SERDES_SHIM_TFL_L0_CFG_TFL_PULSE_SYNC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_tfl_training_enable_rx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_tfl_training_enable_tx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l0_cfg_tx_gb_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_cfg_prbs13_seed_2_attr == 13'd7571
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_cfg_prbs13_seed_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_cfg_tfl_prbs11_en_attr == SERDES_SHIM_TFL_L1_CFG_CFG_TFL_PRBS11_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_cl136_ctrl_field_11_10_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_cl136_ctrl_field_13_12_init_cond_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_cl136_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_cl136_ctrl_field_1_0_coeff_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_cl136_ctrl_field_4_2_coeff_select_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_cl136_ctrl_field_7_5_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_cl136_ctrl_field_9_8_mod_precode_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_cl136_frame_cycle_to_lock_attr == 10'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_cl136_prbs_encoder_select_even_attr == SERDES_SHIM_TFL_L1_CFG_CL136_PRBS_ENCODER_SELECT_EVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_cl136_precoder_out_swz_attr == SERDES_SHIM_TFL_L1_CFG_CL136_PRECODER_OUT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_cl136_precoder_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_cl136_stts_field_11_10_mod_precode_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_cl136_stts_field_14_12_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_cl136_stts_field_15_rx_ready_attr == SERDES_SHIM_TFL_L1_CFG_CL136_STTS_FIELD_15_RX_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_cl136_stts_field_2_0_coeff_stts_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_cl136_stts_field_5_3_coeff_sel_echo_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_cl136_stts_field_6_rsvd_attr == SERDES_SHIM_TFL_L1_CFG_CL136_STTS_FIELD_6_RSVD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_cl136_stts_field_7_parity_attr == SERDES_SHIM_TFL_L1_CFG_CL136_STTS_FIELD_7_PARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_cl136_stts_field_8_init_cond_stts_attr == SERDES_SHIM_TFL_L1_CFG_CL136_STTS_FIELD_8_INIT_COND_STTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_cl136_stts_field_9_rx_frame_lock_attr == SERDES_SHIM_TFL_L1_CFG_CL136_STTS_FIELD_9_RX_FRAME_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_cl72_ctrl_field_11_6_rsvd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_cl72_ctrl_field_12_initialize_attr == SERDES_SHIM_TFL_L1_CFG_CL72_CTRL_FIELD_12_INITIALIZE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_cl72_ctrl_field_13_preset_attr == SERDES_SHIM_TFL_L1_CFG_CL72_CTRL_FIELD_13_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_cl72_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_cl72_ctrl_field_1_0_coef_m1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_cl72_ctrl_field_3_2_coef_0_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_cl72_ctrl_field_5_4_coef_p1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_cl72_frame_cycle_to_lock_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_cl72_stts_field_14_6_rsvd_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_cl72_stts_field_15_rcv_ready_attr == SERDES_SHIM_TFL_L1_CFG_CL72_STTS_FIELD_15_RCV_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_cl72_stts_field_1_0_coef_m1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_cl72_stts_field_3_2_coef_0_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_cl72_stts_field_5_4_coef_p1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_frame_boundary_early_attr == SERDES_SHIM_TFL_L1_CFG_FRAME_BOUNDARY_EARLY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_gb_128_80_en_attr == SERDES_SHIM_TFL_L1_CFG_GB_128_80_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_ignore_tfl_en_to_avoid_cut_frame_attr == SERDES_SHIM_TFL_L1_CFG_IGNORE_TFL_EN_TO_AVOID_CUT_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_polynomial_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_prbs11_seed_2_attr == 11'd977
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_prbs11_seed_attr == 11'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_ber_count_snap_lock_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL136_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_ber_counter_clear_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL136_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_clear_one_marker_seen_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL136_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL136_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL136_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL136_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_pam4_modulation_select_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_prbs_ber_en_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL136_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_prbs_seed_force_en_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL136_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_prbs_seed_force_val_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_ber_count_snap_lock_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL72_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_ber_counter_clear_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL72_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_clear_one_marker_seen_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL72_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL72_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL72_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL72_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_prbs_ber_en_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL72_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_prbs_seed_force_en_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL72_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_prbs_seed_force_val_attr == 13'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_gb_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_rx_sync_pulse_attr == SERDES_SHIM_TFL_L1_CFG_RX_SYNC_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_scrambler_force_init_at_each_frame_attr == SERDES_SHIM_TFL_L1_CFG_SCRAMBLER_FORCE_INIT_AT_EACH_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_send_data_attr == SERDES_SHIM_TFL_L1_CFG_SEND_DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_sync_ctrl_stts_word_pulse_attr == SERDES_SHIM_TFL_L1_CFG_SYNC_CTRL_STTS_WORD_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_tfl_prbs13_en_attr == SERDES_SHIM_TFL_L1_CFG_TFL_PRBS13_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_tfl_pulse_sync_attr == SERDES_SHIM_TFL_L1_CFG_TFL_PULSE_SYNC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_tfl_training_enable_rx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_tfl_training_enable_tx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l1_cfg_tx_gb_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_cfg_prbs13_seed_2_attr == 13'd7571
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_cfg_prbs13_seed_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_cfg_tfl_prbs11_en_attr == SERDES_SHIM_TFL_L2_CFG_CFG_TFL_PRBS11_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_cl136_ctrl_field_11_10_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_cl136_ctrl_field_13_12_init_cond_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_cl136_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_cl136_ctrl_field_1_0_coeff_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_cl136_ctrl_field_4_2_coeff_select_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_cl136_ctrl_field_7_5_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_cl136_ctrl_field_9_8_mod_precode_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_cl136_frame_cycle_to_lock_attr == 10'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_cl136_prbs_encoder_select_even_attr == SERDES_SHIM_TFL_L2_CFG_CL136_PRBS_ENCODER_SELECT_EVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_cl136_precoder_out_swz_attr == SERDES_SHIM_TFL_L2_CFG_CL136_PRECODER_OUT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_cl136_precoder_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_cl136_stts_field_11_10_mod_precode_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_cl136_stts_field_14_12_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_cl136_stts_field_15_rx_ready_attr == SERDES_SHIM_TFL_L2_CFG_CL136_STTS_FIELD_15_RX_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_cl136_stts_field_2_0_coeff_stts_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_cl136_stts_field_5_3_coeff_sel_echo_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_cl136_stts_field_6_rsvd_attr == SERDES_SHIM_TFL_L2_CFG_CL136_STTS_FIELD_6_RSVD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_cl136_stts_field_7_parity_attr == SERDES_SHIM_TFL_L2_CFG_CL136_STTS_FIELD_7_PARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_cl136_stts_field_8_init_cond_stts_attr == SERDES_SHIM_TFL_L2_CFG_CL136_STTS_FIELD_8_INIT_COND_STTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_cl136_stts_field_9_rx_frame_lock_attr == SERDES_SHIM_TFL_L2_CFG_CL136_STTS_FIELD_9_RX_FRAME_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_cl72_ctrl_field_11_6_rsvd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_cl72_ctrl_field_12_initialize_attr == SERDES_SHIM_TFL_L2_CFG_CL72_CTRL_FIELD_12_INITIALIZE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_cl72_ctrl_field_13_preset_attr == SERDES_SHIM_TFL_L2_CFG_CL72_CTRL_FIELD_13_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_cl72_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_cl72_ctrl_field_1_0_coef_m1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_cl72_ctrl_field_3_2_coef_0_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_cl72_ctrl_field_5_4_coef_p1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_cl72_frame_cycle_to_lock_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_cl72_stts_field_14_6_rsvd_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_cl72_stts_field_15_rcv_ready_attr == SERDES_SHIM_TFL_L2_CFG_CL72_STTS_FIELD_15_RCV_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_cl72_stts_field_1_0_coef_m1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_cl72_stts_field_3_2_coef_0_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_cl72_stts_field_5_4_coef_p1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_frame_boundary_early_attr == SERDES_SHIM_TFL_L2_CFG_FRAME_BOUNDARY_EARLY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_gb_128_80_en_attr == SERDES_SHIM_TFL_L2_CFG_GB_128_80_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_ignore_tfl_en_to_avoid_cut_frame_attr == SERDES_SHIM_TFL_L2_CFG_IGNORE_TFL_EN_TO_AVOID_CUT_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_polynomial_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_prbs11_seed_2_attr == 11'd977
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_prbs11_seed_attr == 11'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_ber_count_snap_lock_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL136_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_ber_counter_clear_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL136_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_clear_one_marker_seen_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL136_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL136_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL136_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL136_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_pam4_modulation_select_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_prbs_ber_en_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL136_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_prbs_seed_force_en_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL136_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_prbs_seed_force_val_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_ber_count_snap_lock_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL72_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_ber_counter_clear_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL72_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_clear_one_marker_seen_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL72_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL72_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL72_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL72_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_prbs_ber_en_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL72_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_prbs_seed_force_en_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL72_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_prbs_seed_force_val_attr == 13'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_gb_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_rx_sync_pulse_attr == SERDES_SHIM_TFL_L2_CFG_RX_SYNC_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_scrambler_force_init_at_each_frame_attr == SERDES_SHIM_TFL_L2_CFG_SCRAMBLER_FORCE_INIT_AT_EACH_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_send_data_attr == SERDES_SHIM_TFL_L2_CFG_SEND_DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_sync_ctrl_stts_word_pulse_attr == SERDES_SHIM_TFL_L2_CFG_SYNC_CTRL_STTS_WORD_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_tfl_prbs13_en_attr == SERDES_SHIM_TFL_L2_CFG_TFL_PRBS13_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_tfl_pulse_sync_attr == SERDES_SHIM_TFL_L2_CFG_TFL_PULSE_SYNC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_tfl_training_enable_rx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_tfl_training_enable_tx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l2_cfg_tx_gb_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_cfg_prbs13_seed_2_attr == 13'd7571
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_cfg_prbs13_seed_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_cfg_tfl_prbs11_en_attr == SERDES_SHIM_TFL_L3_CFG_CFG_TFL_PRBS11_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_cl136_ctrl_field_11_10_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_cl136_ctrl_field_13_12_init_cond_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_cl136_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_cl136_ctrl_field_1_0_coeff_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_cl136_ctrl_field_4_2_coeff_select_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_cl136_ctrl_field_7_5_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_cl136_ctrl_field_9_8_mod_precode_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_cl136_frame_cycle_to_lock_attr == 10'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_cl136_prbs_encoder_select_even_attr == SERDES_SHIM_TFL_L3_CFG_CL136_PRBS_ENCODER_SELECT_EVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_cl136_precoder_out_swz_attr == SERDES_SHIM_TFL_L3_CFG_CL136_PRECODER_OUT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_cl136_precoder_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_cl136_stts_field_11_10_mod_precode_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_cl136_stts_field_14_12_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_cl136_stts_field_15_rx_ready_attr == SERDES_SHIM_TFL_L3_CFG_CL136_STTS_FIELD_15_RX_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_cl136_stts_field_2_0_coeff_stts_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_cl136_stts_field_5_3_coeff_sel_echo_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_cl136_stts_field_6_rsvd_attr == SERDES_SHIM_TFL_L3_CFG_CL136_STTS_FIELD_6_RSVD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_cl136_stts_field_7_parity_attr == SERDES_SHIM_TFL_L3_CFG_CL136_STTS_FIELD_7_PARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_cl136_stts_field_8_init_cond_stts_attr == SERDES_SHIM_TFL_L3_CFG_CL136_STTS_FIELD_8_INIT_COND_STTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_cl136_stts_field_9_rx_frame_lock_attr == SERDES_SHIM_TFL_L3_CFG_CL136_STTS_FIELD_9_RX_FRAME_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_cl72_ctrl_field_11_6_rsvd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_cl72_ctrl_field_12_initialize_attr == SERDES_SHIM_TFL_L3_CFG_CL72_CTRL_FIELD_12_INITIALIZE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_cl72_ctrl_field_13_preset_attr == SERDES_SHIM_TFL_L3_CFG_CL72_CTRL_FIELD_13_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_cl72_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_cl72_ctrl_field_1_0_coef_m1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_cl72_ctrl_field_3_2_coef_0_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_cl72_ctrl_field_5_4_coef_p1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_cl72_frame_cycle_to_lock_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_cl72_stts_field_14_6_rsvd_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_cl72_stts_field_15_rcv_ready_attr == SERDES_SHIM_TFL_L3_CFG_CL72_STTS_FIELD_15_RCV_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_cl72_stts_field_1_0_coef_m1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_cl72_stts_field_3_2_coef_0_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_cl72_stts_field_5_4_coef_p1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_frame_boundary_early_attr == SERDES_SHIM_TFL_L3_CFG_FRAME_BOUNDARY_EARLY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_gb_128_80_en_attr == SERDES_SHIM_TFL_L3_CFG_GB_128_80_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_ignore_tfl_en_to_avoid_cut_frame_attr == SERDES_SHIM_TFL_L3_CFG_IGNORE_TFL_EN_TO_AVOID_CUT_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_polynomial_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_prbs11_seed_2_attr == 11'd977
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_prbs11_seed_attr == 11'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_ber_count_snap_lock_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL136_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_ber_counter_clear_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL136_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_clear_one_marker_seen_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL136_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL136_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL136_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL136_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_pam4_modulation_select_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_prbs_ber_en_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL136_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_prbs_seed_force_en_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL136_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_prbs_seed_force_val_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_ber_count_snap_lock_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL72_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_ber_counter_clear_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL72_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_clear_one_marker_seen_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL72_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL72_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL72_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL72_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_prbs_ber_en_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL72_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_prbs_seed_force_en_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL72_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_prbs_seed_force_val_attr == 13'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_gb_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_rx_sync_pulse_attr == SERDES_SHIM_TFL_L3_CFG_RX_SYNC_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_scrambler_force_init_at_each_frame_attr == SERDES_SHIM_TFL_L3_CFG_SCRAMBLER_FORCE_INIT_AT_EACH_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_send_data_attr == SERDES_SHIM_TFL_L3_CFG_SEND_DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_sync_ctrl_stts_word_pulse_attr == SERDES_SHIM_TFL_L3_CFG_SYNC_CTRL_STTS_WORD_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_tfl_prbs13_en_attr == SERDES_SHIM_TFL_L3_CFG_TFL_PRBS13_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_tfl_pulse_sync_attr == SERDES_SHIM_TFL_L3_CFG_TFL_PULSE_SYNC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_tfl_training_enable_rx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_tfl_training_enable_tx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_tfl_l3_cfg_tx_gb_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_top_cfg_broadcast_feature_en_attr == SERDES_SHIM_TOP_CFG_BROADCAST_FEATURE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_top_cfg_broadcast_type_attr == SERDES_SHIM_TOP_CFG_BROADCAST_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_top_cfg_fabric_wd_counter_max_attr == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_top_cfg_fec_ber_datawidth_sel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_top_cfg_fec_ber_en_attr == SERDES_SHIM_TOP_CFG_FEC_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_top_cfg_fec_ber_mask8_attr == 8'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_top_cfg_fec_ber_packet_sel_attr == SERDES_SHIM_TOP_CFG_FEC_BER_PACKET_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_top_cfg_fec_ber_poly_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_top_cfg_fec_ber_rs_type_sel_attr == SERDES_SHIM_TOP_CFG_FEC_BER_RS_TYPE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_top_cfg_fec_ber_statistic_en_attr == SERDES_SHIM_TOP_CFG_FEC_BER_STATISTIC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_top_cfg_serdes_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_top_cfg_serdes_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_top_cfg_serdes_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_top_cfg_wdt_clr_attr == SERDES_SHIM_TOP_CFG_WDT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_top_cfg_wdt_en_attr == SERDES_SHIM_TOP_CFG_WDT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_top_cfg_wdt_pre_scale_attr == 32'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_top_cfg_wdt_rst_after_irq_mode_attr == SERDES_SHIM_TOP_CFG_WDT_RST_AFTER_IRQ_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_top_cfg_wdt_swrst_en_attr == SERDES_SHIM_TOP_CFG_WDT_SWRST_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_top_cfg_wdt_time_val_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_apb_cfg_presetn_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_CFG_PRESETN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_apb_lgc_rstn_serdes_ux_lane0_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_LGC_RSTN_SERDES_UX_LANE0_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_apb_lgc_rstn_serdes_ux_lane1_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_LGC_RSTN_SERDES_UX_LANE1_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_apb_lgc_rstn_serdes_ux_lane2_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_LGC_RSTN_SERDES_UX_LANE2_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_apb_lgc_rstn_serdes_ux_lane3_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_LGC_RSTN_SERDES_UX_LANE3_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_apb_mem_rstn_serdes_ux_lane0_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_MEM_RSTN_SERDES_UX_LANE0_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_apb_mem_rstn_serdes_ux_lane1_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_MEM_RSTN_SERDES_UX_LANE1_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_apb_mem_rstn_serdes_ux_lane2_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_MEM_RSTN_SERDES_UX_LANE2_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_apb_mem_rstn_serdes_ux_lane3_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_MEM_RSTN_SERDES_UX_LANE3_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_clkrx_bot_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_CLKRX_BOT_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_clkrx_top_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_CLKRX_TOP_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_lane0_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_LANE0_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_lane1_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_LANE1_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_lane2_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_LANE2_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_lane3_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_LANE3_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_scmng_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_SCMNG_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_srds_ctrl_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_SRDS_CTRL_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_srds_ux_lane0_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_SRDS_UX_LANE0_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_srds_ux_lane1_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_SRDS_UX_LANE1_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_srds_ux_lane2_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_SRDS_UX_LANE2_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_srds_ux_lane3_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_SRDS_UX_LANE3_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_clkrx_bot_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_CLKRX_BOT_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_clkrx_top_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_CLKRX_TOP_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_lane0_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_LANE0_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_lane1_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_LANE1_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_lane2_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_LANE2_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_lane3_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_LANE3_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_scmng_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_SCMNG_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_srds_ctrl_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_SRDS_CTRL_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_srds_ux_lane0_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_SRDS_UX_LANE0_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_srds_ux_lane1_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_SRDS_UX_LANE1_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_srds_ux_lane2_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_SRDS_UX_LANE2_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_srds_ux_lane3_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_SRDS_UX_LANE3_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_car_ux_lane_rst_src_sel_lane0_attr == SERDES_SHIM_WRAP_CAR_CFG_CAR_UX_LANE_RST_SRC_SEL_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_car_ux_lane_rst_src_sel_lane1_attr == SERDES_SHIM_WRAP_CAR_CFG_CAR_UX_LANE_RST_SRC_SEL_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_car_ux_lane_rst_src_sel_lane2_attr == SERDES_SHIM_WRAP_CAR_CFG_CAR_UX_LANE_RST_SRC_SEL_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_car_ux_lane_rst_src_sel_lane3_attr == SERDES_SHIM_WRAP_CAR_CFG_CAR_UX_LANE_RST_SRC_SEL_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_clkrx_ref_clk_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_cpu_apb_clocks_ratio_attr == SERDES_SHIM_WRAP_CAR_CFG_CPU_APB_CLOCKS_RATIO_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_cpu_clk_sel_attr == SERDES_SHIM_WRAP_CAR_CFG_CPU_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_cpu_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_CPU_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_cpu_runstall_attr == SERDES_SHIM_WRAP_CAR_CFG_CPU_RUNSTALL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_cpu_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_CPU_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_fast_clk_divn_en_attr == SERDES_SHIM_WRAP_CAR_CFG_FAST_CLK_DIVN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_fast_clk_divn_val_attr == 8'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_fast_clk_lane_sel_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_fb_cpu_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_FB_CPU_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_fb_cpu_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_FB_CPU_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_fb_rx_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_FB_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_fb_rx_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_FB_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_fec_ber_lane_select_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_hwrstn_clkrx_bot_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_CLKRX_BOT_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_hwrstn_clkrx_top_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_CLKRX_TOP_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_hwrstn_lane0_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_LANE0_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_hwrstn_lane1_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_LANE1_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_hwrstn_lane2_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_LANE2_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_hwrstn_lane3_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_LANE3_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_hwrstn_scmng_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_SCMNG_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_hwrstn_serdes_ctrl_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_SERDES_CTRL_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_hwrstn_serdes_ux_lane0_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_SERDES_UX_LANE0_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_hwrstn_serdes_ux_lane1_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_SERDES_UX_LANE1_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_hwrstn_serdes_ux_lane2_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_SERDES_UX_LANE2_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_hwrstn_serdes_ux_lane3_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_SERDES_UX_LANE3_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_lane_car_apb_cfg_presetn_swrstn_lane0_attr == SERDES_SHIM_WRAP_CAR_CFG_LANE_CAR_APB_CFG_PRESETN_SWRSTN_LANE0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_lane_car_apb_cfg_presetn_swrstn_lane1_attr == SERDES_SHIM_WRAP_CAR_CFG_LANE_CAR_APB_CFG_PRESETN_SWRSTN_LANE1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_lane_car_apb_cfg_presetn_swrstn_lane2_attr == SERDES_SHIM_WRAP_CAR_CFG_LANE_CAR_APB_CFG_PRESETN_SWRSTN_LANE2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_lane_car_apb_cfg_presetn_swrstn_lane3_attr == SERDES_SHIM_WRAP_CAR_CFG_LANE_CAR_APB_CFG_PRESETN_SWRSTN_LANE3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.serdes_shim_wrap_car_cfg_wrap_car_apb_cfg_presetn_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_WRAP_CAR_APB_CFG_PRESETN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.top_f_fastest_reconfig_refclk_hz == 40'd800000001
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.top_refclk_reconfig_span == TOP_REFCLK_RECONFIG_SPAN_TWO_RIGHT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.top_syspll_refclk_output_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_0_rx_synth_select == UX0_0_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_0_tx_synth_select == UX0_0_TX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_1_rx_synth_select == UX0_1_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_1_tx_synth_select == UX0_1_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_2_rx_synth_select == UX0_2_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_2_tx_synth_select == UX0_2_TX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_3_rx_synth_select == UX0_3_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_3_tx_synth_select == UX0_3_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_4_rx_synth_select == UX0_4_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_4_tx_synth_select == UX0_4_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_0_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_0_hscount == 8'd181
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_0_m_counter_physical == 9'd194
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_0_meascount == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_0_mod_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_0_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_0_postdiv_counter_physical == 7'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_0_postdiv_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_0_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_0_refclk_type_select == UX0_CDR_0_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_0_watchdogtmr == 16'd1188
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_1_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_1_hscount == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_1_m_counter_physical == 9'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_1_meascount == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_1_mod_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_1_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_1_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_1_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_1_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_1_refclk_type_select == UX0_CDR_1_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_1_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_2_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_2_hscount == 8'd180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_2_m_counter_physical == 9'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_2_meascount == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_2_mod_counter == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_2_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_2_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_2_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_2_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_2_refclk_type_select == UX0_CDR_2_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_2_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_3_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_3_hscount == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_3_m_counter_physical == 9'd66
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_3_meascount == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_3_mod_counter == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_3_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_3_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_3_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_3_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_3_refclk_type_select == UX0_CDR_3_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_3_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_4_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_4_hscount == 8'd206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_4_m_counter_physical == 9'd210
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_4_meascount == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_4_mod_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_4_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_4_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_4_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_4_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_4_refclk_type_select == UX0_CDR_4_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_4_watchdogtmr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_bw_sel == UX0_CDR_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_f_mod_hz == 40'd990000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_f_out_hz == 40'd5940000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_f_pfd_hz == 40'd29700000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_f_postdiv_hz == 40'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_f_ref_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_f_vco_hz == 40'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_hscount_scratch == 40'd181
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_is_cascaded == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_is_fractional == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_l_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_l_counter_physical == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_m_counter == 9'd200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_meascount_scratch == 40'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_mod_counter_scratch == 40'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_postdiv_counter == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_ppm_driftcount == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_ppm_driftmax == 16'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_ppm_driftmax_scratch == 47'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_ppm_driftmax_scratch_denominator == 47'd1015257760000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_ppm_driftmax_scratch_numerator == 47'd31129600000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_ppm_tolerance == 16'd7600
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_refclk_mux_select == UX0_CDR_REFCLK_MUX_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_refclk_select == UX0_CDR_REFCLK_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_squelch_sample_count == 10'd144
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_squelch_sample_scratch == 40'd144
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cdr_watchdogtmr_scratch == 40'd1188
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cmn_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cmn_rx_cdr_refclk_mux_select == UX0_CMN_RX_CDR_REFCLK_MUX_SELECT_GLOBAL_REFCLK_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cmnrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cmnrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cmnrpu_evdn_delay_lut_entry3 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cmnrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cmnrpu_evup_delay_lut_entry2 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cmnrpu_evup_delay_lut_entry3 == 50'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cmnrpu_evup_delay_lut_entry4 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cmnrpu_evup_delay_lut_entry5 == 50'd62
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cmnrpu_evup_delay_lut_entry6 == 50'd390
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_cmnrpu_evup_delay_lut_entry7 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_core_pll == UX0_CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_core_pll_bw_sel == UX0_CORE_PLL_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_core_pll_refclk_select == UX0_CORE_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_dpma_f_out_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_dpma_n_counter == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_dpma_n_counter_physical == UX0_DPMA_N_COUNTER_PHYSICAL_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_dpma_n_counter_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_dpma_refclk_source == UX0_DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_dts_ssdiv_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_duplex_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_enable_med_lc_0_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_enable_med_lc_1_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_enable_med_lc_2_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_enable_med_lc_3_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_enable_med_lc_4_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_enable_port_control_of_cdr_ltr_ltd == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_enable_slow_lc_0_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_enable_slow_lc_1_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_enable_slow_lc_2_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_enable_slow_lc_3_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_enable_slow_lc_4_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_ethernet_source == UX0_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_expose_pcie_gen1_gen6_critical_signals == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_f_cascade_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_feed_forward_gain_scratch == 47'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_feed_forward_temp_one == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_feed_forward_temp_two == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_flux_mode == UX0_FLUX_MODE_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_kvcc_settle_maxcnt_scratch == 40'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_lane_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_loopback_mode == UX0_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_master_sup_mode == UX0_MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_oversampling_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_prbs_gen_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_primary_use == UX0_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_ref_clk_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_refclk_in_1us_scratch == 40'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rx_adapt_mode == UX0_RX_ADAPT_MODE_UX_RX_ADAPT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rx_bond_size == UX0_RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rx_cal_dutymeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rx_datarate == 40'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rx_line_rate_bps == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rx_master_bond_chnl == UX0_RX_MASTER_BOND_CHNL_CH15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rx_o_clk_e2_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rx_o_clk_e4_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rx_o_usr_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rx_o_usr_clk_e4_hz == 36'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rx_onchip_termination == UX0_RX_ONCHIP_TERMINATION_R_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rx_over_sample == UX0_RX_OVER_SAMPLE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rx_protocol == UX0_RX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rx_term_mode_select == UX0_RX_TERM_MODE_SELECT_DIFFERENTIAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rx_tuning_hint == UX0_RX_TUNING_HINT_SDI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rx_user_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rx_which_lane_to_copy == UX0_RX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rx_width == UX0_RX_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxeq_ctle_bias_adj == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxeq_ctle_biasboost == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxeq_ctle_lf_gain == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxeq_ctle_midband_zero == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxeq_ctle_stage_1_dcgain == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxeq_ctle_stage_1_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxeq_ctle_stage_2_cap == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxeq_ctle_stage_2_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxeq_ctle_stage_2_reszero == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxeq_ctle_stage_3_dcgain == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxeq_ctle_stage_3_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxeq_dfe_data_tap_10 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxeq_dfe_data_tap_11 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxeq_dfe_data_tap_12 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxeq_dfe_data_tap_13 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxeq_dfe_data_tap_14 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxeq_dfe_data_tap_15 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxeq_dfe_data_tap_16 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxeq_dfe_data_tap_2 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxeq_dfe_data_tap_3 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxeq_dfe_data_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxeq_dfe_data_tap_5 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxeq_dfe_data_tap_6 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxeq_dfe_data_tap_7 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxeq_dfe_data_tap_8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxeq_dfe_data_tap_9 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxeq_dfe_edge_tap_2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxeq_dfe_edge_tap_3 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxeq_dfe_edge_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxeq_iq_clk == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxeq_targ_0_hi == 9'd160
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxeq_targ_0_lo == 9'd140
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxeq_vga_gain == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxratewidth_pd_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxrpu_evup_delay_lut_entry4 == 50'd78
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxrpu_evup_delay_lut_entry5 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxrpu_evup_delay_lut_entry6 == 50'd1406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_rxrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_select_lc_0_tx_path == UX0_SELECT_LC_0_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_select_lc_1_tx_path == UX0_SELECT_LC_1_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_select_lc_2_tx_path == UX0_SELECT_LC_2_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_select_lc_3_tx_path == UX0_SELECT_LC_3_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_select_lc_4_tx_path == UX0_SELECT_LC_4_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_sup_mode == UX0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_afc_range == UX0_SYNTH_LC_0_AFC_RANGE_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_afc_refclk_count == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_dtr_prop_coeff == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_f_max_vco_hz == 40'd10500000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_f_min_vco_hz == 40'd8000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_fast_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_fast_tx_postdiv_counter == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_feed_forward_gain == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_fine_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_fine_int_coeff_tmp == 4'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_fine_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_fine_prop_coeff_tmp == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_kvcc_settle_maxcnt == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_m_counter == 9'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_med_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_med_tx_postdiv_counter == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_refclk_in_1us == 8'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_slow_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_slow_tx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_tdc_fine_res_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_tdc_target_count == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_0_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_afc_range == UX0_SYNTH_LC_1_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_feed_forward_gain == 8'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_m_counter == 9'd90
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_1_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_afc_range == UX0_SYNTH_LC_2_AFC_RANGE_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_dtr_int_coeff == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_feed_forward_gain == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_m_counter == 9'd54
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_2_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_afc_range == UX0_SYNTH_LC_3_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_feed_forward_gain == 8'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_m_counter == 9'd72
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_3_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_afc_range == UX0_SYNTH_LC_4_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_afc_refclk_count == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_dtr_int_coeff == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_feed_forward_gain == 8'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_fine_int_coeff == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_kvcc_settle_maxcnt == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_m_counter == 9'd432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_med_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_refclk_in_1us == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_tdc_refclk_count == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_tdc_target_count == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_4_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_fast_bw_sel == UX0_SYNTH_LC_FAST_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_fast_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_fast_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_fast_primary_use == UX0_SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_fast_refclk_mux_select == UX0_SYNTH_LC_FAST_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_fast_refclk_type_select == UX0_SYNTH_LC_FAST_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_fast_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_fb_div_emb_mult_counter == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_fb_div_n_frac_mode == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_l_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_l_counter_physical == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_med_bw_sel == UX0_SYNTH_LC_MED_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_med_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_med_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_med_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_med_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_med_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_med_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_med_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_med_primary_use == UX0_SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_med_refclk_mux_select == UX0_SYNTH_LC_MED_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_med_refclk_type_select == UX0_SYNTH_LC_MED_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_med_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_slow_bw_sel == UX0_SYNTH_LC_SLOW_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_slow_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_slow_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_slow_primary_use == UX0_SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_slow_refclk_mux_select == UX0_SYNTH_LC_SLOW_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_slow_refclk_type_select == UX0_SYNTH_LC_SLOW_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synth_lc_slow_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlc_0_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlc_0_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlc_0_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlc_0_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlc_1_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlc_1_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlc_1_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlc_1_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlc_2_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlc_2_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlc_2_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlc_2_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlc_3_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlc_3_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlc_3_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlc_3_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlc_4_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlc_4_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlc_4_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlc_4_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlc_dcdmeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlcfastratewidth_pd_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlcfastrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlcfastrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlcfastrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlcfastrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlcfastrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlcfastrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlcfastrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlcfastrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlcfastrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlcfastrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlcfastrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlcmedrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlcmedrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlcmedrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlcmedrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlcmedrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlcmedrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlcmedrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlcmedrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlcmedrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlcmedrpu_evup_delay_lut_entry7 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlcslowrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlcslowrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlcslowrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlcslowrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlcslowrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlcslowrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlcslowrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlcslowrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlcslowrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_synthlcslowrpu_evup_delay_lut_entry7 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tdc_refclk_count_divisor == 40'd850000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tdc_refclk_count_scratch == 40'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tdc_target_count_scratch == 40'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tx_bond_size == UX0_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tx_cal_dutymeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tx_i_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tx_i_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tx_i_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tx_master_bond_chnl == UX0_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tx_o_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tx_o_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tx_o_usr_clk_1_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tx_o_usr_clk_1_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tx_o_usr_clk_2_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tx_over_sample == UX0_TX_OVER_SAMPLE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tx_pll == UX0_TX_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tx_pll_bw_sel == UX0_TX_PLL_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tx_pll_is_downstream_pll == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tx_pll_refclk_mux_select == UX0_TX_PLL_REFCLK_MUX_SELECT_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tx_pll_refclk_select == UX0_TX_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tx_protocol == UX0_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tx_protocol_hard_pcie_lowloss == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tx_tuning_hint == UX0_TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tx_user_clk1_mux == UX0_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tx_user_clk2_mux == UX0_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tx_user_clk_slow_med_mux == UX0_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tx_which_lane_to_copy == UX0_TX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_tx_width == UX0_TX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_txeq_main_tap == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_txratewidth_rst_b0_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_txrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_txrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_txrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_txrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_txrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_txrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_txrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_txrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_txrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_txrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_txrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_txrx_channel_operation == UX0_TXRX_CHANNEL_OPERATION_DUAL_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_txrx_line_encoding_type == UX0_TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_txrx_xcvr_speed_bucket == UX0_TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux0_vreg_loopen_maxcnt_scratch == 40'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_0_rx_synth_select == UX1_0_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_0_tx_synth_select == UX1_0_TX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_1_rx_synth_select == UX1_1_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_1_tx_synth_select == UX1_1_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_2_rx_synth_select == UX1_2_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_2_tx_synth_select == UX1_2_TX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_3_rx_synth_select == UX1_3_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_3_tx_synth_select == UX1_3_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_4_rx_synth_select == UX1_4_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_4_tx_synth_select == UX1_4_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_0_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_0_hscount == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_0_m_counter_physical == 9'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_0_meascount == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_0_mod_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_0_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_0_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_0_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_0_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_0_refclk_type_select == UX1_CDR_0_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_0_watchdogtmr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_1_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_1_hscount == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_1_m_counter_physical == 9'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_1_meascount == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_1_mod_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_1_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_1_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_1_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_1_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_1_refclk_type_select == UX1_CDR_1_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_1_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_2_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_2_hscount == 8'd180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_2_m_counter_physical == 9'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_2_meascount == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_2_mod_counter == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_2_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_2_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_2_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_2_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_2_refclk_type_select == UX1_CDR_2_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_2_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_3_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_3_hscount == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_3_m_counter_physical == 9'd66
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_3_meascount == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_3_mod_counter == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_3_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_3_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_3_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_3_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_3_refclk_type_select == UX1_CDR_3_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_3_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_4_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_4_hscount == 8'd206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_4_m_counter_physical == 9'd210
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_4_meascount == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_4_mod_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_4_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_4_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_4_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_4_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_4_refclk_type_select == UX1_CDR_4_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_4_watchdogtmr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_bw_sel == UX1_CDR_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_f_mod_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_f_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_hscount_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_is_cascaded == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_is_fractional == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_l_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_l_counter_physical == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_m_counter == 9'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_meascount_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_mod_counter_scratch == 40'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_ppm_driftcount == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_ppm_driftmax == 16'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_ppm_driftmax_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_ppm_driftmax_scratch_denominator == 47'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_ppm_driftmax_scratch_numerator == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_ppm_tolerance == 16'd7600
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_refclk_mux_select == UX1_CDR_REFCLK_MUX_SELECT_REGIONAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_refclk_select == UX1_CDR_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_squelch_sample_count == 10'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_squelch_sample_scratch == 40'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cdr_watchdogtmr_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cmn_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cmn_rx_cdr_refclk_mux_select == UX1_CMN_RX_CDR_REFCLK_MUX_SELECT_REGIONAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cmnrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cmnrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cmnrpu_evdn_delay_lut_entry3 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cmnrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cmnrpu_evup_delay_lut_entry2 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cmnrpu_evup_delay_lut_entry3 == 50'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cmnrpu_evup_delay_lut_entry4 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cmnrpu_evup_delay_lut_entry5 == 50'd62
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cmnrpu_evup_delay_lut_entry6 == 50'd390
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_cmnrpu_evup_delay_lut_entry7 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_core_pll == UX1_CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_core_pll_bw_sel == UX1_CORE_PLL_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_core_pll_refclk_select == UX1_CORE_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_dpma_f_out_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_dpma_n_counter == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_dpma_n_counter_physical == UX1_DPMA_N_COUNTER_PHYSICAL_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_dpma_n_counter_scratch == 40'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_dpma_refclk_source == UX1_DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_dts_ssdiv_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_duplex_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_enable_med_lc_0_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_enable_med_lc_1_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_enable_med_lc_2_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_enable_med_lc_3_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_enable_med_lc_4_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_enable_port_control_of_cdr_ltr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_enable_slow_lc_0_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_enable_slow_lc_1_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_enable_slow_lc_2_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_enable_slow_lc_3_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_enable_slow_lc_4_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_ethernet_source == UX1_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_expose_pcie_gen1_gen6_critical_signals == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_f_cascade_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_feed_forward_gain_scratch == 47'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_feed_forward_temp_one == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_feed_forward_temp_two == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_flux_mode == UX1_FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_kvcc_settle_maxcnt_scratch == 40'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_lane_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_loopback_mode == UX1_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_master_sup_mode == UX1_MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_oversampling_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_primary_use == UX1_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_ref_clk_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_refclk_in_1us_scratch == 40'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rx_adapt_mode == UX1_RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rx_bond_size == UX1_RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rx_cal_dutymeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rx_master_bond_chnl == UX1_RX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rx_o_usr_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rx_o_usr_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rx_onchip_termination == UX1_RX_ONCHIP_TERMINATION_R_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rx_over_sample == UX1_RX_OVER_SAMPLE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rx_protocol == UX1_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rx_term_mode_select == UX1_RX_TERM_MODE_SELECT_GROUNDED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rx_tuning_hint == UX1_RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rx_which_lane_to_copy == UX1_RX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rx_width == UX1_RX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxeq_ctle_bias_adj == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxeq_ctle_biasboost == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxeq_ctle_lf_gain == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxeq_ctle_midband_zero == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxeq_ctle_stage_1_dcgain == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxeq_ctle_stage_1_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxeq_ctle_stage_2_cap == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxeq_ctle_stage_2_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxeq_ctle_stage_2_reszero == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxeq_ctle_stage_3_dcgain == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxeq_ctle_stage_3_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxeq_dfe_data_tap_10 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxeq_dfe_data_tap_11 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxeq_dfe_data_tap_12 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxeq_dfe_data_tap_13 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxeq_dfe_data_tap_14 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxeq_dfe_data_tap_15 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxeq_dfe_data_tap_16 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxeq_dfe_data_tap_2 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxeq_dfe_data_tap_3 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxeq_dfe_data_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxeq_dfe_data_tap_5 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxeq_dfe_data_tap_6 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxeq_dfe_data_tap_7 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxeq_dfe_data_tap_8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxeq_dfe_data_tap_9 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxeq_dfe_edge_tap_2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxeq_dfe_edge_tap_3 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxeq_dfe_edge_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxeq_iq_clk == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxeq_targ_0_hi == 9'd149
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxeq_targ_0_lo == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxeq_vga_gain == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxratewidth_pd_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxrpu_evup_delay_lut_entry2 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxrpu_evup_delay_lut_entry4 == 50'd78
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxrpu_evup_delay_lut_entry5 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxrpu_evup_delay_lut_entry6 == 50'd1406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_rxrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_select_lc_0_tx_path == UX1_SELECT_LC_0_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_select_lc_1_tx_path == UX1_SELECT_LC_1_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_select_lc_2_tx_path == UX1_SELECT_LC_2_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_select_lc_3_tx_path == UX1_SELECT_LC_3_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_select_lc_4_tx_path == UX1_SELECT_LC_4_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_sup_mode == UX1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_afc_range == UX1_SYNTH_LC_0_AFC_RANGE_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_afc_refclk_count == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_dtr_prop_coeff == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_f_max_vco_hz == 40'd10500000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_f_min_vco_hz == 40'd8000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_fast_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_fast_tx_postdiv_counter == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_feed_forward_gain == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_fine_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_fine_int_coeff_tmp == 4'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_fine_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_fine_prop_coeff_tmp == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_kvcc_settle_maxcnt == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_m_counter == 9'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_med_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_med_tx_postdiv_counter == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_refclk_in_1us == 8'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_slow_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_slow_tx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_tdc_fine_res_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_tdc_target_count == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_0_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_afc_range == UX1_SYNTH_LC_1_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_feed_forward_gain == 8'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_m_counter == 9'd45
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_1_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_afc_range == UX1_SYNTH_LC_2_AFC_RANGE_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_dtr_int_coeff == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_feed_forward_gain == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_m_counter == 9'd27
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_2_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_afc_range == UX1_SYNTH_LC_3_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_feed_forward_gain == 8'd23
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_m_counter == 9'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_3_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_afc_range == UX1_SYNTH_LC_4_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_afc_refclk_count == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_dtr_int_coeff == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_feed_forward_gain == 8'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_fine_int_coeff == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_kvcc_settle_maxcnt == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_m_counter == 9'd216
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_med_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_refclk_in_1us == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_tdc_refclk_count == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_tdc_target_count == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_4_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_fast_bw_sel == UX1_SYNTH_LC_FAST_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_fast_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_fast_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_fast_primary_use == UX1_SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_fast_refclk_mux_select == UX1_SYNTH_LC_FAST_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_fast_refclk_type_select == UX1_SYNTH_LC_FAST_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_fast_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_fb_div_emb_mult_counter == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_l_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_l_counter_physical == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_med_bw_sel == UX1_SYNTH_LC_MED_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_med_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_med_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_med_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_med_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_med_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_med_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_med_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_med_primary_use == UX1_SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_med_refclk_mux_select == UX1_SYNTH_LC_MED_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_med_refclk_type_select == UX1_SYNTH_LC_MED_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_med_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_slow_bw_sel == UX1_SYNTH_LC_SLOW_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_slow_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_slow_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_slow_primary_use == UX1_SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_slow_refclk_mux_select == UX1_SYNTH_LC_SLOW_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_slow_refclk_type_select == UX1_SYNTH_LC_SLOW_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synth_lc_slow_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlc_0_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlc_0_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlc_0_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlc_0_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlc_1_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlc_1_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlc_1_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlc_1_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlc_2_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlc_2_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlc_2_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlc_2_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlc_3_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlc_3_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlc_3_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlc_3_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlc_4_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlc_4_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlc_4_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlc_4_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlc_dcdmeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlcfastratewidth_pd_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlcfastrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlcfastrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlcfastrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlcfastrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlcfastrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlcfastrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlcfastrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlcfastrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlcfastrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlcfastrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlcfastrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlcmedrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlcmedrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlcmedrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlcmedrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlcmedrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlcmedrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlcmedrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlcmedrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlcmedrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlcmedrpu_evup_delay_lut_entry7 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlcslowrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlcslowrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlcslowrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlcslowrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlcslowrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlcslowrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlcslowrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlcslowrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlcslowrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_synthlcslowrpu_evup_delay_lut_entry7 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tdc_refclk_count_divisor == 40'd850000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tdc_refclk_count_scratch == 40'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tdc_target_count_scratch == 40'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tx_bond_size == UX1_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tx_cal_dutymeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tx_i_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tx_i_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tx_i_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tx_master_bond_chnl == UX1_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tx_o_usr_clk_1_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tx_o_usr_clk_1_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tx_o_usr_clk_2_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tx_over_sample == UX1_TX_OVER_SAMPLE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tx_pll == UX1_TX_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tx_pll_bw_sel == UX1_TX_PLL_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tx_pll_is_downstream_pll == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tx_pll_refclk_mux_select == UX1_TX_PLL_REFCLK_MUX_SELECT_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tx_pll_refclk_select == UX1_TX_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tx_protocol == UX1_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tx_tuning_hint == UX1_TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tx_user_clk1_mux == UX1_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tx_user_clk2_mux == UX1_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tx_user_clk_slow_med_mux == UX1_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tx_which_lane_to_copy == UX1_TX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_tx_width == UX1_TX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_txeq_main_tap == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_txratewidth_rst_b0_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_txrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_txrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_txrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_txrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_txrpu_evup_delay_lut_entry2 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_txrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_txrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_txrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_txrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_txrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_txrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_txrx_channel_operation == UX1_TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_txrx_line_encoding_type == UX1_TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_txrx_xcvr_speed_bucket == UX1_TXRX_XCVR_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux1_vreg_loopen_maxcnt_scratch == 40'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_0_rx_synth_select == UX2_0_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_0_tx_synth_select == UX2_0_TX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_1_rx_synth_select == UX2_1_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_1_tx_synth_select == UX2_1_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_2_rx_synth_select == UX2_2_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_2_tx_synth_select == UX2_2_TX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_3_rx_synth_select == UX2_3_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_3_tx_synth_select == UX2_3_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_4_rx_synth_select == UX2_4_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_4_tx_synth_select == UX2_4_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_0_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_0_hscount == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_0_m_counter_physical == 9'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_0_meascount == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_0_mod_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_0_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_0_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_0_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_0_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_0_refclk_type_select == UX2_CDR_0_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_0_watchdogtmr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_1_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_1_hscount == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_1_m_counter_physical == 9'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_1_meascount == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_1_mod_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_1_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_1_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_1_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_1_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_1_refclk_type_select == UX2_CDR_1_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_1_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_2_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_2_hscount == 8'd180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_2_m_counter_physical == 9'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_2_meascount == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_2_mod_counter == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_2_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_2_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_2_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_2_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_2_refclk_type_select == UX2_CDR_2_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_2_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_3_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_3_hscount == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_3_m_counter_physical == 9'd66
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_3_meascount == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_3_mod_counter == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_3_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_3_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_3_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_3_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_3_refclk_type_select == UX2_CDR_3_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_3_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_4_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_4_hscount == 8'd206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_4_m_counter_physical == 9'd210
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_4_meascount == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_4_mod_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_4_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_4_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_4_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_4_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_4_refclk_type_select == UX2_CDR_4_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_4_watchdogtmr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_bw_sel == UX2_CDR_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_f_mod_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_f_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_hscount_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_is_cascaded == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_is_fractional == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_l_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_l_counter_physical == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_m_counter == 9'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_meascount_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_mod_counter_scratch == 40'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_ppm_driftcount == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_ppm_driftmax == 16'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_ppm_driftmax_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_ppm_driftmax_scratch_denominator == 47'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_ppm_driftmax_scratch_numerator == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_ppm_tolerance == 16'd7600
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_refclk_mux_select == UX2_CDR_REFCLK_MUX_SELECT_REGIONAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_refclk_select == UX2_CDR_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_squelch_sample_count == 10'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_squelch_sample_scratch == 40'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cdr_watchdogtmr_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cmn_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cmn_rx_cdr_refclk_mux_select == UX2_CMN_RX_CDR_REFCLK_MUX_SELECT_REGIONAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cmnrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cmnrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cmnrpu_evdn_delay_lut_entry3 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cmnrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cmnrpu_evup_delay_lut_entry2 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cmnrpu_evup_delay_lut_entry3 == 50'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cmnrpu_evup_delay_lut_entry4 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cmnrpu_evup_delay_lut_entry5 == 50'd62
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cmnrpu_evup_delay_lut_entry6 == 50'd390
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_cmnrpu_evup_delay_lut_entry7 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_core_pll == UX2_CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_core_pll_bw_sel == UX2_CORE_PLL_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_core_pll_refclk_select == UX2_CORE_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_dpma_f_out_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_dpma_n_counter == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_dpma_n_counter_physical == UX2_DPMA_N_COUNTER_PHYSICAL_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_dpma_n_counter_scratch == 40'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_dpma_refclk_source == UX2_DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_dts_ssdiv_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_duplex_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_enable_med_lc_0_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_enable_med_lc_1_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_enable_med_lc_2_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_enable_med_lc_3_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_enable_med_lc_4_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_enable_port_control_of_cdr_ltr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_enable_slow_lc_0_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_enable_slow_lc_1_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_enable_slow_lc_2_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_enable_slow_lc_3_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_enable_slow_lc_4_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_ethernet_source == UX2_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_expose_pcie_gen1_gen6_critical_signals == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_f_cascade_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_feed_forward_gain_scratch == 47'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_feed_forward_temp_one == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_feed_forward_temp_two == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_flux_mode == UX2_FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_kvcc_settle_maxcnt_scratch == 40'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_lane_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_loopback_mode == UX2_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_master_sup_mode == UX2_MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_oversampling_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_primary_use == UX2_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_ref_clk_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_refclk_in_1us_scratch == 40'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rx_adapt_mode == UX2_RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rx_bond_size == UX2_RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rx_cal_dutymeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rx_master_bond_chnl == UX2_RX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rx_o_usr_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rx_o_usr_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rx_onchip_termination == UX2_RX_ONCHIP_TERMINATION_R_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rx_over_sample == UX2_RX_OVER_SAMPLE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rx_protocol == UX2_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rx_term_mode_select == UX2_RX_TERM_MODE_SELECT_GROUNDED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rx_tuning_hint == UX2_RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rx_which_lane_to_copy == UX2_RX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rx_width == UX2_RX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxeq_ctle_bias_adj == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxeq_ctle_biasboost == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxeq_ctle_lf_gain == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxeq_ctle_midband_zero == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxeq_ctle_stage_1_dcgain == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxeq_ctle_stage_1_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxeq_ctle_stage_2_cap == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxeq_ctle_stage_2_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxeq_ctle_stage_2_reszero == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxeq_ctle_stage_3_dcgain == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxeq_ctle_stage_3_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxeq_dfe_data_tap_10 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxeq_dfe_data_tap_11 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxeq_dfe_data_tap_12 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxeq_dfe_data_tap_13 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxeq_dfe_data_tap_14 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxeq_dfe_data_tap_15 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxeq_dfe_data_tap_16 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxeq_dfe_data_tap_2 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxeq_dfe_data_tap_3 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxeq_dfe_data_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxeq_dfe_data_tap_5 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxeq_dfe_data_tap_6 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxeq_dfe_data_tap_7 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxeq_dfe_data_tap_8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxeq_dfe_data_tap_9 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxeq_dfe_edge_tap_2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxeq_dfe_edge_tap_3 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxeq_dfe_edge_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxeq_iq_clk == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxeq_targ_0_hi == 9'd149
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxeq_targ_0_lo == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxeq_vga_gain == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxratewidth_pd_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxrpu_evup_delay_lut_entry2 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxrpu_evup_delay_lut_entry4 == 50'd78
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxrpu_evup_delay_lut_entry5 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxrpu_evup_delay_lut_entry6 == 50'd1406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_rxrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_select_lc_0_tx_path == UX2_SELECT_LC_0_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_select_lc_1_tx_path == UX2_SELECT_LC_1_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_select_lc_2_tx_path == UX2_SELECT_LC_2_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_select_lc_3_tx_path == UX2_SELECT_LC_3_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_select_lc_4_tx_path == UX2_SELECT_LC_4_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_sup_mode == UX2_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_afc_range == UX2_SYNTH_LC_0_AFC_RANGE_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_afc_refclk_count == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_dtr_prop_coeff == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_f_max_vco_hz == 40'd10500000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_f_min_vco_hz == 40'd8000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_fast_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_fast_tx_postdiv_counter == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_feed_forward_gain == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_fine_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_fine_int_coeff_tmp == 4'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_fine_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_fine_prop_coeff_tmp == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_kvcc_settle_maxcnt == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_m_counter == 9'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_med_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_med_tx_postdiv_counter == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_refclk_in_1us == 8'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_slow_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_slow_tx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_tdc_fine_res_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_tdc_target_count == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_0_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_afc_range == UX2_SYNTH_LC_1_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_feed_forward_gain == 8'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_m_counter == 9'd45
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_1_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_afc_range == UX2_SYNTH_LC_2_AFC_RANGE_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_dtr_int_coeff == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_feed_forward_gain == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_m_counter == 9'd27
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_2_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_afc_range == UX2_SYNTH_LC_3_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_feed_forward_gain == 8'd23
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_m_counter == 9'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_3_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_afc_range == UX2_SYNTH_LC_4_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_afc_refclk_count == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_dtr_int_coeff == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_feed_forward_gain == 8'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_fine_int_coeff == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_kvcc_settle_maxcnt == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_m_counter == 9'd216
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_med_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_refclk_in_1us == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_tdc_refclk_count == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_tdc_target_count == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_4_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_fast_bw_sel == UX2_SYNTH_LC_FAST_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_fast_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_fast_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_fast_primary_use == UX2_SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_fast_refclk_mux_select == UX2_SYNTH_LC_FAST_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_fast_refclk_type_select == UX2_SYNTH_LC_FAST_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_fast_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_fb_div_emb_mult_counter == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_l_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_l_counter_physical == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_med_bw_sel == UX2_SYNTH_LC_MED_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_med_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_med_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_med_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_med_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_med_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_med_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_med_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_med_primary_use == UX2_SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_med_refclk_mux_select == UX2_SYNTH_LC_MED_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_med_refclk_type_select == UX2_SYNTH_LC_MED_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_med_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_slow_bw_sel == UX2_SYNTH_LC_SLOW_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_slow_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_slow_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_slow_primary_use == UX2_SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_slow_refclk_mux_select == UX2_SYNTH_LC_SLOW_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_slow_refclk_type_select == UX2_SYNTH_LC_SLOW_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synth_lc_slow_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlc_0_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlc_0_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlc_0_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlc_0_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlc_1_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlc_1_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlc_1_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlc_1_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlc_2_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlc_2_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlc_2_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlc_2_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlc_3_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlc_3_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlc_3_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlc_3_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlc_4_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlc_4_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlc_4_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlc_4_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlc_dcdmeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlcfastratewidth_pd_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlcfastrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlcfastrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlcfastrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlcfastrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlcfastrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlcfastrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlcfastrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlcfastrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlcfastrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlcfastrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlcfastrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlcmedrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlcmedrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlcmedrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlcmedrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlcmedrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlcmedrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlcmedrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlcmedrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlcmedrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlcmedrpu_evup_delay_lut_entry7 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlcslowrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlcslowrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlcslowrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlcslowrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlcslowrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlcslowrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlcslowrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlcslowrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlcslowrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_synthlcslowrpu_evup_delay_lut_entry7 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tdc_refclk_count_divisor == 40'd850000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tdc_refclk_count_scratch == 40'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tdc_target_count_scratch == 40'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tx_bond_size == UX2_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tx_cal_dutymeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tx_i_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tx_i_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tx_i_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tx_master_bond_chnl == UX2_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tx_o_usr_clk_1_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tx_o_usr_clk_1_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tx_o_usr_clk_2_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tx_over_sample == UX2_TX_OVER_SAMPLE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tx_pll == UX2_TX_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tx_pll_bw_sel == UX2_TX_PLL_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tx_pll_is_downstream_pll == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tx_pll_refclk_mux_select == UX2_TX_PLL_REFCLK_MUX_SELECT_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tx_pll_refclk_select == UX2_TX_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tx_protocol == UX2_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tx_tuning_hint == UX2_TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tx_user_clk1_mux == UX2_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tx_user_clk2_mux == UX2_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tx_user_clk_slow_med_mux == UX2_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tx_which_lane_to_copy == UX2_TX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_tx_width == UX2_TX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_txeq_main_tap == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_txratewidth_rst_b0_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_txrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_txrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_txrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_txrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_txrpu_evup_delay_lut_entry2 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_txrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_txrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_txrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_txrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_txrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_txrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_txrx_channel_operation == UX2_TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_txrx_line_encoding_type == UX2_TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_txrx_xcvr_speed_bucket == UX2_TXRX_XCVR_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux2_vreg_loopen_maxcnt_scratch == 40'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_0_rx_synth_select == UX3_0_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_0_tx_synth_select == UX3_0_TX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_1_rx_synth_select == UX3_1_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_1_tx_synth_select == UX3_1_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_2_rx_synth_select == UX3_2_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_2_tx_synth_select == UX3_2_TX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_3_rx_synth_select == UX3_3_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_3_tx_synth_select == UX3_3_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_4_rx_synth_select == UX3_4_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_4_tx_synth_select == UX3_4_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_0_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_0_hscount == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_0_m_counter_physical == 9'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_0_meascount == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_0_mod_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_0_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_0_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_0_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_0_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_0_refclk_type_select == UX3_CDR_0_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_0_watchdogtmr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_1_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_1_hscount == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_1_m_counter_physical == 9'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_1_meascount == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_1_mod_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_1_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_1_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_1_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_1_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_1_refclk_type_select == UX3_CDR_1_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_1_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_2_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_2_hscount == 8'd180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_2_m_counter_physical == 9'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_2_meascount == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_2_mod_counter == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_2_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_2_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_2_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_2_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_2_refclk_type_select == UX3_CDR_2_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_2_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_3_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_3_hscount == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_3_m_counter_physical == 9'd66
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_3_meascount == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_3_mod_counter == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_3_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_3_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_3_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_3_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_3_refclk_type_select == UX3_CDR_3_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_3_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_4_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_4_hscount == 8'd206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_4_m_counter_physical == 9'd210
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_4_meascount == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_4_mod_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_4_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_4_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_4_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_4_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_4_refclk_type_select == UX3_CDR_4_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_4_watchdogtmr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_bw_sel == UX3_CDR_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_f_mod_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_f_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_hscount_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_is_cascaded == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_is_fractional == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_l_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_l_counter_physical == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_m_counter == 9'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_meascount_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_mod_counter_scratch == 40'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_ppm_driftcount == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_ppm_driftmax == 16'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_ppm_driftmax_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_ppm_driftmax_scratch_denominator == 47'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_ppm_driftmax_scratch_numerator == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_ppm_tolerance == 16'd7600
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_refclk_mux_select == UX3_CDR_REFCLK_MUX_SELECT_REGIONAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_refclk_select == UX3_CDR_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_squelch_sample_count == 10'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_squelch_sample_scratch == 40'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cdr_watchdogtmr_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cmn_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cmn_rx_cdr_refclk_mux_select == UX3_CMN_RX_CDR_REFCLK_MUX_SELECT_REGIONAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cmnrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cmnrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cmnrpu_evdn_delay_lut_entry3 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cmnrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cmnrpu_evup_delay_lut_entry2 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cmnrpu_evup_delay_lut_entry3 == 50'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cmnrpu_evup_delay_lut_entry4 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cmnrpu_evup_delay_lut_entry5 == 50'd62
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cmnrpu_evup_delay_lut_entry6 == 50'd390
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_cmnrpu_evup_delay_lut_entry7 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_core_pll == UX3_CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_core_pll_bw_sel == UX3_CORE_PLL_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_core_pll_refclk_select == UX3_CORE_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_dpma_f_out_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_dpma_n_counter == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_dpma_n_counter_physical == UX3_DPMA_N_COUNTER_PHYSICAL_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_dpma_n_counter_scratch == 40'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_dpma_refclk_source == UX3_DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_dts_ssdiv_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_duplex_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_enable_med_lc_0_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_enable_med_lc_1_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_enable_med_lc_2_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_enable_med_lc_3_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_enable_med_lc_4_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_enable_port_control_of_cdr_ltr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_enable_slow_lc_0_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_enable_slow_lc_1_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_enable_slow_lc_2_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_enable_slow_lc_3_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_enable_slow_lc_4_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_ethernet_source == UX3_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_expose_pcie_gen1_gen6_critical_signals == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_f_cascade_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_feed_forward_gain_scratch == 47'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_feed_forward_temp_one == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_feed_forward_temp_two == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_flux_mode == UX3_FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_kvcc_settle_maxcnt_scratch == 40'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_lane_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_loopback_mode == UX3_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_master_sup_mode == UX3_MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_oversampling_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_primary_use == UX3_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_ref_clk_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_refclk_in_1us_scratch == 40'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rx_adapt_mode == UX3_RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rx_bond_size == UX3_RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rx_cal_dutymeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rx_master_bond_chnl == UX3_RX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rx_o_usr_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rx_o_usr_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rx_onchip_termination == UX3_RX_ONCHIP_TERMINATION_R_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rx_over_sample == UX3_RX_OVER_SAMPLE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rx_protocol == UX3_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rx_term_mode_select == UX3_RX_TERM_MODE_SELECT_GROUNDED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rx_tuning_hint == UX3_RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rx_which_lane_to_copy == UX3_RX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rx_width == UX3_RX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxeq_ctle_bias_adj == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxeq_ctle_biasboost == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxeq_ctle_lf_gain == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxeq_ctle_midband_zero == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxeq_ctle_stage_1_dcgain == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxeq_ctle_stage_1_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxeq_ctle_stage_2_cap == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxeq_ctle_stage_2_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxeq_ctle_stage_2_reszero == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxeq_ctle_stage_3_dcgain == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxeq_ctle_stage_3_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxeq_dfe_data_tap_10 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxeq_dfe_data_tap_11 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxeq_dfe_data_tap_12 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxeq_dfe_data_tap_13 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxeq_dfe_data_tap_14 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxeq_dfe_data_tap_15 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxeq_dfe_data_tap_16 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxeq_dfe_data_tap_2 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxeq_dfe_data_tap_3 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxeq_dfe_data_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxeq_dfe_data_tap_5 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxeq_dfe_data_tap_6 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxeq_dfe_data_tap_7 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxeq_dfe_data_tap_8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxeq_dfe_data_tap_9 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxeq_dfe_edge_tap_2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxeq_dfe_edge_tap_3 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxeq_dfe_edge_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxeq_iq_clk == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxeq_targ_0_hi == 9'd149
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxeq_targ_0_lo == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxeq_vga_gain == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxratewidth_pd_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxrpu_evup_delay_lut_entry2 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxrpu_evup_delay_lut_entry4 == 50'd78
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxrpu_evup_delay_lut_entry5 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxrpu_evup_delay_lut_entry6 == 50'd1406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_rxrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_select_lc_0_tx_path == UX3_SELECT_LC_0_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_select_lc_1_tx_path == UX3_SELECT_LC_1_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_select_lc_2_tx_path == UX3_SELECT_LC_2_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_select_lc_3_tx_path == UX3_SELECT_LC_3_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_select_lc_4_tx_path == UX3_SELECT_LC_4_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_sup_mode == UX3_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_afc_range == UX3_SYNTH_LC_0_AFC_RANGE_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_afc_refclk_count == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_dtr_prop_coeff == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_f_max_vco_hz == 40'd10500000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_f_min_vco_hz == 40'd8000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_fast_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_fast_tx_postdiv_counter == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_feed_forward_gain == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_fine_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_fine_int_coeff_tmp == 4'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_fine_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_fine_prop_coeff_tmp == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_kvcc_settle_maxcnt == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_m_counter == 9'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_med_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_med_tx_postdiv_counter == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_refclk_in_1us == 8'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_slow_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_slow_tx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_tdc_fine_res_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_tdc_target_count == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_0_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_afc_range == UX3_SYNTH_LC_1_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_feed_forward_gain == 8'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_m_counter == 9'd45
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_1_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_afc_range == UX3_SYNTH_LC_2_AFC_RANGE_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_dtr_int_coeff == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_feed_forward_gain == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_m_counter == 9'd27
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_2_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_afc_range == UX3_SYNTH_LC_3_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_feed_forward_gain == 8'd23
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_m_counter == 9'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_3_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_afc_range == UX3_SYNTH_LC_4_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_afc_refclk_count == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_dtr_int_coeff == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_feed_forward_gain == 8'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_fine_int_coeff == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_kvcc_settle_maxcnt == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_m_counter == 9'd216
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_med_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_refclk_in_1us == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_tdc_refclk_count == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_tdc_target_count == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_4_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_fast_bw_sel == UX3_SYNTH_LC_FAST_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_fast_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_fast_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_fast_primary_use == UX3_SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_fast_refclk_mux_select == UX3_SYNTH_LC_FAST_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_fast_refclk_type_select == UX3_SYNTH_LC_FAST_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_fast_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_fb_div_emb_mult_counter == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_l_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_l_counter_physical == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_med_bw_sel == UX3_SYNTH_LC_MED_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_med_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_med_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_med_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_med_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_med_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_med_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_med_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_med_primary_use == UX3_SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_med_refclk_mux_select == UX3_SYNTH_LC_MED_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_med_refclk_type_select == UX3_SYNTH_LC_MED_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_med_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_slow_bw_sel == UX3_SYNTH_LC_SLOW_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_slow_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_slow_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_slow_primary_use == UX3_SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_slow_refclk_mux_select == UX3_SYNTH_LC_SLOW_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_slow_refclk_type_select == UX3_SYNTH_LC_SLOW_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synth_lc_slow_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlc_0_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlc_0_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlc_0_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlc_0_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlc_1_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlc_1_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlc_1_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlc_1_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlc_2_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlc_2_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlc_2_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlc_2_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlc_3_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlc_3_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlc_3_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlc_3_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlc_4_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlc_4_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlc_4_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlc_4_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlc_dcdmeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlcfastratewidth_pd_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlcfastrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlcfastrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlcfastrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlcfastrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlcfastrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlcfastrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlcfastrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlcfastrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlcfastrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlcfastrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlcfastrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlcmedrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlcmedrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlcmedrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlcmedrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlcmedrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlcmedrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlcmedrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlcmedrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlcmedrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlcmedrpu_evup_delay_lut_entry7 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlcslowrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlcslowrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlcslowrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlcslowrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlcslowrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlcslowrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlcslowrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlcslowrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlcslowrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_synthlcslowrpu_evup_delay_lut_entry7 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tdc_refclk_count_divisor == 40'd850000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tdc_refclk_count_scratch == 40'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tdc_target_count_scratch == 40'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tx_bond_size == UX3_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tx_cal_dutymeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tx_i_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tx_i_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tx_i_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tx_master_bond_chnl == UX3_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tx_o_usr_clk_1_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tx_o_usr_clk_1_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tx_o_usr_clk_2_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tx_over_sample == UX3_TX_OVER_SAMPLE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tx_pll == UX3_TX_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tx_pll_bw_sel == UX3_TX_PLL_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tx_pll_is_downstream_pll == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tx_pll_refclk_mux_select == UX3_TX_PLL_REFCLK_MUX_SELECT_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tx_pll_refclk_select == UX3_TX_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tx_protocol == UX3_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tx_tuning_hint == UX3_TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tx_user_clk1_mux == UX3_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tx_user_clk2_mux == UX3_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tx_user_clk_slow_med_mux == UX3_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tx_which_lane_to_copy == UX3_TX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_tx_width == UX3_TX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_txeq_main_tap == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_txratewidth_rst_b0_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_txrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_txrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_txrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_txrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_txrpu_evup_delay_lut_entry2 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_txrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_txrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_txrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_txrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_txrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_txrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_txrx_channel_operation == UX3_TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_txrx_line_encoding_type == UX3_TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_txrx_xcvr_speed_bucket == UX3_TXRX_XCVR_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux3_vreg_loopen_maxcnt_scratch == 40'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux_quad_instance == UX_QUAD_INSTANCE_TWO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.flux_top.ux_speed_grade == UX_SPEED_GRADE_DASH2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.all_enabled_refclks_always_running == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.all_ux_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.hard_all_ux_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.refclk0_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.refclk1_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.refclk2_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.refclk3_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.refclk4_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.refclk5_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.refclk6_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.refclk7_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.refclk8_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.refclk9_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_01_st_pt == 6'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_10_st_pt == 6'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_bonding_size_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_bonding_size_cfg_reserved_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ethernet_source == UX0_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_external_dpma_refclk_source == UX0_EXTERNAL_DPMA_REFCLK_SOURCE_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_fec_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_flux_mode == UX0_FLUX_MODE_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_loopback_mode == UX0_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_q_dl_cfg_latpls_bw_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_q_dl_cfg_rst_rxbit_cntr_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_q_dl_cfg_sel_rxbit_adder_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_rx_adapt_mode == UX0_RX_ADAPT_MODE_UX_RX_ADAPT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_rx_protocol == UX0_RX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_rx_rst_value_pre_user_mode_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_rx_tuning_hint == UX0_RX_TUNING_HINT_SDI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_rx_user_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_standalone_core_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_standalone_core_clk_mux == UX0_STANDALONE_CORE_CLK_MUX_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_0_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_0_31 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_1_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_2_16to15 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_syspll0_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_syspll1_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_syspll2_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_tx_bond_size == UX0_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_tx_master_bond_chnl == UX0_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_tx_protocol == UX0_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_tx_rst_value_pre_user_mode_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_tx_tuning_hint == UX0_TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_tx_user_clk1_mux == UX0_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_tx_user_clk2_mux == UX0_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_tx_user_clk_slow_med_mux == UX0_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_tx_width == UX0_TX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_0_23 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_0_31 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_1_1 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_2_16to15 == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxeiosdetectstat_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxeq_clr_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxeq_precal_code_sel_lx_nt_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxeq_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxeq_static_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxeyediag_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxovrcdrlock2dataen_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxterm_hiz_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txbeacon_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txclkdivrate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txdetectrx_req_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txdrv_levn_lx_5to0 == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txdrv_levnm1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txdrv_levnp1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txdrv_levnp2_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txdrv_spare_l0_1to0 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txdrv_spare_l0_3to2 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txdrv_spare_l0_5to4 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txdrv_spare_l0_9to6 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txelecidle_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_0_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_0_31 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_1_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_2_16to15 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux0_vsr_mode == UX0_VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_01_st_pt == 6'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_10_st_pt == 6'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_bonding_size_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_bonding_size_cfg_reserved_attr == 25'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ethernet_source == UX1_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_external_dpma_refclk_source == UX1_EXTERNAL_DPMA_REFCLK_SOURCE_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_flux_mode == UX1_FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_loopback_mode == UX1_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_q_dl_cfg_latpls_bw_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_q_dl_cfg_rst_rxbit_cntr_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_q_dl_cfg_sel_rxbit_adder_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_rx_adapt_mode == UX1_RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_rx_protocol == UX1_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_rx_rst_value_pre_user_mode_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_rx_tuning_hint == UX1_RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_standalone_core_clk_mux == UX1_STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_0_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_0_31 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_1_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_2_16to15 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_syspll0_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_syspll1_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_syspll2_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_tx_bond_size == UX1_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_tx_master_bond_chnl == UX1_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_tx_protocol == UX1_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_tx_rst_value_pre_user_mode_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_tx_tuning_hint == UX1_TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_tx_user_clk1_mux == UX1_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_tx_user_clk2_mux == UX1_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_tx_user_clk_slow_med_mux == UX1_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_tx_width == UX1_TX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_0_23 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_0_31 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_1_1 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_2_16to15 == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxeiosdetectstat_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxeq_clr_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxeq_precal_code_sel_lx_nt_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxeq_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxeq_static_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxeyediag_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxovrcdrlock2dataen_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxterm_hiz_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txbeacon_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txclkdivrate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txdetectrx_req_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txdrv_levn_lx_5to0 == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txdrv_levnm1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txdrv_levnp1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txdrv_levnp2_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txdrv_spare_l0_1to0 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txdrv_spare_l0_3to2 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txdrv_spare_l0_5to4 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txdrv_spare_l0_9to6 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txelecidle_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_0_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_0_31 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_1_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_2_16to15 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux1_vsr_mode == UX1_VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_01_st_pt == 6'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_10_st_pt == 6'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_bonding_size_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_bonding_size_cfg_reserved_attr == 25'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ethernet_source == UX2_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_external_dpma_refclk_source == UX2_EXTERNAL_DPMA_REFCLK_SOURCE_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_flux_mode == UX2_FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_loopback_mode == UX2_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_q_dl_cfg_latpls_bw_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_q_dl_cfg_rst_rxbit_cntr_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_q_dl_cfg_sel_rxbit_adder_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_rx_adapt_mode == UX2_RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_rx_protocol == UX2_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_rx_rst_value_pre_user_mode_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_rx_tuning_hint == UX2_RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_standalone_core_clk_mux == UX2_STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_0_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_0_31 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_1_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_2_16to15 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_syspll0_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_syspll1_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_syspll2_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_tx_bond_size == UX2_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_tx_master_bond_chnl == UX2_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_tx_protocol == UX2_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_tx_rst_value_pre_user_mode_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_tx_tuning_hint == UX2_TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_tx_user_clk1_mux == UX2_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_tx_user_clk2_mux == UX2_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_tx_user_clk_slow_med_mux == UX2_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_tx_width == UX2_TX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_0_23 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_0_31 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_1_1 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_2_16to15 == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxeiosdetectstat_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxeq_clr_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxeq_precal_code_sel_lx_nt_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxeq_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxeq_static_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxeyediag_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxovrcdrlock2dataen_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxterm_hiz_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txbeacon_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txclkdivrate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txdetectrx_req_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txdrv_levn_lx_5to0 == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txdrv_levnm1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txdrv_levnp1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txdrv_levnp2_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txdrv_spare_l0_1to0 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txdrv_spare_l0_3to2 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txdrv_spare_l0_5to4 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txdrv_spare_l0_9to6 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txelecidle_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_0_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_0_31 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_1_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_2_16to15 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux2_vsr_mode == UX2_VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_01_st_pt == 6'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_10_st_pt == 6'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_bonding_size_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_bonding_size_cfg_reserved_attr == 25'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ethernet_source == UX3_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_external_dpma_refclk_source == UX3_EXTERNAL_DPMA_REFCLK_SOURCE_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_flux_mode == UX3_FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_loopback_mode == UX3_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_q_dl_cfg_latpls_bw_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_q_dl_cfg_rst_rxbit_cntr_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_q_dl_cfg_sel_rxbit_adder_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_rx_adapt_mode == UX3_RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_rx_protocol == UX3_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_rx_rst_value_pre_user_mode_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_rx_tuning_hint == UX3_RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_standalone_core_clk_mux == UX3_STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_0_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_0_31 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_1_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_2_16to15 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_syspll0_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_syspll1_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_syspll2_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_tx_bond_size == UX3_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_tx_master_bond_chnl == UX3_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_tx_protocol == UX3_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_tx_rst_value_pre_user_mode_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_tx_tuning_hint == UX3_TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_tx_user_clk1_mux == UX3_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_tx_user_clk2_mux == UX3_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_tx_user_clk_slow_med_mux == UX3_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_tx_width == UX3_TX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_0_23 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_0_31 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_1_1 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_2_16to15 == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxeiosdetectstat_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxeq_clr_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxeq_precal_code_sel_lx_nt_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxeq_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxeq_static_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxeyediag_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxovrcdrlock2dataen_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxterm_hiz_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txbeacon_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txclkdivrate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txdetectrx_req_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txdrv_levn_lx_5to0 == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txdrv_levnm1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txdrv_levnp1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txdrv_levnp2_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txdrv_spare_l0_1to0 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txdrv_spare_l0_3to2 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txdrv_spare_l0_5to4 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txdrv_spare_l0_9to6 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txelecidle_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_0_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_0_31 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_1_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_2_16to15 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux3_vsr_mode == UX3_VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_cpi_cmn2_st_pt == 11'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_cpi_lm_addr == 30'd589884
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_cpi_phy_addr == 30'd589888
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_cpi_reserved == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_cpi_seq_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_cpi_timer_max == 16'd500
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_end_pt == 11'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_flux_cpu_freq == 36'd250
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK1_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_bonding_ctrl_cfg_bonding_ctrl_l0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_bonding_ctrl_cfg_bonding_ctrl_l1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_bonding_ctrl_cfg_bonding_ctrl_l2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_bonding_ctrl_cfg_bonding_ctrl_l3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_bonding_ctrl_cfg_bonding_enable_l0_attr == BONDING_L0_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_bonding_ctrl_cfg_bonding_enable_l1_attr == BONDING_L1_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_bonding_ctrl_cfg_bonding_enable_l2_attr == BONDING_L2_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_bonding_ctrl_cfg_bonding_enable_l3_attr == BONDING_L3_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_ckmux_cpu_attr == CKMUX_CPU_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_cpi_seq_ctrl_cfg_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_datapath_loopback_en_cfg_datapath_loopback_en_l0_attr == LB_L0_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_datapath_loopback_en_cfg_datapath_loopback_en_l1_attr == LB_L1_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_datapath_loopback_en_cfg_datapath_loopback_en_l2_attr == LB_L2_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_datapath_loopback_en_cfg_datapath_loopback_en_l3_attr == LB_L3_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_a_cfg_clk_en_dfd_clk_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_a_cfg_dfd_clk_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_a_cfg_dfd_extrig_muxsel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_a_cfg_dfd_mux_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_a_cfg_dfd_rsvd_muxsel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_a_cfg_pattern_cntr_data_sel_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_a_cfg_pattern_cntr_inc_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_a_cfg_pattern_cntr_rst_b_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_b_cfg_apb_rdata_sel_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_b_cfg_rst_dfd_extrig_cntr_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_dl_ctrl_a_l2_cfg_ctrl_reserved_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_dl_ctrl_a_l3_cfg_ctrl_reserved_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_dpma_clk_mux_reserved_attr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e200_rxclk_en_l0_attr == E200_RXCLK_EN_L0_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e200_rxclk_en_l1_attr == E200_RXCLK_EN_L1_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e200_rxclk_en_l2_attr == E200_RXCLK_EN_L2_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e200_rxclk_en_l3_attr == E200_RXCLK_EN_L3_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e200_txclk_en_l0_attr == E200_TXCLK_EN_L0_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e200_txclk_en_l1_attr == E200_TXCLK_EN_L1_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e200_txclk_en_l2_attr == E200_TXCLK_EN_L2_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e200_txclk_en_l3_attr == E200_TXCLK_EN_L3_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_slow_med_l0_attr == E400_CKMUX_SLOW_MED_L0_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_slow_med_l1_attr == E400_CKMUX_SLOW_MED_L1_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_slow_med_l2_attr == E400_CKMUX_SLOW_MED_L2_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_slow_med_l3_attr == E400_CKMUX_SLOW_MED_L3_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser0_l0_attr == E400_CKMUX_TXUSER0_L0_NON_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser0_l1_attr == E400_CKMUX_TXUSER0_L1_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser0_l2_attr == E400_CKMUX_TXUSER0_L2_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser0_l3_attr == E400_CKMUX_TXUSER0_L3_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser1_l0_attr == E400_CKMUX_TXUSER1_L0_NON_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser1_l1_attr == E400_CKMUX_TXUSER1_L1_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser1_l2_attr == E400_CKMUX_TXUSER1_L2_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser1_l3_attr == E400_CKMUX_TXUSER1_L3_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser2_l0_attr == E400_CKMUX_TXUSER2_L0_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser2_l1_attr == E400_CKMUX_TXUSER2_L1_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser2_l2_attr == E400_CKMUX_TXUSER2_L2_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser2_l3_attr == E400_CKMUX_TXUSER2_L3_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_rxclk_en_l0_attr == E400_RXCLK_EN_L0_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_rxclk_en_l1_attr == E400_RXCLK_EN_L1_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_rxclk_en_l2_attr == E400_RXCLK_EN_L2_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_rxclk_en_l3_attr == E400_RXCLK_EN_L3_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_rxusrclk_en_l0_attr == E400_RXUSRCLK_EN_L0_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_rxusrclk_en_l1_attr == E400_RXUSRCLK_EN_L1_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_rxusrclk_en_l2_attr == E400_RXUSRCLK_EN_L2_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_rxusrclk_en_l3_attr == E400_RXUSRCLK_EN_L3_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_txclk_en_l0_attr == E400_TXCLK_EN_L0_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_txclk_en_l1_attr == E400_TXCLK_EN_L1_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_txclk_en_l2_attr == E400_TXCLK_EN_L2_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_txclk_en_l3_attr == E400_TXCLK_EN_L3_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk0_en_l0_attr == E400_USRCLK0_EN_L0_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk0_en_l1_attr == E400_USRCLK0_EN_L1_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk0_en_l2_attr == E400_USRCLK0_EN_L2_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk0_en_l3_attr == E400_USRCLK0_EN_L3_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk1_en_l0_attr == E400_USRCLK1_EN_L0_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk1_en_l1_attr == E400_USRCLK1_EN_L1_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk1_en_l2_attr == E400_USRCLK1_EN_L2_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk1_en_l3_attr == E400_USRCLK1_EN_L3_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk2_en_l0_attr == E400_USRCLK2_EN_L0_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk2_en_l1_attr == E400_USRCLK2_EN_L1_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk2_en_l2_attr == E400_USRCLK2_EN_L2_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk2_en_l3_attr == E400_USRCLK2_EN_L3_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e_rx_dp_pipe_l0_attr == E_RX_DP_PIPE_L0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e_rx_dp_pipe_l1_attr == E_RX_DP_PIPE_L1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e_rx_dp_pipe_l2_attr == E_RX_DP_PIPE_L2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e_rx_dp_pipe_l3_attr == E_RX_DP_PIPE_L3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e_tx_dp_pipe_l0_attr == E_TX_DP_PIPE_L0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e_tx_dp_pipe_l1_attr == E_TX_DP_PIPE_L1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e_tx_dp_pipe_l2_attr == E_TX_DP_PIPE_L2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_e_tx_dp_pipe_l3_attr == E_TX_DP_PIPE_L3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_fw_load_base_l0_cfg_value_attr == 32'd277792
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_fw_load_base_l1_cfg_value_attr == 32'd310560
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_fw_load_base_l2_cfg_value_attr == 32'd343328
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_fw_load_base_l3_cfg_value_attr == 32'd376096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_i_pll0_hz == 36'd250000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_i_pll1_hz == 36'd250000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_i_pll2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_indirect_access_ctrl_cfg_fw_load_disable_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_indirect_access_ctrl_cfg_fw_load_mode_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_indirect_access_ctrl_cfg_mapped_base_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_indirect_access_ctrl_cfg_reserved_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_indirect_access_ctrl_cfg_unmapped_base_attr == 18'd16384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_mode_ctrl_cfg_func_mode_l0_attr == FUNC_MODE_E400_L0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_mode_ctrl_cfg_func_mode_l1_attr == FUNC_MODE_E400_L1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_mode_ctrl_cfg_func_mode_l2_attr == FUNC_MODE_E400_L2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_mode_ctrl_cfg_func_mode_l3_attr == FUNC_MODE_E400_L3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_medclk_en_l0_attr == PCIE_MEDCLK_EN_L0_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_medclk_en_l1_attr == PCIE_MEDCLK_EN_L1_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_medclk_en_l2_attr == PCIE_MEDCLK_EN_L2_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_medclk_en_l3_attr == PCIE_MEDCLK_EN_L3_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_pclk_en_l0_attr == PCIE_PCLK_EN_L0_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_pclk_en_l1_attr == PCIE_PCLK_EN_L1_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_pclk_en_l2_attr == PCIE_PCLK_EN_L2_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_pclk_en_l3_attr == PCIE_PCLK_EN_L3_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_refclk_en_l0_attr == PCIE_REFCLK_EN_L0_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_refclk_en_l1_attr == PCIE_REFCLK_EN_L1_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_refclk_en_l2_attr == PCIE_REFCLK_EN_L2_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_refclk_en_l3_attr == PCIE_REFCLK_EN_L3_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_rxclk_en_l0_attr == PCIE_RXCLK_EN_L0_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_rxclk_en_l1_attr == PCIE_RXCLK_EN_L1_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_rxclk_en_l2_attr == PCIE_RXCLK_EN_L2_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_rxclk_en_l3_attr == PCIE_RXCLK_EN_L3_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_slowclk_en_l0_attr == PCIE_SLOWCLK_EN_L0_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_slowclk_en_l1_attr == PCIE_SLOWCLK_EN_L1_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_slowclk_en_l2_attr == PCIE_SLOWCLK_EN_L2_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_slowclk_en_l3_attr == PCIE_SLOWCLK_EN_L3_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_reserved0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_10_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_11_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_12_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_13_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_14_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_15_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_16_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_17_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_18_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_19_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_20_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_21_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_22_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_23_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_24_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_25_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_26_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_27_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_28_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_29_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_30_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_31_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_32_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_33_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_34_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_35_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_36_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_37_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_38_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_39_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_40_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_41_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_42_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_43_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_44_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_45_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_46_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_47_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_48_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_49_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_50_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_51_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_52_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_53_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_54_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_55_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_56_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_57_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_58_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_59_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_5_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_60_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_61_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_62_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_63_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_6_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_7_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_8_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_9_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_ctrl_0_cfg_restart_seq_sm_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_ctrl_0_cfg_skip_rd_seq_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_ctrl_1_cfg_seqen_0to31_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_ctrl_2_cfg_seqen_32to63_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_ctrl_3_cfg_seq_rdwrb_0to31_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_ctrl_4_cfg_seq_rdwrb_32to63_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_0_attr == 32'd32874599
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_10_attr == 32'd41731
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_11_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_12_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_13_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_14_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_15_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_16_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_17_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_18_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_19_attr == 32'd41200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_1_attr == 32'd41138
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_20_attr == 32'd41456
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_21_attr == 32'd41712
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_22_attr == 32'd41968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_23_attr == 32'd41060
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_24_attr == 32'd41316
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_25_attr == 32'd41572
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_26_attr == 32'd41828
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_27_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_28_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_29_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_2_attr == 32'd134258864
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_30_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_31_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_32_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_33_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_34_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_35_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_36_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_37_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_38_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_39_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_3_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_40_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_41_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_42_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_43_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_44_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_45_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_46_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_47_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_48_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_49_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_4_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_50_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_51_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_52_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_53_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_54_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_55_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_56_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_57_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_58_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_59_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_5_attr == 32'd16359695
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_60_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_61_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_62_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_63_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_6_attr == 32'd41219
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_7_attr == 32'd16359951
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_8_attr == 32'd41475
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_9_attr == 32'd16360207
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_0_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_10_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_11_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_12_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_13_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_14_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_15_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_16_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_17_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_18_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_19_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_1_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_20_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_21_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_22_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_23_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_24_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_25_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_26_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_27_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_28_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_29_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_2_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_30_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_31_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_32_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_33_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_34_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_35_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_36_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_37_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_38_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_39_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_3_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_40_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_41_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_42_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_43_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_44_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_45_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_46_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_47_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_48_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_49_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_4_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_50_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_51_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_52_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_53_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_54_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_55_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_56_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_57_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_58_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_59_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_5_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_60_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_61_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_62_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_63_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_6_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_7_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_8_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_9_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_quad_instance == UX_QUAD_INSTANCE_TWO
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_2.gdr_ux_quad_avmm_cfgcsr.ux_rst_value_pre_user_mode_reserved_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.all_enabled_refclks_always_running == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.all_ux_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.bot_f_fastest_reconfig_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.bot_refclk_reconfig_span == BOT_REFCLK_RECONFIG_SPAN_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.bot_syspll_refclk_output_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ch1_ch0_master_pll_pair_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ch3_ch2_master_pll_pair_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.clkrx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.f_avmm_clk_hz == 40'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.f_bot_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.f_bot_syspll_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.f_fastest_reconfig_refclk_global_refclk_0_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.f_fastest_reconfig_refclk_global_refclk_1_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.f_fastest_reconfig_refclk_global_refclk_2_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.f_fastest_reconfig_refclk_global_refclk_3_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.f_fastest_reconfig_refclk_regional_refclk_0_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.f_fastest_reconfig_refclk_regional_refclk_1_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.f_global_refclk_0_bot_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.f_global_refclk_0_bot_right_top_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.f_global_refclk_1_bot_right_top_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.f_global_refclk_1_top_right_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.f_global_refclk_2_bot_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.f_global_refclk_2_bot_right_top_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.f_global_refclk_3_bot_right_top_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.f_global_refclk_3_top_right_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.f_local_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.f_regional_refclk_0_bot_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.f_regional_refclk_0_bot_right_top_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.f_regional_refclk_1_bot_right_top_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.f_regional_refclk_1_top_right_hz == 40'd800000001
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.f_top_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.f_top_syspll_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.global_refclk_0_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.global_refclk_0_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.global_refclk_1_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.global_refclk_1_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.global_refclk_2_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.global_refclk_2_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.global_refclk_3_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.global_refclk_3_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.hard_all_ux_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_avmm == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_bot_clkrx_base == POWERMODE_AC_MODE_BOT_CLKRX_BASE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_bot_cmos_driver == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_flux == POWERMODE_AC_MODE_FLUX_FLUX_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_global_refclk_0_bot == POWERMODE_AC_MODE_GLOBAL_REFCLK_0_BOT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_global_refclk_0_top == POWERMODE_AC_MODE_GLOBAL_REFCLK_0_TOP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_global_refclk_1_bot == POWERMODE_AC_MODE_GLOBAL_REFCLK_1_BOT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_global_refclk_1_top == POWERMODE_AC_MODE_GLOBAL_REFCLK_1_TOP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_global_refclk_2_bot == POWERMODE_AC_MODE_GLOBAL_REFCLK_2_BOT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_global_refclk_2_top == POWERMODE_AC_MODE_GLOBAL_REFCLK_2_TOP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_global_refclk_3_bot == POWERMODE_AC_MODE_GLOBAL_REFCLK_3_BOT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_global_refclk_3_top == POWERMODE_AC_MODE_GLOBAL_REFCLK_3_TOP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_regional_refclk_0_bot == POWERMODE_AC_MODE_REGIONAL_REFCLK_0_BOT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_regional_refclk_0_top == POWERMODE_AC_MODE_REGIONAL_REFCLK_0_TOP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_regional_refclk_1_bot == POWERMODE_AC_MODE_REGIONAL_REFCLK_1_BOT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_regional_refclk_1_top == POWERMODE_AC_MODE_REGIONAL_REFCLK_1_TOP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_rx_ux0 == UX0_POWERMODE_AC_MODE_RX_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_rx_ux1 == UX1_POWERMODE_AC_MODE_RX_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_rx_ux2 == UX2_POWERMODE_AC_MODE_RX_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_rx_ux3 == UX3_POWERMODE_AC_MODE_RX_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_synth_lc_fast_ux0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_synth_lc_fast_ux1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_synth_lc_fast_ux2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_synth_lc_fast_ux3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_synth_lc_med_ux0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_synth_lc_med_ux1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_synth_lc_med_ux2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_synth_lc_med_ux3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_synth_lc_slow_ux0 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_synth_lc_slow_ux1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_synth_lc_slow_ux2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_synth_lc_slow_ux3 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_top_clkrx_base == POWERMODE_AC_MODE_TOP_CLKRX_BASE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_top_cmos_driver == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_tx_ux0 == UX0_POWERMODE_AC_MODE_TX_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_tx_ux1 == UX1_POWERMODE_AC_MODE_TX_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_tx_ux2 == UX2_POWERMODE_AC_MODE_TX_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_ac_mode_tx_ux3 == UX3_POWERMODE_AC_MODE_TX_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_dc == POWERUP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_avmm == 40'd62500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_bot_clkrx_base == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_bot_cmos_driver == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_flux == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_global_refclk_0_bot == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_global_refclk_0_top == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_global_refclk_1_bot == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_global_refclk_1_top == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_global_refclk_2_bot == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_global_refclk_2_top == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_global_refclk_3_bot == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_global_refclk_3_top == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_regional_refclk_0_bot == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_regional_refclk_0_top == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_regional_refclk_1_bot == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_regional_refclk_1_top == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_rx_parallel_ux0 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_rx_parallel_ux1 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_rx_parallel_ux2 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_rx_parallel_ux3 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_rx_ux0 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_rx_ux1 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_rx_ux2 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_rx_ux3 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_synth_lc_fast_ux0 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_synth_lc_fast_ux1 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_synth_lc_fast_ux2 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_synth_lc_fast_ux3 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_synth_lc_med_ux0 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_synth_lc_med_ux1 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_synth_lc_med_ux2 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_synth_lc_med_ux3 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_synth_lc_slow_ux0 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_synth_lc_slow_ux1 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_synth_lc_slow_ux2 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_synth_lc_slow_ux3 == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_top_clkrx_base == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_top_cmos_driver == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_tx_parallel_ux0 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_tx_parallel_ux1 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_tx_parallel_ux2 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_tx_parallel_ux3 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_tx_ux0 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_tx_ux1 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_tx_ux2 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.powermode_freq_hz_tx_ux3 == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.refclk0_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.refclk1_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.refclk2_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.refclk3_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.refclk4_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.refclk5_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.refclk6_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.refclk7_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.refclk8_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.refclk9_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.regional_refclk_0_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.regional_refclk_0_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.regional_refclk_1_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.regional_refclk_1_right_adjacent_active == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.top_f_fastest_reconfig_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.top_refclk_reconfig_span == TOP_REFCLK_RECONFIG_SPAN_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.top_syspll_refclk_output_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_cdr_bw_sel == UX0_CDR_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_cdr_f_mod_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_cdr_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_cdr_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_cdr_f_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_cdr_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_cdr_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_cdr_is_cascaded == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_cdr_l_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_cdr_m_counter == 9'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_cdr_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_cdr_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_cdr_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_cdr_ppm_driftcount == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_cdr_refclk_mux_select == UX0_CDR_REFCLK_MUX_SELECT_REGIONAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_cdr_refclk_select == UX0_CDR_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_cmn_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_core_pll == UX0_CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_core_pll_refclk_select == UX0_CORE_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_dpma_refclk_source == UX0_DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_duplex_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_enable_port_control_of_cdr_ltr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ethernet_source == UX0_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_expose_pcie_gen1_gen6_critical_signals == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_external_dpma_refclk_source == UX0_EXTERNAL_DPMA_REFCLK_SOURCE_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_flux_mode == UX0_FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_lane_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_loopback_mode == UX0_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_master_sup_mode == UX0_MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_primary_use == UX0_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ref_clk_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_rx_adapt_mode == UX0_RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_rx_bond_size == UX0_RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_rx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_rx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_rx_master_bond_chnl == UX0_RX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_rx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_rx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_rx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_rx_o_usr_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_rx_o_usr_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_rx_onchip_termination == UX0_RX_ONCHIP_TERMINATION_R_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_rx_protocol == UX0_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_rx_term_mode_select == UX0_RX_TERM_MODE_SELECT_GROUNDED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_rx_tuning_hint == UX0_RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_rx_width == UX0_RX_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_rxeq_vga_gain == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_standalone_core_clk_mux == UX0_STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sup_mode == UX0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sv_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sv_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sv_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sv_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sv_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sv_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sv_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sv_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sv_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sv_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sv_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sv_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sv_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sv_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sv_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sv_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_sv_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_0_feed_forward_gain == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_0_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_fast_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_fast_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_fast_primary_use == UX0_SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_fb_div_emb_mult_counter == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_med_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_med_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_med_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_med_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_med_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_med_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_med_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_med_primary_use == UX0_SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_slow_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_slow_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_slow_primary_use == UX0_SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_syspll0_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_syspll1_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_syspll2_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_tx_bond_size == UX0_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_tx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_tx_i_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_tx_i_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_tx_i_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_tx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_tx_master_bond_chnl == UX0_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_tx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_tx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_tx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_tx_o_usr_clk_1_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_tx_o_usr_clk_1_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_tx_o_usr_clk_2_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_tx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_tx_pll == UX0_TX_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_tx_pll_bw_sel == UX0_TX_PLL_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_tx_pll_refclk_mux_select == UX0_TX_PLL_REFCLK_MUX_SELECT_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_tx_pll_refclk_select == UX0_TX_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_tx_protocol == UX0_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_tx_tuning_hint == UX0_TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_tx_user_clk1_mux == UX0_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_tx_user_clk2_mux == UX0_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_tx_user_clk_slow_med_mux == UX0_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_tx_width == UX0_TX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_txeq_main_tap == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_txrx_channel_operation == UX0_TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_txrx_line_encoding_type == UX0_TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_txrx_xcvr_speed_bucket == UX0_TXRX_XCVR_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_en_rxbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_en_rxeiosdetectstat_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_en_rxeq_clr_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_en_rxeq_precal_code_sel_lx_nt_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_en_rxeq_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_en_rxeq_static_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_en_rxeyediag_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_en_rxovrcdrlock2dataen_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_en_rxpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_en_rxrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_en_rxterm_hiz_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_en_rxwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_en_txbeacon_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_en_txbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_en_txclkdivrate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_en_txdetectrx_req_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_en_txdrv_levn_lx_5to0 == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_en_txdrv_levnm1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_en_txdrv_levnp1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_en_txdrv_levnp2_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_en_txdrv_spare_l0_1to0 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_en_txdrv_spare_l0_3to2 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_en_txdrv_spare_l0_5to4 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_en_txdrv_spare_l0_9to6 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_en_txelecidle_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_en_txpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_en_txrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_en_txwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_ovr_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_ovr_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_ovr_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_ovr_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_ovr_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_ovr_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_ovr_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_ovr_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_ovr_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_ovr_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_ovr_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_ovr_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_ovr_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_ovr_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_ovr_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_ovr_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_ur_ovr_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux0_vsr_mode == UX0_VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_cdr_bw_sel == UX1_CDR_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_cdr_f_mod_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_cdr_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_cdr_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_cdr_f_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_cdr_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_cdr_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_cdr_is_cascaded == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_cdr_l_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_cdr_m_counter == 9'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_cdr_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_cdr_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_cdr_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_cdr_ppm_driftcount == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_cdr_refclk_mux_select == UX1_CDR_REFCLK_MUX_SELECT_REGIONAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_cdr_refclk_select == UX1_CDR_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_cmn_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_core_pll == UX1_CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_core_pll_refclk_select == UX1_CORE_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_dpma_refclk_source == UX1_DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_duplex_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_enable_port_control_of_cdr_ltr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ethernet_source == UX1_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_expose_pcie_gen1_gen6_critical_signals == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_external_dpma_refclk_source == UX1_EXTERNAL_DPMA_REFCLK_SOURCE_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_flux_mode == UX1_FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_lane_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_loopback_mode == UX1_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_master_sup_mode == UX1_MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_primary_use == UX1_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ref_clk_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_rx_adapt_mode == UX1_RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_rx_bond_size == UX1_RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_rx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_rx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_rx_master_bond_chnl == UX1_RX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_rx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_rx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_rx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_rx_o_usr_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_rx_o_usr_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_rx_onchip_termination == UX1_RX_ONCHIP_TERMINATION_R_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_rx_protocol == UX1_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_rx_term_mode_select == UX1_RX_TERM_MODE_SELECT_GROUNDED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_rx_tuning_hint == UX1_RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_rx_width == UX1_RX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_rxeq_vga_gain == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_standalone_core_clk_mux == UX1_STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sup_mode == UX1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sv_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sv_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sv_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sv_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sv_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sv_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sv_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sv_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sv_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sv_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sv_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sv_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sv_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sv_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sv_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sv_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_sv_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_0_feed_forward_gain == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_0_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_fast_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_fast_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_fast_primary_use == UX1_SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_fb_div_emb_mult_counter == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_med_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_med_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_med_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_med_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_med_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_med_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_med_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_med_primary_use == UX1_SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_slow_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_slow_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_slow_primary_use == UX1_SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_syspll0_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_syspll1_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_syspll2_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_tx_bond_size == UX1_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_tx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_tx_i_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_tx_i_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_tx_i_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_tx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_tx_master_bond_chnl == UX1_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_tx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_tx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_tx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_tx_o_usr_clk_1_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_tx_o_usr_clk_1_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_tx_o_usr_clk_2_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_tx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_tx_pll == UX1_TX_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_tx_pll_bw_sel == UX1_TX_PLL_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_tx_pll_refclk_mux_select == UX1_TX_PLL_REFCLK_MUX_SELECT_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_tx_pll_refclk_select == UX1_TX_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_tx_protocol == UX1_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_tx_tuning_hint == UX1_TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_tx_user_clk1_mux == UX1_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_tx_user_clk2_mux == UX1_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_tx_user_clk_slow_med_mux == UX1_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_tx_width == UX1_TX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_txeq_main_tap == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_txrx_channel_operation == UX1_TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_txrx_line_encoding_type == UX1_TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_txrx_xcvr_speed_bucket == UX1_TXRX_XCVR_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_en_rxbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_en_rxeiosdetectstat_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_en_rxeq_clr_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_en_rxeq_precal_code_sel_lx_nt_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_en_rxeq_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_en_rxeq_static_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_en_rxeyediag_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_en_rxovrcdrlock2dataen_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_en_rxpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_en_rxrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_en_rxterm_hiz_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_en_rxwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_en_txbeacon_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_en_txbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_en_txclkdivrate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_en_txdetectrx_req_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_en_txdrv_levn_lx_5to0 == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_en_txdrv_levnm1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_en_txdrv_levnp1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_en_txdrv_levnp2_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_en_txdrv_spare_l0_1to0 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_en_txdrv_spare_l0_3to2 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_en_txdrv_spare_l0_5to4 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_en_txdrv_spare_l0_9to6 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_en_txelecidle_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_en_txpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_en_txrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_en_txwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_ovr_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_ovr_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_ovr_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_ovr_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_ovr_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_ovr_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_ovr_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_ovr_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_ovr_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_ovr_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_ovr_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_ovr_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_ovr_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_ovr_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_ovr_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_ovr_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_ur_ovr_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux1_vsr_mode == UX1_VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_cdr_bw_sel == UX2_CDR_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_cdr_f_mod_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_cdr_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_cdr_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_cdr_f_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_cdr_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_cdr_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_cdr_is_cascaded == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_cdr_l_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_cdr_m_counter == 9'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_cdr_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_cdr_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_cdr_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_cdr_ppm_driftcount == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_cdr_refclk_mux_select == UX2_CDR_REFCLK_MUX_SELECT_REGIONAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_cdr_refclk_select == UX2_CDR_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_cmn_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_core_pll == UX2_CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_core_pll_refclk_select == UX2_CORE_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_dpma_refclk_source == UX2_DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_duplex_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_enable_port_control_of_cdr_ltr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ethernet_source == UX2_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_expose_pcie_gen1_gen6_critical_signals == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_external_dpma_refclk_source == UX2_EXTERNAL_DPMA_REFCLK_SOURCE_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_flux_mode == UX2_FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_lane_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_loopback_mode == UX2_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_master_sup_mode == UX2_MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_primary_use == UX2_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ref_clk_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_rx_adapt_mode == UX2_RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_rx_bond_size == UX2_RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_rx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_rx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_rx_master_bond_chnl == UX2_RX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_rx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_rx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_rx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_rx_o_usr_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_rx_o_usr_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_rx_onchip_termination == UX2_RX_ONCHIP_TERMINATION_R_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_rx_protocol == UX2_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_rx_term_mode_select == UX2_RX_TERM_MODE_SELECT_GROUNDED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_rx_tuning_hint == UX2_RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_rx_width == UX2_RX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_rxeq_vga_gain == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_standalone_core_clk_mux == UX2_STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sup_mode == UX2_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sv_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sv_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sv_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sv_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sv_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sv_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sv_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sv_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sv_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sv_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sv_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sv_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sv_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sv_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sv_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sv_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_sv_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_0_feed_forward_gain == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_0_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_fast_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_fast_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_fast_primary_use == UX2_SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_fb_div_emb_mult_counter == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_med_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_med_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_med_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_med_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_med_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_med_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_med_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_med_primary_use == UX2_SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_slow_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_slow_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_slow_primary_use == UX2_SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_syspll0_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_syspll1_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_syspll2_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_tx_bond_size == UX2_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_tx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_tx_i_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_tx_i_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_tx_i_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_tx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_tx_master_bond_chnl == UX2_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_tx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_tx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_tx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_tx_o_usr_clk_1_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_tx_o_usr_clk_1_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_tx_o_usr_clk_2_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_tx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_tx_pll == UX2_TX_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_tx_pll_bw_sel == UX2_TX_PLL_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_tx_pll_refclk_mux_select == UX2_TX_PLL_REFCLK_MUX_SELECT_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_tx_pll_refclk_select == UX2_TX_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_tx_protocol == UX2_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_tx_tuning_hint == UX2_TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_tx_user_clk1_mux == UX2_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_tx_user_clk2_mux == UX2_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_tx_user_clk_slow_med_mux == UX2_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_tx_width == UX2_TX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_txeq_main_tap == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_txrx_channel_operation == UX2_TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_txrx_line_encoding_type == UX2_TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_txrx_xcvr_speed_bucket == UX2_TXRX_XCVR_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_en_rxbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_en_rxeiosdetectstat_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_en_rxeq_clr_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_en_rxeq_precal_code_sel_lx_nt_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_en_rxeq_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_en_rxeq_static_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_en_rxeyediag_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_en_rxovrcdrlock2dataen_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_en_rxpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_en_rxrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_en_rxterm_hiz_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_en_rxwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_en_txbeacon_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_en_txbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_en_txclkdivrate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_en_txdetectrx_req_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_en_txdrv_levn_lx_5to0 == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_en_txdrv_levnm1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_en_txdrv_levnp1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_en_txdrv_levnp2_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_en_txdrv_spare_l0_1to0 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_en_txdrv_spare_l0_3to2 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_en_txdrv_spare_l0_5to4 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_en_txdrv_spare_l0_9to6 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_en_txelecidle_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_en_txpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_en_txrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_en_txwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_ovr_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_ovr_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_ovr_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_ovr_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_ovr_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_ovr_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_ovr_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_ovr_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_ovr_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_ovr_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_ovr_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_ovr_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_ovr_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_ovr_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_ovr_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_ovr_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_ur_ovr_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux2_vsr_mode == UX2_VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_cdr_bw_sel == UX3_CDR_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_cdr_f_mod_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_cdr_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_cdr_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_cdr_f_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_cdr_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_cdr_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_cdr_is_cascaded == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_cdr_l_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_cdr_m_counter == 9'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_cdr_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_cdr_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_cdr_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_cdr_ppm_driftcount == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_cdr_refclk_mux_select == UX3_CDR_REFCLK_MUX_SELECT_REGIONAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_cdr_refclk_select == UX3_CDR_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_cmn_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_core_pll == UX3_CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_core_pll_refclk_select == UX3_CORE_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_dpma_refclk_source == UX3_DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_duplex_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_enable_port_control_of_cdr_ltr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ethernet_source == UX3_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_expose_pcie_gen1_gen6_critical_signals == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_external_dpma_refclk_source == UX3_EXTERNAL_DPMA_REFCLK_SOURCE_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_flux_mode == UX3_FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_lane_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_loopback_mode == UX3_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_master_sup_mode == UX3_MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_primary_use == UX3_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ref_clk_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_rx_adapt_mode == UX3_RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_rx_bond_size == UX3_RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_rx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_rx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_rx_master_bond_chnl == UX3_RX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_rx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_rx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_rx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_rx_o_usr_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_rx_o_usr_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_rx_onchip_termination == UX3_RX_ONCHIP_TERMINATION_R_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_rx_protocol == UX3_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_rx_term_mode_select == UX3_RX_TERM_MODE_SELECT_GROUNDED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_rx_tuning_hint == UX3_RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_rx_width == UX3_RX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_rxeq_vga_gain == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_standalone_core_clk_mux == UX3_STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sup_mode == UX3_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sv_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sv_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sv_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sv_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sv_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sv_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sv_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sv_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sv_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sv_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sv_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sv_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sv_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sv_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sv_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sv_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_sv_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_0_feed_forward_gain == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_0_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_fast_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_fast_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_fast_primary_use == UX3_SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_fb_div_emb_mult_counter == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_med_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_med_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_med_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_med_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_med_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_med_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_med_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_med_primary_use == UX3_SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_slow_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_slow_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_slow_primary_use == UX3_SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_syspll0_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_syspll1_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_syspll2_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_tx_bond_size == UX3_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_tx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_tx_i_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_tx_i_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_tx_i_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_tx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_tx_master_bond_chnl == UX3_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_tx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_tx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_tx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_tx_o_usr_clk_1_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_tx_o_usr_clk_1_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_tx_o_usr_clk_2_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_tx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_tx_pll == UX3_TX_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_tx_pll_bw_sel == UX3_TX_PLL_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_tx_pll_refclk_mux_select == UX3_TX_PLL_REFCLK_MUX_SELECT_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_tx_pll_refclk_select == UX3_TX_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_tx_protocol == UX3_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_tx_tuning_hint == UX3_TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_tx_user_clk1_mux == UX3_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_tx_user_clk2_mux == UX3_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_tx_user_clk_slow_med_mux == UX3_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_tx_width == UX3_TX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_txeq_main_tap == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_txrx_channel_operation == UX3_TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_txrx_line_encoding_type == UX3_TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_txrx_xcvr_speed_bucket == UX3_TXRX_XCVR_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_en_rxbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_en_rxeiosdetectstat_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_en_rxeq_clr_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_en_rxeq_precal_code_sel_lx_nt_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_en_rxeq_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_en_rxeq_static_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_en_rxeyediag_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_en_rxovrcdrlock2dataen_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_en_rxpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_en_rxrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_en_rxterm_hiz_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_en_rxwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_en_txbeacon_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_en_txbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_en_txclkdivrate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_en_txdetectrx_req_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_en_txdrv_levn_lx_5to0 == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_en_txdrv_levnm1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_en_txdrv_levnp1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_en_txdrv_levnp2_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_en_txdrv_spare_l0_1to0 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_en_txdrv_spare_l0_3to2 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_en_txdrv_spare_l0_5to4 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_en_txdrv_spare_l0_9to6 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_en_txelecidle_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_en_txpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_en_txrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_en_txwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_ovr_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_ovr_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_ovr_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_ovr_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_ovr_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_ovr_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_ovr_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_ovr_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_ovr_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_ovr_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_ovr_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_ovr_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_ovr_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_ovr_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_ovr_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_ovr_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_ur_ovr_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux3_vsr_mode == UX3_VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_PCSREF_L0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_PCSREF_L0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux_q_ckmux_cpu_attr == CKMUX_CPU_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux_q_i_pll0_hz == 36'd250000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux_q_i_pll1_hz == 36'd250000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux_q_i_pll2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux_quad_instance == UX_QUAD_INSTANCE_THREE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.ux_speed_grade == UX_SPEED_GRADE_DASH2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.all_ux_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.bot_f_fastest_reconfig_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.bot_refclk_reconfig_span == BOT_REFCLK_RECONFIG_SPAN_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.bot_syspll_refclk_output_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.cdrdiv_offchip_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ch1_ch0_master_pll_pair_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ch3_ch2_master_pll_pair_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.clkrx_bot_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.clkrx_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.clkrx_top_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_bot_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_bot_syspll_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_ch1_ch0_master_pll_pair_cascade_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_ch3_ch2_master_pll_pair_cascade_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_fastest_reconfig_refclk_global_refclk_0_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_fastest_reconfig_refclk_global_refclk_1_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_fastest_reconfig_refclk_global_refclk_2_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_fastest_reconfig_refclk_global_refclk_3_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_fastest_reconfig_refclk_regional_refclk_0_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_fastest_reconfig_refclk_regional_refclk_1_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_full_quad_master_pll_cascade_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_global_refclk_0_bot_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_global_refclk_0_bot_right_top_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_global_refclk_0_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_global_refclk_0_top_right_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_global_refclk_1_bot_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_global_refclk_1_bot_right_top_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_global_refclk_1_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_global_refclk_1_top_right_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_global_refclk_2_bot_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_global_refclk_2_bot_right_top_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_global_refclk_2_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_global_refclk_2_top_right_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_global_refclk_3_bot_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_global_refclk_3_bot_right_top_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_global_refclk_3_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_global_refclk_3_top_right_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_local_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_regional_refclk_0_bot_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_regional_refclk_0_bot_right_top_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_regional_refclk_0_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_regional_refclk_0_top_right_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_regional_refclk_1_bot_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_regional_refclk_1_bot_right_top_left_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_regional_refclk_1_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_regional_refclk_1_top_right_hz == 40'd800000001
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_regional_refclk_2_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_regional_refclk_3_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_top_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.f_top_syspll_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.fabric_iram_fabric_iram_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.global_refclk_0_bot_control == GLOBAL_REFCLK_0_BOT_CONTROL_ENABLE_T2R_B2L_NO_PASS_THRU
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.global_refclk_0_bot_power_mode == GLOBAL_REFCLK_0_BOT_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.global_refclk_0_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.global_refclk_0_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.global_refclk_0_top_control == GLOBAL_REFCLK_0_TOP_CONTROL_ENABLE_T2R_B2L_NO_PASS_THRU
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.global_refclk_0_top_power_mode == GLOBAL_REFCLK_0_TOP_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.global_refclk_1_bot_control == GLOBAL_REFCLK_1_BOT_CONTROL_ENABLE_T2R_B2L_NO_PASS_THRU
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.global_refclk_1_bot_power_mode == GLOBAL_REFCLK_1_BOT_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.global_refclk_1_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.global_refclk_1_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.global_refclk_1_top_control == GLOBAL_REFCLK_1_TOP_CONTROL_ENABLE_T2R_B2L_NO_PASS_THRU
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.global_refclk_1_top_power_mode == GLOBAL_REFCLK_1_TOP_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.global_refclk_2_bot_control == GLOBAL_REFCLK_2_BOT_CONTROL_ENABLE_T2R_B2L_NO_PASS_THRU
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.global_refclk_2_bot_power_mode == GLOBAL_REFCLK_2_BOT_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.global_refclk_2_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.global_refclk_2_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.global_refclk_2_top_control == GLOBAL_REFCLK_2_TOP_CONTROL_ENABLE_T2R_B2L_NO_PASS_THRU
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.global_refclk_2_top_power_mode == GLOBAL_REFCLK_2_TOP_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.global_refclk_3_bot_control == GLOBAL_REFCLK_3_BOT_CONTROL_ENABLE_T2R_B2L_NO_PASS_THRU
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.global_refclk_3_bot_power_mode == GLOBAL_REFCLK_3_BOT_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.global_refclk_3_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.global_refclk_3_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.global_refclk_3_top_control == GLOBAL_REFCLK_3_TOP_CONTROL_ENABLE_T2R_B2L_NO_PASS_THRU
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.global_refclk_3_top_power_mode == GLOBAL_REFCLK_3_TOP_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.hard_all_ux_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.local_clock_line_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.quad_global_refclk_0_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.quad_global_refclk_1_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.quad_global_refclk_2_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.quad_global_refclk_3_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.quad_regional_refclk_0_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.quad_regional_refclk_1_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.regional_refclk_0_bot_control == REGIONAL_REFCLK_0_BOT_CONTROL_ENABLE_T2R_B2L_NO_PASS_THRU
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.regional_refclk_0_bot_power_mode == REGIONAL_REFCLK_0_BOT_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.regional_refclk_0_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.regional_refclk_0_right_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.regional_refclk_0_top_control == REGIONAL_REFCLK_0_TOP_CONTROL_ENABLE_T2R_B2L_NO_PASS_THRU
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.regional_refclk_0_top_power_mode == REGIONAL_REFCLK_0_TOP_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.regional_refclk_1_bot_control == REGIONAL_REFCLK_1_BOT_CONTROL_ENABLE_T2R_B2L_NO_PASS_THRU
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.regional_refclk_1_bot_power_mode == REGIONAL_REFCLK_1_BOT_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.regional_refclk_1_left_adjacent_active == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.regional_refclk_1_right_adjacent_active == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.regional_refclk_1_top_control == REGIONAL_REFCLK_1_TOP_CONTROL_ENABLE_P2R_R2T
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.regional_refclk_1_top_power_mode == REGIONAL_REFCLK_1_TOP_POWER_MODE_LOW_POWER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_fw_loader_cfg_data_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_fw_loader_cfg_fw_loader_en_attr == SCMNG_FW_LOADER_CFG_FW_LOADER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_fw_loader_cfg_offset_addr_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_fw_loader_cfg_single_mode_en_attr == SCMNG_FW_LOADER_CFG_SINGLE_MODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_ahb_non_posted_write_attr == SCMNG_PM_CFG_AHB_NON_POSTED_WRITE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_an_done_lane0_attr == SCMNG_PM_CFG_AN_DONE_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_an_done_lane1_attr == SCMNG_PM_CFG_AN_DONE_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_an_done_lane2_attr == SCMNG_PM_CFG_AN_DONE_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_an_done_lane3_attr == SCMNG_PM_CFG_AN_DONE_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_apb_broadcast_feature_en_attr == SCMNG_PM_CFG_APB_BROADCAST_FEATURE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_apb_broadcast_type_attr == SCMNG_PM_CFG_APB_BROADCAST_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_apb_security_check_en_attr == SCMNG_PM_CFG_APB_SECURITY_CHECK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_cfg_top_head_visactl0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_cfg_top_head_visactl1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_cfg_top_head_visactl2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_cfg_top_head_visactl3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_cfg_top_head_visaenable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_cpi_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_cpi_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_cpi_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_ecc_double_attr == SCMNG_PM_CFG_ECC_DOUBLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_error_l0_attr == SCMNG_PM_CFG_ERROR_L0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_error_l1_attr == SCMNG_PM_CFG_ERROR_L1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_error_l2_attr == SCMNG_PM_CFG_ERROR_L2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_error_l3_attr == SCMNG_PM_CFG_ERROR_L3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_fabric_wd_counter_max_attr == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_link_mng_cpi_cmd_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_link_mng_cpi_data_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_one_bit_error_corrected_attr == SCMNG_PM_CFG_ONE_BIT_ERROR_CORRECTED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_phy_cpi_cmd_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_phy_cpi_data_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_phy_owner_cpi_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_probe_addr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_rx_ready_lane0_attr == SCMNG_PM_CFG_RX_READY_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_rx_ready_lane1_attr == SCMNG_PM_CFG_RX_READY_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_rx_ready_lane2_attr == SCMNG_PM_CFG_RX_READY_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_rx_ready_lane3_attr == SCMNG_PM_CFG_RX_READY_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_sw_reserved_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_trn_done_lane0_attr == SCMNG_PM_CFG_TRN_DONE_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_trn_done_lane1_attr == SCMNG_PM_CFG_TRN_DONE_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_trn_done_lane2_attr == SCMNG_PM_CFG_TRN_DONE_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_trn_done_lane3_attr == SCMNG_PM_CFG_TRN_DONE_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_tx_ready_lane0_attr == SCMNG_PM_CFG_TX_READY_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_tx_ready_lane1_attr == SCMNG_PM_CFG_TX_READY_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_tx_ready_lane2_attr == SCMNG_PM_CFG_TX_READY_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_tx_ready_lane3_attr == SCMNG_PM_CFG_TX_READY_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_visa_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_visa_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.scmng_pm_cfg_visa_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_aon_cfg_ckgate_disable_attr == SERDES_IP_CLKRX_BOT_AON_CFG_CKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_aon_cfg_cmn_powerup_attr == SERDES_IP_CLKRX_BOT_AON_CFG_CMN_POWERUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_aon_cfg_cmn_powerup_override_en_attr == SERDES_IP_CLKRX_BOT_AON_CFG_CMN_POWERUP_OVERRIDE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_aon_cfg_cmntstbus_addr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_aon_cfg_synth_force_pup_attr == SERDES_IP_CLKRX_BOT_AON_CFG_SYNTH_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_aon_cfg_synth_force_pup_en_attr == SERDES_IP_CLKRX_BOT_AON_CFG_SYNTH_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_aprobe_bot_en_attr == SERDES_IP_CLKRX_BOT_CFG_APROBE_BOT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_aprobe_left_en_attr == SERDES_IP_CLKRX_BOT_CFG_APROBE_LEFT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_aprobe_right_en_attr == SERDES_IP_CLKRX_BOT_CFG_APROBE_RIGHT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_aprobe_top_en_attr == SERDES_IP_CLKRX_BOT_CFG_APROBE_TOP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmn_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmn_pg_disable_attr == SERDES_IP_CLKRX_BOT_CFG_CMN_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmn_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnaprobeclkrx_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnbs_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnbshihyst_attr == SERDES_IP_CLKRX_BOT_CFG_CMNBSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalptr_pstate_refckregopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalptr_pstate_swfabricregopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalptr_quad_refckregopampoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalptr_quad_swfabricregopampoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffset_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREFCKREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffsetfsm_clear_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREFCKREGOPAMPOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffsetfsm_init_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREFCKREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffsetfsm_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREFCKREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffsetfsm_req_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREFCKREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREFCKREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffsetfsmout_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREFCKREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffsetmeas_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREFCKREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalrefckregopampoffsetmeas_req_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREFCKREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_finish_side_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_invert_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_round_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_runcount_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetfsm_signmagen_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetmeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalregopampoffsetmeas_validdlycount_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffset_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALSWFABRICREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffsetfsm_clear_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffsetfsm_init_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffsetfsm_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffsetfsm_req_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffsetfsmout_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffsetmeas_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALSWFABRICREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmncalswfabricregopampoffsetmeas_req_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCALSWFABRICREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrx_bypass_en_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRX_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxcdrdiv_bot_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXCDRDIV_BOT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxcdrdiv_input_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxcdrdiv_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXCDRDIV_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxcdrdiv_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXCDRDIV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxcdrdiv_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXCDRDIV_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxcdrdiv_top_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXCDRDIV_TOP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbuf_buf2dpma_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXREFCKBUF_BUF2DPMA_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbuf_cml_ena_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXREFCKBUF_CML_ENA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbuf_core_cmos_ena_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXREFCKBUF_CORE_CMOS_ENA_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbuf_hs_cmos_ena_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXREFCKBUF_HS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbuf_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXREFCKBUF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbuf_powersave_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXREFCKBUF_POWERSAVE_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbuf_termcal_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbuf_termhiz_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXREFCKBUF_TERMHIZ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbufsel_hs_ls_b_path_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXREFCKBUFSEL_HS_LS_B_PATH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxrefckbufsel_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXREFCKBUFSEL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxspare_attr == 16'd61440
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxsynthdiv_bot_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXSYNTHDIV_BOT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxsynthdiv_input_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxsynthdiv_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXSYNTHDIV_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxsynthdiv_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXSYNTHDIV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxsynthdiv_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXSYNTHDIV_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnclkrxsynthdiv_top_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNCLKRXSYNTHDIV_TOP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmndprobe_addr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnfsm_cken_ovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnfsm_cken_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_changeref_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_REFCK_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_changeref_val_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_REFCK_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_en_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_REFCK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refck_smpltime_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refckm_charge_up_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_REFCKM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refckm_pull_dn_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_REFCKM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refckm_sense_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_REFCKM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refckp_charge_up_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_REFCKP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refckp_pull_dn_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_REFCKP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnntl_refckp_sense_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNNTL_REFCKP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_cdrdivsel_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_hsrefsel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_hsrefsel_powersave_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_HSREFSEL_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_lcrefsel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_lcrefsel_powersave_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_LCREFSEL_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_pad2cmos_ana_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_PAD2CMOS_ANA_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_pad2cmos_dig_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_PAD2CMOS_DIG_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel0_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel0_powersave_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_REFSEL0_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel1_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel1_powersave_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_REFSEL1_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel2_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel2_powersave_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_REFSEL2_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel3_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel3_powersave_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_REFSEL3_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel4_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel4_powersave_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_REFSEL4_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel5_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_refsel5_powersave_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_REFSEL5_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_synthdivsel_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnref_termhiz_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREF_TERMHIZ_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrefckctrl_auto_powerdown_en_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREFCKCTRL_AUTO_POWERDOWN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrefckctrl_cml_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREFCKCTRL_CML_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrefckctrl_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNREFCKCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrefckreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s0q0_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s0q1_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s0q2_attr == 10'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s0q3_attr == 10'd250
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s0q4_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s0q5_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s0q6_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s0q7_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s1q0_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s1q1_attr == 10'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s1q2_attr == 10'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s1q3_attr == 10'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s1q4_attr == 10'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s1q5_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s1q6_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s1q7_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s2q0_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s2q1_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s2q2_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s2q3_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s2q4_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s2q5_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s2q6_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_delay_s2q7_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpu_en_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_dn_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_up_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_up_ptr1_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_refckregpwrupacc_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_dn_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_up_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_up_ptr1_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpuetr_swfabricregpwrupacc_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckbuf_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_refckreg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabric_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpupd_swfabricreg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_refckregreset_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrpurst_swfabricregreset_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_aetrcmn_refckregpwrupacc_ovr_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_AETRCMN_REFCKREGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_aetrcmn_refckregpwrupacc_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_AETRCMN_REFCKREGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_aetrcmn_swfabricregpwrupacc_ovr_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_AETRCMN_SWFABRICREGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_aetrcmn_swfabricregpwrupacc_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_AETRCMN_SWFABRICREGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdcmn_refckbuf_ovr_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdcmn_refckbuf_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdcmn_refckreg_ovr_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDCMN_REFCKREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdcmn_refckreg_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDCMN_REFCKREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdcmn_swfabric_ovr_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDCMN_SWFABRIC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdcmn_swfabric_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDCMN_SWFABRIC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdcmn_swfabricreg_ovr_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDCMN_SWFABRICREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdcmn_swfabricreg_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDCMN_SWFABRICREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdrefck_ntl_b_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDREFCK_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_apdrefck_ntl_ovr_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_APDREFCK_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_arstcmn_refckregreset_ovr_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_ARSTCMN_REFCKREGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_arstcmn_refckregreset_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_ARSTCMN_REFCKREGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_arstcmn_swfabricregreset_ovr_b_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_ARSTCMN_SWFABRICREGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnrstpdovr_arstcmn_swfabricregreset_ovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNRSTPDOVR_ARSTCMN_SWFABRICREGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_locovren_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref0_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF0_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref0_powersave_b_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF0_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref0_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF0_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref0_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref1_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF1_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref1_powersave_b_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF1_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref1_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF1_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref1_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref2_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF2_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref2_powersave_b_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF2_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref2_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF2_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref2_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref3_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF3_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref3_powersave_b_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF3_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref3_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF3_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref3_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref4_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF4_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref4_powersave_b_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF4_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref4_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF4_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref4_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref5_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF5_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref5_powersave_b_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF5_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref5_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF5_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref5_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref6_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF6_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref6_powersave_b_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF6_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref6_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF6_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref6_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref7_left_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF7_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref7_powersave_b_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF7_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref7_right_en_locovr_attr == SERDES_IP_CLKRX_BOT_CFG_CMNSWFABRIC_REF7_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabric_ref7_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_cfg_cmnswfabricreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_egress_override_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_EGRESS_OVERRIDE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_egress_override_val_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_p_vdd_pwrgood_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_P_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_p_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_P_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_pa_vdd_ehv_pwrgood_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_pa_vdd_ehv_pwrgood_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_pa_vdd_pwrgood_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_PA_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_pa_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_PA_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_burnin_mode_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_BURNIN_MODE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_burnin_mode_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_BURNIN_MODE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_cdrdivsel_nt_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_cdrdivsel_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_CDRDIVSEL_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_cmnclkrxrefckbufsel_hs_ls_b_path_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_CMNCLKRXREFCKBUFSEL_HS_LS_B_PATH_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_cmnclkrxrefckbufsel_hs_ls_b_path_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_CMNCLKRXREFCKBUFSEL_HS_LS_B_PATH_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_hsrefsel_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_hsrefsel_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_HSREFSEL_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_hsrefsel_powersave_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_HSREFSEL_POWERSAVE_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_hsrefsel_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_HSREFSEL_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_jtagid_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_JTAGID_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_jtagslvid_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_JTAGSLVID_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_pad2cmos_ana_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_PAD2CMOS_ANA_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_pad2cmos_ana_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_PAD2CMOS_ANA_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_pad2cmos_dig_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_PAD2CMOS_DIG_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_pad2cmos_dig_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_PAD2CMOS_DIG_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_powerup_a_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_POWERUP_A_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_powerup_a_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_POWERUP_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel0_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel0_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel0_powersave_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL0_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel0_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL0_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel1_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel1_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL1_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel1_powersave_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL1_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel1_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL1_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel2_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel2_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL2_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel2_powersave_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL2_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel2_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL2_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel3_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel3_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL3_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel3_powersave_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL3_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel3_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL3_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel4_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel4_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL4_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel4_powersave_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL4_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel4_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL4_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel5_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel5_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL5_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel5_powersave_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL5_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_refsel5_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_REFSEL5_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_synthdivsel_nt_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_synthdivsel_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_SYNTHDIVSEL_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_termhiz_en_nt_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_TERMHIZ_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_termhiz_en_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_TERMHIZ_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_vdd_ehv_sel_nt_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_ref_vdd_ehv_sel_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_REF_VDD_EHV_SEL_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_spare_nt_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_ictl_spare_nt_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_ICTL_SPARE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_idat_txbscan_n_attr == SERDES_IP_CLKRX_BOT_IF_CFG_IDAT_TXBSCAN_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_idat_txbscan_n_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_IDAT_TXBSCAN_N_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_idat_txbscan_p_attr == SERDES_IP_CLKRX_BOT_IF_CFG_IDAT_TXBSCAN_P_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_idat_txbscan_p_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_IDAT_TXBSCAN_P_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_irst_ref_por_b_a_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_IRST_REF_POR_B_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_irst_ref_tstbus_b_a_attr == SERDES_IP_CLKRX_BOT_IF_CFG_IRST_REF_TSTBUS_B_A_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_bot_if_cfg_irst_ref_tstbus_b_a_reg_en_attr == SERDES_IP_CLKRX_BOT_IF_CFG_IRST_REF_TSTBUS_B_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_aon_cfg_ckgate_disable_attr == SERDES_IP_CLKRX_TOP_AON_CFG_CKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_aon_cfg_cmn_powerup_attr == SERDES_IP_CLKRX_TOP_AON_CFG_CMN_POWERUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_aon_cfg_cmn_powerup_override_en_attr == SERDES_IP_CLKRX_TOP_AON_CFG_CMN_POWERUP_OVERRIDE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_aon_cfg_cmntstbus_addr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_aon_cfg_synth_force_pup_attr == SERDES_IP_CLKRX_TOP_AON_CFG_SYNTH_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_aon_cfg_synth_force_pup_en_attr == SERDES_IP_CLKRX_TOP_AON_CFG_SYNTH_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_aprobe_bot_en_attr == SERDES_IP_CLKRX_TOP_CFG_APROBE_BOT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_aprobe_left_en_attr == SERDES_IP_CLKRX_TOP_CFG_APROBE_LEFT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_aprobe_right_en_attr == SERDES_IP_CLKRX_TOP_CFG_APROBE_RIGHT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_aprobe_top_en_attr == SERDES_IP_CLKRX_TOP_CFG_APROBE_TOP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmn_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmn_pg_disable_attr == SERDES_IP_CLKRX_TOP_CFG_CMN_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmn_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnaprobeclkrx_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnbs_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnbshihyst_attr == SERDES_IP_CLKRX_TOP_CFG_CMNBSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalptr_pstate_refckregopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalptr_pstate_swfabricregopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalptr_quad_refckregopampoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalptr_quad_swfabricregopampoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffset_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREFCKREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffsetfsm_clear_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREFCKREGOPAMPOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffsetfsm_init_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREFCKREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffsetfsm_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREFCKREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffsetfsm_req_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREFCKREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREFCKREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffsetfsmout_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREFCKREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffsetmeas_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREFCKREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalrefckregopampoffsetmeas_req_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREFCKREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_finish_side_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_invert_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_round_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_runcount_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetfsm_signmagen_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetmeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalregopampoffsetmeas_validdlycount_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffset_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALSWFABRICREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffsetfsm_clear_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffsetfsm_init_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffsetfsm_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffsetfsm_req_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffsetfsmout_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALSWFABRICREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffsetmeas_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALSWFABRICREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmncalswfabricregopampoffsetmeas_req_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCALSWFABRICREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrx_bypass_en_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRX_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxcdrdiv_bot_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXCDRDIV_BOT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxcdrdiv_input_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxcdrdiv_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXCDRDIV_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxcdrdiv_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXCDRDIV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxcdrdiv_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXCDRDIV_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxcdrdiv_top_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXCDRDIV_TOP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbuf_buf2dpma_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXREFCKBUF_BUF2DPMA_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbuf_cml_ena_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXREFCKBUF_CML_ENA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbuf_core_cmos_ena_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXREFCKBUF_CORE_CMOS_ENA_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbuf_hs_cmos_ena_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXREFCKBUF_HS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbuf_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXREFCKBUF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbuf_powersave_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXREFCKBUF_POWERSAVE_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbuf_termcal_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbuf_termhiz_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXREFCKBUF_TERMHIZ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbufsel_hs_ls_b_path_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXREFCKBUFSEL_HS_LS_B_PATH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxrefckbufsel_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXREFCKBUFSEL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxspare_attr == 16'd61440
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxsynthdiv_bot_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXSYNTHDIV_BOT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxsynthdiv_input_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxsynthdiv_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXSYNTHDIV_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxsynthdiv_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXSYNTHDIV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxsynthdiv_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXSYNTHDIV_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnclkrxsynthdiv_top_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNCLKRXSYNTHDIV_TOP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmndprobe_addr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnfsm_cken_ovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnfsm_cken_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_changeref_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_REFCK_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_changeref_val_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_REFCK_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_en_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_REFCK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refck_smpltime_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refckm_charge_up_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_REFCKM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refckm_pull_dn_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_REFCKM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refckm_sense_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_REFCKM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refckp_charge_up_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_REFCKP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refckp_pull_dn_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_REFCKP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnntl_refckp_sense_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNNTL_REFCKP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnref_cdrdivsel_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnref_hsrefsel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnref_hsrefsel_powersave_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_HSREFSEL_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnref_lcrefsel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnref_lcrefsel_powersave_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_LCREFSEL_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnref_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnref_pad2cmos_ana_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_PAD2CMOS_ANA_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnref_pad2cmos_dig_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_PAD2CMOS_DIG_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel0_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel0_powersave_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_REFSEL0_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel1_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel1_powersave_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_REFSEL1_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel2_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel2_powersave_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_REFSEL2_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel3_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel3_powersave_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_REFSEL3_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel4_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel4_powersave_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_REFSEL4_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel5_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnref_refsel5_powersave_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_REFSEL5_POWERSAVE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnref_synthdivsel_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnref_termhiz_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREF_TERMHIZ_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrefckctrl_auto_powerdown_en_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREFCKCTRL_AUTO_POWERDOWN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrefckctrl_cml_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREFCKCTRL_CML_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrefckctrl_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNREFCKCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrefckreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s0q0_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s0q1_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s0q2_attr == 10'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s0q3_attr == 10'd250
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s0q4_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s0q5_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s0q6_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s0q7_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s1q0_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s1q1_attr == 10'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s1q2_attr == 10'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s1q3_attr == 10'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s1q4_attr == 10'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s1q5_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s1q6_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s1q7_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s2q0_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s2q1_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s2q2_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s2q3_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s2q4_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s2q5_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s2q6_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_delay_s2q7_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpu_en_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_dn_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_up_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_up_ptr1_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_refckregpwrupacc_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_dn_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_up_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_up_ptr1_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpuetr_swfabricregpwrupacc_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckbuf_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_refckreg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabric_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpupd_swfabricreg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_refckregreset_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrpurst_swfabricregreset_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_aetrcmn_refckregpwrupacc_ovr_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_AETRCMN_REFCKREGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_aetrcmn_refckregpwrupacc_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_AETRCMN_REFCKREGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_aetrcmn_swfabricregpwrupacc_ovr_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_AETRCMN_SWFABRICREGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_aetrcmn_swfabricregpwrupacc_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_AETRCMN_SWFABRICREGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdcmn_refckbuf_ovr_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdcmn_refckbuf_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdcmn_refckreg_ovr_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDCMN_REFCKREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdcmn_refckreg_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDCMN_REFCKREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdcmn_swfabric_ovr_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDCMN_SWFABRIC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdcmn_swfabric_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDCMN_SWFABRIC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdcmn_swfabricreg_ovr_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDCMN_SWFABRICREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdcmn_swfabricreg_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDCMN_SWFABRICREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdrefck_ntl_b_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDREFCK_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_apdrefck_ntl_ovr_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_APDREFCK_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_arstcmn_refckregreset_ovr_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_ARSTCMN_REFCKREGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_arstcmn_refckregreset_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_ARSTCMN_REFCKREGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_arstcmn_swfabricregreset_ovr_b_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_ARSTCMN_SWFABRICREGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnrstpdovr_arstcmn_swfabricregreset_ovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNRSTPDOVR_ARSTCMN_SWFABRICREGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_locovren_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref0_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF0_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref0_powersave_b_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF0_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref0_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF0_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref0_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref1_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF1_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref1_powersave_b_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF1_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref1_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF1_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref1_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref2_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF2_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref2_powersave_b_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF2_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref2_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF2_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref2_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref3_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF3_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref3_powersave_b_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF3_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref3_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF3_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref3_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref4_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF4_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref4_powersave_b_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF4_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref4_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF4_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref4_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref5_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF5_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref5_powersave_b_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF5_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref5_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF5_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref5_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref6_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF6_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref6_powersave_b_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF6_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref6_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF6_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref6_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref7_left_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF7_LEFT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref7_powersave_b_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF7_POWERSAVE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref7_right_en_locovr_attr == SERDES_IP_CLKRX_TOP_CFG_CMNSWFABRIC_REF7_RIGHT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabric_ref7_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_cfg_cmnswfabricreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_egress_override_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_EGRESS_OVERRIDE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_egress_override_val_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_p_vdd_pwrgood_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_P_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_p_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_P_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_pa_vdd_ehv_pwrgood_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_pa_vdd_ehv_pwrgood_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_pa_vdd_pwrgood_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_PA_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_pa_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_PA_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_burnin_mode_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_BURNIN_MODE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_burnin_mode_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_BURNIN_MODE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_cdrdivsel_nt_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_cdrdivsel_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_CDRDIVSEL_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_cmnclkrxrefckbufsel_hs_ls_b_path_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_CMNCLKRXREFCKBUFSEL_HS_LS_B_PATH_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_cmnclkrxrefckbufsel_hs_ls_b_path_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_CMNCLKRXREFCKBUFSEL_HS_LS_B_PATH_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_hsrefsel_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_hsrefsel_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_HSREFSEL_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_hsrefsel_powersave_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_HSREFSEL_POWERSAVE_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_hsrefsel_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_HSREFSEL_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_jtagid_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_JTAGID_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_jtagslvid_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_JTAGSLVID_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_pad2cmos_ana_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_PAD2CMOS_ANA_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_pad2cmos_ana_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_PAD2CMOS_ANA_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_pad2cmos_dig_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_PAD2CMOS_DIG_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_pad2cmos_dig_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_PAD2CMOS_DIG_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_powerup_a_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_POWERUP_A_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_powerup_a_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_POWERUP_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel0_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel0_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel0_powersave_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL0_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel0_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL0_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel1_nt_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel1_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL1_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel1_powersave_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL1_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel1_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL1_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel2_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel2_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL2_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel2_powersave_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL2_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel2_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL2_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel3_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel3_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL3_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel3_powersave_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL3_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel3_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL3_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel4_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel4_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL4_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel4_powersave_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL4_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel4_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL4_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel5_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel5_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL5_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel5_powersave_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL5_POWERSAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_refsel5_powersave_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_REFSEL5_POWERSAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_synthdivsel_nt_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_synthdivsel_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_SYNTHDIVSEL_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_termhiz_en_nt_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_TERMHIZ_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_termhiz_en_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_TERMHIZ_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_vdd_ehv_sel_nt_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_ref_vdd_ehv_sel_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_REF_VDD_EHV_SEL_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_spare_nt_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_ictl_spare_nt_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_ICTL_SPARE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_idat_txbscan_n_attr == SERDES_IP_CLKRX_TOP_IF_CFG_IDAT_TXBSCAN_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_idat_txbscan_n_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_IDAT_TXBSCAN_N_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_idat_txbscan_p_attr == SERDES_IP_CLKRX_TOP_IF_CFG_IDAT_TXBSCAN_P_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_idat_txbscan_p_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_IDAT_TXBSCAN_P_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_irst_ref_por_b_a_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_IRST_REF_POR_B_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_irst_ref_tstbus_b_a_attr == SERDES_IP_CLKRX_TOP_IF_CFG_IRST_REF_TSTBUS_B_A_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_clkrx_top_if_cfg_irst_ref_tstbus_b_a_reg_en_attr == SERDES_IP_CLKRX_TOP_IF_CFG_IRST_REF_TSTBUS_B_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l0_cfg_ckgate_disable_attr == SERDES_IP_CMN_AON_L0_CFG_CKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l0_cfg_cmn_force_pup_attr == SERDES_IP_CMN_AON_L0_CFG_CMN_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l0_cfg_cmn_force_pup_en_attr == SERDES_IP_CMN_AON_L0_CFG_CMN_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l0_cfg_cmn_rst_b_attr == SERDES_IP_CMN_AON_L0_CFG_CMN_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l0_cfg_cmn_rst_en_attr == SERDES_IP_CMN_AON_L0_CFG_CMN_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l0_cfg_cmnclk_ctrl_attr == SERDES_IP_CMN_AON_L0_CFG_CMNCLK_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l0_cfg_cmnclkdiv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l0_cfg_cmnfsm_pmu_req_attr == SERDES_IP_CMN_AON_L0_CFG_CMNFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l0_cfg_cmnfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L0_CFG_CMNFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l0_cfg_cmntstbus_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcfast_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcfast_force_pup_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCFAST_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcfast_force_pup_en_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCFAST_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcfast_ignore_mode_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCFAST_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcfast_rst_b_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCFAST_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcfast_rst_en_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCFAST_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcfastfsm_pmu_req_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCFASTFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcfastfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCFASTFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcmed_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcmed_force_pup_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCMED_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcmed_force_pup_en_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCMED_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcmed_ignore_mode_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCMED_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcmed_rst_b_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCMED_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcmed_rst_en_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCMED_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcmedfsm_pmu_req_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCMEDFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcmedfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCMEDFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcslow_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcslow_force_pup_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCSLOW_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcslow_force_pup_en_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCSLOW_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcslow_ignore_mode_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCSLOW_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcslow_rst_b_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCSLOW_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcslow_rst_en_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCSLOW_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcslowfsm_pmu_req_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCSLOWFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l0_cfg_synthlcslowfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L0_CFG_SYNTHLCSLOWFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l0_cfg_tstbus_rst_bypass_attr == SERDES_IP_CMN_AON_L0_CFG_TSTBUS_RST_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l0_cfg_tstbus_rst_bypass_en_attr == SERDES_IP_CMN_AON_L0_CFG_TSTBUS_RST_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l1_cfg_ckgate_disable_attr == SERDES_IP_CMN_AON_L1_CFG_CKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l1_cfg_cmn_force_pup_attr == SERDES_IP_CMN_AON_L1_CFG_CMN_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l1_cfg_cmn_force_pup_en_attr == SERDES_IP_CMN_AON_L1_CFG_CMN_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l1_cfg_cmn_rst_b_attr == SERDES_IP_CMN_AON_L1_CFG_CMN_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l1_cfg_cmn_rst_en_attr == SERDES_IP_CMN_AON_L1_CFG_CMN_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l1_cfg_cmnclk_ctrl_attr == SERDES_IP_CMN_AON_L1_CFG_CMNCLK_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l1_cfg_cmnclkdiv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l1_cfg_cmnfsm_pmu_req_attr == SERDES_IP_CMN_AON_L1_CFG_CMNFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l1_cfg_cmnfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L1_CFG_CMNFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l1_cfg_cmntstbus_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcfast_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcfast_force_pup_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCFAST_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcfast_force_pup_en_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCFAST_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcfast_ignore_mode_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCFAST_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcfast_rst_b_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCFAST_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcfast_rst_en_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCFAST_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcfastfsm_pmu_req_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCFASTFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcfastfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCFASTFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcmed_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcmed_force_pup_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCMED_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcmed_force_pup_en_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCMED_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcmed_ignore_mode_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCMED_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcmed_rst_b_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCMED_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcmed_rst_en_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCMED_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcmedfsm_pmu_req_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCMEDFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcmedfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCMEDFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcslow_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcslow_force_pup_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCSLOW_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcslow_force_pup_en_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCSLOW_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcslow_ignore_mode_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCSLOW_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcslow_rst_b_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCSLOW_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcslow_rst_en_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCSLOW_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcslowfsm_pmu_req_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCSLOWFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l1_cfg_synthlcslowfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L1_CFG_SYNTHLCSLOWFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l1_cfg_tstbus_rst_bypass_attr == SERDES_IP_CMN_AON_L1_CFG_TSTBUS_RST_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l1_cfg_tstbus_rst_bypass_en_attr == SERDES_IP_CMN_AON_L1_CFG_TSTBUS_RST_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l2_cfg_ckgate_disable_attr == SERDES_IP_CMN_AON_L2_CFG_CKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l2_cfg_cmn_force_pup_attr == SERDES_IP_CMN_AON_L2_CFG_CMN_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l2_cfg_cmn_force_pup_en_attr == SERDES_IP_CMN_AON_L2_CFG_CMN_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l2_cfg_cmn_rst_b_attr == SERDES_IP_CMN_AON_L2_CFG_CMN_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l2_cfg_cmn_rst_en_attr == SERDES_IP_CMN_AON_L2_CFG_CMN_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l2_cfg_cmnclk_ctrl_attr == SERDES_IP_CMN_AON_L2_CFG_CMNCLK_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l2_cfg_cmnclkdiv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l2_cfg_cmnfsm_pmu_req_attr == SERDES_IP_CMN_AON_L2_CFG_CMNFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l2_cfg_cmnfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L2_CFG_CMNFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l2_cfg_cmntstbus_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcfast_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcfast_force_pup_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCFAST_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcfast_force_pup_en_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCFAST_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcfast_ignore_mode_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCFAST_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcfast_rst_b_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCFAST_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcfast_rst_en_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCFAST_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcfastfsm_pmu_req_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCFASTFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcfastfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCFASTFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcmed_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcmed_force_pup_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCMED_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcmed_force_pup_en_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCMED_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcmed_ignore_mode_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCMED_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcmed_rst_b_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCMED_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcmed_rst_en_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCMED_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcmedfsm_pmu_req_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCMEDFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcmedfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCMEDFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcslow_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcslow_force_pup_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCSLOW_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcslow_force_pup_en_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCSLOW_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcslow_ignore_mode_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCSLOW_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcslow_rst_b_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCSLOW_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcslow_rst_en_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCSLOW_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcslowfsm_pmu_req_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCSLOWFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l2_cfg_synthlcslowfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L2_CFG_SYNTHLCSLOWFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l2_cfg_tstbus_rst_bypass_attr == SERDES_IP_CMN_AON_L2_CFG_TSTBUS_RST_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l2_cfg_tstbus_rst_bypass_en_attr == SERDES_IP_CMN_AON_L2_CFG_TSTBUS_RST_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l3_cfg_ckgate_disable_attr == SERDES_IP_CMN_AON_L3_CFG_CKGATE_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l3_cfg_cmn_force_pup_attr == SERDES_IP_CMN_AON_L3_CFG_CMN_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l3_cfg_cmn_force_pup_en_attr == SERDES_IP_CMN_AON_L3_CFG_CMN_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l3_cfg_cmn_rst_b_attr == SERDES_IP_CMN_AON_L3_CFG_CMN_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l3_cfg_cmn_rst_en_attr == SERDES_IP_CMN_AON_L3_CFG_CMN_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l3_cfg_cmnclk_ctrl_attr == SERDES_IP_CMN_AON_L3_CFG_CMNCLK_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l3_cfg_cmnclkdiv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l3_cfg_cmnfsm_pmu_req_attr == SERDES_IP_CMN_AON_L3_CFG_CMNFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l3_cfg_cmnfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L3_CFG_CMNFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l3_cfg_cmntstbus_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcfast_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcfast_force_pup_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCFAST_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcfast_force_pup_en_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCFAST_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcfast_ignore_mode_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCFAST_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcfast_rst_b_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCFAST_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcfast_rst_en_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCFAST_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcfastfsm_pmu_req_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCFASTFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcfastfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCFASTFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcmed_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcmed_force_pup_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCMED_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcmed_force_pup_en_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCMED_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcmed_ignore_mode_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCMED_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcmed_rst_b_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCMED_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcmed_rst_en_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCMED_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcmedfsm_pmu_req_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCMEDFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcmedfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCMEDFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcslow_default_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcslow_force_pup_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCSLOW_FORCE_PUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcslow_force_pup_en_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCSLOW_FORCE_PUP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcslow_ignore_mode_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCSLOW_IGNORE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcslow_rst_b_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCSLOW_RST_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcslow_rst_en_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCSLOW_RST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcslowfsm_pmu_req_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCSLOWFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l3_cfg_synthlcslowfsm_pmu_req_en_attr == SERDES_IP_CMN_AON_L3_CFG_SYNTHLCSLOWFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l3_cfg_tstbus_rst_bypass_attr == SERDES_IP_CMN_AON_L3_CFG_TSTBUS_RST_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_aon_l3_cfg_tstbus_rst_bypass_en_attr == SERDES_IP_CMN_AON_L3_CFG_TSTBUS_RST_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_bti_div_attr == 7'd54
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_bti_div_rst_attr == SERDES_IP_CMN_L0_CFG_BTI_DIV_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_bti_en_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_bti_static_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmn_pg_disable_attr == SERDES_IP_CMN_L0_CFG_CMN_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmn_scratch_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnadc_req_attr == SERDES_IP_CMN_L0_CFG_CMNADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnapb2strbbridgecfg_acc_ctrl_field_mask_write_en_attr == SERDES_IP_CMN_L0_CFG_CMNAPB2STRBBRIDGECFG_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnapb2strbbridgecfg_force_state_en_attr == SERDES_IP_CMN_L0_CFG_CMNAPB2STRBBRIDGECFG_FORCE_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnapb2strbbridgecfg_force_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnapb2strbbridgecfg_stbl_time_aftr_strb_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnapb2strbbridgecfg_stbl_time_bfr_strb_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnapb2strbbridgecfg_strb_pulse_width_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnapbmaster_timeout_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobe_addr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobe_lastmux_isolate_attr == SERDES_IP_CMN_L0_CFG_CMNAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobeadc_current_direction_attr == SERDES_IP_CMN_L0_CFG_CMNAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobeadc_resistor_enable_attr == SERDES_IP_CMN_L0_CFG_CMNAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobedac_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobedac_en_attr == SERDES_IP_CMN_L0_CFG_CMNAPROBEDAC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobedacctrl_block_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobedacctrl_en_attr == SERDES_IP_CMN_L0_CFG_CMNAPROBEDACCTRL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobedacctrl_mask_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobedacctrl_rotate_left_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnaprobedacctrl_tstbus_clkdiv_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnbias_icc20uadj_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnbias_icc80uadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnbias_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnbias_termcal_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnbscan_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnbshihyst_attr == SERDES_IP_CMN_L0_CFG_CMNBSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_bg_en_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_bg_one_step_cal_en_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_fg_inc_cal_en_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_fg_one_step_cal_en_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_finish_side_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_initval_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_invert_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_restore_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_round_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_runcount_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetfsm_signmagen_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncaldac_synthdutyoffsetmeas_req_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALDAC_SYNTHDUTYOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncaldacbg_abort_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncaldacbg_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncaldacbg_ready_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncaldacfsm_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncaldacfsm_synthdutyoffsetfsm_clear_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncaldacfsm_synthdutyoffsetfsm_init_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncaldacfsm_synthdutyoffsetfsm_req_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncaldacsynthdutyoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALDACSYNTHDUTYOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncaldacsynthdutyoffsetfsmout_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALDACSYNTHDUTYOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalptr_pstate_rcomp_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalptr_pstate_synthdutyoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalptr_quad_rcomp_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalptr_quad_regopampoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalptr_quad_synthdutyoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_biastrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_cap_tune_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_divrate_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_mode_select_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_ref_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMP_REF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_rx_term_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMP_RX_TERM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_tfr_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMP_TFR_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_tx_term_pd_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMP_TX_TERM_PD_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_tx_term_pu_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMP_TX_TERM_PU_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_txterm_nmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcomp_txterm_pmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_clear_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_code_delay_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_init_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rcomp_tfr_init_cal_value_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rcomp_tfr_max_value_attr == 4'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rcomp_tfr_min_value_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rcomp_txpd_valid_code_lut_vf00_attr == 32'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rcomp_txpd_valid_code_lut_vf01_attr == 32'd4246868100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rcomp_txpu_valid_code_lut_vf00_attr == 32'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rcomp_txpu_valid_code_lut_vf01_attr == 32'd4246868100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_req_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rx_comp_inv_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_RX_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rx_init_cal_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rx_initval_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rx_step_sign_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_RX_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_rx_termcode_delta_lut_attr == 31'd24084352
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tfr_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tfr_comp_inv_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_TFR_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tfr_initval_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tfr_step_sign_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_TFR_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tfr_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_time_comp_config_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_time_lpfsetup_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_time_mode_setup_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_time_reset_release_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_time_sample_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tx_pd_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tx_pd_init_cal_value_attr == 6'd49
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tx_pd_max_value_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tx_pd_min_value_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tx_pu_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tx_pu_init_cal_value_attr == 6'd49
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tx_pu_max_value_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_tx_pu_min_value_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_txpd_comp_inv_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_TXPD_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_txpd_initval_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_txpd_step_sign_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_TXPD_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_txpd_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_txpu_comp_inv_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_TXPU_COMP_INV_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_txpu_initval_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_txpu_step_sign_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPFSM_TXPU_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_txpu_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompfsm_txterm_pmos_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmaster_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPMASTER_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmaster_rx_locovr_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmaster_tfr_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmaster_txpd_locovr_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmaster_txpu_locovr_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmaster_valid_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALRCOMPMASTER_VALID_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmeas_dlycount_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalrcompmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffset_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_clear_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_finish_side_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_init_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_invert_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_req_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsm_runcount_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetfsmout_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetmeas_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetmeas_req_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmncalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_avg_en_attr == SERDES_IP_CMN_L0_CFG_CMNCKM_AVG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_clk_en_attr == SERDES_IP_CMN_L0_CFG_CMNCKM_CLK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_continuous_attr == SERDES_IP_CMN_L0_CFG_CMNCKM_CONTINUOUS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_dig_meas_en_attr == SERDES_IP_CMN_L0_CFG_CMNCKM_DIG_MEAS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_dig_meas_err_clr_attr == SERDES_IP_CMN_L0_CFG_CMNCKM_DIG_MEAS_ERR_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_en_attr == SERDES_IP_CMN_L0_CFG_CMNCKM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_max_thr_attr == 25'd33554431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_meas_ck_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_ref_ck_div_ratio_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_result_clr_attr == SERDES_IP_CMN_L0_CFG_CMNCKM_RESULT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_start_attr == SERDES_IP_CMN_L0_CFG_CMNCKM_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_wdt_interval_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnckm_win_thr_ref_attr == 25'd16777215
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnclk_keepalive_en_b_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnclk_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmndmondac_en_attr == SERDES_IP_CMN_L0_CFG_CMNDMONDAC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnfsm_cken_ovr_attr == SERDES_IP_CMN_L0_CFG_CMNFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnfsm_cken_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_aprobe1_charge_up_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_APROBE1_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_aprobe1_pull_dn_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_APROBE1_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_aprobe1_sense_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_APROBE1_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_aprobe2_charge_up_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_APROBE2_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_aprobe2_pull_dn_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_APROBE2_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_aprobe2_sense_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_APROBE2_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_changeref_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_changeref_val_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_en_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_CMN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_ntl_sel_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_CMN_NTL_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_cmn_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_refckm_charge_up_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_REFCKM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_refckm_pull_dn_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_REFCKM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_refckm_sense_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_REFCKM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_refckp_charge_up_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_REFCKP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_refckp_pull_dn_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_REFCKP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnntl_refckp_sense_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNNTL_REFCKP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnpcs_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnpcs_ref_sel_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnpcs_ref_sel_tx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnperfmon_compare_val_start_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnperfmon_compare_val_stop_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnperfmon_en_attr == SERDES_IP_CMN_L0_CFG_CMNPERFMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnperfmon_mask_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprefckbufprelut_delta_attr == 15'd32767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprefckbufprelut_init_termcal_rx_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprefckbufprelut_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNRCOMPREFCKBUFPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprefckbufprelut_termcal_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprefcktxdrvprelut_delta_attr == 15'd4672
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprefcktxdrvprelut_init_termcal_rx_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprefcktxdrvprelut_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNRCOMPREFCKTXDRVPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprefcktxdrvprelut_termcal_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprxdfeprelut_delta_attr == 15'd32767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprxdfeprelut_init_termcal_tfr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprxdfeprelut_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNRCOMPRXDFEPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrcomprxdfeprelut_termcal_tfr_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckbuf_cml_ena_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKBUF_CML_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckbuf_hs_cmos_ena_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKBUF_HS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckbuf_hs_ls_b_path_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKBUF_HS_LS_B_PATH_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckbuf_hs_ref_to_cdrdiv_ena_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKBUF_HS_REF_TO_CDRDIV_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckbuf_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKBUF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckbuf_ls_cmos_ena_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKBUF_LS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckbuf_powersave_b_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKBUF_POWERSAVE_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckbuf_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckbuf_termhiz_b_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKBUF_TERMHIZ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrefckdrv_powersave_en_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKDRV_POWERSAVE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrefcktxdrv_cdrdiv_en_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKTXDRV_CDRDIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrefcktxdrv_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNREFCKTXDRV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrefcktxdrv_termcal_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_en_b_attr == SERDES_IP_CMN_L0_CFG_CMNRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_entry3_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s0q2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s0q3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s1q4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s1q5_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s1q6_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s1q7_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evdn_delay_lut_sel_s2q0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_entry2_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_entry3_attr == 13'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_entry4_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_entry5_attr == 13'd62
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_entry6_attr == 13'd390
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_entry7_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s0q2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s0q3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s1q1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s1q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s1q5_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s1q7_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpu_evup_delay_lut_sel_s2q0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_term_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_term_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_term_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_term_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_term_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_term_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_term_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_cal_term_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_keepalive_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_keepalive_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpuetr_reg_pwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_bias_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_bias_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_refckbuf_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_refckbuf_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_refckbuf_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_refckbuf_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_rxref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_rxref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_rxref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_rxref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_synthdutycomp_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_synthdutycomp_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_synthdutycomp_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_synthdutycomp_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_synthlcslowref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_synthlcslowref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_synthlcslowref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_synthlcslowref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_txref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_txref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_txref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpupd_txref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpurst_regreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpurst_regreset_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpurst_regreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrpurst_regreset_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_aetrcmn_regpwrupacc_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_AETRCMN_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_aetrcmn_regpwrupacc_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_AETRCMN_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_adc_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_adc_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_ADC_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_biasicc_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_biasicc_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_ntl_b_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_ntl_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_refckbuf_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_refckbuf_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_reg_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_reg_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_rxref_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_RXREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_rxref_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_RXREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_synthlcslowref_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_SYNTHLCSLOWREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_synthlcslowref_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_SYNTHLCSLOWREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_txref_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_TXREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_apdcmn_txref_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_APDCMN_TXREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_arstcmn_adc_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_ARSTCMN_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_arstcmn_adc_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_ARSTCMN_ADC_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_arstcmn_aprobedac_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_ARSTCMN_APROBEDAC_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_arstcmn_refcktxdrv_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_ARSTCMN_REFCKTXDRV_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_arstcmn_refcktxdrv_hiz_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_ARSTCMN_REFCKTXDRV_HIZ_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_arstcmn_regreset_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_ARSTCMN_REGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_arstcmn_regreset_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_ARSTCMN_REGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_synthdutycomp_ovr_b_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_SYNTHDUTYCOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrstpdovr_synthdutycomp_ovren_attr == SERDES_IP_CMN_L0_CFG_CMNRSTPDOVR_SYNTHDUTYCOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrxref_dpma_en_attr == SERDES_IP_CMN_L0_CFG_CMNRXREF_DPMA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrxref_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNRXREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnrxref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnspare0_attr == 32'd163
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnspare_attr == 9'd384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_rxlane0_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_rxlane1_timer_attr == 12'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_rxlane2_timer_attr == 12'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_rxlane3_timer_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_synthlcfast_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_synthlcmed_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_synthlcslow_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_txlane0_timer_attr == 12'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_txlane1_timer_attr == 12'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_txlane2_timer_attr == 12'd70
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnstagger_txlane3_timer_attr == 12'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthdiv_cdrdiv_en_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHDIV_CDRDIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthdiv_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHDIV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthdiv_slowmed_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHDIV_SLOWMED_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthdutyoffsetcal_en_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHDUTYOFFSETCAL_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthdutyoffsetcal_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHDUTYOFFSETCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthdutysel_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHDUTYSEL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthdutysel_mux_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlccaldac_currentdacdcdmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlccaldac_currentdacdcdmeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlccaldac_currentdacdcdmeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlccaldac_currentdacdcdmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlccaldac_synthdutyoffsetmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlccaldac_tx_disable_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHLCCALDAC_TX_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlccaldacerr_calsynthdutyerr_locovr_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHLCCALDACERR_CALSYNTHDUTYERR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlccaldacerr_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHLCCALDACERR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlcslowref_dpma_en_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHLCSLOWREF_DPMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlcslowref_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNSYNTHLCSLOWREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnsynthlcslowref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmntxref_dpma_en_attr == SERDES_IP_CMN_L0_CFG_CMNTXREF_DPMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmntxref_locovren_attr == SERDES_IP_CMN_L0_CFG_CMNTXREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmntxref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_cmnynthdutyselpolarity_attr == SERDES_IP_CMN_L0_CFG_CMNYNTHDUTYSELPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_lbcmn_locovren_attr == SERDES_IP_CMN_L0_CFG_LBCMN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_lbcmn_synthlcslowmedpostdivclk2cdrrefclken_locovr_attr == SERDES_IP_CMN_L0_CFG_LBCMN_SYNTHLCSLOWMEDPOSTDIVCLK2CDRREFCLKEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_rcompmaster_en_locovr_attr == SERDES_IP_CMN_L0_CFG_RCOMPMASTER_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_rcompmaster_locovren_attr == SERDES_IP_CMN_L0_CFG_RCOMPMASTER_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_rcompslave_locovr_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_rcompslave_locovren_attr == SERDES_IP_CMN_L0_CFG_RCOMPSLAVE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_rcompslave_valid_locovr_attr == SERDES_IP_CMN_L0_CFG_RCOMPSLAVE_VALID_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_rcompterm_rx_termcode_base_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_rcompterm_tfr_termcode_base_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_rcompterm_txpd_termcode_base_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_rcompterm_txpu_termcode_base_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmed_locovren_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMED_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmed_txbitclkselect_locovr_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMED_TXBITCLKSELECT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedcaldac_locovren_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMEDCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedcalregopampoffset_locovren_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedcalregopampoffsetfsmout_locovren_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedpcs_locovren_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMEDPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedpcs_postdiv2clk0_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedpcs_postdiv2clk0en_locovr_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMEDPCS_POSTDIV2CLK0EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedpcs_postdivclk0en_locovr_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMEDPCS_POSTDIVCLK0EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedreg_lev_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l0_cfg_synthlcslowmedreg_locovren_attr == SERDES_IP_CMN_L0_CFG_SYNTHLCSLOWMEDREG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_bti_div_attr == 7'd54
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_bti_div_rst_attr == SERDES_IP_CMN_L1_CFG_BTI_DIV_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_bti_en_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_bti_static_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmn_pg_disable_attr == SERDES_IP_CMN_L1_CFG_CMN_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmn_scratch_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnadc_req_attr == SERDES_IP_CMN_L1_CFG_CMNADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnapb2strbbridgecfg_acc_ctrl_field_mask_write_en_attr == SERDES_IP_CMN_L1_CFG_CMNAPB2STRBBRIDGECFG_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnapb2strbbridgecfg_force_state_en_attr == SERDES_IP_CMN_L1_CFG_CMNAPB2STRBBRIDGECFG_FORCE_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnapb2strbbridgecfg_force_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnapb2strbbridgecfg_stbl_time_aftr_strb_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnapb2strbbridgecfg_stbl_time_bfr_strb_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnapb2strbbridgecfg_strb_pulse_width_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnapbmaster_timeout_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobe_addr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobe_lastmux_isolate_attr == SERDES_IP_CMN_L1_CFG_CMNAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobeadc_current_direction_attr == SERDES_IP_CMN_L1_CFG_CMNAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobeadc_resistor_enable_attr == SERDES_IP_CMN_L1_CFG_CMNAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobedac_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobedac_en_attr == SERDES_IP_CMN_L1_CFG_CMNAPROBEDAC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobedacctrl_block_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobedacctrl_en_attr == SERDES_IP_CMN_L1_CFG_CMNAPROBEDACCTRL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobedacctrl_mask_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobedacctrl_rotate_left_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnaprobedacctrl_tstbus_clkdiv_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnbias_icc20uadj_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnbias_icc80uadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnbias_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnbias_termcal_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnbscan_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnbshihyst_attr == SERDES_IP_CMN_L1_CFG_CMNBSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_bg_en_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_bg_one_step_cal_en_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_fg_inc_cal_en_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_fg_one_step_cal_en_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_finish_side_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_initval_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_invert_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_restore_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_round_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_runcount_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetfsm_signmagen_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncaldac_synthdutyoffsetmeas_req_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALDAC_SYNTHDUTYOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncaldacbg_abort_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncaldacbg_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncaldacbg_ready_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncaldacfsm_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncaldacfsm_synthdutyoffsetfsm_clear_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncaldacfsm_synthdutyoffsetfsm_init_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncaldacfsm_synthdutyoffsetfsm_req_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncaldacsynthdutyoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALDACSYNTHDUTYOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncaldacsynthdutyoffsetfsmout_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALDACSYNTHDUTYOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalptr_pstate_rcomp_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalptr_pstate_synthdutyoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalptr_quad_rcomp_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalptr_quad_regopampoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalptr_quad_synthdutyoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_biastrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_cap_tune_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_divrate_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_mode_select_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_ref_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMP_REF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_rx_term_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMP_RX_TERM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_tfr_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMP_TFR_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_tx_term_pd_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMP_TX_TERM_PD_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_tx_term_pu_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMP_TX_TERM_PU_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_txterm_nmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcomp_txterm_pmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_clear_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_code_delay_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_init_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rcomp_tfr_init_cal_value_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rcomp_tfr_max_value_attr == 4'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rcomp_tfr_min_value_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rcomp_txpd_valid_code_lut_vf00_attr == 32'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rcomp_txpd_valid_code_lut_vf01_attr == 32'd4246868100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rcomp_txpu_valid_code_lut_vf00_attr == 32'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rcomp_txpu_valid_code_lut_vf01_attr == 32'd4246868100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_req_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rx_comp_inv_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_RX_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rx_init_cal_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rx_initval_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rx_step_sign_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_RX_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_rx_termcode_delta_lut_attr == 31'd24084352
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tfr_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tfr_comp_inv_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_TFR_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tfr_initval_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tfr_step_sign_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_TFR_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tfr_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_time_comp_config_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_time_lpfsetup_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_time_mode_setup_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_time_reset_release_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_time_sample_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tx_pd_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tx_pd_init_cal_value_attr == 6'd49
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tx_pd_max_value_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tx_pd_min_value_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tx_pu_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tx_pu_init_cal_value_attr == 6'd49
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tx_pu_max_value_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_tx_pu_min_value_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_txpd_comp_inv_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_TXPD_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_txpd_initval_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_txpd_step_sign_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_TXPD_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_txpd_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_txpu_comp_inv_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_TXPU_COMP_INV_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_txpu_initval_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_txpu_step_sign_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPFSM_TXPU_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_txpu_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompfsm_txterm_pmos_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmaster_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPMASTER_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmaster_rx_locovr_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmaster_tfr_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmaster_txpd_locovr_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmaster_txpu_locovr_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmaster_valid_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALRCOMPMASTER_VALID_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmeas_dlycount_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalrcompmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffset_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_clear_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_finish_side_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_init_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_invert_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_req_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsm_runcount_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetfsmout_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetmeas_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetmeas_req_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmncalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_avg_en_attr == SERDES_IP_CMN_L1_CFG_CMNCKM_AVG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_clk_en_attr == SERDES_IP_CMN_L1_CFG_CMNCKM_CLK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_continuous_attr == SERDES_IP_CMN_L1_CFG_CMNCKM_CONTINUOUS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_dig_meas_en_attr == SERDES_IP_CMN_L1_CFG_CMNCKM_DIG_MEAS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_dig_meas_err_clr_attr == SERDES_IP_CMN_L1_CFG_CMNCKM_DIG_MEAS_ERR_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_en_attr == SERDES_IP_CMN_L1_CFG_CMNCKM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_max_thr_attr == 25'd33554431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_meas_ck_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_ref_ck_div_ratio_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_result_clr_attr == SERDES_IP_CMN_L1_CFG_CMNCKM_RESULT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_start_attr == SERDES_IP_CMN_L1_CFG_CMNCKM_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_wdt_interval_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnckm_win_thr_ref_attr == 25'd16777215
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnclk_keepalive_en_b_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnclk_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmndmondac_en_attr == SERDES_IP_CMN_L1_CFG_CMNDMONDAC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnfsm_cken_ovr_attr == SERDES_IP_CMN_L1_CFG_CMNFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnfsm_cken_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_aprobe1_charge_up_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_APROBE1_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_aprobe1_pull_dn_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_APROBE1_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_aprobe1_sense_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_APROBE1_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_aprobe2_charge_up_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_APROBE2_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_aprobe2_pull_dn_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_APROBE2_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_aprobe2_sense_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_APROBE2_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_changeref_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_changeref_val_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_en_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_CMN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_ntl_sel_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_CMN_NTL_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_cmn_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_refckm_charge_up_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_REFCKM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_refckm_pull_dn_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_REFCKM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_refckm_sense_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_REFCKM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_refckp_charge_up_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_REFCKP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_refckp_pull_dn_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_REFCKP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnntl_refckp_sense_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNNTL_REFCKP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnpcs_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnpcs_ref_sel_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnpcs_ref_sel_tx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnperfmon_compare_val_start_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnperfmon_compare_val_stop_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnperfmon_en_attr == SERDES_IP_CMN_L1_CFG_CMNPERFMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnperfmon_mask_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprefckbufprelut_delta_attr == 15'd32767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprefckbufprelut_init_termcal_rx_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprefckbufprelut_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNRCOMPREFCKBUFPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprefckbufprelut_termcal_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprefcktxdrvprelut_delta_attr == 15'd4672
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprefcktxdrvprelut_init_termcal_rx_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprefcktxdrvprelut_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNRCOMPREFCKTXDRVPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprefcktxdrvprelut_termcal_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprxdfeprelut_delta_attr == 15'd32767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprxdfeprelut_init_termcal_tfr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprxdfeprelut_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNRCOMPRXDFEPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrcomprxdfeprelut_termcal_tfr_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckbuf_cml_ena_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKBUF_CML_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckbuf_hs_cmos_ena_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKBUF_HS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckbuf_hs_ls_b_path_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKBUF_HS_LS_B_PATH_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckbuf_hs_ref_to_cdrdiv_ena_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKBUF_HS_REF_TO_CDRDIV_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckbuf_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKBUF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckbuf_ls_cmos_ena_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKBUF_LS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckbuf_powersave_b_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKBUF_POWERSAVE_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckbuf_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckbuf_termhiz_b_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKBUF_TERMHIZ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrefckdrv_powersave_en_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKDRV_POWERSAVE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrefcktxdrv_cdrdiv_en_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKTXDRV_CDRDIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrefcktxdrv_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNREFCKTXDRV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrefcktxdrv_termcal_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_en_b_attr == SERDES_IP_CMN_L1_CFG_CMNRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_entry3_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s0q2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s0q3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s1q4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s1q5_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s1q6_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s1q7_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evdn_delay_lut_sel_s2q0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_entry2_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_entry3_attr == 13'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_entry4_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_entry5_attr == 13'd62
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_entry6_attr == 13'd390
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_entry7_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s0q2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s0q3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s1q1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s1q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s1q5_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s1q7_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpu_evup_delay_lut_sel_s2q0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_term_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_term_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_term_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_term_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_term_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_term_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_term_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_cal_term_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_keepalive_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_keepalive_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpuetr_reg_pwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_bias_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_bias_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_refckbuf_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_refckbuf_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_refckbuf_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_refckbuf_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_rxref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_rxref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_rxref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_rxref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_synthdutycomp_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_synthdutycomp_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_synthdutycomp_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_synthdutycomp_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_synthlcslowref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_synthlcslowref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_synthlcslowref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_synthlcslowref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_txref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_txref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_txref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpupd_txref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpurst_regreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpurst_regreset_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpurst_regreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrpurst_regreset_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_aetrcmn_regpwrupacc_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_AETRCMN_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_aetrcmn_regpwrupacc_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_AETRCMN_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_adc_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_adc_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_ADC_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_biasicc_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_biasicc_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_ntl_b_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_ntl_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_refckbuf_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_refckbuf_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_reg_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_reg_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_rxref_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_RXREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_rxref_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_RXREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_synthlcslowref_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_SYNTHLCSLOWREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_synthlcslowref_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_SYNTHLCSLOWREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_txref_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_TXREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_apdcmn_txref_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_APDCMN_TXREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_arstcmn_adc_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_ARSTCMN_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_arstcmn_adc_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_ARSTCMN_ADC_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_arstcmn_aprobedac_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_ARSTCMN_APROBEDAC_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_arstcmn_refcktxdrv_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_ARSTCMN_REFCKTXDRV_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_arstcmn_refcktxdrv_hiz_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_ARSTCMN_REFCKTXDRV_HIZ_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_arstcmn_regreset_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_ARSTCMN_REGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_arstcmn_regreset_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_ARSTCMN_REGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_synthdutycomp_ovr_b_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_SYNTHDUTYCOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrstpdovr_synthdutycomp_ovren_attr == SERDES_IP_CMN_L1_CFG_CMNRSTPDOVR_SYNTHDUTYCOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrxref_dpma_en_attr == SERDES_IP_CMN_L1_CFG_CMNRXREF_DPMA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrxref_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNRXREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnrxref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnspare0_attr == 32'd163
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnspare_attr == 9'd384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_rxlane0_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_rxlane1_timer_attr == 12'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_rxlane2_timer_attr == 12'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_rxlane3_timer_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_synthlcfast_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_synthlcmed_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_synthlcslow_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_txlane0_timer_attr == 12'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_txlane1_timer_attr == 12'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_txlane2_timer_attr == 12'd70
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnstagger_txlane3_timer_attr == 12'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthdiv_cdrdiv_en_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHDIV_CDRDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthdiv_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHDIV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthdiv_slowmed_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHDIV_SLOWMED_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthdutyoffsetcal_en_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHDUTYOFFSETCAL_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthdutyoffsetcal_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHDUTYOFFSETCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthdutysel_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHDUTYSEL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthdutysel_mux_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlccaldac_currentdacdcdmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlccaldac_currentdacdcdmeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlccaldac_currentdacdcdmeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlccaldac_currentdacdcdmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlccaldac_synthdutyoffsetmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlccaldac_tx_disable_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHLCCALDAC_TX_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlccaldacerr_calsynthdutyerr_locovr_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHLCCALDACERR_CALSYNTHDUTYERR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlccaldacerr_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHLCCALDACERR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlcslowref_dpma_en_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHLCSLOWREF_DPMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlcslowref_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNSYNTHLCSLOWREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnsynthlcslowref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmntxref_dpma_en_attr == SERDES_IP_CMN_L1_CFG_CMNTXREF_DPMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmntxref_locovren_attr == SERDES_IP_CMN_L1_CFG_CMNTXREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmntxref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_cmnynthdutyselpolarity_attr == SERDES_IP_CMN_L1_CFG_CMNYNTHDUTYSELPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_lbcmn_locovren_attr == SERDES_IP_CMN_L1_CFG_LBCMN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_lbcmn_synthlcslowmedpostdivclk2cdrrefclken_locovr_attr == SERDES_IP_CMN_L1_CFG_LBCMN_SYNTHLCSLOWMEDPOSTDIVCLK2CDRREFCLKEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_rcompmaster_en_locovr_attr == SERDES_IP_CMN_L1_CFG_RCOMPMASTER_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_rcompmaster_locovren_attr == SERDES_IP_CMN_L1_CFG_RCOMPMASTER_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_rcompslave_locovr_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_rcompslave_locovren_attr == SERDES_IP_CMN_L1_CFG_RCOMPSLAVE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_rcompslave_valid_locovr_attr == SERDES_IP_CMN_L1_CFG_RCOMPSLAVE_VALID_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_rcompterm_rx_termcode_base_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_rcompterm_tfr_termcode_base_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_rcompterm_txpd_termcode_base_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_rcompterm_txpu_termcode_base_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmed_locovren_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMED_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmed_txbitclkselect_locovr_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMED_TXBITCLKSELECT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedcaldac_locovren_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMEDCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedcalregopampoffset_locovren_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedcalregopampoffsetfsmout_locovren_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedpcs_locovren_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMEDPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedpcs_postdiv2clk0_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedpcs_postdiv2clk0en_locovr_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMEDPCS_POSTDIV2CLK0EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedpcs_postdivclk0en_locovr_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMEDPCS_POSTDIVCLK0EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedreg_lev_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l1_cfg_synthlcslowmedreg_locovren_attr == SERDES_IP_CMN_L1_CFG_SYNTHLCSLOWMEDREG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_bti_div_attr == 7'd54
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_bti_div_rst_attr == SERDES_IP_CMN_L2_CFG_BTI_DIV_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_bti_en_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_bti_static_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmn_pg_disable_attr == SERDES_IP_CMN_L2_CFG_CMN_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmn_scratch_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnadc_req_attr == SERDES_IP_CMN_L2_CFG_CMNADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnapb2strbbridgecfg_acc_ctrl_field_mask_write_en_attr == SERDES_IP_CMN_L2_CFG_CMNAPB2STRBBRIDGECFG_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnapb2strbbridgecfg_force_state_en_attr == SERDES_IP_CMN_L2_CFG_CMNAPB2STRBBRIDGECFG_FORCE_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnapb2strbbridgecfg_force_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnapb2strbbridgecfg_stbl_time_aftr_strb_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnapb2strbbridgecfg_stbl_time_bfr_strb_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnapb2strbbridgecfg_strb_pulse_width_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnapbmaster_timeout_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobe_addr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobe_lastmux_isolate_attr == SERDES_IP_CMN_L2_CFG_CMNAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobeadc_current_direction_attr == SERDES_IP_CMN_L2_CFG_CMNAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobeadc_resistor_enable_attr == SERDES_IP_CMN_L2_CFG_CMNAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobedac_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobedac_en_attr == SERDES_IP_CMN_L2_CFG_CMNAPROBEDAC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobedacctrl_block_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobedacctrl_en_attr == SERDES_IP_CMN_L2_CFG_CMNAPROBEDACCTRL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobedacctrl_mask_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobedacctrl_rotate_left_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnaprobedacctrl_tstbus_clkdiv_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnbias_icc20uadj_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnbias_icc80uadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnbias_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnbias_termcal_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnbscan_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnbshihyst_attr == SERDES_IP_CMN_L2_CFG_CMNBSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_bg_en_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_bg_one_step_cal_en_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_fg_inc_cal_en_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_fg_one_step_cal_en_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_finish_side_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_initval_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_invert_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_restore_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_round_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_runcount_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetfsm_signmagen_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncaldac_synthdutyoffsetmeas_req_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALDAC_SYNTHDUTYOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncaldacbg_abort_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncaldacbg_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncaldacbg_ready_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncaldacfsm_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncaldacfsm_synthdutyoffsetfsm_clear_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncaldacfsm_synthdutyoffsetfsm_init_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncaldacfsm_synthdutyoffsetfsm_req_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncaldacsynthdutyoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALDACSYNTHDUTYOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncaldacsynthdutyoffsetfsmout_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALDACSYNTHDUTYOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalptr_pstate_rcomp_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalptr_pstate_synthdutyoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalptr_quad_rcomp_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalptr_quad_regopampoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalptr_quad_synthdutyoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_biastrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_cap_tune_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_divrate_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_mode_select_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_ref_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMP_REF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_rx_term_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMP_RX_TERM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_tfr_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMP_TFR_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_tx_term_pd_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMP_TX_TERM_PD_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_tx_term_pu_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMP_TX_TERM_PU_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_txterm_nmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcomp_txterm_pmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_clear_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_code_delay_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_init_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rcomp_tfr_init_cal_value_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rcomp_tfr_max_value_attr == 4'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rcomp_tfr_min_value_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rcomp_txpd_valid_code_lut_vf00_attr == 32'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rcomp_txpd_valid_code_lut_vf01_attr == 32'd4246868100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rcomp_txpu_valid_code_lut_vf00_attr == 32'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rcomp_txpu_valid_code_lut_vf01_attr == 32'd4246868100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_req_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rx_comp_inv_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_RX_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rx_init_cal_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rx_initval_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rx_step_sign_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_RX_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_rx_termcode_delta_lut_attr == 31'd24084352
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tfr_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tfr_comp_inv_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_TFR_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tfr_initval_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tfr_step_sign_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_TFR_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tfr_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_time_comp_config_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_time_lpfsetup_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_time_mode_setup_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_time_reset_release_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_time_sample_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tx_pd_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tx_pd_init_cal_value_attr == 6'd49
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tx_pd_max_value_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tx_pd_min_value_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tx_pu_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tx_pu_init_cal_value_attr == 6'd49
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tx_pu_max_value_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_tx_pu_min_value_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_txpd_comp_inv_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_TXPD_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_txpd_initval_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_txpd_step_sign_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_TXPD_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_txpd_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_txpu_comp_inv_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_TXPU_COMP_INV_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_txpu_initval_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_txpu_step_sign_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPFSM_TXPU_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_txpu_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompfsm_txterm_pmos_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmaster_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPMASTER_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmaster_rx_locovr_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmaster_tfr_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmaster_txpd_locovr_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmaster_txpu_locovr_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmaster_valid_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALRCOMPMASTER_VALID_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmeas_dlycount_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalrcompmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffset_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_clear_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_finish_side_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_init_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_invert_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_req_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsm_runcount_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetfsmout_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetmeas_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetmeas_req_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmncalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_avg_en_attr == SERDES_IP_CMN_L2_CFG_CMNCKM_AVG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_clk_en_attr == SERDES_IP_CMN_L2_CFG_CMNCKM_CLK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_continuous_attr == SERDES_IP_CMN_L2_CFG_CMNCKM_CONTINUOUS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_dig_meas_en_attr == SERDES_IP_CMN_L2_CFG_CMNCKM_DIG_MEAS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_dig_meas_err_clr_attr == SERDES_IP_CMN_L2_CFG_CMNCKM_DIG_MEAS_ERR_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_en_attr == SERDES_IP_CMN_L2_CFG_CMNCKM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_max_thr_attr == 25'd33554431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_meas_ck_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_ref_ck_div_ratio_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_result_clr_attr == SERDES_IP_CMN_L2_CFG_CMNCKM_RESULT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_start_attr == SERDES_IP_CMN_L2_CFG_CMNCKM_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_wdt_interval_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnckm_win_thr_ref_attr == 25'd16777215
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnclk_keepalive_en_b_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnclk_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmndmondac_en_attr == SERDES_IP_CMN_L2_CFG_CMNDMONDAC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnfsm_cken_ovr_attr == SERDES_IP_CMN_L2_CFG_CMNFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnfsm_cken_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_aprobe1_charge_up_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_APROBE1_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_aprobe1_pull_dn_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_APROBE1_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_aprobe1_sense_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_APROBE1_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_aprobe2_charge_up_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_APROBE2_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_aprobe2_pull_dn_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_APROBE2_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_aprobe2_sense_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_APROBE2_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_changeref_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_changeref_val_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_en_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_CMN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_ntl_sel_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_CMN_NTL_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_cmn_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_refckm_charge_up_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_REFCKM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_refckm_pull_dn_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_REFCKM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_refckm_sense_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_REFCKM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_refckp_charge_up_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_REFCKP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_refckp_pull_dn_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_REFCKP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnntl_refckp_sense_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNNTL_REFCKP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnpcs_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnpcs_ref_sel_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnpcs_ref_sel_tx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnperfmon_compare_val_start_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnperfmon_compare_val_stop_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnperfmon_en_attr == SERDES_IP_CMN_L2_CFG_CMNPERFMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnperfmon_mask_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprefckbufprelut_delta_attr == 15'd32767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprefckbufprelut_init_termcal_rx_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprefckbufprelut_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNRCOMPREFCKBUFPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprefckbufprelut_termcal_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprefcktxdrvprelut_delta_attr == 15'd4672
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprefcktxdrvprelut_init_termcal_rx_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprefcktxdrvprelut_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNRCOMPREFCKTXDRVPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprefcktxdrvprelut_termcal_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprxdfeprelut_delta_attr == 15'd32767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprxdfeprelut_init_termcal_tfr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprxdfeprelut_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNRCOMPRXDFEPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrcomprxdfeprelut_termcal_tfr_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckbuf_cml_ena_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKBUF_CML_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckbuf_hs_cmos_ena_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKBUF_HS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckbuf_hs_ls_b_path_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKBUF_HS_LS_B_PATH_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckbuf_hs_ref_to_cdrdiv_ena_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKBUF_HS_REF_TO_CDRDIV_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckbuf_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKBUF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckbuf_ls_cmos_ena_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKBUF_LS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckbuf_powersave_b_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKBUF_POWERSAVE_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckbuf_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckbuf_termhiz_b_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKBUF_TERMHIZ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrefckdrv_powersave_en_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKDRV_POWERSAVE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrefcktxdrv_cdrdiv_en_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKTXDRV_CDRDIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrefcktxdrv_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNREFCKTXDRV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrefcktxdrv_termcal_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_en_b_attr == SERDES_IP_CMN_L2_CFG_CMNRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_entry3_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s0q2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s0q3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s1q4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s1q5_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s1q6_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s1q7_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evdn_delay_lut_sel_s2q0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_entry2_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_entry3_attr == 13'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_entry4_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_entry5_attr == 13'd62
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_entry6_attr == 13'd390
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_entry7_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s0q2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s0q3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s1q1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s1q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s1q5_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s1q7_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpu_evup_delay_lut_sel_s2q0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_term_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_term_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_term_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_term_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_term_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_term_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_term_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_cal_term_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_keepalive_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_keepalive_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpuetr_reg_pwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_bias_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_bias_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_refckbuf_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_refckbuf_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_refckbuf_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_refckbuf_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_rxref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_rxref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_rxref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_rxref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_synthdutycomp_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_synthdutycomp_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_synthdutycomp_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_synthdutycomp_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_synthlcslowref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_synthlcslowref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_synthlcslowref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_synthlcslowref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_txref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_txref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_txref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpupd_txref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpurst_regreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpurst_regreset_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpurst_regreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrpurst_regreset_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_aetrcmn_regpwrupacc_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_AETRCMN_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_aetrcmn_regpwrupacc_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_AETRCMN_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_adc_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_adc_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_ADC_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_biasicc_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_biasicc_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_ntl_b_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_ntl_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_refckbuf_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_refckbuf_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_reg_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_reg_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_rxref_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_RXREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_rxref_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_RXREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_synthlcslowref_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_SYNTHLCSLOWREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_synthlcslowref_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_SYNTHLCSLOWREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_txref_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_TXREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_apdcmn_txref_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_APDCMN_TXREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_arstcmn_adc_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_ARSTCMN_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_arstcmn_adc_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_ARSTCMN_ADC_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_arstcmn_aprobedac_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_ARSTCMN_APROBEDAC_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_arstcmn_refcktxdrv_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_ARSTCMN_REFCKTXDRV_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_arstcmn_refcktxdrv_hiz_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_ARSTCMN_REFCKTXDRV_HIZ_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_arstcmn_regreset_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_ARSTCMN_REGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_arstcmn_regreset_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_ARSTCMN_REGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_synthdutycomp_ovr_b_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_SYNTHDUTYCOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrstpdovr_synthdutycomp_ovren_attr == SERDES_IP_CMN_L2_CFG_CMNRSTPDOVR_SYNTHDUTYCOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrxref_dpma_en_attr == SERDES_IP_CMN_L2_CFG_CMNRXREF_DPMA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrxref_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNRXREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnrxref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnspare0_attr == 32'd163
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnspare_attr == 9'd384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_rxlane0_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_rxlane1_timer_attr == 12'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_rxlane2_timer_attr == 12'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_rxlane3_timer_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_synthlcfast_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_synthlcmed_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_synthlcslow_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_txlane0_timer_attr == 12'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_txlane1_timer_attr == 12'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_txlane2_timer_attr == 12'd70
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnstagger_txlane3_timer_attr == 12'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthdiv_cdrdiv_en_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHDIV_CDRDIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthdiv_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHDIV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthdiv_slowmed_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHDIV_SLOWMED_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthdutyoffsetcal_en_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHDUTYOFFSETCAL_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthdutyoffsetcal_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHDUTYOFFSETCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthdutysel_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHDUTYSEL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthdutysel_mux_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlccaldac_currentdacdcdmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlccaldac_currentdacdcdmeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlccaldac_currentdacdcdmeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlccaldac_currentdacdcdmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlccaldac_synthdutyoffsetmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlccaldac_tx_disable_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHLCCALDAC_TX_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlccaldacerr_calsynthdutyerr_locovr_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHLCCALDACERR_CALSYNTHDUTYERR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlccaldacerr_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHLCCALDACERR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlcslowref_dpma_en_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHLCSLOWREF_DPMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlcslowref_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNSYNTHLCSLOWREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnsynthlcslowref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmntxref_dpma_en_attr == SERDES_IP_CMN_L2_CFG_CMNTXREF_DPMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmntxref_locovren_attr == SERDES_IP_CMN_L2_CFG_CMNTXREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmntxref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_cmnynthdutyselpolarity_attr == SERDES_IP_CMN_L2_CFG_CMNYNTHDUTYSELPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_lbcmn_locovren_attr == SERDES_IP_CMN_L2_CFG_LBCMN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_lbcmn_synthlcslowmedpostdivclk2cdrrefclken_locovr_attr == SERDES_IP_CMN_L2_CFG_LBCMN_SYNTHLCSLOWMEDPOSTDIVCLK2CDRREFCLKEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_rcompmaster_en_locovr_attr == SERDES_IP_CMN_L2_CFG_RCOMPMASTER_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_rcompmaster_locovren_attr == SERDES_IP_CMN_L2_CFG_RCOMPMASTER_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_rcompslave_locovr_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_rcompslave_locovren_attr == SERDES_IP_CMN_L2_CFG_RCOMPSLAVE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_rcompslave_valid_locovr_attr == SERDES_IP_CMN_L2_CFG_RCOMPSLAVE_VALID_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_rcompterm_rx_termcode_base_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_rcompterm_tfr_termcode_base_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_rcompterm_txpd_termcode_base_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_rcompterm_txpu_termcode_base_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmed_locovren_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMED_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmed_txbitclkselect_locovr_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMED_TXBITCLKSELECT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedcaldac_locovren_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMEDCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedcalregopampoffset_locovren_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedcalregopampoffsetfsmout_locovren_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedpcs_locovren_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMEDPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedpcs_postdiv2clk0_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedpcs_postdiv2clk0en_locovr_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMEDPCS_POSTDIV2CLK0EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedpcs_postdivclk0en_locovr_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMEDPCS_POSTDIVCLK0EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedreg_lev_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l2_cfg_synthlcslowmedreg_locovren_attr == SERDES_IP_CMN_L2_CFG_SYNTHLCSLOWMEDREG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_bti_div_attr == 7'd54
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_bti_div_rst_attr == SERDES_IP_CMN_L3_CFG_BTI_DIV_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_bti_en_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_bti_static_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmn_pg_disable_attr == SERDES_IP_CMN_L3_CFG_CMN_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmn_scratch_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnadc_req_attr == SERDES_IP_CMN_L3_CFG_CMNADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnapb2strbbridgecfg_acc_ctrl_field_mask_write_en_attr == SERDES_IP_CMN_L3_CFG_CMNAPB2STRBBRIDGECFG_ACC_CTRL_FIELD_MASK_WRITE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnapb2strbbridgecfg_force_state_en_attr == SERDES_IP_CMN_L3_CFG_CMNAPB2STRBBRIDGECFG_FORCE_STATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnapb2strbbridgecfg_force_state_val_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnapb2strbbridgecfg_stbl_time_aftr_strb_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnapb2strbbridgecfg_stbl_time_bfr_strb_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnapb2strbbridgecfg_strb_pulse_width_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnapbmaster_timeout_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobe_addr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobe_lastmux_isolate_attr == SERDES_IP_CMN_L3_CFG_CMNAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobeadc_current_direction_attr == SERDES_IP_CMN_L3_CFG_CMNAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobeadc_resistor_enable_attr == SERDES_IP_CMN_L3_CFG_CMNAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobedac_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobedac_en_attr == SERDES_IP_CMN_L3_CFG_CMNAPROBEDAC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobedacctrl_block_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobedacctrl_en_attr == SERDES_IP_CMN_L3_CFG_CMNAPROBEDACCTRL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobedacctrl_mask_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobedacctrl_rotate_left_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnaprobedacctrl_tstbus_clkdiv_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnbias_icc20uadj_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnbias_icc80uadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnbias_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnbias_termcal_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnbscan_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnbshihyst_attr == SERDES_IP_CMN_L3_CFG_CMNBSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_bg_en_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_bg_one_step_cal_en_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_fg_inc_cal_en_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_fg_one_step_cal_en_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_finish_side_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_initval_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_invert_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_restore_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_round_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_runcount_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetfsm_signmagen_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_SYNTHDUTYOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncaldac_synthdutyoffsetmeas_req_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALDAC_SYNTHDUTYOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncaldacbg_abort_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncaldacbg_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncaldacbg_ready_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncaldacfsm_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncaldacfsm_synthdutyoffsetfsm_clear_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncaldacfsm_synthdutyoffsetfsm_init_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncaldacfsm_synthdutyoffsetfsm_req_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALDACFSM_SYNTHDUTYOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncaldacsynthdutyoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALDACSYNTHDUTYOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncaldacsynthdutyoffsetfsmout_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALDACSYNTHDUTYOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalptr_pstate_rcomp_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalptr_pstate_synthdutyoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalptr_quad_rcomp_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalptr_quad_regopampoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalptr_quad_synthdutyoffset_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_biastrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_cap_tune_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_divrate_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_mode_select_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_ref_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMP_REF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_rx_term_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMP_RX_TERM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_tfr_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMP_TFR_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_tx_term_pd_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMP_TX_TERM_PD_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_tx_term_pu_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMP_TX_TERM_PU_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_txterm_nmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcomp_txterm_pmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_clear_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_code_delay_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_init_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rcomp_tfr_init_cal_value_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rcomp_tfr_max_value_attr == 4'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rcomp_tfr_min_value_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rcomp_txpd_valid_code_lut_vf00_attr == 32'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rcomp_txpd_valid_code_lut_vf01_attr == 32'd4246868100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rcomp_txpu_valid_code_lut_vf00_attr == 32'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rcomp_txpu_valid_code_lut_vf01_attr == 32'd4246868100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_req_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rx_comp_inv_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_RX_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rx_init_cal_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rx_initval_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rx_step_sign_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_RX_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_rx_termcode_delta_lut_attr == 31'd24084352
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tfr_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tfr_comp_inv_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_TFR_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tfr_initval_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tfr_step_sign_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_TFR_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tfr_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_time_comp_config_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_time_lpfsetup_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_time_mode_setup_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_time_reset_release_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_time_sample_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tx_pd_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tx_pd_init_cal_value_attr == 6'd49
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tx_pd_max_value_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tx_pd_min_value_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tx_pu_capcode_value_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tx_pu_init_cal_value_attr == 6'd49
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tx_pu_max_value_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_tx_pu_min_value_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_txpd_comp_inv_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_TXPD_COMP_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_txpd_initval_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_txpd_step_sign_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_TXPD_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_txpd_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_txpu_comp_inv_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_TXPU_COMP_INV_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_txpu_initval_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_txpu_step_sign_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPFSM_TXPU_STEP_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_txpu_termcode_delta_lut_attr == 31'd2147483647
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompfsm_txterm_pmos_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmaster_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPMASTER_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmaster_rx_locovr_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmaster_tfr_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmaster_txpd_locovr_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmaster_txpu_locovr_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmaster_valid_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALRCOMPMASTER_VALID_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmeas_dlycount_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalrcompmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffset_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_clear_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_finish_side_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_init_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_invert_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_req_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsm_runcount_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetfsmout_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetmeas_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetmeas_req_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmncalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_avg_en_attr == SERDES_IP_CMN_L3_CFG_CMNCKM_AVG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_clk_en_attr == SERDES_IP_CMN_L3_CFG_CMNCKM_CLK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_continuous_attr == SERDES_IP_CMN_L3_CFG_CMNCKM_CONTINUOUS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_dig_meas_en_attr == SERDES_IP_CMN_L3_CFG_CMNCKM_DIG_MEAS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_dig_meas_err_clr_attr == SERDES_IP_CMN_L3_CFG_CMNCKM_DIG_MEAS_ERR_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_en_attr == SERDES_IP_CMN_L3_CFG_CMNCKM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_max_thr_attr == 25'd33554431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_meas_ck_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_ref_ck_div_ratio_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_result_clr_attr == SERDES_IP_CMN_L3_CFG_CMNCKM_RESULT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_start_attr == SERDES_IP_CMN_L3_CFG_CMNCKM_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_wdt_interval_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnckm_win_thr_ref_attr == 25'd16777215
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnclk_keepalive_en_b_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnclk_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmndmondac_en_attr == SERDES_IP_CMN_L3_CFG_CMNDMONDAC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnfsm_cken_ovr_attr == SERDES_IP_CMN_L3_CFG_CMNFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnfsm_cken_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_aprobe1_charge_up_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_APROBE1_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_aprobe1_pull_dn_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_APROBE1_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_aprobe1_sense_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_APROBE1_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_aprobe2_charge_up_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_APROBE2_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_aprobe2_pull_dn_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_APROBE2_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_aprobe2_sense_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_APROBE2_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_changeref_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_changeref_val_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_en_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_CMN_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_ntl_sel_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_CMN_NTL_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_cmn_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_refckm_charge_up_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_REFCKM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_refckm_pull_dn_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_REFCKM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_refckm_sense_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_REFCKM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_refckp_charge_up_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_REFCKP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_refckp_pull_dn_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_REFCKP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnntl_refckp_sense_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNNTL_REFCKP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnpcs_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnpcs_ref_sel_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnpcs_ref_sel_tx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnperfmon_compare_val_start_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnperfmon_compare_val_stop_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnperfmon_en_attr == SERDES_IP_CMN_L3_CFG_CMNPERFMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnperfmon_mask_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprefckbufprelut_delta_attr == 15'd32767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprefckbufprelut_init_termcal_rx_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprefckbufprelut_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNRCOMPREFCKBUFPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprefckbufprelut_termcal_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprefcktxdrvprelut_delta_attr == 15'd4672
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprefcktxdrvprelut_init_termcal_rx_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprefcktxdrvprelut_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNRCOMPREFCKTXDRVPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprefcktxdrvprelut_termcal_rx_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprxdfeprelut_delta_attr == 15'd32767
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprxdfeprelut_init_termcal_tfr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprxdfeprelut_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNRCOMPRXDFEPRELUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrcomprxdfeprelut_termcal_tfr_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckbuf_cml_ena_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKBUF_CML_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckbuf_hs_cmos_ena_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKBUF_HS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckbuf_hs_ls_b_path_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKBUF_HS_LS_B_PATH_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckbuf_hs_ref_to_cdrdiv_ena_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKBUF_HS_REF_TO_CDRDIV_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckbuf_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKBUF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckbuf_ls_cmos_ena_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKBUF_LS_CMOS_ENA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckbuf_powersave_b_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKBUF_POWERSAVE_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckbuf_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckbuf_termhiz_b_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKBUF_TERMHIZ_B_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrefckdrv_powersave_en_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKDRV_POWERSAVE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrefcktxdrv_cdrdiv_en_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKTXDRV_CDRDIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrefcktxdrv_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNREFCKTXDRV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrefcktxdrv_termcal_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_en_b_attr == SERDES_IP_CMN_L3_CFG_CMNRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_entry3_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s0q2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s0q3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s1q4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s1q5_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s1q6_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s1q7_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evdn_delay_lut_sel_s2q0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_entry2_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_entry3_attr == 13'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_entry4_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_entry5_attr == 13'd62
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_entry6_attr == 13'd390
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_entry7_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s0q2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s0q3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s1q1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s1q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s1q5_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s1q7_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpu_evup_delay_lut_sel_s2q0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_dacsynthdutyoffsetfsm_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_devicetrim_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_devicetrim_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_term_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_term_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_term_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_term_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_term_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_term_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_term_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_cal_term_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_keepalive_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_keepalive_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpuetr_reg_pwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_bias_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_bias_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_refckbuf_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_refckbuf_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_refckbuf_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_refckbuf_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_rxref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_rxref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_rxref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_rxref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_synthdutycomp_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_synthdutycomp_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_synthdutycomp_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_synthdutycomp_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_synthlcslowref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_synthlcslowref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_synthlcslowref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_synthlcslowref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_txref_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_txref_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_txref_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpupd_txref_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpurst_regreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpurst_regreset_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpurst_regreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrpurst_regreset_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_aetrcmn_regpwrupacc_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_AETRCMN_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_aetrcmn_regpwrupacc_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_AETRCMN_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_adc_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_adc_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_ADC_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_biasicc_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_biasicc_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_ntl_b_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_ntl_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_refckbuf_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_refckbuf_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_REFCKBUF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_reg_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_reg_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_rxref_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_RXREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_rxref_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_RXREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_synthlcslowref_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_SYNTHLCSLOWREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_synthlcslowref_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_SYNTHLCSLOWREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_txref_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_TXREF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_apdcmn_txref_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_APDCMN_TXREF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_arstcmn_adc_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_ARSTCMN_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_arstcmn_adc_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_ARSTCMN_ADC_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_arstcmn_aprobedac_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_ARSTCMN_APROBEDAC_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_arstcmn_refcktxdrv_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_ARSTCMN_REFCKTXDRV_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_arstcmn_refcktxdrv_hiz_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_ARSTCMN_REFCKTXDRV_HIZ_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_arstcmn_regreset_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_ARSTCMN_REGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_arstcmn_regreset_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_ARSTCMN_REGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_synthdutycomp_ovr_b_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_SYNTHDUTYCOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrstpdovr_synthdutycomp_ovren_attr == SERDES_IP_CMN_L3_CFG_CMNRSTPDOVR_SYNTHDUTYCOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrxref_dpma_en_attr == SERDES_IP_CMN_L3_CFG_CMNRXREF_DPMA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrxref_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNRXREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnrxref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnspare0_attr == 32'd163
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnspare_attr == 9'd384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_rxlane0_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_rxlane1_timer_attr == 12'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_rxlane2_timer_attr == 12'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_rxlane3_timer_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_synthlcfast_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_synthlcmed_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_synthlcslow_timer_attr == 12'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_txlane0_timer_attr == 12'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_txlane1_timer_attr == 12'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_txlane2_timer_attr == 12'd70
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnstagger_txlane3_timer_attr == 12'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthdiv_cdrdiv_en_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHDIV_CDRDIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthdiv_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHDIV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthdiv_slowmed_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHDIV_SLOWMED_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthdutyoffsetcal_en_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHDUTYOFFSETCAL_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthdutyoffsetcal_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHDUTYOFFSETCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthdutysel_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHDUTYSEL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthdutysel_mux_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlccaldac_currentdacdcdmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlccaldac_currentdacdcdmeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlccaldac_currentdacdcdmeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlccaldac_currentdacdcdmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlccaldac_synthdutyoffsetmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlccaldac_tx_disable_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHLCCALDAC_TX_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlccaldacerr_calsynthdutyerr_locovr_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHLCCALDACERR_CALSYNTHDUTYERR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlccaldacerr_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHLCCALDACERR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlcslowref_dpma_en_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHLCSLOWREF_DPMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlcslowref_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNSYNTHLCSLOWREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnsynthlcslowref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmntxref_dpma_en_attr == SERDES_IP_CMN_L3_CFG_CMNTXREF_DPMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmntxref_locovren_attr == SERDES_IP_CMN_L3_CFG_CMNTXREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmntxref_sel_en_locovr_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_cmnynthdutyselpolarity_attr == SERDES_IP_CMN_L3_CFG_CMNYNTHDUTYSELPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_lbcmn_locovren_attr == SERDES_IP_CMN_L3_CFG_LBCMN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_lbcmn_synthlcslowmedpostdivclk2cdrrefclken_locovr_attr == SERDES_IP_CMN_L3_CFG_LBCMN_SYNTHLCSLOWMEDPOSTDIVCLK2CDRREFCLKEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_rcompmaster_en_locovr_attr == SERDES_IP_CMN_L3_CFG_RCOMPMASTER_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_rcompmaster_locovren_attr == SERDES_IP_CMN_L3_CFG_RCOMPMASTER_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_rcompslave_locovr_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_rcompslave_locovren_attr == SERDES_IP_CMN_L3_CFG_RCOMPSLAVE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_rcompslave_valid_locovr_attr == SERDES_IP_CMN_L3_CFG_RCOMPSLAVE_VALID_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_rcompterm_rx_termcode_base_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_rcompterm_tfr_termcode_base_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_rcompterm_txpd_termcode_base_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_rcompterm_txpu_termcode_base_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmed_locovren_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMED_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmed_txbitclkselect_locovr_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMED_TXBITCLKSELECT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedcaldac_locovren_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMEDCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedcalregopampoffset_locovren_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedcalregopampoffsetfsmout_locovren_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMEDCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedpcs_locovren_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMEDPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedpcs_postdiv2clk0_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedpcs_postdiv2clk0en_locovr_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMEDPCS_POSTDIV2CLK0EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedpcs_postdivclk0en_locovr_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMEDPCS_POSTDIVCLK0EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedreg_lev_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_cmn_l3_cfg_synthlcslowmedreg_locovren_attr == SERDES_IP_CMN_L3_CFG_SYNTHLCSLOWMEDREG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_clock_ratio_cnt_max_timer_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_clock_ratio_cnt_min_timer_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_enable_flex_override_en_attr == SERDES_IP_FLEX_FW_LOADER_L0_CFG_CFG_ENABLE_FLEX_OVERRIDE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_enable_flex_override_value_attr == SERDES_IP_FLEX_FW_LOADER_L0_CFG_CFG_ENABLE_FLEX_OVERRIDE_VALUE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_flex_gpi_attr == 17'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_gp_lvl_attr == SERDES_IP_FLEX_FW_LOADER_L0_CFG_CFG_GP_LVL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_gp_pls_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_lms_cont_dis_attr == SERDES_IP_FLEX_FW_LOADER_L0_CFG_CFG_LMS_CONT_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_local_tp_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_periodical_rst_dis_attr == SERDES_IP_FLEX_FW_LOADER_L0_CFG_CFG_PERIODICAL_RST_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_spa_sat_dir_attr == SERDES_IP_FLEX_FW_LOADER_L0_CFG_CFG_SPA_SAT_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l0_cfg_cfg_vg_inv_cb_attr == SERDES_IP_FLEX_FW_LOADER_L0_CFG_CFG_VG_INV_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l0_cfg_data_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l0_cfg_fw_loader_en_attr == SERDES_IP_FLEX_FW_LOADER_L0_CFG_FW_LOADER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l0_cfg_offset_addr_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l0_cfg_single_mode_en_attr == SERDES_IP_FLEX_FW_LOADER_L0_CFG_SINGLE_MODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_clock_ratio_cnt_max_timer_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_clock_ratio_cnt_min_timer_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_enable_flex_override_en_attr == SERDES_IP_FLEX_FW_LOADER_L1_CFG_CFG_ENABLE_FLEX_OVERRIDE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_enable_flex_override_value_attr == SERDES_IP_FLEX_FW_LOADER_L1_CFG_CFG_ENABLE_FLEX_OVERRIDE_VALUE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_flex_gpi_attr == 17'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_gp_lvl_attr == SERDES_IP_FLEX_FW_LOADER_L1_CFG_CFG_GP_LVL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_gp_pls_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_lms_cont_dis_attr == SERDES_IP_FLEX_FW_LOADER_L1_CFG_CFG_LMS_CONT_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_local_tp_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_periodical_rst_dis_attr == SERDES_IP_FLEX_FW_LOADER_L1_CFG_CFG_PERIODICAL_RST_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_spa_sat_dir_attr == SERDES_IP_FLEX_FW_LOADER_L1_CFG_CFG_SPA_SAT_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l1_cfg_cfg_vg_inv_cb_attr == SERDES_IP_FLEX_FW_LOADER_L1_CFG_CFG_VG_INV_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l1_cfg_data_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l1_cfg_fw_loader_en_attr == SERDES_IP_FLEX_FW_LOADER_L1_CFG_FW_LOADER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l1_cfg_offset_addr_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l1_cfg_single_mode_en_attr == SERDES_IP_FLEX_FW_LOADER_L1_CFG_SINGLE_MODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_clock_ratio_cnt_max_timer_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_clock_ratio_cnt_min_timer_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_enable_flex_override_en_attr == SERDES_IP_FLEX_FW_LOADER_L2_CFG_CFG_ENABLE_FLEX_OVERRIDE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_enable_flex_override_value_attr == SERDES_IP_FLEX_FW_LOADER_L2_CFG_CFG_ENABLE_FLEX_OVERRIDE_VALUE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_flex_gpi_attr == 17'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_gp_lvl_attr == SERDES_IP_FLEX_FW_LOADER_L2_CFG_CFG_GP_LVL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_gp_pls_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_lms_cont_dis_attr == SERDES_IP_FLEX_FW_LOADER_L2_CFG_CFG_LMS_CONT_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_local_tp_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_periodical_rst_dis_attr == SERDES_IP_FLEX_FW_LOADER_L2_CFG_CFG_PERIODICAL_RST_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_spa_sat_dir_attr == SERDES_IP_FLEX_FW_LOADER_L2_CFG_CFG_SPA_SAT_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l2_cfg_cfg_vg_inv_cb_attr == SERDES_IP_FLEX_FW_LOADER_L2_CFG_CFG_VG_INV_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l2_cfg_data_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l2_cfg_fw_loader_en_attr == SERDES_IP_FLEX_FW_LOADER_L2_CFG_FW_LOADER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l2_cfg_offset_addr_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l2_cfg_single_mode_en_attr == SERDES_IP_FLEX_FW_LOADER_L2_CFG_SINGLE_MODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_clock_ratio_cnt_max_timer_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_clock_ratio_cnt_min_timer_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_enable_flex_override_en_attr == SERDES_IP_FLEX_FW_LOADER_L3_CFG_CFG_ENABLE_FLEX_OVERRIDE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_enable_flex_override_value_attr == SERDES_IP_FLEX_FW_LOADER_L3_CFG_CFG_ENABLE_FLEX_OVERRIDE_VALUE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_flex_gpi_attr == 17'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_gp_lvl_attr == SERDES_IP_FLEX_FW_LOADER_L3_CFG_CFG_GP_LVL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_gp_pls_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_lms_cont_dis_attr == SERDES_IP_FLEX_FW_LOADER_L3_CFG_CFG_LMS_CONT_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_local_tp_mode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_periodical_rst_dis_attr == SERDES_IP_FLEX_FW_LOADER_L3_CFG_CFG_PERIODICAL_RST_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_spa_sat_dir_attr == SERDES_IP_FLEX_FW_LOADER_L3_CFG_CFG_SPA_SAT_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l3_cfg_cfg_vg_inv_cb_attr == SERDES_IP_FLEX_FW_LOADER_L3_CFG_CFG_VG_INV_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l3_cfg_data_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l3_cfg_fw_loader_en_attr == SERDES_IP_FLEX_FW_LOADER_L3_CFG_FW_LOADER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l3_cfg_offset_addr_for_fw_load_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_flex_fw_loader_l3_cfg_single_mode_en_attr == SERDES_IP_FLEX_FW_LOADER_L3_CFG_SINGLE_MODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_cpi_port_mode_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_dfx_secure_visa_nt_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_dfx_secure_visa_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_DFX_SECURE_VISA_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_p_vdd_pwrgood_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_P_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_p_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_P_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pa_vdd_ehv_pwrgood_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pa_vdd_ehv_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pa_vdd_pwrgood_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PA_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pa_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PA_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_andme_en_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_ANDME_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_andme_en_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_ANDME_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bist_modesel_l0_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bist_modesel_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BIST_MODESEL_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_capturedr_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_CAPTUREDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_clamp_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_CLAMP_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_exit1dr_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_EXIT1DR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_exit2dr_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_EXIT2DR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_extest_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_EXTEST_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_extestpulse_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_EXTESTPULSE_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_extesttrain_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_EXTESTTRAIN_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_highz_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_HIGHZ_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_mode_en_nt_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_MODE_EN_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_preload_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_PRELOAD_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_runtestidle_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_RUNTESTIDLE_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_shiftdr_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_SHIFTDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_txinvert_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_TXINVERT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_bs_updatedr_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_BS_UPDATEDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_cmn_force_pup_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_CMN_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_cmn_force_pup_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_CMN_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_disconnect_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_DISCONNECT_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_disconnect_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_DISCONNECT_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_isolate_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_ISOLATE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_isolate_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_ISOLATE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_jtagid_nt_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_JTAGID_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_jtagslvid_nt_int_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_JTAGSLVID_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_lb_cdrclk2txen_l0_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_LB_CDRCLK2TXEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_lb_cdrclk2txen_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_LB_CDRCLK2TXEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_lb_parrx2txtimeden_l0_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_LB_PARRX2TXTIMEDEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_lb_parrx2txtimeden_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_LB_PARRX2TXTIMEDEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_lb_tx2rxbuftimeden_l0_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_LB_TX2RXBUFTIMEDEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_lb_tx2rxbuftimeden_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_LB_TX2RXBUFTIMEDEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_lfps_en_l0_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_LFPS_EN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_lfps_en_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_LFPS_EN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_mode_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_MODE_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_mode_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_MODE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_pcie_l1d1_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_PCIE_L1D1_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_pcie_l1d1_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_PCIE_L1D1_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_pcie_l1d2_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_PCIE_L1D2_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_pcie_l1d2_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_PCIE_L1D2_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rcomp_slave_en_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RCOMP_SLAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rcomp_slave_en_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RCOMP_SLAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rcomp_slave_nt_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rcomp_slave_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RCOMP_SLAVE_NT_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rcomp_slave_valid_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RCOMP_SLAVE_VALID_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rcomp_slave_valid_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RCOMP_SLAVE_VALID_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_ref_sel_rx_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_ref_sel_rx_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_REF_SEL_RX_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_ref_sel_tx_nt_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_ref_sel_tx_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_REF_SEL_TX_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_ref_term_hiz_en_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_REF_TERM_HIZ_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_ref_term_hiz_en_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_REF_TERM_HIZ_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxbist_en_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXBIST_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxbist_en_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXBIST_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxbitslip_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXBITSLIP_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxbitslip_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXBITSLIP_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeiosdetectstat_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEIOSDETECTSTAT_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeiosdetectstat_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEIOSDETECTSTAT_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeq_clr_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEQ_CLR_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeq_clr_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEQ_CLR_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeq_precal_code_sel_l0_nt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeq_precal_code_sel_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEQ_PRECAL_CODE_SEL_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeq_start_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEQ_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeq_start_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEQ_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeq_static_en_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEQ_STATIC_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeq_static_en_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEQ_STATIC_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeyediag_start_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEYEDIAG_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxeyediag_start_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXEYEDIAG_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_direction_l0_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXMARGIN_DIRECTION_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_direction_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXMARGIN_DIRECTION_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_mode_l0_nt_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXMARGIN_MODE_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_mode_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXMARGIN_MODE_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_offset_change_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXMARGIN_OFFSET_CHANGE_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_offset_change_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXMARGIN_OFFSET_CHANGE_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_offset_l0_nt_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_offset_l0_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXMARGIN_OFFSET_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_start_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXMARGIN_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxmargin_start_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXMARGIN_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxpam_gray_en_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXPAM_GRAY_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxpam_gray_en_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXPAM_GRAY_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxpam_precode_en_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXPAM_PRECODE_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxpam_precode_en_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXPAM_PRECODE_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxrate_l0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxrate_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxterm_hiz_en_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXTERM_HIZ_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxterm_hiz_en_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXTERM_HIZ_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxwidth_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_rxwidth_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_RXWIDTH_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_spare_nt_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_spare_nt_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SPARE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcfast_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcfast_divrate_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SYNTHLCFAST_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcfast_force_pup_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SYNTHLCFAST_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcfast_force_pup_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SYNTHLCFAST_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcmed_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcmed_divrate_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SYNTHLCMED_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcmed_force_pup_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SYNTHLCMED_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcmed_force_pup_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SYNTHLCMED_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcslow_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcslow_divrate_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SYNTHLCSLOW_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcslow_force_pup_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SYNTHLCSLOW_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_synthlcslow_force_pup_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_SYNTHLCSLOW_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txbeacon_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXBEACON_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txbeacon_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXBEACON_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txbist_en_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXBIST_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txbist_en_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXBIST_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txclkdivrate_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txclkdivrate_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXCLKDIVRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdetectrx_req_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXDETECTRX_REQ_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdetectrx_req_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXDETECTRX_REQ_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_levn_l0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_levn_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXDRV_LEVN_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_levnm1_l0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_levnm1_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXDRV_LEVNM1_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_levnm2_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_levnm2_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXDRV_LEVNM2_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_levnp1_l0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_levnp1_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXDRV_LEVNP1_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_slew_l0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_slew_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXDRV_SLEW_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_spare_l0_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txdrv_spare_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXDRV_SPARE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txenable_l0_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXENABLE_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txenable_l0_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXENABLE_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txpam_gray_en_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXPAM_GRAY_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txpam_gray_en_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXPAM_GRAY_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txpam_precode_en_a_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXPAM_PRECODE_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txpam_precode_en_a_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXPAM_PRECODE_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txrate_l0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txrate_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txwidth_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_pcs_txwidth_l0_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_PCS_TXWIDTH_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_visa_unit_id_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_ictl_visa_unit_id_reg_en_attr == SERDES_IP_IF_L0_CFG_ICTL_VISA_UNIT_ID_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_idat_dfx_obs_dig_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_idat_visa_serial_cfg_in_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_irst_apb_mem_b_attr == SERDES_IP_IF_L0_CFG_IRST_APB_MEM_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_irst_apb_mem_b_reg_en_attr == SERDES_IP_IF_L0_CFG_IRST_APB_MEM_B_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_irst_pcs_rx_l0_b_a_attr == SERDES_IP_IF_L0_CFG_IRST_PCS_RX_L0_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_irst_pcs_rx_l0_b_a_reg_en_attr == SERDES_IP_IF_L0_CFG_IRST_PCS_RX_L0_B_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_irst_pcs_tstbus_b_a_attr == SERDES_IP_IF_L0_CFG_IRST_PCS_TSTBUS_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_irst_pcs_tx_l0_b_a_attr == SERDES_IP_IF_L0_CFG_IRST_PCS_TX_L0_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_irst_pcs_tx_l0_b_a_reg_en_attr == SERDES_IP_IF_L0_CFG_IRST_PCS_TX_L0_B_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l0_cfg_irst_visa_reset_b_a_attr == SERDES_IP_IF_L0_CFG_IRST_VISA_RESET_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_cpi_port_mode_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_dfx_secure_visa_nt_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_dfx_secure_visa_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_DFX_SECURE_VISA_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_p_vdd_pwrgood_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_P_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_p_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_P_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pa_vdd_ehv_pwrgood_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pa_vdd_ehv_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pa_vdd_pwrgood_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PA_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pa_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PA_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_andme_en_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_ANDME_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_andme_en_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_ANDME_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bist_modesel_l0_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bist_modesel_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BIST_MODESEL_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_capturedr_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_CAPTUREDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_clamp_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_CLAMP_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_exit1dr_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_EXIT1DR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_exit2dr_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_EXIT2DR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_extest_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_EXTEST_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_extestpulse_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_EXTESTPULSE_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_extesttrain_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_EXTESTTRAIN_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_highz_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_HIGHZ_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_mode_en_nt_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_MODE_EN_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_preload_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_PRELOAD_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_runtestidle_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_RUNTESTIDLE_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_shiftdr_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_SHIFTDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_txinvert_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_TXINVERT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_bs_updatedr_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_BS_UPDATEDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_cmn_force_pup_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_CMN_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_cmn_force_pup_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_CMN_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_disconnect_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_DISCONNECT_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_disconnect_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_DISCONNECT_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_isolate_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_ISOLATE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_isolate_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_ISOLATE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_jtagid_nt_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_JTAGID_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_jtagslvid_nt_int_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_JTAGSLVID_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_lb_cdrclk2txen_l0_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_LB_CDRCLK2TXEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_lb_cdrclk2txen_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_LB_CDRCLK2TXEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_lb_parrx2txtimeden_l0_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_LB_PARRX2TXTIMEDEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_lb_parrx2txtimeden_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_LB_PARRX2TXTIMEDEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_lb_tx2rxbuftimeden_l0_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_LB_TX2RXBUFTIMEDEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_lb_tx2rxbuftimeden_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_LB_TX2RXBUFTIMEDEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_lfps_en_l0_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_LFPS_EN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_lfps_en_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_LFPS_EN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_mode_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_MODE_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_mode_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_MODE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_pcie_l1d1_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_PCIE_L1D1_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_pcie_l1d1_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_PCIE_L1D1_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_pcie_l1d2_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_PCIE_L1D2_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_pcie_l1d2_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_PCIE_L1D2_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rcomp_slave_en_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RCOMP_SLAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rcomp_slave_en_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RCOMP_SLAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rcomp_slave_nt_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rcomp_slave_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RCOMP_SLAVE_NT_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rcomp_slave_valid_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RCOMP_SLAVE_VALID_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rcomp_slave_valid_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RCOMP_SLAVE_VALID_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_ref_sel_rx_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_ref_sel_rx_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_REF_SEL_RX_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_ref_sel_tx_nt_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_ref_sel_tx_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_REF_SEL_TX_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_ref_term_hiz_en_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_REF_TERM_HIZ_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_ref_term_hiz_en_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_REF_TERM_HIZ_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxbist_en_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXBIST_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxbist_en_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXBIST_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxbitslip_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXBITSLIP_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxbitslip_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXBITSLIP_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeiosdetectstat_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEIOSDETECTSTAT_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeiosdetectstat_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEIOSDETECTSTAT_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeq_clr_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEQ_CLR_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeq_clr_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEQ_CLR_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeq_precal_code_sel_l0_nt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeq_precal_code_sel_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEQ_PRECAL_CODE_SEL_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeq_start_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEQ_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeq_start_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEQ_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeq_static_en_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEQ_STATIC_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeq_static_en_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEQ_STATIC_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeyediag_start_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEYEDIAG_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxeyediag_start_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXEYEDIAG_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_direction_l0_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXMARGIN_DIRECTION_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_direction_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXMARGIN_DIRECTION_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_mode_l0_nt_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXMARGIN_MODE_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_mode_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXMARGIN_MODE_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_offset_change_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXMARGIN_OFFSET_CHANGE_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_offset_change_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXMARGIN_OFFSET_CHANGE_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_offset_l0_nt_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_offset_l0_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXMARGIN_OFFSET_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_start_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXMARGIN_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxmargin_start_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXMARGIN_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxpam_gray_en_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXPAM_GRAY_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxpam_gray_en_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXPAM_GRAY_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxpam_precode_en_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXPAM_PRECODE_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxpam_precode_en_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXPAM_PRECODE_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxrate_l0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxrate_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxterm_hiz_en_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXTERM_HIZ_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxterm_hiz_en_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXTERM_HIZ_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxwidth_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_rxwidth_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_RXWIDTH_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_spare_nt_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_spare_nt_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SPARE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcfast_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcfast_divrate_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SYNTHLCFAST_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcfast_force_pup_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SYNTHLCFAST_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcfast_force_pup_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SYNTHLCFAST_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcmed_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcmed_divrate_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SYNTHLCMED_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcmed_force_pup_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SYNTHLCMED_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcmed_force_pup_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SYNTHLCMED_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcslow_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcslow_divrate_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SYNTHLCSLOW_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcslow_force_pup_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SYNTHLCSLOW_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_synthlcslow_force_pup_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_SYNTHLCSLOW_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txbeacon_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXBEACON_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txbeacon_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXBEACON_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txbist_en_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXBIST_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txbist_en_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXBIST_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txclkdivrate_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txclkdivrate_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXCLKDIVRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdetectrx_req_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXDETECTRX_REQ_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdetectrx_req_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXDETECTRX_REQ_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_levn_l0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_levn_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXDRV_LEVN_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_levnm1_l0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_levnm1_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXDRV_LEVNM1_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_levnm2_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_levnm2_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXDRV_LEVNM2_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_levnp1_l0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_levnp1_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXDRV_LEVNP1_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_slew_l0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_slew_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXDRV_SLEW_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_spare_l0_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txdrv_spare_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXDRV_SPARE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txenable_l0_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXENABLE_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txenable_l0_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXENABLE_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txpam_gray_en_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXPAM_GRAY_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txpam_gray_en_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXPAM_GRAY_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txpam_precode_en_a_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXPAM_PRECODE_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txpam_precode_en_a_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXPAM_PRECODE_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txrate_l0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txrate_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txwidth_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_pcs_txwidth_l0_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_PCS_TXWIDTH_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_visa_unit_id_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_ictl_visa_unit_id_reg_en_attr == SERDES_IP_IF_L1_CFG_ICTL_VISA_UNIT_ID_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_idat_dfx_obs_dig_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_idat_visa_serial_cfg_in_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_irst_apb_mem_b_attr == SERDES_IP_IF_L1_CFG_IRST_APB_MEM_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_irst_apb_mem_b_reg_en_attr == SERDES_IP_IF_L1_CFG_IRST_APB_MEM_B_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_irst_pcs_rx_l0_b_a_attr == SERDES_IP_IF_L1_CFG_IRST_PCS_RX_L0_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_irst_pcs_rx_l0_b_a_reg_en_attr == SERDES_IP_IF_L1_CFG_IRST_PCS_RX_L0_B_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_irst_pcs_tstbus_b_a_attr == SERDES_IP_IF_L1_CFG_IRST_PCS_TSTBUS_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_irst_pcs_tx_l0_b_a_attr == SERDES_IP_IF_L1_CFG_IRST_PCS_TX_L0_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_irst_pcs_tx_l0_b_a_reg_en_attr == SERDES_IP_IF_L1_CFG_IRST_PCS_TX_L0_B_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l1_cfg_irst_visa_reset_b_a_attr == SERDES_IP_IF_L1_CFG_IRST_VISA_RESET_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_cpi_port_mode_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_dfx_secure_visa_nt_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_dfx_secure_visa_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_DFX_SECURE_VISA_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_p_vdd_pwrgood_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_P_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_p_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_P_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pa_vdd_ehv_pwrgood_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pa_vdd_ehv_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pa_vdd_pwrgood_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PA_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pa_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PA_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_andme_en_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_ANDME_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_andme_en_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_ANDME_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bist_modesel_l0_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bist_modesel_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BIST_MODESEL_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_capturedr_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_CAPTUREDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_clamp_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_CLAMP_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_exit1dr_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_EXIT1DR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_exit2dr_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_EXIT2DR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_extest_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_EXTEST_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_extestpulse_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_EXTESTPULSE_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_extesttrain_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_EXTESTTRAIN_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_highz_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_HIGHZ_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_mode_en_nt_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_MODE_EN_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_preload_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_PRELOAD_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_runtestidle_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_RUNTESTIDLE_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_shiftdr_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_SHIFTDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_txinvert_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_TXINVERT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_bs_updatedr_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_BS_UPDATEDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_cmn_force_pup_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_CMN_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_cmn_force_pup_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_CMN_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_disconnect_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_DISCONNECT_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_disconnect_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_DISCONNECT_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_isolate_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_ISOLATE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_isolate_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_ISOLATE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_jtagid_nt_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_JTAGID_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_jtagslvid_nt_int_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_JTAGSLVID_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_lb_cdrclk2txen_l0_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_LB_CDRCLK2TXEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_lb_cdrclk2txen_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_LB_CDRCLK2TXEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_lb_parrx2txtimeden_l0_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_LB_PARRX2TXTIMEDEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_lb_parrx2txtimeden_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_LB_PARRX2TXTIMEDEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_lb_tx2rxbuftimeden_l0_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_LB_TX2RXBUFTIMEDEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_lb_tx2rxbuftimeden_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_LB_TX2RXBUFTIMEDEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_lfps_en_l0_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_LFPS_EN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_lfps_en_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_LFPS_EN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_mode_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_MODE_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_mode_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_MODE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_pcie_l1d1_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_PCIE_L1D1_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_pcie_l1d1_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_PCIE_L1D1_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_pcie_l1d2_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_PCIE_L1D2_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_pcie_l1d2_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_PCIE_L1D2_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rcomp_slave_en_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RCOMP_SLAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rcomp_slave_en_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RCOMP_SLAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rcomp_slave_nt_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rcomp_slave_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RCOMP_SLAVE_NT_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rcomp_slave_valid_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RCOMP_SLAVE_VALID_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rcomp_slave_valid_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RCOMP_SLAVE_VALID_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_ref_sel_rx_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_ref_sel_rx_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_REF_SEL_RX_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_ref_sel_tx_nt_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_ref_sel_tx_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_REF_SEL_TX_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_ref_term_hiz_en_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_REF_TERM_HIZ_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_ref_term_hiz_en_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_REF_TERM_HIZ_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxbist_en_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXBIST_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxbist_en_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXBIST_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxbitslip_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXBITSLIP_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxbitslip_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXBITSLIP_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeiosdetectstat_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEIOSDETECTSTAT_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeiosdetectstat_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEIOSDETECTSTAT_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeq_clr_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEQ_CLR_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeq_clr_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEQ_CLR_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeq_precal_code_sel_l0_nt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeq_precal_code_sel_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEQ_PRECAL_CODE_SEL_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeq_start_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEQ_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeq_start_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEQ_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeq_static_en_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEQ_STATIC_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeq_static_en_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEQ_STATIC_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeyediag_start_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEYEDIAG_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxeyediag_start_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXEYEDIAG_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_direction_l0_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXMARGIN_DIRECTION_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_direction_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXMARGIN_DIRECTION_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_mode_l0_nt_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXMARGIN_MODE_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_mode_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXMARGIN_MODE_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_offset_change_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXMARGIN_OFFSET_CHANGE_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_offset_change_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXMARGIN_OFFSET_CHANGE_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_offset_l0_nt_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_offset_l0_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXMARGIN_OFFSET_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_start_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXMARGIN_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxmargin_start_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXMARGIN_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxpam_gray_en_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXPAM_GRAY_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxpam_gray_en_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXPAM_GRAY_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxpam_precode_en_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXPAM_PRECODE_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxpam_precode_en_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXPAM_PRECODE_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxrate_l0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxrate_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxterm_hiz_en_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXTERM_HIZ_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxterm_hiz_en_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXTERM_HIZ_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxwidth_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_rxwidth_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_RXWIDTH_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_spare_nt_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_spare_nt_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SPARE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcfast_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcfast_divrate_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SYNTHLCFAST_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcfast_force_pup_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SYNTHLCFAST_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcfast_force_pup_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SYNTHLCFAST_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcmed_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcmed_divrate_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SYNTHLCMED_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcmed_force_pup_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SYNTHLCMED_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcmed_force_pup_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SYNTHLCMED_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcslow_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcslow_divrate_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SYNTHLCSLOW_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcslow_force_pup_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SYNTHLCSLOW_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_synthlcslow_force_pup_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_SYNTHLCSLOW_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txbeacon_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXBEACON_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txbeacon_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXBEACON_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txbist_en_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXBIST_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txbist_en_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXBIST_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txclkdivrate_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txclkdivrate_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXCLKDIVRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdetectrx_req_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXDETECTRX_REQ_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdetectrx_req_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXDETECTRX_REQ_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_levn_l0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_levn_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXDRV_LEVN_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_levnm1_l0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_levnm1_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXDRV_LEVNM1_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_levnm2_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_levnm2_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXDRV_LEVNM2_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_levnp1_l0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_levnp1_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXDRV_LEVNP1_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_slew_l0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_slew_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXDRV_SLEW_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_spare_l0_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txdrv_spare_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXDRV_SPARE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txenable_l0_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXENABLE_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txenable_l0_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXENABLE_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txpam_gray_en_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXPAM_GRAY_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txpam_gray_en_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXPAM_GRAY_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txpam_precode_en_a_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXPAM_PRECODE_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txpam_precode_en_a_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXPAM_PRECODE_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txrate_l0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txrate_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txwidth_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_pcs_txwidth_l0_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_PCS_TXWIDTH_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_visa_unit_id_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_ictl_visa_unit_id_reg_en_attr == SERDES_IP_IF_L2_CFG_ICTL_VISA_UNIT_ID_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_idat_dfx_obs_dig_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_idat_visa_serial_cfg_in_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_irst_apb_mem_b_attr == SERDES_IP_IF_L2_CFG_IRST_APB_MEM_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_irst_apb_mem_b_reg_en_attr == SERDES_IP_IF_L2_CFG_IRST_APB_MEM_B_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_irst_pcs_rx_l0_b_a_attr == SERDES_IP_IF_L2_CFG_IRST_PCS_RX_L0_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_irst_pcs_rx_l0_b_a_reg_en_attr == SERDES_IP_IF_L2_CFG_IRST_PCS_RX_L0_B_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_irst_pcs_tstbus_b_a_attr == SERDES_IP_IF_L2_CFG_IRST_PCS_TSTBUS_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_irst_pcs_tx_l0_b_a_attr == SERDES_IP_IF_L2_CFG_IRST_PCS_TX_L0_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_irst_pcs_tx_l0_b_a_reg_en_attr == SERDES_IP_IF_L2_CFG_IRST_PCS_TX_L0_B_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l2_cfg_irst_visa_reset_b_a_attr == SERDES_IP_IF_L2_CFG_IRST_VISA_RESET_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_cpi_port_mode_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_dfx_secure_visa_nt_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_dfx_secure_visa_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_DFX_SECURE_VISA_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_p_vdd_pwrgood_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_P_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_p_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_P_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pa_vdd_ehv_pwrgood_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pa_vdd_ehv_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PA_VDD_EHV_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pa_vdd_pwrgood_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PA_VDD_PWRGOOD_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pa_vdd_pwrgood_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PA_VDD_PWRGOOD_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_andme_en_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_ANDME_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_andme_en_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_ANDME_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bist_modesel_l0_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bist_modesel_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BIST_MODESEL_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_capturedr_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_CAPTUREDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_clamp_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_CLAMP_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_exit1dr_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_EXIT1DR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_exit2dr_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_EXIT2DR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_extest_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_EXTEST_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_extestpulse_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_EXTESTPULSE_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_extesttrain_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_EXTESTTRAIN_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_highz_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_HIGHZ_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_mode_en_nt_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_MODE_EN_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_preload_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_PRELOAD_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_runtestidle_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_RUNTESTIDLE_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_shiftdr_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_SHIFTDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_txinvert_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_TXINVERT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_bs_updatedr_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_BS_UPDATEDR_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_cmn_force_pup_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_CMN_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_cmn_force_pup_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_CMN_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_disconnect_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_DISCONNECT_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_disconnect_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_DISCONNECT_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_isolate_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_ISOLATE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_isolate_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_ISOLATE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_jtagid_nt_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_JTAGID_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_jtagslvid_nt_int_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_JTAGSLVID_NT_INT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_lb_cdrclk2txen_l0_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_LB_CDRCLK2TXEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_lb_cdrclk2txen_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_LB_CDRCLK2TXEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_lb_parrx2txtimeden_l0_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_LB_PARRX2TXTIMEDEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_lb_parrx2txtimeden_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_LB_PARRX2TXTIMEDEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_lb_tx2rxbuftimeden_l0_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_LB_TX2RXBUFTIMEDEN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_lb_tx2rxbuftimeden_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_LB_TX2RXBUFTIMEDEN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_lfps_en_l0_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_LFPS_EN_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_lfps_en_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_LFPS_EN_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_mode_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_MODE_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_mode_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_MODE_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_pcie_l1d1_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_PCIE_L1D1_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_pcie_l1d1_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_PCIE_L1D1_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_pcie_l1d2_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_PCIE_L1D2_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_pcie_l1d2_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_PCIE_L1D2_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rcomp_slave_en_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RCOMP_SLAVE_EN_NT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rcomp_slave_en_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RCOMP_SLAVE_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rcomp_slave_nt_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rcomp_slave_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RCOMP_SLAVE_NT_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rcomp_slave_valid_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RCOMP_SLAVE_VALID_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rcomp_slave_valid_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RCOMP_SLAVE_VALID_A_REG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_ref_sel_rx_nt_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_ref_sel_rx_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_REF_SEL_RX_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_ref_sel_tx_nt_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_ref_sel_tx_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_REF_SEL_TX_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_ref_term_hiz_en_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_REF_TERM_HIZ_EN_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_ref_term_hiz_en_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_REF_TERM_HIZ_EN_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxbist_en_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXBIST_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxbist_en_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXBIST_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxbitslip_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXBITSLIP_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxbitslip_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXBITSLIP_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeiosdetectstat_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEIOSDETECTSTAT_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeiosdetectstat_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEIOSDETECTSTAT_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeq_clr_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEQ_CLR_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeq_clr_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEQ_CLR_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeq_precal_code_sel_l0_nt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeq_precal_code_sel_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEQ_PRECAL_CODE_SEL_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeq_start_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEQ_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeq_start_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEQ_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeq_static_en_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEQ_STATIC_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeq_static_en_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEQ_STATIC_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeyediag_start_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEYEDIAG_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxeyediag_start_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXEYEDIAG_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_direction_l0_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXMARGIN_DIRECTION_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_direction_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXMARGIN_DIRECTION_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_mode_l0_nt_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXMARGIN_MODE_L0_NT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_mode_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXMARGIN_MODE_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_offset_change_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXMARGIN_OFFSET_CHANGE_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_offset_change_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXMARGIN_OFFSET_CHANGE_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_offset_l0_nt_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_offset_l0_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXMARGIN_OFFSET_L0_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_start_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXMARGIN_START_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxmargin_start_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXMARGIN_START_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxpam_gray_en_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXPAM_GRAY_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxpam_gray_en_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXPAM_GRAY_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxpam_precode_en_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXPAM_PRECODE_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxpam_precode_en_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXPAM_PRECODE_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxrate_l0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxrate_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxterm_hiz_en_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXTERM_HIZ_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxterm_hiz_en_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXTERM_HIZ_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxwidth_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_rxwidth_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_RXWIDTH_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_spare_nt_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_spare_nt_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SPARE_NT_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcfast_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcfast_divrate_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SYNTHLCFAST_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcfast_force_pup_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SYNTHLCFAST_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcfast_force_pup_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SYNTHLCFAST_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcmed_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcmed_divrate_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SYNTHLCMED_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcmed_force_pup_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SYNTHLCMED_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcmed_force_pup_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SYNTHLCMED_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcslow_divrate_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcslow_divrate_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SYNTHLCSLOW_DIVRATE_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcslow_force_pup_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SYNTHLCSLOW_FORCE_PUP_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_synthlcslow_force_pup_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_SYNTHLCSLOW_FORCE_PUP_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txbeacon_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXBEACON_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txbeacon_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXBEACON_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txbist_en_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXBIST_EN_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txbist_en_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXBIST_EN_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txclkdivrate_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txclkdivrate_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXCLKDIVRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdetectrx_req_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXDETECTRX_REQ_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdetectrx_req_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXDETECTRX_REQ_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_levn_l0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_levn_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXDRV_LEVN_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_levnm1_l0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_levnm1_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXDRV_LEVNM1_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_levnm2_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_levnm2_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXDRV_LEVNM2_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_levnp1_l0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_levnp1_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXDRV_LEVNP1_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_slew_l0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_slew_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXDRV_SLEW_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_spare_l0_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txdrv_spare_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXDRV_SPARE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txenable_l0_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXENABLE_L0_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txenable_l0_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXENABLE_L0_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txpam_gray_en_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXPAM_GRAY_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txpam_gray_en_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXPAM_GRAY_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txpam_precode_en_a_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXPAM_PRECODE_EN_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txpam_precode_en_a_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXPAM_PRECODE_EN_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txrate_l0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txrate_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXRATE_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txwidth_l0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_pcs_txwidth_l0_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_PCS_TXWIDTH_L0_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_visa_unit_id_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_ictl_visa_unit_id_reg_en_attr == SERDES_IP_IF_L3_CFG_ICTL_VISA_UNIT_ID_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_idat_dfx_obs_dig_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_idat_visa_serial_cfg_in_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_irst_apb_mem_b_attr == SERDES_IP_IF_L3_CFG_IRST_APB_MEM_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_irst_apb_mem_b_reg_en_attr == SERDES_IP_IF_L3_CFG_IRST_APB_MEM_B_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_irst_pcs_rx_l0_b_a_attr == SERDES_IP_IF_L3_CFG_IRST_PCS_RX_L0_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_irst_pcs_rx_l0_b_a_reg_en_attr == SERDES_IP_IF_L3_CFG_IRST_PCS_RX_L0_B_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_irst_pcs_tstbus_b_a_attr == SERDES_IP_IF_L3_CFG_IRST_PCS_TSTBUS_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_irst_pcs_tx_l0_b_a_attr == SERDES_IP_IF_L3_CFG_IRST_PCS_TX_L0_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_irst_pcs_tx_l0_b_a_reg_en_attr == SERDES_IP_IF_L3_CFG_IRST_PCS_TX_L0_B_A_REG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_if_l3_cfg_irst_visa_reset_b_a_attr == SERDES_IP_IF_L3_CFG_IRST_VISA_RESET_B_A_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l0_cfg_laneclk_ctrl_attr == SERDES_IP_LANE_AON_L0_CFG_LANECLK_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l0_cfg_lanefsm_pmu_req_attr == SERDES_IP_LANE_AON_L0_CFG_LANEFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l0_cfg_lanefsm_pmu_req_en_attr == SERDES_IP_LANE_AON_L0_CFG_LANEFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l0_cfg_lanetstbus_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l0_cfg_rxmem_clr_attr == SERDES_IP_LANE_AON_L0_CFG_RXMEM_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l0_cfg_rxmem_en_attr == SERDES_IP_LANE_AON_L0_CFG_RXMEM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l0_cfg_rxmem_pstate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l0_cfg_rxmem_rate_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l0_cfg_rxmem_req_attr == SERDES_IP_LANE_AON_L0_CFG_RXMEM_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l0_cfg_rxmem_rst_b_attr == SERDES_IP_LANE_AON_L0_CFG_RXMEM_RST_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l0_cfg_rxmem_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l0_cfg_rxrstpdovr_apdrx_sqlch_ovr_b_attr == SERDES_IP_LANE_AON_L0_CFG_RXRSTPDOVR_APDRX_SQLCH_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l0_cfg_rxrstpdovr_apdrx_sqlch_ovren_attr == SERDES_IP_LANE_AON_L0_CFG_RXRSTPDOVR_APDRX_SQLCH_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l0_cfg_rxsussigdetout_ovr_attr == SERDES_IP_LANE_AON_L0_CFG_RXSUSSIGDETOUT_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l0_cfg_rxsussigdetout_ovr_en_attr == SERDES_IP_LANE_AON_L0_CFG_RXSUSSIGDETOUT_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l0_cfg_rxsussqlch_enable_attr == SERDES_IP_LANE_AON_L0_CFG_RXSUSSQLCH_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l0_cfg_txmem_clr_attr == SERDES_IP_LANE_AON_L0_CFG_TXMEM_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l0_cfg_txmem_en_attr == SERDES_IP_LANE_AON_L0_CFG_TXMEM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l0_cfg_txmem_pstate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l0_cfg_txmem_rate_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l0_cfg_txmem_req_attr == SERDES_IP_LANE_AON_L0_CFG_TXMEM_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l0_cfg_txmem_rst_b_attr == SERDES_IP_LANE_AON_L0_CFG_TXMEM_RST_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l0_cfg_txmem_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l0_cfg_txpcs_pciel1d1_ovr_attr == SERDES_IP_LANE_AON_L0_CFG_TXPCS_PCIEL1D1_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l0_cfg_txpcs_pciel1d1_ovren_attr == SERDES_IP_LANE_AON_L0_CFG_TXPCS_PCIEL1D1_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l0_cfg_txpcs_pciel1d2_ovr_attr == SERDES_IP_LANE_AON_L0_CFG_TXPCS_PCIEL1D2_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l0_cfg_txpcs_pciel1d2_ovren_attr == SERDES_IP_LANE_AON_L0_CFG_TXPCS_PCIEL1D2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l0_cfg_txrstpdovr_apdtx_bias_ovr_b_attr == SERDES_IP_LANE_AON_L0_CFG_TXRSTPDOVR_APDTX_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l0_cfg_txrstpdovr_apdtx_bias_ovren_attr == SERDES_IP_LANE_AON_L0_CFG_TXRSTPDOVR_APDTX_BIAS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l0_cfg_txrstpdovr_apdtx_drv_ovr_b_attr == SERDES_IP_LANE_AON_L0_CFG_TXRSTPDOVR_APDTX_DRV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l0_cfg_txrstpdovr_apdtx_drv_ovren_attr == SERDES_IP_LANE_AON_L0_CFG_TXRSTPDOVR_APDTX_DRV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l1_cfg_laneclk_ctrl_attr == SERDES_IP_LANE_AON_L1_CFG_LANECLK_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l1_cfg_lanefsm_pmu_req_attr == SERDES_IP_LANE_AON_L1_CFG_LANEFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l1_cfg_lanefsm_pmu_req_en_attr == SERDES_IP_LANE_AON_L1_CFG_LANEFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l1_cfg_lanetstbus_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l1_cfg_rxmem_clr_attr == SERDES_IP_LANE_AON_L1_CFG_RXMEM_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l1_cfg_rxmem_en_attr == SERDES_IP_LANE_AON_L1_CFG_RXMEM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l1_cfg_rxmem_pstate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l1_cfg_rxmem_rate_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l1_cfg_rxmem_req_attr == SERDES_IP_LANE_AON_L1_CFG_RXMEM_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l1_cfg_rxmem_rst_b_attr == SERDES_IP_LANE_AON_L1_CFG_RXMEM_RST_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l1_cfg_rxmem_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l1_cfg_rxrstpdovr_apdrx_sqlch_ovr_b_attr == SERDES_IP_LANE_AON_L1_CFG_RXRSTPDOVR_APDRX_SQLCH_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l1_cfg_rxrstpdovr_apdrx_sqlch_ovren_attr == SERDES_IP_LANE_AON_L1_CFG_RXRSTPDOVR_APDRX_SQLCH_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l1_cfg_rxsussigdetout_ovr_attr == SERDES_IP_LANE_AON_L1_CFG_RXSUSSIGDETOUT_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l1_cfg_rxsussigdetout_ovr_en_attr == SERDES_IP_LANE_AON_L1_CFG_RXSUSSIGDETOUT_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l1_cfg_rxsussqlch_enable_attr == SERDES_IP_LANE_AON_L1_CFG_RXSUSSQLCH_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l1_cfg_txmem_clr_attr == SERDES_IP_LANE_AON_L1_CFG_TXMEM_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l1_cfg_txmem_en_attr == SERDES_IP_LANE_AON_L1_CFG_TXMEM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l1_cfg_txmem_pstate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l1_cfg_txmem_rate_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l1_cfg_txmem_req_attr == SERDES_IP_LANE_AON_L1_CFG_TXMEM_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l1_cfg_txmem_rst_b_attr == SERDES_IP_LANE_AON_L1_CFG_TXMEM_RST_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l1_cfg_txmem_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l1_cfg_txpcs_pciel1d1_ovr_attr == SERDES_IP_LANE_AON_L1_CFG_TXPCS_PCIEL1D1_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l1_cfg_txpcs_pciel1d1_ovren_attr == SERDES_IP_LANE_AON_L1_CFG_TXPCS_PCIEL1D1_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l1_cfg_txpcs_pciel1d2_ovr_attr == SERDES_IP_LANE_AON_L1_CFG_TXPCS_PCIEL1D2_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l1_cfg_txpcs_pciel1d2_ovren_attr == SERDES_IP_LANE_AON_L1_CFG_TXPCS_PCIEL1D2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l1_cfg_txrstpdovr_apdtx_bias_ovr_b_attr == SERDES_IP_LANE_AON_L1_CFG_TXRSTPDOVR_APDTX_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l1_cfg_txrstpdovr_apdtx_bias_ovren_attr == SERDES_IP_LANE_AON_L1_CFG_TXRSTPDOVR_APDTX_BIAS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l1_cfg_txrstpdovr_apdtx_drv_ovr_b_attr == SERDES_IP_LANE_AON_L1_CFG_TXRSTPDOVR_APDTX_DRV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l1_cfg_txrstpdovr_apdtx_drv_ovren_attr == SERDES_IP_LANE_AON_L1_CFG_TXRSTPDOVR_APDTX_DRV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l2_cfg_laneclk_ctrl_attr == SERDES_IP_LANE_AON_L2_CFG_LANECLK_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l2_cfg_lanefsm_pmu_req_attr == SERDES_IP_LANE_AON_L2_CFG_LANEFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l2_cfg_lanefsm_pmu_req_en_attr == SERDES_IP_LANE_AON_L2_CFG_LANEFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l2_cfg_lanetstbus_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l2_cfg_rxmem_clr_attr == SERDES_IP_LANE_AON_L2_CFG_RXMEM_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l2_cfg_rxmem_en_attr == SERDES_IP_LANE_AON_L2_CFG_RXMEM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l2_cfg_rxmem_pstate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l2_cfg_rxmem_rate_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l2_cfg_rxmem_req_attr == SERDES_IP_LANE_AON_L2_CFG_RXMEM_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l2_cfg_rxmem_rst_b_attr == SERDES_IP_LANE_AON_L2_CFG_RXMEM_RST_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l2_cfg_rxmem_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l2_cfg_rxrstpdovr_apdrx_sqlch_ovr_b_attr == SERDES_IP_LANE_AON_L2_CFG_RXRSTPDOVR_APDRX_SQLCH_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l2_cfg_rxrstpdovr_apdrx_sqlch_ovren_attr == SERDES_IP_LANE_AON_L2_CFG_RXRSTPDOVR_APDRX_SQLCH_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l2_cfg_rxsussigdetout_ovr_attr == SERDES_IP_LANE_AON_L2_CFG_RXSUSSIGDETOUT_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l2_cfg_rxsussigdetout_ovr_en_attr == SERDES_IP_LANE_AON_L2_CFG_RXSUSSIGDETOUT_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l2_cfg_rxsussqlch_enable_attr == SERDES_IP_LANE_AON_L2_CFG_RXSUSSQLCH_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l2_cfg_txmem_clr_attr == SERDES_IP_LANE_AON_L2_CFG_TXMEM_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l2_cfg_txmem_en_attr == SERDES_IP_LANE_AON_L2_CFG_TXMEM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l2_cfg_txmem_pstate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l2_cfg_txmem_rate_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l2_cfg_txmem_req_attr == SERDES_IP_LANE_AON_L2_CFG_TXMEM_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l2_cfg_txmem_rst_b_attr == SERDES_IP_LANE_AON_L2_CFG_TXMEM_RST_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l2_cfg_txmem_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l2_cfg_txpcs_pciel1d1_ovr_attr == SERDES_IP_LANE_AON_L2_CFG_TXPCS_PCIEL1D1_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l2_cfg_txpcs_pciel1d1_ovren_attr == SERDES_IP_LANE_AON_L2_CFG_TXPCS_PCIEL1D1_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l2_cfg_txpcs_pciel1d2_ovr_attr == SERDES_IP_LANE_AON_L2_CFG_TXPCS_PCIEL1D2_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l2_cfg_txpcs_pciel1d2_ovren_attr == SERDES_IP_LANE_AON_L2_CFG_TXPCS_PCIEL1D2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l2_cfg_txrstpdovr_apdtx_bias_ovr_b_attr == SERDES_IP_LANE_AON_L2_CFG_TXRSTPDOVR_APDTX_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l2_cfg_txrstpdovr_apdtx_bias_ovren_attr == SERDES_IP_LANE_AON_L2_CFG_TXRSTPDOVR_APDTX_BIAS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l2_cfg_txrstpdovr_apdtx_drv_ovr_b_attr == SERDES_IP_LANE_AON_L2_CFG_TXRSTPDOVR_APDTX_DRV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l2_cfg_txrstpdovr_apdtx_drv_ovren_attr == SERDES_IP_LANE_AON_L2_CFG_TXRSTPDOVR_APDTX_DRV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l3_cfg_laneclk_ctrl_attr == SERDES_IP_LANE_AON_L3_CFG_LANECLK_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l3_cfg_lanefsm_pmu_req_attr == SERDES_IP_LANE_AON_L3_CFG_LANEFSM_PMU_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l3_cfg_lanefsm_pmu_req_en_attr == SERDES_IP_LANE_AON_L3_CFG_LANEFSM_PMU_REQ_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l3_cfg_lanetstbus_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l3_cfg_rxmem_clr_attr == SERDES_IP_LANE_AON_L3_CFG_RXMEM_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l3_cfg_rxmem_en_attr == SERDES_IP_LANE_AON_L3_CFG_RXMEM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l3_cfg_rxmem_pstate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l3_cfg_rxmem_rate_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l3_cfg_rxmem_req_attr == SERDES_IP_LANE_AON_L3_CFG_RXMEM_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l3_cfg_rxmem_rst_b_attr == SERDES_IP_LANE_AON_L3_CFG_RXMEM_RST_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l3_cfg_rxmem_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l3_cfg_rxrstpdovr_apdrx_sqlch_ovr_b_attr == SERDES_IP_LANE_AON_L3_CFG_RXRSTPDOVR_APDRX_SQLCH_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l3_cfg_rxrstpdovr_apdrx_sqlch_ovren_attr == SERDES_IP_LANE_AON_L3_CFG_RXRSTPDOVR_APDRX_SQLCH_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l3_cfg_rxsussigdetout_ovr_attr == SERDES_IP_LANE_AON_L3_CFG_RXSUSSIGDETOUT_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l3_cfg_rxsussigdetout_ovr_en_attr == SERDES_IP_LANE_AON_L3_CFG_RXSUSSIGDETOUT_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l3_cfg_rxsussqlch_enable_attr == SERDES_IP_LANE_AON_L3_CFG_RXSUSSQLCH_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l3_cfg_txmem_clr_attr == SERDES_IP_LANE_AON_L3_CFG_TXMEM_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l3_cfg_txmem_en_attr == SERDES_IP_LANE_AON_L3_CFG_TXMEM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l3_cfg_txmem_pstate_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l3_cfg_txmem_rate_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l3_cfg_txmem_req_attr == SERDES_IP_LANE_AON_L3_CFG_TXMEM_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l3_cfg_txmem_rst_b_attr == SERDES_IP_LANE_AON_L3_CFG_TXMEM_RST_B_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l3_cfg_txmem_width_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l3_cfg_txpcs_pciel1d1_ovr_attr == SERDES_IP_LANE_AON_L3_CFG_TXPCS_PCIEL1D1_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l3_cfg_txpcs_pciel1d1_ovren_attr == SERDES_IP_LANE_AON_L3_CFG_TXPCS_PCIEL1D1_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l3_cfg_txpcs_pciel1d2_ovr_attr == SERDES_IP_LANE_AON_L3_CFG_TXPCS_PCIEL1D2_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l3_cfg_txpcs_pciel1d2_ovren_attr == SERDES_IP_LANE_AON_L3_CFG_TXPCS_PCIEL1D2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l3_cfg_txrstpdovr_apdtx_bias_ovr_b_attr == SERDES_IP_LANE_AON_L3_CFG_TXRSTPDOVR_APDTX_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l3_cfg_txrstpdovr_apdtx_bias_ovren_attr == SERDES_IP_LANE_AON_L3_CFG_TXRSTPDOVR_APDTX_BIAS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l3_cfg_txrstpdovr_apdtx_drv_ovr_b_attr == SERDES_IP_LANE_AON_L3_CFG_TXRSTPDOVR_APDTX_DRV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_aon_l3_cfg_txrstpdovr_apdtx_drv_ovren_attr == SERDES_IP_LANE_AON_L3_CFG_TXRSTPDOVR_APDTX_DRV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_bshihyst_attr == SERDES_IP_LANE_L0_CFG_BSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_bstxdrv_levn_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_bstxdrv_levnm1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_bstxdrv_levnp1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_bstxdrv_levnp2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_calsqlchosc_locovren_attr == SERDES_IP_LANE_L0_CFG_CALSQLCHOSC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_calsqlchosc_trimcode_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_cdrclkstat_locovren_attr == SERDES_IP_LANE_L0_CFG_CDRCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_cdrclkstat_ready_locovr_attr == SERDES_IP_LANE_L0_CFG_CDRCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_etrregrxcdrclk_ready_attr == SERDES_IP_LANE_L0_CFG_ETRREGRXCDRCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_laneckm_avg_en_attr == SERDES_IP_LANE_L0_CFG_LANECKM_AVG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_laneckm_clk_en_attr == SERDES_IP_LANE_L0_CFG_LANECKM_CLK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_laneckm_continuous_attr == SERDES_IP_LANE_L0_CFG_LANECKM_CONTINUOUS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_laneckm_dig_meas_en_attr == SERDES_IP_LANE_L0_CFG_LANECKM_DIG_MEAS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_laneckm_dig_meas_err_clr_attr == SERDES_IP_LANE_L0_CFG_LANECKM_DIG_MEAS_ERR_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_laneckm_en_attr == SERDES_IP_LANE_L0_CFG_LANECKM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_laneckm_max_thr_attr == 25'd33554431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_laneckm_meas_ck_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_laneckm_ref_ck_div_ratio_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_laneckm_result_clr_attr == SERDES_IP_LANE_L0_CFG_LANECKM_RESULT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_laneckm_start_attr == SERDES_IP_LANE_L0_CFG_LANECKM_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_laneckm_wdt_interval_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_laneckm_win_thr_ref_attr == 25'd16777215
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_lanepcs_locovren_attr == SERDES_IP_LANE_L0_CFG_LANEPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_lanepcs_mode_locovr_attr == SERDES_IP_LANE_L0_CFG_LANEPCS_MODE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_laneperfmon_compare_val_start_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_laneperfmon_compare_val_stop_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_laneperfmon_en_attr == SERDES_IP_LANE_L0_CFG_LANEPERFMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_laneperfmon_mask_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_lanepmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_lanepmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_lanepmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_lanepmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_lanepmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_lanepmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_lb_cdrclk2txen_locovr_attr == SERDES_IP_LANE_L0_CFG_LB_CDRCLK2TXEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_lb_cdrclkdiven_attr == SERDES_IP_LANE_L0_CFG_LB_CDRCLKDIVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_lb_cdrdivclk2exten_attr == SERDES_IP_LANE_L0_CFG_LB_CDRDIVCLK2EXTEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_lb_cdrdivclk2txen_attr == SERDES_IP_LANE_L0_CFG_LB_CDRDIVCLK2TXEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_lb_hsclk2cdrdiven_attr == SERDES_IP_LANE_L0_CFG_LB_HSCLK2CDRDIVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_lb_locovren_attr == SERDES_IP_LANE_L0_CFG_LB_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_lb_parrx2txtimeden_locovr_attr == SERDES_IP_LANE_L0_CFG_LB_PARRX2TXTIMEDEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_lb_pllfbclk2cdrrefclken_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_lb_pllfbclk2cdrrefclken_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_lb_pllfbclk2cdrrefclken_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_lb_pllfbclk2cdrrefclken_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_lb_pllfbclk2cdrrefclken_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_lb_rx2txuntimeden_attr == SERDES_IP_LANE_L0_CFG_LB_RX2TXUNTIMEDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_lb_rxwordck2pcstxwordcken_attr == SERDES_IP_LANE_L0_CFG_LB_RXWORDCK2PCSTXWORDCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_lb_tx2rxbuftimeden_lsb_locovr_attr == SERDES_IP_LANE_L0_CFG_LB_TX2RXBUFTIMEDEN_LSB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_lb_tx2rxbuftimeden_msb_locovr_attr == SERDES_IP_LANE_L0_CFG_LB_TX2RXBUFTIMEDEN_MSB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_lb_tx2rxiotimeden_attr == SERDES_IP_LANE_L0_CFG_LB_TX2RXIOTIMEDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_lfps_det_locovr_attr == SERDES_IP_LANE_L0_CFG_LFPS_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_lfps_locovren_attr == SERDES_IP_LANE_L0_CFG_LFPS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_lfps_out_en_attr == SERDES_IP_LANE_L0_CFG_LFPS_OUT_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_pcslfps_en_locovr_attr == SERDES_IP_LANE_L0_CFG_PCSLFPS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_pcslfps_locovren_attr == SERDES_IP_LANE_L0_CFG_PCSLFPS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_pcsrx_dme_en_locovr_attr == SERDES_IP_LANE_L0_CFG_PCSRX_DME_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_pcsrx_locovren_attr == SERDES_IP_LANE_L0_CFG_PCSRX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_pcsrxbist_locovren_attr == SERDES_IP_LANE_L0_CFG_PCSRXBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_pcsrxbist_modesel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_pcstx_beaconen_locovr_attr == SERDES_IP_LANE_L0_CFG_PCSTX_BEACONEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_pcstx_locovren_attr == SERDES_IP_LANE_L0_CFG_PCSTX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_polarity_rx_attr == SERDES_IP_LANE_L0_CFG_POLARITY_RX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_polarity_tx_attr == SERDES_IP_LANE_L0_CFG_POLARITY_TX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rx_cmn_on_state_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rx_fastregpwrup_en_attr == SERDES_IP_LANE_L0_CFG_RX_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rx_frac_mode_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rx_on_state_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rx_pg_disable_attr == SERDES_IP_LANE_L0_CFG_RX_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rx_synth_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rx_synth_sel_amode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rx_synth_sel_bmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rx_synth_sel_cmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rx_synth_sel_dmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rx_synth_sel_emode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxadc_req_attr == SERDES_IP_LANE_L0_CFG_RXADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxagc_dccoupleen_attr == SERDES_IP_LANE_L0_CFG_RXAGC_DCCOUPLEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxaprobe_addr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxaprobe_lastmux_isolate_attr == SERDES_IP_LANE_L0_CFG_RXAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxaprobeadc_current_direction_attr == SERDES_IP_LANE_L0_CFG_RXAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxaprobeadc_resistor_enable_attr == SERDES_IP_LANE_L0_CFG_RXAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxbias_iccadj_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxbias_icvadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxbias_locovren_attr == SERDES_IP_LANE_L0_CFG_RXBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxbias_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxbist_burst_four_errtype_attr == SERDES_IP_LANE_L0_CFG_RXBIST_BURST_FOUR_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxbist_burst_one_errtype_attr == SERDES_IP_LANE_L0_CFG_RXBIST_BURST_ONE_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxbist_burst_three_errtype_attr == SERDES_IP_LANE_L0_CFG_RXBIST_BURST_THREE_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxbist_burst_two_errtype_attr == SERDES_IP_LANE_L0_CFG_RXBIST_BURST_TWO_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxbist_cdrlock2data_bypass_attr == SERDES_IP_LANE_L0_CFG_RXBIST_CDRLOCK2DATA_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxbist_cdrlock2data_postamble_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxbist_clear_errcount_attr == SERDES_IP_LANE_L0_CFG_RXBIST_CLEAR_ERRCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxbist_err_en_attr == SERDES_IP_LANE_L0_CFG_RXBIST_ERR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxbist_err_trig_type_attr == SERDES_IP_LANE_L0_CFG_RXBIST_ERR_TRIG_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxbist_errmask_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxbist_errtype_attr == SERDES_IP_LANE_L0_CFG_RXBIST_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxbist_firsterr_type_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxbist_lockchk_count_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxbist_maxbitcnt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxbist_mostrecent_err_attr == SERDES_IP_LANE_L0_CFG_RXBIST_MOSTRECENT_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxbist_relock_itercount_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxbist_seed_attr == 31'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxbist_status_hold_attr == SERDES_IP_LANE_L0_CFG_RXBIST_STATUS_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxbitslip_locovr_attr == SERDES_IP_LANE_L0_CFG_RXBITSLIP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxbitslip_locovren_attr == SERDES_IP_LANE_L0_CFG_RXBITSLIP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxbscan_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxbshicm_attr == SERDES_IP_LANE_L0_CFG_RXBSHICM_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalcdrfbdiv_div2_bypass_muxd0_attr == SERDES_IP_LANE_L0_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalcdrfbdiv_div2_bypass_muxd1_attr == SERDES_IP_LANE_L0_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalcdrfbdiv_div2_bypass_muxd2_attr == SERDES_IP_LANE_L0_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalcdrfbdiv_div2_bypass_muxd3_attr == SERDES_IP_LANE_L0_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalcdrfbdiv_div2_bypass_muxd4_attr == SERDES_IP_LANE_L0_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalduty_iclk_gray_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalduty_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTY_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalduty_qclk_gray_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalduty_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutybg_abort_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutybg_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutybg_ready_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycomp_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycomp_offset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_finish_side_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_init_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_initval_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_invert_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_round_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_runcount_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsm_signmagen_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsmout_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompfsmout_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCOMPFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutycompmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_disable_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCTRL_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_i_div1_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_i_div2_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_i_div4_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_i_div8_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_q_div1_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_q_div2_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_q_div4_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyctrl_q_div8_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_bg_en_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_bg_one_step_cal_en_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_finish_side_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_i_polarity_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_I_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_i_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_I_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_init_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_q_polarity_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_Q_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_q_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_Q_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_round_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_runcount_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutyfsm_signmagen_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_comp_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEAS_COMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_comp_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEAS_COMP_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_i_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEAS_I_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_i_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEAS_I_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_q_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEAS_Q_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_q_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEAS_Q_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeasout_comp_ack_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEASOUT_COMP_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeasout_comp_erravg_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEASOUT_COMP_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeasout_i_ack_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEASOUT_I_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeasout_i_erravg_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEASOUT_I_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeasout_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeasout_q_ack_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEASOUT_Q_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutymeasout_q_erravg_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYMEASOUT_Q_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutystat_done_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaldutystat_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALDUTYSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_centerfreq_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_end_delay_attr == 9'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_hscount_muxd0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_hscount_muxd1_attr == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_hscount_muxd2_attr == 8'd180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_hscount_muxd3_attr == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_hscount_muxd4_attr == 8'd206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_initval_centerfreq_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_initval_fosc_attr == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfosc_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_centerfreq_finish_side_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_CENTERFREQ_FINISH_SIDE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_centerfreq_to_fosc_offset_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_centerfreqen_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_CENTERFREQEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_centerfreqoffset_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_fosc_finishside_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_FOSC_FINISHSIDE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_foscen_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_FOSCEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_foscoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_init_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_invert_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_lpfax_calfosccoarse_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_lpfax_calfoscfine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_lpfax_centerfreqcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_lpfax_centerfreqfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_runcount_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_signmagen_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsm_vcorepen_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSM_VCOREPEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsmout_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscfsmout_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_count_muxd0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_count_muxd1_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_count_muxd2_attr == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_count_muxd3_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_count_muxd4_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_dlycount_attr == 9'd68
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeasout_clear_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCMEASOUT_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeasout_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscmeasout_start_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCMEASOUT_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscval_int_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalfoscval_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALFOSCVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalintsval_int_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalintsval_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALINTSVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaloffsetfsm_init_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaloffsetfsm_init_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaloffsetfsm_init_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALOFFSETFSM_INIT_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaloffsetfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcaloffsetfsmout_input_en_attr == SERDES_IP_LANE_L0_CFG_RXCALOFFSETFSMOUT_INPUT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_duty_i_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_duty_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_dutycomp_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_foscfsm_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_offsetfsm_init_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_regopampoffset_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_rxppm_lockstatus_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_sqlch_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_sqlchosc_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_synthppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_pstate_voscregopampoffset_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_duty_i_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_duty_q_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_dutycomp_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_foscfsm_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_offsetfsm_init_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_rxppm_lockstatus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_sqlch_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_sqlchosc_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_synthppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalptr_quad_voscregopampoffset_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffset_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_finish_side_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_round_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_runcount_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsm_signmagen_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchfsm_clear_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchfsm_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchfsmout_caldone_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHFSMOUT_CALDONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchfsmout_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_codeoffset_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_finish_side_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHOSCFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_init_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHOSCFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_initval_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_invert_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHOSCFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHOSCFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHOSCFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_round_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHOSCFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscfsm_runcount_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHOSCFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscmeas_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHOSCMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscmeas_ref_cnt_attr == 10'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscmeas_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALSQLCHOSCMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscmeas_settle_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalsqlchoscmeas_smpl_cnt_attr == 10'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvbiascap_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALVBIASCAP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvbiascap_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALVBIASCAP_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvcoopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvcoopampoffsetmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvcoopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvcoopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffset_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffset_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_codeoffset_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_finish_side_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_initval_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_invert_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_lpfaxcoarse_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_round_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_runcount_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETFSM_RUNCOUNT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsm_signmagen_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsmout_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetfsmout_runcount_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETFSMOUT_RUNCOUNT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetmeas_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvcorepoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALVCOREPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffset_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALVOSCREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALVOSCREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L0_CFG_RXCALVOSCREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALVOSCREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALVOSCREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALVOSCREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALVOSCREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCALVOSCREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcalvoscregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCALVOSCREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrdiv_local_en_attr == SERDES_IP_LANE_L0_CFG_RXCDRDIV_LOCAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdiv_moddiv_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdiv_moddiv_muxd1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdiv_moddiv_muxd2_attr == 4'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdiv_moddiv_muxd3_attr == 4'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdiv_moddiv_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdivslip_mdiv_muxd0_attr == 9'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdivslip_mdiv_muxd1_attr == 9'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdivslip_mdiv_muxd2_attr == 9'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdivslip_mdiv_muxd3_attr == 9'd66
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrfbdivslip_mdiv_muxd4_attr == 9'd210
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrpfd_forcedn_attr == SERDES_IP_LANE_L0_CFG_RXCDRPFD_FORCEDN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrpfd_forceen_attr == SERDES_IP_LANE_L0_CFG_RXCDRPFD_FORCEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrpfd_forceup_attr == SERDES_IP_LANE_L0_CFG_RXCDRPFD_FORCEUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrpfd_propgain_attr == SERDES_IP_LANE_L0_CFG_RXCDRPFD_PROPGAIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrpfd_pulsewidth_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrphd_asym_override_ignore_attr == SERDES_IP_LANE_L0_CFG_RXCDRPHD_ASYM_OVERRIDE_IGNORE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrphd_bitshift_en_attr == SERDES_IP_LANE_L0_CFG_RXCDRPHD_BITSHIFT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrphd_forcedn_attr == SERDES_IP_LANE_L0_CFG_RXCDRPHD_FORCEDN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrphd_forceen_attr == SERDES_IP_LANE_L0_CFG_RXCDRPHD_FORCEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrphd_forceup_attr == SERDES_IP_LANE_L0_CFG_RXCDRPHD_FORCEUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrphdrate_doublerate2s2p_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCDRPHDRATE_DOUBLERATE2S2P_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrphdrate_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCDRPHDRATE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrrefck_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrrefck_refdiv_muxd1_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrrefck_refdiv_muxd2_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrrefck_refdiv_muxd3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrrefck_refdiv_muxd4_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_biastop_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_biastopbypass_attr == SERDES_IP_LANE_L0_CFG_RXCDRVCO_BIASTOPBYPASS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_datapropgain_high_attr == 5'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_datapropgain_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_datapropgain_low_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_ff_ovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_ff_ovr_en_attr == SERDES_IP_LANE_L0_CFG_RXCDRVCO_FF_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_fil_short_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_flickerdegen_attr == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_gmfoscshort_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCDRVCO_GMFOSCSHORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_intf_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_intf_fil_short_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_intrj_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCDRVCO_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_refpropgain_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxcdrvco_refpropgain_nom_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxclk_cdrfb_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCLK_CDRFB_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxclk_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L0_CFG_RXCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxclk_locovren_attr == SERDES_IP_LANE_L0_CFG_RXCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdat_nrz_64b80b_bcword_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdata_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXDATA_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdata_locovren_attr == SERDES_IP_LANE_L0_CFG_RXDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdatapath_locovren_attr == SERDES_IP_LANE_L0_CFG_RXDATAPATH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdatapath_on_state_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdatapath_ready_locovr_attr == SERDES_IP_LANE_L0_CFG_RXDATAPATH_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdfe_datatap_vcasc_attr == 4'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdfe_dfebiasadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdfe_nbiasctle_en_attr == SERDES_IP_LANE_L0_CFG_RXDFE_NBIASCTLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdfe_vcasc_sel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdfeterm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXDFETERM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdfeterm_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdfeyadjdac_datamid_edge_coarse_en_attr == SERDES_IP_LANE_L0_CFG_RXDFEYADJDAC_DATAMID_EDGE_COARSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdfeyadjdac_datatopbot_aux_coarse_en_attr == SERDES_IP_LANE_L0_CFG_RXDFEYADJDAC_DATATOPBOT_AUX_COARSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_accum_mon_en_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_ACCUM_MON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_accum_mon_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_bypasscdrpdetupdnsmpl_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_bypassenfosc_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_BYPASSENFOSC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_bypassenints_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_BYPASSENINTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_bypassenupdnsmpl_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_BYPASSENUPDNSMPL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_bypassfosc_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_bypasspllpfdupdnsmpl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_bypassrxints_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_data2pll_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_deltasigmode_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_DELTASIGMODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_fastref_muxd0_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_FASTREF_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_fastref_muxd1_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_FASTREF_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_fastref_muxd2_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_FASTREF_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_fastref_muxd3_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_FASTREF_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_fastref_muxd4_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_FASTREF_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_fosc_mod_bypass_en_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_FOSC_MOD_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_fosc_sample_pedge_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_FOSC_SAMPLE_PEDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gain_step_on_lock_recovery_en_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_GAIN_STEP_ON_LOCK_RECOVERY_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gaindelaycount_init_attr == 9'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gaindelaycount_pow2_muxd0_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gaindelaycount_pow2_muxd1_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gaindelaycount_pow2_muxd2_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gaindelaycount_pow2_muxd3_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gaindelaycount_pow2_muxd4_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2ref_pow2_muxd0_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2ref_pow2_muxd1_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2ref_pow2_muxd2_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2ref_pow2_muxd3_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainlocked2ref_pow2_muxd4_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainunlocked_pow2_muxd0_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainunlocked_pow2_muxd1_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainunlocked_pow2_muxd2_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainunlocked_pow2_muxd3_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_gainunlocked_pow2_muxd4_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_initintegrator_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_INITINTEGRATOR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_initmodulator_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_INITMODULATOR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_deltasig_mode_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_INTS_DELTASIG_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_freeze_en_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_INTS_FREEZE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gaindelaycount_pow2_muxd0_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gaindelaycount_pow2_muxd1_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gaindelaycount_pow2_muxd2_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gaindelaycount_pow2_muxd3_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gaindelaycount_pow2_muxd4_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd0_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd1_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd2_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd3_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd4_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd0_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd1_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd2_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd3_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd4_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainunlocked_pow2_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainunlocked_pow2_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainunlocked_pow2_muxd2_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainunlocked_pow2_muxd3_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_gainunlocked_pow2_muxd4_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_guardband_hi_attr == 8'd200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_guardband_lo_attr == 8'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_loop_sel_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_INTS_LOOP_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_mod_bypass_en_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_INTS_MOD_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_mod_load_pedge_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_INTS_MOD_LOAD_PEDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_ints_step_to_integer_en_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_INTS_STEP_TO_INTEGER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_jit_length_attr == 18'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_jit_mode_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_JIT_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_modck_ctrl_en_attr == SERDES_IP_LANE_L0_CFG_RXDPIF_MODCK_CTRL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_pll2data_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_restore_cntr_attr == 9'd258
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_store_cntr_attr == 16'd258
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpif_trnsfrdelay_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpiffreeze_inten_attr == SERDES_IP_LANE_L0_CFG_RXDPIFFREEZE_INTEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdpiffreeze_moden_attr == SERDES_IP_LANE_L0_CFG_RXDPIFFREEZE_MODEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxdutyselpolarity_attr == SERDES_IP_LANE_L0_CFG_RXDUTYSELPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxflxgate_force_rxeq_gate_locovr_attr == SERDES_IP_LANE_L0_CFG_RXFLXGATE_FORCE_RXEQ_GATE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxflxgate_locovren_attr == SERDES_IP_LANE_L0_CFG_RXFLXGATE_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxfoscstat_done_locovr_attr == SERDES_IP_LANE_L0_CFG_RXFOSCSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxfoscstat_locovren_attr == SERDES_IP_LANE_L0_CFG_RXFOSCSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxfsm_cken_ovr_attr == SERDES_IP_LANE_L0_CFG_RXFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxfsm_cken_ovren_attr == SERDES_IP_LANE_L0_CFG_RXFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxints_prev_votes_hold_en_attr == SERDES_IP_LANE_L0_CFG_RXINTS_PREV_VOTES_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxlanepam_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXLANEPAM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxlanepam_locovren_attr == SERDES_IP_LANE_L0_CFG_RXLANEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxlock2datatmr_attr == 8'd240
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxlock2datatmr_short_attr == 8'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxntl_changeref_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxntl_changeref_val_locovr_attr == SERDES_IP_LANE_L0_CFG_RXNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxntl_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxntl_en_attr == SERDES_IP_LANE_L0_CFG_RXNTL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxntl_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxntl_locovren_attr == SERDES_IP_LANE_L0_CFG_RXNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxntl_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxntl_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxntl_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxntl_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxntl_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxntl_rxm_charge_up_locovr_attr == SERDES_IP_LANE_L0_CFG_RXNTL_RXM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxntl_rxm_pull_dn_locovr_attr == SERDES_IP_LANE_L0_CFG_RXNTL_RXM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxntl_rxm_sense_locovr_attr == SERDES_IP_LANE_L0_CFG_RXNTL_RXM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxntl_rxp_charge_up_locovr_attr == SERDES_IP_LANE_L0_CFG_RXNTL_RXP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxntl_rxp_pull_dn_locovr_attr == SERDES_IP_LANE_L0_CFG_RXNTL_RXP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxntl_rxp_sense_locovr_attr == SERDES_IP_LANE_L0_CFG_RXNTL_RXP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxntl_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_acc_freeze_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_ACC_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_cdrlock2data_gater_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_cdrlock2data_gater_hold_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_cdrlock2data_gater_ovrd_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_cdrlock2datatmr_optcl_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_cdrlock2datatmr_optcl_sel_ovrd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_enter_lock2data_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_ENTER_LOCK2DATA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_enter_lock2data_hold_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_ENTER_LOCK2DATA_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_exit_lock2data_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_EXIT_LOCK2DATA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_exit_lock2data_hold_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_EXIT_LOCK2DATA_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_force_lock2data_ovrd_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_FORCE_LOCK2DATA_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_force_lock2ref_ovrd_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_FORCE_LOCK2REF_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_hold_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_hold_timer_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_intf_ovrd_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_INTF_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_intf_ovrd_type_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_INTF_OVRD_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_mod_freeze_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_MOD_FREEZE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_ovrd_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_ppm_detect_freeze_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_PPM_DETECT_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_ppm_detect_freeze_ovrd_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_PPM_DETECT_FREEZE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_ppm_detect_hold_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_PPM_DETECT_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_prop_freeze_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_PROP_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_prop_freeze_ovrd_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_PROP_FREEZE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_rxdata_en_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_RXDATA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxoptclfastlock_skip_init_lock2data_attr == SERDES_IP_LANE_L0_CFG_RXOPTCLFASTLOCK_SKIP_INIT_LOCK2DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxpam_bitorder_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxpam_gray_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXPAM_GRAY_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxpam_locovren_attr == SERDES_IP_LANE_L0_CFG_RXPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxpam_precode_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXPAM_PRECODE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_p5_muxd0_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIV_P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_p5_muxd1_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIV_P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_p5_muxd2_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIV_P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_p5_muxd3_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIV_P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdiv_p5_muxd4_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIV_P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdivclken_muxd0_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIVCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdivclken_muxd1_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIVCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdivclken_muxd2_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIVCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdivclken_muxd3_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIVCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxpcs_postdivclken_muxd4_attr == SERDES_IP_LANE_L0_CFG_RXPCS_POSTDIVCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxpcsbist_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXPCSBIST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxpcsbist_locovren_attr == SERDES_IP_LANE_L0_CFG_RXPCSBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxphd_gain_hold_en_attr == SERDES_IP_LANE_L0_CFG_RXPHD_GAIN_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxphd_gain_zero_locovr_attr == SERDES_IP_LANE_L0_CFG_RXPHD_GAIN_ZERO_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxphd_locovren_attr == SERDES_IP_LANE_L0_CFG_RXPHD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxphd_majvote_basegain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxphd_majvote_en_attr == SERDES_IP_LANE_L0_CFG_RXPHD_MAJVOTE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxphd_mute_cntr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxphd_nrz8b10b_pam16b20b_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxphd_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxphd_pam_transition_sel_attr == SERDES_IP_LANE_L0_CFG_RXPHD_PAM_TRANSITION_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxphd_sign_invert_attr == SERDES_IP_LANE_L0_CFG_RXPHD_SIGN_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxpostdiv_wait_for_lock_disable_attr == SERDES_IP_LANE_L0_CFG_RXPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxppm_freq_max_offset_h_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxppm_freq_max_offset_l_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxppm_freq_ref_cnt_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxppm_lockstatus_locovr_attr == SERDES_IP_LANE_L0_CFG_RXPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxppm_lockstatus_synthlcfast_en_attr == SERDES_IP_LANE_L0_CFG_RXPPM_LOCKSTATUS_SYNTHLCFAST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxppm_lockstatus_synthlcmed_en_attr == SERDES_IP_LANE_L0_CFG_RXPPM_LOCKSTATUS_SYNTHLCMED_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxppm_lockstatus_synthlcslow_en_attr == SERDES_IP_LANE_L0_CFG_RXPPM_LOCKSTATUS_SYNTHLCSLOW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxppm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxppm_ppmdriftcount_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxppm_ppmdriftmax_attr == 16'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxppm_status_hold_attr == SERDES_IP_LANE_L0_CFG_RXPPM_STATUS_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxppm_unlock_clear_attr == SERDES_IP_LANE_L0_CFG_RXPPM_UNLOCK_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_fast_muxd0_attr == 16'd666
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_fast_muxd1_attr == 16'd4000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_fast_muxd2_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_fast_muxd3_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_fast_muxd4_attr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_muxd0_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_muxd1_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_muxd2_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_muxd3_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxppm_watchdogtmr_muxd4_attr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxppmctrl_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXPPMCTRL_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxppmctrl_locovren_attr == SERDES_IP_LANE_L0_CFG_RXPPMCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxppmlockstat_locovren_attr == SERDES_IP_LANE_L0_CFG_RXPPMLOCKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxppmlockstat_sticky_locovr_attr == SERDES_IP_LANE_L0_CFG_RXPPMLOCKSTAT_STICKY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxppmtmr_locovren_attr == SERDES_IP_LANE_L0_CFG_RXPPMTMR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxppmtmr_watchdogtmr_sel_locovr_attr == SERDES_IP_LANE_L0_CFG_RXPPMTMR_WATCHDOGTMR_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_cal_clear_delay_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_clk_chk_disable_attr == SERDES_IP_LANE_L0_CFG_RXRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_clk_delay_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_etr_on_delay_attr == 12'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_locovren_attr == SERDES_IP_LANE_L0_CFG_RXRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxreg_lev_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxreg_toggle_reset_on_rate_change_en_attr == SERDES_IP_LANE_L0_CFG_RXREG_TOGGLE_RESET_ON_RATE_CHANGE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxreg_vreg_bypass_attr == SERDES_IP_LANE_L0_CFG_RXREG_VREG_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_en_b_attr == SERDES_IP_LANE_L0_CFG_RXRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s0q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s0q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s2q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s2q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s2q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s2q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s2q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s2q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s2q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s3q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s3q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s3q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s3q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s3q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s3q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s3q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s3q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s4q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s4q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evdn_delay_lut_sel_s5q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_entry2_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_entry4_attr == 13'd78
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_entry5_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_entry6_attr == 13'd1406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s0q2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s0q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s1q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s1q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s1q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s1q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s1q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s1q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s2q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s2q2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s2q3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s2q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s2q5_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s2q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s2q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s3q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s3q1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s3q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s3q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s3q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s3q5_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s3q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s3q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s4q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s4q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpu_evup_delay_lut_sel_s5q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_duty_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_fosc_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cal_sqlch_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_cdrfb_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrfbdivcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_cdrmoddivcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpuetr_termhiz_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_auxcomp_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_datfbdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_dfe_yadj_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_hifreqagc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_sqlch_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpupd_vco_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_cdrfbdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_dpif_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pdet_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_pfd_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_ppm_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pa_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrpurst_s2pb_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_aetrrx_cdrfbdivcken_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_AETRRX_CDRFBDIVCKEN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_aetrrx_cdrfbdivcken_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_AETRRX_CDRFBDIVCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_aetrrx_cdrmoddivcken_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_AETRRX_CDRMODDIVCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_aetrrx_cdrmoddivcken_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_AETRRX_CDRMODDIVCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_aetrrx_termhiz_en_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_AETRRX_TERMHIZ_EN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_aetrrx_termhiz_en_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_AETRRX_TERMHIZ_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_aetrsynth_pcspostdivclksel_ovr_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_AETRSYNTH_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_aetrsynth_pcspostdivclksel_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_AETRSYNTH_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_adc_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_adc_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_auxcomp_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_AUXCOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_auxcomp_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_AUXCOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_bias_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_bias_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_BIAS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_ctlecomp_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_CTLECOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_ctlecomp_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_CTLECOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_datfbdiv_b_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DATFBDIV_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_datfbdiv_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DATFBDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_dfe_bias_b_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DFE_BIAS_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_dfe_bias_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DFE_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_dfe_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DFE_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_dfe_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DFE_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_dfe_yadj_b_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DFE_YADJ_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_dfe_yadj_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DFE_YADJ_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_duty_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DUTY_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_duty_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_DUTY_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_hifreqagc_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_HIFREQAGC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_hifreqagc_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_HIFREQAGC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_ntl_b_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_ntl_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_reg_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_reg_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_vco_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_VCO_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_vco_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_VCO_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_voscreg_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_VOSCREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_apdrx_voscreg_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_APDRX_VOSCREG_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_adc_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_adc_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_cdrfbdiv_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_CDRFBDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_cdrfbdiv_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_CDRFBDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_pdet_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_PDET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_pdet_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_PDET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_pfd_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_PFD_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_pfd_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_PFD_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_refdiv_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_refdiv_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_reg_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_reg_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_s2pa_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_S2PA_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_s2pa_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_S2PA_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_s2pb_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_S2PB_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_s2pb_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_S2PB_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_vco_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_VCO_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_vco_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_VCO_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_voscreg_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_VOSCREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstrx_voscreg_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTRX_VOSCREG_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstsynth_postdiv_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTSYNTH_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_arstsynth_postdiv_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_ARSTSYNTH_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_drstrx_dpif_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_DRSTRX_DPIF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_drstrx_dpif_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_DRSTRX_DPIF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_drstrx_ppm_ovr_b_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_DRSTRX_PPM_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxrstpdovr_drstrx_ppm_ovren_attr == SERDES_IP_LANE_L0_CFG_RXRSTPDOVR_DRSTRX_PPM_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_cdrlock2data_locovr_attr == SERDES_IP_LANE_L0_CFG_RXSIGDET_CDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_diglfpsdeten_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_diglfpsdeten_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_diglfpsdeten_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_diglfpsdeten_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_diglfpsdeten_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrancnten_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrancnten_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrancnten_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrancnten_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrancnten_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrancnten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrandeten_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrandeten_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrandeten_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrandeten_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrandeten_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_digtrandeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_eiosdeten_muxd0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_eiosdeten_muxd1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_eiosdeten_muxd2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_eiosdeten_muxd3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_eiosdeten_muxd4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_eiosdeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_enable_attr == SERDES_IP_LANE_L0_CFG_RXSIGDET_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_fastlock_winsize_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_leveldeten_muxd0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_leveldeten_muxd1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_leveldeten_muxd2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_leveldeten_muxd3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_leveldeten_muxd4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_leveldeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_lfpsexit_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_locovren_attr == SERDES_IP_LANE_L0_CFG_RXSIGDET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_ppmdeten_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_ppmdeten_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_ppmdeten_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_ppmdeten_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_ppmdeten_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_ppmdeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_rxeq_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_rxeqen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_rxeqen_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_rxleveldet_debounce_dncount_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_rxleveldet_debounce_flush_en_attr == SERDES_IP_LANE_L0_CFG_RXSIGDET_RXLEVELDET_DEBOUNCE_FLUSH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_rxleveldet_debounce_upcount_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_sigdet_debounce_attr == SERDES_IP_LANE_L0_CFG_RXSIGDET_SIGDET_DEBOUNCE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_tmr_clksel_attr == SERDES_IP_LANE_L0_CFG_RXSIGDET_TMR_CLKSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_toggle_count_en_attr == SERDES_IP_LANE_L0_CFG_RXSIGDET_TOGGLE_COUNT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_toggle_count_pause_attr == SERDES_IP_LANE_L0_CFG_RXSIGDET_TOGGLE_COUNT_PAUSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdet_toggle_monitor_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdetin_eiosdetectstat_locovr_attr == SERDES_IP_LANE_L0_CFG_RXSIGDETIN_EIOSDETECTSTAT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdetin_locovren_attr == SERDES_IP_LANE_L0_CFG_RXSIGDETIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdetin_ovrcdrlock2data_locovr_attr == SERDES_IP_LANE_L0_CFG_RXSIGDETIN_OVRCDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdetin_ovrencdrlock2data_locovr_attr == SERDES_IP_LANE_L0_CFG_RXSIGDETIN_OVRENCDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdetout_lock2data_noforce_ltr_locovr_attr == SERDES_IP_LANE_L0_CFG_RXSIGDETOUT_LOCK2DATA_NOFORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsigdetout_locovren_attr == SERDES_IP_LANE_L0_CFG_RXSIGDETOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxspare0_attr == 32'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxspare_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsqlchlfps_consec_one_thresh_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsqlchlfps_consec_zero_thresh_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsqlchlfps_cycle_thresh_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsqlchlfps_dat_bitorder_attr == SERDES_IP_LANE_L0_CFG_RXSQLCHLFPS_DAT_BITORDER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsqlchlfps_debounce_type_attr == SERDES_IP_LANE_L0_CFG_RXSQLCHLFPS_DEBOUNCE_TYPE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsqlchlfps_one_run_length_thresh_attr == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsqlchlfps_one_run_length_timeout_attr == 8'd103
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsqlchlfps_zero_run_length_thresh_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsqlchlfps_zero_run_length_timeout_attr == 8'd103
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsynthdiv_slowmed_en_muxd0_attr == SERDES_IP_LANE_L0_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsynthdiv_slowmed_en_muxd1_attr == SERDES_IP_LANE_L0_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsynthdiv_slowmed_en_muxd2_attr == SERDES_IP_LANE_L0_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsynthdiv_slowmed_en_muxd3_attr == SERDES_IP_LANE_L0_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxsynthdiv_slowmed_en_muxd4_attr == SERDES_IP_LANE_L0_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxterm_cal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxterm_coarse_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxterm_locovren_attr == SERDES_IP_LANE_L0_CFG_RXTERM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxterm_modeselect_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxtermhiz_en_locovr_attr == SERDES_IP_LANE_L0_CFG_RXTERMHIZ_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxtermhiz_locovren_attr == SERDES_IP_LANE_L0_CFG_RXTERMHIZ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxvoscreg_bypass_vosc_attr == SERDES_IP_LANE_L0_CFG_RXVOSCREG_BYPASS_VOSC_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxvoscregopampoffsetctrl_sel_attr == SERDES_IP_LANE_L0_CFG_RXVOSCREGOPAMPOFFSETCTRL_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxvoscregopampoffseterr_locovren_attr == SERDES_IP_LANE_L0_CFG_RXVOSCREGOPAMPOFFSETERR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxvoscregopampoffseterr_sel_locovr_attr == SERDES_IP_LANE_L0_CFG_RXVOSCREGOPAMPOFFSETERR_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxvoscregvref_locovren_attr == SERDES_IP_LANE_L0_CFG_RXVOSCREGVREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_rxvoscregvref_sel_locovr_attr == SERDES_IP_LANE_L0_CFG_RXVOSCREGVREF_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlch_acqgain_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlch_acqtime_attr == 13'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlch_cal_quiet_locovr_attr == SERDES_IP_LANE_L0_CFG_SQLCH_CAL_QUIET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlch_cal_sel_locovr_attr == SERDES_IP_LANE_L0_CFG_SQLCH_CAL_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlch_calctrl_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlch_calen_locovr_attr == SERDES_IP_LANE_L0_CFG_SQLCH_CALEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlch_caltimer_attr == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlch_clkgate_locovr_attr == SERDES_IP_LANE_L0_CFG_SQLCH_CLKGATE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlch_cmshiften_attr == SERDES_IP_LANE_L0_CFG_SQLCH_CMSHIFTEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_acq_gain_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_acq_pct_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_cal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_clr_errlog_attr == SERDES_IP_LANE_L0_CFG_SQLCH_CONT_CLR_ERRLOG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_controller_mode_attr == SERDES_IP_LANE_L0_CFG_SQLCH_CONT_CONTROLLER_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_dis_attr == SERDES_IP_LANE_L0_CFG_SQLCH_CONT_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_pause_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_postcal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_precal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlch_cont_quiet_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlch_lfps_en_attr == SERDES_IP_LANE_L0_CFG_SQLCH_LFPS_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlch_locovren_attr == SERDES_IP_LANE_L0_CFG_SQLCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlch_ovrd_val_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlch_pkdet_freqsel_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlch_polarity_attr == SERDES_IP_LANE_L0_CFG_SQLCH_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlch_rdacen_attr == SERDES_IP_LANE_L0_CFG_SQLCH_RDACEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlch_thresh_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlch_time_out_attr == 16'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlch_vrefsel0_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlch_vrefsel1_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlch_vrefsel_ovr_en_attr == SERDES_IP_LANE_L0_CFG_SQLCH_VREFSEL_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlchdeb_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlchdeb_deb_cnt_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlchdeb_deb_status_cnt_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlchdeb_en_attr == SERDES_IP_LANE_L0_CFG_SQLCHDEB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlchdeb_ign_cnt_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlchdeb_sigdet_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlchdeb_thresh_cnt_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlchdebout_exit_good_debounced_locovr_attr == SERDES_IP_LANE_L0_CFG_SQLCHDEBOUT_EXIT_GOOD_DEBOUNCED_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlchdebout_exit_good_debounced_status_locovr_attr == SERDES_IP_LANE_L0_CFG_SQLCHDEBOUT_EXIT_GOOD_DEBOUNCED_STATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlchdebout_exit_good_locovr_attr == SERDES_IP_LANE_L0_CFG_SQLCHDEBOUT_EXIT_GOOD_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_sqlchdebout_locovren_attr == SERDES_IP_LANE_L0_CFG_SQLCHDEBOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_trancnt_off_attr == 10'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_trancnt_on_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_trancntout_det_locovr_attr == SERDES_IP_LANE_L0_CFG_TRANCNTOUT_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_trancntout_locovren_attr == SERDES_IP_LANE_L0_CFG_TRANCNTOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_trandet_ax_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_trandet_ay_attr == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_trandet_off_h_attr == 6'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_trandet_off_l_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_trandet_on_h_attr == 6'd39
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_trandet_on_l_attr == 6'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_trandetout_det_locovr_attr == SERDES_IP_LANE_L0_CFG_TRANDETOUT_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_trandetout_locovren_attr == SERDES_IP_LANE_L0_CFG_TRANDETOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_tx2rxlb_en_attr == SERDES_IP_LANE_L0_CFG_TX2RXLB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_tx2rxlb_init_offset_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_tx_cmn_on_state_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_tx_fastregpwrup_en_attr == SERDES_IP_LANE_L0_CFG_TX_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_tx_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_tx_pg_disable_attr == SERDES_IP_LANE_L0_CFG_TX_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_tx_synth_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_tx_synth_sel_amode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_tx_synth_sel_bmode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_tx_synth_sel_cmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_tx_synth_sel_dmode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_tx_synth_sel_emode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_tx_txdetrx_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txadc_req_attr == SERDES_IP_LANE_L0_CFG_TXADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txaprobe_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txaprobe_lastmux_isolate_attr == SERDES_IP_LANE_L0_CFG_TXAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txaprobeadc_current_direction_attr == SERDES_IP_LANE_L0_CFG_TXAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txaprobeadc_resistor_enable_attr == SERDES_IP_LANE_L0_CFG_TXAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txbdvdr_pma2pcstxworden_attr == SERDES_IP_LANE_L0_CFG_TXBDVDR_PMA2PCSTXWORDEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txbeacon_div_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txbeacon_sel_attr == SERDES_IP_LANE_L0_CFG_TXBEACON_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txbias_icc20uadj_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txbias_icc80uadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txbias_locovren_attr == SERDES_IP_LANE_L0_CFG_TXBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txbias_termcal_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txbist_biterror_en_attr == SERDES_IP_LANE_L0_CFG_TXBIST_BITERROR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txbist_locovren_attr == SERDES_IP_LANE_L0_CFG_TXBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txbist_modesel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txbist_oobmode_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txbist_oobtburst_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txbist_oobtcomrstinit_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txbist_oobtcomsas_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txbist_oobtcomwake_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txbist_seed_attr == 31'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_size_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf00_attr == 32'd1985229328
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf01_attr == 32'd4275878552
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf02_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf03_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf04_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf05_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf06_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf07_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf08_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txbist_udp_vf09_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txbit_select_muxd0_attr == SERDES_IP_LANE_L0_CFG_TXBIT_SELECT_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txbit_select_muxd1_attr == SERDES_IP_LANE_L0_CFG_TXBIT_SELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txbit_select_muxd2_attr == SERDES_IP_LANE_L0_CFG_TXBIT_SELECT_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txbit_select_muxd3_attr == SERDES_IP_LANE_L0_CFG_TXBIT_SELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txbit_select_muxd4_attr == SERDES_IP_LANE_L0_CFG_TXBIT_SELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txbti_data_replication_attr == SERDES_IP_LANE_L0_CFG_TXBTI_DATA_REPLICATION_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txbti_tx_idle_data_en_attr == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcal_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcal_tclkduty_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalduty_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalduty_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTY_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalduty_sel_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutybg_abort_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutybg_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutybg_ready_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutycomp_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutycomp_offset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_finish_side_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_init_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_initval_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_invert_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_req_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_round_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_runcount_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsm_signmagen_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsmout_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompfsmout_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompmeas_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompmeas_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompmeas_req_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompmeasout_ack_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPMEASOUT_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompmeasout_erravg_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPMEASOUT_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutycompmeasout_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYCOMPMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_bg_en_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_bg_one_step_cal_en_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_finish_side_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_init_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_invert_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_req_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_round_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_runcount_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutyfsm_signmagen_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeas_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeas_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeas_req_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeasout_ack_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYMEASOUT_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeasout_erravg_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYMEASOUT_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutymeasout_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutystat_done_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaldutystat_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALDUTYSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalptr_pstate_duty_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalptr_pstate_dutycomp_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalptr_pstate_regopampoffset_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_duty_muxd0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_duty_muxd1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_duty_muxd2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_duty_muxd3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_duty_muxd4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_dutycomp_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_dutycomp_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_dutycomp_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_dutycomp_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_dutycomp_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_regopampoffset_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalptr_quad_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffset_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_finish_side_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_round_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_runcount_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsm_signmagen_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcaltclkdutyforce_div1_attr == SERDES_IP_LANE_L0_CFG_TXCALTCLKDUTYFORCE_DIV1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txcdrdiv_local_en_attr == SERDES_IP_LANE_L0_CFG_TXCDRDIV_LOCAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txclk_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L0_CFG_TXCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txclk_locovren_attr == SERDES_IP_LANE_L0_CFG_TXCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txclkgenmuxsel_txinternal_attr == SERDES_IP_LANE_L0_CFG_TXCLKGENMUXSEL_TXINTERNAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txdetectrx_thr_attr == 5'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeas_count_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeas_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXDETECTRXMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeas_locovren_attr == SERDES_IP_LANE_L0_CFG_TXDETECTRXMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeas_validdlycount_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeasin_locovren_attr == SERDES_IP_LANE_L0_CFG_TXDETECTRXMEASIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeasin_start_locovr_attr == SERDES_IP_LANE_L0_CFG_TXDETECTRXMEASIN_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeaspcs_locovren_attr == SERDES_IP_LANE_L0_CFG_TXDETECTRXMEASPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeaspcs_req_locovr_attr == SERDES_IP_LANE_L0_CFG_TXDETECTRXMEASPCS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeasval_locovren_attr == SERDES_IP_LANE_L0_CFG_TXDETECTRXMEASVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txdetectrxmeasval_stat_locovr_attr == SERDES_IP_LANE_L0_CFG_TXDETECTRXMEASVAL_STAT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txdetrx_levn_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txdetrx_levnm1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txdetrx_levnp1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txdetrx_levnp2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txdrv_hizen_locovr_attr == SERDES_IP_LANE_L0_CFG_TXDRV_HIZEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txdrv_levn_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txdrv_levnm1_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txdrv_levnp1_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txdrv_levnp2_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txdrv_locovren_attr == SERDES_IP_LANE_L0_CFG_TXDRV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txdrv_refcken_attr == SERDES_IP_LANE_L0_CFG_TXDRV_REFCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txdrv_termref_attr == SERDES_IP_LANE_L0_CFG_TXDRV_TERMREF_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txdrvmute_locovr_attr == SERDES_IP_LANE_L0_CFG_TXDRVMUTE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txdrvmute_locovren_attr == SERDES_IP_LANE_L0_CFG_TXDRVMUTE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txduty_ctrl_disable_attr == SERDES_IP_LANE_L0_CFG_TXDUTY_CTRL_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txduty_pad_sense_en_attr == SERDES_IP_LANE_L0_CFG_TXDUTY_PAD_SENSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txdutycal_div16_en_attr == SERDES_IP_LANE_L0_CFG_TXDUTYCAL_DIV16_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txdutycal_div1_en_attr == SERDES_IP_LANE_L0_CFG_TXDUTYCAL_DIV1_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txdutycal_div2_en_attr == SERDES_IP_LANE_L0_CFG_TXDUTYCAL_DIV2_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txdutycal_div4_en_attr == SERDES_IP_LANE_L0_CFG_TXDUTYCAL_DIV4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txdutycal_div8_en_attr == SERDES_IP_LANE_L0_CFG_TXDUTYCAL_DIV8_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txfifo_elecidle_deskew_en_attr == SERDES_IP_LANE_L0_CFG_TXFIFO_ELECIDLE_DESKEW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txfifo_force_txidlebit1_zero_disable_attr == SERDES_IP_LANE_L0_CFG_TXFIFO_FORCE_TXIDLEBIT1_ZERO_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txfifo_kill_dly_10b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txfifo_kill_dly_16b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txfifo_kill_dly_20b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txfifo_kill_dly_32b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txfifo_kill_dly_40b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txfifo_kill_dly_64b_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txfifo_kill_dly_80b_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txfifo_kill_dly_8b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txfifo_kill_en_attr == SERDES_IP_LANE_L0_CFG_TXFIFO_KILL_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txfsm_cken_ovr_attr == SERDES_IP_LANE_L0_CFG_TXFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txfsm_cken_ovren_attr == SERDES_IP_LANE_L0_CFG_TXFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txfsm_main_on_state_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txl1d1_doze_ctrl_attr == SERDES_IP_LANE_L0_CFG_TXL1D1_DOZE_CTRL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txl1d1_txbias_ctrl_attr == SERDES_IP_LANE_L0_CFG_TXL1D1_TXBIAS_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txlanepam_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXLANEPAM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txlanepam_locovren_attr == SERDES_IP_LANE_L0_CFG_TXLANEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txmeaslatovrhd_meas_sel_attr == SERDES_IP_LANE_L0_CFG_TXMEASLATOVRHD_MEAS_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txmute_delay_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txntl_changeref_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txntl_changeref_val_locovr_attr == SERDES_IP_LANE_L0_CFG_TXNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txntl_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txntl_en_attr == SERDES_IP_LANE_L0_CFG_TXNTL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txntl_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txntl_locovren_attr == SERDES_IP_LANE_L0_CFG_TXNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txntl_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txntl_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txntl_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txntl_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txntl_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txntl_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txntl_txm_charge_up_locovr_attr == SERDES_IP_LANE_L0_CFG_TXNTL_TXM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txntl_txm_pull_dn_locovr_attr == SERDES_IP_LANE_L0_CFG_TXNTL_TXM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txntl_txm_sense_locovr_attr == SERDES_IP_LANE_L0_CFG_TXNTL_TXM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txntl_txp_charge_up_locovr_attr == SERDES_IP_LANE_L0_CFG_TXNTL_TXP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txntl_txp_pull_dn_locovr_attr == SERDES_IP_LANE_L0_CFG_TXNTL_TXP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txntl_txp_sense_locovr_attr == SERDES_IP_LANE_L0_CFG_TXNTL_TXP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txp2s_txwordsyncbypen_attr == SERDES_IP_LANE_L0_CFG_TXP2S_TXWORDSYNCBYPEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txpam_bitorder_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txpam_gray_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXPAM_GRAY_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txpam_locovren_attr == SERDES_IP_LANE_L0_CFG_TXPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txpam_precode_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXPAM_PRECODE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txpcs_locovren_attr == SERDES_IP_LANE_L0_CFG_TXPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txpcs_txenable_locovr_attr == SERDES_IP_LANE_L0_CFG_TXPCS_TXENABLE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txpcsbist_en_locovr_attr == SERDES_IP_LANE_L0_CFG_TXPCSBIST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txpcsbist_locovren_attr == SERDES_IP_LANE_L0_CFG_TXPCSBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txratewidth_clk_chk_disable_attr == SERDES_IP_LANE_L0_CFG_TXRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txratewidth_etr_on_delay_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txratewidth_locovren_attr == SERDES_IP_LANE_L0_CFG_TXRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txreg_toggle_pwrupacc_on_rate_change_en_attr == SERDES_IP_LANE_L0_CFG_TXREG_TOGGLE_PWRUPACC_ON_RATE_CHANGE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txreg_toggle_reset_on_rate_change_en_attr == SERDES_IP_LANE_L0_CFG_TXREG_TOGGLE_RESET_ON_RATE_CHANGE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txresetdel_sel_attr == SERDES_IP_LANE_L0_CFG_TXRESETDEL_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_en_b_attr == SERDES_IP_LANE_L0_CFG_TXRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s0q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s0q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s1q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s1q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s2q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s2q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s2q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s2q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s2q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s2q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s2q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s3q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s3q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s3q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s3q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s3q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s3q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s3q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s3q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s4q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s4q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evdn_delay_lut_sel_s5q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_entry2_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s0q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s0q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s1q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s1q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s1q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s1q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s1q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s1q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s2q0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s2q1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s2q2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s2q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s2q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s2q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s2q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s2q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s3q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s3q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s3q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s3q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s3q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s3q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s3q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s3q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s4q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s4q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpu_evup_delay_lut_sel_s5q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_duty_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_bitckdvdrcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_dn_ptr0_s_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_up_ptr0_s_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_drvdoze_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_p2s_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpurst_pma2pcstxword_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpurst_regreset_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrpurst_txdetectrx_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_aetrtx_bitckdvdrcken_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_AETRTX_BITCKDVDRCKEN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_aetrtx_bitckdvdrcken_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_AETRTX_BITCKDVDRCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_aetrtx_regpwrupacc_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_AETRTX_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_aetrtx_regpwrupacc_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_AETRTX_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_adc_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_adc_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_drvdoze_b_ovr_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_DRVDOZE_B_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_drvdoze_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_DRVDOZE_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_duty_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_DUTY_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_duty_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_DUTY_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_ntl_b_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_ntl_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_p2s_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_P2S_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_p2s_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_P2S_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_reg_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_apdtx_reg_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_APDTX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_arsttx_adc_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_ARSTTX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_arsttx_adc_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_ARSTTX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_arsttx_pma2pcstxword_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_ARSTTX_PMA2PCSTXWORD_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_arsttx_pma2pcstxword_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_ARSTTX_PMA2PCSTXWORD_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_arsttx_regreset_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_ARSTTX_REGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_arsttx_regreset_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_ARSTTX_REGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_arsttx_txdetectrx_ovr_b_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_ARSTTX_TXDETECTRX_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrstpdovr_arsttx_txdetectrx_ovren_attr == SERDES_IP_LANE_L0_CFG_TXRSTPDOVR_ARSTTX_TXDETECTRX_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txrststate_hiz_en_attr == SERDES_IP_LANE_L0_CFG_TXRSTSTATE_HIZ_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txspare0_attr == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txspare_attr == 10'd384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txterm_coarse_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txtermtrim_locovren_attr == SERDES_IP_LANE_L0_CFG_TXTERMTRIM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txtermtrim_nmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txtermtrim_pmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txwclk_div_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txwclk_div_en_attr == SERDES_IP_LANE_L0_CFG_TXWCLK_DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txwclk_div_smpl_attr == SERDES_IP_LANE_L0_CFG_TXWCLK_DIV_SMPL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txwptr_init01_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txwptr_init02_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txwptr_init04_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txwptr_init08_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txwptr_init16_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txwptr_init32_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l0_cfg_txwptr_init_rx2txparlb_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_bshihyst_attr == SERDES_IP_LANE_L1_CFG_BSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_bstxdrv_levn_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_bstxdrv_levnm1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_bstxdrv_levnp1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_bstxdrv_levnp2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_calsqlchosc_locovren_attr == SERDES_IP_LANE_L1_CFG_CALSQLCHOSC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_calsqlchosc_trimcode_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_cdrclkstat_locovren_attr == SERDES_IP_LANE_L1_CFG_CDRCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_cdrclkstat_ready_locovr_attr == SERDES_IP_LANE_L1_CFG_CDRCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_etrregrxcdrclk_ready_attr == SERDES_IP_LANE_L1_CFG_ETRREGRXCDRCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_laneckm_avg_en_attr == SERDES_IP_LANE_L1_CFG_LANECKM_AVG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_laneckm_clk_en_attr == SERDES_IP_LANE_L1_CFG_LANECKM_CLK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_laneckm_continuous_attr == SERDES_IP_LANE_L1_CFG_LANECKM_CONTINUOUS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_laneckm_dig_meas_en_attr == SERDES_IP_LANE_L1_CFG_LANECKM_DIG_MEAS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_laneckm_dig_meas_err_clr_attr == SERDES_IP_LANE_L1_CFG_LANECKM_DIG_MEAS_ERR_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_laneckm_en_attr == SERDES_IP_LANE_L1_CFG_LANECKM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_laneckm_max_thr_attr == 25'd33554431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_laneckm_meas_ck_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_laneckm_ref_ck_div_ratio_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_laneckm_result_clr_attr == SERDES_IP_LANE_L1_CFG_LANECKM_RESULT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_laneckm_start_attr == SERDES_IP_LANE_L1_CFG_LANECKM_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_laneckm_wdt_interval_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_laneckm_win_thr_ref_attr == 25'd16777215
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_lanepcs_locovren_attr == SERDES_IP_LANE_L1_CFG_LANEPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_lanepcs_mode_locovr_attr == SERDES_IP_LANE_L1_CFG_LANEPCS_MODE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_laneperfmon_compare_val_start_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_laneperfmon_compare_val_stop_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_laneperfmon_en_attr == SERDES_IP_LANE_L1_CFG_LANEPERFMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_laneperfmon_mask_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_lanepmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_lanepmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_lanepmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_lanepmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_lanepmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_lanepmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_lb_cdrclk2txen_locovr_attr == SERDES_IP_LANE_L1_CFG_LB_CDRCLK2TXEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_lb_cdrclkdiven_attr == SERDES_IP_LANE_L1_CFG_LB_CDRCLKDIVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_lb_cdrdivclk2exten_attr == SERDES_IP_LANE_L1_CFG_LB_CDRDIVCLK2EXTEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_lb_cdrdivclk2txen_attr == SERDES_IP_LANE_L1_CFG_LB_CDRDIVCLK2TXEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_lb_hsclk2cdrdiven_attr == SERDES_IP_LANE_L1_CFG_LB_HSCLK2CDRDIVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_lb_locovren_attr == SERDES_IP_LANE_L1_CFG_LB_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_lb_parrx2txtimeden_locovr_attr == SERDES_IP_LANE_L1_CFG_LB_PARRX2TXTIMEDEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_lb_pllfbclk2cdrrefclken_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_lb_pllfbclk2cdrrefclken_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_lb_pllfbclk2cdrrefclken_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_lb_pllfbclk2cdrrefclken_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_lb_pllfbclk2cdrrefclken_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_lb_rx2txuntimeden_attr == SERDES_IP_LANE_L1_CFG_LB_RX2TXUNTIMEDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_lb_rxwordck2pcstxwordcken_attr == SERDES_IP_LANE_L1_CFG_LB_RXWORDCK2PCSTXWORDCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_lb_tx2rxbuftimeden_lsb_locovr_attr == SERDES_IP_LANE_L1_CFG_LB_TX2RXBUFTIMEDEN_LSB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_lb_tx2rxbuftimeden_msb_locovr_attr == SERDES_IP_LANE_L1_CFG_LB_TX2RXBUFTIMEDEN_MSB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_lb_tx2rxiotimeden_attr == SERDES_IP_LANE_L1_CFG_LB_TX2RXIOTIMEDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_lfps_det_locovr_attr == SERDES_IP_LANE_L1_CFG_LFPS_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_lfps_locovren_attr == SERDES_IP_LANE_L1_CFG_LFPS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_lfps_out_en_attr == SERDES_IP_LANE_L1_CFG_LFPS_OUT_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_pcslfps_en_locovr_attr == SERDES_IP_LANE_L1_CFG_PCSLFPS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_pcslfps_locovren_attr == SERDES_IP_LANE_L1_CFG_PCSLFPS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_pcsrx_dme_en_locovr_attr == SERDES_IP_LANE_L1_CFG_PCSRX_DME_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_pcsrx_locovren_attr == SERDES_IP_LANE_L1_CFG_PCSRX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_pcsrxbist_locovren_attr == SERDES_IP_LANE_L1_CFG_PCSRXBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_pcsrxbist_modesel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_pcstx_beaconen_locovr_attr == SERDES_IP_LANE_L1_CFG_PCSTX_BEACONEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_pcstx_locovren_attr == SERDES_IP_LANE_L1_CFG_PCSTX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_polarity_rx_attr == SERDES_IP_LANE_L1_CFG_POLARITY_RX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_polarity_tx_attr == SERDES_IP_LANE_L1_CFG_POLARITY_TX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rx_cmn_on_state_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rx_fastregpwrup_en_attr == SERDES_IP_LANE_L1_CFG_RX_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rx_frac_mode_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rx_on_state_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rx_pg_disable_attr == SERDES_IP_LANE_L1_CFG_RX_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rx_synth_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rx_synth_sel_amode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rx_synth_sel_bmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rx_synth_sel_cmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rx_synth_sel_dmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rx_synth_sel_emode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxadc_req_attr == SERDES_IP_LANE_L1_CFG_RXADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxagc_dccoupleen_attr == SERDES_IP_LANE_L1_CFG_RXAGC_DCCOUPLEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxaprobe_addr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxaprobe_lastmux_isolate_attr == SERDES_IP_LANE_L1_CFG_RXAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxaprobeadc_current_direction_attr == SERDES_IP_LANE_L1_CFG_RXAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxaprobeadc_resistor_enable_attr == SERDES_IP_LANE_L1_CFG_RXAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxbias_iccadj_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxbias_icvadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxbias_locovren_attr == SERDES_IP_LANE_L1_CFG_RXBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxbias_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxbist_burst_four_errtype_attr == SERDES_IP_LANE_L1_CFG_RXBIST_BURST_FOUR_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxbist_burst_one_errtype_attr == SERDES_IP_LANE_L1_CFG_RXBIST_BURST_ONE_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxbist_burst_three_errtype_attr == SERDES_IP_LANE_L1_CFG_RXBIST_BURST_THREE_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxbist_burst_two_errtype_attr == SERDES_IP_LANE_L1_CFG_RXBIST_BURST_TWO_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxbist_cdrlock2data_bypass_attr == SERDES_IP_LANE_L1_CFG_RXBIST_CDRLOCK2DATA_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxbist_cdrlock2data_postamble_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxbist_clear_errcount_attr == SERDES_IP_LANE_L1_CFG_RXBIST_CLEAR_ERRCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxbist_err_en_attr == SERDES_IP_LANE_L1_CFG_RXBIST_ERR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxbist_err_trig_type_attr == SERDES_IP_LANE_L1_CFG_RXBIST_ERR_TRIG_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxbist_errmask_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxbist_errtype_attr == SERDES_IP_LANE_L1_CFG_RXBIST_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxbist_firsterr_type_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxbist_lockchk_count_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxbist_maxbitcnt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxbist_mostrecent_err_attr == SERDES_IP_LANE_L1_CFG_RXBIST_MOSTRECENT_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxbist_relock_itercount_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxbist_seed_attr == 31'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxbist_status_hold_attr == SERDES_IP_LANE_L1_CFG_RXBIST_STATUS_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxbitslip_locovr_attr == SERDES_IP_LANE_L1_CFG_RXBITSLIP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxbitslip_locovren_attr == SERDES_IP_LANE_L1_CFG_RXBITSLIP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxbscan_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxbshicm_attr == SERDES_IP_LANE_L1_CFG_RXBSHICM_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalcdrfbdiv_div2_bypass_muxd0_attr == SERDES_IP_LANE_L1_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalcdrfbdiv_div2_bypass_muxd1_attr == SERDES_IP_LANE_L1_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalcdrfbdiv_div2_bypass_muxd2_attr == SERDES_IP_LANE_L1_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalcdrfbdiv_div2_bypass_muxd3_attr == SERDES_IP_LANE_L1_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalcdrfbdiv_div2_bypass_muxd4_attr == SERDES_IP_LANE_L1_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalduty_iclk_gray_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalduty_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTY_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalduty_qclk_gray_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalduty_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutybg_abort_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutybg_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutybg_ready_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycomp_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycomp_offset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_finish_side_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_init_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_initval_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_invert_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_round_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_runcount_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsm_signmagen_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsmout_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompfsmout_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCOMPFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutycompmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_disable_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCTRL_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_i_div1_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_i_div2_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_i_div4_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_i_div8_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_q_div1_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_q_div2_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_q_div4_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyctrl_q_div8_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_bg_en_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_bg_one_step_cal_en_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_finish_side_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_i_polarity_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_I_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_i_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_I_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_init_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_q_polarity_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_Q_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_q_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_Q_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_round_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_runcount_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutyfsm_signmagen_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_comp_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEAS_COMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_comp_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEAS_COMP_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_i_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEAS_I_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_i_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEAS_I_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_q_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEAS_Q_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_q_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEAS_Q_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeasout_comp_ack_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEASOUT_COMP_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeasout_comp_erravg_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEASOUT_COMP_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeasout_i_ack_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEASOUT_I_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeasout_i_erravg_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEASOUT_I_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeasout_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeasout_q_ack_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEASOUT_Q_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutymeasout_q_erravg_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYMEASOUT_Q_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutystat_done_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaldutystat_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALDUTYSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_centerfreq_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_end_delay_attr == 9'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_hscount_muxd0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_hscount_muxd1_attr == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_hscount_muxd2_attr == 8'd180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_hscount_muxd3_attr == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_hscount_muxd4_attr == 8'd206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_initval_centerfreq_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_initval_fosc_attr == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfosc_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_centerfreq_finish_side_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_CENTERFREQ_FINISH_SIDE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_centerfreq_to_fosc_offset_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_centerfreqen_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_CENTERFREQEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_centerfreqoffset_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_fosc_finishside_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_FOSC_FINISHSIDE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_foscen_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_FOSCEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_foscoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_init_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_invert_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_lpfax_calfosccoarse_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_lpfax_calfoscfine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_lpfax_centerfreqcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_lpfax_centerfreqfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_runcount_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_signmagen_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsm_vcorepen_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSM_VCOREPEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsmout_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscfsmout_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_count_muxd0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_count_muxd1_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_count_muxd2_attr == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_count_muxd3_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_count_muxd4_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_dlycount_attr == 9'd68
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeasout_clear_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCMEASOUT_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeasout_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscmeasout_start_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCMEASOUT_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscval_int_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalfoscval_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALFOSCVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalintsval_int_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalintsval_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALINTSVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaloffsetfsm_init_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaloffsetfsm_init_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaloffsetfsm_init_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALOFFSETFSM_INIT_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaloffsetfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcaloffsetfsmout_input_en_attr == SERDES_IP_LANE_L1_CFG_RXCALOFFSETFSMOUT_INPUT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_duty_i_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_duty_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_dutycomp_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_foscfsm_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_offsetfsm_init_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_regopampoffset_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_rxppm_lockstatus_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_sqlch_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_sqlchosc_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_synthppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_pstate_voscregopampoffset_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_duty_i_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_duty_q_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_dutycomp_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_foscfsm_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_offsetfsm_init_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_rxppm_lockstatus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_sqlch_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_sqlchosc_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_synthppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalptr_quad_voscregopampoffset_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffset_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_finish_side_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_round_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_runcount_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsm_signmagen_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchfsm_clear_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchfsm_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchfsmout_caldone_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHFSMOUT_CALDONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchfsmout_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_codeoffset_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_finish_side_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHOSCFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_init_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHOSCFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_initval_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_invert_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHOSCFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHOSCFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHOSCFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_round_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHOSCFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscfsm_runcount_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHOSCFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscmeas_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHOSCMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscmeas_ref_cnt_attr == 10'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscmeas_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALSQLCHOSCMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscmeas_settle_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalsqlchoscmeas_smpl_cnt_attr == 10'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvbiascap_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALVBIASCAP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvbiascap_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALVBIASCAP_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvcoopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvcoopampoffsetmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvcoopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvcoopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffset_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffset_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_codeoffset_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_finish_side_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_initval_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_invert_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_lpfaxcoarse_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_round_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_runcount_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETFSM_RUNCOUNT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsm_signmagen_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsmout_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetfsmout_runcount_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETFSMOUT_RUNCOUNT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetmeas_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvcorepoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALVCOREPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffset_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALVOSCREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALVOSCREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L1_CFG_RXCALVOSCREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALVOSCREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALVOSCREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALVOSCREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALVOSCREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCALVOSCREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcalvoscregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCALVOSCREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrdiv_local_en_attr == SERDES_IP_LANE_L1_CFG_RXCDRDIV_LOCAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdiv_moddiv_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdiv_moddiv_muxd1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdiv_moddiv_muxd2_attr == 4'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdiv_moddiv_muxd3_attr == 4'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdiv_moddiv_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdivslip_mdiv_muxd0_attr == 9'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdivslip_mdiv_muxd1_attr == 9'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdivslip_mdiv_muxd2_attr == 9'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdivslip_mdiv_muxd3_attr == 9'd66
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrfbdivslip_mdiv_muxd4_attr == 9'd210
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrpfd_forcedn_attr == SERDES_IP_LANE_L1_CFG_RXCDRPFD_FORCEDN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrpfd_forceen_attr == SERDES_IP_LANE_L1_CFG_RXCDRPFD_FORCEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrpfd_forceup_attr == SERDES_IP_LANE_L1_CFG_RXCDRPFD_FORCEUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrpfd_propgain_attr == SERDES_IP_LANE_L1_CFG_RXCDRPFD_PROPGAIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrpfd_pulsewidth_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrphd_asym_override_ignore_attr == SERDES_IP_LANE_L1_CFG_RXCDRPHD_ASYM_OVERRIDE_IGNORE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrphd_bitshift_en_attr == SERDES_IP_LANE_L1_CFG_RXCDRPHD_BITSHIFT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrphd_forcedn_attr == SERDES_IP_LANE_L1_CFG_RXCDRPHD_FORCEDN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrphd_forceen_attr == SERDES_IP_LANE_L1_CFG_RXCDRPHD_FORCEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrphd_forceup_attr == SERDES_IP_LANE_L1_CFG_RXCDRPHD_FORCEUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrphdrate_doublerate2s2p_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCDRPHDRATE_DOUBLERATE2S2P_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrphdrate_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCDRPHDRATE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrrefck_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrrefck_refdiv_muxd1_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrrefck_refdiv_muxd2_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrrefck_refdiv_muxd3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrrefck_refdiv_muxd4_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_biastop_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_biastopbypass_attr == SERDES_IP_LANE_L1_CFG_RXCDRVCO_BIASTOPBYPASS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_datapropgain_high_attr == 5'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_datapropgain_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_datapropgain_low_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_ff_ovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_ff_ovr_en_attr == SERDES_IP_LANE_L1_CFG_RXCDRVCO_FF_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_fil_short_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_flickerdegen_attr == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_gmfoscshort_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCDRVCO_GMFOSCSHORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_intf_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_intf_fil_short_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_intrj_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCDRVCO_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_refpropgain_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxcdrvco_refpropgain_nom_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxclk_cdrfb_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCLK_CDRFB_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxclk_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L1_CFG_RXCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxclk_locovren_attr == SERDES_IP_LANE_L1_CFG_RXCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdat_nrz_64b80b_bcword_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdata_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXDATA_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdata_locovren_attr == SERDES_IP_LANE_L1_CFG_RXDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdatapath_locovren_attr == SERDES_IP_LANE_L1_CFG_RXDATAPATH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdatapath_on_state_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdatapath_ready_locovr_attr == SERDES_IP_LANE_L1_CFG_RXDATAPATH_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdfe_datatap_vcasc_attr == 4'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdfe_dfebiasadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdfe_nbiasctle_en_attr == SERDES_IP_LANE_L1_CFG_RXDFE_NBIASCTLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdfe_vcasc_sel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdfeterm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXDFETERM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdfeterm_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdfeyadjdac_datamid_edge_coarse_en_attr == SERDES_IP_LANE_L1_CFG_RXDFEYADJDAC_DATAMID_EDGE_COARSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdfeyadjdac_datatopbot_aux_coarse_en_attr == SERDES_IP_LANE_L1_CFG_RXDFEYADJDAC_DATATOPBOT_AUX_COARSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_accum_mon_en_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_ACCUM_MON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_accum_mon_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_bypasscdrpdetupdnsmpl_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_bypassenfosc_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_BYPASSENFOSC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_bypassenints_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_BYPASSENINTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_bypassenupdnsmpl_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_BYPASSENUPDNSMPL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_bypassfosc_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_bypasspllpfdupdnsmpl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_bypassrxints_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_data2pll_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_deltasigmode_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_DELTASIGMODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_fastref_muxd0_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_FASTREF_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_fastref_muxd1_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_FASTREF_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_fastref_muxd2_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_FASTREF_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_fastref_muxd3_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_FASTREF_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_fastref_muxd4_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_FASTREF_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_fosc_mod_bypass_en_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_FOSC_MOD_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_fosc_sample_pedge_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_FOSC_SAMPLE_PEDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gain_step_on_lock_recovery_en_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_GAIN_STEP_ON_LOCK_RECOVERY_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gaindelaycount_init_attr == 9'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gaindelaycount_pow2_muxd0_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gaindelaycount_pow2_muxd1_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gaindelaycount_pow2_muxd2_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gaindelaycount_pow2_muxd3_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gaindelaycount_pow2_muxd4_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2ref_pow2_muxd0_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2ref_pow2_muxd1_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2ref_pow2_muxd2_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2ref_pow2_muxd3_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainlocked2ref_pow2_muxd4_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainunlocked_pow2_muxd0_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainunlocked_pow2_muxd1_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainunlocked_pow2_muxd2_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainunlocked_pow2_muxd3_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_gainunlocked_pow2_muxd4_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_initintegrator_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_INITINTEGRATOR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_initmodulator_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_INITMODULATOR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_deltasig_mode_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_INTS_DELTASIG_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_freeze_en_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_INTS_FREEZE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gaindelaycount_pow2_muxd0_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gaindelaycount_pow2_muxd1_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gaindelaycount_pow2_muxd2_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gaindelaycount_pow2_muxd3_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gaindelaycount_pow2_muxd4_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd0_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd1_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd2_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd3_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd4_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd0_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd1_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd2_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd3_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd4_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainunlocked_pow2_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainunlocked_pow2_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainunlocked_pow2_muxd2_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainunlocked_pow2_muxd3_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_gainunlocked_pow2_muxd4_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_guardband_hi_attr == 8'd200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_guardband_lo_attr == 8'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_loop_sel_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_INTS_LOOP_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_mod_bypass_en_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_INTS_MOD_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_mod_load_pedge_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_INTS_MOD_LOAD_PEDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_ints_step_to_integer_en_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_INTS_STEP_TO_INTEGER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_jit_length_attr == 18'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_jit_mode_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_JIT_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_modck_ctrl_en_attr == SERDES_IP_LANE_L1_CFG_RXDPIF_MODCK_CTRL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_pll2data_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_restore_cntr_attr == 9'd258
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_store_cntr_attr == 16'd258
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpif_trnsfrdelay_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpiffreeze_inten_attr == SERDES_IP_LANE_L1_CFG_RXDPIFFREEZE_INTEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdpiffreeze_moden_attr == SERDES_IP_LANE_L1_CFG_RXDPIFFREEZE_MODEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxdutyselpolarity_attr == SERDES_IP_LANE_L1_CFG_RXDUTYSELPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxflxgate_force_rxeq_gate_locovr_attr == SERDES_IP_LANE_L1_CFG_RXFLXGATE_FORCE_RXEQ_GATE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxflxgate_locovren_attr == SERDES_IP_LANE_L1_CFG_RXFLXGATE_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxfoscstat_done_locovr_attr == SERDES_IP_LANE_L1_CFG_RXFOSCSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxfoscstat_locovren_attr == SERDES_IP_LANE_L1_CFG_RXFOSCSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxfsm_cken_ovr_attr == SERDES_IP_LANE_L1_CFG_RXFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxfsm_cken_ovren_attr == SERDES_IP_LANE_L1_CFG_RXFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxints_prev_votes_hold_en_attr == SERDES_IP_LANE_L1_CFG_RXINTS_PREV_VOTES_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxlanepam_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXLANEPAM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxlanepam_locovren_attr == SERDES_IP_LANE_L1_CFG_RXLANEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxlock2datatmr_attr == 8'd240
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxlock2datatmr_short_attr == 8'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxntl_changeref_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxntl_changeref_val_locovr_attr == SERDES_IP_LANE_L1_CFG_RXNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxntl_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxntl_en_attr == SERDES_IP_LANE_L1_CFG_RXNTL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxntl_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxntl_locovren_attr == SERDES_IP_LANE_L1_CFG_RXNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxntl_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxntl_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxntl_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxntl_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxntl_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxntl_rxm_charge_up_locovr_attr == SERDES_IP_LANE_L1_CFG_RXNTL_RXM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxntl_rxm_pull_dn_locovr_attr == SERDES_IP_LANE_L1_CFG_RXNTL_RXM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxntl_rxm_sense_locovr_attr == SERDES_IP_LANE_L1_CFG_RXNTL_RXM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxntl_rxp_charge_up_locovr_attr == SERDES_IP_LANE_L1_CFG_RXNTL_RXP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxntl_rxp_pull_dn_locovr_attr == SERDES_IP_LANE_L1_CFG_RXNTL_RXP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxntl_rxp_sense_locovr_attr == SERDES_IP_LANE_L1_CFG_RXNTL_RXP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxntl_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_acc_freeze_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_ACC_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_cdrlock2data_gater_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_cdrlock2data_gater_hold_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_cdrlock2data_gater_ovrd_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_cdrlock2datatmr_optcl_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_cdrlock2datatmr_optcl_sel_ovrd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_enter_lock2data_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_ENTER_LOCK2DATA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_enter_lock2data_hold_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_ENTER_LOCK2DATA_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_exit_lock2data_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_EXIT_LOCK2DATA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_exit_lock2data_hold_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_EXIT_LOCK2DATA_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_force_lock2data_ovrd_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_FORCE_LOCK2DATA_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_force_lock2ref_ovrd_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_FORCE_LOCK2REF_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_hold_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_hold_timer_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_intf_ovrd_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_INTF_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_intf_ovrd_type_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_INTF_OVRD_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_mod_freeze_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_MOD_FREEZE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_ovrd_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_ppm_detect_freeze_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_PPM_DETECT_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_ppm_detect_freeze_ovrd_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_PPM_DETECT_FREEZE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_ppm_detect_hold_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_PPM_DETECT_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_prop_freeze_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_PROP_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_prop_freeze_ovrd_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_PROP_FREEZE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_rxdata_en_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_RXDATA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxoptclfastlock_skip_init_lock2data_attr == SERDES_IP_LANE_L1_CFG_RXOPTCLFASTLOCK_SKIP_INIT_LOCK2DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxpam_bitorder_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxpam_gray_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXPAM_GRAY_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxpam_locovren_attr == SERDES_IP_LANE_L1_CFG_RXPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxpam_precode_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXPAM_PRECODE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_p5_muxd0_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIV_P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_p5_muxd1_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIV_P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_p5_muxd2_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIV_P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_p5_muxd3_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIV_P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdiv_p5_muxd4_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIV_P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdivclken_muxd0_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIVCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdivclken_muxd1_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIVCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdivclken_muxd2_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIVCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdivclken_muxd3_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIVCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxpcs_postdivclken_muxd4_attr == SERDES_IP_LANE_L1_CFG_RXPCS_POSTDIVCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxpcsbist_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXPCSBIST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxpcsbist_locovren_attr == SERDES_IP_LANE_L1_CFG_RXPCSBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxphd_gain_hold_en_attr == SERDES_IP_LANE_L1_CFG_RXPHD_GAIN_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxphd_gain_zero_locovr_attr == SERDES_IP_LANE_L1_CFG_RXPHD_GAIN_ZERO_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxphd_locovren_attr == SERDES_IP_LANE_L1_CFG_RXPHD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxphd_majvote_basegain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxphd_majvote_en_attr == SERDES_IP_LANE_L1_CFG_RXPHD_MAJVOTE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxphd_mute_cntr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxphd_nrz8b10b_pam16b20b_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxphd_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxphd_pam_transition_sel_attr == SERDES_IP_LANE_L1_CFG_RXPHD_PAM_TRANSITION_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxphd_sign_invert_attr == SERDES_IP_LANE_L1_CFG_RXPHD_SIGN_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxpostdiv_wait_for_lock_disable_attr == SERDES_IP_LANE_L1_CFG_RXPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxppm_freq_max_offset_h_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxppm_freq_max_offset_l_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxppm_freq_ref_cnt_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxppm_lockstatus_locovr_attr == SERDES_IP_LANE_L1_CFG_RXPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxppm_lockstatus_synthlcfast_en_attr == SERDES_IP_LANE_L1_CFG_RXPPM_LOCKSTATUS_SYNTHLCFAST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxppm_lockstatus_synthlcmed_en_attr == SERDES_IP_LANE_L1_CFG_RXPPM_LOCKSTATUS_SYNTHLCMED_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxppm_lockstatus_synthlcslow_en_attr == SERDES_IP_LANE_L1_CFG_RXPPM_LOCKSTATUS_SYNTHLCSLOW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxppm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxppm_ppmdriftcount_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxppm_ppmdriftmax_attr == 16'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxppm_status_hold_attr == SERDES_IP_LANE_L1_CFG_RXPPM_STATUS_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxppm_unlock_clear_attr == SERDES_IP_LANE_L1_CFG_RXPPM_UNLOCK_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_fast_muxd0_attr == 16'd666
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_fast_muxd1_attr == 16'd4000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_fast_muxd2_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_fast_muxd3_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_fast_muxd4_attr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_muxd0_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_muxd1_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_muxd2_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_muxd3_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxppm_watchdogtmr_muxd4_attr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxppmctrl_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXPPMCTRL_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxppmctrl_locovren_attr == SERDES_IP_LANE_L1_CFG_RXPPMCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxppmlockstat_locovren_attr == SERDES_IP_LANE_L1_CFG_RXPPMLOCKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxppmlockstat_sticky_locovr_attr == SERDES_IP_LANE_L1_CFG_RXPPMLOCKSTAT_STICKY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxppmtmr_locovren_attr == SERDES_IP_LANE_L1_CFG_RXPPMTMR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxppmtmr_watchdogtmr_sel_locovr_attr == SERDES_IP_LANE_L1_CFG_RXPPMTMR_WATCHDOGTMR_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_cal_clear_delay_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_clk_chk_disable_attr == SERDES_IP_LANE_L1_CFG_RXRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_clk_delay_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_etr_on_delay_attr == 12'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_locovren_attr == SERDES_IP_LANE_L1_CFG_RXRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxreg_lev_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxreg_toggle_reset_on_rate_change_en_attr == SERDES_IP_LANE_L1_CFG_RXREG_TOGGLE_RESET_ON_RATE_CHANGE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxreg_vreg_bypass_attr == SERDES_IP_LANE_L1_CFG_RXREG_VREG_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_en_b_attr == SERDES_IP_LANE_L1_CFG_RXRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s0q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s0q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s2q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s2q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s2q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s2q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s2q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s2q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s2q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s3q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s3q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s3q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s3q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s3q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s3q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s3q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s3q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s4q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s4q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evdn_delay_lut_sel_s5q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_entry2_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_entry4_attr == 13'd78
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_entry5_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_entry6_attr == 13'd1406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s0q2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s0q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s1q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s1q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s1q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s1q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s1q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s1q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s2q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s2q2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s2q3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s2q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s2q5_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s2q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s2q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s3q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s3q1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s3q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s3q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s3q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s3q5_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s3q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s3q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s4q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s4q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpu_evup_delay_lut_sel_s5q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_duty_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_fosc_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cal_sqlch_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_cdrfb_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrfbdivcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_cdrmoddivcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpuetr_termhiz_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_auxcomp_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_datfbdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_dfe_yadj_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_hifreqagc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_sqlch_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpupd_vco_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_cdrfbdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_dpif_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pdet_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_pfd_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_ppm_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pa_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrpurst_s2pb_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_aetrrx_cdrfbdivcken_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_AETRRX_CDRFBDIVCKEN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_aetrrx_cdrfbdivcken_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_AETRRX_CDRFBDIVCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_aetrrx_cdrmoddivcken_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_AETRRX_CDRMODDIVCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_aetrrx_cdrmoddivcken_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_AETRRX_CDRMODDIVCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_aetrrx_termhiz_en_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_AETRRX_TERMHIZ_EN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_aetrrx_termhiz_en_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_AETRRX_TERMHIZ_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_aetrsynth_pcspostdivclksel_ovr_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_AETRSYNTH_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_aetrsynth_pcspostdivclksel_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_AETRSYNTH_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_adc_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_adc_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_auxcomp_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_AUXCOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_auxcomp_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_AUXCOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_bias_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_bias_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_BIAS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_ctlecomp_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_CTLECOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_ctlecomp_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_CTLECOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_datfbdiv_b_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DATFBDIV_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_datfbdiv_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DATFBDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_dfe_bias_b_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DFE_BIAS_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_dfe_bias_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DFE_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_dfe_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DFE_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_dfe_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DFE_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_dfe_yadj_b_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DFE_YADJ_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_dfe_yadj_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DFE_YADJ_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_duty_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DUTY_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_duty_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_DUTY_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_hifreqagc_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_HIFREQAGC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_hifreqagc_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_HIFREQAGC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_ntl_b_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_ntl_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_reg_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_reg_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_vco_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_VCO_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_vco_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_VCO_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_voscreg_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_VOSCREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_apdrx_voscreg_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_APDRX_VOSCREG_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_adc_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_adc_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_cdrfbdiv_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_CDRFBDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_cdrfbdiv_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_CDRFBDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_pdet_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_PDET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_pdet_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_PDET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_pfd_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_PFD_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_pfd_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_PFD_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_refdiv_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_refdiv_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_reg_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_reg_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_s2pa_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_S2PA_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_s2pa_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_S2PA_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_s2pb_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_S2PB_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_s2pb_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_S2PB_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_vco_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_VCO_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_vco_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_VCO_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_voscreg_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_VOSCREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstrx_voscreg_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTRX_VOSCREG_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstsynth_postdiv_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTSYNTH_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_arstsynth_postdiv_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_ARSTSYNTH_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_drstrx_dpif_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_DRSTRX_DPIF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_drstrx_dpif_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_DRSTRX_DPIF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_drstrx_ppm_ovr_b_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_DRSTRX_PPM_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxrstpdovr_drstrx_ppm_ovren_attr == SERDES_IP_LANE_L1_CFG_RXRSTPDOVR_DRSTRX_PPM_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_cdrlock2data_locovr_attr == SERDES_IP_LANE_L1_CFG_RXSIGDET_CDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_diglfpsdeten_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_diglfpsdeten_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_diglfpsdeten_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_diglfpsdeten_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_diglfpsdeten_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrancnten_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrancnten_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrancnten_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrancnten_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrancnten_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrancnten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrandeten_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrandeten_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrandeten_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrandeten_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrandeten_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_digtrandeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_eiosdeten_muxd0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_eiosdeten_muxd1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_eiosdeten_muxd2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_eiosdeten_muxd3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_eiosdeten_muxd4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_eiosdeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_enable_attr == SERDES_IP_LANE_L1_CFG_RXSIGDET_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_fastlock_winsize_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_leveldeten_muxd0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_leveldeten_muxd1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_leveldeten_muxd2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_leveldeten_muxd3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_leveldeten_muxd4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_leveldeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_lfpsexit_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_locovren_attr == SERDES_IP_LANE_L1_CFG_RXSIGDET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_ppmdeten_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_ppmdeten_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_ppmdeten_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_ppmdeten_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_ppmdeten_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_ppmdeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_rxeq_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_rxeqen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_rxeqen_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_rxleveldet_debounce_dncount_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_rxleveldet_debounce_flush_en_attr == SERDES_IP_LANE_L1_CFG_RXSIGDET_RXLEVELDET_DEBOUNCE_FLUSH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_rxleveldet_debounce_upcount_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_sigdet_debounce_attr == SERDES_IP_LANE_L1_CFG_RXSIGDET_SIGDET_DEBOUNCE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_tmr_clksel_attr == SERDES_IP_LANE_L1_CFG_RXSIGDET_TMR_CLKSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_toggle_count_en_attr == SERDES_IP_LANE_L1_CFG_RXSIGDET_TOGGLE_COUNT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_toggle_count_pause_attr == SERDES_IP_LANE_L1_CFG_RXSIGDET_TOGGLE_COUNT_PAUSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdet_toggle_monitor_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdetin_eiosdetectstat_locovr_attr == SERDES_IP_LANE_L1_CFG_RXSIGDETIN_EIOSDETECTSTAT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdetin_locovren_attr == SERDES_IP_LANE_L1_CFG_RXSIGDETIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdetin_ovrcdrlock2data_locovr_attr == SERDES_IP_LANE_L1_CFG_RXSIGDETIN_OVRCDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdetin_ovrencdrlock2data_locovr_attr == SERDES_IP_LANE_L1_CFG_RXSIGDETIN_OVRENCDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdetout_lock2data_noforce_ltr_locovr_attr == SERDES_IP_LANE_L1_CFG_RXSIGDETOUT_LOCK2DATA_NOFORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsigdetout_locovren_attr == SERDES_IP_LANE_L1_CFG_RXSIGDETOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxspare0_attr == 32'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxspare_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsqlchlfps_consec_one_thresh_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsqlchlfps_consec_zero_thresh_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsqlchlfps_cycle_thresh_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsqlchlfps_dat_bitorder_attr == SERDES_IP_LANE_L1_CFG_RXSQLCHLFPS_DAT_BITORDER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsqlchlfps_debounce_type_attr == SERDES_IP_LANE_L1_CFG_RXSQLCHLFPS_DEBOUNCE_TYPE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsqlchlfps_one_run_length_thresh_attr == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsqlchlfps_one_run_length_timeout_attr == 8'd103
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsqlchlfps_zero_run_length_thresh_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsqlchlfps_zero_run_length_timeout_attr == 8'd103
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsynthdiv_slowmed_en_muxd0_attr == SERDES_IP_LANE_L1_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsynthdiv_slowmed_en_muxd1_attr == SERDES_IP_LANE_L1_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsynthdiv_slowmed_en_muxd2_attr == SERDES_IP_LANE_L1_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsynthdiv_slowmed_en_muxd3_attr == SERDES_IP_LANE_L1_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxsynthdiv_slowmed_en_muxd4_attr == SERDES_IP_LANE_L1_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxterm_cal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxterm_coarse_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxterm_locovren_attr == SERDES_IP_LANE_L1_CFG_RXTERM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxterm_modeselect_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxtermhiz_en_locovr_attr == SERDES_IP_LANE_L1_CFG_RXTERMHIZ_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxtermhiz_locovren_attr == SERDES_IP_LANE_L1_CFG_RXTERMHIZ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxvoscreg_bypass_vosc_attr == SERDES_IP_LANE_L1_CFG_RXVOSCREG_BYPASS_VOSC_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxvoscregopampoffsetctrl_sel_attr == SERDES_IP_LANE_L1_CFG_RXVOSCREGOPAMPOFFSETCTRL_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxvoscregopampoffseterr_locovren_attr == SERDES_IP_LANE_L1_CFG_RXVOSCREGOPAMPOFFSETERR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxvoscregopampoffseterr_sel_locovr_attr == SERDES_IP_LANE_L1_CFG_RXVOSCREGOPAMPOFFSETERR_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxvoscregvref_locovren_attr == SERDES_IP_LANE_L1_CFG_RXVOSCREGVREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_rxvoscregvref_sel_locovr_attr == SERDES_IP_LANE_L1_CFG_RXVOSCREGVREF_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlch_acqgain_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlch_acqtime_attr == 13'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlch_cal_quiet_locovr_attr == SERDES_IP_LANE_L1_CFG_SQLCH_CAL_QUIET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlch_cal_sel_locovr_attr == SERDES_IP_LANE_L1_CFG_SQLCH_CAL_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlch_calctrl_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlch_calen_locovr_attr == SERDES_IP_LANE_L1_CFG_SQLCH_CALEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlch_caltimer_attr == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlch_clkgate_locovr_attr == SERDES_IP_LANE_L1_CFG_SQLCH_CLKGATE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlch_cmshiften_attr == SERDES_IP_LANE_L1_CFG_SQLCH_CMSHIFTEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_acq_gain_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_acq_pct_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_cal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_clr_errlog_attr == SERDES_IP_LANE_L1_CFG_SQLCH_CONT_CLR_ERRLOG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_controller_mode_attr == SERDES_IP_LANE_L1_CFG_SQLCH_CONT_CONTROLLER_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_dis_attr == SERDES_IP_LANE_L1_CFG_SQLCH_CONT_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_pause_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_postcal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_precal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlch_cont_quiet_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlch_lfps_en_attr == SERDES_IP_LANE_L1_CFG_SQLCH_LFPS_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlch_locovren_attr == SERDES_IP_LANE_L1_CFG_SQLCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlch_ovrd_val_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlch_pkdet_freqsel_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlch_polarity_attr == SERDES_IP_LANE_L1_CFG_SQLCH_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlch_rdacen_attr == SERDES_IP_LANE_L1_CFG_SQLCH_RDACEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlch_thresh_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlch_time_out_attr == 16'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlch_vrefsel0_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlch_vrefsel1_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlch_vrefsel_ovr_en_attr == SERDES_IP_LANE_L1_CFG_SQLCH_VREFSEL_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlchdeb_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlchdeb_deb_cnt_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlchdeb_deb_status_cnt_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlchdeb_en_attr == SERDES_IP_LANE_L1_CFG_SQLCHDEB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlchdeb_ign_cnt_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlchdeb_sigdet_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlchdeb_thresh_cnt_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlchdebout_exit_good_debounced_locovr_attr == SERDES_IP_LANE_L1_CFG_SQLCHDEBOUT_EXIT_GOOD_DEBOUNCED_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlchdebout_exit_good_debounced_status_locovr_attr == SERDES_IP_LANE_L1_CFG_SQLCHDEBOUT_EXIT_GOOD_DEBOUNCED_STATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlchdebout_exit_good_locovr_attr == SERDES_IP_LANE_L1_CFG_SQLCHDEBOUT_EXIT_GOOD_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_sqlchdebout_locovren_attr == SERDES_IP_LANE_L1_CFG_SQLCHDEBOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_trancnt_off_attr == 10'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_trancnt_on_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_trancntout_det_locovr_attr == SERDES_IP_LANE_L1_CFG_TRANCNTOUT_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_trancntout_locovren_attr == SERDES_IP_LANE_L1_CFG_TRANCNTOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_trandet_ax_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_trandet_ay_attr == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_trandet_off_h_attr == 6'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_trandet_off_l_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_trandet_on_h_attr == 6'd39
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_trandet_on_l_attr == 6'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_trandetout_det_locovr_attr == SERDES_IP_LANE_L1_CFG_TRANDETOUT_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_trandetout_locovren_attr == SERDES_IP_LANE_L1_CFG_TRANDETOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_tx2rxlb_en_attr == SERDES_IP_LANE_L1_CFG_TX2RXLB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_tx2rxlb_init_offset_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_tx_cmn_on_state_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_tx_fastregpwrup_en_attr == SERDES_IP_LANE_L1_CFG_TX_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_tx_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_tx_pg_disable_attr == SERDES_IP_LANE_L1_CFG_TX_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_tx_synth_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_tx_synth_sel_amode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_tx_synth_sel_bmode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_tx_synth_sel_cmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_tx_synth_sel_dmode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_tx_synth_sel_emode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_tx_txdetrx_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txadc_req_attr == SERDES_IP_LANE_L1_CFG_TXADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txaprobe_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txaprobe_lastmux_isolate_attr == SERDES_IP_LANE_L1_CFG_TXAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txaprobeadc_current_direction_attr == SERDES_IP_LANE_L1_CFG_TXAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txaprobeadc_resistor_enable_attr == SERDES_IP_LANE_L1_CFG_TXAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txbdvdr_pma2pcstxworden_attr == SERDES_IP_LANE_L1_CFG_TXBDVDR_PMA2PCSTXWORDEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txbeacon_div_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txbeacon_sel_attr == SERDES_IP_LANE_L1_CFG_TXBEACON_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txbias_icc20uadj_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txbias_icc80uadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txbias_locovren_attr == SERDES_IP_LANE_L1_CFG_TXBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txbias_termcal_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txbist_biterror_en_attr == SERDES_IP_LANE_L1_CFG_TXBIST_BITERROR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txbist_locovren_attr == SERDES_IP_LANE_L1_CFG_TXBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txbist_modesel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txbist_oobmode_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txbist_oobtburst_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txbist_oobtcomrstinit_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txbist_oobtcomsas_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txbist_oobtcomwake_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txbist_seed_attr == 31'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_size_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf00_attr == 32'd1985229328
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf01_attr == 32'd4275878552
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf02_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf03_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf04_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf05_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf06_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf07_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf08_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txbist_udp_vf09_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txbit_select_muxd0_attr == SERDES_IP_LANE_L1_CFG_TXBIT_SELECT_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txbit_select_muxd1_attr == SERDES_IP_LANE_L1_CFG_TXBIT_SELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txbit_select_muxd2_attr == SERDES_IP_LANE_L1_CFG_TXBIT_SELECT_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txbit_select_muxd3_attr == SERDES_IP_LANE_L1_CFG_TXBIT_SELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txbit_select_muxd4_attr == SERDES_IP_LANE_L1_CFG_TXBIT_SELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txbti_data_replication_attr == SERDES_IP_LANE_L1_CFG_TXBTI_DATA_REPLICATION_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txbti_tx_idle_data_en_attr == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcal_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcal_tclkduty_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalduty_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalduty_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTY_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalduty_sel_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutybg_abort_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutybg_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutybg_ready_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutycomp_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutycomp_offset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_finish_side_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_init_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_initval_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_invert_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_req_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_round_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_runcount_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsm_signmagen_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsmout_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompfsmout_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompmeas_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompmeas_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompmeas_req_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompmeasout_ack_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPMEASOUT_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompmeasout_erravg_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPMEASOUT_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutycompmeasout_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYCOMPMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_bg_en_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_bg_one_step_cal_en_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_finish_side_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_init_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_invert_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_req_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_round_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_runcount_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutyfsm_signmagen_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeas_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeas_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeas_req_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeasout_ack_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYMEASOUT_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeasout_erravg_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYMEASOUT_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutymeasout_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutystat_done_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaldutystat_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALDUTYSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalptr_pstate_duty_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalptr_pstate_dutycomp_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalptr_pstate_regopampoffset_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_duty_muxd0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_duty_muxd1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_duty_muxd2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_duty_muxd3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_duty_muxd4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_dutycomp_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_dutycomp_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_dutycomp_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_dutycomp_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_dutycomp_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_regopampoffset_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalptr_quad_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffset_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_finish_side_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_round_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_runcount_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsm_signmagen_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcaltclkdutyforce_div1_attr == SERDES_IP_LANE_L1_CFG_TXCALTCLKDUTYFORCE_DIV1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txcdrdiv_local_en_attr == SERDES_IP_LANE_L1_CFG_TXCDRDIV_LOCAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txclk_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L1_CFG_TXCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txclk_locovren_attr == SERDES_IP_LANE_L1_CFG_TXCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txclkgenmuxsel_txinternal_attr == SERDES_IP_LANE_L1_CFG_TXCLKGENMUXSEL_TXINTERNAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txdetectrx_thr_attr == 5'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeas_count_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeas_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXDETECTRXMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeas_locovren_attr == SERDES_IP_LANE_L1_CFG_TXDETECTRXMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeas_validdlycount_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeasin_locovren_attr == SERDES_IP_LANE_L1_CFG_TXDETECTRXMEASIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeasin_start_locovr_attr == SERDES_IP_LANE_L1_CFG_TXDETECTRXMEASIN_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeaspcs_locovren_attr == SERDES_IP_LANE_L1_CFG_TXDETECTRXMEASPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeaspcs_req_locovr_attr == SERDES_IP_LANE_L1_CFG_TXDETECTRXMEASPCS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeasval_locovren_attr == SERDES_IP_LANE_L1_CFG_TXDETECTRXMEASVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txdetectrxmeasval_stat_locovr_attr == SERDES_IP_LANE_L1_CFG_TXDETECTRXMEASVAL_STAT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txdetrx_levn_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txdetrx_levnm1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txdetrx_levnp1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txdetrx_levnp2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txdrv_hizen_locovr_attr == SERDES_IP_LANE_L1_CFG_TXDRV_HIZEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txdrv_levn_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txdrv_levnm1_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txdrv_levnp1_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txdrv_levnp2_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txdrv_locovren_attr == SERDES_IP_LANE_L1_CFG_TXDRV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txdrv_refcken_attr == SERDES_IP_LANE_L1_CFG_TXDRV_REFCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txdrv_termref_attr == SERDES_IP_LANE_L1_CFG_TXDRV_TERMREF_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txdrvmute_locovr_attr == SERDES_IP_LANE_L1_CFG_TXDRVMUTE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txdrvmute_locovren_attr == SERDES_IP_LANE_L1_CFG_TXDRVMUTE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txduty_ctrl_disable_attr == SERDES_IP_LANE_L1_CFG_TXDUTY_CTRL_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txduty_pad_sense_en_attr == SERDES_IP_LANE_L1_CFG_TXDUTY_PAD_SENSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txdutycal_div16_en_attr == SERDES_IP_LANE_L1_CFG_TXDUTYCAL_DIV16_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txdutycal_div1_en_attr == SERDES_IP_LANE_L1_CFG_TXDUTYCAL_DIV1_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txdutycal_div2_en_attr == SERDES_IP_LANE_L1_CFG_TXDUTYCAL_DIV2_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txdutycal_div4_en_attr == SERDES_IP_LANE_L1_CFG_TXDUTYCAL_DIV4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txdutycal_div8_en_attr == SERDES_IP_LANE_L1_CFG_TXDUTYCAL_DIV8_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txfifo_elecidle_deskew_en_attr == SERDES_IP_LANE_L1_CFG_TXFIFO_ELECIDLE_DESKEW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txfifo_force_txidlebit1_zero_disable_attr == SERDES_IP_LANE_L1_CFG_TXFIFO_FORCE_TXIDLEBIT1_ZERO_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txfifo_kill_dly_10b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txfifo_kill_dly_16b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txfifo_kill_dly_20b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txfifo_kill_dly_32b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txfifo_kill_dly_40b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txfifo_kill_dly_64b_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txfifo_kill_dly_80b_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txfifo_kill_dly_8b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txfifo_kill_en_attr == SERDES_IP_LANE_L1_CFG_TXFIFO_KILL_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txfsm_cken_ovr_attr == SERDES_IP_LANE_L1_CFG_TXFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txfsm_cken_ovren_attr == SERDES_IP_LANE_L1_CFG_TXFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txfsm_main_on_state_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txl1d1_doze_ctrl_attr == SERDES_IP_LANE_L1_CFG_TXL1D1_DOZE_CTRL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txl1d1_txbias_ctrl_attr == SERDES_IP_LANE_L1_CFG_TXL1D1_TXBIAS_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txlanepam_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXLANEPAM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txlanepam_locovren_attr == SERDES_IP_LANE_L1_CFG_TXLANEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txmeaslatovrhd_meas_sel_attr == SERDES_IP_LANE_L1_CFG_TXMEASLATOVRHD_MEAS_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txmute_delay_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txntl_changeref_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txntl_changeref_val_locovr_attr == SERDES_IP_LANE_L1_CFG_TXNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txntl_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txntl_en_attr == SERDES_IP_LANE_L1_CFG_TXNTL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txntl_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txntl_locovren_attr == SERDES_IP_LANE_L1_CFG_TXNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txntl_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txntl_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txntl_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txntl_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txntl_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txntl_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txntl_txm_charge_up_locovr_attr == SERDES_IP_LANE_L1_CFG_TXNTL_TXM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txntl_txm_pull_dn_locovr_attr == SERDES_IP_LANE_L1_CFG_TXNTL_TXM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txntl_txm_sense_locovr_attr == SERDES_IP_LANE_L1_CFG_TXNTL_TXM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txntl_txp_charge_up_locovr_attr == SERDES_IP_LANE_L1_CFG_TXNTL_TXP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txntl_txp_pull_dn_locovr_attr == SERDES_IP_LANE_L1_CFG_TXNTL_TXP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txntl_txp_sense_locovr_attr == SERDES_IP_LANE_L1_CFG_TXNTL_TXP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txp2s_txwordsyncbypen_attr == SERDES_IP_LANE_L1_CFG_TXP2S_TXWORDSYNCBYPEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txpam_bitorder_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txpam_gray_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXPAM_GRAY_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txpam_locovren_attr == SERDES_IP_LANE_L1_CFG_TXPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txpam_precode_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXPAM_PRECODE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txpcs_locovren_attr == SERDES_IP_LANE_L1_CFG_TXPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txpcs_txenable_locovr_attr == SERDES_IP_LANE_L1_CFG_TXPCS_TXENABLE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txpcsbist_en_locovr_attr == SERDES_IP_LANE_L1_CFG_TXPCSBIST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txpcsbist_locovren_attr == SERDES_IP_LANE_L1_CFG_TXPCSBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txratewidth_clk_chk_disable_attr == SERDES_IP_LANE_L1_CFG_TXRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txratewidth_etr_on_delay_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txratewidth_locovren_attr == SERDES_IP_LANE_L1_CFG_TXRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txreg_toggle_pwrupacc_on_rate_change_en_attr == SERDES_IP_LANE_L1_CFG_TXREG_TOGGLE_PWRUPACC_ON_RATE_CHANGE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txreg_toggle_reset_on_rate_change_en_attr == SERDES_IP_LANE_L1_CFG_TXREG_TOGGLE_RESET_ON_RATE_CHANGE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txresetdel_sel_attr == SERDES_IP_LANE_L1_CFG_TXRESETDEL_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_en_b_attr == SERDES_IP_LANE_L1_CFG_TXRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s0q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s0q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s1q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s1q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s2q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s2q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s2q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s2q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s2q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s2q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s2q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s3q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s3q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s3q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s3q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s3q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s3q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s3q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s3q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s4q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s4q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evdn_delay_lut_sel_s5q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_entry2_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s0q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s0q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s1q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s1q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s1q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s1q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s1q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s1q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s2q0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s2q1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s2q2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s2q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s2q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s2q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s2q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s2q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s3q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s3q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s3q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s3q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s3q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s3q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s3q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s3q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s4q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s4q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpu_evup_delay_lut_sel_s5q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_duty_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_bitckdvdrcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_dn_ptr0_s_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_up_ptr0_s_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_drvdoze_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_p2s_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpurst_pma2pcstxword_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpurst_regreset_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrpurst_txdetectrx_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_aetrtx_bitckdvdrcken_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_AETRTX_BITCKDVDRCKEN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_aetrtx_bitckdvdrcken_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_AETRTX_BITCKDVDRCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_aetrtx_regpwrupacc_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_AETRTX_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_aetrtx_regpwrupacc_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_AETRTX_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_adc_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_adc_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_drvdoze_b_ovr_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_DRVDOZE_B_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_drvdoze_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_DRVDOZE_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_duty_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_DUTY_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_duty_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_DUTY_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_ntl_b_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_ntl_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_p2s_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_P2S_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_p2s_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_P2S_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_reg_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_apdtx_reg_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_APDTX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_arsttx_adc_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_ARSTTX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_arsttx_adc_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_ARSTTX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_arsttx_pma2pcstxword_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_ARSTTX_PMA2PCSTXWORD_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_arsttx_pma2pcstxword_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_ARSTTX_PMA2PCSTXWORD_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_arsttx_regreset_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_ARSTTX_REGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_arsttx_regreset_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_ARSTTX_REGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_arsttx_txdetectrx_ovr_b_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_ARSTTX_TXDETECTRX_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrstpdovr_arsttx_txdetectrx_ovren_attr == SERDES_IP_LANE_L1_CFG_TXRSTPDOVR_ARSTTX_TXDETECTRX_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txrststate_hiz_en_attr == SERDES_IP_LANE_L1_CFG_TXRSTSTATE_HIZ_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txspare0_attr == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txspare_attr == 10'd384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txterm_coarse_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txtermtrim_locovren_attr == SERDES_IP_LANE_L1_CFG_TXTERMTRIM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txtermtrim_nmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txtermtrim_pmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txwclk_div_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txwclk_div_en_attr == SERDES_IP_LANE_L1_CFG_TXWCLK_DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txwclk_div_smpl_attr == SERDES_IP_LANE_L1_CFG_TXWCLK_DIV_SMPL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txwptr_init01_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txwptr_init02_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txwptr_init04_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txwptr_init08_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txwptr_init16_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txwptr_init32_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l1_cfg_txwptr_init_rx2txparlb_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_bshihyst_attr == SERDES_IP_LANE_L2_CFG_BSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_bstxdrv_levn_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_bstxdrv_levnm1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_bstxdrv_levnp1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_bstxdrv_levnp2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_calsqlchosc_locovren_attr == SERDES_IP_LANE_L2_CFG_CALSQLCHOSC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_calsqlchosc_trimcode_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_cdrclkstat_locovren_attr == SERDES_IP_LANE_L2_CFG_CDRCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_cdrclkstat_ready_locovr_attr == SERDES_IP_LANE_L2_CFG_CDRCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_etrregrxcdrclk_ready_attr == SERDES_IP_LANE_L2_CFG_ETRREGRXCDRCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_laneckm_avg_en_attr == SERDES_IP_LANE_L2_CFG_LANECKM_AVG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_laneckm_clk_en_attr == SERDES_IP_LANE_L2_CFG_LANECKM_CLK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_laneckm_continuous_attr == SERDES_IP_LANE_L2_CFG_LANECKM_CONTINUOUS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_laneckm_dig_meas_en_attr == SERDES_IP_LANE_L2_CFG_LANECKM_DIG_MEAS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_laneckm_dig_meas_err_clr_attr == SERDES_IP_LANE_L2_CFG_LANECKM_DIG_MEAS_ERR_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_laneckm_en_attr == SERDES_IP_LANE_L2_CFG_LANECKM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_laneckm_max_thr_attr == 25'd33554431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_laneckm_meas_ck_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_laneckm_ref_ck_div_ratio_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_laneckm_result_clr_attr == SERDES_IP_LANE_L2_CFG_LANECKM_RESULT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_laneckm_start_attr == SERDES_IP_LANE_L2_CFG_LANECKM_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_laneckm_wdt_interval_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_laneckm_win_thr_ref_attr == 25'd16777215
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_lanepcs_locovren_attr == SERDES_IP_LANE_L2_CFG_LANEPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_lanepcs_mode_locovr_attr == SERDES_IP_LANE_L2_CFG_LANEPCS_MODE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_laneperfmon_compare_val_start_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_laneperfmon_compare_val_stop_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_laneperfmon_en_attr == SERDES_IP_LANE_L2_CFG_LANEPERFMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_laneperfmon_mask_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_lanepmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_lanepmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_lanepmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_lanepmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_lanepmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_lanepmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_lb_cdrclk2txen_locovr_attr == SERDES_IP_LANE_L2_CFG_LB_CDRCLK2TXEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_lb_cdrclkdiven_attr == SERDES_IP_LANE_L2_CFG_LB_CDRCLKDIVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_lb_cdrdivclk2exten_attr == SERDES_IP_LANE_L2_CFG_LB_CDRDIVCLK2EXTEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_lb_cdrdivclk2txen_attr == SERDES_IP_LANE_L2_CFG_LB_CDRDIVCLK2TXEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_lb_hsclk2cdrdiven_attr == SERDES_IP_LANE_L2_CFG_LB_HSCLK2CDRDIVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_lb_locovren_attr == SERDES_IP_LANE_L2_CFG_LB_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_lb_parrx2txtimeden_locovr_attr == SERDES_IP_LANE_L2_CFG_LB_PARRX2TXTIMEDEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_lb_pllfbclk2cdrrefclken_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_lb_pllfbclk2cdrrefclken_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_lb_pllfbclk2cdrrefclken_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_lb_pllfbclk2cdrrefclken_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_lb_pllfbclk2cdrrefclken_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_lb_rx2txuntimeden_attr == SERDES_IP_LANE_L2_CFG_LB_RX2TXUNTIMEDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_lb_rxwordck2pcstxwordcken_attr == SERDES_IP_LANE_L2_CFG_LB_RXWORDCK2PCSTXWORDCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_lb_tx2rxbuftimeden_lsb_locovr_attr == SERDES_IP_LANE_L2_CFG_LB_TX2RXBUFTIMEDEN_LSB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_lb_tx2rxbuftimeden_msb_locovr_attr == SERDES_IP_LANE_L2_CFG_LB_TX2RXBUFTIMEDEN_MSB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_lb_tx2rxiotimeden_attr == SERDES_IP_LANE_L2_CFG_LB_TX2RXIOTIMEDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_lfps_det_locovr_attr == SERDES_IP_LANE_L2_CFG_LFPS_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_lfps_locovren_attr == SERDES_IP_LANE_L2_CFG_LFPS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_lfps_out_en_attr == SERDES_IP_LANE_L2_CFG_LFPS_OUT_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_pcslfps_en_locovr_attr == SERDES_IP_LANE_L2_CFG_PCSLFPS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_pcslfps_locovren_attr == SERDES_IP_LANE_L2_CFG_PCSLFPS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_pcsrx_dme_en_locovr_attr == SERDES_IP_LANE_L2_CFG_PCSRX_DME_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_pcsrx_locovren_attr == SERDES_IP_LANE_L2_CFG_PCSRX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_pcsrxbist_locovren_attr == SERDES_IP_LANE_L2_CFG_PCSRXBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_pcsrxbist_modesel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_pcstx_beaconen_locovr_attr == SERDES_IP_LANE_L2_CFG_PCSTX_BEACONEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_pcstx_locovren_attr == SERDES_IP_LANE_L2_CFG_PCSTX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_polarity_rx_attr == SERDES_IP_LANE_L2_CFG_POLARITY_RX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_polarity_tx_attr == SERDES_IP_LANE_L2_CFG_POLARITY_TX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rx_cmn_on_state_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rx_fastregpwrup_en_attr == SERDES_IP_LANE_L2_CFG_RX_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rx_frac_mode_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rx_on_state_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rx_pg_disable_attr == SERDES_IP_LANE_L2_CFG_RX_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rx_synth_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rx_synth_sel_amode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rx_synth_sel_bmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rx_synth_sel_cmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rx_synth_sel_dmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rx_synth_sel_emode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxadc_req_attr == SERDES_IP_LANE_L2_CFG_RXADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxagc_dccoupleen_attr == SERDES_IP_LANE_L2_CFG_RXAGC_DCCOUPLEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxaprobe_addr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxaprobe_lastmux_isolate_attr == SERDES_IP_LANE_L2_CFG_RXAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxaprobeadc_current_direction_attr == SERDES_IP_LANE_L2_CFG_RXAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxaprobeadc_resistor_enable_attr == SERDES_IP_LANE_L2_CFG_RXAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxbias_iccadj_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxbias_icvadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxbias_locovren_attr == SERDES_IP_LANE_L2_CFG_RXBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxbias_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxbist_burst_four_errtype_attr == SERDES_IP_LANE_L2_CFG_RXBIST_BURST_FOUR_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxbist_burst_one_errtype_attr == SERDES_IP_LANE_L2_CFG_RXBIST_BURST_ONE_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxbist_burst_three_errtype_attr == SERDES_IP_LANE_L2_CFG_RXBIST_BURST_THREE_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxbist_burst_two_errtype_attr == SERDES_IP_LANE_L2_CFG_RXBIST_BURST_TWO_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxbist_cdrlock2data_bypass_attr == SERDES_IP_LANE_L2_CFG_RXBIST_CDRLOCK2DATA_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxbist_cdrlock2data_postamble_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxbist_clear_errcount_attr == SERDES_IP_LANE_L2_CFG_RXBIST_CLEAR_ERRCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxbist_err_en_attr == SERDES_IP_LANE_L2_CFG_RXBIST_ERR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxbist_err_trig_type_attr == SERDES_IP_LANE_L2_CFG_RXBIST_ERR_TRIG_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxbist_errmask_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxbist_errtype_attr == SERDES_IP_LANE_L2_CFG_RXBIST_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxbist_firsterr_type_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxbist_lockchk_count_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxbist_maxbitcnt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxbist_mostrecent_err_attr == SERDES_IP_LANE_L2_CFG_RXBIST_MOSTRECENT_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxbist_relock_itercount_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxbist_seed_attr == 31'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxbist_status_hold_attr == SERDES_IP_LANE_L2_CFG_RXBIST_STATUS_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxbitslip_locovr_attr == SERDES_IP_LANE_L2_CFG_RXBITSLIP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxbitslip_locovren_attr == SERDES_IP_LANE_L2_CFG_RXBITSLIP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxbscan_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxbshicm_attr == SERDES_IP_LANE_L2_CFG_RXBSHICM_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalcdrfbdiv_div2_bypass_muxd0_attr == SERDES_IP_LANE_L2_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalcdrfbdiv_div2_bypass_muxd1_attr == SERDES_IP_LANE_L2_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalcdrfbdiv_div2_bypass_muxd2_attr == SERDES_IP_LANE_L2_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalcdrfbdiv_div2_bypass_muxd3_attr == SERDES_IP_LANE_L2_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalcdrfbdiv_div2_bypass_muxd4_attr == SERDES_IP_LANE_L2_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalduty_iclk_gray_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalduty_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTY_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalduty_qclk_gray_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalduty_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutybg_abort_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutybg_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutybg_ready_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycomp_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycomp_offset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_finish_side_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_init_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_initval_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_invert_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_round_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_runcount_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsm_signmagen_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsmout_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompfsmout_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCOMPFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutycompmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_disable_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCTRL_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_i_div1_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_i_div2_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_i_div4_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_i_div8_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_q_div1_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_q_div2_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_q_div4_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyctrl_q_div8_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_bg_en_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_bg_one_step_cal_en_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_finish_side_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_i_polarity_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_I_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_i_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_I_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_init_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_q_polarity_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_Q_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_q_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_Q_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_round_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_runcount_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutyfsm_signmagen_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_comp_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEAS_COMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_comp_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEAS_COMP_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_i_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEAS_I_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_i_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEAS_I_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_q_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEAS_Q_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_q_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEAS_Q_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeasout_comp_ack_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEASOUT_COMP_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeasout_comp_erravg_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEASOUT_COMP_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeasout_i_ack_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEASOUT_I_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeasout_i_erravg_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEASOUT_I_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeasout_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeasout_q_ack_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEASOUT_Q_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutymeasout_q_erravg_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYMEASOUT_Q_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutystat_done_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaldutystat_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALDUTYSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_centerfreq_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_end_delay_attr == 9'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_hscount_muxd0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_hscount_muxd1_attr == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_hscount_muxd2_attr == 8'd180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_hscount_muxd3_attr == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_hscount_muxd4_attr == 8'd206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_initval_centerfreq_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_initval_fosc_attr == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfosc_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_centerfreq_finish_side_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_CENTERFREQ_FINISH_SIDE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_centerfreq_to_fosc_offset_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_centerfreqen_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_CENTERFREQEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_centerfreqoffset_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_fosc_finishside_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_FOSC_FINISHSIDE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_foscen_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_FOSCEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_foscoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_init_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_invert_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_lpfax_calfosccoarse_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_lpfax_calfoscfine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_lpfax_centerfreqcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_lpfax_centerfreqfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_runcount_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_signmagen_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsm_vcorepen_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSM_VCOREPEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsmout_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscfsmout_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_count_muxd0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_count_muxd1_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_count_muxd2_attr == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_count_muxd3_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_count_muxd4_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_dlycount_attr == 9'd68
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeasout_clear_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCMEASOUT_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeasout_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscmeasout_start_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCMEASOUT_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscval_int_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalfoscval_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALFOSCVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalintsval_int_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalintsval_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALINTSVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaloffsetfsm_init_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaloffsetfsm_init_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaloffsetfsm_init_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALOFFSETFSM_INIT_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaloffsetfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcaloffsetfsmout_input_en_attr == SERDES_IP_LANE_L2_CFG_RXCALOFFSETFSMOUT_INPUT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_duty_i_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_duty_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_dutycomp_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_foscfsm_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_offsetfsm_init_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_regopampoffset_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_rxppm_lockstatus_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_sqlch_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_sqlchosc_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_synthppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_pstate_voscregopampoffset_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_duty_i_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_duty_q_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_dutycomp_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_foscfsm_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_offsetfsm_init_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_rxppm_lockstatus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_sqlch_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_sqlchosc_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_synthppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalptr_quad_voscregopampoffset_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffset_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_finish_side_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_round_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_runcount_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsm_signmagen_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchfsm_clear_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchfsm_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchfsmout_caldone_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHFSMOUT_CALDONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchfsmout_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_codeoffset_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_finish_side_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHOSCFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_init_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHOSCFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_initval_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_invert_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHOSCFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHOSCFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHOSCFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_round_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHOSCFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscfsm_runcount_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHOSCFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscmeas_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHOSCMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscmeas_ref_cnt_attr == 10'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscmeas_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALSQLCHOSCMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscmeas_settle_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalsqlchoscmeas_smpl_cnt_attr == 10'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvbiascap_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALVBIASCAP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvbiascap_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALVBIASCAP_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvcoopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvcoopampoffsetmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvcoopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvcoopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffset_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffset_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_codeoffset_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_finish_side_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_initval_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_invert_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_lpfaxcoarse_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_round_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_runcount_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETFSM_RUNCOUNT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsm_signmagen_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsmout_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetfsmout_runcount_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETFSMOUT_RUNCOUNT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetmeas_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvcorepoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALVCOREPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffset_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALVOSCREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALVOSCREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L2_CFG_RXCALVOSCREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALVOSCREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALVOSCREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALVOSCREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALVOSCREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCALVOSCREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcalvoscregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCALVOSCREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrdiv_local_en_attr == SERDES_IP_LANE_L2_CFG_RXCDRDIV_LOCAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdiv_moddiv_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdiv_moddiv_muxd1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdiv_moddiv_muxd2_attr == 4'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdiv_moddiv_muxd3_attr == 4'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdiv_moddiv_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdivslip_mdiv_muxd0_attr == 9'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdivslip_mdiv_muxd1_attr == 9'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdivslip_mdiv_muxd2_attr == 9'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdivslip_mdiv_muxd3_attr == 9'd66
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrfbdivslip_mdiv_muxd4_attr == 9'd210
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrpfd_forcedn_attr == SERDES_IP_LANE_L2_CFG_RXCDRPFD_FORCEDN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrpfd_forceen_attr == SERDES_IP_LANE_L2_CFG_RXCDRPFD_FORCEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrpfd_forceup_attr == SERDES_IP_LANE_L2_CFG_RXCDRPFD_FORCEUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrpfd_propgain_attr == SERDES_IP_LANE_L2_CFG_RXCDRPFD_PROPGAIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrpfd_pulsewidth_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrphd_asym_override_ignore_attr == SERDES_IP_LANE_L2_CFG_RXCDRPHD_ASYM_OVERRIDE_IGNORE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrphd_bitshift_en_attr == SERDES_IP_LANE_L2_CFG_RXCDRPHD_BITSHIFT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrphd_forcedn_attr == SERDES_IP_LANE_L2_CFG_RXCDRPHD_FORCEDN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrphd_forceen_attr == SERDES_IP_LANE_L2_CFG_RXCDRPHD_FORCEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrphd_forceup_attr == SERDES_IP_LANE_L2_CFG_RXCDRPHD_FORCEUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrphdrate_doublerate2s2p_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCDRPHDRATE_DOUBLERATE2S2P_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrphdrate_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCDRPHDRATE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrrefck_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrrefck_refdiv_muxd1_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrrefck_refdiv_muxd2_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrrefck_refdiv_muxd3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrrefck_refdiv_muxd4_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_biastop_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_biastopbypass_attr == SERDES_IP_LANE_L2_CFG_RXCDRVCO_BIASTOPBYPASS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_datapropgain_high_attr == 5'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_datapropgain_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_datapropgain_low_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_ff_ovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_ff_ovr_en_attr == SERDES_IP_LANE_L2_CFG_RXCDRVCO_FF_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_fil_short_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_flickerdegen_attr == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_gmfoscshort_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCDRVCO_GMFOSCSHORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_intf_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_intf_fil_short_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_intrj_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCDRVCO_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_refpropgain_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxcdrvco_refpropgain_nom_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxclk_cdrfb_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCLK_CDRFB_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxclk_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L2_CFG_RXCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxclk_locovren_attr == SERDES_IP_LANE_L2_CFG_RXCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdat_nrz_64b80b_bcword_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdata_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXDATA_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdata_locovren_attr == SERDES_IP_LANE_L2_CFG_RXDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdatapath_locovren_attr == SERDES_IP_LANE_L2_CFG_RXDATAPATH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdatapath_on_state_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdatapath_ready_locovr_attr == SERDES_IP_LANE_L2_CFG_RXDATAPATH_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdfe_datatap_vcasc_attr == 4'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdfe_dfebiasadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdfe_nbiasctle_en_attr == SERDES_IP_LANE_L2_CFG_RXDFE_NBIASCTLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdfe_vcasc_sel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdfeterm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXDFETERM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdfeterm_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdfeyadjdac_datamid_edge_coarse_en_attr == SERDES_IP_LANE_L2_CFG_RXDFEYADJDAC_DATAMID_EDGE_COARSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdfeyadjdac_datatopbot_aux_coarse_en_attr == SERDES_IP_LANE_L2_CFG_RXDFEYADJDAC_DATATOPBOT_AUX_COARSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_accum_mon_en_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_ACCUM_MON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_accum_mon_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_bypasscdrpdetupdnsmpl_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_bypassenfosc_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_BYPASSENFOSC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_bypassenints_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_BYPASSENINTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_bypassenupdnsmpl_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_BYPASSENUPDNSMPL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_bypassfosc_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_bypasspllpfdupdnsmpl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_bypassrxints_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_data2pll_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_deltasigmode_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_DELTASIGMODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_fastref_muxd0_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_FASTREF_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_fastref_muxd1_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_FASTREF_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_fastref_muxd2_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_FASTREF_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_fastref_muxd3_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_FASTREF_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_fastref_muxd4_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_FASTREF_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_fosc_mod_bypass_en_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_FOSC_MOD_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_fosc_sample_pedge_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_FOSC_SAMPLE_PEDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gain_step_on_lock_recovery_en_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_GAIN_STEP_ON_LOCK_RECOVERY_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gaindelaycount_init_attr == 9'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gaindelaycount_pow2_muxd0_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gaindelaycount_pow2_muxd1_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gaindelaycount_pow2_muxd2_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gaindelaycount_pow2_muxd3_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gaindelaycount_pow2_muxd4_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2ref_pow2_muxd0_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2ref_pow2_muxd1_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2ref_pow2_muxd2_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2ref_pow2_muxd3_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainlocked2ref_pow2_muxd4_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainunlocked_pow2_muxd0_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainunlocked_pow2_muxd1_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainunlocked_pow2_muxd2_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainunlocked_pow2_muxd3_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_gainunlocked_pow2_muxd4_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_initintegrator_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_INITINTEGRATOR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_initmodulator_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_INITMODULATOR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_deltasig_mode_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_INTS_DELTASIG_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_freeze_en_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_INTS_FREEZE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gaindelaycount_pow2_muxd0_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gaindelaycount_pow2_muxd1_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gaindelaycount_pow2_muxd2_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gaindelaycount_pow2_muxd3_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gaindelaycount_pow2_muxd4_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd0_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd1_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd2_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd3_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd4_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd0_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd1_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd2_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd3_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd4_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainunlocked_pow2_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainunlocked_pow2_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainunlocked_pow2_muxd2_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainunlocked_pow2_muxd3_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_gainunlocked_pow2_muxd4_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_guardband_hi_attr == 8'd200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_guardband_lo_attr == 8'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_loop_sel_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_INTS_LOOP_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_mod_bypass_en_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_INTS_MOD_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_mod_load_pedge_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_INTS_MOD_LOAD_PEDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_ints_step_to_integer_en_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_INTS_STEP_TO_INTEGER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_jit_length_attr == 18'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_jit_mode_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_JIT_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_modck_ctrl_en_attr == SERDES_IP_LANE_L2_CFG_RXDPIF_MODCK_CTRL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_pll2data_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_restore_cntr_attr == 9'd258
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_store_cntr_attr == 16'd258
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpif_trnsfrdelay_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpiffreeze_inten_attr == SERDES_IP_LANE_L2_CFG_RXDPIFFREEZE_INTEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdpiffreeze_moden_attr == SERDES_IP_LANE_L2_CFG_RXDPIFFREEZE_MODEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxdutyselpolarity_attr == SERDES_IP_LANE_L2_CFG_RXDUTYSELPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxflxgate_force_rxeq_gate_locovr_attr == SERDES_IP_LANE_L2_CFG_RXFLXGATE_FORCE_RXEQ_GATE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxflxgate_locovren_attr == SERDES_IP_LANE_L2_CFG_RXFLXGATE_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxfoscstat_done_locovr_attr == SERDES_IP_LANE_L2_CFG_RXFOSCSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxfoscstat_locovren_attr == SERDES_IP_LANE_L2_CFG_RXFOSCSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxfsm_cken_ovr_attr == SERDES_IP_LANE_L2_CFG_RXFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxfsm_cken_ovren_attr == SERDES_IP_LANE_L2_CFG_RXFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxints_prev_votes_hold_en_attr == SERDES_IP_LANE_L2_CFG_RXINTS_PREV_VOTES_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxlanepam_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXLANEPAM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxlanepam_locovren_attr == SERDES_IP_LANE_L2_CFG_RXLANEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxlock2datatmr_attr == 8'd240
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxlock2datatmr_short_attr == 8'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxntl_changeref_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxntl_changeref_val_locovr_attr == SERDES_IP_LANE_L2_CFG_RXNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxntl_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxntl_en_attr == SERDES_IP_LANE_L2_CFG_RXNTL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxntl_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxntl_locovren_attr == SERDES_IP_LANE_L2_CFG_RXNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxntl_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxntl_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxntl_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxntl_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxntl_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxntl_rxm_charge_up_locovr_attr == SERDES_IP_LANE_L2_CFG_RXNTL_RXM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxntl_rxm_pull_dn_locovr_attr == SERDES_IP_LANE_L2_CFG_RXNTL_RXM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxntl_rxm_sense_locovr_attr == SERDES_IP_LANE_L2_CFG_RXNTL_RXM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxntl_rxp_charge_up_locovr_attr == SERDES_IP_LANE_L2_CFG_RXNTL_RXP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxntl_rxp_pull_dn_locovr_attr == SERDES_IP_LANE_L2_CFG_RXNTL_RXP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxntl_rxp_sense_locovr_attr == SERDES_IP_LANE_L2_CFG_RXNTL_RXP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxntl_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_acc_freeze_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_ACC_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_cdrlock2data_gater_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_cdrlock2data_gater_hold_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_cdrlock2data_gater_ovrd_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_cdrlock2datatmr_optcl_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_cdrlock2datatmr_optcl_sel_ovrd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_enter_lock2data_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_ENTER_LOCK2DATA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_enter_lock2data_hold_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_ENTER_LOCK2DATA_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_exit_lock2data_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_EXIT_LOCK2DATA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_exit_lock2data_hold_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_EXIT_LOCK2DATA_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_force_lock2data_ovrd_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_FORCE_LOCK2DATA_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_force_lock2ref_ovrd_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_FORCE_LOCK2REF_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_hold_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_hold_timer_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_intf_ovrd_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_INTF_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_intf_ovrd_type_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_INTF_OVRD_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_mod_freeze_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_MOD_FREEZE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_ovrd_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_ppm_detect_freeze_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_PPM_DETECT_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_ppm_detect_freeze_ovrd_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_PPM_DETECT_FREEZE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_ppm_detect_hold_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_PPM_DETECT_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_prop_freeze_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_PROP_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_prop_freeze_ovrd_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_PROP_FREEZE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_rxdata_en_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_RXDATA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxoptclfastlock_skip_init_lock2data_attr == SERDES_IP_LANE_L2_CFG_RXOPTCLFASTLOCK_SKIP_INIT_LOCK2DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxpam_bitorder_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxpam_gray_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXPAM_GRAY_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxpam_locovren_attr == SERDES_IP_LANE_L2_CFG_RXPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxpam_precode_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXPAM_PRECODE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_p5_muxd0_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIV_P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_p5_muxd1_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIV_P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_p5_muxd2_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIV_P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_p5_muxd3_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIV_P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdiv_p5_muxd4_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIV_P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdivclken_muxd0_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIVCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdivclken_muxd1_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIVCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdivclken_muxd2_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIVCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdivclken_muxd3_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIVCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxpcs_postdivclken_muxd4_attr == SERDES_IP_LANE_L2_CFG_RXPCS_POSTDIVCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxpcsbist_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXPCSBIST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxpcsbist_locovren_attr == SERDES_IP_LANE_L2_CFG_RXPCSBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxphd_gain_hold_en_attr == SERDES_IP_LANE_L2_CFG_RXPHD_GAIN_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxphd_gain_zero_locovr_attr == SERDES_IP_LANE_L2_CFG_RXPHD_GAIN_ZERO_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxphd_locovren_attr == SERDES_IP_LANE_L2_CFG_RXPHD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxphd_majvote_basegain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxphd_majvote_en_attr == SERDES_IP_LANE_L2_CFG_RXPHD_MAJVOTE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxphd_mute_cntr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxphd_nrz8b10b_pam16b20b_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxphd_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxphd_pam_transition_sel_attr == SERDES_IP_LANE_L2_CFG_RXPHD_PAM_TRANSITION_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxphd_sign_invert_attr == SERDES_IP_LANE_L2_CFG_RXPHD_SIGN_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxpostdiv_wait_for_lock_disable_attr == SERDES_IP_LANE_L2_CFG_RXPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxppm_freq_max_offset_h_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxppm_freq_max_offset_l_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxppm_freq_ref_cnt_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxppm_lockstatus_locovr_attr == SERDES_IP_LANE_L2_CFG_RXPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxppm_lockstatus_synthlcfast_en_attr == SERDES_IP_LANE_L2_CFG_RXPPM_LOCKSTATUS_SYNTHLCFAST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxppm_lockstatus_synthlcmed_en_attr == SERDES_IP_LANE_L2_CFG_RXPPM_LOCKSTATUS_SYNTHLCMED_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxppm_lockstatus_synthlcslow_en_attr == SERDES_IP_LANE_L2_CFG_RXPPM_LOCKSTATUS_SYNTHLCSLOW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxppm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxppm_ppmdriftcount_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxppm_ppmdriftmax_attr == 16'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxppm_status_hold_attr == SERDES_IP_LANE_L2_CFG_RXPPM_STATUS_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxppm_unlock_clear_attr == SERDES_IP_LANE_L2_CFG_RXPPM_UNLOCK_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_fast_muxd0_attr == 16'd666
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_fast_muxd1_attr == 16'd4000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_fast_muxd2_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_fast_muxd3_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_fast_muxd4_attr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_muxd0_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_muxd1_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_muxd2_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_muxd3_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxppm_watchdogtmr_muxd4_attr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxppmctrl_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXPPMCTRL_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxppmctrl_locovren_attr == SERDES_IP_LANE_L2_CFG_RXPPMCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxppmlockstat_locovren_attr == SERDES_IP_LANE_L2_CFG_RXPPMLOCKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxppmlockstat_sticky_locovr_attr == SERDES_IP_LANE_L2_CFG_RXPPMLOCKSTAT_STICKY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxppmtmr_locovren_attr == SERDES_IP_LANE_L2_CFG_RXPPMTMR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxppmtmr_watchdogtmr_sel_locovr_attr == SERDES_IP_LANE_L2_CFG_RXPPMTMR_WATCHDOGTMR_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_cal_clear_delay_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_clk_chk_disable_attr == SERDES_IP_LANE_L2_CFG_RXRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_clk_delay_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_etr_on_delay_attr == 12'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_locovren_attr == SERDES_IP_LANE_L2_CFG_RXRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxreg_lev_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxreg_toggle_reset_on_rate_change_en_attr == SERDES_IP_LANE_L2_CFG_RXREG_TOGGLE_RESET_ON_RATE_CHANGE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxreg_vreg_bypass_attr == SERDES_IP_LANE_L2_CFG_RXREG_VREG_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_en_b_attr == SERDES_IP_LANE_L2_CFG_RXRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s0q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s0q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s2q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s2q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s2q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s2q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s2q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s2q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s2q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s3q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s3q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s3q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s3q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s3q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s3q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s3q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s3q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s4q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s4q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evdn_delay_lut_sel_s5q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_entry2_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_entry4_attr == 13'd78
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_entry5_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_entry6_attr == 13'd1406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s0q2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s0q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s1q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s1q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s1q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s1q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s1q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s1q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s2q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s2q2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s2q3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s2q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s2q5_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s2q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s2q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s3q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s3q1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s3q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s3q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s3q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s3q5_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s3q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s3q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s4q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s4q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpu_evup_delay_lut_sel_s5q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_duty_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_fosc_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cal_sqlch_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_cdrfb_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrfbdivcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_cdrmoddivcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpuetr_termhiz_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_auxcomp_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_datfbdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_dfe_yadj_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_hifreqagc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_sqlch_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpupd_vco_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_cdrfbdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_dpif_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pdet_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_pfd_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_ppm_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pa_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrpurst_s2pb_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_aetrrx_cdrfbdivcken_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_AETRRX_CDRFBDIVCKEN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_aetrrx_cdrfbdivcken_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_AETRRX_CDRFBDIVCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_aetrrx_cdrmoddivcken_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_AETRRX_CDRMODDIVCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_aetrrx_cdrmoddivcken_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_AETRRX_CDRMODDIVCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_aetrrx_termhiz_en_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_AETRRX_TERMHIZ_EN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_aetrrx_termhiz_en_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_AETRRX_TERMHIZ_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_aetrsynth_pcspostdivclksel_ovr_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_AETRSYNTH_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_aetrsynth_pcspostdivclksel_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_AETRSYNTH_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_adc_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_adc_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_auxcomp_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_AUXCOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_auxcomp_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_AUXCOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_bias_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_bias_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_BIAS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_ctlecomp_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_CTLECOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_ctlecomp_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_CTLECOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_datfbdiv_b_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DATFBDIV_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_datfbdiv_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DATFBDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_dfe_bias_b_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DFE_BIAS_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_dfe_bias_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DFE_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_dfe_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DFE_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_dfe_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DFE_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_dfe_yadj_b_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DFE_YADJ_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_dfe_yadj_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DFE_YADJ_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_duty_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DUTY_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_duty_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_DUTY_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_hifreqagc_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_HIFREQAGC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_hifreqagc_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_HIFREQAGC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_ntl_b_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_ntl_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_reg_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_reg_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_vco_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_VCO_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_vco_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_VCO_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_voscreg_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_VOSCREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_apdrx_voscreg_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_APDRX_VOSCREG_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_adc_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_adc_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_cdrfbdiv_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_CDRFBDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_cdrfbdiv_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_CDRFBDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_pdet_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_PDET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_pdet_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_PDET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_pfd_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_PFD_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_pfd_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_PFD_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_refdiv_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_refdiv_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_reg_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_reg_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_s2pa_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_S2PA_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_s2pa_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_S2PA_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_s2pb_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_S2PB_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_s2pb_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_S2PB_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_vco_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_VCO_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_vco_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_VCO_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_voscreg_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_VOSCREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstrx_voscreg_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTRX_VOSCREG_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstsynth_postdiv_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTSYNTH_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_arstsynth_postdiv_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_ARSTSYNTH_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_drstrx_dpif_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_DRSTRX_DPIF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_drstrx_dpif_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_DRSTRX_DPIF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_drstrx_ppm_ovr_b_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_DRSTRX_PPM_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxrstpdovr_drstrx_ppm_ovren_attr == SERDES_IP_LANE_L2_CFG_RXRSTPDOVR_DRSTRX_PPM_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_cdrlock2data_locovr_attr == SERDES_IP_LANE_L2_CFG_RXSIGDET_CDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_diglfpsdeten_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_diglfpsdeten_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_diglfpsdeten_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_diglfpsdeten_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_diglfpsdeten_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrancnten_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrancnten_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrancnten_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrancnten_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrancnten_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrancnten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrandeten_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrandeten_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrandeten_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrandeten_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrandeten_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_digtrandeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_eiosdeten_muxd0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_eiosdeten_muxd1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_eiosdeten_muxd2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_eiosdeten_muxd3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_eiosdeten_muxd4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_eiosdeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_enable_attr == SERDES_IP_LANE_L2_CFG_RXSIGDET_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_fastlock_winsize_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_leveldeten_muxd0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_leveldeten_muxd1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_leveldeten_muxd2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_leveldeten_muxd3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_leveldeten_muxd4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_leveldeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_lfpsexit_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_locovren_attr == SERDES_IP_LANE_L2_CFG_RXSIGDET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_ppmdeten_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_ppmdeten_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_ppmdeten_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_ppmdeten_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_ppmdeten_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_ppmdeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_rxeq_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_rxeqen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_rxeqen_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_rxleveldet_debounce_dncount_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_rxleveldet_debounce_flush_en_attr == SERDES_IP_LANE_L2_CFG_RXSIGDET_RXLEVELDET_DEBOUNCE_FLUSH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_rxleveldet_debounce_upcount_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_sigdet_debounce_attr == SERDES_IP_LANE_L2_CFG_RXSIGDET_SIGDET_DEBOUNCE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_tmr_clksel_attr == SERDES_IP_LANE_L2_CFG_RXSIGDET_TMR_CLKSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_toggle_count_en_attr == SERDES_IP_LANE_L2_CFG_RXSIGDET_TOGGLE_COUNT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_toggle_count_pause_attr == SERDES_IP_LANE_L2_CFG_RXSIGDET_TOGGLE_COUNT_PAUSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdet_toggle_monitor_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdetin_eiosdetectstat_locovr_attr == SERDES_IP_LANE_L2_CFG_RXSIGDETIN_EIOSDETECTSTAT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdetin_locovren_attr == SERDES_IP_LANE_L2_CFG_RXSIGDETIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdetin_ovrcdrlock2data_locovr_attr == SERDES_IP_LANE_L2_CFG_RXSIGDETIN_OVRCDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdetin_ovrencdrlock2data_locovr_attr == SERDES_IP_LANE_L2_CFG_RXSIGDETIN_OVRENCDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdetout_lock2data_noforce_ltr_locovr_attr == SERDES_IP_LANE_L2_CFG_RXSIGDETOUT_LOCK2DATA_NOFORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsigdetout_locovren_attr == SERDES_IP_LANE_L2_CFG_RXSIGDETOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxspare0_attr == 32'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxspare_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsqlchlfps_consec_one_thresh_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsqlchlfps_consec_zero_thresh_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsqlchlfps_cycle_thresh_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsqlchlfps_dat_bitorder_attr == SERDES_IP_LANE_L2_CFG_RXSQLCHLFPS_DAT_BITORDER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsqlchlfps_debounce_type_attr == SERDES_IP_LANE_L2_CFG_RXSQLCHLFPS_DEBOUNCE_TYPE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsqlchlfps_one_run_length_thresh_attr == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsqlchlfps_one_run_length_timeout_attr == 8'd103
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsqlchlfps_zero_run_length_thresh_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsqlchlfps_zero_run_length_timeout_attr == 8'd103
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsynthdiv_slowmed_en_muxd0_attr == SERDES_IP_LANE_L2_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsynthdiv_slowmed_en_muxd1_attr == SERDES_IP_LANE_L2_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsynthdiv_slowmed_en_muxd2_attr == SERDES_IP_LANE_L2_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsynthdiv_slowmed_en_muxd3_attr == SERDES_IP_LANE_L2_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxsynthdiv_slowmed_en_muxd4_attr == SERDES_IP_LANE_L2_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxterm_cal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxterm_coarse_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxterm_locovren_attr == SERDES_IP_LANE_L2_CFG_RXTERM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxterm_modeselect_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxtermhiz_en_locovr_attr == SERDES_IP_LANE_L2_CFG_RXTERMHIZ_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxtermhiz_locovren_attr == SERDES_IP_LANE_L2_CFG_RXTERMHIZ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxvoscreg_bypass_vosc_attr == SERDES_IP_LANE_L2_CFG_RXVOSCREG_BYPASS_VOSC_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxvoscregopampoffsetctrl_sel_attr == SERDES_IP_LANE_L2_CFG_RXVOSCREGOPAMPOFFSETCTRL_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxvoscregopampoffseterr_locovren_attr == SERDES_IP_LANE_L2_CFG_RXVOSCREGOPAMPOFFSETERR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxvoscregopampoffseterr_sel_locovr_attr == SERDES_IP_LANE_L2_CFG_RXVOSCREGOPAMPOFFSETERR_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxvoscregvref_locovren_attr == SERDES_IP_LANE_L2_CFG_RXVOSCREGVREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_rxvoscregvref_sel_locovr_attr == SERDES_IP_LANE_L2_CFG_RXVOSCREGVREF_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlch_acqgain_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlch_acqtime_attr == 13'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlch_cal_quiet_locovr_attr == SERDES_IP_LANE_L2_CFG_SQLCH_CAL_QUIET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlch_cal_sel_locovr_attr == SERDES_IP_LANE_L2_CFG_SQLCH_CAL_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlch_calctrl_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlch_calen_locovr_attr == SERDES_IP_LANE_L2_CFG_SQLCH_CALEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlch_caltimer_attr == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlch_clkgate_locovr_attr == SERDES_IP_LANE_L2_CFG_SQLCH_CLKGATE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlch_cmshiften_attr == SERDES_IP_LANE_L2_CFG_SQLCH_CMSHIFTEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_acq_gain_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_acq_pct_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_cal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_clr_errlog_attr == SERDES_IP_LANE_L2_CFG_SQLCH_CONT_CLR_ERRLOG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_controller_mode_attr == SERDES_IP_LANE_L2_CFG_SQLCH_CONT_CONTROLLER_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_dis_attr == SERDES_IP_LANE_L2_CFG_SQLCH_CONT_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_pause_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_postcal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_precal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlch_cont_quiet_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlch_lfps_en_attr == SERDES_IP_LANE_L2_CFG_SQLCH_LFPS_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlch_locovren_attr == SERDES_IP_LANE_L2_CFG_SQLCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlch_ovrd_val_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlch_pkdet_freqsel_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlch_polarity_attr == SERDES_IP_LANE_L2_CFG_SQLCH_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlch_rdacen_attr == SERDES_IP_LANE_L2_CFG_SQLCH_RDACEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlch_thresh_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlch_time_out_attr == 16'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlch_vrefsel0_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlch_vrefsel1_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlch_vrefsel_ovr_en_attr == SERDES_IP_LANE_L2_CFG_SQLCH_VREFSEL_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlchdeb_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlchdeb_deb_cnt_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlchdeb_deb_status_cnt_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlchdeb_en_attr == SERDES_IP_LANE_L2_CFG_SQLCHDEB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlchdeb_ign_cnt_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlchdeb_sigdet_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlchdeb_thresh_cnt_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlchdebout_exit_good_debounced_locovr_attr == SERDES_IP_LANE_L2_CFG_SQLCHDEBOUT_EXIT_GOOD_DEBOUNCED_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlchdebout_exit_good_debounced_status_locovr_attr == SERDES_IP_LANE_L2_CFG_SQLCHDEBOUT_EXIT_GOOD_DEBOUNCED_STATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlchdebout_exit_good_locovr_attr == SERDES_IP_LANE_L2_CFG_SQLCHDEBOUT_EXIT_GOOD_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_sqlchdebout_locovren_attr == SERDES_IP_LANE_L2_CFG_SQLCHDEBOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_trancnt_off_attr == 10'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_trancnt_on_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_trancntout_det_locovr_attr == SERDES_IP_LANE_L2_CFG_TRANCNTOUT_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_trancntout_locovren_attr == SERDES_IP_LANE_L2_CFG_TRANCNTOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_trandet_ax_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_trandet_ay_attr == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_trandet_off_h_attr == 6'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_trandet_off_l_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_trandet_on_h_attr == 6'd39
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_trandet_on_l_attr == 6'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_trandetout_det_locovr_attr == SERDES_IP_LANE_L2_CFG_TRANDETOUT_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_trandetout_locovren_attr == SERDES_IP_LANE_L2_CFG_TRANDETOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_tx2rxlb_en_attr == SERDES_IP_LANE_L2_CFG_TX2RXLB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_tx2rxlb_init_offset_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_tx_cmn_on_state_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_tx_fastregpwrup_en_attr == SERDES_IP_LANE_L2_CFG_TX_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_tx_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_tx_pg_disable_attr == SERDES_IP_LANE_L2_CFG_TX_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_tx_synth_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_tx_synth_sel_amode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_tx_synth_sel_bmode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_tx_synth_sel_cmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_tx_synth_sel_dmode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_tx_synth_sel_emode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_tx_txdetrx_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txadc_req_attr == SERDES_IP_LANE_L2_CFG_TXADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txaprobe_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txaprobe_lastmux_isolate_attr == SERDES_IP_LANE_L2_CFG_TXAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txaprobeadc_current_direction_attr == SERDES_IP_LANE_L2_CFG_TXAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txaprobeadc_resistor_enable_attr == SERDES_IP_LANE_L2_CFG_TXAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txbdvdr_pma2pcstxworden_attr == SERDES_IP_LANE_L2_CFG_TXBDVDR_PMA2PCSTXWORDEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txbeacon_div_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txbeacon_sel_attr == SERDES_IP_LANE_L2_CFG_TXBEACON_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txbias_icc20uadj_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txbias_icc80uadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txbias_locovren_attr == SERDES_IP_LANE_L2_CFG_TXBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txbias_termcal_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txbist_biterror_en_attr == SERDES_IP_LANE_L2_CFG_TXBIST_BITERROR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txbist_locovren_attr == SERDES_IP_LANE_L2_CFG_TXBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txbist_modesel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txbist_oobmode_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txbist_oobtburst_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txbist_oobtcomrstinit_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txbist_oobtcomsas_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txbist_oobtcomwake_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txbist_seed_attr == 31'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_size_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf00_attr == 32'd1985229328
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf01_attr == 32'd4275878552
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf02_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf03_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf04_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf05_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf06_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf07_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf08_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txbist_udp_vf09_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txbit_select_muxd0_attr == SERDES_IP_LANE_L2_CFG_TXBIT_SELECT_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txbit_select_muxd1_attr == SERDES_IP_LANE_L2_CFG_TXBIT_SELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txbit_select_muxd2_attr == SERDES_IP_LANE_L2_CFG_TXBIT_SELECT_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txbit_select_muxd3_attr == SERDES_IP_LANE_L2_CFG_TXBIT_SELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txbit_select_muxd4_attr == SERDES_IP_LANE_L2_CFG_TXBIT_SELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txbti_data_replication_attr == SERDES_IP_LANE_L2_CFG_TXBTI_DATA_REPLICATION_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txbti_tx_idle_data_en_attr == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcal_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcal_tclkduty_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalduty_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalduty_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTY_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalduty_sel_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutybg_abort_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutybg_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutybg_ready_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutycomp_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutycomp_offset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_finish_side_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_init_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_initval_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_invert_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_req_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_round_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_runcount_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsm_signmagen_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsmout_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompfsmout_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompmeas_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompmeas_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompmeas_req_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompmeasout_ack_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPMEASOUT_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompmeasout_erravg_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPMEASOUT_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutycompmeasout_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYCOMPMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_bg_en_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_bg_one_step_cal_en_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_finish_side_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_init_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_invert_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_req_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_round_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_runcount_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutyfsm_signmagen_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeas_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeas_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeas_req_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeasout_ack_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYMEASOUT_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeasout_erravg_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYMEASOUT_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutymeasout_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutystat_done_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaldutystat_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALDUTYSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalptr_pstate_duty_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalptr_pstate_dutycomp_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalptr_pstate_regopampoffset_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_duty_muxd0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_duty_muxd1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_duty_muxd2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_duty_muxd3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_duty_muxd4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_dutycomp_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_dutycomp_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_dutycomp_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_dutycomp_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_dutycomp_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_regopampoffset_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalptr_quad_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffset_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_finish_side_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_round_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_runcount_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsm_signmagen_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcaltclkdutyforce_div1_attr == SERDES_IP_LANE_L2_CFG_TXCALTCLKDUTYFORCE_DIV1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txcdrdiv_local_en_attr == SERDES_IP_LANE_L2_CFG_TXCDRDIV_LOCAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txclk_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L2_CFG_TXCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txclk_locovren_attr == SERDES_IP_LANE_L2_CFG_TXCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txclkgenmuxsel_txinternal_attr == SERDES_IP_LANE_L2_CFG_TXCLKGENMUXSEL_TXINTERNAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txdetectrx_thr_attr == 5'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeas_count_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeas_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXDETECTRXMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeas_locovren_attr == SERDES_IP_LANE_L2_CFG_TXDETECTRXMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeas_validdlycount_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeasin_locovren_attr == SERDES_IP_LANE_L2_CFG_TXDETECTRXMEASIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeasin_start_locovr_attr == SERDES_IP_LANE_L2_CFG_TXDETECTRXMEASIN_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeaspcs_locovren_attr == SERDES_IP_LANE_L2_CFG_TXDETECTRXMEASPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeaspcs_req_locovr_attr == SERDES_IP_LANE_L2_CFG_TXDETECTRXMEASPCS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeasval_locovren_attr == SERDES_IP_LANE_L2_CFG_TXDETECTRXMEASVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txdetectrxmeasval_stat_locovr_attr == SERDES_IP_LANE_L2_CFG_TXDETECTRXMEASVAL_STAT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txdetrx_levn_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txdetrx_levnm1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txdetrx_levnp1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txdetrx_levnp2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txdrv_hizen_locovr_attr == SERDES_IP_LANE_L2_CFG_TXDRV_HIZEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txdrv_levn_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txdrv_levnm1_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txdrv_levnp1_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txdrv_levnp2_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txdrv_locovren_attr == SERDES_IP_LANE_L2_CFG_TXDRV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txdrv_refcken_attr == SERDES_IP_LANE_L2_CFG_TXDRV_REFCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txdrv_termref_attr == SERDES_IP_LANE_L2_CFG_TXDRV_TERMREF_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txdrvmute_locovr_attr == SERDES_IP_LANE_L2_CFG_TXDRVMUTE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txdrvmute_locovren_attr == SERDES_IP_LANE_L2_CFG_TXDRVMUTE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txduty_ctrl_disable_attr == SERDES_IP_LANE_L2_CFG_TXDUTY_CTRL_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txduty_pad_sense_en_attr == SERDES_IP_LANE_L2_CFG_TXDUTY_PAD_SENSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txdutycal_div16_en_attr == SERDES_IP_LANE_L2_CFG_TXDUTYCAL_DIV16_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txdutycal_div1_en_attr == SERDES_IP_LANE_L2_CFG_TXDUTYCAL_DIV1_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txdutycal_div2_en_attr == SERDES_IP_LANE_L2_CFG_TXDUTYCAL_DIV2_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txdutycal_div4_en_attr == SERDES_IP_LANE_L2_CFG_TXDUTYCAL_DIV4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txdutycal_div8_en_attr == SERDES_IP_LANE_L2_CFG_TXDUTYCAL_DIV8_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txfifo_elecidle_deskew_en_attr == SERDES_IP_LANE_L2_CFG_TXFIFO_ELECIDLE_DESKEW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txfifo_force_txidlebit1_zero_disable_attr == SERDES_IP_LANE_L2_CFG_TXFIFO_FORCE_TXIDLEBIT1_ZERO_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txfifo_kill_dly_10b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txfifo_kill_dly_16b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txfifo_kill_dly_20b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txfifo_kill_dly_32b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txfifo_kill_dly_40b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txfifo_kill_dly_64b_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txfifo_kill_dly_80b_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txfifo_kill_dly_8b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txfifo_kill_en_attr == SERDES_IP_LANE_L2_CFG_TXFIFO_KILL_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txfsm_cken_ovr_attr == SERDES_IP_LANE_L2_CFG_TXFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txfsm_cken_ovren_attr == SERDES_IP_LANE_L2_CFG_TXFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txfsm_main_on_state_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txl1d1_doze_ctrl_attr == SERDES_IP_LANE_L2_CFG_TXL1D1_DOZE_CTRL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txl1d1_txbias_ctrl_attr == SERDES_IP_LANE_L2_CFG_TXL1D1_TXBIAS_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txlanepam_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXLANEPAM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txlanepam_locovren_attr == SERDES_IP_LANE_L2_CFG_TXLANEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txmeaslatovrhd_meas_sel_attr == SERDES_IP_LANE_L2_CFG_TXMEASLATOVRHD_MEAS_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txmute_delay_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txntl_changeref_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txntl_changeref_val_locovr_attr == SERDES_IP_LANE_L2_CFG_TXNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txntl_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txntl_en_attr == SERDES_IP_LANE_L2_CFG_TXNTL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txntl_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txntl_locovren_attr == SERDES_IP_LANE_L2_CFG_TXNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txntl_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txntl_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txntl_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txntl_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txntl_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txntl_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txntl_txm_charge_up_locovr_attr == SERDES_IP_LANE_L2_CFG_TXNTL_TXM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txntl_txm_pull_dn_locovr_attr == SERDES_IP_LANE_L2_CFG_TXNTL_TXM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txntl_txm_sense_locovr_attr == SERDES_IP_LANE_L2_CFG_TXNTL_TXM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txntl_txp_charge_up_locovr_attr == SERDES_IP_LANE_L2_CFG_TXNTL_TXP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txntl_txp_pull_dn_locovr_attr == SERDES_IP_LANE_L2_CFG_TXNTL_TXP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txntl_txp_sense_locovr_attr == SERDES_IP_LANE_L2_CFG_TXNTL_TXP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txp2s_txwordsyncbypen_attr == SERDES_IP_LANE_L2_CFG_TXP2S_TXWORDSYNCBYPEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txpam_bitorder_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txpam_gray_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXPAM_GRAY_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txpam_locovren_attr == SERDES_IP_LANE_L2_CFG_TXPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txpam_precode_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXPAM_PRECODE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txpcs_locovren_attr == SERDES_IP_LANE_L2_CFG_TXPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txpcs_txenable_locovr_attr == SERDES_IP_LANE_L2_CFG_TXPCS_TXENABLE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txpcsbist_en_locovr_attr == SERDES_IP_LANE_L2_CFG_TXPCSBIST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txpcsbist_locovren_attr == SERDES_IP_LANE_L2_CFG_TXPCSBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txratewidth_clk_chk_disable_attr == SERDES_IP_LANE_L2_CFG_TXRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txratewidth_etr_on_delay_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txratewidth_locovren_attr == SERDES_IP_LANE_L2_CFG_TXRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txreg_toggle_pwrupacc_on_rate_change_en_attr == SERDES_IP_LANE_L2_CFG_TXREG_TOGGLE_PWRUPACC_ON_RATE_CHANGE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txreg_toggle_reset_on_rate_change_en_attr == SERDES_IP_LANE_L2_CFG_TXREG_TOGGLE_RESET_ON_RATE_CHANGE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txresetdel_sel_attr == SERDES_IP_LANE_L2_CFG_TXRESETDEL_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_en_b_attr == SERDES_IP_LANE_L2_CFG_TXRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s0q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s0q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s1q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s1q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s2q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s2q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s2q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s2q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s2q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s2q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s2q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s3q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s3q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s3q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s3q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s3q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s3q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s3q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s3q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s4q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s4q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evdn_delay_lut_sel_s5q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_entry2_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s0q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s0q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s1q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s1q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s1q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s1q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s1q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s1q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s2q0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s2q1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s2q2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s2q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s2q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s2q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s2q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s2q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s3q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s3q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s3q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s3q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s3q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s3q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s3q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s3q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s4q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s4q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpu_evup_delay_lut_sel_s5q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_duty_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_bitckdvdrcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_dn_ptr0_s_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_up_ptr0_s_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_drvdoze_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_p2s_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpurst_pma2pcstxword_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpurst_regreset_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrpurst_txdetectrx_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_aetrtx_bitckdvdrcken_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_AETRTX_BITCKDVDRCKEN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_aetrtx_bitckdvdrcken_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_AETRTX_BITCKDVDRCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_aetrtx_regpwrupacc_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_AETRTX_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_aetrtx_regpwrupacc_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_AETRTX_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_adc_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_adc_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_drvdoze_b_ovr_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_DRVDOZE_B_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_drvdoze_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_DRVDOZE_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_duty_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_DUTY_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_duty_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_DUTY_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_ntl_b_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_ntl_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_p2s_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_P2S_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_p2s_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_P2S_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_reg_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_apdtx_reg_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_APDTX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_arsttx_adc_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_ARSTTX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_arsttx_adc_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_ARSTTX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_arsttx_pma2pcstxword_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_ARSTTX_PMA2PCSTXWORD_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_arsttx_pma2pcstxword_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_ARSTTX_PMA2PCSTXWORD_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_arsttx_regreset_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_ARSTTX_REGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_arsttx_regreset_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_ARSTTX_REGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_arsttx_txdetectrx_ovr_b_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_ARSTTX_TXDETECTRX_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrstpdovr_arsttx_txdetectrx_ovren_attr == SERDES_IP_LANE_L2_CFG_TXRSTPDOVR_ARSTTX_TXDETECTRX_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txrststate_hiz_en_attr == SERDES_IP_LANE_L2_CFG_TXRSTSTATE_HIZ_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txspare0_attr == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txspare_attr == 10'd384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txterm_coarse_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txtermtrim_locovren_attr == SERDES_IP_LANE_L2_CFG_TXTERMTRIM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txtermtrim_nmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txtermtrim_pmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txwclk_div_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txwclk_div_en_attr == SERDES_IP_LANE_L2_CFG_TXWCLK_DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txwclk_div_smpl_attr == SERDES_IP_LANE_L2_CFG_TXWCLK_DIV_SMPL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txwptr_init01_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txwptr_init02_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txwptr_init04_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txwptr_init08_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txwptr_init16_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txwptr_init32_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l2_cfg_txwptr_init_rx2txparlb_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_bshihyst_attr == SERDES_IP_LANE_L3_CFG_BSHIHYST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_bstxdrv_levn_attr == 6'd53
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_bstxdrv_levnm1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_bstxdrv_levnp1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_bstxdrv_levnp2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_calsqlchosc_locovren_attr == SERDES_IP_LANE_L3_CFG_CALSQLCHOSC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_calsqlchosc_trimcode_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_cdrclkstat_locovren_attr == SERDES_IP_LANE_L3_CFG_CDRCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_cdrclkstat_ready_locovr_attr == SERDES_IP_LANE_L3_CFG_CDRCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_etrregrxcdrclk_ready_attr == SERDES_IP_LANE_L3_CFG_ETRREGRXCDRCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_laneckm_avg_en_attr == SERDES_IP_LANE_L3_CFG_LANECKM_AVG_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_laneckm_clk_en_attr == SERDES_IP_LANE_L3_CFG_LANECKM_CLK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_laneckm_continuous_attr == SERDES_IP_LANE_L3_CFG_LANECKM_CONTINUOUS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_laneckm_dig_meas_en_attr == SERDES_IP_LANE_L3_CFG_LANECKM_DIG_MEAS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_laneckm_dig_meas_err_clr_attr == SERDES_IP_LANE_L3_CFG_LANECKM_DIG_MEAS_ERR_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_laneckm_en_attr == SERDES_IP_LANE_L3_CFG_LANECKM_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_laneckm_max_thr_attr == 25'd33554431
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_laneckm_meas_ck_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_laneckm_ref_ck_div_ratio_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_laneckm_result_clr_attr == SERDES_IP_LANE_L3_CFG_LANECKM_RESULT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_laneckm_start_attr == SERDES_IP_LANE_L3_CFG_LANECKM_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_laneckm_wdt_interval_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_laneckm_win_thr_ref_attr == 25'd16777215
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_lanepcs_locovren_attr == SERDES_IP_LANE_L3_CFG_LANEPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_lanepcs_mode_locovr_attr == SERDES_IP_LANE_L3_CFG_LANEPCS_MODE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_laneperfmon_compare_val_start_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_laneperfmon_compare_val_stop_attr == 8'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_laneperfmon_en_attr == SERDES_IP_LANE_L3_CFG_LANEPERFMON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_laneperfmon_mask_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_lanepmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_lanepmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_lanepmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_lanepmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_lanepmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_lanepmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_lb_cdrclk2txen_locovr_attr == SERDES_IP_LANE_L3_CFG_LB_CDRCLK2TXEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_lb_cdrclkdiven_attr == SERDES_IP_LANE_L3_CFG_LB_CDRCLKDIVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_lb_cdrdivclk2exten_attr == SERDES_IP_LANE_L3_CFG_LB_CDRDIVCLK2EXTEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_lb_cdrdivclk2txen_attr == SERDES_IP_LANE_L3_CFG_LB_CDRDIVCLK2TXEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_lb_hsclk2cdrdiven_attr == SERDES_IP_LANE_L3_CFG_LB_HSCLK2CDRDIVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_lb_locovren_attr == SERDES_IP_LANE_L3_CFG_LB_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_lb_parrx2txtimeden_locovr_attr == SERDES_IP_LANE_L3_CFG_LB_PARRX2TXTIMEDEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_lb_pllfbclk2cdrrefclken_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_lb_pllfbclk2cdrrefclken_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_lb_pllfbclk2cdrrefclken_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_lb_pllfbclk2cdrrefclken_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_lb_pllfbclk2cdrrefclken_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_lb_rx2txuntimeden_attr == SERDES_IP_LANE_L3_CFG_LB_RX2TXUNTIMEDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_lb_rxwordck2pcstxwordcken_attr == SERDES_IP_LANE_L3_CFG_LB_RXWORDCK2PCSTXWORDCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_lb_tx2rxbuftimeden_lsb_locovr_attr == SERDES_IP_LANE_L3_CFG_LB_TX2RXBUFTIMEDEN_LSB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_lb_tx2rxbuftimeden_msb_locovr_attr == SERDES_IP_LANE_L3_CFG_LB_TX2RXBUFTIMEDEN_MSB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_lb_tx2rxiotimeden_attr == SERDES_IP_LANE_L3_CFG_LB_TX2RXIOTIMEDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_lfps_det_locovr_attr == SERDES_IP_LANE_L3_CFG_LFPS_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_lfps_locovren_attr == SERDES_IP_LANE_L3_CFG_LFPS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_lfps_out_en_attr == SERDES_IP_LANE_L3_CFG_LFPS_OUT_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_pcslfps_en_locovr_attr == SERDES_IP_LANE_L3_CFG_PCSLFPS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_pcslfps_locovren_attr == SERDES_IP_LANE_L3_CFG_PCSLFPS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_pcsrx_dme_en_locovr_attr == SERDES_IP_LANE_L3_CFG_PCSRX_DME_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_pcsrx_locovren_attr == SERDES_IP_LANE_L3_CFG_PCSRX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_pcsrxbist_locovren_attr == SERDES_IP_LANE_L3_CFG_PCSRXBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_pcsrxbist_modesel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_pcstx_beaconen_locovr_attr == SERDES_IP_LANE_L3_CFG_PCSTX_BEACONEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_pcstx_locovren_attr == SERDES_IP_LANE_L3_CFG_PCSTX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_polarity_rx_attr == SERDES_IP_LANE_L3_CFG_POLARITY_RX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_polarity_tx_attr == SERDES_IP_LANE_L3_CFG_POLARITY_TX_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rx_cmn_on_state_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rx_fastregpwrup_en_attr == SERDES_IP_LANE_L3_CFG_RX_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rx_frac_mode_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rx_on_state_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rx_pg_disable_attr == SERDES_IP_LANE_L3_CFG_RX_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rx_synth_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rx_synth_sel_amode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rx_synth_sel_bmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rx_synth_sel_cmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rx_synth_sel_dmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rx_synth_sel_emode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxadc_req_attr == SERDES_IP_LANE_L3_CFG_RXADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxagc_dccoupleen_attr == SERDES_IP_LANE_L3_CFG_RXAGC_DCCOUPLEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxaprobe_addr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxaprobe_lastmux_isolate_attr == SERDES_IP_LANE_L3_CFG_RXAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxaprobeadc_current_direction_attr == SERDES_IP_LANE_L3_CFG_RXAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxaprobeadc_resistor_enable_attr == SERDES_IP_LANE_L3_CFG_RXAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxbias_iccadj_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxbias_icvadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxbias_locovren_attr == SERDES_IP_LANE_L3_CFG_RXBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxbias_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxbist_burst_four_errtype_attr == SERDES_IP_LANE_L3_CFG_RXBIST_BURST_FOUR_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxbist_burst_one_errtype_attr == SERDES_IP_LANE_L3_CFG_RXBIST_BURST_ONE_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxbist_burst_three_errtype_attr == SERDES_IP_LANE_L3_CFG_RXBIST_BURST_THREE_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxbist_burst_two_errtype_attr == SERDES_IP_LANE_L3_CFG_RXBIST_BURST_TWO_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxbist_cdrlock2data_bypass_attr == SERDES_IP_LANE_L3_CFG_RXBIST_CDRLOCK2DATA_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxbist_cdrlock2data_postamble_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxbist_clear_errcount_attr == SERDES_IP_LANE_L3_CFG_RXBIST_CLEAR_ERRCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxbist_err_en_attr == SERDES_IP_LANE_L3_CFG_RXBIST_ERR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxbist_err_trig_type_attr == SERDES_IP_LANE_L3_CFG_RXBIST_ERR_TRIG_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxbist_errmask_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxbist_errtype_attr == SERDES_IP_LANE_L3_CFG_RXBIST_ERRTYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxbist_firsterr_type_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxbist_lockchk_count_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxbist_maxbitcnt_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxbist_mostrecent_err_attr == SERDES_IP_LANE_L3_CFG_RXBIST_MOSTRECENT_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxbist_relock_itercount_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxbist_seed_attr == 31'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxbist_status_hold_attr == SERDES_IP_LANE_L3_CFG_RXBIST_STATUS_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxbitslip_locovr_attr == SERDES_IP_LANE_L3_CFG_RXBITSLIP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxbitslip_locovren_attr == SERDES_IP_LANE_L3_CFG_RXBITSLIP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxbscan_vref_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxbshicm_attr == SERDES_IP_LANE_L3_CFG_RXBSHICM_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalcdrfbdiv_div2_bypass_muxd0_attr == SERDES_IP_LANE_L3_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalcdrfbdiv_div2_bypass_muxd1_attr == SERDES_IP_LANE_L3_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalcdrfbdiv_div2_bypass_muxd2_attr == SERDES_IP_LANE_L3_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalcdrfbdiv_div2_bypass_muxd3_attr == SERDES_IP_LANE_L3_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalcdrfbdiv_div2_bypass_muxd4_attr == SERDES_IP_LANE_L3_CFG_RXCALCDRFBDIV_DIV2_BYPASS_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalduty_iclk_gray_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalduty_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTY_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalduty_qclk_gray_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalduty_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutybg_abort_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutybg_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutybg_ready_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycomp_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycomp_offset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_finish_side_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_init_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_initval_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_invert_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_round_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_runcount_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsm_signmagen_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsmout_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompfsmout_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCOMPFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutycompmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_disable_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCTRL_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_i_div1_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_i_div2_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_i_div4_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_i_div8_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_q_div1_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_q_div2_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_q_div4_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyctrl_q_div8_bin_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_bg_en_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_bg_one_step_cal_en_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_finish_side_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_i_polarity_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_I_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_i_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_I_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_init_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_q_polarity_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_Q_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_q_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_Q_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_round_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_runcount_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutyfsm_signmagen_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_comp_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEAS_COMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_comp_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEAS_COMP_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_i_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEAS_I_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_i_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEAS_I_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_q_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEAS_Q_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_q_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEAS_Q_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeasout_comp_ack_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEASOUT_COMP_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeasout_comp_erravg_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEASOUT_COMP_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeasout_i_ack_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEASOUT_I_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeasout_i_erravg_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEASOUT_I_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeasout_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeasout_q_ack_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEASOUT_Q_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutymeasout_q_erravg_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYMEASOUT_Q_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutystat_done_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaldutystat_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALDUTYSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_centerfreq_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_end_delay_attr == 9'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_hscount_muxd0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_hscount_muxd1_attr == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_hscount_muxd2_attr == 8'd180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_hscount_muxd3_attr == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_hscount_muxd4_attr == 8'd206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_initval_centerfreq_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_initval_fosc_attr == 8'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfosc_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_centerfreq_finish_side_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_CENTERFREQ_FINISH_SIDE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_centerfreq_to_fosc_offset_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_centerfreqen_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_CENTERFREQEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_centerfreqoffset_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_fosc_finishside_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_FOSC_FINISHSIDE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_foscen_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_FOSCEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_foscoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_init_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_invert_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_lpfax_calfosccoarse_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_lpfax_calfoscfine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_lpfax_centerfreqcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_lpfax_centerfreqfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_runcount_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_signmagen_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsm_vcorepen_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSM_VCOREPEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsmout_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscfsmout_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_count_muxd0_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_count_muxd1_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_count_muxd2_attr == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_count_muxd3_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_count_muxd4_attr == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_dlycount_attr == 9'd68
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeasout_clear_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCMEASOUT_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeasout_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscmeasout_start_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCMEASOUT_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscval_int_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalfoscval_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALFOSCVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalintsval_int_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalintsval_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALINTSVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaloffsetfsm_init_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaloffsetfsm_init_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaloffsetfsm_init_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALOFFSETFSM_INIT_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaloffsetfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcaloffsetfsmout_input_en_attr == SERDES_IP_LANE_L3_CFG_RXCALOFFSETFSMOUT_INPUT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_duty_i_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_duty_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_dutycomp_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_foscfsm_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_offsetfsm_init_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_regopampoffset_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_rxppm_lockstatus_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_sqlch_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_sqlchosc_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_synthppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_pstate_voscregopampoffset_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_duty_i_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_duty_q_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_dutycomp_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_foscfsm_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_offsetfsm_init_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_rxppm_lockstatus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_sqlch_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_sqlchosc_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_synthppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalptr_quad_voscregopampoffset_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffset_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_finish_side_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_round_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_runcount_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsm_signmagen_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchfsm_clear_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHFSM_CLEAR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchfsm_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchfsmout_caldone_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHFSMOUT_CALDONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchfsmout_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_codeoffset_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_finish_side_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHOSCFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_init_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHOSCFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_initval_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_invert_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHOSCFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHOSCFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHOSCFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_round_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHOSCFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscfsm_runcount_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHOSCFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscmeas_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHOSCMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscmeas_ref_cnt_attr == 10'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscmeas_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALSQLCHOSCMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscmeas_settle_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalsqlchoscmeas_smpl_cnt_attr == 10'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvbiascap_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALVBIASCAP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvbiascap_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALVBIASCAP_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvcoopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvcoopampoffsetmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvcoopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvcoopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffset_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffset_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_codeoffset_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_finish_side_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_initval_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_invert_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_lpfaxcoarse_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_round_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_runcount_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETFSM_RUNCOUNT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsm_signmagen_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsmout_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetfsmout_runcount_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETFSMOUT_RUNCOUNT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetmeas_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvcorepoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALVCOREPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffset_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALVOSCREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALVOSCREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L3_CFG_RXCALVOSCREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALVOSCREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALVOSCREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALVOSCREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALVOSCREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCALVOSCREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcalvoscregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCALVOSCREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrdiv_local_en_attr == SERDES_IP_LANE_L3_CFG_RXCDRDIV_LOCAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdiv_moddiv_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdiv_moddiv_muxd1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdiv_moddiv_muxd2_attr == 4'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdiv_moddiv_muxd3_attr == 4'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdiv_moddiv_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdivslip_mdiv_muxd0_attr == 9'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdivslip_mdiv_muxd1_attr == 9'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdivslip_mdiv_muxd2_attr == 9'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdivslip_mdiv_muxd3_attr == 9'd66
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrfbdivslip_mdiv_muxd4_attr == 9'd210
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrpfd_forcedn_attr == SERDES_IP_LANE_L3_CFG_RXCDRPFD_FORCEDN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrpfd_forceen_attr == SERDES_IP_LANE_L3_CFG_RXCDRPFD_FORCEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrpfd_forceup_attr == SERDES_IP_LANE_L3_CFG_RXCDRPFD_FORCEUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrpfd_propgain_attr == SERDES_IP_LANE_L3_CFG_RXCDRPFD_PROPGAIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrpfd_pulsewidth_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrphd_asym_override_ignore_attr == SERDES_IP_LANE_L3_CFG_RXCDRPHD_ASYM_OVERRIDE_IGNORE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrphd_bitshift_en_attr == SERDES_IP_LANE_L3_CFG_RXCDRPHD_BITSHIFT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrphd_forcedn_attr == SERDES_IP_LANE_L3_CFG_RXCDRPHD_FORCEDN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrphd_forceen_attr == SERDES_IP_LANE_L3_CFG_RXCDRPHD_FORCEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrphd_forceup_attr == SERDES_IP_LANE_L3_CFG_RXCDRPHD_FORCEUP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrphdrate_doublerate2s2p_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCDRPHDRATE_DOUBLERATE2S2P_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrphdrate_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCDRPHDRATE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrrefck_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrrefck_refdiv_muxd1_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrrefck_refdiv_muxd2_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrrefck_refdiv_muxd3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrrefck_refdiv_muxd4_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_biastop_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_biastopbypass_attr == SERDES_IP_LANE_L3_CFG_RXCDRVCO_BIASTOPBYPASS_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_datapropgain_high_attr == 5'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_datapropgain_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_datapropgain_low_attr == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_ff_ovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_ff_ovr_en_attr == SERDES_IP_LANE_L3_CFG_RXCDRVCO_FF_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_fil_short_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_flickerdegen_attr == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_gmfoscshort_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCDRVCO_GMFOSCSHORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_intf_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_intf_fil_short_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_intrj_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCDRVCO_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_refpropgain_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxcdrvco_refpropgain_nom_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxclk_cdrfb_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCLK_CDRFB_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxclk_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L3_CFG_RXCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxclk_locovren_attr == SERDES_IP_LANE_L3_CFG_RXCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdat_nrz_64b80b_bcword_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdata_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXDATA_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdata_locovren_attr == SERDES_IP_LANE_L3_CFG_RXDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdatapath_locovren_attr == SERDES_IP_LANE_L3_CFG_RXDATAPATH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdatapath_on_state_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdatapath_ready_locovr_attr == SERDES_IP_LANE_L3_CFG_RXDATAPATH_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdfe_datatap_vcasc_attr == 4'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdfe_dfebiasadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdfe_nbiasctle_en_attr == SERDES_IP_LANE_L3_CFG_RXDFE_NBIASCTLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdfe_vcasc_sel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdfeterm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXDFETERM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdfeterm_termcal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdfeyadjdac_datamid_edge_coarse_en_attr == SERDES_IP_LANE_L3_CFG_RXDFEYADJDAC_DATAMID_EDGE_COARSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdfeyadjdac_datatopbot_aux_coarse_en_attr == SERDES_IP_LANE_L3_CFG_RXDFEYADJDAC_DATATOPBOT_AUX_COARSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_accum_mon_en_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_ACCUM_MON_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_accum_mon_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_bypasscdrpdetupdnsmpl_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_bypassenfosc_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_BYPASSENFOSC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_bypassenints_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_BYPASSENINTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_bypassenupdnsmpl_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_BYPASSENUPDNSMPL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_bypassfosc_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_bypasspllpfdupdnsmpl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_bypassrxints_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_data2pll_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_deltasigmode_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_DELTASIGMODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_fastref_muxd0_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_FASTREF_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_fastref_muxd1_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_FASTREF_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_fastref_muxd2_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_FASTREF_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_fastref_muxd3_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_FASTREF_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_fastref_muxd4_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_FASTREF_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_fosc_mod_bypass_en_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_FOSC_MOD_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_fosc_sample_pedge_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_FOSC_SAMPLE_PEDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gain_step_on_lock_recovery_en_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_GAIN_STEP_ON_LOCK_RECOVERY_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gaindelaycount_init_attr == 9'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gaindelaycount_pow2_muxd0_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gaindelaycount_pow2_muxd1_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gaindelaycount_pow2_muxd2_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gaindelaycount_pow2_muxd3_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gaindelaycount_pow2_muxd4_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_10b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_16b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_20b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_32b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_40b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_64b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_80b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd0_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd1_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd2_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd3_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2dat_8b_pow2_muxd4_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2ref_pow2_muxd0_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2ref_pow2_muxd1_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2ref_pow2_muxd2_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2ref_pow2_muxd3_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainlocked2ref_pow2_muxd4_attr == 6'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainunlocked_pow2_muxd0_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainunlocked_pow2_muxd1_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainunlocked_pow2_muxd2_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainunlocked_pow2_muxd3_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_gainunlocked_pow2_muxd4_attr == 6'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_initintegrator_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_INITINTEGRATOR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_initmodulator_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_INITMODULATOR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_deltasig_mode_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_INTS_DELTASIG_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_freeze_en_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_INTS_FREEZE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gaindelaycount_pow2_muxd0_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gaindelaycount_pow2_muxd1_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gaindelaycount_pow2_muxd2_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gaindelaycount_pow2_muxd3_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gaindelaycount_pow2_muxd4_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd0_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd1_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd2_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd3_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2dat_pow2_muxd4_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd0_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd1_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd2_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd3_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainlocked2ref_pow2_muxd4_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainunlocked_pow2_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainunlocked_pow2_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainunlocked_pow2_muxd2_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainunlocked_pow2_muxd3_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_gainunlocked_pow2_muxd4_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_guardband_hi_attr == 8'd200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_guardband_lo_attr == 8'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_loop_sel_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_INTS_LOOP_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_mod_bypass_en_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_INTS_MOD_BYPASS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_mod_load_pedge_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_INTS_MOD_LOAD_PEDGE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_ints_step_to_integer_en_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_INTS_STEP_TO_INTEGER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_jit_length_attr == 18'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_jit_mode_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_JIT_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_modck_ctrl_en_attr == SERDES_IP_LANE_L3_CFG_RXDPIF_MODCK_CTRL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_pll2data_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_restore_cntr_attr == 9'd258
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_store_cntr_attr == 16'd258
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpif_trnsfrdelay_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpiffreeze_inten_attr == SERDES_IP_LANE_L3_CFG_RXDPIFFREEZE_INTEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdpiffreeze_moden_attr == SERDES_IP_LANE_L3_CFG_RXDPIFFREEZE_MODEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxdutyselpolarity_attr == SERDES_IP_LANE_L3_CFG_RXDUTYSELPOLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxflxgate_force_rxeq_gate_locovr_attr == SERDES_IP_LANE_L3_CFG_RXFLXGATE_FORCE_RXEQ_GATE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxflxgate_locovren_attr == SERDES_IP_LANE_L3_CFG_RXFLXGATE_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxfoscstat_done_locovr_attr == SERDES_IP_LANE_L3_CFG_RXFOSCSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxfoscstat_locovren_attr == SERDES_IP_LANE_L3_CFG_RXFOSCSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxfsm_cken_ovr_attr == SERDES_IP_LANE_L3_CFG_RXFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxfsm_cken_ovren_attr == SERDES_IP_LANE_L3_CFG_RXFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxints_prev_votes_hold_en_attr == SERDES_IP_LANE_L3_CFG_RXINTS_PREV_VOTES_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxlanepam_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXLANEPAM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxlanepam_locovren_attr == SERDES_IP_LANE_L3_CFG_RXLANEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxlock2datatmr_attr == 8'd240
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxlock2datatmr_short_attr == 8'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxntl_changeref_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxntl_changeref_val_locovr_attr == SERDES_IP_LANE_L3_CFG_RXNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxntl_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxntl_en_attr == SERDES_IP_LANE_L3_CFG_RXNTL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxntl_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxntl_locovren_attr == SERDES_IP_LANE_L3_CFG_RXNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxntl_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxntl_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxntl_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxntl_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxntl_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxntl_rxm_charge_up_locovr_attr == SERDES_IP_LANE_L3_CFG_RXNTL_RXM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxntl_rxm_pull_dn_locovr_attr == SERDES_IP_LANE_L3_CFG_RXNTL_RXM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxntl_rxm_sense_locovr_attr == SERDES_IP_LANE_L3_CFG_RXNTL_RXM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxntl_rxp_charge_up_locovr_attr == SERDES_IP_LANE_L3_CFG_RXNTL_RXP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxntl_rxp_pull_dn_locovr_attr == SERDES_IP_LANE_L3_CFG_RXNTL_RXP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxntl_rxp_sense_locovr_attr == SERDES_IP_LANE_L3_CFG_RXNTL_RXP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxntl_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_acc_freeze_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_ACC_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_cdrlock2data_gater_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_cdrlock2data_gater_hold_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_cdrlock2data_gater_ovrd_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_CDRLOCK2DATA_GATER_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_cdrlock2datatmr_optcl_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_cdrlock2datatmr_optcl_sel_ovrd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_enter_lock2data_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_ENTER_LOCK2DATA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_enter_lock2data_hold_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_ENTER_LOCK2DATA_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_exit_lock2data_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_EXIT_LOCK2DATA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_exit_lock2data_hold_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_EXIT_LOCK2DATA_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_force_lock2data_ovrd_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_FORCE_LOCK2DATA_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_force_lock2ref_ovrd_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_FORCE_LOCK2REF_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_hold_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_hold_timer_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_intf_ovrd_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_INTF_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_intf_ovrd_type_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_INTF_OVRD_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_mod_freeze_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_MOD_FREEZE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_ovrd_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_OVRD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_ppm_detect_freeze_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_PPM_DETECT_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_ppm_detect_freeze_ovrd_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_PPM_DETECT_FREEZE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_ppm_detect_hold_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_PPM_DETECT_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_prop_freeze_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_PROP_FREEZE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_prop_freeze_ovrd_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_PROP_FREEZE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_rxdata_en_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_RXDATA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxoptclfastlock_skip_init_lock2data_attr == SERDES_IP_LANE_L3_CFG_RXOPTCLFASTLOCK_SKIP_INIT_LOCK2DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxpam_bitorder_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxpam_gray_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXPAM_GRAY_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxpam_locovren_attr == SERDES_IP_LANE_L3_CFG_RXPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxpam_precode_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXPAM_PRECODE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_p5_muxd0_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIV_P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_p5_muxd1_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIV_P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_p5_muxd2_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIV_P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_p5_muxd3_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIV_P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdiv_p5_muxd4_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIV_P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdivclken_muxd0_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIVCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdivclken_muxd1_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIVCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdivclken_muxd2_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIVCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdivclken_muxd3_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIVCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxpcs_postdivclken_muxd4_attr == SERDES_IP_LANE_L3_CFG_RXPCS_POSTDIVCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxpcsbist_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXPCSBIST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxpcsbist_locovren_attr == SERDES_IP_LANE_L3_CFG_RXPCSBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxphd_gain_hold_en_attr == SERDES_IP_LANE_L3_CFG_RXPHD_GAIN_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxphd_gain_zero_locovr_attr == SERDES_IP_LANE_L3_CFG_RXPHD_GAIN_ZERO_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxphd_locovren_attr == SERDES_IP_LANE_L3_CFG_RXPHD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxphd_majvote_basegain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxphd_majvote_en_attr == SERDES_IP_LANE_L3_CFG_RXPHD_MAJVOTE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxphd_mute_cntr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxphd_nrz8b10b_pam16b20b_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxphd_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxphd_pam_transition_sel_attr == SERDES_IP_LANE_L3_CFG_RXPHD_PAM_TRANSITION_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxphd_sign_invert_attr == SERDES_IP_LANE_L3_CFG_RXPHD_SIGN_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxpostdiv_wait_for_lock_disable_attr == SERDES_IP_LANE_L3_CFG_RXPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxppm_freq_max_offset_h_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxppm_freq_max_offset_l_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxppm_freq_ref_cnt_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxppm_lockstatus_locovr_attr == SERDES_IP_LANE_L3_CFG_RXPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxppm_lockstatus_synthlcfast_en_attr == SERDES_IP_LANE_L3_CFG_RXPPM_LOCKSTATUS_SYNTHLCFAST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxppm_lockstatus_synthlcmed_en_attr == SERDES_IP_LANE_L3_CFG_RXPPM_LOCKSTATUS_SYNTHLCMED_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxppm_lockstatus_synthlcslow_en_attr == SERDES_IP_LANE_L3_CFG_RXPPM_LOCKSTATUS_SYNTHLCSLOW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxppm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxppm_ppmdriftcount_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxppm_ppmdriftmax_attr == 16'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxppm_status_hold_attr == SERDES_IP_LANE_L3_CFG_RXPPM_STATUS_HOLD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxppm_unlock_clear_attr == SERDES_IP_LANE_L3_CFG_RXPPM_UNLOCK_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_fast_muxd0_attr == 16'd666
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_fast_muxd1_attr == 16'd4000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_fast_muxd2_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_fast_muxd3_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_fast_muxd4_attr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_muxd0_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_muxd1_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_muxd2_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_muxd3_attr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxppm_watchdogtmr_muxd4_attr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxppmctrl_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXPPMCTRL_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxppmctrl_locovren_attr == SERDES_IP_LANE_L3_CFG_RXPPMCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxppmlockstat_locovren_attr == SERDES_IP_LANE_L3_CFG_RXPPMLOCKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxppmlockstat_sticky_locovr_attr == SERDES_IP_LANE_L3_CFG_RXPPMLOCKSTAT_STICKY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxppmtmr_locovren_attr == SERDES_IP_LANE_L3_CFG_RXPPMTMR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxppmtmr_watchdogtmr_sel_locovr_attr == SERDES_IP_LANE_L3_CFG_RXPPMTMR_WATCHDOGTMR_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_cal_clear_delay_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_clk_chk_disable_attr == SERDES_IP_LANE_L3_CFG_RXRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_clk_delay_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_etr_on_delay_attr == 12'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_locovren_attr == SERDES_IP_LANE_L3_CFG_RXRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxreg_lev_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxreg_toggle_reset_on_rate_change_en_attr == SERDES_IP_LANE_L3_CFG_RXREG_TOGGLE_RESET_ON_RATE_CHANGE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxreg_vreg_bypass_attr == SERDES_IP_LANE_L3_CFG_RXREG_VREG_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_en_b_attr == SERDES_IP_LANE_L3_CFG_RXRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s0q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s0q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s2q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s2q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s2q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s2q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s2q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s2q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s2q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s3q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s3q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s3q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s3q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s3q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s3q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s3q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s3q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s4q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s4q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evdn_delay_lut_sel_s5q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_entry2_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_entry4_attr == 13'd78
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_entry5_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_entry6_attr == 13'd1406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s0q2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s0q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s1q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s1q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s1q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s1q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s1q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s1q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s2q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s2q2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s2q3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s2q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s2q5_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s2q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s2q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s3q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s3q1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s3q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s3q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s3q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s3q5_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s3q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s3q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s4q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s4q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpu_evup_delay_lut_sel_s5q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_duty_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_fosc_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cal_sqlch_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_cdrfb_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrfbdivcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_cdrmoddivcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpuetr_termhiz_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_auxcomp_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_datfbdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_dfe_yadj_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_hifreqagc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_sqlch_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpupd_vco_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_cdrfbdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_dpif_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pdet_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_pfd_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_ppm_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pa_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_dn_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_dn_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_up_ptr0_s_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrpurst_s2pb_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_aetrrx_cdrfbdivcken_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_AETRRX_CDRFBDIVCKEN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_aetrrx_cdrfbdivcken_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_AETRRX_CDRFBDIVCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_aetrrx_cdrmoddivcken_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_AETRRX_CDRMODDIVCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_aetrrx_cdrmoddivcken_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_AETRRX_CDRMODDIVCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_aetrrx_termhiz_en_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_AETRRX_TERMHIZ_EN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_aetrrx_termhiz_en_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_AETRRX_TERMHIZ_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_aetrsynth_pcspostdivclksel_ovr_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_AETRSYNTH_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_aetrsynth_pcspostdivclksel_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_AETRSYNTH_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_adc_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_adc_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_auxcomp_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_AUXCOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_auxcomp_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_AUXCOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_bias_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_bias_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_BIAS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_ctlecomp_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_CTLECOMP_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_ctlecomp_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_CTLECOMP_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_datfbdiv_b_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DATFBDIV_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_datfbdiv_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DATFBDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_dfe_bias_b_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DFE_BIAS_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_dfe_bias_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DFE_BIAS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_dfe_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DFE_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_dfe_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DFE_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_dfe_yadj_b_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DFE_YADJ_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_dfe_yadj_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DFE_YADJ_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_duty_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DUTY_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_duty_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_DUTY_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_hifreqagc_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_HIFREQAGC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_hifreqagc_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_HIFREQAGC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_ntl_b_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_ntl_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_reg_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_reg_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_vco_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_VCO_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_vco_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_VCO_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_voscreg_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_VOSCREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_apdrx_voscreg_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_APDRX_VOSCREG_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_adc_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_adc_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_cdrfbdiv_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_CDRFBDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_cdrfbdiv_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_CDRFBDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_pdet_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_PDET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_pdet_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_PDET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_pfd_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_PFD_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_pfd_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_PFD_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_refdiv_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_refdiv_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_reg_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_reg_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_s2pa_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_S2PA_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_s2pa_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_S2PA_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_s2pb_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_S2PB_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_s2pb_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_S2PB_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_vco_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_VCO_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_vco_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_VCO_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_voscreg_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_VOSCREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstrx_voscreg_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTRX_VOSCREG_OVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstsynth_postdiv_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTSYNTH_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_arstsynth_postdiv_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_ARSTSYNTH_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_drstrx_dpif_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_DRSTRX_DPIF_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_drstrx_dpif_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_DRSTRX_DPIF_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_drstrx_ppm_ovr_b_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_DRSTRX_PPM_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxrstpdovr_drstrx_ppm_ovren_attr == SERDES_IP_LANE_L3_CFG_RXRSTPDOVR_DRSTRX_PPM_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_cdrlock2data_locovr_attr == SERDES_IP_LANE_L3_CFG_RXSIGDET_CDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_diglfpsdeten_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_diglfpsdeten_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_diglfpsdeten_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_diglfpsdeten_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_diglfpsdeten_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrancnten_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrancnten_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrancnten_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrancnten_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrancnten_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrancnten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrandeten_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrandeten_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrandeten_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrandeten_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrandeten_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_digtrandeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_eiosdeten_muxd0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_eiosdeten_muxd1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_eiosdeten_muxd2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_eiosdeten_muxd3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_eiosdeten_muxd4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_eiosdeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_enable_attr == SERDES_IP_LANE_L3_CFG_RXSIGDET_ENABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_fastlock_winsize_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_leveldeten_muxd0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_leveldeten_muxd1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_leveldeten_muxd2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_leveldeten_muxd3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_leveldeten_muxd4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_leveldeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_lfpsexit_delay_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_locovren_attr == SERDES_IP_LANE_L3_CFG_RXSIGDET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_ppmdeten_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_ppmdeten_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_ppmdeten_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_ppmdeten_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_ppmdeten_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_ppmdeten_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_rxeq_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_rxeqen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_rxeqen_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_rxleveldet_debounce_dncount_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_rxleveldet_debounce_flush_en_attr == SERDES_IP_LANE_L3_CFG_RXSIGDET_RXLEVELDET_DEBOUNCE_FLUSH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_rxleveldet_debounce_upcount_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_sigdet_debounce_attr == SERDES_IP_LANE_L3_CFG_RXSIGDET_SIGDET_DEBOUNCE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_tmr_clksel_attr == SERDES_IP_LANE_L3_CFG_RXSIGDET_TMR_CLKSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_toggle_count_en_attr == SERDES_IP_LANE_L3_CFG_RXSIGDET_TOGGLE_COUNT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_toggle_count_pause_attr == SERDES_IP_LANE_L3_CFG_RXSIGDET_TOGGLE_COUNT_PAUSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdet_toggle_monitor_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdetin_eiosdetectstat_locovr_attr == SERDES_IP_LANE_L3_CFG_RXSIGDETIN_EIOSDETECTSTAT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdetin_locovren_attr == SERDES_IP_LANE_L3_CFG_RXSIGDETIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdetin_ovrcdrlock2data_locovr_attr == SERDES_IP_LANE_L3_CFG_RXSIGDETIN_OVRCDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdetin_ovrencdrlock2data_locovr_attr == SERDES_IP_LANE_L3_CFG_RXSIGDETIN_OVRENCDRLOCK2DATA_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdetout_lock2data_noforce_ltr_locovr_attr == SERDES_IP_LANE_L3_CFG_RXSIGDETOUT_LOCK2DATA_NOFORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsigdetout_locovren_attr == SERDES_IP_LANE_L3_CFG_RXSIGDETOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxspare0_attr == 32'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxspare_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsqlchlfps_consec_one_thresh_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsqlchlfps_consec_zero_thresh_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsqlchlfps_cycle_thresh_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsqlchlfps_dat_bitorder_attr == SERDES_IP_LANE_L3_CFG_RXSQLCHLFPS_DAT_BITORDER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsqlchlfps_debounce_type_attr == SERDES_IP_LANE_L3_CFG_RXSQLCHLFPS_DEBOUNCE_TYPE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsqlchlfps_one_run_length_thresh_attr == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsqlchlfps_one_run_length_timeout_attr == 8'd103
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsqlchlfps_zero_run_length_thresh_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsqlchlfps_zero_run_length_timeout_attr == 8'd103
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsynthdiv_slowmed_en_muxd0_attr == SERDES_IP_LANE_L3_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsynthdiv_slowmed_en_muxd1_attr == SERDES_IP_LANE_L3_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsynthdiv_slowmed_en_muxd2_attr == SERDES_IP_LANE_L3_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsynthdiv_slowmed_en_muxd3_attr == SERDES_IP_LANE_L3_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxsynthdiv_slowmed_en_muxd4_attr == SERDES_IP_LANE_L3_CFG_RXSYNTHDIV_SLOWMED_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxterm_cal_locovr_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxterm_coarse_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxterm_locovren_attr == SERDES_IP_LANE_L3_CFG_RXTERM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxterm_modeselect_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxtermhiz_en_locovr_attr == SERDES_IP_LANE_L3_CFG_RXTERMHIZ_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxtermhiz_locovren_attr == SERDES_IP_LANE_L3_CFG_RXTERMHIZ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxvoscreg_bypass_vosc_attr == SERDES_IP_LANE_L3_CFG_RXVOSCREG_BYPASS_VOSC_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxvoscregopampoffsetctrl_sel_attr == SERDES_IP_LANE_L3_CFG_RXVOSCREGOPAMPOFFSETCTRL_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxvoscregopampoffseterr_locovren_attr == SERDES_IP_LANE_L3_CFG_RXVOSCREGOPAMPOFFSETERR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxvoscregopampoffseterr_sel_locovr_attr == SERDES_IP_LANE_L3_CFG_RXVOSCREGOPAMPOFFSETERR_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxvoscregvref_locovren_attr == SERDES_IP_LANE_L3_CFG_RXVOSCREGVREF_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_rxvoscregvref_sel_locovr_attr == SERDES_IP_LANE_L3_CFG_RXVOSCREGVREF_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlch_acqgain_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlch_acqtime_attr == 13'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlch_cal_quiet_locovr_attr == SERDES_IP_LANE_L3_CFG_SQLCH_CAL_QUIET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlch_cal_sel_locovr_attr == SERDES_IP_LANE_L3_CFG_SQLCH_CAL_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlch_calctrl_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlch_calen_locovr_attr == SERDES_IP_LANE_L3_CFG_SQLCH_CALEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlch_caltimer_attr == 16'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlch_clkgate_locovr_attr == SERDES_IP_LANE_L3_CFG_SQLCH_CLKGATE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlch_cmshiften_attr == SERDES_IP_LANE_L3_CFG_SQLCH_CMSHIFTEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_acq_gain_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_acq_pct_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_cal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_clr_errlog_attr == SERDES_IP_LANE_L3_CFG_SQLCH_CONT_CLR_ERRLOG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_controller_mode_attr == SERDES_IP_LANE_L3_CFG_SQLCH_CONT_CONTROLLER_MODE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_dis_attr == SERDES_IP_LANE_L3_CFG_SQLCH_CONT_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_pause_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_postcal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_precal_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlch_cont_quiet_time_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlch_lfps_en_attr == SERDES_IP_LANE_L3_CFG_SQLCH_LFPS_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlch_locovren_attr == SERDES_IP_LANE_L3_CFG_SQLCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlch_ovrd_val_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlch_pkdet_freqsel_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlch_polarity_attr == SERDES_IP_LANE_L3_CFG_SQLCH_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlch_rdacen_attr == SERDES_IP_LANE_L3_CFG_SQLCH_RDACEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlch_thresh_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlch_time_out_attr == 16'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlch_vrefsel0_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlch_vrefsel1_locovr_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlch_vrefsel_ovr_en_attr == SERDES_IP_LANE_L3_CFG_SQLCH_VREFSEL_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlchdeb_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlchdeb_deb_cnt_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlchdeb_deb_status_cnt_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlchdeb_en_attr == SERDES_IP_LANE_L3_CFG_SQLCHDEB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlchdeb_ign_cnt_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlchdeb_sigdet_ctrl_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlchdeb_thresh_cnt_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlchdebout_exit_good_debounced_locovr_attr == SERDES_IP_LANE_L3_CFG_SQLCHDEBOUT_EXIT_GOOD_DEBOUNCED_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlchdebout_exit_good_debounced_status_locovr_attr == SERDES_IP_LANE_L3_CFG_SQLCHDEBOUT_EXIT_GOOD_DEBOUNCED_STATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlchdebout_exit_good_locovr_attr == SERDES_IP_LANE_L3_CFG_SQLCHDEBOUT_EXIT_GOOD_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_sqlchdebout_locovren_attr == SERDES_IP_LANE_L3_CFG_SQLCHDEBOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_trancnt_off_attr == 10'd255
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_trancnt_on_attr == 10'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_trancntout_det_locovr_attr == SERDES_IP_LANE_L3_CFG_TRANCNTOUT_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_trancntout_locovren_attr == SERDES_IP_LANE_L3_CFG_TRANCNTOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_trandet_ax_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_trandet_ay_attr == 6'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_trandet_off_h_attr == 6'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_trandet_off_l_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_trandet_on_h_attr == 6'd39
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_trandet_on_l_attr == 6'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_trandetout_det_locovr_attr == SERDES_IP_LANE_L3_CFG_TRANDETOUT_DET_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_trandetout_locovren_attr == SERDES_IP_LANE_L3_CFG_TRANDETOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_tx2rxlb_en_attr == SERDES_IP_LANE_L3_CFG_TX2RXLB_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_tx2rxlb_init_offset_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_tx_cmn_on_state_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_tx_fastregpwrup_en_attr == SERDES_IP_LANE_L3_CFG_TX_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_tx_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_tx_pg_disable_attr == SERDES_IP_LANE_L3_CFG_TX_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_tx_synth_on_state_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_tx_synth_sel_amode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_tx_synth_sel_bmode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_tx_synth_sel_cmode_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_tx_synth_sel_dmode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_tx_synth_sel_emode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_tx_txdetrx_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txadc_count_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txadc_req_attr == SERDES_IP_LANE_L3_CFG_TXADC_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txaprobe_addr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txaprobe_lastmux_isolate_attr == SERDES_IP_LANE_L3_CFG_TXAPROBE_LASTMUX_ISOLATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txaprobeadc_current_direction_attr == SERDES_IP_LANE_L3_CFG_TXAPROBEADC_CURRENT_DIRECTION_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txaprobeadc_resistor_enable_attr == SERDES_IP_LANE_L3_CFG_TXAPROBEADC_RESISTOR_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txaprobeadc_vcm_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txbdvdr_pma2pcstxworden_attr == SERDES_IP_LANE_L3_CFG_TXBDVDR_PMA2PCSTXWORDEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txbeacon_div_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txbeacon_sel_attr == SERDES_IP_LANE_L3_CFG_TXBEACON_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txbias_icc20uadj_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txbias_icc80uadj_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txbias_locovren_attr == SERDES_IP_LANE_L3_CFG_TXBIAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txbias_termcal_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txbist_biterror_en_attr == SERDES_IP_LANE_L3_CFG_TXBIST_BITERROR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txbist_locovren_attr == SERDES_IP_LANE_L3_CFG_TXBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txbist_modesel_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txbist_oobmode_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txbist_oobtburst_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txbist_oobtcomrstinit_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txbist_oobtcomsas_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txbist_oobtcomwake_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txbist_seed_attr == 31'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_size_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf00_attr == 32'd1985229328
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf01_attr == 32'd4275878552
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf02_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf03_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf04_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf05_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf06_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf07_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf08_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txbist_udp_vf09_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txbit_select_muxd0_attr == SERDES_IP_LANE_L3_CFG_TXBIT_SELECT_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txbit_select_muxd1_attr == SERDES_IP_LANE_L3_CFG_TXBIT_SELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txbit_select_muxd2_attr == SERDES_IP_LANE_L3_CFG_TXBIT_SELECT_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txbit_select_muxd3_attr == SERDES_IP_LANE_L3_CFG_TXBIT_SELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txbit_select_muxd4_attr == SERDES_IP_LANE_L3_CFG_TXBIT_SELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txbti_data_replication_attr == SERDES_IP_LANE_L3_CFG_TXBTI_DATA_REPLICATION_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txbti_tx_idle_data_en_attr == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcal_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcal_tclkduty_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalduty_bin_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalduty_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTY_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalduty_sel_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutybg_abort_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutybg_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutybg_ready_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutycomp_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutycomp_offset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_codeoffset_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_finish_side_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_init_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_initval_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_invert_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_precalfsmstart_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_req_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_round_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_runcount_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsm_signmagen_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsmout_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompfsmout_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompmeas_dlycount_attr == 9'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompmeas_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompmeas_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompmeas_req_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompmeasout_ack_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPMEASOUT_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompmeasout_erravg_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPMEASOUT_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutycompmeasout_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYCOMPMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_bg_en_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_bg_one_step_cal_en_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_fg_inc_cal_en_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_fg_one_step_cal_en_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_finish_side_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_init_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_invert_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_req_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_round_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_runcount_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutyfsm_signmagen_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeas_dlycount_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeas_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeas_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeas_pow2count_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeas_req_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeasout_ack_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYMEASOUT_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeasout_erravg_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYMEASOUT_ERRAVG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutymeasout_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutystat_done_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYSTAT_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaldutystat_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALDUTYSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalptr_pstate_duty_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalptr_pstate_dutycomp_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalptr_pstate_regopampoffset_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_duty_muxd0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_duty_muxd1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_duty_muxd2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_duty_muxd3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_duty_muxd4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_dutycomp_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_dutycomp_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_dutycomp_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_dutycomp_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_dutycomp_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_regopampoffset_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalptr_quad_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffset_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_finish_side_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_invert_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_maxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_round_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_runcount_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsm_signmagen_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetfsmout_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetmeas_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcaltclkdutyforce_div1_attr == SERDES_IP_LANE_L3_CFG_TXCALTCLKDUTYFORCE_DIV1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txcdrdiv_local_en_attr == SERDES_IP_LANE_L3_CFG_TXCDRDIV_LOCAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txclk_keepalive_en_b_locovr_attr == SERDES_IP_LANE_L3_CFG_TXCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txclk_locovren_attr == SERDES_IP_LANE_L3_CFG_TXCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txclkgenmuxsel_txinternal_attr == SERDES_IP_LANE_L3_CFG_TXCLKGENMUXSEL_TXINTERNAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txdetectrx_thr_attr == 5'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeas_count_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeas_dlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeas_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXDETECTRXMEAS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeas_locovren_attr == SERDES_IP_LANE_L3_CFG_TXDETECTRXMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeas_validdlycount_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeasin_locovren_attr == SERDES_IP_LANE_L3_CFG_TXDETECTRXMEASIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeasin_start_locovr_attr == SERDES_IP_LANE_L3_CFG_TXDETECTRXMEASIN_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeaspcs_locovren_attr == SERDES_IP_LANE_L3_CFG_TXDETECTRXMEASPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeaspcs_req_locovr_attr == SERDES_IP_LANE_L3_CFG_TXDETECTRXMEASPCS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeasval_locovren_attr == SERDES_IP_LANE_L3_CFG_TXDETECTRXMEASVAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txdetectrxmeasval_stat_locovr_attr == SERDES_IP_LANE_L3_CFG_TXDETECTRXMEASVAL_STAT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txdetrx_levn_attr == 6'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txdetrx_levnm1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txdetrx_levnp1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txdetrx_levnp2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txdrv_hizen_locovr_attr == SERDES_IP_LANE_L3_CFG_TXDRV_HIZEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txdrv_levn_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txdrv_levnm1_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txdrv_levnp1_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txdrv_levnp2_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txdrv_locovren_attr == SERDES_IP_LANE_L3_CFG_TXDRV_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txdrv_refcken_attr == SERDES_IP_LANE_L3_CFG_TXDRV_REFCKEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txdrv_termref_attr == SERDES_IP_LANE_L3_CFG_TXDRV_TERMREF_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txdrvmute_locovr_attr == SERDES_IP_LANE_L3_CFG_TXDRVMUTE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txdrvmute_locovren_attr == SERDES_IP_LANE_L3_CFG_TXDRVMUTE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txduty_ctrl_disable_attr == SERDES_IP_LANE_L3_CFG_TXDUTY_CTRL_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txduty_pad_sense_en_attr == SERDES_IP_LANE_L3_CFG_TXDUTY_PAD_SENSE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txdutycal_div16_en_attr == SERDES_IP_LANE_L3_CFG_TXDUTYCAL_DIV16_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txdutycal_div1_en_attr == SERDES_IP_LANE_L3_CFG_TXDUTYCAL_DIV1_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txdutycal_div2_en_attr == SERDES_IP_LANE_L3_CFG_TXDUTYCAL_DIV2_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txdutycal_div4_en_attr == SERDES_IP_LANE_L3_CFG_TXDUTYCAL_DIV4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txdutycal_div8_en_attr == SERDES_IP_LANE_L3_CFG_TXDUTYCAL_DIV8_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txfifo_elecidle_deskew_en_attr == SERDES_IP_LANE_L3_CFG_TXFIFO_ELECIDLE_DESKEW_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txfifo_force_txidlebit1_zero_disable_attr == SERDES_IP_LANE_L3_CFG_TXFIFO_FORCE_TXIDLEBIT1_ZERO_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txfifo_kill_dly_10b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txfifo_kill_dly_16b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txfifo_kill_dly_20b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txfifo_kill_dly_32b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txfifo_kill_dly_40b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txfifo_kill_dly_64b_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txfifo_kill_dly_80b_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txfifo_kill_dly_8b_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txfifo_kill_en_attr == SERDES_IP_LANE_L3_CFG_TXFIFO_KILL_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txfsm_cken_ovr_attr == SERDES_IP_LANE_L3_CFG_TXFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txfsm_cken_ovren_attr == SERDES_IP_LANE_L3_CFG_TXFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txfsm_main_on_state_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txl1d1_doze_ctrl_attr == SERDES_IP_LANE_L3_CFG_TXL1D1_DOZE_CTRL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txl1d1_txbias_ctrl_attr == SERDES_IP_LANE_L3_CFG_TXL1D1_TXBIAS_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txlanepam_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXLANEPAM_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txlanepam_locovren_attr == SERDES_IP_LANE_L3_CFG_TXLANEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txmeaslatovrhd_meas_sel_attr == SERDES_IP_LANE_L3_CFG_TXMEASLATOVRHD_MEAS_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txmute_delay_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txntl_changeref_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXNTL_CHANGEREF_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txntl_changeref_val_locovr_attr == SERDES_IP_LANE_L3_CFG_TXNTL_CHANGEREF_VAL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txntl_chrgtime_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txntl_en_attr == SERDES_IP_LANE_L3_CFG_TXNTL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txntl_fsmclksel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txntl_locovren_attr == SERDES_IP_LANE_L3_CFG_TXNTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txntl_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txntl_pdmtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txntl_pdn_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txntl_pumtchval_attr == 19'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txntl_pup_vrefcode_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txntl_smpltime_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txntl_txm_charge_up_locovr_attr == SERDES_IP_LANE_L3_CFG_TXNTL_TXM_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txntl_txm_pull_dn_locovr_attr == SERDES_IP_LANE_L3_CFG_TXNTL_TXM_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txntl_txm_sense_locovr_attr == SERDES_IP_LANE_L3_CFG_TXNTL_TXM_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txntl_txp_charge_up_locovr_attr == SERDES_IP_LANE_L3_CFG_TXNTL_TXP_CHARGE_UP_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txntl_txp_pull_dn_locovr_attr == SERDES_IP_LANE_L3_CFG_TXNTL_TXP_PULL_DN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txntl_txp_sense_locovr_attr == SERDES_IP_LANE_L3_CFG_TXNTL_TXP_SENSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txp2s_txwordsyncbypen_attr == SERDES_IP_LANE_L3_CFG_TXP2S_TXWORDSYNCBYPEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txpam_bitorder_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txpam_gray_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXPAM_GRAY_EN_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txpam_locovren_attr == SERDES_IP_LANE_L3_CFG_TXPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txpam_precode_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXPAM_PRECODE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txpcs_locovren_attr == SERDES_IP_LANE_L3_CFG_TXPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txpcs_txenable_locovr_attr == SERDES_IP_LANE_L3_CFG_TXPCS_TXENABLE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txpcsbist_en_locovr_attr == SERDES_IP_LANE_L3_CFG_TXPCSBIST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txpcsbist_locovren_attr == SERDES_IP_LANE_L3_CFG_TXPCSBIST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txratewidth_clk_chk_disable_attr == SERDES_IP_LANE_L3_CFG_TXRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txratewidth_etr_on_delay_attr == 12'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txratewidth_locovren_attr == SERDES_IP_LANE_L3_CFG_TXRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txreg_toggle_pwrupacc_on_rate_change_en_attr == SERDES_IP_LANE_L3_CFG_TXREG_TOGGLE_PWRUPACC_ON_RATE_CHANGE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txreg_toggle_reset_on_rate_change_en_attr == SERDES_IP_LANE_L3_CFG_TXREG_TOGGLE_RESET_ON_RATE_CHANGE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txresetdel_sel_attr == SERDES_IP_LANE_L3_CFG_TXRESETDEL_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_en_b_attr == SERDES_IP_LANE_L3_CFG_TXRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s0q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s0q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s1q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s1q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s2q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s2q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s2q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s2q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s2q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s2q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s2q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s3q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s3q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s3q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s3q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s3q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s3q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s3q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s3q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s4q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s4q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evdn_delay_lut_sel_s5q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_entry2_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s0q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s0q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s1q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s1q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s1q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s1q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s1q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s1q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s2q0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s2q1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s2q2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s2q3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s2q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s2q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s2q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s2q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s3q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s3q1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s3q2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s3q3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s3q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s3q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s3q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s3q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s4q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s4q1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpu_evup_delay_lut_sel_s5q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_duty_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_bitckdvdrcken_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_bias_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_dn_ptr0_s_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_up_ptr0_s_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_drvdoze_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_p2s_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_dn_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_up_ptr0_s_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpurst_pma2pcstxword_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpurst_regreset_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrpurst_txdetectrx_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_aetrtx_bitckdvdrcken_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_AETRTX_BITCKDVDRCKEN_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_aetrtx_bitckdvdrcken_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_AETRTX_BITCKDVDRCKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_aetrtx_regpwrupacc_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_AETRTX_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_aetrtx_regpwrupacc_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_AETRTX_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_adc_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_adc_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_drvdoze_b_ovr_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_DRVDOZE_B_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_drvdoze_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_DRVDOZE_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_duty_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_DUTY_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_duty_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_DUTY_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_ntl_b_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_NTL_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_ntl_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_NTL_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_p2s_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_P2S_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_p2s_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_P2S_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_reg_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_apdtx_reg_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_APDTX_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_arsttx_adc_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_ARSTTX_ADC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_arsttx_adc_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_ARSTTX_ADC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_arsttx_pma2pcstxword_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_ARSTTX_PMA2PCSTXWORD_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_arsttx_pma2pcstxword_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_ARSTTX_PMA2PCSTXWORD_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_arsttx_regreset_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_ARSTTX_REGRESET_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_arsttx_regreset_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_ARSTTX_REGRESET_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_arsttx_txdetectrx_ovr_b_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_ARSTTX_TXDETECTRX_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrstpdovr_arsttx_txdetectrx_ovren_attr == SERDES_IP_LANE_L3_CFG_TXRSTPDOVR_ARSTTX_TXDETECTRX_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txrststate_hiz_en_attr == SERDES_IP_LANE_L3_CFG_TXRSTSTATE_HIZ_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txspare0_attr == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txspare_attr == 10'd384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txterm_coarse_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txtermtrim_locovren_attr == SERDES_IP_LANE_L3_CFG_TXTERMTRIM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txtermtrim_nmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txtermtrim_pmos_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txwclk_div_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txwclk_div_en_attr == SERDES_IP_LANE_L3_CFG_TXWCLK_DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txwclk_div_smpl_attr == SERDES_IP_LANE_L3_CFG_TXWCLK_DIV_SMPL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txwptr_init01_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txwptr_init02_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txwptr_init04_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txwptr_init08_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txwptr_init16_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txwptr_init32_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_l3_cfg_txwptr_init_rx2txparlb_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_dfeyadj_aging_cdrlock2data_loc_ov_attr == SERDES_IP_LANE_RXEQ_L0_CFG_DFEYADJ_AGING_CDRLOCK2DATA_LOC_OV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_dfeyadj_aging_cdrlock2data_loc_ov_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_DFEYADJ_AGING_CDRLOCK2DATA_LOC_OV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_dfeyadj_aging_div_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_dfeyadj_aging_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_DFEYADJ_AGING_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxagc_ctlecomp_filterbypass_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXAGC_CTLECOMP_FILTERBYPASS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxagc_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXAGC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxbgcal_calfsmmeas_dlycount_attr == 10'd392
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxbgcal_clear_mask_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxbgcal_fsmmaxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxbgcal_lpfax_coarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxbgcal_lpfax_fine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxbgcalorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxbgcalorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxbgcalorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_calbiasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_calbiasboost_use_lut_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_CALBIASBOOST_USE_LUT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_callbbiasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_callbbiasboost_use_lut_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_CALLBBIASBOOST_USE_LUT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlecomp_filterbypass_smplrcal_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_CTLECOMP_FILTERBYPASS_SMPLRCAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg1_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg2_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg3_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctleinput_probe_mux_smplrcal_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg1_probe_mux_en_smplrcal_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg1_state_en_smplrcal_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg1_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg1_state_en_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg1_state_en_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg1_use_stg2code_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_CTLESTG1_USE_STG2CODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg2_probe_mux_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg2_state_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg2_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg2_state_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg2_state_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg3_probe_mux_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg3_state_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg3_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg3_state_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_ctlestg3_state_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_hifreqagc_n5targin_sel_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_HIFREQAGC_N5TARGIN_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_inputcmadjust_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_inputcmadjust_stg1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_inputcmadjust_stg2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_inputcmadjust_stg3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_sdimode_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCAL_SDIMODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_smplroffset_aux0_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_smplroffset_aux1_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_smplroffset_d0_bot_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_smplroffset_d0_mid_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_smplroffset_d0_top_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_smplroffset_d1_bot_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_smplroffset_d1_mid_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_smplroffset_d1_top_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_tfrtrim_outen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_tfrtrim_outen_tfrcal_stg1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_tfrtrim_outen_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcal_tfrtrim_outen_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalalign_iqclk_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalalign_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALALIGN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctl_cal_abort_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALCTL_CAL_ABORT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctl_cal_type_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctl_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALCTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctl_post_delay_pow2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctl_pre_delay_pow2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecalctrl_input_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecalctrl_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALCTLECALCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecalctrl_stg1_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecalctrl_stg1_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecalctrl_stg2_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecalctrl_stg2_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecalctrl_stg3_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecalctrl_stg3_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecompoffset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecompoffset_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALCTLECOMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecompoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALCTLECOMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecompoffsetfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALCTLECOMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalctlecompoffsetfsmout_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaldutybkgnd_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALDUTYBKGND_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaldutybkgnd_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALDUTYBKGND_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_biasboost_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_hf1deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_hf1resdcgain_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_hf2cap_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_hf2deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_hf2reszero_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_hf3deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_hf3resdcgain_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_hf4deq_gray_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaleq_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALEQ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_ctlecmnmode_stg1_finish_side_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALFSM_CTLECMNMODE_STG1_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_ctlecmnmode_stg1_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_ctlecmnmode_stg2_finish_side_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALFSM_CTLECMNMODE_STG2_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_ctlecmnmode_stg2_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_ctlecmnmode_stg3_finish_side_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALFSM_CTLECMNMODE_STG3_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_ctlecmnmode_stg3_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_runcount_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_smplroffset_finish_side_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALFSM_SMPLROFFSET_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsm_smplroffset_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsmmeas_ctlecmnmode_stg1_invert_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALFSMMEAS_CTLECMNMODE_STG1_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsmmeas_ctlecmnmode_stg2_invert_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALFSMMEAS_CTLECMNMODE_STG2_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsmmeas_ctlecmnmode_stg3_invert_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALFSMMEAS_CTLECMNMODE_STG3_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalfsmmeas_smplroffset_invert_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALFSMMEAS_SMPLROFFSET_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_ctlecmnmode_stg1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_ctlecmnmode_stg2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_ctlecmnmode_stg3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_aux0_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_aux1_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_d0_bot_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_d0_mid_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_d0_top_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_d1_bot_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_d1_mid_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_d1_top_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_e0_lo_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalinit_smplroffset_e1_lo_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeas_pow2count_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasin_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasin_req_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASIN_REQ_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasin_req_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASIN_REQ_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasin_req_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASIN_REQ_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasout_ack_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASOUT_ACK_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasout_ack_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASOUT_ACK_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasout_ack_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASOUT_ACK_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasout_avg_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASOUT_AVG_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasout_avg_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASOUT_AVG_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasout_avg_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASOUT_AVG_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalmeasout_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaloffsetfsmout_auxdatacomp_offset_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALOFFSETFSMOUT_AUXDATACOMP_OFFSET_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaloffsetfsmout_boost_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALOFFSETFSMOUT_BOOST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaloffsetfsmout_edgecomp_offset_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALOFFSETFSMOUT_EDGECOMP_OFFSET_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcaloffsetfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalset_cal_clear_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalset_cal_mode_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALSET_CAL_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalset_cal_req_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALSET_CAL_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalset_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalstat_cal_ack_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALSTAT_CAL_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalstat_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalsummerfsmout_comp_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALSUMMERFSMOUT_COMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcalsummerfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCALSUMMERFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcdrphd_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCDRPHD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxcdrphd_override_ignore_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCDRPHD_OVERRIDE_IGNORE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_caloffset_range_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_calstg1offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_calstg1offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_calstg2offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_calstg2offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_calstg3offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_calstg3offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_dccouple_sigpath_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCTLE_DCCOUPLE_SIGPATH_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_lbbiasboost_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCTLE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_stg1tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_stg2tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_stg3tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_tfrtrim_outmem_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCTLE_TFRTRIM_OUTMEM_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctle_tfrtrim_outpen_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCTLE_TFRTRIM_OUTPEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctledc_dccouple_tgate_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCTLEDC_DCCOUPLE_TGATE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxctledc_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXCTLEDC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxdfe_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXDFE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxdfe_tapgain_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxdfepam_enable_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXDFEPAM_ENABLE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxdfepam_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXDFEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxdpifjit_enb_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXDPIFJIT_ENB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxdpifjit_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXDPIFJIT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxdpifjit_offset_locovr_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqadj_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQADJ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqadj_yadjust_aux0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqadj_yadjust_aux1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqadj_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqadj_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqadj_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqadj_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqadj_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqadj_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqauxxor_amux_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqauxxor_dmux_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqauxxor_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQAUXXOR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcal2flx_pstate_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCAL2FLX_PSTATE_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcal2flx_rate_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCAL2FLX_RATE_MASK_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_16a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_16b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_16c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_16d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_16e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_1a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_1b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_1c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_1d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_1e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_2a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_2b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_2c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_2d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_2e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_4a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_4b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_4c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_4d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_4e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_8a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_8b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_8c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_8d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalhfagcbiasadj_lut_8e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_16a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_16b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_16c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_16d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_16e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_1a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_1b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_1c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_1d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_1e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_2a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_2b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_2c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_2d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_2e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_4a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_4b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_4c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_4d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_4e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_8a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_8b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_8c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_8d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcallofreqagcgain_lut_8e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_16a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_16b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_16c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_16d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_16e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_1a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_1b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_1c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_1d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_1e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_2a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_2b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_2c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_2d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_2e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_4a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_4b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_4c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_4d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_4e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_8a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_8b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_8c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_8d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcalmidbandzero_lut_8e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcals_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCALS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcals_offset_datasummer0_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcals_offset_datasummer0_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcals_offset_datasummer1_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcals_offset_datasummer1_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcals_offset_edgesummer0_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcals_offset_edgesummer0_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcals_offset_edgesummer1_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcals_offset_edgesummer1_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcdr_force_ltr_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCDR_FORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqcdr_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCDR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqctl_clear_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCTL_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqctl_fg_run_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCTL_FG_RUN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqctlelut_hifreqagcres_ovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCTLELUT_HIFREQAGCRES_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqctlelut_hifreqvgagain_ovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCTLELUT_HIFREQVGAGAIN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqctls_oddeven_tapgain_sel_inv_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCTLS_ODDEVEN_TAPGAIN_SEL_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqctls_static_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQCTLS_STATIC_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqdat_aux_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQDAT_AUX_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqdat_edge_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQDAT_EDGE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqdatactl_auxswap_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqdatactl_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQDATACTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqdatarate_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQDATARATE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqdatarate_rx_rate_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqdfeyadj_agingl2r_delay_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqdfeyadj_agingl2r_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQDFEYADJ_AGINGL2R_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqedgeadj_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEDGEADJ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqedgeadj_yadjust_edge0lo_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqedgeadj_yadjust_edge1lo_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm2flx_ehm_done_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHM2FLX_EHM_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm2flx_ehm_done_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHM2FLX_EHM_DONE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm2flx_ehm_err_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHM2FLX_EHM_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm2flx_ehm_err_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHM2FLX_EHM_ERR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm2flx_ehm_fom_locovr_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHM2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_data_extshift_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHM_DATA_EXTSHIFT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_distance_th_50p_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_distance_th_rate_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_err_mask_vf00_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_err_mask_vf01_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_event_rate_vf00_attr == 32'd67108864
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_event_rate_vf01_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_general_in_vf00_attr == 32'd5505024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_general_in_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_lms_th_50p_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_lms_th_rate_attr == 20'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_mask_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_no_change_th_50p_attr == 12'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_no_change_th_rate_attr == 12'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_reflections_num_50p_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_reflections_num_rate_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_slicer_swap_cb_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHM_SLICER_SWAP_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_sym_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_sym_dly_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_tap_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_test_aux_slicer_val_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehm_test_hits_th_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjaux_ehm_yadjust_aux0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjaux_ehm_yadjust_aux1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjaux_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJAUX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjauxen_ehm_aux_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJAUXEN_EHM_AUX_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjauxen_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJAUXEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjauxltch_aux_yadj_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJAUXLTCH_AUX_YADJ_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjauxltch_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJAUXLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdata_ehm_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdata_ehm_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdata_ehm_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdata_ehm_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdata_ehm_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdata_ehm_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdata_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdataen_ehm_data_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJDATAEN_EHM_DATA_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdataen_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJDATAEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdataltch_data_yadj_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJDATALTCH_DATA_YADJ_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqehmyadjdataltch_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQEHMYADJDATALTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2ehm_ehm_run_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2EHM_EHM_RUN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2ehm_ehm_run_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2EHM_EHM_RUN_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2lms_coarse_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2LMS_COARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2lms_ctrl_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2LMS_CTRL_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2lms_dfecore_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2LMS_DFECORE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2lms_force_evrefupd_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2LMS_FORCE_EVREFUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2lms_freeze_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2LMS_FREEZE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2lms_incr_decr_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2LMS_INCR_DECR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2lms_mu_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2LMS_MU_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2lms_rst_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2LMS_RST_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2ofc_ofc_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2OFC_OFC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx2ofc_ofc_en_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX2OFC_OFC_EN_OVRDEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx_pcs_rxeq_clr_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX_PCS_RXEQ_CLR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx_pcs_rxeq_start_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX_PCS_RXEQ_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx_pcs_rxeq_static_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLX_PCS_RXEQ_STATIC_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx_rxrate2pcie1_map_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx_rxrate2pcie2_map_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx_rxrate2pcie3_map_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflx_rxrate2pcie4_map_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxehmdata_ehm_data_slc_sel_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXEHMDATA_EHM_DATA_SLC_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxehmdata_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXEHMDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxfsm_generalpurpose_reg_in_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxfsm_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXFSM_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxfsm_pause_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXFSM_PAUSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxfsm_state_obs_hold_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXFSM_STATE_OBS_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxfsm_state_obs_sel_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXFSM_STATE_OBS_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxltr_force_ltr_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXLTR_FORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxltr_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXLTR_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxpcsrxeyediag_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXPCSRXEYEDIAG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxpcsrxeyediag_start_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXPCSRXEYEDIAG_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqflxsigdet_sel_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFLXSIGDET_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqfsm2ofc_ofc_cal_req_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFSM2OFC_OFC_CAL_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqfsm2ofc_ofc_cal_req_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQFSM2OFC_OFC_CAL_REQ_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_16a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_16b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_16c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_16d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_16e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_1a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_1b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_1c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_1d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_1e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_2a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_2b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_2c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_2d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_2e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_4a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_4b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_4c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_4d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_4e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_8a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_8b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_8c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_8d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqhf2cap_lut_8e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_done_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmax_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmax_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_SATMAX_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmax_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmax_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmax_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_SATMAX_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmax_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_SATMAX_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmax_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_SATMAX_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmin_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmin_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_SATMIN_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmin_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmin_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmin_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_SATMIN_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmin_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_SATMIN_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_satmin_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_SATMIN_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_stable_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_stable_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_STABLE_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_stable_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_stable_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_stable_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_STABLE_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_stable_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_STABLE_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlms2flx_stable_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMS2FLX_STABLE_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsupd_chng_ack_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSUPD_CHNG_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsupd_chng_req_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSUPD_CHNG_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsupd_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSUPD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjaux_lms_vref0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjaux_lms_vref1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjaux_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJAUX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjauxen_lms_aux_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJAUXEN_LMS_AUX_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjauxen_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJAUXEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjauxltch_lms_aux_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJAUXLTCH_LMS_AUX_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjauxltch_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJAUXLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdata_lms_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdata_lms_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdata_lms_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdata_lms_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdata_lms_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdata_lms_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdata_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdataen_lms_data_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJDATAEN_LMS_DATA_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdataen_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJDATAEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdataltch_lms_data_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJDATALTCH_LMS_DATA_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjdataltch_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJDATALTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjedge_lms_yadjust_edge0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjedge_lms_yadjust_edge1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjedge_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJEDGE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjedgeen_lms_edge_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJEDGEEN_LMS_EDGE_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjedgeen_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJEDGEEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjedgeltch_lms_edge_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJEDGELTCH_LMS_EDGE_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqlmsyadjedgeltch_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLMSYADJEDGELTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqltch_dfe_aux_yadj_b_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLTCH_DFE_AUX_YADJ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqltch_dfe_b_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLTCH_DFE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqltch_dfe_data_yadj_b_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLTCH_DFE_DATA_YADJ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqltch_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqltchc_auxswap_b_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLTCHC_AUXSWAP_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqltchc_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQLTCHC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofc2flx_ofc_cal_done_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQOFC2FLX_OFC_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofc2flx_ofc_cal_done_ovrden_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQOFC2FLX_OFC_CAL_DONE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_ctle_rxinpprobemuxen_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_ctle_rxstg1_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_ctle_rxstg1probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_ctle_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_ctle_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_ctle_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_ctle_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_summer_rxinpprobemuxen_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_summer_rxstg1_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_summer_rxstg1probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_summer_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_summer_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_summer_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_summer_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_time_h_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_adapt_time_l_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_ctle_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_ctle_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_ctle_rxstg1probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_ctle_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_ctle_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_ctle_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_ctle_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_summer_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_summer_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_summer_rxstg1probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_summer_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_summer_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_summer_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_summer_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_cal_time_l_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_compsel_ctle_st1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_compsel_ctle_st2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_compsel_ctle_st3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_compsel_idle_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_compsel_sa_d0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_compsel_sa_d1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_compsel_sa_e0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_compsel_sa_e1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_invert_comp_fb_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_lpexitcal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_lpexitcal_time_l_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_adapt_en_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_adapt_thr_sel_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_cal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_cal_thr_sel_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_data_disp_sticky_clr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQOFCCFG_OFC_DATA_DISP_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_disparity_disable_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQOFCCFG_OFC_DISPARITY_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_disparity_leak_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_disparity_thr_sel_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_lpexitcal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_lpf_bypass_en_cb_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQOFCCFG_OFC_LPF_BYPASS_EN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ofc_ratechangecal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_pre_timer_setting_pow2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ratechangecal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_ratechangecal_time_l_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_rxinpprobemuxen_idle_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_rxstg1_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_rxstg1probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_rxstg2_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_rxstg2probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_rxstg3_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqofccfg_rxstg3probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqout_init_restore_avail_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQOUT_INIT_RESTORE_AVAIL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqprecal_code_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqprecal_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQPRECAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_hf1deq_dir_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_BOOSTLUT_HF1DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_hf2deq_dir_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_BOOSTLUT_HF2DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_hf2reszero_dir_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_BOOSTLUT_HF2RESZERO_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_hf3deq_dir_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_BOOSTLUT_HF3DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_idx_hf1deq_vf00_attr == 32'd599186
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_idx_hf1deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_idx_hf2deq_vf00_attr == 32'd1198372
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_idx_hf2deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_idx_hf2reszero_vf00_attr == 32'd4290772992
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_idx_hf2reszero_vf01_attr == 21'd2097151
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_idx_hf3deq_vf00_attr == 32'd2396744
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_idx_hf3deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_init_hf1deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_init_hf2deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_init_hf2reszero_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_boostlut_init_hf3deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_cal_hifreqagcres_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_cal_hifreqvgagain_attr == 7'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_cal_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_cal_yadjust_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_biasboost_dir_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_GAINLUT_BIASBOOST_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_hf1resdcgain_dir_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_GAINLUT_HF1RESDCGAIN_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_hf3resdcgain_dir_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_GAINLUT_HF3RESDCGAIN_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_biasboost_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_biasboost_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_biasboost_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf00_attr == 32'd2863311530
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf01_attr == 32'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf00_attr == 32'd1431655764
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf01_attr == 32'd1431655765
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_lbbiasboost_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_lbbiasboost_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_idx_lbbiasboost_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_init_biasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_init_hf1resdcgain_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_init_hf3resdcgain_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_init_lbbiasboost_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_gainlut_lbbiasboost_dir_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_GAINLUT_LBBIASBOOST_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_latch_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref0_initval_attr == 9'd61
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref1_initval_attr == 9'd191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref2_initval_attr == 9'd321
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref3_initval_attr == 9'd451
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_decr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_AUXVREF_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_frac_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_AUXVREF_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_frac_reset_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_incr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_AUXVREF_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_incr_decr_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_pam4adj_swizzle_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_AUXVREF_PAM4ADJ_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_AUXVREF_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_pol_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_single_step_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_AUXVREF_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_stable_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_AUXVREF_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_AUXVREF_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_targ_0_hi_attr == 9'd149
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_auxvref_targ_0_lo_attr == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_auxvref_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_auxvref_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_dfe_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_dfe_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_edge_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_edge_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_edgevref_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_edgevref_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_iqalign_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_iqalign_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_level_vga_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_vga_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_block_vote_vga_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_blockcount_fast_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_BLOCKCOUNT_FAST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_coarse_detect_clear_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_COARSE_DETECT_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_coarse_detect_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_COARSE_DETECT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_continuous_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_CONTINUOUS_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_datastats_incr_decr_swizzle_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_DATASTATS_INCR_DECR_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_datastats_pol_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_DATASTATS_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_datastats_thres_attr == 16'd1023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe1_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe2_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe3_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe4p_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_core_sel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_decr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_DFE_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_frac_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_DFE_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_frac_reset_mask_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_incr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_DFE_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_incr_decr_mask_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_inner_lvl_filter_en_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_DFE_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_pol_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_single_step_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_DFE_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_stable_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_DFE_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_DFE_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_targtap1_attr == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_targtap2_attr == 7'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_targtap3_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_dfe_targtap4_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_decr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGE_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_frac_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGE_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_frac_reset_mask_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_incr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGE_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_incr_decr_mask_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGE_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_pol_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_single_step_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGE_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_stable_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGE_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edge_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGE_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_decr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGEVREF_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_frac_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGEVREF_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGEVREF_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_incr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGEVREF_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_initval_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGEVREF_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_pol_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGEVREF_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_single_step_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGEVREF_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_stable_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGEVREF_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_edgevref_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_EDGEVREF_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_fast_blockcnt_attr == 16'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_filter_mode_auxvref_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_filter_mode_dfe_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_filter_mode_edge_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_filter_mode_edgevref_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_filter_mode_iqalign_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_filter_mode_vga_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_freeze_auxvrefupd_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_freeze_dfeupd_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_freeze_edgeupd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_freeze_edgevrefupd_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_FREEZE_EDGEVREFUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_freeze_forcebg_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_FREEZE_FORCEBG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_freeze_hifreqagcupd_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_FREEZE_HIFREQAGCUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_freeze_iqalignupd_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_FREEZE_IQALIGNUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_freeze_lofreqagcupd_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_FREEZE_LOFREQAGCUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_freeze_vgaupd_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_FREEZE_VGAUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_gated_update_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_GATED_UPDATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_accum_count_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_accum_level_en_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_decr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_HIFREQAGC_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_frac_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_HIFREQAGC_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_HIFREQAGC_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_incr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_HIFREQAGC_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_n1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_n2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_n3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_n4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_n5_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_HIFREQAGC_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_pol_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_HIFREQAGC_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_single_step_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_HIFREQAGC_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_stable_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_HIFREQAGC_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_hifreqagc_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_HIFREQAGC_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_init_adapt_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_INIT_ADAPT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_decr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_IQALIGN_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_frac_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_IQALIGN_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_IQALIGN_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_incr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_IQALIGN_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_IQALIGN_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_pol_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_IQALIGN_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_single_step_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_IQALIGN_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_stable_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_IQALIGN_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_IQALIGN_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_iqalign_targ_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_itercount_attr == 10'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_latch_delay_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_latch_prepost_delay_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_decr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOFREQAGC_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_frac_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOFREQAGC_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOFREQAGC_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_incr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOFREQAGC_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOFREQAGC_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_pol_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOFREQAGC_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_single_step_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOFREQAGC_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_stable_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOFREQAGC_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_lofreqagc_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOFREQAGC_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_logain_auxvref_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOGAIN_AUXVREF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_logain_dfe_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_logain_edge_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_logain_edgevref_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOGAIN_EDGEVREF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_logain_hifreqagc_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOGAIN_HIFREQAGC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_logain_iqalign_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOGAIN_IQALIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_logain_lofreqagc_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOGAIN_LOFREQAGC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_logain_vga_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_LOGAIN_VGA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_auxvref_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_dfe1_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_dfe23_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_dfe4p_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_edge2_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_edge3_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_edge4_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_edgevref_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_hifreqagc_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_iqalign_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_lofreqagc_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_mu_vga_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_nrz_to_pam4_mode_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_NRZ_TO_PAM4_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_slow_blockcnt_attr == 16'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_start_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_tsettle_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_accum_count_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_accum_level_en_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_decr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_frac_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_incr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_mode_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_pol_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_single_step_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_stable_reset_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_vga_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_VGA_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lms_yadjdata_mid_clamp_zero_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LMS_YADJDATA_MID_CLAMP_ZERO_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_lofreqagcgain_sel_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_LOFREQAGCGAIN_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_caldfedatatap1gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_caldfedatatap2gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_caldfedatatap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_caldfedatatap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_caldfeedgetap2gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_caldfeedgetap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_caldfeedgetap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal0_lofreqagcgain_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_caldfedatatap1gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal1_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_caldfedatatap1gain_attr == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal2_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_caldfedatatap1gain_attr == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal3_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal4_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal5_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal6_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_precal7_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_shift_auxshft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_shift_capture_trigger_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_SHIFT_CAPTURE_TRIGGER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_shift_clear_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_SHIFT_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_shift_dat_bitsel_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_SHIFT_DAT_BITSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_shift_datashft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_shift_edgeshft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_shift_edgeshft_nrz8b10b_pam16b20b_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_shift_polarity_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSET_SHIFT_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap10gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap11gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap12gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap13gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap14gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap15gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap16gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap1gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap2gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap5gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap6gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap7gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap8gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfedatatap9gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfeedgetap2gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfeedgetap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_caldfeedgetap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_hifreqvgagain_attr == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_static_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_auxvref0_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_auxvref1_attr == 9'd223
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_auxvref2_attr == 9'd339
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_auxvref3_attr == 9'd456
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_caldfedatatap1gain_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_caldfeedgetap2gain_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_calhifreqagcres_attr == 6'd52
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_callofreqagcgain_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_edgevref_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_hifreqvgagain_attr == 7'd77
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmax_iqalign_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_auxvref0_attr == 9'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_auxvref1_attr == 9'd173
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_auxvref2_attr == 9'd289
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_auxvref3_attr == 9'd356
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_caldfedatatap1gain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_caldfeedgetap2gain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_calhifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_callofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_edgevref_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqset_swpmin_iqalign_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqsetnrztopam4_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSETNRZTOPAM4_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqsetnrztopam4_switch_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSETNRZTOPAM4_SWITCH_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqsigdet_pause_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSIGDET_PAUSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqspare0_attr == 32'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqspare1_attr == 32'd15871
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqspare2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqsync2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSYNC2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqsync2flx_rxdatapath_ready_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQSYNC2FLX_RXDATAPATH_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqtapctrl_data_tap13to16_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQTAPCTRL_DATA_TAP13TO16_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqtapctrl_data_tap1to4_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQTAPCTRL_DATA_TAP1TO4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqtapctrl_data_tap5to8_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQTAPCTRL_DATA_TAP5TO8_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqtapctrl_data_tap9to12_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQTAPCTRL_DATA_TAP9TO12_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqtapctrl_edge_tap_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQTAPCTRL_EDGE_TAP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqtapctrl_tap1to4gain_dbl_res_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQTAPCTRL_TAP1TO4GAIN_DBL_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqtapctrl_tap5to16gain_dbl_res_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQTAPCTRL_TAP5TO16GAIN_DBL_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvalc_hifreqagcbiasadjust_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvalc_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQVALC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvalc_midbandzero_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvalcl_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQVALCL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvalcl_lofreqagcgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap01gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap02gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap03gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap04gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap05gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap06gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap07gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap08gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap09gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap10gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap11gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap12gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap13gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap14gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap15gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_caldfedatatap16gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvald_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQVALD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvale_caldfeedgetap02gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvale_caldfeedgetap03gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvale_caldfeedgetap04gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxeqvale_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXEQVALE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1cal_clear_mask_attr == 13'd8184
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_aux0_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_aux1_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_d0_bot_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_d0_mid_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_d0_top_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_d1_bot_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_d1_mid_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_d1_top_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_e0_lo_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg1calorder_smplroffset_e1_lo_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2cal_clear_mask_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_aux0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_aux1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_d0_bot_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_d0_mid_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_d0_top_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_d1_bot_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_d1_mid_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_d1_top_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_e0_lo_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfg2calorder_smplroffset_e1_lo_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfgcal_calfsmmeas_dlycount_attr == 10'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfgcal_fsmmaxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfgcal_lpfax_coarse_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxfgcal_lpfax_fine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxhifreqagc_inputcmadjust_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxhifreqagc_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXHIFREQAGC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcal_clear_mask_attr == 13'd8191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_ctlecmnmode_stg1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_ctlecmnmode_stg2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_ctlecmnmode_stg3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_aux0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_aux1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_d0_bot_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_d0_mid_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_d0_top_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_d1_bot_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_d1_mid_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_d1_top_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_e0_lo_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxinitcalorder_smplroffset_e1_lo_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmargin_flx_jit_offset_shift_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmargin_jit_disable_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmargin_jit_enable_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmargin_jit_offset_shift_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmargin_jit_setup_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmargin_volt_comp_mask_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmargin_volt_forcel2d_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXMARGIN_VOLT_FORCEL2D_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmargin_volt_offset_shift_d0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmargin_volt_offset_shift_d1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmarginin_direction_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXMARGININ_DIRECTION_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmarginin_flx_jit_offset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmarginin_locovren_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXMARGININ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmarginin_mode_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXMARGININ_MODE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmarginin_offset_change_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXMARGININ_OFFSET_CHANGE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmarginin_offset_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxmarginin_start_locovr_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXMARGININ_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxsum_cm_vref_attr == 9'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxsum_summer_cmfb_en_attr == SERDES_IP_LANE_RXEQ_L0_CFG_RXSUM_SUMMER_CMFB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l0_cfg_rxsum_summer_cmfb_ibias_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_dfeyadj_aging_cdrlock2data_loc_ov_attr == SERDES_IP_LANE_RXEQ_L1_CFG_DFEYADJ_AGING_CDRLOCK2DATA_LOC_OV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_dfeyadj_aging_cdrlock2data_loc_ov_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_DFEYADJ_AGING_CDRLOCK2DATA_LOC_OV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_dfeyadj_aging_div_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_dfeyadj_aging_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_DFEYADJ_AGING_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxagc_ctlecomp_filterbypass_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXAGC_CTLECOMP_FILTERBYPASS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxagc_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXAGC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxbgcal_calfsmmeas_dlycount_attr == 10'd392
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxbgcal_clear_mask_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxbgcal_fsmmaxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxbgcal_lpfax_coarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxbgcal_lpfax_fine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxbgcalorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxbgcalorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxbgcalorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_calbiasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_calbiasboost_use_lut_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_CALBIASBOOST_USE_LUT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_callbbiasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_callbbiasboost_use_lut_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_CALLBBIASBOOST_USE_LUT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlecomp_filterbypass_smplrcal_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_CTLECOMP_FILTERBYPASS_SMPLRCAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg1_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg2_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg3_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctleinput_probe_mux_smplrcal_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg1_probe_mux_en_smplrcal_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg1_state_en_smplrcal_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg1_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg1_state_en_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg1_state_en_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg1_use_stg2code_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_CTLESTG1_USE_STG2CODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg2_probe_mux_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg2_state_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg2_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg2_state_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg2_state_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg3_probe_mux_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg3_state_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg3_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg3_state_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_ctlestg3_state_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_hifreqagc_n5targin_sel_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_HIFREQAGC_N5TARGIN_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_inputcmadjust_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_inputcmadjust_stg1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_inputcmadjust_stg2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_inputcmadjust_stg3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_sdimode_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCAL_SDIMODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_smplroffset_aux0_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_smplroffset_aux1_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_smplroffset_d0_bot_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_smplroffset_d0_mid_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_smplroffset_d0_top_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_smplroffset_d1_bot_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_smplroffset_d1_mid_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_smplroffset_d1_top_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_tfrtrim_outen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_tfrtrim_outen_tfrcal_stg1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_tfrtrim_outen_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcal_tfrtrim_outen_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalalign_iqclk_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalalign_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALALIGN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctl_cal_abort_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALCTL_CAL_ABORT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctl_cal_type_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctl_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALCTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctl_post_delay_pow2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctl_pre_delay_pow2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecalctrl_input_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecalctrl_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALCTLECALCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecalctrl_stg1_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecalctrl_stg1_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecalctrl_stg2_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecalctrl_stg2_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecalctrl_stg3_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecalctrl_stg3_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecompoffset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecompoffset_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALCTLECOMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecompoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALCTLECOMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecompoffsetfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALCTLECOMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalctlecompoffsetfsmout_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaldutybkgnd_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALDUTYBKGND_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaldutybkgnd_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALDUTYBKGND_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_biasboost_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_hf1deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_hf1resdcgain_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_hf2cap_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_hf2deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_hf2reszero_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_hf3deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_hf3resdcgain_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_hf4deq_gray_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaleq_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALEQ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_ctlecmnmode_stg1_finish_side_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALFSM_CTLECMNMODE_STG1_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_ctlecmnmode_stg1_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_ctlecmnmode_stg2_finish_side_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALFSM_CTLECMNMODE_STG2_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_ctlecmnmode_stg2_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_ctlecmnmode_stg3_finish_side_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALFSM_CTLECMNMODE_STG3_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_ctlecmnmode_stg3_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_runcount_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_smplroffset_finish_side_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALFSM_SMPLROFFSET_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsm_smplroffset_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsmmeas_ctlecmnmode_stg1_invert_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALFSMMEAS_CTLECMNMODE_STG1_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsmmeas_ctlecmnmode_stg2_invert_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALFSMMEAS_CTLECMNMODE_STG2_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsmmeas_ctlecmnmode_stg3_invert_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALFSMMEAS_CTLECMNMODE_STG3_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalfsmmeas_smplroffset_invert_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALFSMMEAS_SMPLROFFSET_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_ctlecmnmode_stg1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_ctlecmnmode_stg2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_ctlecmnmode_stg3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_aux0_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_aux1_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_d0_bot_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_d0_mid_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_d0_top_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_d1_bot_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_d1_mid_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_d1_top_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_e0_lo_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalinit_smplroffset_e1_lo_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeas_pow2count_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasin_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasin_req_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASIN_REQ_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasin_req_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASIN_REQ_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasin_req_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASIN_REQ_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasout_ack_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASOUT_ACK_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasout_ack_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASOUT_ACK_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasout_ack_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASOUT_ACK_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasout_avg_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASOUT_AVG_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasout_avg_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASOUT_AVG_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasout_avg_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASOUT_AVG_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalmeasout_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaloffsetfsmout_auxdatacomp_offset_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALOFFSETFSMOUT_AUXDATACOMP_OFFSET_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaloffsetfsmout_boost_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALOFFSETFSMOUT_BOOST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaloffsetfsmout_edgecomp_offset_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALOFFSETFSMOUT_EDGECOMP_OFFSET_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcaloffsetfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalset_cal_clear_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalset_cal_mode_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALSET_CAL_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalset_cal_req_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALSET_CAL_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalset_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalstat_cal_ack_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALSTAT_CAL_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalstat_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalsummerfsmout_comp_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALSUMMERFSMOUT_COMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcalsummerfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCALSUMMERFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcdrphd_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCDRPHD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxcdrphd_override_ignore_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCDRPHD_OVERRIDE_IGNORE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_caloffset_range_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_calstg1offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_calstg1offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_calstg2offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_calstg2offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_calstg3offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_calstg3offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_dccouple_sigpath_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCTLE_DCCOUPLE_SIGPATH_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_lbbiasboost_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCTLE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_stg1tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_stg2tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_stg3tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_tfrtrim_outmem_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCTLE_TFRTRIM_OUTMEM_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctle_tfrtrim_outpen_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCTLE_TFRTRIM_OUTPEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctledc_dccouple_tgate_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCTLEDC_DCCOUPLE_TGATE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxctledc_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXCTLEDC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxdfe_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXDFE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxdfe_tapgain_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxdfepam_enable_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXDFEPAM_ENABLE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxdfepam_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXDFEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxdpifjit_enb_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXDPIFJIT_ENB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxdpifjit_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXDPIFJIT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxdpifjit_offset_locovr_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqadj_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQADJ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqadj_yadjust_aux0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqadj_yadjust_aux1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqadj_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqadj_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqadj_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqadj_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqadj_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqadj_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqauxxor_amux_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqauxxor_dmux_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqauxxor_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQAUXXOR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcal2flx_pstate_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCAL2FLX_PSTATE_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcal2flx_rate_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCAL2FLX_RATE_MASK_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_16a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_16b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_16c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_16d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_16e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_1a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_1b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_1c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_1d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_1e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_2a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_2b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_2c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_2d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_2e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_4a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_4b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_4c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_4d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_4e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_8a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_8b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_8c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_8d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalhfagcbiasadj_lut_8e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_16a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_16b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_16c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_16d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_16e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_1a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_1b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_1c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_1d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_1e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_2a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_2b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_2c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_2d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_2e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_4a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_4b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_4c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_4d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_4e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_8a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_8b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_8c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_8d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcallofreqagcgain_lut_8e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_16a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_16b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_16c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_16d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_16e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_1a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_1b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_1c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_1d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_1e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_2a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_2b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_2c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_2d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_2e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_4a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_4b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_4c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_4d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_4e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_8a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_8b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_8c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_8d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcalmidbandzero_lut_8e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcals_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCALS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcals_offset_datasummer0_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcals_offset_datasummer0_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcals_offset_datasummer1_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcals_offset_datasummer1_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcals_offset_edgesummer0_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcals_offset_edgesummer0_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcals_offset_edgesummer1_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcals_offset_edgesummer1_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcdr_force_ltr_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCDR_FORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqcdr_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCDR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqctl_clear_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCTL_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqctl_fg_run_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCTL_FG_RUN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqctlelut_hifreqagcres_ovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCTLELUT_HIFREQAGCRES_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqctlelut_hifreqvgagain_ovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCTLELUT_HIFREQVGAGAIN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqctls_oddeven_tapgain_sel_inv_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCTLS_ODDEVEN_TAPGAIN_SEL_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqctls_static_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQCTLS_STATIC_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqdat_aux_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQDAT_AUX_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqdat_edge_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQDAT_EDGE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqdatactl_auxswap_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqdatactl_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQDATACTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqdatarate_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQDATARATE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqdatarate_rx_rate_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqdfeyadj_agingl2r_delay_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqdfeyadj_agingl2r_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQDFEYADJ_AGINGL2R_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqedgeadj_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEDGEADJ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqedgeadj_yadjust_edge0lo_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqedgeadj_yadjust_edge1lo_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm2flx_ehm_done_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHM2FLX_EHM_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm2flx_ehm_done_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHM2FLX_EHM_DONE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm2flx_ehm_err_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHM2FLX_EHM_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm2flx_ehm_err_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHM2FLX_EHM_ERR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm2flx_ehm_fom_locovr_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHM2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_data_extshift_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHM_DATA_EXTSHIFT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_distance_th_50p_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_distance_th_rate_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_err_mask_vf00_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_err_mask_vf01_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_event_rate_vf00_attr == 32'd67108864
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_event_rate_vf01_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_general_in_vf00_attr == 32'd5505024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_general_in_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_lms_th_50p_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_lms_th_rate_attr == 20'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_mask_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_no_change_th_50p_attr == 12'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_no_change_th_rate_attr == 12'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_reflections_num_50p_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_reflections_num_rate_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_slicer_swap_cb_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHM_SLICER_SWAP_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_sym_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_sym_dly_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_tap_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_test_aux_slicer_val_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehm_test_hits_th_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjaux_ehm_yadjust_aux0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjaux_ehm_yadjust_aux1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjaux_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJAUX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjauxen_ehm_aux_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJAUXEN_EHM_AUX_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjauxen_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJAUXEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjauxltch_aux_yadj_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJAUXLTCH_AUX_YADJ_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjauxltch_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJAUXLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdata_ehm_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdata_ehm_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdata_ehm_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdata_ehm_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdata_ehm_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdata_ehm_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdata_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdataen_ehm_data_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJDATAEN_EHM_DATA_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdataen_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJDATAEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdataltch_data_yadj_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJDATALTCH_DATA_YADJ_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqehmyadjdataltch_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQEHMYADJDATALTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2ehm_ehm_run_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2EHM_EHM_RUN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2ehm_ehm_run_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2EHM_EHM_RUN_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2lms_coarse_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2LMS_COARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2lms_ctrl_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2LMS_CTRL_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2lms_dfecore_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2LMS_DFECORE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2lms_force_evrefupd_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2LMS_FORCE_EVREFUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2lms_freeze_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2LMS_FREEZE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2lms_incr_decr_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2LMS_INCR_DECR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2lms_mu_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2LMS_MU_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2lms_rst_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2LMS_RST_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2ofc_ofc_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2OFC_OFC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx2ofc_ofc_en_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX2OFC_OFC_EN_OVRDEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx_pcs_rxeq_clr_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX_PCS_RXEQ_CLR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx_pcs_rxeq_start_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX_PCS_RXEQ_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx_pcs_rxeq_static_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLX_PCS_RXEQ_STATIC_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx_rxrate2pcie1_map_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx_rxrate2pcie2_map_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx_rxrate2pcie3_map_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflx_rxrate2pcie4_map_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxehmdata_ehm_data_slc_sel_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXEHMDATA_EHM_DATA_SLC_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxehmdata_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXEHMDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxfsm_generalpurpose_reg_in_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxfsm_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXFSM_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxfsm_pause_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXFSM_PAUSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxfsm_state_obs_hold_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXFSM_STATE_OBS_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxfsm_state_obs_sel_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXFSM_STATE_OBS_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxltr_force_ltr_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXLTR_FORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxltr_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXLTR_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxpcsrxeyediag_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXPCSRXEYEDIAG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxpcsrxeyediag_start_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXPCSRXEYEDIAG_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqflxsigdet_sel_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFLXSIGDET_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqfsm2ofc_ofc_cal_req_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFSM2OFC_OFC_CAL_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqfsm2ofc_ofc_cal_req_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQFSM2OFC_OFC_CAL_REQ_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_16a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_16b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_16c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_16d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_16e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_1a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_1b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_1c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_1d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_1e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_2a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_2b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_2c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_2d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_2e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_4a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_4b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_4c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_4d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_4e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_8a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_8b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_8c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_8d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqhf2cap_lut_8e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_done_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmax_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmax_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_SATMAX_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmax_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmax_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmax_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_SATMAX_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmax_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_SATMAX_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmax_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_SATMAX_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmin_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmin_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_SATMIN_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmin_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmin_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmin_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_SATMIN_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmin_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_SATMIN_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_satmin_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_SATMIN_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_stable_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_stable_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_STABLE_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_stable_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_stable_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_stable_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_STABLE_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_stable_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_STABLE_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlms2flx_stable_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMS2FLX_STABLE_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsupd_chng_ack_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSUPD_CHNG_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsupd_chng_req_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSUPD_CHNG_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsupd_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSUPD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjaux_lms_vref0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjaux_lms_vref1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjaux_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJAUX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjauxen_lms_aux_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJAUXEN_LMS_AUX_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjauxen_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJAUXEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjauxltch_lms_aux_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJAUXLTCH_LMS_AUX_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjauxltch_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJAUXLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdata_lms_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdata_lms_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdata_lms_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdata_lms_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdata_lms_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdata_lms_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdata_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdataen_lms_data_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJDATAEN_LMS_DATA_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdataen_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJDATAEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdataltch_lms_data_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJDATALTCH_LMS_DATA_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjdataltch_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJDATALTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjedge_lms_yadjust_edge0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjedge_lms_yadjust_edge1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjedge_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJEDGE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjedgeen_lms_edge_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJEDGEEN_LMS_EDGE_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjedgeen_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJEDGEEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjedgeltch_lms_edge_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJEDGELTCH_LMS_EDGE_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqlmsyadjedgeltch_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLMSYADJEDGELTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqltch_dfe_aux_yadj_b_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLTCH_DFE_AUX_YADJ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqltch_dfe_b_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLTCH_DFE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqltch_dfe_data_yadj_b_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLTCH_DFE_DATA_YADJ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqltch_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqltchc_auxswap_b_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLTCHC_AUXSWAP_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqltchc_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQLTCHC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofc2flx_ofc_cal_done_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQOFC2FLX_OFC_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofc2flx_ofc_cal_done_ovrden_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQOFC2FLX_OFC_CAL_DONE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_ctle_rxinpprobemuxen_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_ctle_rxstg1_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_ctle_rxstg1probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_ctle_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_ctle_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_ctle_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_ctle_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_summer_rxinpprobemuxen_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_summer_rxstg1_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_summer_rxstg1probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_summer_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_summer_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_summer_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_summer_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_time_h_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_adapt_time_l_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_ctle_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_ctle_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_ctle_rxstg1probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_ctle_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_ctle_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_ctle_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_ctle_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_summer_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_summer_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_summer_rxstg1probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_summer_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_summer_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_summer_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_summer_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_cal_time_l_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_compsel_ctle_st1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_compsel_ctle_st2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_compsel_ctle_st3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_compsel_idle_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_compsel_sa_d0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_compsel_sa_d1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_compsel_sa_e0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_compsel_sa_e1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_invert_comp_fb_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_lpexitcal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_lpexitcal_time_l_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_adapt_en_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_adapt_thr_sel_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_cal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_cal_thr_sel_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_data_disp_sticky_clr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQOFCCFG_OFC_DATA_DISP_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_disparity_disable_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQOFCCFG_OFC_DISPARITY_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_disparity_leak_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_disparity_thr_sel_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_lpexitcal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_lpf_bypass_en_cb_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQOFCCFG_OFC_LPF_BYPASS_EN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ofc_ratechangecal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_pre_timer_setting_pow2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ratechangecal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_ratechangecal_time_l_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_rxinpprobemuxen_idle_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_rxstg1_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_rxstg1probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_rxstg2_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_rxstg2probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_rxstg3_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqofccfg_rxstg3probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqout_init_restore_avail_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQOUT_INIT_RESTORE_AVAIL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqprecal_code_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqprecal_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQPRECAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_hf1deq_dir_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_BOOSTLUT_HF1DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_hf2deq_dir_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_BOOSTLUT_HF2DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_hf2reszero_dir_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_BOOSTLUT_HF2RESZERO_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_hf3deq_dir_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_BOOSTLUT_HF3DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_idx_hf1deq_vf00_attr == 32'd599186
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_idx_hf1deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_idx_hf2deq_vf00_attr == 32'd1198372
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_idx_hf2deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_idx_hf2reszero_vf00_attr == 32'd4290772992
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_idx_hf2reszero_vf01_attr == 21'd2097151
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_idx_hf3deq_vf00_attr == 32'd2396744
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_idx_hf3deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_init_hf1deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_init_hf2deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_init_hf2reszero_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_boostlut_init_hf3deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_cal_hifreqagcres_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_cal_hifreqvgagain_attr == 7'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_cal_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_cal_yadjust_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_biasboost_dir_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_GAINLUT_BIASBOOST_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_hf1resdcgain_dir_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_GAINLUT_HF1RESDCGAIN_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_hf3resdcgain_dir_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_GAINLUT_HF3RESDCGAIN_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_biasboost_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_biasboost_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_biasboost_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf00_attr == 32'd2863311530
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf01_attr == 32'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf00_attr == 32'd1431655764
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf01_attr == 32'd1431655765
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_lbbiasboost_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_lbbiasboost_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_idx_lbbiasboost_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_init_biasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_init_hf1resdcgain_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_init_hf3resdcgain_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_init_lbbiasboost_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_gainlut_lbbiasboost_dir_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_GAINLUT_LBBIASBOOST_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_latch_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref0_initval_attr == 9'd61
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref1_initval_attr == 9'd191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref2_initval_attr == 9'd321
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref3_initval_attr == 9'd451
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_decr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_AUXVREF_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_frac_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_AUXVREF_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_frac_reset_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_incr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_AUXVREF_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_incr_decr_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_pam4adj_swizzle_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_AUXVREF_PAM4ADJ_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_AUXVREF_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_pol_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_single_step_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_AUXVREF_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_stable_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_AUXVREF_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_AUXVREF_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_targ_0_hi_attr == 9'd149
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_auxvref_targ_0_lo_attr == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_auxvref_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_auxvref_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_dfe_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_dfe_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_edge_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_edge_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_edgevref_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_edgevref_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_iqalign_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_iqalign_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_level_vga_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_vga_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_block_vote_vga_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_blockcount_fast_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_BLOCKCOUNT_FAST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_coarse_detect_clear_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_COARSE_DETECT_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_coarse_detect_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_COARSE_DETECT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_continuous_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_CONTINUOUS_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_datastats_incr_decr_swizzle_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_DATASTATS_INCR_DECR_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_datastats_pol_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_DATASTATS_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_datastats_thres_attr == 16'd1023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe1_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe2_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe3_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe4p_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_core_sel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_decr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_DFE_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_frac_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_DFE_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_frac_reset_mask_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_incr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_DFE_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_incr_decr_mask_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_inner_lvl_filter_en_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_DFE_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_pol_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_single_step_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_DFE_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_stable_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_DFE_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_DFE_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_targtap1_attr == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_targtap2_attr == 7'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_targtap3_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_dfe_targtap4_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_decr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGE_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_frac_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGE_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_frac_reset_mask_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_incr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGE_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_incr_decr_mask_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGE_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_pol_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_single_step_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGE_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_stable_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGE_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edge_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGE_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_decr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGEVREF_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_frac_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGEVREF_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGEVREF_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_incr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGEVREF_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_initval_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGEVREF_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_pol_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGEVREF_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_single_step_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGEVREF_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_stable_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGEVREF_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_edgevref_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_EDGEVREF_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_fast_blockcnt_attr == 16'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_filter_mode_auxvref_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_filter_mode_dfe_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_filter_mode_edge_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_filter_mode_edgevref_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_filter_mode_iqalign_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_filter_mode_vga_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_freeze_auxvrefupd_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_freeze_dfeupd_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_freeze_edgeupd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_freeze_edgevrefupd_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_FREEZE_EDGEVREFUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_freeze_forcebg_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_FREEZE_FORCEBG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_freeze_hifreqagcupd_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_FREEZE_HIFREQAGCUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_freeze_iqalignupd_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_FREEZE_IQALIGNUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_freeze_lofreqagcupd_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_FREEZE_LOFREQAGCUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_freeze_vgaupd_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_FREEZE_VGAUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_gated_update_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_GATED_UPDATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_accum_count_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_accum_level_en_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_decr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_HIFREQAGC_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_frac_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_HIFREQAGC_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_HIFREQAGC_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_incr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_HIFREQAGC_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_n1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_n2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_n3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_n4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_n5_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_HIFREQAGC_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_pol_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_HIFREQAGC_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_single_step_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_HIFREQAGC_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_stable_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_HIFREQAGC_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_hifreqagc_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_HIFREQAGC_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_init_adapt_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_INIT_ADAPT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_decr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_IQALIGN_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_frac_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_IQALIGN_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_IQALIGN_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_incr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_IQALIGN_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_IQALIGN_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_pol_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_IQALIGN_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_single_step_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_IQALIGN_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_stable_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_IQALIGN_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_IQALIGN_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_iqalign_targ_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_itercount_attr == 10'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_latch_delay_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_latch_prepost_delay_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_decr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOFREQAGC_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_frac_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOFREQAGC_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOFREQAGC_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_incr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOFREQAGC_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOFREQAGC_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_pol_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOFREQAGC_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_single_step_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOFREQAGC_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_stable_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOFREQAGC_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_lofreqagc_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOFREQAGC_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_logain_auxvref_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOGAIN_AUXVREF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_logain_dfe_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_logain_edge_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_logain_edgevref_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOGAIN_EDGEVREF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_logain_hifreqagc_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOGAIN_HIFREQAGC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_logain_iqalign_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOGAIN_IQALIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_logain_lofreqagc_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOGAIN_LOFREQAGC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_logain_vga_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_LOGAIN_VGA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_auxvref_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_dfe1_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_dfe23_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_dfe4p_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_edge2_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_edge3_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_edge4_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_edgevref_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_hifreqagc_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_iqalign_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_lofreqagc_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_mu_vga_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_nrz_to_pam4_mode_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_NRZ_TO_PAM4_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_slow_blockcnt_attr == 16'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_start_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_tsettle_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_accum_count_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_accum_level_en_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_decr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_frac_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_incr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_mode_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_pol_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_single_step_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_stable_reset_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_vga_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_VGA_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lms_yadjdata_mid_clamp_zero_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LMS_YADJDATA_MID_CLAMP_ZERO_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_lofreqagcgain_sel_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_LOFREQAGCGAIN_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_caldfedatatap1gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_caldfedatatap2gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_caldfedatatap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_caldfedatatap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_caldfeedgetap2gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_caldfeedgetap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_caldfeedgetap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal0_lofreqagcgain_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_caldfedatatap1gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal1_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_caldfedatatap1gain_attr == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal2_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_caldfedatatap1gain_attr == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal3_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal4_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal5_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal6_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_precal7_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_shift_auxshft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_shift_capture_trigger_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_SHIFT_CAPTURE_TRIGGER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_shift_clear_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_SHIFT_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_shift_dat_bitsel_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_SHIFT_DAT_BITSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_shift_datashft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_shift_edgeshft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_shift_edgeshft_nrz8b10b_pam16b20b_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_shift_polarity_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSET_SHIFT_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap10gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap11gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap12gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap13gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap14gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap15gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap16gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap1gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap2gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap5gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap6gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap7gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap8gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfedatatap9gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfeedgetap2gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfeedgetap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_caldfeedgetap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_hifreqvgagain_attr == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_static_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_auxvref0_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_auxvref1_attr == 9'd223
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_auxvref2_attr == 9'd339
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_auxvref3_attr == 9'd456
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_caldfedatatap1gain_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_caldfeedgetap2gain_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_calhifreqagcres_attr == 6'd52
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_callofreqagcgain_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_edgevref_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_hifreqvgagain_attr == 7'd77
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmax_iqalign_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_auxvref0_attr == 9'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_auxvref1_attr == 9'd173
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_auxvref2_attr == 9'd289
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_auxvref3_attr == 9'd356
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_caldfedatatap1gain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_caldfeedgetap2gain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_calhifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_callofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_edgevref_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqset_swpmin_iqalign_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqsetnrztopam4_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSETNRZTOPAM4_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqsetnrztopam4_switch_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSETNRZTOPAM4_SWITCH_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqsigdet_pause_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSIGDET_PAUSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqspare0_attr == 32'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqspare1_attr == 32'd15871
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqspare2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqsync2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSYNC2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqsync2flx_rxdatapath_ready_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQSYNC2FLX_RXDATAPATH_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqtapctrl_data_tap13to16_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQTAPCTRL_DATA_TAP13TO16_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqtapctrl_data_tap1to4_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQTAPCTRL_DATA_TAP1TO4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqtapctrl_data_tap5to8_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQTAPCTRL_DATA_TAP5TO8_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqtapctrl_data_tap9to12_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQTAPCTRL_DATA_TAP9TO12_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqtapctrl_edge_tap_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQTAPCTRL_EDGE_TAP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqtapctrl_tap1to4gain_dbl_res_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQTAPCTRL_TAP1TO4GAIN_DBL_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqtapctrl_tap5to16gain_dbl_res_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQTAPCTRL_TAP5TO16GAIN_DBL_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvalc_hifreqagcbiasadjust_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvalc_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQVALC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvalc_midbandzero_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvalcl_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQVALCL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvalcl_lofreqagcgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap01gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap02gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap03gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap04gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap05gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap06gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap07gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap08gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap09gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap10gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap11gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap12gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap13gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap14gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap15gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_caldfedatatap16gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvald_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQVALD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvale_caldfeedgetap02gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvale_caldfeedgetap03gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvale_caldfeedgetap04gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxeqvale_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXEQVALE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1cal_clear_mask_attr == 13'd8184
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_aux0_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_aux1_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_d0_bot_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_d0_mid_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_d0_top_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_d1_bot_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_d1_mid_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_d1_top_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_e0_lo_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg1calorder_smplroffset_e1_lo_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2cal_clear_mask_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_aux0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_aux1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_d0_bot_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_d0_mid_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_d0_top_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_d1_bot_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_d1_mid_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_d1_top_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_e0_lo_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfg2calorder_smplroffset_e1_lo_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfgcal_calfsmmeas_dlycount_attr == 10'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfgcal_fsmmaxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfgcal_lpfax_coarse_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxfgcal_lpfax_fine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxhifreqagc_inputcmadjust_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxhifreqagc_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXHIFREQAGC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcal_clear_mask_attr == 13'd8191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_ctlecmnmode_stg1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_ctlecmnmode_stg2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_ctlecmnmode_stg3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_aux0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_aux1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_d0_bot_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_d0_mid_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_d0_top_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_d1_bot_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_d1_mid_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_d1_top_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_e0_lo_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxinitcalorder_smplroffset_e1_lo_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmargin_flx_jit_offset_shift_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmargin_jit_disable_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmargin_jit_enable_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmargin_jit_offset_shift_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmargin_jit_setup_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmargin_volt_comp_mask_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmargin_volt_forcel2d_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXMARGIN_VOLT_FORCEL2D_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmargin_volt_offset_shift_d0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmargin_volt_offset_shift_d1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmarginin_direction_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXMARGININ_DIRECTION_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmarginin_flx_jit_offset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmarginin_locovren_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXMARGININ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmarginin_mode_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXMARGININ_MODE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmarginin_offset_change_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXMARGININ_OFFSET_CHANGE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmarginin_offset_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxmarginin_start_locovr_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXMARGININ_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxsum_cm_vref_attr == 9'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxsum_summer_cmfb_en_attr == SERDES_IP_LANE_RXEQ_L1_CFG_RXSUM_SUMMER_CMFB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l1_cfg_rxsum_summer_cmfb_ibias_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_dfeyadj_aging_cdrlock2data_loc_ov_attr == SERDES_IP_LANE_RXEQ_L2_CFG_DFEYADJ_AGING_CDRLOCK2DATA_LOC_OV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_dfeyadj_aging_cdrlock2data_loc_ov_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_DFEYADJ_AGING_CDRLOCK2DATA_LOC_OV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_dfeyadj_aging_div_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_dfeyadj_aging_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_DFEYADJ_AGING_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxagc_ctlecomp_filterbypass_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXAGC_CTLECOMP_FILTERBYPASS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxagc_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXAGC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxbgcal_calfsmmeas_dlycount_attr == 10'd392
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxbgcal_clear_mask_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxbgcal_fsmmaxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxbgcal_lpfax_coarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxbgcal_lpfax_fine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxbgcalorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxbgcalorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxbgcalorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_calbiasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_calbiasboost_use_lut_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_CALBIASBOOST_USE_LUT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_callbbiasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_callbbiasboost_use_lut_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_CALLBBIASBOOST_USE_LUT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlecomp_filterbypass_smplrcal_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_CTLECOMP_FILTERBYPASS_SMPLRCAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg1_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg2_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg3_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctleinput_probe_mux_smplrcal_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg1_probe_mux_en_smplrcal_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg1_state_en_smplrcal_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg1_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg1_state_en_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg1_state_en_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg1_use_stg2code_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_CTLESTG1_USE_STG2CODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg2_probe_mux_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg2_state_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg2_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg2_state_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg2_state_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg3_probe_mux_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg3_state_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg3_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg3_state_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_ctlestg3_state_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_hifreqagc_n5targin_sel_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_HIFREQAGC_N5TARGIN_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_inputcmadjust_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_inputcmadjust_stg1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_inputcmadjust_stg2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_inputcmadjust_stg3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_sdimode_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCAL_SDIMODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_smplroffset_aux0_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_smplroffset_aux1_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_smplroffset_d0_bot_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_smplroffset_d0_mid_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_smplroffset_d0_top_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_smplroffset_d1_bot_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_smplroffset_d1_mid_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_smplroffset_d1_top_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_tfrtrim_outen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_tfrtrim_outen_tfrcal_stg1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_tfrtrim_outen_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcal_tfrtrim_outen_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalalign_iqclk_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalalign_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALALIGN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctl_cal_abort_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALCTL_CAL_ABORT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctl_cal_type_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctl_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALCTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctl_post_delay_pow2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctl_pre_delay_pow2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecalctrl_input_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecalctrl_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALCTLECALCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecalctrl_stg1_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecalctrl_stg1_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecalctrl_stg2_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecalctrl_stg2_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecalctrl_stg3_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecalctrl_stg3_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecompoffset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecompoffset_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALCTLECOMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecompoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALCTLECOMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecompoffsetfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALCTLECOMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalctlecompoffsetfsmout_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaldutybkgnd_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALDUTYBKGND_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaldutybkgnd_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALDUTYBKGND_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_biasboost_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_hf1deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_hf1resdcgain_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_hf2cap_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_hf2deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_hf2reszero_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_hf3deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_hf3resdcgain_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_hf4deq_gray_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaleq_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALEQ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_ctlecmnmode_stg1_finish_side_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALFSM_CTLECMNMODE_STG1_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_ctlecmnmode_stg1_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_ctlecmnmode_stg2_finish_side_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALFSM_CTLECMNMODE_STG2_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_ctlecmnmode_stg2_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_ctlecmnmode_stg3_finish_side_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALFSM_CTLECMNMODE_STG3_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_ctlecmnmode_stg3_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_runcount_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_smplroffset_finish_side_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALFSM_SMPLROFFSET_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsm_smplroffset_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsmmeas_ctlecmnmode_stg1_invert_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALFSMMEAS_CTLECMNMODE_STG1_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsmmeas_ctlecmnmode_stg2_invert_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALFSMMEAS_CTLECMNMODE_STG2_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsmmeas_ctlecmnmode_stg3_invert_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALFSMMEAS_CTLECMNMODE_STG3_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalfsmmeas_smplroffset_invert_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALFSMMEAS_SMPLROFFSET_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_ctlecmnmode_stg1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_ctlecmnmode_stg2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_ctlecmnmode_stg3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_aux0_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_aux1_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_d0_bot_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_d0_mid_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_d0_top_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_d1_bot_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_d1_mid_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_d1_top_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_e0_lo_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalinit_smplroffset_e1_lo_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeas_pow2count_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasin_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasin_req_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASIN_REQ_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasin_req_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASIN_REQ_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasin_req_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASIN_REQ_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasout_ack_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASOUT_ACK_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasout_ack_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASOUT_ACK_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasout_ack_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASOUT_ACK_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasout_avg_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASOUT_AVG_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasout_avg_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASOUT_AVG_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasout_avg_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASOUT_AVG_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalmeasout_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaloffsetfsmout_auxdatacomp_offset_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALOFFSETFSMOUT_AUXDATACOMP_OFFSET_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaloffsetfsmout_boost_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALOFFSETFSMOUT_BOOST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaloffsetfsmout_edgecomp_offset_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALOFFSETFSMOUT_EDGECOMP_OFFSET_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcaloffsetfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalset_cal_clear_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalset_cal_mode_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALSET_CAL_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalset_cal_req_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALSET_CAL_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalset_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalstat_cal_ack_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALSTAT_CAL_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalstat_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalsummerfsmout_comp_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALSUMMERFSMOUT_COMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcalsummerfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCALSUMMERFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcdrphd_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCDRPHD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxcdrphd_override_ignore_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCDRPHD_OVERRIDE_IGNORE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_caloffset_range_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_calstg1offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_calstg1offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_calstg2offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_calstg2offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_calstg3offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_calstg3offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_dccouple_sigpath_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCTLE_DCCOUPLE_SIGPATH_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_lbbiasboost_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCTLE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_stg1tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_stg2tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_stg3tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_tfrtrim_outmem_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCTLE_TFRTRIM_OUTMEM_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctle_tfrtrim_outpen_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCTLE_TFRTRIM_OUTPEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctledc_dccouple_tgate_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCTLEDC_DCCOUPLE_TGATE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxctledc_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXCTLEDC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxdfe_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXDFE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxdfe_tapgain_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxdfepam_enable_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXDFEPAM_ENABLE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxdfepam_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXDFEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxdpifjit_enb_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXDPIFJIT_ENB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxdpifjit_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXDPIFJIT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxdpifjit_offset_locovr_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqadj_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQADJ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqadj_yadjust_aux0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqadj_yadjust_aux1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqadj_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqadj_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqadj_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqadj_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqadj_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqadj_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqauxxor_amux_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqauxxor_dmux_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqauxxor_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQAUXXOR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcal2flx_pstate_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCAL2FLX_PSTATE_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcal2flx_rate_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCAL2FLX_RATE_MASK_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_16a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_16b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_16c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_16d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_16e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_1a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_1b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_1c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_1d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_1e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_2a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_2b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_2c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_2d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_2e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_4a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_4b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_4c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_4d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_4e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_8a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_8b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_8c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_8d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalhfagcbiasadj_lut_8e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_16a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_16b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_16c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_16d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_16e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_1a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_1b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_1c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_1d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_1e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_2a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_2b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_2c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_2d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_2e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_4a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_4b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_4c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_4d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_4e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_8a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_8b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_8c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_8d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcallofreqagcgain_lut_8e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_16a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_16b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_16c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_16d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_16e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_1a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_1b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_1c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_1d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_1e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_2a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_2b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_2c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_2d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_2e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_4a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_4b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_4c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_4d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_4e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_8a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_8b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_8c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_8d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcalmidbandzero_lut_8e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcals_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCALS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcals_offset_datasummer0_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcals_offset_datasummer0_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcals_offset_datasummer1_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcals_offset_datasummer1_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcals_offset_edgesummer0_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcals_offset_edgesummer0_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcals_offset_edgesummer1_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcals_offset_edgesummer1_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcdr_force_ltr_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCDR_FORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqcdr_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCDR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqctl_clear_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCTL_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqctl_fg_run_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCTL_FG_RUN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqctlelut_hifreqagcres_ovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCTLELUT_HIFREQAGCRES_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqctlelut_hifreqvgagain_ovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCTLELUT_HIFREQVGAGAIN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqctls_oddeven_tapgain_sel_inv_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCTLS_ODDEVEN_TAPGAIN_SEL_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqctls_static_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQCTLS_STATIC_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqdat_aux_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQDAT_AUX_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqdat_edge_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQDAT_EDGE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqdatactl_auxswap_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqdatactl_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQDATACTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqdatarate_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQDATARATE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqdatarate_rx_rate_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqdfeyadj_agingl2r_delay_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqdfeyadj_agingl2r_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQDFEYADJ_AGINGL2R_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqedgeadj_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEDGEADJ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqedgeadj_yadjust_edge0lo_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqedgeadj_yadjust_edge1lo_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm2flx_ehm_done_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHM2FLX_EHM_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm2flx_ehm_done_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHM2FLX_EHM_DONE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm2flx_ehm_err_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHM2FLX_EHM_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm2flx_ehm_err_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHM2FLX_EHM_ERR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm2flx_ehm_fom_locovr_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHM2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_data_extshift_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHM_DATA_EXTSHIFT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_distance_th_50p_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_distance_th_rate_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_err_mask_vf00_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_err_mask_vf01_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_event_rate_vf00_attr == 32'd67108864
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_event_rate_vf01_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_general_in_vf00_attr == 32'd5505024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_general_in_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_lms_th_50p_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_lms_th_rate_attr == 20'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_mask_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_no_change_th_50p_attr == 12'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_no_change_th_rate_attr == 12'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_reflections_num_50p_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_reflections_num_rate_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_slicer_swap_cb_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHM_SLICER_SWAP_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_sym_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_sym_dly_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_tap_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_test_aux_slicer_val_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehm_test_hits_th_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjaux_ehm_yadjust_aux0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjaux_ehm_yadjust_aux1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjaux_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJAUX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjauxen_ehm_aux_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJAUXEN_EHM_AUX_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjauxen_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJAUXEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjauxltch_aux_yadj_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJAUXLTCH_AUX_YADJ_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjauxltch_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJAUXLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdata_ehm_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdata_ehm_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdata_ehm_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdata_ehm_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdata_ehm_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdata_ehm_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdata_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdataen_ehm_data_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJDATAEN_EHM_DATA_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdataen_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJDATAEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdataltch_data_yadj_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJDATALTCH_DATA_YADJ_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqehmyadjdataltch_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQEHMYADJDATALTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2ehm_ehm_run_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2EHM_EHM_RUN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2ehm_ehm_run_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2EHM_EHM_RUN_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2lms_coarse_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2LMS_COARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2lms_ctrl_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2LMS_CTRL_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2lms_dfecore_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2LMS_DFECORE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2lms_force_evrefupd_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2LMS_FORCE_EVREFUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2lms_freeze_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2LMS_FREEZE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2lms_incr_decr_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2LMS_INCR_DECR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2lms_mu_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2LMS_MU_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2lms_rst_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2LMS_RST_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2ofc_ofc_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2OFC_OFC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx2ofc_ofc_en_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX2OFC_OFC_EN_OVRDEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx_pcs_rxeq_clr_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX_PCS_RXEQ_CLR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx_pcs_rxeq_start_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX_PCS_RXEQ_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx_pcs_rxeq_static_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLX_PCS_RXEQ_STATIC_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx_rxrate2pcie1_map_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx_rxrate2pcie2_map_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx_rxrate2pcie3_map_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflx_rxrate2pcie4_map_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxehmdata_ehm_data_slc_sel_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXEHMDATA_EHM_DATA_SLC_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxehmdata_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXEHMDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxfsm_generalpurpose_reg_in_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxfsm_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXFSM_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxfsm_pause_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXFSM_PAUSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxfsm_state_obs_hold_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXFSM_STATE_OBS_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxfsm_state_obs_sel_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXFSM_STATE_OBS_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxltr_force_ltr_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXLTR_FORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxltr_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXLTR_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxpcsrxeyediag_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXPCSRXEYEDIAG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxpcsrxeyediag_start_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXPCSRXEYEDIAG_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqflxsigdet_sel_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFLXSIGDET_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqfsm2ofc_ofc_cal_req_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFSM2OFC_OFC_CAL_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqfsm2ofc_ofc_cal_req_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQFSM2OFC_OFC_CAL_REQ_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_16a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_16b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_16c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_16d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_16e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_1a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_1b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_1c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_1d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_1e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_2a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_2b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_2c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_2d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_2e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_4a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_4b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_4c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_4d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_4e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_8a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_8b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_8c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_8d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqhf2cap_lut_8e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_done_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmax_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmax_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_SATMAX_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmax_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmax_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmax_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_SATMAX_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmax_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_SATMAX_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmax_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_SATMAX_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmin_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmin_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_SATMIN_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmin_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmin_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmin_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_SATMIN_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmin_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_SATMIN_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_satmin_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_SATMIN_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_stable_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_stable_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_STABLE_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_stable_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_stable_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_stable_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_STABLE_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_stable_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_STABLE_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlms2flx_stable_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMS2FLX_STABLE_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsupd_chng_ack_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSUPD_CHNG_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsupd_chng_req_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSUPD_CHNG_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsupd_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSUPD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjaux_lms_vref0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjaux_lms_vref1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjaux_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJAUX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjauxen_lms_aux_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJAUXEN_LMS_AUX_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjauxen_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJAUXEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjauxltch_lms_aux_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJAUXLTCH_LMS_AUX_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjauxltch_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJAUXLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdata_lms_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdata_lms_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdata_lms_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdata_lms_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdata_lms_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdata_lms_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdata_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdataen_lms_data_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJDATAEN_LMS_DATA_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdataen_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJDATAEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdataltch_lms_data_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJDATALTCH_LMS_DATA_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjdataltch_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJDATALTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjedge_lms_yadjust_edge0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjedge_lms_yadjust_edge1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjedge_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJEDGE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjedgeen_lms_edge_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJEDGEEN_LMS_EDGE_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjedgeen_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJEDGEEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjedgeltch_lms_edge_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJEDGELTCH_LMS_EDGE_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqlmsyadjedgeltch_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLMSYADJEDGELTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqltch_dfe_aux_yadj_b_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLTCH_DFE_AUX_YADJ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqltch_dfe_b_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLTCH_DFE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqltch_dfe_data_yadj_b_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLTCH_DFE_DATA_YADJ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqltch_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqltchc_auxswap_b_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLTCHC_AUXSWAP_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqltchc_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQLTCHC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofc2flx_ofc_cal_done_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQOFC2FLX_OFC_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofc2flx_ofc_cal_done_ovrden_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQOFC2FLX_OFC_CAL_DONE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_ctle_rxinpprobemuxen_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_ctle_rxstg1_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_ctle_rxstg1probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_ctle_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_ctle_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_ctle_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_ctle_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_summer_rxinpprobemuxen_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_summer_rxstg1_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_summer_rxstg1probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_summer_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_summer_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_summer_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_summer_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_time_h_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_adapt_time_l_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_ctle_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_ctle_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_ctle_rxstg1probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_ctle_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_ctle_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_ctle_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_ctle_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_summer_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_summer_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_summer_rxstg1probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_summer_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_summer_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_summer_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_summer_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_cal_time_l_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_compsel_ctle_st1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_compsel_ctle_st2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_compsel_ctle_st3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_compsel_idle_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_compsel_sa_d0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_compsel_sa_d1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_compsel_sa_e0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_compsel_sa_e1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_invert_comp_fb_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_lpexitcal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_lpexitcal_time_l_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_adapt_en_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_adapt_thr_sel_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_cal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_cal_thr_sel_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_data_disp_sticky_clr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQOFCCFG_OFC_DATA_DISP_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_disparity_disable_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQOFCCFG_OFC_DISPARITY_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_disparity_leak_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_disparity_thr_sel_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_lpexitcal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_lpf_bypass_en_cb_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQOFCCFG_OFC_LPF_BYPASS_EN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ofc_ratechangecal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_pre_timer_setting_pow2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ratechangecal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_ratechangecal_time_l_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_rxinpprobemuxen_idle_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_rxstg1_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_rxstg1probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_rxstg2_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_rxstg2probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_rxstg3_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqofccfg_rxstg3probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqout_init_restore_avail_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQOUT_INIT_RESTORE_AVAIL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqprecal_code_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqprecal_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQPRECAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_hf1deq_dir_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_BOOSTLUT_HF1DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_hf2deq_dir_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_BOOSTLUT_HF2DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_hf2reszero_dir_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_BOOSTLUT_HF2RESZERO_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_hf3deq_dir_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_BOOSTLUT_HF3DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_idx_hf1deq_vf00_attr == 32'd599186
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_idx_hf1deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_idx_hf2deq_vf00_attr == 32'd1198372
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_idx_hf2deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_idx_hf2reszero_vf00_attr == 32'd4290772992
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_idx_hf2reszero_vf01_attr == 21'd2097151
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_idx_hf3deq_vf00_attr == 32'd2396744
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_idx_hf3deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_init_hf1deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_init_hf2deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_init_hf2reszero_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_boostlut_init_hf3deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_cal_hifreqagcres_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_cal_hifreqvgagain_attr == 7'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_cal_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_cal_yadjust_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_biasboost_dir_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_GAINLUT_BIASBOOST_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_hf1resdcgain_dir_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_GAINLUT_HF1RESDCGAIN_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_hf3resdcgain_dir_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_GAINLUT_HF3RESDCGAIN_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_biasboost_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_biasboost_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_biasboost_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf00_attr == 32'd2863311530
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf01_attr == 32'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf00_attr == 32'd1431655764
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf01_attr == 32'd1431655765
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_lbbiasboost_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_lbbiasboost_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_idx_lbbiasboost_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_init_biasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_init_hf1resdcgain_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_init_hf3resdcgain_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_init_lbbiasboost_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_gainlut_lbbiasboost_dir_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_GAINLUT_LBBIASBOOST_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_latch_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref0_initval_attr == 9'd61
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref1_initval_attr == 9'd191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref2_initval_attr == 9'd321
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref3_initval_attr == 9'd451
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_decr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_AUXVREF_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_frac_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_AUXVREF_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_frac_reset_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_incr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_AUXVREF_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_incr_decr_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_pam4adj_swizzle_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_AUXVREF_PAM4ADJ_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_AUXVREF_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_pol_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_single_step_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_AUXVREF_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_stable_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_AUXVREF_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_AUXVREF_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_targ_0_hi_attr == 9'd149
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_auxvref_targ_0_lo_attr == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_auxvref_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_auxvref_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_dfe_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_dfe_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_edge_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_edge_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_edgevref_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_edgevref_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_iqalign_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_iqalign_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_level_vga_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_vga_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_block_vote_vga_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_blockcount_fast_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_BLOCKCOUNT_FAST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_coarse_detect_clear_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_COARSE_DETECT_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_coarse_detect_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_COARSE_DETECT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_continuous_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_CONTINUOUS_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_datastats_incr_decr_swizzle_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_DATASTATS_INCR_DECR_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_datastats_pol_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_DATASTATS_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_datastats_thres_attr == 16'd1023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe1_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe2_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe3_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe4p_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_core_sel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_decr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_DFE_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_frac_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_DFE_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_frac_reset_mask_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_incr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_DFE_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_incr_decr_mask_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_inner_lvl_filter_en_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_DFE_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_pol_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_single_step_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_DFE_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_stable_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_DFE_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_DFE_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_targtap1_attr == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_targtap2_attr == 7'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_targtap3_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_dfe_targtap4_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_decr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGE_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_frac_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGE_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_frac_reset_mask_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_incr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGE_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_incr_decr_mask_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGE_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_pol_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_single_step_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGE_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_stable_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGE_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edge_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGE_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_decr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGEVREF_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_frac_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGEVREF_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGEVREF_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_incr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGEVREF_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_initval_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGEVREF_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_pol_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGEVREF_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_single_step_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGEVREF_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_stable_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGEVREF_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_edgevref_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_EDGEVREF_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_fast_blockcnt_attr == 16'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_filter_mode_auxvref_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_filter_mode_dfe_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_filter_mode_edge_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_filter_mode_edgevref_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_filter_mode_iqalign_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_filter_mode_vga_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_freeze_auxvrefupd_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_freeze_dfeupd_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_freeze_edgeupd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_freeze_edgevrefupd_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_FREEZE_EDGEVREFUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_freeze_forcebg_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_FREEZE_FORCEBG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_freeze_hifreqagcupd_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_FREEZE_HIFREQAGCUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_freeze_iqalignupd_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_FREEZE_IQALIGNUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_freeze_lofreqagcupd_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_FREEZE_LOFREQAGCUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_freeze_vgaupd_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_FREEZE_VGAUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_gated_update_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_GATED_UPDATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_accum_count_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_accum_level_en_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_decr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_HIFREQAGC_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_frac_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_HIFREQAGC_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_HIFREQAGC_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_incr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_HIFREQAGC_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_n1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_n2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_n3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_n4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_n5_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_HIFREQAGC_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_pol_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_HIFREQAGC_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_single_step_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_HIFREQAGC_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_stable_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_HIFREQAGC_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_hifreqagc_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_HIFREQAGC_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_init_adapt_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_INIT_ADAPT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_decr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_IQALIGN_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_frac_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_IQALIGN_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_IQALIGN_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_incr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_IQALIGN_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_IQALIGN_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_pol_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_IQALIGN_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_single_step_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_IQALIGN_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_stable_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_IQALIGN_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_IQALIGN_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_iqalign_targ_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_itercount_attr == 10'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_latch_delay_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_latch_prepost_delay_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_decr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOFREQAGC_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_frac_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOFREQAGC_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOFREQAGC_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_incr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOFREQAGC_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOFREQAGC_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_pol_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOFREQAGC_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_single_step_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOFREQAGC_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_stable_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOFREQAGC_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_lofreqagc_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOFREQAGC_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_logain_auxvref_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOGAIN_AUXVREF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_logain_dfe_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_logain_edge_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_logain_edgevref_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOGAIN_EDGEVREF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_logain_hifreqagc_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOGAIN_HIFREQAGC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_logain_iqalign_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOGAIN_IQALIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_logain_lofreqagc_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOGAIN_LOFREQAGC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_logain_vga_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_LOGAIN_VGA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_auxvref_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_dfe1_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_dfe23_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_dfe4p_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_edge2_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_edge3_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_edge4_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_edgevref_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_hifreqagc_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_iqalign_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_lofreqagc_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_mu_vga_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_nrz_to_pam4_mode_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_NRZ_TO_PAM4_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_slow_blockcnt_attr == 16'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_start_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_tsettle_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_accum_count_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_accum_level_en_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_decr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_frac_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_incr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_mode_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_pol_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_single_step_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_stable_reset_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_vga_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_VGA_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lms_yadjdata_mid_clamp_zero_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LMS_YADJDATA_MID_CLAMP_ZERO_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_lofreqagcgain_sel_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_LOFREQAGCGAIN_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_caldfedatatap1gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_caldfedatatap2gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_caldfedatatap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_caldfedatatap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_caldfeedgetap2gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_caldfeedgetap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_caldfeedgetap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal0_lofreqagcgain_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_caldfedatatap1gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal1_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_caldfedatatap1gain_attr == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal2_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_caldfedatatap1gain_attr == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal3_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal4_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal5_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal6_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_precal7_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_shift_auxshft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_shift_capture_trigger_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_SHIFT_CAPTURE_TRIGGER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_shift_clear_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_SHIFT_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_shift_dat_bitsel_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_SHIFT_DAT_BITSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_shift_datashft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_shift_edgeshft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_shift_edgeshft_nrz8b10b_pam16b20b_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_shift_polarity_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSET_SHIFT_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap10gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap11gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap12gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap13gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap14gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap15gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap16gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap1gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap2gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap5gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap6gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap7gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap8gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfedatatap9gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfeedgetap2gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfeedgetap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_caldfeedgetap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_hifreqvgagain_attr == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_static_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_auxvref0_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_auxvref1_attr == 9'd223
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_auxvref2_attr == 9'd339
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_auxvref3_attr == 9'd456
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_caldfedatatap1gain_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_caldfeedgetap2gain_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_calhifreqagcres_attr == 6'd52
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_callofreqagcgain_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_edgevref_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_hifreqvgagain_attr == 7'd77
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmax_iqalign_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_auxvref0_attr == 9'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_auxvref1_attr == 9'd173
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_auxvref2_attr == 9'd289
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_auxvref3_attr == 9'd356
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_caldfedatatap1gain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_caldfeedgetap2gain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_calhifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_callofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_edgevref_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqset_swpmin_iqalign_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqsetnrztopam4_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSETNRZTOPAM4_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqsetnrztopam4_switch_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSETNRZTOPAM4_SWITCH_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqsigdet_pause_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSIGDET_PAUSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqspare0_attr == 32'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqspare1_attr == 32'd15871
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqspare2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqsync2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSYNC2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqsync2flx_rxdatapath_ready_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQSYNC2FLX_RXDATAPATH_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqtapctrl_data_tap13to16_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQTAPCTRL_DATA_TAP13TO16_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqtapctrl_data_tap1to4_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQTAPCTRL_DATA_TAP1TO4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqtapctrl_data_tap5to8_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQTAPCTRL_DATA_TAP5TO8_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqtapctrl_data_tap9to12_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQTAPCTRL_DATA_TAP9TO12_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqtapctrl_edge_tap_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQTAPCTRL_EDGE_TAP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqtapctrl_tap1to4gain_dbl_res_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQTAPCTRL_TAP1TO4GAIN_DBL_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqtapctrl_tap5to16gain_dbl_res_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQTAPCTRL_TAP5TO16GAIN_DBL_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvalc_hifreqagcbiasadjust_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvalc_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQVALC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvalc_midbandzero_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvalcl_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQVALCL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvalcl_lofreqagcgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap01gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap02gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap03gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap04gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap05gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap06gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap07gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap08gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap09gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap10gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap11gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap12gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap13gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap14gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap15gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_caldfedatatap16gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvald_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQVALD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvale_caldfeedgetap02gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvale_caldfeedgetap03gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvale_caldfeedgetap04gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxeqvale_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXEQVALE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1cal_clear_mask_attr == 13'd8184
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_aux0_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_aux1_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_d0_bot_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_d0_mid_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_d0_top_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_d1_bot_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_d1_mid_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_d1_top_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_e0_lo_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg1calorder_smplroffset_e1_lo_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2cal_clear_mask_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_aux0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_aux1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_d0_bot_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_d0_mid_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_d0_top_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_d1_bot_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_d1_mid_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_d1_top_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_e0_lo_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfg2calorder_smplroffset_e1_lo_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfgcal_calfsmmeas_dlycount_attr == 10'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfgcal_fsmmaxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfgcal_lpfax_coarse_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxfgcal_lpfax_fine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxhifreqagc_inputcmadjust_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxhifreqagc_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXHIFREQAGC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcal_clear_mask_attr == 13'd8191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_ctlecmnmode_stg1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_ctlecmnmode_stg2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_ctlecmnmode_stg3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_aux0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_aux1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_d0_bot_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_d0_mid_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_d0_top_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_d1_bot_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_d1_mid_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_d1_top_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_e0_lo_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxinitcalorder_smplroffset_e1_lo_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmargin_flx_jit_offset_shift_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmargin_jit_disable_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmargin_jit_enable_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmargin_jit_offset_shift_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmargin_jit_setup_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmargin_volt_comp_mask_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmargin_volt_forcel2d_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXMARGIN_VOLT_FORCEL2D_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmargin_volt_offset_shift_d0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmargin_volt_offset_shift_d1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmarginin_direction_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXMARGININ_DIRECTION_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmarginin_flx_jit_offset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmarginin_locovren_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXMARGININ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmarginin_mode_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXMARGININ_MODE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmarginin_offset_change_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXMARGININ_OFFSET_CHANGE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmarginin_offset_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxmarginin_start_locovr_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXMARGININ_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxsum_cm_vref_attr == 9'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxsum_summer_cmfb_en_attr == SERDES_IP_LANE_RXEQ_L2_CFG_RXSUM_SUMMER_CMFB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l2_cfg_rxsum_summer_cmfb_ibias_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_dfeyadj_aging_cdrlock2data_loc_ov_attr == SERDES_IP_LANE_RXEQ_L3_CFG_DFEYADJ_AGING_CDRLOCK2DATA_LOC_OV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_dfeyadj_aging_cdrlock2data_loc_ov_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_DFEYADJ_AGING_CDRLOCK2DATA_LOC_OV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_dfeyadj_aging_div_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_dfeyadj_aging_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_DFEYADJ_AGING_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxagc_ctlecomp_filterbypass_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXAGC_CTLECOMP_FILTERBYPASS_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxagc_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXAGC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxbgcal_calfsmmeas_dlycount_attr == 10'd392
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxbgcal_clear_mask_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxbgcal_fsmmaxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxbgcal_lpfax_coarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxbgcal_lpfax_fine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxbgcalorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxbgcalorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxbgcalorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_calbiasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_calbiasboost_use_lut_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_CALBIASBOOST_USE_LUT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_callbbiasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_callbbiasboost_use_lut_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_CALLBBIASBOOST_USE_LUT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlecomp_filterbypass_smplrcal_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_CTLECOMP_FILTERBYPASS_SMPLRCAL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg1_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg2_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlecomp_filterbypass_tfrcal_stg3_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_CTLECOMP_FILTERBYPASS_TFRCAL_STG3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctleinput_probe_mux_smplrcal_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctleinput_probe_mux_tfrcal_stg3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg1_probe_mux_en_smplrcal_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg1_probe_mux_en_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg1_state_en_smplrcal_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg1_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg1_state_en_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg1_state_en_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg1_use_stg2code_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_CTLESTG1_USE_STG2CODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg2_probe_mux_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg2_probe_mux_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg2_state_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg2_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg2_state_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg2_state_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg3_probe_mux_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg3_probe_mux_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg3_state_en_smplrcal_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg3_state_en_tfrcal_stg1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg3_state_en_tfrcal_stg2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_ctlestg3_state_en_tfrcal_stg3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_hifreqagc_n5targin_sel_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_HIFREQAGC_N5TARGIN_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_inputcmadjust_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_inputcmadjust_stg1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_inputcmadjust_stg2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_inputcmadjust_stg3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_sdimode_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCAL_SDIMODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_smplroffset_aux0_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_smplroffset_aux1_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_smplroffset_d0_bot_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_smplroffset_d0_mid_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_smplroffset_d0_top_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_smplroffset_d1_bot_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_smplroffset_d1_mid_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_smplroffset_d1_top_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_tfrtrim_outen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_tfrtrim_outen_tfrcal_stg1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_tfrtrim_outen_tfrcal_stg2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcal_tfrtrim_outen_tfrcal_stg3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalalign_iqclk_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalalign_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALALIGN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctl_cal_abort_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALCTL_CAL_ABORT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctl_cal_type_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctl_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALCTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctl_post_delay_pow2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctl_pre_delay_pow2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecalctrl_input_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecalctrl_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALCTLECALCTRL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecalctrl_stg1_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecalctrl_stg1_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecalctrl_stg2_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecalctrl_stg2_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecalctrl_stg3_probemuxen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecalctrl_stg3_stateen_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecompoffset_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecompoffset_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALCTLECOMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecompoffsetfsmout_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALCTLECOMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecompoffsetfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALCTLECOMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalctlecompoffsetfsmout_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaldutybkgnd_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALDUTYBKGND_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaldutybkgnd_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALDUTYBKGND_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_biasboost_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_hf1deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_hf1resdcgain_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_hf2cap_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_hf2deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_hf2reszero_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_hf3deq_gray_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_hf3resdcgain_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_hf4deq_gray_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaleq_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALEQ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_ctlecmnmode_stg1_finish_side_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALFSM_CTLECMNMODE_STG1_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_ctlecmnmode_stg1_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_ctlecmnmode_stg2_finish_side_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALFSM_CTLECMNMODE_STG2_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_ctlecmnmode_stg2_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_ctlecmnmode_stg3_finish_side_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALFSM_CTLECMNMODE_STG3_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_ctlecmnmode_stg3_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_runcount_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_smplroffset_finish_side_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALFSM_SMPLROFFSET_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsm_smplroffset_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsmmeas_ctlecmnmode_stg1_invert_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALFSMMEAS_CTLECMNMODE_STG1_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsmmeas_ctlecmnmode_stg2_invert_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALFSMMEAS_CTLECMNMODE_STG2_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsmmeas_ctlecmnmode_stg3_invert_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALFSMMEAS_CTLECMNMODE_STG3_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalfsmmeas_smplroffset_invert_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALFSMMEAS_SMPLROFFSET_INVERT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_ctlecmnmode_stg1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_ctlecmnmode_stg2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_ctlecmnmode_stg3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_aux0_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_aux1_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_d0_bot_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_d0_mid_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_d0_top_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_d1_bot_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_d1_mid_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_d1_top_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_e0_lo_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalinit_smplroffset_e1_lo_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeas_pow2count_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasin_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasin_req_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASIN_REQ_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasin_req_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASIN_REQ_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasin_req_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASIN_REQ_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasout_ack_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASOUT_ACK_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasout_ack_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASOUT_ACK_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasout_ack_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASOUT_ACK_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasout_avg_grp0_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASOUT_AVG_GRP0_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasout_avg_grp1_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASOUT_AVG_GRP1_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasout_avg_grp2_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASOUT_AVG_GRP2_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalmeasout_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALMEASOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaloffsetfsmout_auxdatacomp_offset_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALOFFSETFSMOUT_AUXDATACOMP_OFFSET_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaloffsetfsmout_boost_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALOFFSETFSMOUT_BOOST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaloffsetfsmout_edgecomp_offset_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALOFFSETFSMOUT_EDGECOMP_OFFSET_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcaloffsetfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalset_cal_clear_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalset_cal_mode_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALSET_CAL_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalset_cal_req_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALSET_CAL_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalset_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalstat_cal_ack_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALSTAT_CAL_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalstat_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalsummerfsmout_comp_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALSUMMERFSMOUT_COMP_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcalsummerfsmout_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCALSUMMERFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcdrphd_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCDRPHD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxcdrphd_override_ignore_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCDRPHD_OVERRIDE_IGNORE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_caloffset_range_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_calstg1offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_calstg1offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_calstg2offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_calstg2offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_calstg3offset_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_calstg3offset_preenc_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_dccouple_sigpath_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCTLE_DCCOUPLE_SIGPATH_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_lbbiasboost_gray_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCTLE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_stg1tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_stg2tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_stg3tfrtrim_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_tfrtrim_outmem_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCTLE_TFRTRIM_OUTMEM_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctle_tfrtrim_outpen_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCTLE_TFRTRIM_OUTPEN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctledc_dccouple_tgate_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCTLEDC_DCCOUPLE_TGATE_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxctledc_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXCTLEDC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxdfe_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXDFE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxdfe_tapgain_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxdfepam_enable_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXDFEPAM_ENABLE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxdfepam_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXDFEPAM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxdpifjit_enb_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXDPIFJIT_ENB_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxdpifjit_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXDPIFJIT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxdpifjit_offset_locovr_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqadj_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQADJ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqadj_yadjust_aux0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqadj_yadjust_aux1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqadj_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqadj_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqadj_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqadj_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqadj_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqadj_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqauxxor_amux_sel_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqauxxor_dmux_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqauxxor_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQAUXXOR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcal2flx_pstate_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCAL2FLX_PSTATE_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcal2flx_rate_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCAL2FLX_RATE_MASK_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_16a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_16b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_16c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_16d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_16e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_1a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_1b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_1c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_1d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_1e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_2a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_2b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_2c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_2d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_2e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_4a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_4b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_4c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_4d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_4e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_8a_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_8b_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_8c_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_8d_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalhfagcbiasadj_lut_8e_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_16a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_16b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_16c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_16d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_16e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_1a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_1b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_1c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_1d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_1e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_2a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_2b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_2c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_2d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_2e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_4a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_4b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_4c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_4d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_4e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_8a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_8b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_8c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_8d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcallofreqagcgain_lut_8e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_16a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_16b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_16c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_16d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_16e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_1a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_1b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_1c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_1d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_1e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_2a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_2b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_2c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_2d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_2e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_4a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_4b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_4c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_4d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_4e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_8a_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_8b_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_8c_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_8d_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcalmidbandzero_lut_8e_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcals_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCALS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcals_offset_datasummer0_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcals_offset_datasummer0_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcals_offset_datasummer1_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcals_offset_datasummer1_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcals_offset_edgesummer0_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcals_offset_edgesummer0_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcals_offset_edgesummer1_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcals_offset_edgesummer1_preenc_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcdr_force_ltr_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCDR_FORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqcdr_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCDR_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqctl_clear_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCTL_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqctl_fg_run_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCTL_FG_RUN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqctlelut_hifreqagcres_ovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCTLELUT_HIFREQAGCRES_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqctlelut_hifreqvgagain_ovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCTLELUT_HIFREQVGAGAIN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqctls_oddeven_tapgain_sel_inv_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCTLS_ODDEVEN_TAPGAIN_SEL_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqctls_static_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQCTLS_STATIC_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqdat_aux_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQDAT_AUX_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqdat_edge_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQDAT_EDGE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqdatactl_auxswap_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqdatactl_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQDATACTL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqdatarate_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQDATARATE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqdatarate_rx_rate_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqdfeyadj_agingl2r_delay_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqdfeyadj_agingl2r_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQDFEYADJ_AGINGL2R_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqedgeadj_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEDGEADJ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqedgeadj_yadjust_edge0lo_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqedgeadj_yadjust_edge1lo_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm2flx_ehm_done_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHM2FLX_EHM_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm2flx_ehm_done_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHM2FLX_EHM_DONE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm2flx_ehm_err_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHM2FLX_EHM_ERR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm2flx_ehm_err_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHM2FLX_EHM_ERR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm2flx_ehm_fom_locovr_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHM2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_data_extshift_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHM_DATA_EXTSHIFT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_distance_th_50p_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_distance_th_rate_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_err_mask_vf00_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_err_mask_vf01_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_event_rate_vf00_attr == 32'd67108864
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_event_rate_vf01_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_general_in_vf00_attr == 32'd5505024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_general_in_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_lms_th_50p_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_lms_th_rate_attr == 20'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_mask_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_no_change_th_50p_attr == 12'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_no_change_th_rate_attr == 12'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_reflections_num_50p_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_reflections_num_rate_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_slicer_swap_cb_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHM_SLICER_SWAP_CB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_sym_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_sym_dly_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_tap_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_test_aux_slicer_val_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehm_test_hits_th_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjaux_ehm_yadjust_aux0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjaux_ehm_yadjust_aux1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjaux_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJAUX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjauxen_ehm_aux_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJAUXEN_EHM_AUX_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjauxen_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJAUXEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjauxltch_aux_yadj_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJAUXLTCH_AUX_YADJ_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjauxltch_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJAUXLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdata_ehm_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdata_ehm_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdata_ehm_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdata_ehm_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdata_ehm_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdata_ehm_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdata_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdataen_ehm_data_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJDATAEN_EHM_DATA_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdataen_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJDATAEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdataltch_data_yadj_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJDATALTCH_DATA_YADJ_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqehmyadjdataltch_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQEHMYADJDATALTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2ehm_ehm_run_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2EHM_EHM_RUN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2ehm_ehm_run_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2EHM_EHM_RUN_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2lms_coarse_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2LMS_COARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2lms_ctrl_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2LMS_CTRL_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2lms_dfecore_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2LMS_DFECORE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2lms_force_evrefupd_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2LMS_FORCE_EVREFUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2lms_freeze_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2LMS_FREEZE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2lms_incr_decr_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2LMS_INCR_DECR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2lms_mu_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2LMS_MU_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2lms_rst_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2LMS_RST_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2ofc_ofc_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2OFC_OFC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx2ofc_ofc_en_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX2OFC_OFC_EN_OVRDEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx_pcs_rxeq_clr_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX_PCS_RXEQ_CLR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx_pcs_rxeq_start_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX_PCS_RXEQ_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx_pcs_rxeq_static_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLX_PCS_RXEQ_STATIC_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx_rxrate2pcie1_map_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx_rxrate2pcie2_map_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx_rxrate2pcie3_map_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflx_rxrate2pcie4_map_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxehmdata_ehm_data_slc_sel_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXEHMDATA_EHM_DATA_SLC_SEL_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxehmdata_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXEHMDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxfsm_generalpurpose_reg_in_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxfsm_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXFSM_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxfsm_pause_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXFSM_PAUSE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxfsm_state_obs_hold_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXFSM_STATE_OBS_HOLD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxfsm_state_obs_sel_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXFSM_STATE_OBS_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxltr_force_ltr_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXLTR_FORCE_LTR_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxltr_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXLTR_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxpcsrxeyediag_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXPCSRXEYEDIAG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxpcsrxeyediag_start_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXPCSRXEYEDIAG_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqflxsigdet_sel_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFLXSIGDET_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqfsm2ofc_ofc_cal_req_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFSM2OFC_OFC_CAL_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqfsm2ofc_ofc_cal_req_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQFSM2OFC_OFC_CAL_REQ_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_16a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_16b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_16c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_16d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_16e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_1a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_1b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_1c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_1d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_1e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_2a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_2b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_2c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_2d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_2e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_4a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_4b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_4c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_4d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_4e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_8a_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_8b_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_8c_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_8d_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqhf2cap_lut_8e_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_done_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_DONE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmax_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmax_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_SATMAX_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmax_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmax_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmax_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_SATMAX_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmax_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_SATMAX_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmax_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_SATMAX_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmin_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmin_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_SATMIN_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmin_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmin_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmin_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_SATMIN_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmin_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_SATMIN_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_satmin_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_SATMIN_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_stable_auxvref_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_stable_calalign_iqclk_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_STABLE_CALALIGN_IQCLK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_stable_caldfedatatapgain_locovr_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_stable_caldfeedgetapgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_stable_hifreqagcres_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_STABLE_HIFREQAGCRES_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_stable_hifreqvgagain_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_STABLE_HIFREQVGAGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlms2flx_stable_lofreqagcgain_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMS2FLX_STABLE_LOFREQAGCGAIN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsupd_chng_ack_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSUPD_CHNG_ACK_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsupd_chng_req_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSUPD_CHNG_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsupd_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSUPD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjaux_lms_vref0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjaux_lms_vref1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjaux_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJAUX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjauxen_lms_aux_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJAUXEN_LMS_AUX_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjauxen_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJAUXEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjauxltch_lms_aux_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJAUXLTCH_LMS_AUX_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjauxltch_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJAUXLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdata_lms_yadjust_d0_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdata_lms_yadjust_d0_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdata_lms_yadjust_d0_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdata_lms_yadjust_d1_bot_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdata_lms_yadjust_d1_mid_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdata_lms_yadjust_d1_top_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdata_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJDATA_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdataen_lms_data_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJDATAEN_LMS_DATA_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdataen_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJDATAEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdataltch_lms_data_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJDATALTCH_LMS_DATA_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjdataltch_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJDATALTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjedge_lms_yadjust_edge0_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjedge_lms_yadjust_edge1_locovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjedge_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJEDGE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjedgeen_lms_edge_yadjust_en_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJEDGEEN_LMS_EDGE_YADJUST_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjedgeen_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJEDGEEN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjedgeltch_lms_edge_latch_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJEDGELTCH_LMS_EDGE_LATCH_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqlmsyadjedgeltch_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLMSYADJEDGELTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqltch_dfe_aux_yadj_b_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLTCH_DFE_AUX_YADJ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqltch_dfe_b_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLTCH_DFE_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqltch_dfe_data_yadj_b_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLTCH_DFE_DATA_YADJ_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqltch_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLTCH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqltchc_auxswap_b_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLTCHC_AUXSWAP_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqltchc_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQLTCHC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofc2flx_ofc_cal_done_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQOFC2FLX_OFC_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofc2flx_ofc_cal_done_ovrden_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQOFC2FLX_OFC_CAL_DONE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_ctle_rxinpprobemuxen_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_ctle_rxstg1_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_ctle_rxstg1probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_ctle_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_ctle_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_ctle_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_ctle_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_summer_rxinpprobemuxen_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_summer_rxstg1_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_summer_rxstg1probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_summer_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_summer_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_summer_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_summer_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_time_h_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_adapt_time_l_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_ctle_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_ctle_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_ctle_rxstg1probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_ctle_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_ctle_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_ctle_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_ctle_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_summer_rxinpprobemuxen_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_summer_rxstg1_stateen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_summer_rxstg1probemuxen_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_summer_rxstg2_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_summer_rxstg2probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_summer_rxstg3_stateen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_summer_rxstg3probemuxen_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_cal_time_l_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_compsel_ctle_st1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_compsel_ctle_st2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_compsel_ctle_st3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_compsel_idle_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_compsel_sa_d0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_compsel_sa_d1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_compsel_sa_e0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_compsel_sa_e1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_invert_comp_fb_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_lpexitcal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_lpexitcal_time_l_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_adapt_en_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_adapt_thr_sel_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_cal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_cal_thr_sel_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_data_disp_sticky_clr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQOFCCFG_OFC_DATA_DISP_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_disparity_disable_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQOFCCFG_OFC_DISPARITY_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_disparity_leak_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_disparity_thr_sel_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_lpexitcal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_lpf_bypass_en_cb_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQOFCCFG_OFC_LPF_BYPASS_EN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ofc_ratechangecal_en_attr == 8'd253
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_pre_timer_setting_pow2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ratechangecal_time_h_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_ratechangecal_time_l_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_rxinpprobemuxen_idle_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_rxstg1_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_rxstg1probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_rxstg2_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_rxstg2probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_rxstg3_stateen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqofccfg_rxstg3probemuxen_idle_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqout_init_restore_avail_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQOUT_INIT_RESTORE_AVAIL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqprecal_code_sel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqprecal_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQPRECAL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_hf1deq_dir_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_BOOSTLUT_HF1DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_hf2deq_dir_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_BOOSTLUT_HF2DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_hf2reszero_dir_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_BOOSTLUT_HF2RESZERO_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_hf3deq_dir_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_BOOSTLUT_HF3DEQ_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_idx_hf1deq_vf00_attr == 32'd599186
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_idx_hf1deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_idx_hf2deq_vf00_attr == 32'd1198372
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_idx_hf2deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_idx_hf2reszero_vf00_attr == 32'd4290772992
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_idx_hf2reszero_vf01_attr == 21'd2097151
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_idx_hf3deq_vf00_attr == 32'd2396744
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_idx_hf3deq_vf01_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_init_hf1deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_init_hf2deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_init_hf2reszero_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_boostlut_init_hf3deq_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_cal_hifreqagcres_attr == 6'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_cal_hifreqvgagain_attr == 7'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_cal_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_cal_yadjust_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_biasboost_dir_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_GAINLUT_BIASBOOST_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_hf1resdcgain_dir_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_GAINLUT_HF1RESDCGAIN_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_hf3resdcgain_dir_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_GAINLUT_HF3RESDCGAIN_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_biasboost_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_biasboost_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_biasboost_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf00_attr == 32'd2863311530
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf01_attr == 32'd715827882
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_hf1resdcgain_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf00_attr == 32'd1431655764
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf01_attr == 32'd1431655765
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_hf3resdcgain_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_lbbiasboost_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_lbbiasboost_vf01_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_idx_lbbiasboost_vf02_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_init_biasboost_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_init_hf1resdcgain_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_init_hf3resdcgain_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_init_lbbiasboost_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_gainlut_lbbiasboost_dir_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_GAINLUT_LBBIASBOOST_DIR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_latch_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref0_initval_attr == 9'd61
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref1_initval_attr == 9'd191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref2_initval_attr == 9'd321
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref3_initval_attr == 9'd451
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_decr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_AUXVREF_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_frac_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_AUXVREF_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_frac_reset_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_incr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_AUXVREF_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_incr_decr_mask_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_pam4adj_swizzle_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_AUXVREF_PAM4ADJ_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_AUXVREF_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_pol_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_single_step_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_AUXVREF_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_stable_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_AUXVREF_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_AUXVREF_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_targ_0_hi_attr == 9'd149
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_auxvref_targ_0_lo_attr == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_auxvref_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_auxvref_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_dfe_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_dfe_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_edge_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_edge_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_edgevref_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_edgevref_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_iqalign_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_iqalign_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_level_vga_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_vga_vf00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_block_vote_vga_vf01_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_blockcount_fast_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_BLOCKCOUNT_FAST_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_coarse_detect_clear_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_COARSE_DETECT_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_coarse_detect_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_COARSE_DETECT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_continuous_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_CONTINUOUS_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_datastats_incr_decr_swizzle_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_DATASTATS_INCR_DECR_SWIZZLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_datastats_pol_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_DATASTATS_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_datastats_thres_attr == 16'd1023
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe1_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe2_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe3_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe4p_accum_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_core_sel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_decr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_DFE_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_frac_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_DFE_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_frac_reset_mask_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_incr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_DFE_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_incr_decr_mask_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_inner_lvl_filter_en_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_DFE_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_pol_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_single_step_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_DFE_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_stable_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_DFE_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_DFE_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_targtap1_attr == 6'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_targtap2_attr == 7'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_targtap3_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_dfe_targtap4_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_decr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGE_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_frac_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGE_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_frac_reset_mask_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_incr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGE_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_incr_decr_mask_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGE_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_pol_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_single_step_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGE_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_stable_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGE_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edge_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGE_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_decr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGEVREF_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_frac_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGEVREF_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGEVREF_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_incr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGEVREF_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_initval_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGEVREF_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_pol_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGEVREF_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_single_step_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGEVREF_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_stable_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGEVREF_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_edgevref_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_EDGEVREF_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_fast_blockcnt_attr == 16'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_filter_mode_auxvref_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_filter_mode_dfe_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_filter_mode_edge_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_filter_mode_edgevref_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_filter_mode_iqalign_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_filter_mode_vga_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_freeze_auxvrefupd_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_freeze_dfeupd_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_freeze_edgeupd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_freeze_edgevrefupd_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_FREEZE_EDGEVREFUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_freeze_forcebg_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_FREEZE_FORCEBG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_freeze_hifreqagcupd_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_FREEZE_HIFREQAGCUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_freeze_iqalignupd_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_FREEZE_IQALIGNUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_freeze_lofreqagcupd_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_FREEZE_LOFREQAGCUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_freeze_vgaupd_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_FREEZE_VGAUPD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_gated_update_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_GATED_UPDATE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_accum_count_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_accum_level_en_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_decr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_HIFREQAGC_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_frac_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_HIFREQAGC_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_HIFREQAGC_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_incr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_HIFREQAGC_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_n1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_n2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_n3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_n4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_n5_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_HIFREQAGC_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_pol_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_HIFREQAGC_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_single_step_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_HIFREQAGC_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_stable_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_HIFREQAGC_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_hifreqagc_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_HIFREQAGC_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_init_adapt_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_INIT_ADAPT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_decr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_IQALIGN_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_frac_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_IQALIGN_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_IQALIGN_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_incr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_IQALIGN_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_IQALIGN_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_pol_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_IQALIGN_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_single_step_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_IQALIGN_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_stable_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_IQALIGN_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_IQALIGN_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_iqalign_targ_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_itercount_attr == 10'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_latch_delay_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_latch_prepost_delay_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_level_en_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_decr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOFREQAGC_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_frac_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOFREQAGC_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOFREQAGC_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_incr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOFREQAGC_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOFREQAGC_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_pol_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOFREQAGC_POL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_single_step_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOFREQAGC_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_stable_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOFREQAGC_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_lofreqagc_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOFREQAGC_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_logain_auxvref_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOGAIN_AUXVREF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_logain_dfe_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_logain_edge_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_logain_edgevref_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOGAIN_EDGEVREF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_logain_hifreqagc_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOGAIN_HIFREQAGC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_logain_iqalign_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOGAIN_IQALIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_logain_lofreqagc_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOGAIN_LOFREQAGC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_logain_vga_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_LOGAIN_VGA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_auxvref_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_dfe1_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_dfe23_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_dfe4p_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_edge2_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_edge3_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_edge4_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_edgevref_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_hifreqagc_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_iqalign_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_lofreqagc_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_mu_vga_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_nrz_to_pam4_mode_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_NRZ_TO_PAM4_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_slow_blockcnt_attr == 16'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_start_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_START_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_tsettle_attr == 6'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_accum_count_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_accum_level_en_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_decr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_DECR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_frac_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_FRAC_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_frac_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_FRAC_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_frac_reset_type_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_frac_rst_prd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_incr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_INCR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_mode_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_periodic_frac_reset_enable_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_PERIODIC_FRAC_RESET_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_pol_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_single_step_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_SINGLE_STEP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_stable_distance_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_stable_nochange_th_attr == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_stable_reflect_th_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_stable_reset_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_STABLE_RESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_vga_stable_reset_mask_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_VGA_STABLE_RESET_MASK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lms_yadjdata_mid_clamp_zero_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LMS_YADJDATA_MID_CLAMP_ZERO_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_lofreqagcgain_sel_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_LOFREQAGCGAIN_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_caldfedatatap1gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_caldfedatatap2gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_caldfedatatap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_caldfedatatap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_caldfeedgetap2gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_caldfeedgetap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_caldfeedgetap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal0_lofreqagcgain_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_caldfedatatap1gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal1_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_caldfedatatap1gain_attr == 6'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal2_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_caldfedatatap1gain_attr == 6'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal3_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal4_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal5_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal6_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_caldfedatatap1gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_caldfedatatap2gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_caldfedatatap3gain_attr == 7'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_caldfedatatap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_caldfeedgetap2gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_caldfeedgetap3gain_attr == 7'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_caldfeedgetap4gain_attr == 6'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_precal7_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_shift_auxshft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_shift_capture_trigger_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_SHIFT_CAPTURE_TRIGGER_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_shift_clear_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_SHIFT_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_shift_dat_bitsel_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_SHIFT_DAT_BITSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_shift_datashft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_shift_edgeshft_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_shift_edgeshft_nrz8b10b_pam16b20b_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_shift_polarity_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSET_SHIFT_POLARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap10gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap11gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap12gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap13gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap14gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap15gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap16gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap1gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap2gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap5gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap6gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap7gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap8gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfedatatap9gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfeedgetap2gain_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfeedgetap3gain_attr == 7'd64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_caldfeedgetap4gain_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_hifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_hifreqvgagain_attr == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_iqalign_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_static_lofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_auxvref0_attr == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_auxvref1_attr == 9'd223
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_auxvref2_attr == 9'd339
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_auxvref3_attr == 9'd456
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_caldfedatatap1gain_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_caldfeedgetap2gain_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_calhifreqagcres_attr == 6'd52
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_callofreqagcgain_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_edgevref_attr == 9'd511
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_hifreqvgagain_attr == 7'd77
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmax_iqalign_attr == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_auxvref0_attr == 9'd56
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_auxvref1_attr == 9'd173
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_auxvref2_attr == 9'd289
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_auxvref3_attr == 9'd356
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_caldfedatatap1gain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_caldfeedgetap2gain_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_calhifreqagcres_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_callofreqagcgain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_edgevref_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_hifreqvgagain_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqset_swpmin_iqalign_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqsetnrztopam4_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSETNRZTOPAM4_LOCOVREN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqsetnrztopam4_switch_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSETNRZTOPAM4_SWITCH_LOCOVR_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqsigdet_pause_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSIGDET_PAUSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqspare0_attr == 32'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqspare1_attr == 32'd15871
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqspare2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqsync2flx_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSYNC2FLX_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqsync2flx_rxdatapath_ready_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQSYNC2FLX_RXDATAPATH_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqtapctrl_data_tap13to16_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQTAPCTRL_DATA_TAP13TO16_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqtapctrl_data_tap1to4_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQTAPCTRL_DATA_TAP1TO4_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqtapctrl_data_tap5to8_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQTAPCTRL_DATA_TAP5TO8_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqtapctrl_data_tap9to12_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQTAPCTRL_DATA_TAP9TO12_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqtapctrl_edge_tap_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQTAPCTRL_EDGE_TAP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqtapctrl_tap1to4gain_dbl_res_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQTAPCTRL_TAP1TO4GAIN_DBL_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqtapctrl_tap5to16gain_dbl_res_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQTAPCTRL_TAP5TO16GAIN_DBL_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvalc_hifreqagcbiasadjust_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvalc_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQVALC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvalc_midbandzero_locovr_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvalcl_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQVALCL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvalcl_lofreqagcgain_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap01gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap02gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap03gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap04gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap05gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap06gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap07gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap08gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap09gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap10gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap11gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap12gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap13gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap14gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap15gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_caldfedatatap16gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvald_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQVALD_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvale_caldfeedgetap02gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvale_caldfeedgetap03gain_graysm_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvale_caldfeedgetap04gain_graysm_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxeqvale_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXEQVALE_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1cal_clear_mask_attr == 13'd8184
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_aux0_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_aux1_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_d0_bot_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_d0_mid_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_d0_top_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_d1_bot_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_d1_mid_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_d1_top_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_e0_lo_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg1calorder_smplroffset_e1_lo_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2cal_clear_mask_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_ctlecmnmode_stg1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_ctlecmnmode_stg2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_ctlecmnmode_stg3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_aux0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_aux1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_d0_bot_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_d0_mid_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_d0_top_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_d1_bot_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_d1_mid_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_d1_top_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_e0_lo_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfg2calorder_smplroffset_e1_lo_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfgcal_calfsmmeas_dlycount_attr == 10'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfgcal_fsmmaxiter_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfgcal_lpfax_coarse_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxfgcal_lpfax_fine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxhifreqagc_inputcmadjust_locovr_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxhifreqagc_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXHIFREQAGC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcal_clear_mask_attr == 13'd8191
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_ctlecmnmode_stg1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_ctlecmnmode_stg2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_ctlecmnmode_stg3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_aux0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_aux1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_d0_bot_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_d0_mid_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_d0_top_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_d1_bot_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_d1_mid_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_d1_top_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_e0_lo_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxinitcalorder_smplroffset_e1_lo_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmargin_flx_jit_offset_shift_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmargin_jit_disable_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmargin_jit_enable_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmargin_jit_offset_shift_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmargin_jit_setup_delay_attr == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmargin_volt_comp_mask_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmargin_volt_forcel2d_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXMARGIN_VOLT_FORCEL2D_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmargin_volt_offset_shift_d0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmargin_volt_offset_shift_d1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmarginin_direction_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXMARGININ_DIRECTION_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmarginin_flx_jit_offset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmarginin_locovren_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXMARGININ_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmarginin_mode_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXMARGININ_MODE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmarginin_offset_change_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXMARGININ_OFFSET_CHANGE_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmarginin_offset_locovr_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxmarginin_start_locovr_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXMARGININ_START_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxsum_cm_vref_attr == 9'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxsum_summer_cmfb_en_attr == SERDES_IP_LANE_RXEQ_L3_CFG_RXSUM_SUMMER_CMFB_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_lane_rxeq_l3_cfg_rxsum_summer_cmfb_ibias_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_done_pwr2_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_apb_dwmask_muxd0_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_apb_dwmask_muxd1_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_apb_dwmask_muxd2_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_apb_dwmask_muxd3_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_apb_dwmask_muxd4_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_a2f_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_a2f_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_a2f_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_a2f_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_a2f_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd0_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd1_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd2_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd3_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd4_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd0_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd1_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd2_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd3_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd4_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd0_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd1_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd2_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd3_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd4_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd0_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd1_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd2_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd3_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd4_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd0_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd1_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd2_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd3_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd4_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_marker_muxd0_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_marker_muxd1_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_marker_muxd2_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_marker_muxd3_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dpso_marker_muxd4_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd0_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd1_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd2_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd3_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd4_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd0_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd1_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd2_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd3_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd0_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd1_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd2_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd3_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd4_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd0_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd3_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd4_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd0_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd2_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd2_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd3_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd4_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd0_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd1_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd2_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd3_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd4_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd0_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd1_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd2_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd3_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd4_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd0_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd1_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd2_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd3_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd4_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd0_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd1_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd2_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd3_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd4_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd2_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd3_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd4_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd0_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd2_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd0_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd0_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd1_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd2_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd3_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd4_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd0_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd1_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd2_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd3_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd4_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd4_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd0_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd1_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd2_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd3_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd4_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd0_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd1_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd2_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd3_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd4_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_lock_thresh_muxd0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_lock_thresh_muxd1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_lock_thresh_muxd2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_lock_thresh_muxd3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_lock_thresh_muxd4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd0_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd1_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd2_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd3_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd4_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchn_offset_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchn_offset_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchn_offset_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchn_offset_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchn_offset_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchp_offset_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchp_offset_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchp_offset_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchp_offset_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_notchp_offset_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_bypass_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_bypass_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_bypass_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_bypass_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_bypass_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd4_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_step_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_step_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_step_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_step_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ramp_step_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd0_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd1_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd2_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd3_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd4_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd2_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd0_attr == 8'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd1_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd2_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd3_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd4_attr == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd0_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd1_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd2_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd3_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd4_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd2_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd3_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd4_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_fll_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_fll_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_fll_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_fll_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_fll_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_pll_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_pll_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_pll_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_pll_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_stay_pll_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd0_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd1_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd2_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd4_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd0_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd1_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd3_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd4_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_temp_track_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_temp_track_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_temp_track_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_temp_track_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_temp_track_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd0_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd1_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd2_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd3_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd4_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd0_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd1_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd2_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd3_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd4_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd0_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd1_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd2_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd3_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd4_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd0_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd1_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd2_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd3_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd4_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bb_gain_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bb_gain_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bb_gain_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bb_gain_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bb_gain_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbinlock_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbinlock_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbinlock_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbinlock_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbinlock_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbthresh_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbthresh_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbthresh_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbthresh_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_bbthresh_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrlhext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrlhext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrlhext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrlhext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrlhext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrllext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrllext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrllext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrllext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_cloadctrllext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_muxd0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_muxd1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_muxd2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_muxd3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_muxd4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcoditheren_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcoditheren_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcoditheren_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcoditheren_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcoditheren_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofine_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofine_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofine_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofine_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofine_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofinedftsel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofinedftsel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofinedftsel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofinedftsel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dcofinedftsel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dither_value_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dither_value_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dither_value_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dither_value_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_dither_value_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_earlylock_criteria_muxd0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_earlylock_criteria_muxd1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_earlylock_criteria_muxd2_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_earlylock_criteria_muxd3_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_earlylock_criteria_muxd4_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_frac_muxd0_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_frac_muxd1_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_frac_muxd2_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_frac_muxd3_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_frac_muxd4_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd0_attr == 9'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd1_attr == 9'd45
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd2_attr == 9'd27
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd3_attr == 9'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd4_attr == 9'd216
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdgain_muxd0_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdgain_muxd1_attr == 8'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdgain_muxd2_attr == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdgain_muxd3_attr == 8'd23
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_feedfwrdgain_muxd4_attr == 8'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fracnen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fracnen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fracnen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fracnen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_fracnen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_lock_criteria_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_lock_criteria_muxd1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_lock_criteria_muxd2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_lock_criteria_muxd3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_lock_criteria_muxd4_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_regen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_regen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_regen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_regen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllc_regen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllock_sel_muxd0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllock_sel_muxd1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllock_sel_muxd2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllock_sel_muxd3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_plllock_sel_muxd4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdc_fine_res_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdc_fine_res_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdc_fine_res_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdc_fine_res_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdc_fine_res_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdccalexten_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdccalexten_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdccalexten_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdccalexten_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdccalexten_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcroen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcroen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcroen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcroen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcroen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L0_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcsel_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcsel_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcsel_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcsel_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdcsel_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdctargetcnt_muxd0_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdctargetcnt_muxd1_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdctargetcnt_muxd2_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdctargetcnt_muxd3_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tdctargetcnt_muxd4_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tribufctrlext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tribufctrlext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tribufctrlext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tribufctrlext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l0_cfg_pllloader_synthlc_o_tribufctrlext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_done_pwr2_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_apb_dwmask_muxd0_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_apb_dwmask_muxd1_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_apb_dwmask_muxd2_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_apb_dwmask_muxd3_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_apb_dwmask_muxd4_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_a2f_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_a2f_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_a2f_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_a2f_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_a2f_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd0_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd1_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd2_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd3_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd4_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd0_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd1_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd2_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd3_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd4_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd0_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd1_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd2_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd3_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd4_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd0_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd1_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd2_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd3_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd4_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd0_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd1_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd2_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd3_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd4_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_marker_muxd0_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_marker_muxd1_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_marker_muxd2_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_marker_muxd3_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dpso_marker_muxd4_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd0_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd1_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd2_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd3_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd4_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd0_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd1_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd2_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd3_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd0_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd1_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd2_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd3_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd4_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd0_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd3_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd4_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd0_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd2_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd2_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd3_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd4_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd0_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd1_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd2_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd3_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd4_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd0_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd1_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd2_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd3_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd4_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd0_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd1_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd2_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd3_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd4_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd0_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd1_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd2_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd3_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd4_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd2_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd3_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd4_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd0_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd2_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd0_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd0_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd1_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd2_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd3_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd4_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd0_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd1_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd2_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd3_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd4_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd4_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd0_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd1_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd2_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd3_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd4_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd0_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd1_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd2_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd3_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd4_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_lock_thresh_muxd0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_lock_thresh_muxd1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_lock_thresh_muxd2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_lock_thresh_muxd3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_lock_thresh_muxd4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd0_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd1_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd2_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd3_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd4_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchn_offset_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchn_offset_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchn_offset_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchn_offset_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchn_offset_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchp_offset_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchp_offset_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchp_offset_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchp_offset_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_notchp_offset_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_bypass_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_bypass_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_bypass_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_bypass_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_bypass_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd4_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_step_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_step_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_step_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_step_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ramp_step_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd0_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd1_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd2_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd3_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd4_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd2_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd0_attr == 8'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd1_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd2_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd3_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd4_attr == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd0_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd1_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd2_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd3_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd4_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd2_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd3_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd4_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_fll_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_fll_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_fll_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_fll_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_fll_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_pll_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_pll_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_pll_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_pll_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_stay_pll_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd0_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd1_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd2_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd4_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd0_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd1_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd3_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd4_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_temp_track_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_temp_track_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_temp_track_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_temp_track_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_temp_track_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd0_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd1_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd2_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd3_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd4_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd0_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd1_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd2_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd3_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd4_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd0_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd1_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd2_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd3_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd4_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd0_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd1_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd2_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd3_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd4_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bb_gain_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bb_gain_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bb_gain_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bb_gain_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bb_gain_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbinlock_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbinlock_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbinlock_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbinlock_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbinlock_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbthresh_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbthresh_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbthresh_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbthresh_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_bbthresh_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrlhext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrlhext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrlhext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrlhext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrlhext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrllext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrllext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrllext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrllext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_cloadctrllext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_muxd0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_muxd1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_muxd2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_muxd3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_muxd4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcoditheren_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcoditheren_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcoditheren_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcoditheren_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcoditheren_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofine_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofine_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofine_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofine_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofine_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofinedftsel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofinedftsel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofinedftsel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofinedftsel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dcofinedftsel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dither_value_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dither_value_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dither_value_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dither_value_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_dither_value_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_earlylock_criteria_muxd0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_earlylock_criteria_muxd1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_earlylock_criteria_muxd2_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_earlylock_criteria_muxd3_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_earlylock_criteria_muxd4_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_frac_muxd0_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_frac_muxd1_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_frac_muxd2_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_frac_muxd3_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_frac_muxd4_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd0_attr == 9'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd1_attr == 9'd45
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd2_attr == 9'd27
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd3_attr == 9'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd4_attr == 9'd216
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdgain_muxd0_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdgain_muxd1_attr == 8'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdgain_muxd2_attr == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdgain_muxd3_attr == 8'd23
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_feedfwrdgain_muxd4_attr == 8'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fracnen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fracnen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fracnen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fracnen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_fracnen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_lock_criteria_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_lock_criteria_muxd1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_lock_criteria_muxd2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_lock_criteria_muxd3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_lock_criteria_muxd4_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_regen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_regen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_regen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_regen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllc_regen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllock_sel_muxd0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllock_sel_muxd1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllock_sel_muxd2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllock_sel_muxd3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_plllock_sel_muxd4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdc_fine_res_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdc_fine_res_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdc_fine_res_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdc_fine_res_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdc_fine_res_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdccalexten_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdccalexten_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdccalexten_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdccalexten_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdccalexten_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcroen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcroen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcroen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcroen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcroen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L1_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcsel_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcsel_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcsel_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcsel_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdcsel_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdctargetcnt_muxd0_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdctargetcnt_muxd1_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdctargetcnt_muxd2_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdctargetcnt_muxd3_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tdctargetcnt_muxd4_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tribufctrlext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tribufctrlext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tribufctrlext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tribufctrlext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l1_cfg_pllloader_synthlc_o_tribufctrlext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_done_pwr2_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_apb_dwmask_muxd0_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_apb_dwmask_muxd1_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_apb_dwmask_muxd2_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_apb_dwmask_muxd3_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_apb_dwmask_muxd4_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_a2f_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_a2f_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_a2f_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_a2f_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_a2f_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd0_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd1_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd2_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd3_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd4_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd0_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd1_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd2_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd3_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd4_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd0_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd1_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd2_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd3_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd4_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd0_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd1_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd2_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd3_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd4_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd0_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd1_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd2_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd3_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd4_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_marker_muxd0_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_marker_muxd1_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_marker_muxd2_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_marker_muxd3_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dpso_marker_muxd4_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd0_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd1_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd2_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd3_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd4_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd0_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd1_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd2_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd3_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd0_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd1_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd2_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd3_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd4_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd0_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd3_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd4_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd0_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd2_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd2_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd3_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd4_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd0_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd1_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd2_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd3_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd4_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd0_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd1_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd2_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd3_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd4_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd0_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd1_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd2_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd3_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd4_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd0_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd1_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd2_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd3_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd4_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd2_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd3_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd4_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd0_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd2_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd0_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd0_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd1_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd2_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd3_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd4_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd0_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd1_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd2_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd3_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd4_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd4_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd0_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd1_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd2_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd3_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd4_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd0_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd1_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd2_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd3_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd4_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_lock_thresh_muxd0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_lock_thresh_muxd1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_lock_thresh_muxd2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_lock_thresh_muxd3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_lock_thresh_muxd4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd0_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd1_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd2_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd3_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd4_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchn_offset_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchn_offset_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchn_offset_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchn_offset_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchn_offset_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchp_offset_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchp_offset_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchp_offset_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchp_offset_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_notchp_offset_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_bypass_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_bypass_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_bypass_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_bypass_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_bypass_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd4_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_step_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_step_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_step_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_step_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ramp_step_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd0_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd1_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd2_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd3_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd4_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd2_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd0_attr == 8'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd1_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd2_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd3_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd4_attr == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd0_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd1_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd2_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd3_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd4_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd2_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd3_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd4_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_fll_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_fll_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_fll_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_fll_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_fll_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_pll_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_pll_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_pll_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_pll_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_stay_pll_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd0_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd1_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd2_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd4_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd0_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd1_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd3_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd4_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_temp_track_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_temp_track_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_temp_track_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_temp_track_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_temp_track_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd0_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd1_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd2_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd3_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd4_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd0_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd1_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd2_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd3_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd4_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd0_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd1_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd2_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd3_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd4_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd0_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd1_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd2_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd3_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd4_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bb_gain_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bb_gain_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bb_gain_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bb_gain_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bb_gain_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbinlock_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbinlock_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbinlock_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbinlock_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbinlock_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbthresh_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbthresh_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbthresh_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbthresh_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_bbthresh_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrlhext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrlhext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrlhext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrlhext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrlhext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrllext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrllext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrllext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrllext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_cloadctrllext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_muxd0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_muxd1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_muxd2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_muxd3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_muxd4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcoditheren_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcoditheren_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcoditheren_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcoditheren_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcoditheren_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofine_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofine_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofine_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofine_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofine_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofinedftsel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofinedftsel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofinedftsel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofinedftsel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dcofinedftsel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dither_value_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dither_value_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dither_value_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dither_value_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_dither_value_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_earlylock_criteria_muxd0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_earlylock_criteria_muxd1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_earlylock_criteria_muxd2_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_earlylock_criteria_muxd3_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_earlylock_criteria_muxd4_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_frac_muxd0_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_frac_muxd1_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_frac_muxd2_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_frac_muxd3_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_frac_muxd4_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd0_attr == 9'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd1_attr == 9'd45
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd2_attr == 9'd27
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd3_attr == 9'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd4_attr == 9'd216
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdgain_muxd0_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdgain_muxd1_attr == 8'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdgain_muxd2_attr == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdgain_muxd3_attr == 8'd23
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_feedfwrdgain_muxd4_attr == 8'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fracnen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fracnen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fracnen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fracnen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_fracnen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_lock_criteria_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_lock_criteria_muxd1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_lock_criteria_muxd2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_lock_criteria_muxd3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_lock_criteria_muxd4_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_regen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_regen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_regen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_regen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllc_regen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllock_sel_muxd0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllock_sel_muxd1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllock_sel_muxd2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllock_sel_muxd3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_plllock_sel_muxd4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdc_fine_res_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdc_fine_res_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdc_fine_res_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdc_fine_res_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdc_fine_res_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdccalexten_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdccalexten_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdccalexten_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdccalexten_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdccalexten_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcroen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcroen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcroen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcroen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcroen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L2_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcsel_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcsel_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcsel_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcsel_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdcsel_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdctargetcnt_muxd0_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdctargetcnt_muxd1_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdctargetcnt_muxd2_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdctargetcnt_muxd3_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tdctargetcnt_muxd4_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tribufctrlext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tribufctrlext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tribufctrlext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tribufctrlext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l2_cfg_pllloader_synthlc_o_tribufctrlext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_done_pwr2_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_apb_dwmask_muxd0_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_apb_dwmask_muxd1_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_apb_dwmask_muxd2_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_apb_dwmask_muxd3_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_apb_dwmask_muxd4_attr == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_a2f_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_a2f_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_a2f_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_a2f_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_a2f_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_A2F_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux0_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_anamonmux1_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_dtr_const_zeta_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_DTR_CONST_ZETA_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boost_fine_const_zeta_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_BOOST_FINE_CONST_ZETA_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd0_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd1_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd2_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd3_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_boostgain_maxcnt_muxd4_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_calib_comp_out_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CALIB_COMP_OUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_cb56_lane32div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CB56_LANE32DIV_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_cb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_CB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_clkouten_lane_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_CLKOUTEN_LANE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd0_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd1_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd2_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd3_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_cnt_max_muxd4_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_max_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd0_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd1_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd2_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd3_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_coarse_loop_gscale_min_muxd4_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrd_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcocoarse_ovrden_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOCOARSE_OVRDEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_mode_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DCOSETTLE_MODE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd0_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd1_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd2_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd3_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dcosettle_time_muxd4_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_cnt_restart_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_CNT_RESTART_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dft_freq_meas_enable_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFT_FREQ_MEAS_ENABLE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_disable_dft_timer_ovrd_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrd_offset_ovr_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrddir_ovr_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_FEEDFWRDDIR_OVR_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd0_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd1_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd2_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd3_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_feedfwrdphase_ovr_val_muxd4_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_dir_ovr_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_DIR_OVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_enable_ovr_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_ENABLE_OVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_toggle_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DFX_RAMP_TOGGLE_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dfx_ramp_val_ovr_muxd4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_bypass_mode_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DPSO_BYPASS_MODE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_marker_muxd0_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_marker_muxd1_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_marker_muxd2_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_marker_muxd3_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dpso_marker_muxd4_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_EARLYLOCK_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_earlylock_timer_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_final_code_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_FINAL_CODE_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd0_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd1_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd2_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd3_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_step_muxd4_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd0_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd1_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd2_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd3_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_boost_val_muxd4_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd0_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd1_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd2_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd3_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_int_coeff_muxd4_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrd_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_ovrden_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_DTR_OVRDEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_step_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd0_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd2_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd3_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_boost_val_muxd4_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd0_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd2_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_dtr_prop_coeff_muxd4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_earlylock_thresh_muxd4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_en_peak_sense_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_EN_PEAK_SENSE_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_clkgate_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_CLKGATE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fbdiv_rat0p5_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FBDIV_RAT0P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_dtr_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_DTR_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_filter_boostfade_fine_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FILTER_BOOSTFADE_FINE_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd2_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd3_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine2dtr_ratio_muxd4_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_first_boost_repeat_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd0_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd1_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd2_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd3_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_high_limit_muxd4_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd0_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd1_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd2_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd3_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_step_muxd4_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd0_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd1_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd2_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd3_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_boost_val_muxd4_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd0_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd1_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd2_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd3_attr == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_int_coeff_muxd4_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd0_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd1_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd2_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd3_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_low_limit_muxd4_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_modulation_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FINE_MODULATION_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd0_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_step_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd0_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd1_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd2_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd3_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_boost_val_muxd4_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd0_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd1_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd2_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd3_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fine_prop_coeff_muxd4_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_kvcc_done_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_KVCC_DONE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_tdcdone_at_afcdone_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_TDCDONE_AT_AFCDONE_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_force_vreglpfbyp_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FORCE_VREGLPFBYP_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FRACN_SD_STEP_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fracn_sd_step_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_full_range_afc_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FULL_RANGE_AFC_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_force_vreg_cal_done_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_FORCE_VREG_CAL_DONE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_FW_VREG_ACCUM_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd0_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd1_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd2_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd3_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_fw_vreg_accum_val_muxd4_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_gaincal_update_rate_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vpeak_comb_fb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VPEAK_COMB_FB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_inv_vreg_comb_fb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_INV_VREG_COMB_FB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_bin_code_limit_sel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_calib_by_fw_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CALIB_BY_FW_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_CODE_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd0_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd1_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd2_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd3_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_code_val_muxd4_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_inv_polarity_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_INV_POLARITY_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd0_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_measure_maxcnt_muxd4_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd0_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd1_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd2_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd3_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_settle_maxcnt_muxd4_attr == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_ovrd_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_OVRD_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcc_vreg_offset_en_val_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_KVCC_VREG_OFFSET_EN_VAL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd0_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd1_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd2_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd3_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_kvcccalib_vreg_offset_muxd4_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_lock_thresh_muxd0_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_lock_thresh_muxd1_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_lock_thresh_muxd2_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_lock_thresh_muxd3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_lock_thresh_muxd4_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd0_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd1_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd2_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd3_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_locktimer_maxcnt_muxd4_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_modulation_toggle_delay_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchn_offset_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchn_offset_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchn_offset_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchn_offset_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchn_offset_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchp_offset_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchp_offset_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchp_offset_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchp_offset_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_notchp_offset_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_del_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX0_DEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux0_sel_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_del_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_OBSMUX1_DEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_obsmux1_sel_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334_divsel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs3334div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS3334DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pcs40div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PCS40DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_bypass_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_bypass_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_bypass_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_bypass_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_bypass_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLL_BYPASS_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_pll_refclkreg_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_plllock_state_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_PLLLOCK_STATE_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_prediv_ratio_muxd4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_ctr_delay_muxd4_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_step_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_step_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_step_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_step_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ramp_step_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_rat0p5_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REF156DIV_RAT0P5_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd0_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd1_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd2_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd3_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ref156div_ratio_muxd4_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk100div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK100DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk156div_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_REFCLK156DIV_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd2_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cnt_limit_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd0_attr == 8'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd1_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd2_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd3_attr == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_refclk_cycles_per_1us_maxcnt_muxd4_attr == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDIV_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddiv_ratio_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sddtr_clk_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SDDTR_CLK_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_sigma_delta2_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SIGMA_DELTA2_SEL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_skip_second_afc_calib_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SKIP_SECOND_AFC_CALIB_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd0_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd1_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd2_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd3_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_spare_dig2ana_muxd4_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ss_comp_out_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SS_COMP_OUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_ctr_delay_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd2_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd3_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_ramp_step_muxd4_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_ssc_track_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_SSC_TRACK_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_fll_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_fll_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_fll_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_fll_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_fll_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_FLL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_pll_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_pll_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_pll_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_pll_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_stay_pll_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_STAY_PLL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdc_bb_input_sel_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDC_BB_INPUT_SEL_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd0_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd1_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd2_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd3_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_cnt_limit_muxd4_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcbbpd_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCBBPD_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TDCPE_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcpe_modulation_val_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd0_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd1_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd2_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd3_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_tdcrefclkcnt_muxd4_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_temp_track_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_temp_track_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_temp_track_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_temp_track_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_temp_track_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_TEMP_TRACK_EN_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_visa8to1_2obs_sel_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_dac_modulation_en_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_CFG_VREG_DAC_MODULATION_EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd0_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd1_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd2_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd3_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_final_gain_maxcnt_muxd4_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd0_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd1_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd2_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd3_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_gain_maxcnt_muxd4_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_init_gain_muxd4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd0_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd1_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd2_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd3_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_loopen_maxcnt_muxd4_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd0_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd1_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd2_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd3_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vreg_swing_peak_ref_ctl_bin_muxd4_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd0_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd1_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd2_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd3_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_average_cnt_muxd4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_cfg_vregcomp_cmnsel_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bb_gain_muxd0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bb_gain_muxd1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bb_gain_muxd2_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bb_gain_muxd3_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bb_gain_muxd4_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbinlock_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbinlock_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbinlock_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbinlock_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbinlock_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_BBINLOCK_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbthresh_muxd0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbthresh_muxd1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbthresh_muxd2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbthresh_muxd3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_bbthresh_muxd4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrlhext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrlhext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrlhext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrlhext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrlhext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrllext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrllext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrllext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrllext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_cloadctrllext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_muxd0_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_muxd1_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_muxd2_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_muxd3_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_muxd4_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcocoarse_ovrd_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCOCOARSE_OVRD_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcoditheren_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcoditheren_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcoditheren_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcoditheren_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcoditheren_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DCODITHEREN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofine_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofine_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofine_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofine_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofine_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofinedftsel_muxd0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofinedftsel_muxd1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofinedftsel_muxd2_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofinedftsel_muxd3_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dcofinedftsel_muxd4_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dfx_tdc_disable_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_DFX_TDC_DISABLE_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dither_value_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dither_value_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dither_value_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dither_value_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_dither_value_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_earlylock_criteria_muxd0_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_earlylock_criteria_muxd1_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_earlylock_criteria_muxd2_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_earlylock_criteria_muxd3_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_earlylock_criteria_muxd4_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_frac_muxd0_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_frac_muxd1_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_frac_muxd2_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_frac_muxd3_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_frac_muxd4_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd0_attr == 9'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd1_attr == 9'd45
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd2_attr == 9'd27
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd3_attr == 9'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_intgr_muxd4_attr == 9'd216
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fbdiv_strobe_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FBDIV_STROBE_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_EN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdcal_pause_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FEEDFWRDCAL_PAUSE_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdgain_muxd0_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdgain_muxd1_attr == 8'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdgain_muxd2_attr == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdgain_muxd3_attr == 8'd23
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_feedfwrdgain_muxd4_attr == 8'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fracnen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fracnen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fracnen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fracnen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_fracnen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_FRACNEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_lock_criteria_muxd0_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_lock_criteria_muxd1_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_lock_criteria_muxd2_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_lock_criteria_muxd3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_lock_criteria_muxd4_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_mode_ctrl_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MODE_CTRL_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_pll_reg_resetb_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLL_REG_RESETB_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd0_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd1_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_en_mode_ctrl_muxd4_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_regen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_regen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_regen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_regen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllc_regen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_PLLLC_REGEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllock_sel_muxd0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllock_sel_muxd1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllock_sel_muxd2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllock_sel_muxd3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_plllock_sel_muxd4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdc_fine_res_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdc_fine_res_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdc_fine_res_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdc_fine_res_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdc_fine_res_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDC_FINE_RES_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdccalexten_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdccalexten_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdccalexten_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdccalexten_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdccalexten_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCCALEXTEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcdc_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCDC_EN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcovccorr_en_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCOVCCORR_EN_H_MUXD4_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcroen_h_muxd0_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcroen_h_muxd1_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcroen_h_muxd2_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcroen_h_muxd3_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcroen_h_muxd4_attr == SERDES_IP_PLL_CFG_LOADER_L3_CFG_PLLLOADER_SYNTHLC_O_TDCROEN_H_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcsel_muxd0_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcsel_muxd1_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcsel_muxd2_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcsel_muxd3_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdcsel_muxd4_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdctargetcnt_muxd0_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdctargetcnt_muxd1_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdctargetcnt_muxd2_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdctargetcnt_muxd3_attr == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tdctargetcnt_muxd4_attr == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tribufctrlext_muxd0_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tribufctrlext_muxd1_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tribufctrlext_muxd2_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tribufctrlext_muxd3_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_pll_cfg_loader_l3_cfg_pllloader_synthlc_o_tribufctrlext_muxd4_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_a2f_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_clkouten_cb_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_clkouten_lane_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_en_peak_sense_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_obsmux0_del_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_obsmux1_del_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_pcs40div_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_pll_bypass_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_refclk100div_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_refclk156div_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_sddiv_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_spare_dig2ana_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_ssc_track_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_stay_fll_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_stay_pll_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_temp_track_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_bbinlock_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_dcoditheren_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_fracnen_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_pll_reg_resetb_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_plllc_regen_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_tdc_fine_res_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_tdccalexten_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_tdcdc_en_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_tdcroen_h_attr == SERDES_IP_PLLLCFAST_L0_CFG_PLLLCFAST_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l0_cfg_plllcfast_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_a2f_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_clkouten_cb_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_clkouten_lane_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_en_peak_sense_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_obsmux0_del_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_obsmux1_del_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_pcs40div_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_pll_bypass_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_refclk100div_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_refclk156div_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_sddiv_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_spare_dig2ana_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_ssc_track_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_stay_fll_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_stay_pll_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_temp_track_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_bbinlock_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_dcoditheren_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_fracnen_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_pll_reg_resetb_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_plllc_regen_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_tdc_fine_res_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_tdccalexten_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_tdcdc_en_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_tdcroen_h_attr == SERDES_IP_PLLLCFAST_L1_CFG_PLLLCFAST_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l1_cfg_plllcfast_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_a2f_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_clkouten_cb_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_clkouten_lane_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_en_peak_sense_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_obsmux0_del_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_obsmux1_del_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_pcs40div_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_pll_bypass_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_refclk100div_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_refclk156div_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_sddiv_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_spare_dig2ana_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_ssc_track_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_stay_fll_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_stay_pll_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_temp_track_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_bbinlock_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_dcoditheren_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_fracnen_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_pll_reg_resetb_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_plllc_regen_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_tdc_fine_res_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_tdccalexten_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_tdcdc_en_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_tdcroen_h_attr == SERDES_IP_PLLLCFAST_L2_CFG_PLLLCFAST_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l2_cfg_plllcfast_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_a2f_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_clkouten_cb_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_clkouten_lane_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_en_peak_sense_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_obsmux0_del_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_obsmux1_del_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_pcs40div_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_pll_bypass_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_refclk100div_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_refclk156div_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_sddiv_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_spare_dig2ana_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_ssc_track_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_stay_fll_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_stay_pll_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_temp_track_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_bbinlock_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_dcoditheren_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_fracnen_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_pll_reg_resetb_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_plllc_regen_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_tdc_fine_res_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_tdccalexten_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_tdcdc_en_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_tdcroen_h_attr == SERDES_IP_PLLLCFAST_L3_CFG_PLLLCFAST_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcfast_l3_cfg_plllcfast_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_a2f_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_clkouten_cb_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_clkouten_lane_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_en_peak_sense_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_obsmux0_del_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_obsmux1_del_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_pcs40div_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_pll_bypass_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_refclk100div_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_refclk156div_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_sddiv_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_spare_dig2ana_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_ssc_track_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_stay_fll_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_stay_pll_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_temp_track_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_bbinlock_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_dcoditheren_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_fracnen_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_pll_reg_resetb_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_plllc_regen_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_tdc_fine_res_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_tdccalexten_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_tdcdc_en_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_tdcroen_h_attr == SERDES_IP_PLLLCMED_L0_CFG_PLLLCMED_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l0_cfg_plllcmed_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_a2f_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_clkouten_cb_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_clkouten_lane_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_en_peak_sense_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_obsmux0_del_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_obsmux1_del_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_pcs40div_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_pll_bypass_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_refclk100div_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_refclk156div_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_sddiv_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_spare_dig2ana_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_ssc_track_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_stay_fll_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_stay_pll_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_temp_track_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_bbinlock_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_dcoditheren_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_fracnen_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_pll_reg_resetb_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_plllc_regen_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_tdc_fine_res_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_tdccalexten_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_tdcdc_en_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_tdcroen_h_attr == SERDES_IP_PLLLCMED_L1_CFG_PLLLCMED_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l1_cfg_plllcmed_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_a2f_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_clkouten_cb_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_clkouten_lane_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_en_peak_sense_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_obsmux0_del_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_obsmux1_del_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_pcs40div_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_pll_bypass_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_refclk100div_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_refclk156div_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_sddiv_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_spare_dig2ana_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_ssc_track_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_stay_fll_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_stay_pll_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_temp_track_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_bbinlock_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_dcoditheren_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_fracnen_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_pll_reg_resetb_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_plllc_regen_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_tdc_fine_res_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_tdccalexten_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_tdcdc_en_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_tdcroen_h_attr == SERDES_IP_PLLLCMED_L2_CFG_PLLLCMED_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l2_cfg_plllcmed_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_a2f_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_clkouten_cb_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_clkouten_lane_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_en_peak_sense_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_obsmux0_del_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_obsmux1_del_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_pcs40div_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_pll_bypass_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_refclk100div_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_refclk156div_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_sddiv_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_spare_dig2ana_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_ssc_track_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_stay_fll_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_stay_pll_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_temp_track_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_bbinlock_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_dcoditheren_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_fracnen_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_pll_reg_resetb_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_plllc_regen_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_tdc_fine_res_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_tdccalexten_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_tdcdc_en_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_tdcroen_h_attr == SERDES_IP_PLLLCMED_L3_CFG_PLLLCMED_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcmed_l3_cfg_plllcmed_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_a2f_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_clkouten_cb_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_clkouten_lane_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_en_peak_sense_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_obsmux0_del_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_obsmux1_del_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_pcs40div_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_pll_bypass_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_refclk100div_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_refclk156div_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_sddiv_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_spare_dig2ana_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_ssc_track_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_stay_fll_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_stay_pll_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_temp_track_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_bbinlock_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_dcoditheren_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_fracnen_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_pll_reg_resetb_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_plllc_regen_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_tdc_fine_res_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_tdccalexten_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_tdcdc_en_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_tdcroen_h_attr == SERDES_IP_PLLLCSLOW_L0_CFG_PLLLCSLOW_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l0_cfg_plllcslow_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_a2f_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_clkouten_cb_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_clkouten_lane_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_en_peak_sense_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_obsmux0_del_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_obsmux1_del_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_pcs40div_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_pll_bypass_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_refclk100div_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_refclk156div_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_sddiv_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_spare_dig2ana_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_ssc_track_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_stay_fll_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_stay_pll_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_temp_track_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_bbinlock_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_dcoditheren_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_fracnen_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_pll_reg_resetb_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_plllc_regen_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_tdc_fine_res_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_tdccalexten_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_tdcdc_en_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_tdcroen_h_attr == SERDES_IP_PLLLCSLOW_L1_CFG_PLLLCSLOW_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l1_cfg_plllcslow_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_a2f_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_clkouten_cb_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_clkouten_lane_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_en_peak_sense_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_obsmux0_del_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_obsmux1_del_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_pcs40div_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_pll_bypass_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_refclk100div_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_refclk156div_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_sddiv_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_spare_dig2ana_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_ssc_track_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_stay_fll_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_stay_pll_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_temp_track_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_bbinlock_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_dcoditheren_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_fracnen_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_pll_reg_resetb_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_plllc_regen_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_tdc_fine_res_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_tdccalexten_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_tdcdc_en_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_tdcroen_h_attr == SERDES_IP_PLLLCSLOW_L2_CFG_PLLLCSLOW_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l2_cfg_plllcslow_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_a2f_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_A2F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_anamonmux0_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_anamonmux1_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_boost_dtr_const_zeta_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_BOOST_DTR_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_boost_fine_const_zeta_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_BOOST_FINE_CONST_ZETA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_boostgain_maxcnt_attr == 10'd512
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_calib_comp_out_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_CALIB_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_cb56_lane32div_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_CB56_LANE32DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_clkouten_cb_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_CLKOUTEN_CB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_clkouten_lane_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_CLKOUTEN_LANE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_coarse_loop_gscale_cnt_max_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_coarse_loop_gscale_max_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_coarse_loop_gscale_min_attr == 4'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dcocoarse_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dcocoarse_ovrden_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DCOCOARSE_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dcosettle_mode_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DCOSETTLE_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dcosettle_time_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dft_cnt_restart_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DFT_CNT_RESTART_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dft_freq_meas_enable_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DFT_FREQ_MEAS_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dfx_disable_dft_timer_ovrd_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DFX_DISABLE_DFT_TIMER_OVRD_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dfx_disable_dft_timer_ovrd_val_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DFX_DISABLE_DFT_TIMER_OVRD_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dfx_feedfwrd_offset_ovr_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DFX_FEEDFWRD_OFFSET_OVR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dfx_feedfwrddir_ovr_val_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DFX_FEEDFWRDDIR_OVR_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dfx_feedfwrdphase_ovr_val_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dfx_ramp_dir_ovr_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DFX_RAMP_DIR_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dfx_ramp_enable_ovr_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DFX_RAMP_ENABLE_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dfx_ramp_toggle_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DFX_RAMP_TOGGLE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dfx_ramp_val_ovr_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dpso_bypass_mode_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DPSO_BYPASS_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dpso_marker_attr == 16'd43690
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_earlylock_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DTR_EARLYLOCK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_earlylock_timer_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_final_code_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DTR_FINAL_CODE_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_int_coeff_boost_val_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_modulation_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DTR_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_ovrd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_ovrden_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_DTR_OVRDEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_prop_coeff_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_dtr_prop_coeff_boost_val_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_earlylock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_en_peak_sense_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_EN_PEAK_SENSE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fbdiv_clkgate_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FBDIV_CLKGATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fbdiv_rat0p5_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FBDIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_filter_boostfade_dtr_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FILTER_BOOSTFADE_DTR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_filter_boostfade_fine_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FILTER_BOOSTFADE_FINE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine2dtr_ratio_attr == 6'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_first_boost_repeat_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_high_limit_attr == 6'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_int_coeff_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_int_coeff_boost_step_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_int_coeff_boost_val_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_low_limit_attr == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_modulation_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FINE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_modulation_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FINE_MODULATION_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_prop_coeff_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_prop_coeff_boost_step_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fine_prop_coeff_boost_val_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_force_kvcc_done_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FORCE_KVCC_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_force_tdcdone_at_afcdone_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FORCE_TDCDONE_AT_AFCDONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_force_vreglpfbyp_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FORCE_VREGLPFBYP_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fracn_sd_step_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fracn_sd_step_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FRACN_SD_STEP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_full_range_afc_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FULL_RANGE_AFC_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fw_force_vreg_cal_done_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FW_FORCE_VREG_CAL_DONE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fw_vreg_accum_ovrd_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_FW_VREG_ACCUM_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_fw_vreg_accum_val_attr == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_gaincal_update_rate_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_inv_vpeak_comb_fb_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_INV_VPEAK_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_inv_vreg_comb_fb_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_INV_VREG_COMB_FB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcc_bin_code_limit_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcc_calib_by_fw_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_KVCC_CALIB_BY_FW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcc_code_ovrd_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_KVCC_CODE_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcc_code_val_attr == 9'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcc_inv_polarity_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_KVCC_INV_POLARITY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcc_measure_maxcnt_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcc_settle_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcc_vreg_offset_en_ovrd_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_KVCC_VREG_OFFSET_EN_OVRD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcc_vreg_offset_en_val_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_KVCC_VREG_OFFSET_EN_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_kvcccalib_vreg_offset_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_lock_thresh_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_locktimer_maxcnt_attr == 14'd3968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_modulation_toggle_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_notchn_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_notchp_offset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_obsmux0_del_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_OBSMUX0_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_obsmux0_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_obsmux1_del_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_OBSMUX1_DEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_obsmux1_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_pcs3334_divsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_pcs3334div_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_PCS3334DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_pcs40div_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_PCS40DIV_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_pll_bypass_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_PLL_BYPASS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_pll_refclkreg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_plllock_state_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_PLLLOCK_STATE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_prediv_ratio_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_ramp_ctr_delay_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_ramp_step_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_ref156div_rat0p5_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_REF156DIV_RAT0P5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_ref156div_ratio_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_refclk100div_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_REFCLK100DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_refclk156div_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_REFCLK156DIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_refclk_cnt_limit_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_refclk_cycles_per_1us_maxcnt_attr == 8'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_sddiv_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_SDDIV_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_sddiv_ratio_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_sddtr_clk_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_SDDTR_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_sigma_delta2_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_SIGMA_DELTA2_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_skip_second_afc_calib_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_SKIP_SECOND_AFC_CALIB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_spare_dig2ana_attr == 18'd4096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_ss_comp_out_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_SS_COMP_OUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_ssc_ramp_ctr_delay_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_ssc_ramp_step_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_ssc_track_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_SSC_TRACK_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_stay_fll_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_STAY_FLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_stay_pll_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_STAY_PLL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_tdc_bb_input_sel_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_TDC_BB_INPUT_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_tdcbbpd_cnt_limit_attr == 4'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_tdcbbpd_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_TDCBBPD_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_tdcpe_modulation_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_TDCPE_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_tdcpe_modulation_val_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_tdcrefclkcnt_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_temp_track_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_TEMP_TRACK_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_visa8to1_2obs_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_visa_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_visa_lane0_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_visa_lane1_sel_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_vreg_dac_modulation_en_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_CFG_VREG_DAC_MODULATION_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_vreg_final_gain_maxcnt_attr == 8'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_vreg_gain_maxcnt_attr == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_vreg_init_gain_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_vreg_loopen_maxcnt_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_vreg_swing_peak_ref_ctl_bin_attr == 5'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_vregcomp_average_cnt_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_cfg_vregcomp_cmnsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_bb_gain_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_bbinlock_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_BBINLOCK_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_bbthresh_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_cloadctrlhext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_cloadctrllext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_dcocoarse_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_dcocoarse_ovrd_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_DCOCOARSE_OVRD_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_dcoditheren_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_DCODITHEREN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_dcofine_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_dcofinedftsel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_dfx_tdc_disable_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_DFX_TDC_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_dither_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_earlylock_criteria_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_fbdiv_frac_attr == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_fbdiv_intgr_attr == 9'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_fbdiv_strobe_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_FBDIV_STROBE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_feedfwrdcal_en_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_FEEDFWRDCAL_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_feedfwrdcal_pause_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_FEEDFWRDCAL_PAUSE_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_feedfwrdgain_attr == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_fracnen_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_FRACNEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_lock_criteria_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_pll_reg_resetb_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_PLL_REG_RESETB_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_pll_reg_resetb_mode_ctrl_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_PLL_REG_RESETB_MODE_CTRL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_plllc_en_mode_ctrl_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_plllc_regen_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_PLLLC_REGEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_plllock_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_tdc_fine_res_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_TDC_FINE_RES_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_tdccalexten_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_TDCCALEXTEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_tdcdc_en_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_TDCDC_EN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_tdcovccorr_en_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_TDCOVCCORR_EN_H_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_tdcroen_h_attr == SERDES_IP_PLLLCSLOW_L3_CFG_PLLLCSLOW_O_TDCROEN_H_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_tdcsel_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_tdctargetcnt_attr == 8'd58
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_plllcslow_l3_cfg_plllcslow_o_tribufctrlext_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_flavor_table_attr == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_flavor_table_en_attr == SERDES_IP_RX_FLEX_L0_CFG_FLX_FLAVOR_TABLE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_force_frame_lock_attr == SERDES_IP_RX_FLEX_L0_CFG_FLX_FORCE_FRAME_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_freeze_in_state_attr == SERDES_IP_RX_FLEX_L0_CFG_FLX_FREEZE_IN_STATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_01_attr == 32'd65537
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_02_attr == 32'd2147516416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_03_attr == 32'd2181169152
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_04_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_05_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_06_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_07_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_08_attr == 32'd16384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_09_attr == 32'd131072
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_10_attr == 32'd2416050176
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_11_attr == 32'd33554432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_12_attr == 32'd1075838976
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_13_attr == 32'd301989888
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_14_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_15_attr == 32'd2181169152
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_16_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_17_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_18_attr == 32'd302006272
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_19_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_20_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_21_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_22_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_23_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_24_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_25_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_26_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_27_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_28_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_29_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_30_attr == 32'd33587200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_mask_31_attr == 32'd1107329024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_02_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_03_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_10_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_12_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_13_attr == 5'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_15_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_18_attr == 5'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_ir_state_31_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_02_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_03_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_10_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_11_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_12_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_13_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_15_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_18_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_30_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_next_lpcnt_state_31_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_one_state_inc_pulse_attr == SERDES_IP_RX_FLEX_L0_CFG_FLX_ONE_STATE_INC_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_00_attr == 32'd1056783
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_01_attr == 32'd9510943
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_02_attr == 32'd9502735
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_03_attr == 32'd9437199
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_04_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_05_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_06_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_07_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_08_attr == 32'd14680079
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_09_attr == 32'd26017807
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_10_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_11_attr == 32'd9502735
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_12_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_13_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_14_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_15_attr == 32'd25493519
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_16_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_17_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_18_attr == 32'd14942223
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_19_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_20_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_21_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_22_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_23_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_24_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_25_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_26_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_27_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_28_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_29_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_30_attr == 32'd1376271
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl1_31_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_00_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_01_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_02_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_03_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_04_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_05_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_06_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_07_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_08_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_09_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_10_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_11_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_12_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_13_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_14_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_15_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_16_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_17_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_18_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_19_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_20_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_21_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_22_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_23_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_24_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_25_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_26_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_27_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_28_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_29_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_30_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_out_ctrl_31_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_state_force_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_state_force_value_en_attr == SERDES_IP_RX_FLEX_L0_CFG_FLX_STATE_FORCE_VALUE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_flx_stop_tmr_in_handshake_attr == SERDES_IP_RX_FLEX_L0_CFG_FLX_STOP_TMR_IN_HANDSHAKE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_00_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_00_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_01_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_01_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_02_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_02_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_03_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_03_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_04_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_04_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_05_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_05_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_06_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_06_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_07_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_07_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_08_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_08_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_09_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_09_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_10_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_10_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_11_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_12_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_13_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_14_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_15_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_15_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_16_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_17_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_18_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_19_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_19_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_20_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_20_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_21_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_21_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_22_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_22_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_23_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_23_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_24_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_24_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_25_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_25_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_26_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_26_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_27_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_27_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_28_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_28_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_29_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_29_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_30_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_30_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_en_31_attr == SERDES_IP_RX_FLEX_L0_CFG_MAX_TIMER_EN_31_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_02_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_03_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_10_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_12_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_13_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_15_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_18_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_max_timer_value_31_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_00_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_00_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_01_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_01_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_02_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_02_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_03_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_03_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_04_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_04_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_05_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_05_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_06_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_06_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_07_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_07_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_08_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_08_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_09_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_09_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_10_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_11_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_12_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_13_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_14_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_15_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_16_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_17_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_18_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_19_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_19_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_20_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_20_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_21_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_21_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_22_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_22_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_23_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_23_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_24_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_24_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_25_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_25_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_26_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_26_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_27_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_27_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_28_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_28_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_29_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_29_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_30_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_30_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_start_event_31_attr == SERDES_IP_RX_FLEX_L0_CFG_MIN_TIMER_START_EVENT_31_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_00_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_02_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_03_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_10_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_12_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_13_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_15_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_18_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l0_cfg_min_timer_value_31_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_flavor_table_attr == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_flavor_table_en_attr == SERDES_IP_RX_FLEX_L1_CFG_FLX_FLAVOR_TABLE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_force_frame_lock_attr == SERDES_IP_RX_FLEX_L1_CFG_FLX_FORCE_FRAME_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_freeze_in_state_attr == SERDES_IP_RX_FLEX_L1_CFG_FLX_FREEZE_IN_STATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_01_attr == 32'd65537
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_02_attr == 32'd2147516416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_03_attr == 32'd2181169152
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_04_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_05_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_06_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_07_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_08_attr == 32'd16384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_09_attr == 32'd131072
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_10_attr == 32'd2416050176
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_11_attr == 32'd33554432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_12_attr == 32'd1075838976
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_13_attr == 32'd301989888
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_14_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_15_attr == 32'd2181169152
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_16_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_17_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_18_attr == 32'd302006272
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_19_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_20_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_21_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_22_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_23_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_24_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_25_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_26_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_27_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_28_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_29_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_30_attr == 32'd33587200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_mask_31_attr == 32'd1107329024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_02_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_03_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_10_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_12_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_13_attr == 5'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_15_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_18_attr == 5'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_ir_state_31_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_02_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_03_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_10_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_11_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_12_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_13_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_15_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_18_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_30_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_next_lpcnt_state_31_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_one_state_inc_pulse_attr == SERDES_IP_RX_FLEX_L1_CFG_FLX_ONE_STATE_INC_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_00_attr == 32'd1056783
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_01_attr == 32'd9510943
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_02_attr == 32'd9502735
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_03_attr == 32'd9437199
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_04_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_05_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_06_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_07_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_08_attr == 32'd14680079
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_09_attr == 32'd26017807
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_10_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_11_attr == 32'd9502735
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_12_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_13_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_14_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_15_attr == 32'd25493519
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_16_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_17_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_18_attr == 32'd14942223
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_19_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_20_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_21_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_22_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_23_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_24_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_25_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_26_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_27_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_28_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_29_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_30_attr == 32'd1376271
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl1_31_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_00_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_01_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_02_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_03_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_04_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_05_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_06_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_07_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_08_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_09_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_10_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_11_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_12_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_13_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_14_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_15_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_16_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_17_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_18_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_19_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_20_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_21_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_22_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_23_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_24_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_25_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_26_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_27_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_28_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_29_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_30_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_out_ctrl_31_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_state_force_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_state_force_value_en_attr == SERDES_IP_RX_FLEX_L1_CFG_FLX_STATE_FORCE_VALUE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_flx_stop_tmr_in_handshake_attr == SERDES_IP_RX_FLEX_L1_CFG_FLX_STOP_TMR_IN_HANDSHAKE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_00_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_00_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_01_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_01_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_02_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_02_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_03_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_03_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_04_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_04_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_05_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_05_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_06_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_06_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_07_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_07_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_08_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_08_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_09_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_09_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_10_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_10_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_11_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_12_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_13_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_14_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_15_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_15_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_16_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_17_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_18_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_19_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_19_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_20_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_20_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_21_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_21_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_22_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_22_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_23_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_23_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_24_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_24_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_25_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_25_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_26_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_26_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_27_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_27_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_28_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_28_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_29_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_29_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_30_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_30_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_en_31_attr == SERDES_IP_RX_FLEX_L1_CFG_MAX_TIMER_EN_31_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_02_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_03_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_10_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_12_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_13_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_15_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_18_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_max_timer_value_31_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_00_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_00_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_01_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_01_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_02_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_02_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_03_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_03_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_04_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_04_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_05_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_05_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_06_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_06_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_07_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_07_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_08_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_08_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_09_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_09_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_10_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_11_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_12_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_13_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_14_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_15_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_16_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_17_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_18_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_19_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_19_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_20_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_20_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_21_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_21_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_22_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_22_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_23_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_23_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_24_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_24_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_25_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_25_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_26_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_26_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_27_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_27_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_28_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_28_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_29_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_29_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_30_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_30_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_start_event_31_attr == SERDES_IP_RX_FLEX_L1_CFG_MIN_TIMER_START_EVENT_31_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_00_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_02_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_03_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_10_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_12_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_13_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_15_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_18_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l1_cfg_min_timer_value_31_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_flavor_table_attr == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_flavor_table_en_attr == SERDES_IP_RX_FLEX_L2_CFG_FLX_FLAVOR_TABLE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_force_frame_lock_attr == SERDES_IP_RX_FLEX_L2_CFG_FLX_FORCE_FRAME_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_freeze_in_state_attr == SERDES_IP_RX_FLEX_L2_CFG_FLX_FREEZE_IN_STATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_01_attr == 32'd65537
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_02_attr == 32'd2147516416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_03_attr == 32'd2181169152
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_04_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_05_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_06_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_07_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_08_attr == 32'd16384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_09_attr == 32'd131072
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_10_attr == 32'd2416050176
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_11_attr == 32'd33554432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_12_attr == 32'd1075838976
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_13_attr == 32'd301989888
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_14_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_15_attr == 32'd2181169152
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_16_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_17_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_18_attr == 32'd302006272
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_19_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_20_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_21_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_22_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_23_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_24_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_25_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_26_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_27_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_28_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_29_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_30_attr == 32'd33587200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_mask_31_attr == 32'd1107329024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_02_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_03_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_10_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_12_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_13_attr == 5'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_15_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_18_attr == 5'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_ir_state_31_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_02_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_03_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_10_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_11_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_12_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_13_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_15_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_18_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_30_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_next_lpcnt_state_31_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_one_state_inc_pulse_attr == SERDES_IP_RX_FLEX_L2_CFG_FLX_ONE_STATE_INC_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_00_attr == 32'd1056783
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_01_attr == 32'd9510943
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_02_attr == 32'd9502735
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_03_attr == 32'd9437199
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_04_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_05_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_06_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_07_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_08_attr == 32'd14680079
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_09_attr == 32'd26017807
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_10_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_11_attr == 32'd9502735
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_12_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_13_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_14_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_15_attr == 32'd25493519
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_16_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_17_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_18_attr == 32'd14942223
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_19_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_20_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_21_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_22_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_23_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_24_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_25_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_26_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_27_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_28_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_29_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_30_attr == 32'd1376271
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl1_31_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_00_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_01_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_02_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_03_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_04_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_05_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_06_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_07_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_08_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_09_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_10_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_11_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_12_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_13_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_14_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_15_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_16_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_17_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_18_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_19_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_20_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_21_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_22_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_23_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_24_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_25_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_26_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_27_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_28_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_29_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_30_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_out_ctrl_31_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_state_force_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_state_force_value_en_attr == SERDES_IP_RX_FLEX_L2_CFG_FLX_STATE_FORCE_VALUE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_flx_stop_tmr_in_handshake_attr == SERDES_IP_RX_FLEX_L2_CFG_FLX_STOP_TMR_IN_HANDSHAKE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_00_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_00_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_01_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_01_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_02_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_02_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_03_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_03_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_04_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_04_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_05_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_05_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_06_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_06_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_07_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_07_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_08_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_08_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_09_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_09_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_10_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_10_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_11_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_12_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_13_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_14_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_15_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_15_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_16_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_17_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_18_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_19_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_19_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_20_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_20_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_21_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_21_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_22_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_22_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_23_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_23_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_24_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_24_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_25_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_25_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_26_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_26_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_27_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_27_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_28_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_28_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_29_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_29_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_30_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_30_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_en_31_attr == SERDES_IP_RX_FLEX_L2_CFG_MAX_TIMER_EN_31_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_02_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_03_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_10_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_12_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_13_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_15_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_18_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_max_timer_value_31_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_00_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_00_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_01_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_01_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_02_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_02_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_03_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_03_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_04_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_04_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_05_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_05_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_06_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_06_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_07_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_07_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_08_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_08_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_09_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_09_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_10_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_11_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_12_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_13_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_14_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_15_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_16_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_17_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_18_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_19_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_19_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_20_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_20_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_21_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_21_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_22_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_22_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_23_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_23_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_24_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_24_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_25_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_25_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_26_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_26_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_27_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_27_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_28_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_28_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_29_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_29_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_30_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_30_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_start_event_31_attr == SERDES_IP_RX_FLEX_L2_CFG_MIN_TIMER_START_EVENT_31_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_00_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_02_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_03_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_10_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_12_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_13_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_15_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_18_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l2_cfg_min_timer_value_31_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_flavor_table_attr == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_flavor_table_en_attr == SERDES_IP_RX_FLEX_L3_CFG_FLX_FLAVOR_TABLE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_force_frame_lock_attr == SERDES_IP_RX_FLEX_L3_CFG_FLX_FORCE_FRAME_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_freeze_in_state_attr == SERDES_IP_RX_FLEX_L3_CFG_FLX_FREEZE_IN_STATE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_00_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_01_attr == 32'd65537
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_02_attr == 32'd2147516416
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_03_attr == 32'd2181169152
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_04_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_05_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_06_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_07_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_08_attr == 32'd16384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_09_attr == 32'd131072
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_10_attr == 32'd2416050176
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_11_attr == 32'd33554432
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_12_attr == 32'd1075838976
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_13_attr == 32'd301989888
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_14_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_15_attr == 32'd2181169152
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_16_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_17_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_18_attr == 32'd302006272
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_19_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_20_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_21_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_22_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_23_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_24_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_25_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_26_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_27_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_28_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_29_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_30_attr == 32'd33587200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_mask_31_attr == 32'd1107329024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_02_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_03_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_10_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_12_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_13_attr == 5'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_15_attr == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_18_attr == 5'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_ir_state_31_attr == 5'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_02_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_03_attr == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_10_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_11_attr == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_12_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_13_attr == 5'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_15_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_18_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_30_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_next_lpcnt_state_31_attr == 5'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_one_state_inc_pulse_attr == SERDES_IP_RX_FLEX_L3_CFG_FLX_ONE_STATE_INC_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_00_attr == 32'd1056783
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_01_attr == 32'd9510943
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_02_attr == 32'd9502735
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_03_attr == 32'd9437199
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_04_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_05_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_06_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_07_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_08_attr == 32'd14680079
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_09_attr == 32'd26017807
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_10_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_11_attr == 32'd9502735
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_12_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_13_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_14_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_15_attr == 32'd25493519
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_16_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_17_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_18_attr == 32'd14942223
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_19_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_20_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_21_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_22_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_23_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_24_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_25_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_26_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_27_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_28_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_29_attr == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_30_attr == 32'd1376271
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl1_31_attr == 32'd8716303
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_00_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_01_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_02_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_03_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_04_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_05_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_06_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_07_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_08_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_09_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_10_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_11_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_12_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_13_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_14_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_15_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_16_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_17_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_18_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_19_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_20_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_21_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_22_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_23_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_24_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_25_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_26_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_27_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_28_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_29_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_30_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_out_ctrl_31_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_state_force_value_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_state_force_value_en_attr == SERDES_IP_RX_FLEX_L3_CFG_FLX_STATE_FORCE_VALUE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_flx_stop_tmr_in_handshake_attr == SERDES_IP_RX_FLEX_L3_CFG_FLX_STOP_TMR_IN_HANDSHAKE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_00_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_00_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_01_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_01_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_02_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_02_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_03_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_03_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_04_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_04_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_05_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_05_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_06_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_06_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_07_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_07_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_08_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_08_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_09_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_09_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_10_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_10_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_11_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_12_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_13_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_14_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_15_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_15_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_16_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_17_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_18_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_19_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_19_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_20_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_20_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_21_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_21_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_22_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_22_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_23_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_23_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_24_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_24_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_25_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_25_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_26_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_26_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_27_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_27_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_28_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_28_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_29_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_29_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_30_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_30_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_en_31_attr == SERDES_IP_RX_FLEX_L3_CFG_MAX_TIMER_EN_31_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_00_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_02_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_03_attr == 5'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_10_attr == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_12_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_13_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_15_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_18_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_max_timer_value_31_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_00_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_00_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_01_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_01_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_02_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_02_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_03_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_03_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_04_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_04_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_05_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_05_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_06_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_06_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_07_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_07_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_08_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_08_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_09_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_09_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_10_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_11_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_12_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_13_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_14_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_15_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_16_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_17_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_18_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_19_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_19_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_20_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_20_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_21_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_21_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_22_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_22_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_23_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_23_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_24_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_24_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_25_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_25_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_26_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_26_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_27_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_27_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_28_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_28_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_29_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_29_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_30_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_30_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_start_event_31_attr == SERDES_IP_RX_FLEX_L3_CFG_MIN_TIMER_START_EVENT_31_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_00_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_01_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_02_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_03_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_04_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_05_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_06_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_07_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_08_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_09_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_10_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_11_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_12_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_13_attr == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_14_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_15_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_16_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_17_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_18_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_19_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_20_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_21_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_22_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_23_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_24_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_25_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_26_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_27_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_28_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_29_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_30_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_rx_flex_l3_cfg_min_timer_value_31_attr == 5'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_etrregsynthlcfastclk_ready2_attr == SERDES_IP_SYNTH_FAST_L0_CFG_ETRREGSYNTHLCFASTCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_etrregsynthlcfastclk_ready_attr == SERDES_IP_SYNTH_FAST_L0_CFG_ETRREGSYNTHLCFASTCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_FAST_L0_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_FAST_L0_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_FAST_L0_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_FAST_L0_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_FAST_L0_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_fastregpwrup_en_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFAST_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFAST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_pg_disable_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFAST_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_refdiv_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_refdiv_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_refdiv_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_refdiv_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_static_divrate_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFAST_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfast_used_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFAST_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastbias_icc400uadj_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldac_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldacbg_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcaldacfsm_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastclk_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastclkstat_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastclkstat_ready_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastdccrst_disable_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastearlylock_dig_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastearlylock_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastfsm_cken_ovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastfsm_cken_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_locovr_muxd0_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_locovr_muxd1_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_locovr_muxd2_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_locovr_muxd3_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_locovr_muxd4_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpllstatus_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastppm_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrecal_on_pd_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_en_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfastspare1_attr == 32'd45078
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfaststartup_locovren_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfaststartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_FAST_L0_CFG_SYNTHLCFASTSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfasttimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l0_cfg_synthlcfasttimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_etrregsynthlcfastclk_ready2_attr == SERDES_IP_SYNTH_FAST_L1_CFG_ETRREGSYNTHLCFASTCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_etrregsynthlcfastclk_ready_attr == SERDES_IP_SYNTH_FAST_L1_CFG_ETRREGSYNTHLCFASTCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_FAST_L1_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_FAST_L1_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_FAST_L1_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_FAST_L1_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_FAST_L1_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_fastregpwrup_en_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFAST_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFAST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_pg_disable_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFAST_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_refdiv_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_refdiv_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_refdiv_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_refdiv_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_static_divrate_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFAST_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfast_used_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFAST_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastbias_icc400uadj_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldac_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldacbg_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcaldacfsm_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastclk_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastclkstat_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastclkstat_ready_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastdccrst_disable_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastearlylock_dig_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastearlylock_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastfsm_cken_ovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastfsm_cken_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_locovr_muxd0_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_locovr_muxd1_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_locovr_muxd2_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_locovr_muxd3_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_locovr_muxd4_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpllstatus_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastppm_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrecal_on_pd_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_en_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfastspare1_attr == 32'd45078
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfaststartup_locovren_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfaststartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_FAST_L1_CFG_SYNTHLCFASTSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfasttimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l1_cfg_synthlcfasttimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_etrregsynthlcfastclk_ready2_attr == SERDES_IP_SYNTH_FAST_L2_CFG_ETRREGSYNTHLCFASTCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_etrregsynthlcfastclk_ready_attr == SERDES_IP_SYNTH_FAST_L2_CFG_ETRREGSYNTHLCFASTCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_FAST_L2_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_FAST_L2_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_FAST_L2_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_FAST_L2_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_FAST_L2_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_fastregpwrup_en_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFAST_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFAST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_pg_disable_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFAST_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_refdiv_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_refdiv_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_refdiv_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_refdiv_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_static_divrate_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFAST_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfast_used_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFAST_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastbias_icc400uadj_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldac_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldacbg_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcaldacfsm_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastclk_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastclkstat_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastclkstat_ready_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastdccrst_disable_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastearlylock_dig_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastearlylock_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastfsm_cken_ovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastfsm_cken_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_locovr_muxd0_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_locovr_muxd1_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_locovr_muxd2_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_locovr_muxd3_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_locovr_muxd4_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpllstatus_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastppm_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrecal_on_pd_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_en_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfastspare1_attr == 32'd45078
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfaststartup_locovren_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfaststartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_FAST_L2_CFG_SYNTHLCFASTSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfasttimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l2_cfg_synthlcfasttimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_etrregsynthlcfastclk_ready2_attr == SERDES_IP_SYNTH_FAST_L3_CFG_ETRREGSYNTHLCFASTCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_etrregsynthlcfastclk_ready_attr == SERDES_IP_SYNTH_FAST_L3_CFG_ETRREGSYNTHLCFASTCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_FAST_L3_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_FAST_L3_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_FAST_L3_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_FAST_L3_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_lb_synthlcfastpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_FAST_L3_CFG_LB_SYNTHLCFASTPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_fastregpwrup_en_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFAST_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFAST_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_pg_disable_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFAST_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_refdiv_muxd1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_refdiv_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_refdiv_muxd3_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_refdiv_muxd4_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_static_divrate_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFAST_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfast_used_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFAST_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastbias_icc400uadj_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldac_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldacbg_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcaldacfsm_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastclk_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastclkstat_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastclkstat_ready_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastdccrst_disable_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastearlylock_dig_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastearlylock_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastfsm_cken_ovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastfsm_cken_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_locovr_muxd0_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_locovr_muxd1_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_locovr_muxd2_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_locovr_muxd3_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_locovr_muxd4_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpllstatus_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastppm_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrecal_on_pd_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_en_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_entry7_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfastspare1_attr == 32'd45078
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfaststartup_locovren_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfaststartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_FAST_L3_CFG_SYNTHLCFASTSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfasttimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_fast_l3_cfg_synthlcfasttimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_etrregsynthlcmedclk_ready2_attr == SERDES_IP_SYNTH_MED_L0_CFG_ETRREGSYNTHLCMEDCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_etrregsynthlcmedclk_ready_attr == SERDES_IP_SYNTH_MED_L0_CFG_ETRREGSYNTHLCMEDCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_MED_L0_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_MED_L0_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_MED_L0_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_MED_L0_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_MED_L0_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_fastregpwrup_en_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_pg_disable_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_refdiv_muxd1_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_refdiv_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_refdiv_muxd3_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_refdiv_muxd4_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_static_divrate_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_txbitclkselect_muxd0_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_txbitclkselect_muxd1_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_txbitclkselect_muxd2_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_txbitclkselect_muxd3_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_txbitclkselect_muxd4_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmed_used_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMED_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedbias_icc400uadj_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldac_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldacbg_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcaldacfsm_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedclk_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedclkstat_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedclkstat_ready_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmeddccrst_disable_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedearlylock_dig_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedearlylock_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedfsm_cken_ovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedfsm_cken_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_locovr_muxd0_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_locovr_muxd1_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_locovr_muxd2_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_locovr_muxd3_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_locovr_muxd4_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpllstatus_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedppm_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrecal_on_pd_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_en_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_entry7_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedstartup_locovren_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedstartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_MED_L0_CFG_SYNTHLCMEDSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedtimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l0_cfg_synthlcmedtimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_etrregsynthlcmedclk_ready2_attr == SERDES_IP_SYNTH_MED_L1_CFG_ETRREGSYNTHLCMEDCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_etrregsynthlcmedclk_ready_attr == SERDES_IP_SYNTH_MED_L1_CFG_ETRREGSYNTHLCMEDCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_MED_L1_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_MED_L1_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_MED_L1_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_MED_L1_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_MED_L1_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_fastregpwrup_en_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_pg_disable_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_refdiv_muxd1_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_refdiv_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_refdiv_muxd3_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_refdiv_muxd4_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_static_divrate_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_txbitclkselect_muxd0_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_txbitclkselect_muxd1_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_txbitclkselect_muxd2_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_txbitclkselect_muxd3_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_txbitclkselect_muxd4_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmed_used_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMED_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedbias_icc400uadj_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldac_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldacbg_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcaldacfsm_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedclk_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedclkstat_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedclkstat_ready_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmeddccrst_disable_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedearlylock_dig_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedearlylock_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedfsm_cken_ovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedfsm_cken_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_locovr_muxd0_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_locovr_muxd1_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_locovr_muxd2_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_locovr_muxd3_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_locovr_muxd4_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpllstatus_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedppm_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrecal_on_pd_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_en_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_entry7_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedstartup_locovren_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedstartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_MED_L1_CFG_SYNTHLCMEDSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedtimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l1_cfg_synthlcmedtimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_etrregsynthlcmedclk_ready2_attr == SERDES_IP_SYNTH_MED_L2_CFG_ETRREGSYNTHLCMEDCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_etrregsynthlcmedclk_ready_attr == SERDES_IP_SYNTH_MED_L2_CFG_ETRREGSYNTHLCMEDCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_MED_L2_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_MED_L2_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_MED_L2_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_MED_L2_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_MED_L2_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_fastregpwrup_en_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_pg_disable_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_refdiv_muxd1_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_refdiv_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_refdiv_muxd3_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_refdiv_muxd4_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_static_divrate_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_txbitclkselect_muxd0_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_txbitclkselect_muxd1_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_txbitclkselect_muxd2_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_txbitclkselect_muxd3_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_txbitclkselect_muxd4_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmed_used_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMED_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedbias_icc400uadj_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldac_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldacbg_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcaldacfsm_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedclk_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedclkstat_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedclkstat_ready_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmeddccrst_disable_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedearlylock_dig_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedearlylock_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedfsm_cken_ovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedfsm_cken_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_locovr_muxd0_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_locovr_muxd1_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_locovr_muxd2_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_locovr_muxd3_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_locovr_muxd4_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpllstatus_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedppm_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrecal_on_pd_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_en_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_entry7_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedstartup_locovren_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedstartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_MED_L2_CFG_SYNTHLCMEDSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedtimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l2_cfg_synthlcmedtimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_etrregsynthlcmedclk_ready2_attr == SERDES_IP_SYNTH_MED_L3_CFG_ETRREGSYNTHLCMEDCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_etrregsynthlcmedclk_ready_attr == SERDES_IP_SYNTH_MED_L3_CFG_ETRREGSYNTHLCMEDCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_MED_L3_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_MED_L3_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_MED_L3_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_MED_L3_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_lb_synthlcmedpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_MED_L3_CFG_LB_SYNTHLCMEDPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_fastregpwrup_en_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_pg_disable_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_refdiv_muxd0_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_refdiv_muxd1_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_refdiv_muxd2_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_refdiv_muxd3_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_refdiv_muxd4_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_static_divrate_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_txbitclkselect_muxd0_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_txbitclkselect_muxd1_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_txbitclkselect_muxd2_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_txbitclkselect_muxd3_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_txbitclkselect_muxd4_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_TXBITCLKSELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmed_used_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMED_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedbias_icc400uadj_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldac_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldacbg_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcaldacfsm_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedclk_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedclkstat_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedclkstat_ready_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmeddccrst_disable_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedearlylock_dig_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedearlylock_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedfsm_cken_ovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedfsm_cken_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_locovr_muxd0_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_locovr_muxd1_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_locovr_muxd2_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_locovr_muxd3_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_locovr_muxd4_attr == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpllstatus_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedppm_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_clk_delay_attr == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrecal_on_pd_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_en_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_entry7_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedstartup_locovren_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedstartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_MED_L3_CFG_SYNTHLCMEDSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedtimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_med_l3_cfg_synthlcmedtimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_etrregsynthlcslowclk_ready2_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_ETRREGSYNTHLCSLOWCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_etrregsynthlcslowclk_ready_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_ETRREGSYNTHLCSLOWCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_fastregpwrup_en_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_pg_disable_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_refdiv_muxd0_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_refdiv_muxd1_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_refdiv_muxd2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_refdiv_muxd3_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_refdiv_muxd4_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_static_divrate_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_txbitclkselect_muxd0_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_txbitclkselect_muxd1_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_txbitclkselect_muxd2_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_txbitclkselect_muxd3_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_txbitclkselect_muxd4_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslow_used_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOW_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowbias_icc400uadj_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldac_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldacbg_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcaldacfsm_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowclk_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowclkstat_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowclkstat_ready_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowdccrst_disable_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowearlylock_dig_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowearlylock_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowfsm_cken_ovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowfsm_cken_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_locovr_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_locovr_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_locovr_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_locovr_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_locovr_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpllstatus_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowppm_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_clk_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrecal_on_pd_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_en_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_entry7_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowstartup_locovren_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowstartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_SLOW_L0_CFG_SYNTHLCSLOWSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowtimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l0_cfg_synthlcslowtimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_etrregsynthlcslowclk_ready2_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_ETRREGSYNTHLCSLOWCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_etrregsynthlcslowclk_ready_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_ETRREGSYNTHLCSLOWCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_fastregpwrup_en_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_pg_disable_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_refdiv_muxd0_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_refdiv_muxd1_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_refdiv_muxd2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_refdiv_muxd3_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_refdiv_muxd4_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_static_divrate_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_txbitclkselect_muxd0_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_txbitclkselect_muxd1_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_txbitclkselect_muxd2_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_txbitclkselect_muxd3_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_txbitclkselect_muxd4_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslow_used_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOW_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowbias_icc400uadj_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldac_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldacbg_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcaldacfsm_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowclk_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowclkstat_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowclkstat_ready_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowdccrst_disable_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowearlylock_dig_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowearlylock_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowfsm_cken_ovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowfsm_cken_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_locovr_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_locovr_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_locovr_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_locovr_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_locovr_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpllstatus_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowppm_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_clk_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrecal_on_pd_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_en_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_entry7_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowstartup_locovren_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowstartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_SLOW_L1_CFG_SYNTHLCSLOWSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowtimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l1_cfg_synthlcslowtimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_etrregsynthlcslowclk_ready2_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_ETRREGSYNTHLCSLOWCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_etrregsynthlcslowclk_ready_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_ETRREGSYNTHLCSLOWCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_fastregpwrup_en_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_pg_disable_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_refdiv_muxd0_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_refdiv_muxd1_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_refdiv_muxd2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_refdiv_muxd3_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_refdiv_muxd4_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_static_divrate_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_txbitclkselect_muxd0_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_txbitclkselect_muxd1_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_txbitclkselect_muxd2_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_txbitclkselect_muxd3_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_txbitclkselect_muxd4_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslow_used_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOW_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowbias_icc400uadj_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldac_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldacbg_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcaldacfsm_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowclk_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowclkstat_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowclkstat_ready_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowdccrst_disable_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowearlylock_dig_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowearlylock_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowfsm_cken_ovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowfsm_cken_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_locovr_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_locovr_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_locovr_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_locovr_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_locovr_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpllstatus_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowppm_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_clk_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrecal_on_pd_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_en_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_entry7_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowstartup_locovren_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowstartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_SLOW_L2_CFG_SYNTHLCSLOWSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowtimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l2_cfg_synthlcslowtimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_etrregsynthlcslowclk_ready2_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_ETRREGSYNTHLCSLOWCLK_READY2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_etrregsynthlcslowclk_ready_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_ETRREGSYNTHLCSLOWCLK_READY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd0_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd1_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd2_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd3_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_lb_synthlcslowpostdivclk2cdrrefclken_muxd4_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_LB_SYNTHLCSLOWPOSTDIVCLK2CDRREFCLKEN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_fastregpwrup_en_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_FASTREGPWRUP_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_on_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_pg_disable_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_PG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_ready_state_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_refdiv_muxd0_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_refdiv_muxd1_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_refdiv_muxd2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_refdiv_muxd3_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_refdiv_muxd4_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_refinctl_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_static_divrate_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_STATIC_DIVRATE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_txbitclkselect_muxd0_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_txbitclkselect_muxd1_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_txbitclkselect_muxd2_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_txbitclkselect_muxd3_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_txbitclkselect_muxd4_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_TXBITCLKSELECT_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslow_used_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOW_USED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowbias_icc400uadj_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWBIAS_ICC400UADJ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcd_gray_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_en_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_BG_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_intvl_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_bg_one_step_cal_en_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_BG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_fg_inc_cal_en_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FG_INC_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_fg_one_step_cal_en_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FG_ONE_STEP_CAL_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_finish_side_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_initval_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_invert_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_lpfaxcoarse_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_lpfaxfine_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_lpflockdet_count_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_restore_delay_attr == 16'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_round_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_runcount_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdfsm_signmagen_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDFSM_SIGNMAGEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_currentdacdcdmeas_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_CURRENTDACDCDMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldac_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDAC_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldacbg_abort_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDACBG_ABORT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldacbg_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDACBG_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldacbg_ready_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDACBG_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldaccurrentdacdcdfsm_recal_attr == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldaccurrentdacdcdfsmout_en_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDACCURRENTDACDCDFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldaccurrentdacdcdfsmout_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDACCURRENTDACDCDFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldacencoderin_currentdacdcd_bin_locovr_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldacencoderin_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDACENCODERIN_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_init_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDACFSM_CURRENTDACDCDFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldacfsm_currentdacdcdfsm_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDACFSM_CURRENTDACDCDFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcaldacfsm_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALDACFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_pstate_currentdacdcdfsm_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_pstate_plllc_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_pstate_regopampoffset_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_pstate_rxppm_lockstatus_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_pstate_startup_plllc_en_h_sus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_pstate_synthlcppm_lockstatus_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_quad_currentdacdcdfsm_attr == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_quad_plllc_lockstatus_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_quad_regopampoffset_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_quad_rxppm_lockstatus_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_quad_startup_plllc_en_h_sus_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalptr_quad_synthlcppm_lockstatus_attr == 4'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffset_locovr_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffset_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSET_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_clear_locovr_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_codeoffset_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_finish_side_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_FINISH_SIDE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_init_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_INIT_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_initval_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_invert_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_lpfaxcoarse_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_lpfaxfine_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_lpflockdet_count_attr == 16'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_lpflockdet_tolerance_attr == 16'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_maxiter_attr == 12'd4095
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_precalfsmstart_delay_attr == 16'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_recal_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_restore_delay_attr == 16'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_round_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_ROUND_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_runcount_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_RUNCOUNT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsm_signmagen_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSM_SIGNMAGEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsmout_en_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSMOUT_EN_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetfsmout_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETFSMOUT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetmeas_clrcount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetmeas_dlycount_attr == 5'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetmeas_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETMEAS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetmeas_pow2count_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetmeas_req_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCALREGOPAMPOFFSETMEAS_REQ_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowcalregopampoffsetmeas_validdlycount_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowclk_keepalive_en_b_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCLK_KEEPALIVE_EN_B_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowclk_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCLK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowclkstat_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCLKSTAT_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowclkstat_ready_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWCLKSTAT_READY_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowdccrst_disable_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWDCCRST_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowearlylock_dig_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWEARLYLOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowearlylock_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWEARLYLOCK_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowfsm_calabort_pulse_width_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowfsm_cken_ovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWFSM_CKEN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowfsm_cken_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWFSM_CKEN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0en_muxd0_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0en_muxd1_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0en_muxd2_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0en_muxd3_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv2clk0en_muxd4_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV2CLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_locovr_muxd0_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_locovr_muxd1_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_locovr_muxd2_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_locovr_muxd3_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_locovr_muxd4_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd0_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd1_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd2_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd3_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdiv_p5_locovr_muxd4_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIV_P5_LOCOVR_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdivclk0en_muxd0_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdivclk0en_muxd1_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdivclk0en_muxd2_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdivclk0en_muxd3_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpcs_postdivclk0en_muxd4_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPCS_POSTDIVCLK0EN_MUXD4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_disable_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_hardreset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPLL_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_refclksel_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_sel_cb0_lane1_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPLL_SEL_CB0_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_shutdown_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_spare_dout_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_strbreg_reset_t0_attr == 12'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpll_strbreg_reset_t1_attr == 12'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpllcfgloader_load_req_ovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPLLCFGLOADER_LOAD_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpllcfgloader_load_req_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPLLCFGLOADER_LOAD_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpllcfgloader_mode_ovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpllcfgloader_pll_off_req_ovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPLLCFGLOADER_PLL_OFF_REQ_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpllcfgloader_pll_off_req_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPLLCFGLOADER_PLL_OFF_REQ_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpllregpwrdn_refclksel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpllregpwrup_refclksel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpllstatus_lock_dig_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPLLSTATUS_LOCK_DIG_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpllstatus_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPLLSTATUS_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpmu_h8_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpmu_h8_rst_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpmu_iso_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpmu_restore_iso_on_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpmu_restore_off_delay_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpmu_rst_off_delay_attr == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowpostdiv_wait_for_lock_disable_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPOSTDIV_WAIT_FOR_LOCK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowppm_lockstatus_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPPM_LOCKSTATUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowppm_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWPPM_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_cal_clear_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_clk_chk_disable_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRATEWIDTH_CLK_CHK_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_clk_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_etr_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_etr_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRATEWIDTH_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_mode_locovr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_pd_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_pd_on_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_ratewidth_delay_attr == 12'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_rst_a_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_rst_b0_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_rst_b1_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowratewidth_rst_b2_off_delay_attr == 12'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrecal_on_pd_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRECAL_ON_PD_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrefck_refinctl_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrefck_refinctl_lr_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrefck_refinctl_slv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowreg_lev_attr == 4'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_en_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRPU_EN_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_entry1_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_entry2_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_entry3_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q2_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q3_attr == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s0q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q1_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q2_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q3_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q4_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q5_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q6_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s1q7_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evdn_delay_lut_sel_s2q0_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_entry1_attr == 13'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_entry2_attr == 13'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_entry3_attr == 13'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_entry4_attr == 13'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_entry5_attr == 13'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_entry6_attr == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_entry7_attr == 13'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q3_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s0q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q1_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q2_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q3_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q4_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q5_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q6_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s1q7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpu_evup_delay_lut_sel_s2q0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_up_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_clear_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_currentdacdcd_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr0_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr1_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_cal_regopamp_init_up_ptr1_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_up_ptr0_q_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuctl_keepalive_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdiv2clksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_pcspostdivclksel_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_regpwrupacc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpuetr_startup_plllc_sus_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_dn_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_up_ptr0_q_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_biasicc_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_dn_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_up_ptr0_q_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_pll_en_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpupd_reg_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_dn_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_up_ptr0_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_dccrst_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv2_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_postdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_dn_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_dn_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_up_ptr0_q_attr == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_up_ptr0_s_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_refdiv_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_dn_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr0_q_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_dn_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_up_attr == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_up_ptr0_q_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_up_ptr0_s_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_up_ptr1_q_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrpurst_synthregreset_b_up_ptr1_s_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdiv2clksel_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIV2CLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdivclksel_ovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_aetrsynthlc_pcspostdivclksel_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_PCSPOSTDIVCLKSEL_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_aetrsynthlc_regpwrupacc_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_aetrsynthlc_regpwrupacc_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_AETRSYNTHLC_REGPWRUPACC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_apdsynthlc_biasicc_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_BIASICC_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_apdsynthlc_biasicc_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_BIASICC_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_apdsynthlc_reg_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_REG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_apdsynthlc_reg_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_APDSYNTHLC_REG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_dcc_b_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_DCC_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_dcc_b_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_DCC_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv2_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv2_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV2_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_postdiv_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_POSTDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_refdiv_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_REFDIV_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_refdiv_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_REFDIV_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_strbreg_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_strbreg_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_STRBREG_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_sus_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_startup_plllc_sus_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_STARTUP_PLLLC_SUS_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_synthregreset_b_ovr_b_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVR_B_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_arstsynthlc_synthregreset_b_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_ARSTSYNTHLC_SYNTHREGRESET_B_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_synthlcstartup_plllc_en_ovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowrstpdovr_synthlcstartup_plllc_en_ovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWRSTPDOVR_SYNTHLCSTARTUP_PLLLC_EN_OVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowspare0_attr == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowspare1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowstartup_locovren_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWSTARTUP_LOCOVREN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowstartup_plllc_en_h_sus_locovr_attr == SERDES_IP_SYNTH_SLOW_L3_CFG_SYNTHLCSLOWSTARTUP_PLLLC_EN_H_SUS_LOCOVR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowtimer_dccrst2lockmask_attr == 8'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_ip_synth_slow_l3_cfg_synthlcslowtimer_rawlock2dccrst_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_an_idle_stiky_clear_attr == SERDES_SHIM_AN_L0_CFG_AN_IDLE_STIKY_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_an_reserv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_debug_fw_reg1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_debug_fw_reg2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_debug_fw_reg3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_debug_fw_reg4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_dig_cdr_disable_attr == SERDES_SHIM_AN_L0_CFG_DIG_CDR_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_direct_control_bus0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_direct_control_bus1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_direct_control_bus2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_direct_control_bus3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_direct_control_bus4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_direct_control_bus5_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_direct_control_bus6_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_direct_control_bus_en_attr == SERDES_SHIM_AN_L0_CFG_DIRECT_CONTROL_BUS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_edge_too_long_disable_attr == SERDES_SHIM_AN_L0_CFG_EDGE_TOO_LONG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_edge_too_short_disable_attr == SERDES_SHIM_AN_L0_CFG_EDGE_TOO_SHORT_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_page_max_timer_disable_attr == SERDES_SHIM_AN_L0_CFG_PAGE_MAX_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_page_min_timer_disable_attr == SERDES_SHIM_AN_L0_CFG_PAGE_MIN_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_pcs_lock_attr == SERDES_SHIM_AN_L0_CFG_PCS_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_pcs_tx_bypass_sample_attr == SERDES_SHIM_AN_L0_CFG_PCS_TX_BYPASS_SAMPLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_rx_enable_m_attr == SERDES_SHIM_AN_L0_CFG_RX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_rx_lcw_re_attr == SERDES_SHIM_AN_L0_CFG_RX_LCW_RE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_rx_pma_en_attr == SERDES_SHIM_AN_L0_CFG_RX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_rx_unencoder_ctrl_en_attr == SERDES_SHIM_AN_L0_CFG_RX_UNENCODER_CTRL_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_rx_unencoder_gray_en_attr == SERDES_SHIM_AN_L0_CFG_RX_UNENCODER_GRAY_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_rx_unencoder_pam_bitorder_swz_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_rx_unencoder_pam_en_attr == SERDES_SHIM_AN_L0_CFG_RX_UNENCODER_PAM_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_rx_unencoder_polarity_swz_attr == SERDES_SHIM_AN_L0_CFG_RX_UNENCODER_POLARITY_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_rx_unencoder_precode_en_attr == SERDES_SHIM_AN_L0_CFG_RX_UNENCODER_PRECODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_rx_unencoder_width_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_serdes_irq_bus_sel_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_serdes_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_serdes_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_serdes_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_transmit_mode_scan_mode_dbg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_tx_complete_ack_attr == SERDES_SHIM_AN_L0_CFG_TX_COMPLETE_ACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_tx_enable_m_attr == SERDES_SHIM_AN_L0_CFG_TX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_tx_lcw_high_attr == 27'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_tx_lcw_low_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_tx_lcw_reserv_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_tx_lcw_we_attr == SERDES_SHIM_AN_L0_CFG_TX_LCW_WE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l0_cfg_tx_pma_en_attr == SERDES_SHIM_AN_L0_CFG_TX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_an_idle_stiky_clear_attr == SERDES_SHIM_AN_L1_CFG_AN_IDLE_STIKY_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_an_reserv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_debug_fw_reg1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_debug_fw_reg2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_debug_fw_reg3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_debug_fw_reg4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_dig_cdr_disable_attr == SERDES_SHIM_AN_L1_CFG_DIG_CDR_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_direct_control_bus0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_direct_control_bus1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_direct_control_bus2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_direct_control_bus3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_direct_control_bus4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_direct_control_bus5_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_direct_control_bus6_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_direct_control_bus_en_attr == SERDES_SHIM_AN_L1_CFG_DIRECT_CONTROL_BUS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_edge_too_long_disable_attr == SERDES_SHIM_AN_L1_CFG_EDGE_TOO_LONG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_edge_too_short_disable_attr == SERDES_SHIM_AN_L1_CFG_EDGE_TOO_SHORT_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_page_max_timer_disable_attr == SERDES_SHIM_AN_L1_CFG_PAGE_MAX_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_page_min_timer_disable_attr == SERDES_SHIM_AN_L1_CFG_PAGE_MIN_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_pcs_lock_attr == SERDES_SHIM_AN_L1_CFG_PCS_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_pcs_tx_bypass_sample_attr == SERDES_SHIM_AN_L1_CFG_PCS_TX_BYPASS_SAMPLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_rx_enable_m_attr == SERDES_SHIM_AN_L1_CFG_RX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_rx_lcw_re_attr == SERDES_SHIM_AN_L1_CFG_RX_LCW_RE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_rx_pma_en_attr == SERDES_SHIM_AN_L1_CFG_RX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_rx_unencoder_ctrl_en_attr == SERDES_SHIM_AN_L1_CFG_RX_UNENCODER_CTRL_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_rx_unencoder_gray_en_attr == SERDES_SHIM_AN_L1_CFG_RX_UNENCODER_GRAY_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_rx_unencoder_pam_bitorder_swz_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_rx_unencoder_pam_en_attr == SERDES_SHIM_AN_L1_CFG_RX_UNENCODER_PAM_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_rx_unencoder_polarity_swz_attr == SERDES_SHIM_AN_L1_CFG_RX_UNENCODER_POLARITY_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_rx_unencoder_precode_en_attr == SERDES_SHIM_AN_L1_CFG_RX_UNENCODER_PRECODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_rx_unencoder_width_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_serdes_irq_bus_sel_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_serdes_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_serdes_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_serdes_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_transmit_mode_scan_mode_dbg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_tx_complete_ack_attr == SERDES_SHIM_AN_L1_CFG_TX_COMPLETE_ACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_tx_enable_m_attr == SERDES_SHIM_AN_L1_CFG_TX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_tx_lcw_high_attr == 27'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_tx_lcw_low_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_tx_lcw_reserv_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_tx_lcw_we_attr == SERDES_SHIM_AN_L1_CFG_TX_LCW_WE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l1_cfg_tx_pma_en_attr == SERDES_SHIM_AN_L1_CFG_TX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_an_idle_stiky_clear_attr == SERDES_SHIM_AN_L2_CFG_AN_IDLE_STIKY_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_an_reserv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_debug_fw_reg1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_debug_fw_reg2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_debug_fw_reg3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_debug_fw_reg4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_dig_cdr_disable_attr == SERDES_SHIM_AN_L2_CFG_DIG_CDR_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_direct_control_bus0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_direct_control_bus1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_direct_control_bus2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_direct_control_bus3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_direct_control_bus4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_direct_control_bus5_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_direct_control_bus6_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_direct_control_bus_en_attr == SERDES_SHIM_AN_L2_CFG_DIRECT_CONTROL_BUS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_edge_too_long_disable_attr == SERDES_SHIM_AN_L2_CFG_EDGE_TOO_LONG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_edge_too_short_disable_attr == SERDES_SHIM_AN_L2_CFG_EDGE_TOO_SHORT_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_page_max_timer_disable_attr == SERDES_SHIM_AN_L2_CFG_PAGE_MAX_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_page_min_timer_disable_attr == SERDES_SHIM_AN_L2_CFG_PAGE_MIN_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_pcs_lock_attr == SERDES_SHIM_AN_L2_CFG_PCS_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_pcs_tx_bypass_sample_attr == SERDES_SHIM_AN_L2_CFG_PCS_TX_BYPASS_SAMPLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_rx_enable_m_attr == SERDES_SHIM_AN_L2_CFG_RX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_rx_lcw_re_attr == SERDES_SHIM_AN_L2_CFG_RX_LCW_RE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_rx_pma_en_attr == SERDES_SHIM_AN_L2_CFG_RX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_rx_unencoder_ctrl_en_attr == SERDES_SHIM_AN_L2_CFG_RX_UNENCODER_CTRL_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_rx_unencoder_gray_en_attr == SERDES_SHIM_AN_L2_CFG_RX_UNENCODER_GRAY_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_rx_unencoder_pam_bitorder_swz_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_rx_unencoder_pam_en_attr == SERDES_SHIM_AN_L2_CFG_RX_UNENCODER_PAM_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_rx_unencoder_polarity_swz_attr == SERDES_SHIM_AN_L2_CFG_RX_UNENCODER_POLARITY_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_rx_unencoder_precode_en_attr == SERDES_SHIM_AN_L2_CFG_RX_UNENCODER_PRECODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_rx_unencoder_width_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_serdes_irq_bus_sel_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_serdes_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_serdes_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_serdes_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_transmit_mode_scan_mode_dbg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_tx_complete_ack_attr == SERDES_SHIM_AN_L2_CFG_TX_COMPLETE_ACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_tx_enable_m_attr == SERDES_SHIM_AN_L2_CFG_TX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_tx_lcw_high_attr == 27'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_tx_lcw_low_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_tx_lcw_reserv_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_tx_lcw_we_attr == SERDES_SHIM_AN_L2_CFG_TX_LCW_WE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l2_cfg_tx_pma_en_attr == SERDES_SHIM_AN_L2_CFG_TX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_an_idle_stiky_clear_attr == SERDES_SHIM_AN_L3_CFG_AN_IDLE_STIKY_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_an_reserv_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_debug_fw_reg1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_debug_fw_reg2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_debug_fw_reg3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_debug_fw_reg4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_dig_cdr_disable_attr == SERDES_SHIM_AN_L3_CFG_DIG_CDR_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_direct_control_bus0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_direct_control_bus1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_direct_control_bus2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_direct_control_bus3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_direct_control_bus4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_direct_control_bus5_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_direct_control_bus6_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_direct_control_bus_en_attr == SERDES_SHIM_AN_L3_CFG_DIRECT_CONTROL_BUS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_edge_too_long_disable_attr == SERDES_SHIM_AN_L3_CFG_EDGE_TOO_LONG_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_edge_too_short_disable_attr == SERDES_SHIM_AN_L3_CFG_EDGE_TOO_SHORT_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_page_max_timer_disable_attr == SERDES_SHIM_AN_L3_CFG_PAGE_MAX_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_page_min_timer_disable_attr == SERDES_SHIM_AN_L3_CFG_PAGE_MIN_TIMER_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_pcs_lock_attr == SERDES_SHIM_AN_L3_CFG_PCS_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_pcs_tx_bypass_sample_attr == SERDES_SHIM_AN_L3_CFG_PCS_TX_BYPASS_SAMPLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_rx_enable_m_attr == SERDES_SHIM_AN_L3_CFG_RX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_rx_lcw_re_attr == SERDES_SHIM_AN_L3_CFG_RX_LCW_RE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_rx_pma_en_attr == SERDES_SHIM_AN_L3_CFG_RX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_rx_unencoder_ctrl_en_attr == SERDES_SHIM_AN_L3_CFG_RX_UNENCODER_CTRL_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_rx_unencoder_gray_en_attr == SERDES_SHIM_AN_L3_CFG_RX_UNENCODER_GRAY_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_rx_unencoder_pam_bitorder_swz_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_rx_unencoder_pam_en_attr == SERDES_SHIM_AN_L3_CFG_RX_UNENCODER_PAM_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_rx_unencoder_polarity_swz_attr == SERDES_SHIM_AN_L3_CFG_RX_UNENCODER_POLARITY_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_rx_unencoder_precode_en_attr == SERDES_SHIM_AN_L3_CFG_RX_UNENCODER_PRECODE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_rx_unencoder_width_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_serdes_irq_bus_sel_attr == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_serdes_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_serdes_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_serdes_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_transmit_mode_scan_mode_dbg_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_tx_complete_ack_attr == SERDES_SHIM_AN_L3_CFG_TX_COMPLETE_ACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_tx_enable_m_attr == SERDES_SHIM_AN_L3_CFG_TX_ENABLE_M_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_tx_lcw_high_attr == 27'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_tx_lcw_low_attr == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_tx_lcw_reserv_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_tx_lcw_we_attr == SERDES_SHIM_AN_L3_CFG_TX_LCW_WE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_an_l3_cfg_tx_pma_en_attr == SERDES_SHIM_AN_L3_CFG_TX_PMA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_apb_dsp_clk_sel_attr == SERDES_SHIM_CAR_L0_CFG_APB_DSP_CLK_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_apb_dsp_divn_en_attr == SERDES_SHIM_CAR_L0_CFG_APB_DSP_DIVN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_apb_dsp_divn_value_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_apb_dsp_pclken_attr == SERDES_SHIM_CAR_L0_CFG_APB_DSP_PCLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_apb_dsp_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_APB_DSP_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_dp_rx_80b_swz_attr == SERDES_SHIM_CAR_L0_CFG_DP_RX_80B_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_dp_tx_80b_swz_attr == SERDES_SHIM_CAR_L0_CFG_DP_TX_80B_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_eee_alert_force_en_attr == SERDES_SHIM_CAR_L0_CFG_EEE_ALERT_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_eee_alert_force_val_attr == SERDES_SHIM_CAR_L0_CFG_EEE_ALERT_FORCE_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_flux_srds_tx_divn_clken_attr == SERDES_SHIM_CAR_L0_CFG_FLUX_SRDS_TX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_iflux_tx_or_apb_clk_for_ux_ctrl_clk_sel_attr == SERDES_SHIM_CAR_L0_CFG_IFLUX_TX_OR_APB_CLK_FOR_UX_CTRL_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_oflux_srds_rx_clken_attr == SERDES_SHIM_CAR_L0_CFG_OFLUX_SRDS_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_oflux_srds_rx_divn_clken_attr == SERDES_SHIM_CAR_L0_CFG_OFLUX_SRDS_RX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_oflux_srds_tx_clken_attr == SERDES_SHIM_CAR_L0_CFG_OFLUX_SRDS_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_pcs_ick_ctrl_cmn_clk_sel_attr == SERDES_SHIM_CAR_L0_CFG_PCS_ICK_CTRL_CMN_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_pcs_ick_ctrl_l0_clk_sel_attr == SERDES_SHIM_CAR_L0_CFG_PCS_ICK_CTRL_L0_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_rxovrcdrlock2data_attr == SERDES_SHIM_CAR_L0_CFG_RXOVRCDRLOCK2DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_rxovrcdrlock2data_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_rxovrcdrlock2dataen_attr == SERDES_SHIM_CAR_L0_CFG_RXOVRCDRLOCK2DATAEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_rxovrcdrlock2dataen_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_rxpstate_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_rxpstate_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_srds_an_rx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_AN_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_srds_an_rx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_AN_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_srds_an_tx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_AN_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_srds_an_tx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_AN_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_srds_ctrl_rx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_CTRL_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_srds_ctrl_rx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_CTRL_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_srds_ctrl_tx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_CTRL_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_srds_ctrl_tx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_CTRL_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_srds_dfx_rx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_DFX_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_srds_dfx_rx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_DFX_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_srds_dfx_tx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_DFX_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_srds_dfx_tx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_DFX_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_srds_dsp_rx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_DSP_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_srds_dsp_rx_isi_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_DSP_RX_ISI_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_srds_dsp_rx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_DSP_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_srds_eee_rx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_EEE_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_srds_eee_rx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_EEE_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_srds_eee_tx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_EEE_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_srds_eee_tx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_EEE_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_srds_pcs_tx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_PCS_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_srds_pcs_tx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_PCS_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_srds_trn_rx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_TRN_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_srds_trn_rx_divn_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_TRN_RX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_srds_trn_rx_divn_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_TRN_RX_DIVN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_srds_trn_rx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_TRN_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_srds_trn_tx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_TRN_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_srds_trn_tx_divn_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_TRN_TX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_srds_trn_tx_divn_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_TRN_TX_DIVN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_srds_trn_tx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_TRN_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_srds_ux_ctrl_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_UX_CTRL_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_srds_ux_ctrl_cmn_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_UX_CTRL_CMN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_srds_ux_ctrl_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_UX_CTRL_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_srds_ux_tx_clken_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_UX_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_srds_ux_tx_swrstn_attr == SERDES_SHIM_CAR_L0_CFG_SRDS_UX_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_timer_en_attr == SERDES_SHIM_CAR_L0_CFG_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_timer_value_attr == 8'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_transmit_mode_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_tx_postdiv_clk_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_txelecidle_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_txelecidle_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_txpstate_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l0_cfg_txpstate_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_apb_dsp_clk_sel_attr == SERDES_SHIM_CAR_L1_CFG_APB_DSP_CLK_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_apb_dsp_divn_en_attr == SERDES_SHIM_CAR_L1_CFG_APB_DSP_DIVN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_apb_dsp_divn_value_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_apb_dsp_pclken_attr == SERDES_SHIM_CAR_L1_CFG_APB_DSP_PCLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_apb_dsp_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_APB_DSP_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_dp_rx_80b_swz_attr == SERDES_SHIM_CAR_L1_CFG_DP_RX_80B_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_dp_tx_80b_swz_attr == SERDES_SHIM_CAR_L1_CFG_DP_TX_80B_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_eee_alert_force_en_attr == SERDES_SHIM_CAR_L1_CFG_EEE_ALERT_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_eee_alert_force_val_attr == SERDES_SHIM_CAR_L1_CFG_EEE_ALERT_FORCE_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_flux_srds_tx_divn_clken_attr == SERDES_SHIM_CAR_L1_CFG_FLUX_SRDS_TX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_iflux_tx_or_apb_clk_for_ux_ctrl_clk_sel_attr == SERDES_SHIM_CAR_L1_CFG_IFLUX_TX_OR_APB_CLK_FOR_UX_CTRL_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_oflux_srds_rx_clken_attr == SERDES_SHIM_CAR_L1_CFG_OFLUX_SRDS_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_oflux_srds_rx_divn_clken_attr == SERDES_SHIM_CAR_L1_CFG_OFLUX_SRDS_RX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_oflux_srds_tx_clken_attr == SERDES_SHIM_CAR_L1_CFG_OFLUX_SRDS_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_pcs_ick_ctrl_cmn_clk_sel_attr == SERDES_SHIM_CAR_L1_CFG_PCS_ICK_CTRL_CMN_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_pcs_ick_ctrl_l0_clk_sel_attr == SERDES_SHIM_CAR_L1_CFG_PCS_ICK_CTRL_L0_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_rxovrcdrlock2data_attr == SERDES_SHIM_CAR_L1_CFG_RXOVRCDRLOCK2DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_rxovrcdrlock2data_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_rxovrcdrlock2dataen_attr == SERDES_SHIM_CAR_L1_CFG_RXOVRCDRLOCK2DATAEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_rxovrcdrlock2dataen_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_rxpstate_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_rxpstate_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_srds_an_rx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_AN_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_srds_an_rx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_AN_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_srds_an_tx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_AN_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_srds_an_tx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_AN_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_srds_ctrl_rx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_CTRL_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_srds_ctrl_rx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_CTRL_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_srds_ctrl_tx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_CTRL_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_srds_ctrl_tx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_CTRL_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_srds_dfx_rx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_DFX_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_srds_dfx_rx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_DFX_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_srds_dfx_tx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_DFX_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_srds_dfx_tx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_DFX_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_srds_dsp_rx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_DSP_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_srds_dsp_rx_isi_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_DSP_RX_ISI_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_srds_dsp_rx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_DSP_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_srds_eee_rx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_EEE_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_srds_eee_rx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_EEE_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_srds_eee_tx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_EEE_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_srds_eee_tx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_EEE_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_srds_pcs_tx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_PCS_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_srds_pcs_tx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_PCS_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_srds_trn_rx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_TRN_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_srds_trn_rx_divn_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_TRN_RX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_srds_trn_rx_divn_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_TRN_RX_DIVN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_srds_trn_rx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_TRN_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_srds_trn_tx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_TRN_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_srds_trn_tx_divn_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_TRN_TX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_srds_trn_tx_divn_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_TRN_TX_DIVN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_srds_trn_tx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_TRN_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_srds_ux_ctrl_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_UX_CTRL_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_srds_ux_ctrl_cmn_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_UX_CTRL_CMN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_srds_ux_ctrl_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_UX_CTRL_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_srds_ux_tx_clken_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_UX_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_srds_ux_tx_swrstn_attr == SERDES_SHIM_CAR_L1_CFG_SRDS_UX_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_timer_en_attr == SERDES_SHIM_CAR_L1_CFG_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_timer_value_attr == 8'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_transmit_mode_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_tx_postdiv_clk_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_txelecidle_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_txelecidle_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_txpstate_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l1_cfg_txpstate_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_apb_dsp_clk_sel_attr == SERDES_SHIM_CAR_L2_CFG_APB_DSP_CLK_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_apb_dsp_divn_en_attr == SERDES_SHIM_CAR_L2_CFG_APB_DSP_DIVN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_apb_dsp_divn_value_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_apb_dsp_pclken_attr == SERDES_SHIM_CAR_L2_CFG_APB_DSP_PCLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_apb_dsp_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_APB_DSP_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_dp_rx_80b_swz_attr == SERDES_SHIM_CAR_L2_CFG_DP_RX_80B_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_dp_tx_80b_swz_attr == SERDES_SHIM_CAR_L2_CFG_DP_TX_80B_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_eee_alert_force_en_attr == SERDES_SHIM_CAR_L2_CFG_EEE_ALERT_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_eee_alert_force_val_attr == SERDES_SHIM_CAR_L2_CFG_EEE_ALERT_FORCE_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_flux_srds_tx_divn_clken_attr == SERDES_SHIM_CAR_L2_CFG_FLUX_SRDS_TX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_iflux_tx_or_apb_clk_for_ux_ctrl_clk_sel_attr == SERDES_SHIM_CAR_L2_CFG_IFLUX_TX_OR_APB_CLK_FOR_UX_CTRL_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_oflux_srds_rx_clken_attr == SERDES_SHIM_CAR_L2_CFG_OFLUX_SRDS_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_oflux_srds_rx_divn_clken_attr == SERDES_SHIM_CAR_L2_CFG_OFLUX_SRDS_RX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_oflux_srds_tx_clken_attr == SERDES_SHIM_CAR_L2_CFG_OFLUX_SRDS_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_pcs_ick_ctrl_cmn_clk_sel_attr == SERDES_SHIM_CAR_L2_CFG_PCS_ICK_CTRL_CMN_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_pcs_ick_ctrl_l0_clk_sel_attr == SERDES_SHIM_CAR_L2_CFG_PCS_ICK_CTRL_L0_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_rxovrcdrlock2data_attr == SERDES_SHIM_CAR_L2_CFG_RXOVRCDRLOCK2DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_rxovrcdrlock2data_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_rxovrcdrlock2dataen_attr == SERDES_SHIM_CAR_L2_CFG_RXOVRCDRLOCK2DATAEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_rxovrcdrlock2dataen_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_rxpstate_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_rxpstate_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_srds_an_rx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_AN_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_srds_an_rx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_AN_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_srds_an_tx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_AN_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_srds_an_tx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_AN_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_srds_ctrl_rx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_CTRL_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_srds_ctrl_rx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_CTRL_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_srds_ctrl_tx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_CTRL_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_srds_ctrl_tx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_CTRL_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_srds_dfx_rx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_DFX_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_srds_dfx_rx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_DFX_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_srds_dfx_tx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_DFX_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_srds_dfx_tx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_DFX_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_srds_dsp_rx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_DSP_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_srds_dsp_rx_isi_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_DSP_RX_ISI_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_srds_dsp_rx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_DSP_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_srds_eee_rx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_EEE_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_srds_eee_rx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_EEE_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_srds_eee_tx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_EEE_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_srds_eee_tx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_EEE_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_srds_pcs_tx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_PCS_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_srds_pcs_tx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_PCS_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_srds_trn_rx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_TRN_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_srds_trn_rx_divn_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_TRN_RX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_srds_trn_rx_divn_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_TRN_RX_DIVN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_srds_trn_rx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_TRN_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_srds_trn_tx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_TRN_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_srds_trn_tx_divn_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_TRN_TX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_srds_trn_tx_divn_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_TRN_TX_DIVN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_srds_trn_tx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_TRN_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_srds_ux_ctrl_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_UX_CTRL_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_srds_ux_ctrl_cmn_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_UX_CTRL_CMN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_srds_ux_ctrl_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_UX_CTRL_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_srds_ux_tx_clken_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_UX_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_srds_ux_tx_swrstn_attr == SERDES_SHIM_CAR_L2_CFG_SRDS_UX_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_timer_en_attr == SERDES_SHIM_CAR_L2_CFG_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_timer_value_attr == 8'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_transmit_mode_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_tx_postdiv_clk_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_txelecidle_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_txelecidle_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_txpstate_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l2_cfg_txpstate_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_apb_dsp_clk_sel_attr == SERDES_SHIM_CAR_L3_CFG_APB_DSP_CLK_SEL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_apb_dsp_divn_en_attr == SERDES_SHIM_CAR_L3_CFG_APB_DSP_DIVN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_apb_dsp_divn_value_attr == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_apb_dsp_pclken_attr == SERDES_SHIM_CAR_L3_CFG_APB_DSP_PCLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_apb_dsp_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_APB_DSP_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_dp_rx_80b_swz_attr == SERDES_SHIM_CAR_L3_CFG_DP_RX_80B_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_dp_tx_80b_swz_attr == SERDES_SHIM_CAR_L3_CFG_DP_TX_80B_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_eee_alert_force_en_attr == SERDES_SHIM_CAR_L3_CFG_EEE_ALERT_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_eee_alert_force_val_attr == SERDES_SHIM_CAR_L3_CFG_EEE_ALERT_FORCE_VAL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_flux_srds_tx_divn_clken_attr == SERDES_SHIM_CAR_L3_CFG_FLUX_SRDS_TX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_iflux_tx_or_apb_clk_for_ux_ctrl_clk_sel_attr == SERDES_SHIM_CAR_L3_CFG_IFLUX_TX_OR_APB_CLK_FOR_UX_CTRL_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_oflux_srds_rx_clken_attr == SERDES_SHIM_CAR_L3_CFG_OFLUX_SRDS_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_oflux_srds_rx_divn_clken_attr == SERDES_SHIM_CAR_L3_CFG_OFLUX_SRDS_RX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_oflux_srds_tx_clken_attr == SERDES_SHIM_CAR_L3_CFG_OFLUX_SRDS_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_pcs_ick_ctrl_cmn_clk_sel_attr == SERDES_SHIM_CAR_L3_CFG_PCS_ICK_CTRL_CMN_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_pcs_ick_ctrl_l0_clk_sel_attr == SERDES_SHIM_CAR_L3_CFG_PCS_ICK_CTRL_L0_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_rxovrcdrlock2data_attr == SERDES_SHIM_CAR_L3_CFG_RXOVRCDRLOCK2DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_rxovrcdrlock2data_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_rxovrcdrlock2dataen_attr == SERDES_SHIM_CAR_L3_CFG_RXOVRCDRLOCK2DATAEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_rxovrcdrlock2dataen_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_rxpstate_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_rxpstate_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_srds_an_rx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_AN_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_srds_an_rx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_AN_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_srds_an_tx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_AN_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_srds_an_tx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_AN_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_srds_ctrl_rx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_CTRL_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_srds_ctrl_rx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_CTRL_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_srds_ctrl_tx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_CTRL_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_srds_ctrl_tx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_CTRL_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_srds_dfx_rx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_DFX_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_srds_dfx_rx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_DFX_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_srds_dfx_tx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_DFX_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_srds_dfx_tx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_DFX_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_srds_dsp_rx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_DSP_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_srds_dsp_rx_isi_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_DSP_RX_ISI_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_srds_dsp_rx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_DSP_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_srds_eee_rx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_EEE_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_srds_eee_rx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_EEE_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_srds_eee_tx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_EEE_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_srds_eee_tx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_EEE_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_srds_pcs_tx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_PCS_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_srds_pcs_tx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_PCS_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_srds_trn_rx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_TRN_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_srds_trn_rx_divn_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_TRN_RX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_srds_trn_rx_divn_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_TRN_RX_DIVN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_srds_trn_rx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_TRN_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_srds_trn_tx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_TRN_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_srds_trn_tx_divn_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_TRN_TX_DIVN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_srds_trn_tx_divn_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_TRN_TX_DIVN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_srds_trn_tx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_TRN_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_srds_ux_ctrl_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_UX_CTRL_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_srds_ux_ctrl_cmn_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_UX_CTRL_CMN_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_srds_ux_ctrl_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_UX_CTRL_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_srds_ux_tx_clken_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_UX_TX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_srds_ux_tx_swrstn_attr == SERDES_SHIM_CAR_L3_CFG_SRDS_UX_TX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_timer_en_attr == SERDES_SHIM_CAR_L3_CFG_TIMER_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_timer_value_attr == 8'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_transmit_mode_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_tx_postdiv_clk_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_txelecidle_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_txelecidle_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_txpstate_attr == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_car_l3_cfg_txpstate_src_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_cpu_atresetn_attr == SERDES_SHIM_CPU_PM_CFG_CPU_ATRESETN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_cpu_breakin_attr == SERDES_SHIM_CPU_PM_CFG_CPU_BREAKIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_cpu_breakoutack_attr == SERDES_SHIM_CPU_PM_CFG_CPU_BREAKOUTACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_cpu_crosstriggerin_attr == SERDES_SHIM_CPU_PM_CFG_CPU_CROSSTRIGGERIN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_cpu_crosstriggeroutack_attr == SERDES_SHIM_CPU_PM_CFG_CPU_CROSSTRIGGEROUTACK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_cpu_ocdhaltonreset_attr == SERDES_SHIM_CPU_PM_CFG_CPU_OCDHALTONRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_cpu_pdebugenable_attr == SERDES_SHIM_CPU_PM_CFG_CPU_PDEBUGENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_cpu_prid_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_cpu_statvectorsel_attr == SERDES_SHIM_CPU_PM_CFG_CPU_STATVECTORSEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_cpu_tmodeclkgateoverride_reserved_attr == SERDES_SHIM_CPU_PM_CFG_CPU_TMODECLKGATEOVERRIDE_RESERVED_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_dram_pwr_mgmt_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_dram0_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_DRAM0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_dram1_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_DRAM1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_dram2_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_DRAM2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_dram3_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_DRAM3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_fifo_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_FIFO_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_iram0_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_IRAM0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_iram1_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_IRAM1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_iram2_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_IRAM2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_iram3_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_IRAM3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_iram4_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_IRAM4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_iram5_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_IRAM5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_iram6_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_IRAM6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_iram7_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_IRAM7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_clkbyp_trace_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_CLKBYP_TRACE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_dram0_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_DRAM0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_dram1_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_DRAM1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_dram2_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_DRAM2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_dram3_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_DRAM3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_fifo_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_FIFO_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_iram0_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_IRAM0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_iram1_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_IRAM1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_iram2_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_IRAM2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_iram3_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_IRAM3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_iram4_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_IRAM4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_iram5_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_IRAM5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_iram6_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_IRAM6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_iram7_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_IRAM7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_mce_trace_attr == SERDES_SHIM_CPU_PM_CFG_FUSE_MCE_TRACE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_dram0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_dram1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_dram2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_dram3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_iram0_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_iram1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_iram2_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_iram3_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_iram4_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_iram5_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_iram6_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_iram7_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_ra_trace_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_dram0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_dram1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_dram2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_dram3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_fifo_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_iram0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_iram1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_iram2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_iram3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_iram4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_iram5_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_iram6_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_iram7_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_rmce_trace_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_dram0_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_dram1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_dram2_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_dram3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_fifo_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_iram0_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_iram1_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_iram2_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_iram3_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_iram4_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_iram5_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_iram6_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_iram7_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wa_trace_attr == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_dram0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_dram1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_dram2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_dram3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_fifo_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_iram0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_iram1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_iram2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_iram3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_iram4_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_iram5_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_iram6_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_iram7_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wmce_trace_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_dram0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_dram1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_dram2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_dram3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_fifo_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_iram0_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_iram1_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_iram2_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_iram3_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_iram4_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_iram5_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_iram6_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_iram7_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fuse_wpulse_trace_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fw_status_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_fw_version_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_iramh_pwr_mgmt_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_iraml_pwr_mgmt_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_nmi_icu_mux_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_tb_reg0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_tb_reg1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_tb_reg2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_tb_reg3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_tb_reg4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_tie_queue_pwr_mgmt_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_cpu_pm_cfg_tram_pwr_mgmt_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_acc_clr_en_attr == SERDES_SHIM_DSP_L0_CFG_ACC_CLR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_acc_clr_rst_attr == SERDES_SHIM_DSP_L0_CFG_ACC_CLR_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_agc_acc_clr_attr == SERDES_SHIM_DSP_L0_CFG_AGC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_agc_clr_en_attr == SERDES_SHIM_DSP_L0_CFG_AGC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_agc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_agc_coarse_det_en_attr == SERDES_SHIM_DSP_L0_CFG_AGC_COARSE_DET_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_agc_coarse_det_pol_attr == SERDES_SHIM_DSP_L0_CFG_AGC_COARSE_DET_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_agc_d_sign_attr == SERDES_SHIM_DSP_L0_CFG_AGC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_agc_en_attr == SERDES_SHIM_DSP_L0_CFG_AGC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_agc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_agc_event_sign_attr == SERDES_SHIM_DSP_L0_CFG_AGC_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_agc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_agc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_agc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_agc_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_bb_stable_attr == SERDES_SHIM_DSP_L0_CFG_BB_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ctle_hf_stable_attr == SERDES_SHIM_DSP_L0_CFG_CTLE_HF_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_d_dly_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_data_sel_mux_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_data_width_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe10_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe11_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe12_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe13_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe14_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe15_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe16_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe1_clr_en_attr == SERDES_SHIM_DSP_L0_CFG_DFE1_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe1_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe1_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe1_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe2_16_clr_en_attr == SERDES_SHIM_DSP_L0_CFG_DFE2_16_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe2_16_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe2_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe4_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe5_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe6_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe7_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe8_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe9_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_0_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_10_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_11_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_12_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_13_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_14_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_15_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_1_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_2_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_3_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_4_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_5_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_6_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_7_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_8_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_acc_clr_9_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ACC_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_all_taps_en_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_ALL_TAPS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_0_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_10_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_11_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_12_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_13_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_14_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_15_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_1_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_2_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_3_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_4_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_5_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_6_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_7_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_8_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_adapt_en_9_attr == SERDES_SHIM_DSP_L0_CFG_DFE_ADAPT_EN_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_common_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_common_th_en_attr == SERDES_SHIM_DSP_L0_CFG_DFE_COMMON_TH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_d_sign_attr == SERDES_SHIM_DSP_L0_CFG_DFE_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_event_sign_attr == SERDES_SHIM_DSP_L0_CFG_DFE_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_tap10_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_tap11_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_tap12_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_tap13_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_tap14_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_tap15_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_tap16_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_tap1_sel_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dfe_tap9_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dsp_bit_swz_attr == SERDES_SHIM_DSP_L0_CFG_DSP_BIT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dsp_d_swz_attr == SERDES_SHIM_DSP_L0_CFG_DSP_D_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dsp_en_attr == SERDES_SHIM_DSP_L0_CFG_DSP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dsp_inner_d_swz_attr == SERDES_SHIM_DSP_L0_CFG_DSP_INNER_D_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dsp_inner_m_swz_attr == SERDES_SHIM_DSP_L0_CFG_DSP_INNER_M_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dsp_latch_dis_attr == SERDES_SHIM_DSP_L0_CFG_DSP_LATCH_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dsp_m_swz_attr == SERDES_SHIM_DSP_L0_CFG_DSP_M_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_dsp_sticky_clr_attr == SERDES_SHIM_DSP_L0_CFG_DSP_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_e_dly_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ehm_acc_clr_attr == SERDES_SHIM_DSP_L0_CFG_EHM_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ehm_event_rate_lsb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ehm_event_rate_msb_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ehm_event_sign_attr == SERDES_SHIM_DSP_L0_CFG_EHM_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ehm_sym1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ehm_sym_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ehm_tap_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ehm_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_en_duration_cnt_trig_attr == SERDES_SHIM_DSP_L0_CFG_EN_DURATION_CNT_TRIG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_en_duration_val_attr == 16'd625
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_err_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_err_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_error_counter_clr_attr == SERDES_SHIM_DSP_L0_CFG_ERROR_COUNTER_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_error_counter_enable_attr == SERDES_SHIM_DSP_L0_CFG_ERROR_COUNTER_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_error_counter_even_odd_select_attr == SERDES_SHIM_DSP_L0_CFG_ERROR_COUNTER_EVEN_ODD_SELECT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_error_counter_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_error_counter_resetb_attr == SERDES_SHIM_DSP_L0_CFG_ERROR_COUNTER_RESETB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_error_sel_mux_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_fine_attr == SERDES_SHIM_DSP_L0_CFG_FINE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_acc_clr1_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_acc_clr2_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_acc_clr3_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_acc_clr4_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_acc_clr5_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_acc_clr6_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_acc_clr7_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_acc_clr8_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_en_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L0_CFG_GAIN_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_gain_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_gps_tap32_sel_attr == SERDES_SHIM_DSP_L0_CFG_GPS_TAP32_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_gps_tap64_sel_attr == SERDES_SHIM_DSP_L0_CFG_GPS_TAP64_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ingress_dsp_disable_chkn_bit_attr == SERDES_SHIM_DSP_L0_CFG_INGRESS_DSP_DISABLE_CHKN_BIT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_io_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_joint_dfe_en_attr == SERDES_SHIM_DSP_L0_CFG_JOINT_DFE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_acc_clr_attr == SERDES_SHIM_DSP_L0_CFG_OFC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_clr_en_attr == SERDES_SHIM_DSP_L0_CFG_OFC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_cnt_offset_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_d_sign_attr == SERDES_SHIM_DSP_L0_CFG_OFC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_en_attr == SERDES_SHIM_DSP_L0_CFG_OFC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_event_sign_attr == SERDES_SHIM_DSP_L0_CFG_OFC_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_acc_clr1_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_acc_clr2_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_acc_clr3_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_acc_clr4_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_acc_clr5_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_acc_clr6_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_acc_clr7_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_acc_clr8_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_en_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L0_CFG_OFC_LSB_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_lsb_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_acc_clr1_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_acc_clr2_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_acc_clr3_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_acc_clr4_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_acc_clr5_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_acc_clr6_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_acc_clr7_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_acc_clr8_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_en_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_lsb_inv_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_LSB_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_lsb_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L0_CFG_OFC_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_ofc_th_attr == 20'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_pam4_bit_flip_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_pam4_gray_enable_attr == SERDES_SHIM_DSP_L0_CFG_PAM4_GRAY_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_pam_4_en_attr == SERDES_SHIM_DSP_L0_CFG_PAM_4_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_phase_cnt_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_phase_mask0_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_phase_mask1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_phase_mask2_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_phase_mask3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_phase_num_mask_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_pol_invert_attr == SERDES_SHIM_DSP_L0_CFG_POL_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_power_save_en_attr == SERDES_SHIM_DSP_L0_CFG_POWER_SAVE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_regs2visa_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_regs2visa_en_attr == SERDES_SHIM_DSP_L0_CFG_REGS2VISA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_res_isi_mes_en_attr == SERDES_SHIM_DSP_L0_CFG_RES_ISI_MES_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_snr_div_facror_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_snr_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_snr_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_snr_meter_en_attr == SERDES_SHIM_DSP_L0_CFG_SNR_METER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_snr_smooth_bw_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_0_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_10_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_11_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_12_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_13_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_14_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_15_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_16_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_17_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_18_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_1_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_2_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_3_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_4_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_5_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_6_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_7_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_8_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_sticky_clr_9_attr == SERDES_SHIM_DSP_L0_CFG_STICKY_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_swap_bot_en_attr == SERDES_SHIM_DSP_L0_CFG_SWAP_BOT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_swap_top_en_attr == SERDES_SHIM_DSP_L0_CFG_SWAP_TOP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_timeout_counter_value_attr == 17'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_vga_acc_clr_attr == SERDES_SHIM_DSP_L0_CFG_VGA_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_vga_clr_en_attr == SERDES_SHIM_DSP_L0_CFG_VGA_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_vga_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_vga_en_attr == SERDES_SHIM_DSP_L0_CFG_VGA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_vga_range_detect_comp_const_h_attr == 7'd126
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_vga_range_detect_comp_const_l_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_vga_range_detect_sub_const_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_vga_shift_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_vga_sticky_clr_attr == SERDES_SHIM_DSP_L0_CFG_VGA_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_vga_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_vref_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_x3_acc_clr_attr == SERDES_SHIM_DSP_L0_CFG_X3_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_x3_en_attr == SERDES_SHIM_DSP_L0_CFG_X3_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_x3_sticky_clr_attr == SERDES_SHIM_DSP_L0_CFG_X3_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l0_cfg_x3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_acc_clr_en_attr == SERDES_SHIM_DSP_L1_CFG_ACC_CLR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_acc_clr_rst_attr == SERDES_SHIM_DSP_L1_CFG_ACC_CLR_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_agc_acc_clr_attr == SERDES_SHIM_DSP_L1_CFG_AGC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_agc_clr_en_attr == SERDES_SHIM_DSP_L1_CFG_AGC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_agc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_agc_coarse_det_en_attr == SERDES_SHIM_DSP_L1_CFG_AGC_COARSE_DET_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_agc_coarse_det_pol_attr == SERDES_SHIM_DSP_L1_CFG_AGC_COARSE_DET_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_agc_d_sign_attr == SERDES_SHIM_DSP_L1_CFG_AGC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_agc_en_attr == SERDES_SHIM_DSP_L1_CFG_AGC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_agc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_agc_event_sign_attr == SERDES_SHIM_DSP_L1_CFG_AGC_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_agc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_agc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_agc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_agc_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_bb_stable_attr == SERDES_SHIM_DSP_L1_CFG_BB_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ctle_hf_stable_attr == SERDES_SHIM_DSP_L1_CFG_CTLE_HF_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_d_dly_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_data_sel_mux_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_data_width_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe10_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe11_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe12_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe13_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe14_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe15_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe16_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe1_clr_en_attr == SERDES_SHIM_DSP_L1_CFG_DFE1_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe1_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe1_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe1_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe2_16_clr_en_attr == SERDES_SHIM_DSP_L1_CFG_DFE2_16_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe2_16_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe2_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe4_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe5_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe6_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe7_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe8_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe9_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_0_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_10_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_11_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_12_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_13_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_14_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_15_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_1_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_2_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_3_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_4_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_5_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_6_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_7_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_8_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_acc_clr_9_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ACC_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_all_taps_en_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_ALL_TAPS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_0_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_10_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_11_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_12_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_13_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_14_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_15_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_1_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_2_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_3_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_4_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_5_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_6_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_7_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_8_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_adapt_en_9_attr == SERDES_SHIM_DSP_L1_CFG_DFE_ADAPT_EN_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_common_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_common_th_en_attr == SERDES_SHIM_DSP_L1_CFG_DFE_COMMON_TH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_d_sign_attr == SERDES_SHIM_DSP_L1_CFG_DFE_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_event_sign_attr == SERDES_SHIM_DSP_L1_CFG_DFE_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_tap10_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_tap11_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_tap12_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_tap13_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_tap14_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_tap15_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_tap16_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_tap1_sel_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dfe_tap9_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dsp_bit_swz_attr == SERDES_SHIM_DSP_L1_CFG_DSP_BIT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dsp_d_swz_attr == SERDES_SHIM_DSP_L1_CFG_DSP_D_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dsp_en_attr == SERDES_SHIM_DSP_L1_CFG_DSP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dsp_inner_d_swz_attr == SERDES_SHIM_DSP_L1_CFG_DSP_INNER_D_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dsp_inner_m_swz_attr == SERDES_SHIM_DSP_L1_CFG_DSP_INNER_M_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dsp_latch_dis_attr == SERDES_SHIM_DSP_L1_CFG_DSP_LATCH_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dsp_m_swz_attr == SERDES_SHIM_DSP_L1_CFG_DSP_M_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_dsp_sticky_clr_attr == SERDES_SHIM_DSP_L1_CFG_DSP_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_e_dly_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ehm_acc_clr_attr == SERDES_SHIM_DSP_L1_CFG_EHM_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ehm_event_rate_lsb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ehm_event_rate_msb_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ehm_event_sign_attr == SERDES_SHIM_DSP_L1_CFG_EHM_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ehm_sym1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ehm_sym_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ehm_tap_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ehm_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_en_duration_cnt_trig_attr == SERDES_SHIM_DSP_L1_CFG_EN_DURATION_CNT_TRIG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_en_duration_val_attr == 16'd625
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_err_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_err_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_error_counter_clr_attr == SERDES_SHIM_DSP_L1_CFG_ERROR_COUNTER_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_error_counter_enable_attr == SERDES_SHIM_DSP_L1_CFG_ERROR_COUNTER_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_error_counter_even_odd_select_attr == SERDES_SHIM_DSP_L1_CFG_ERROR_COUNTER_EVEN_ODD_SELECT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_error_counter_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_error_counter_resetb_attr == SERDES_SHIM_DSP_L1_CFG_ERROR_COUNTER_RESETB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_error_sel_mux_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_fine_attr == SERDES_SHIM_DSP_L1_CFG_FINE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_acc_clr1_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_acc_clr2_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_acc_clr3_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_acc_clr4_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_acc_clr5_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_acc_clr6_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_acc_clr7_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_acc_clr8_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_en_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L1_CFG_GAIN_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_gain_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_gps_tap32_sel_attr == SERDES_SHIM_DSP_L1_CFG_GPS_TAP32_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_gps_tap64_sel_attr == SERDES_SHIM_DSP_L1_CFG_GPS_TAP64_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ingress_dsp_disable_chkn_bit_attr == SERDES_SHIM_DSP_L1_CFG_INGRESS_DSP_DISABLE_CHKN_BIT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_io_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_joint_dfe_en_attr == SERDES_SHIM_DSP_L1_CFG_JOINT_DFE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_acc_clr_attr == SERDES_SHIM_DSP_L1_CFG_OFC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_clr_en_attr == SERDES_SHIM_DSP_L1_CFG_OFC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_cnt_offset_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_d_sign_attr == SERDES_SHIM_DSP_L1_CFG_OFC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_en_attr == SERDES_SHIM_DSP_L1_CFG_OFC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_event_sign_attr == SERDES_SHIM_DSP_L1_CFG_OFC_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_acc_clr1_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_acc_clr2_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_acc_clr3_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_acc_clr4_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_acc_clr5_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_acc_clr6_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_acc_clr7_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_acc_clr8_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_en_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L1_CFG_OFC_LSB_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_lsb_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_acc_clr1_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_acc_clr2_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_acc_clr3_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_acc_clr4_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_acc_clr5_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_acc_clr6_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_acc_clr7_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_acc_clr8_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_en_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_lsb_inv_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_LSB_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_lsb_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L1_CFG_OFC_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_ofc_th_attr == 20'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_pam4_bit_flip_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_pam4_gray_enable_attr == SERDES_SHIM_DSP_L1_CFG_PAM4_GRAY_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_pam_4_en_attr == SERDES_SHIM_DSP_L1_CFG_PAM_4_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_phase_cnt_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_phase_mask0_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_phase_mask1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_phase_mask2_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_phase_mask3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_phase_num_mask_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_pol_invert_attr == SERDES_SHIM_DSP_L1_CFG_POL_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_power_save_en_attr == SERDES_SHIM_DSP_L1_CFG_POWER_SAVE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_regs2visa_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_regs2visa_en_attr == SERDES_SHIM_DSP_L1_CFG_REGS2VISA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_res_isi_mes_en_attr == SERDES_SHIM_DSP_L1_CFG_RES_ISI_MES_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_snr_div_facror_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_snr_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_snr_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_snr_meter_en_attr == SERDES_SHIM_DSP_L1_CFG_SNR_METER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_snr_smooth_bw_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_0_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_10_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_11_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_12_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_13_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_14_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_15_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_16_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_17_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_18_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_1_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_2_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_3_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_4_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_5_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_6_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_7_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_8_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_sticky_clr_9_attr == SERDES_SHIM_DSP_L1_CFG_STICKY_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_swap_bot_en_attr == SERDES_SHIM_DSP_L1_CFG_SWAP_BOT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_swap_top_en_attr == SERDES_SHIM_DSP_L1_CFG_SWAP_TOP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_timeout_counter_value_attr == 17'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_vga_acc_clr_attr == SERDES_SHIM_DSP_L1_CFG_VGA_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_vga_clr_en_attr == SERDES_SHIM_DSP_L1_CFG_VGA_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_vga_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_vga_en_attr == SERDES_SHIM_DSP_L1_CFG_VGA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_vga_range_detect_comp_const_h_attr == 7'd126
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_vga_range_detect_comp_const_l_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_vga_range_detect_sub_const_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_vga_shift_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_vga_sticky_clr_attr == SERDES_SHIM_DSP_L1_CFG_VGA_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_vga_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_vref_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_x3_acc_clr_attr == SERDES_SHIM_DSP_L1_CFG_X3_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_x3_en_attr == SERDES_SHIM_DSP_L1_CFG_X3_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_x3_sticky_clr_attr == SERDES_SHIM_DSP_L1_CFG_X3_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l1_cfg_x3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_acc_clr_en_attr == SERDES_SHIM_DSP_L2_CFG_ACC_CLR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_acc_clr_rst_attr == SERDES_SHIM_DSP_L2_CFG_ACC_CLR_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_agc_acc_clr_attr == SERDES_SHIM_DSP_L2_CFG_AGC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_agc_clr_en_attr == SERDES_SHIM_DSP_L2_CFG_AGC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_agc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_agc_coarse_det_en_attr == SERDES_SHIM_DSP_L2_CFG_AGC_COARSE_DET_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_agc_coarse_det_pol_attr == SERDES_SHIM_DSP_L2_CFG_AGC_COARSE_DET_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_agc_d_sign_attr == SERDES_SHIM_DSP_L2_CFG_AGC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_agc_en_attr == SERDES_SHIM_DSP_L2_CFG_AGC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_agc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_agc_event_sign_attr == SERDES_SHIM_DSP_L2_CFG_AGC_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_agc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_agc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_agc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_agc_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_bb_stable_attr == SERDES_SHIM_DSP_L2_CFG_BB_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ctle_hf_stable_attr == SERDES_SHIM_DSP_L2_CFG_CTLE_HF_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_d_dly_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_data_sel_mux_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_data_width_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe10_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe11_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe12_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe13_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe14_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe15_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe16_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe1_clr_en_attr == SERDES_SHIM_DSP_L2_CFG_DFE1_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe1_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe1_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe1_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe2_16_clr_en_attr == SERDES_SHIM_DSP_L2_CFG_DFE2_16_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe2_16_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe2_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe4_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe5_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe6_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe7_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe8_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe9_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_0_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_10_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_11_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_12_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_13_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_14_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_15_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_1_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_2_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_3_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_4_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_5_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_6_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_7_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_8_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_acc_clr_9_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ACC_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_all_taps_en_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_ALL_TAPS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_0_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_10_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_11_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_12_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_13_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_14_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_15_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_1_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_2_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_3_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_4_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_5_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_6_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_7_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_8_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_adapt_en_9_attr == SERDES_SHIM_DSP_L2_CFG_DFE_ADAPT_EN_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_common_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_common_th_en_attr == SERDES_SHIM_DSP_L2_CFG_DFE_COMMON_TH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_d_sign_attr == SERDES_SHIM_DSP_L2_CFG_DFE_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_event_sign_attr == SERDES_SHIM_DSP_L2_CFG_DFE_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_tap10_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_tap11_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_tap12_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_tap13_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_tap14_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_tap15_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_tap16_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_tap1_sel_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dfe_tap9_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dsp_bit_swz_attr == SERDES_SHIM_DSP_L2_CFG_DSP_BIT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dsp_d_swz_attr == SERDES_SHIM_DSP_L2_CFG_DSP_D_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dsp_en_attr == SERDES_SHIM_DSP_L2_CFG_DSP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dsp_inner_d_swz_attr == SERDES_SHIM_DSP_L2_CFG_DSP_INNER_D_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dsp_inner_m_swz_attr == SERDES_SHIM_DSP_L2_CFG_DSP_INNER_M_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dsp_latch_dis_attr == SERDES_SHIM_DSP_L2_CFG_DSP_LATCH_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dsp_m_swz_attr == SERDES_SHIM_DSP_L2_CFG_DSP_M_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_dsp_sticky_clr_attr == SERDES_SHIM_DSP_L2_CFG_DSP_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_e_dly_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ehm_acc_clr_attr == SERDES_SHIM_DSP_L2_CFG_EHM_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ehm_event_rate_lsb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ehm_event_rate_msb_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ehm_event_sign_attr == SERDES_SHIM_DSP_L2_CFG_EHM_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ehm_sym1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ehm_sym_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ehm_tap_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ehm_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_en_duration_cnt_trig_attr == SERDES_SHIM_DSP_L2_CFG_EN_DURATION_CNT_TRIG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_en_duration_val_attr == 16'd625
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_err_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_err_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_error_counter_clr_attr == SERDES_SHIM_DSP_L2_CFG_ERROR_COUNTER_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_error_counter_enable_attr == SERDES_SHIM_DSP_L2_CFG_ERROR_COUNTER_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_error_counter_even_odd_select_attr == SERDES_SHIM_DSP_L2_CFG_ERROR_COUNTER_EVEN_ODD_SELECT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_error_counter_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_error_counter_resetb_attr == SERDES_SHIM_DSP_L2_CFG_ERROR_COUNTER_RESETB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_error_sel_mux_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_fine_attr == SERDES_SHIM_DSP_L2_CFG_FINE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_acc_clr1_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_acc_clr2_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_acc_clr3_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_acc_clr4_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_acc_clr5_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_acc_clr6_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_acc_clr7_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_acc_clr8_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_en_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L2_CFG_GAIN_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_gain_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_gps_tap32_sel_attr == SERDES_SHIM_DSP_L2_CFG_GPS_TAP32_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_gps_tap64_sel_attr == SERDES_SHIM_DSP_L2_CFG_GPS_TAP64_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ingress_dsp_disable_chkn_bit_attr == SERDES_SHIM_DSP_L2_CFG_INGRESS_DSP_DISABLE_CHKN_BIT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_io_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_joint_dfe_en_attr == SERDES_SHIM_DSP_L2_CFG_JOINT_DFE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_acc_clr_attr == SERDES_SHIM_DSP_L2_CFG_OFC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_clr_en_attr == SERDES_SHIM_DSP_L2_CFG_OFC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_cnt_offset_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_d_sign_attr == SERDES_SHIM_DSP_L2_CFG_OFC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_en_attr == SERDES_SHIM_DSP_L2_CFG_OFC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_event_sign_attr == SERDES_SHIM_DSP_L2_CFG_OFC_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_acc_clr1_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_acc_clr2_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_acc_clr3_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_acc_clr4_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_acc_clr5_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_acc_clr6_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_acc_clr7_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_acc_clr8_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_en_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L2_CFG_OFC_LSB_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_lsb_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_acc_clr1_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_acc_clr2_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_acc_clr3_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_acc_clr4_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_acc_clr5_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_acc_clr6_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_acc_clr7_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_acc_clr8_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_en_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_lsb_inv_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_LSB_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_lsb_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L2_CFG_OFC_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_ofc_th_attr == 20'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_pam4_bit_flip_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_pam4_gray_enable_attr == SERDES_SHIM_DSP_L2_CFG_PAM4_GRAY_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_pam_4_en_attr == SERDES_SHIM_DSP_L2_CFG_PAM_4_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_phase_cnt_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_phase_mask0_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_phase_mask1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_phase_mask2_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_phase_mask3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_phase_num_mask_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_pol_invert_attr == SERDES_SHIM_DSP_L2_CFG_POL_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_power_save_en_attr == SERDES_SHIM_DSP_L2_CFG_POWER_SAVE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_regs2visa_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_regs2visa_en_attr == SERDES_SHIM_DSP_L2_CFG_REGS2VISA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_res_isi_mes_en_attr == SERDES_SHIM_DSP_L2_CFG_RES_ISI_MES_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_snr_div_facror_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_snr_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_snr_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_snr_meter_en_attr == SERDES_SHIM_DSP_L2_CFG_SNR_METER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_snr_smooth_bw_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_0_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_10_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_11_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_12_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_13_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_14_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_15_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_16_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_17_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_18_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_1_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_2_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_3_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_4_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_5_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_6_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_7_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_8_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_sticky_clr_9_attr == SERDES_SHIM_DSP_L2_CFG_STICKY_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_swap_bot_en_attr == SERDES_SHIM_DSP_L2_CFG_SWAP_BOT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_swap_top_en_attr == SERDES_SHIM_DSP_L2_CFG_SWAP_TOP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_timeout_counter_value_attr == 17'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_vga_acc_clr_attr == SERDES_SHIM_DSP_L2_CFG_VGA_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_vga_clr_en_attr == SERDES_SHIM_DSP_L2_CFG_VGA_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_vga_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_vga_en_attr == SERDES_SHIM_DSP_L2_CFG_VGA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_vga_range_detect_comp_const_h_attr == 7'd126
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_vga_range_detect_comp_const_l_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_vga_range_detect_sub_const_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_vga_shift_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_vga_sticky_clr_attr == SERDES_SHIM_DSP_L2_CFG_VGA_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_vga_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_vref_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_x3_acc_clr_attr == SERDES_SHIM_DSP_L2_CFG_X3_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_x3_en_attr == SERDES_SHIM_DSP_L2_CFG_X3_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_x3_sticky_clr_attr == SERDES_SHIM_DSP_L2_CFG_X3_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l2_cfg_x3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_acc_clr_en_attr == SERDES_SHIM_DSP_L3_CFG_ACC_CLR_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_acc_clr_rst_attr == SERDES_SHIM_DSP_L3_CFG_ACC_CLR_RST_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_agc_acc_clr_attr == SERDES_SHIM_DSP_L3_CFG_AGC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_agc_clr_en_attr == SERDES_SHIM_DSP_L3_CFG_AGC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_agc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_agc_coarse_det_en_attr == SERDES_SHIM_DSP_L3_CFG_AGC_COARSE_DET_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_agc_coarse_det_pol_attr == SERDES_SHIM_DSP_L3_CFG_AGC_COARSE_DET_POL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_agc_d_sign_attr == SERDES_SHIM_DSP_L3_CFG_AGC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_agc_en_attr == SERDES_SHIM_DSP_L3_CFG_AGC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_agc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_agc_event_sign_attr == SERDES_SHIM_DSP_L3_CFG_AGC_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_agc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_agc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_agc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_agc_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_bb_stable_attr == SERDES_SHIM_DSP_L3_CFG_BB_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ctle_hf_stable_attr == SERDES_SHIM_DSP_L3_CFG_CTLE_HF_STABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_d_dly_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_data_sel_mux_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_data_width_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe10_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe11_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe12_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe13_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe14_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe15_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe16_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe1_clr_en_attr == SERDES_SHIM_DSP_L3_CFG_DFE1_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe1_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe1_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe1_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe2_16_clr_en_attr == SERDES_SHIM_DSP_L3_CFG_DFE2_16_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe2_16_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe2_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe4_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe5_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe6_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe7_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe8_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe9_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_0_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_10_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_11_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_12_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_13_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_14_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_15_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_1_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_2_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_3_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_4_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_5_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_6_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_7_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_8_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_acc_clr_9_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ACC_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_all_taps_en_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_ALL_TAPS_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_0_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_10_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_11_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_12_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_13_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_14_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_15_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_1_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_2_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_3_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_4_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_5_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_6_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_7_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_8_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_adapt_en_9_attr == SERDES_SHIM_DSP_L3_CFG_DFE_ADAPT_EN_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_common_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_common_th_en_attr == SERDES_SHIM_DSP_L3_CFG_DFE_COMMON_TH_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_d_sign_attr == SERDES_SHIM_DSP_L3_CFG_DFE_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_event_sign_attr == SERDES_SHIM_DSP_L3_CFG_DFE_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_tap10_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_tap11_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_tap12_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_tap13_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_tap14_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_tap15_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_tap16_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_tap1_sel_attr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dfe_tap9_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dsp_bit_swz_attr == SERDES_SHIM_DSP_L3_CFG_DSP_BIT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dsp_d_swz_attr == SERDES_SHIM_DSP_L3_CFG_DSP_D_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dsp_en_attr == SERDES_SHIM_DSP_L3_CFG_DSP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dsp_inner_d_swz_attr == SERDES_SHIM_DSP_L3_CFG_DSP_INNER_D_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dsp_inner_m_swz_attr == SERDES_SHIM_DSP_L3_CFG_DSP_INNER_M_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dsp_latch_dis_attr == SERDES_SHIM_DSP_L3_CFG_DSP_LATCH_DIS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dsp_m_swz_attr == SERDES_SHIM_DSP_L3_CFG_DSP_M_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_dsp_sticky_clr_attr == SERDES_SHIM_DSP_L3_CFG_DSP_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_e_dly_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ehm_acc_clr_attr == SERDES_SHIM_DSP_L3_CFG_EHM_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ehm_event_rate_lsb_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ehm_event_rate_msb_attr == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ehm_event_sign_attr == SERDES_SHIM_DSP_L3_CFG_EHM_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ehm_sym1_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ehm_sym_attr == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ehm_tap_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ehm_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_en_duration_cnt_trig_attr == SERDES_SHIM_DSP_L3_CFG_EN_DURATION_CNT_TRIG_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_en_duration_val_attr == 16'd625
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_err_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_err_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_error_counter_clr_attr == SERDES_SHIM_DSP_L3_CFG_ERROR_COUNTER_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_error_counter_enable_attr == SERDES_SHIM_DSP_L3_CFG_ERROR_COUNTER_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_error_counter_even_odd_select_attr == SERDES_SHIM_DSP_L3_CFG_ERROR_COUNTER_EVEN_ODD_SELECT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_error_counter_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_error_counter_resetb_attr == SERDES_SHIM_DSP_L3_CFG_ERROR_COUNTER_RESETB_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_error_sel_mux_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_fine_attr == SERDES_SHIM_DSP_L3_CFG_FINE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_acc_clr1_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_acc_clr2_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_acc_clr3_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_acc_clr4_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_acc_clr5_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_acc_clr6_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_acc_clr7_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_acc_clr8_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_en_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L3_CFG_GAIN_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_gain_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_gps_tap32_sel_attr == SERDES_SHIM_DSP_L3_CFG_GPS_TAP32_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_gps_tap64_sel_attr == SERDES_SHIM_DSP_L3_CFG_GPS_TAP64_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ingress_dsp_disable_chkn_bit_attr == SERDES_SHIM_DSP_L3_CFG_INGRESS_DSP_DISABLE_CHKN_BIT_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_io_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_joint_dfe_en_attr == SERDES_SHIM_DSP_L3_CFG_JOINT_DFE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_acc_clr_attr == SERDES_SHIM_DSP_L3_CFG_OFC_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_clr_en_attr == SERDES_SHIM_DSP_L3_CFG_OFC_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_cnt_offset_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_d_sign_attr == SERDES_SHIM_DSP_L3_CFG_OFC_D_SIGN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_en_attr == SERDES_SHIM_DSP_L3_CFG_OFC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_event_rate_attr == 6'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_event_sign_attr == SERDES_SHIM_DSP_L3_CFG_OFC_EVENT_SIGN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_acc_clr1_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_acc_clr2_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_acc_clr3_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_acc_clr4_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_acc_clr5_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_acc_clr6_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_acc_clr7_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_acc_clr8_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_en_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L3_CFG_OFC_LSB_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_lsb_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_mask0_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_mask1_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_mask2_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_acc_clr1_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_ACC_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_acc_clr2_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_ACC_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_acc_clr3_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_ACC_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_acc_clr4_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_ACC_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_acc_clr5_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_ACC_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_acc_clr6_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_ACC_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_acc_clr7_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_ACC_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_acc_clr8_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_ACC_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_en_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_lsb_inv_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_LSB_INV_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_lsb_sel_attr == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_num1_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_num2_attr == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_num3_attr == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_num4_attr == 6'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_num5_attr == 6'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_num6_attr == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_num7_attr == 6'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_num8_attr == 6'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_sticky_clr1_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_STICKY_CLR1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_sticky_clr2_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_STICKY_CLR2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_sticky_clr3_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_STICKY_CLR3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_sticky_clr4_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_STICKY_CLR4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_sticky_clr5_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_STICKY_CLR5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_sticky_clr6_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_STICKY_CLR6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_sticky_clr7_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_STICKY_CLR7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_sticky_clr8_attr == SERDES_SHIM_DSP_L3_CFG_OFC_SAR_STICKY_CLR8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_sar_th_attr == 20'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_ofc_th_attr == 20'd2048
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_pam4_bit_flip_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_pam4_gray_enable_attr == SERDES_SHIM_DSP_L3_CFG_PAM4_GRAY_ENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_pam_4_en_attr == SERDES_SHIM_DSP_L3_CFG_PAM_4_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_phase_cnt_th_attr == 20'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_phase_mask0_attr == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_phase_mask1_attr == 4'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_phase_mask2_attr == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_phase_mask3_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_phase_num_mask_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_pol_invert_attr == SERDES_SHIM_DSP_L3_CFG_POL_INVERT_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_power_save_en_attr == SERDES_SHIM_DSP_L3_CFG_POWER_SAVE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_regs2visa_addr_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_regs2visa_en_attr == SERDES_SHIM_DSP_L3_CFG_REGS2VISA_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_res_isi_mes_en_attr == SERDES_SHIM_DSP_L3_CFG_RES_ISI_MES_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_snr_div_facror_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_snr_mask_lsb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_snr_mask_msb_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_snr_meter_en_attr == SERDES_SHIM_DSP_L3_CFG_SNR_METER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_snr_smooth_bw_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_0_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_10_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_10_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_11_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_11_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_12_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_12_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_13_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_13_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_14_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_14_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_15_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_15_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_16_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_16_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_17_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_17_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_18_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_18_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_1_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_2_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_3_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_4_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_4_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_5_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_5_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_6_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_6_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_7_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_7_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_8_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_8_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_sticky_clr_9_attr == SERDES_SHIM_DSP_L3_CFG_STICKY_CLR_9_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_swap_bot_en_attr == SERDES_SHIM_DSP_L3_CFG_SWAP_BOT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_swap_top_en_attr == SERDES_SHIM_DSP_L3_CFG_SWAP_TOP_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_timeout_counter_value_attr == 17'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_vga_acc_clr_attr == SERDES_SHIM_DSP_L3_CFG_VGA_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_vga_clr_en_attr == SERDES_SHIM_DSP_L3_CFG_VGA_CLR_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_vga_clr_sel_attr == 4'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_vga_en_attr == SERDES_SHIM_DSP_L3_CFG_VGA_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_vga_range_detect_comp_const_h_attr == 7'd126
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_vga_range_detect_comp_const_l_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_vga_range_detect_sub_const_attr == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_vga_shift_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_vga_sticky_clr_attr == SERDES_SHIM_DSP_L3_CFG_VGA_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_vga_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_vref_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_x3_acc_clr_attr == SERDES_SHIM_DSP_L3_CFG_X3_ACC_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_x3_en_attr == SERDES_SHIM_DSP_L3_CFG_X3_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_x3_sticky_clr_attr == SERDES_SHIM_DSP_L3_CFG_X3_STICKY_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_dsp_l3_cfg_x3_th_attr == 20'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_cfg_prbs13_seed_2_attr == 13'd7571
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_cfg_prbs13_seed_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_cfg_tfl_prbs11_en_attr == SERDES_SHIM_TFL_L0_CFG_CFG_TFL_PRBS11_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_cl136_ctrl_field_11_10_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_cl136_ctrl_field_13_12_init_cond_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_cl136_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_cl136_ctrl_field_1_0_coeff_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_cl136_ctrl_field_4_2_coeff_select_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_cl136_ctrl_field_7_5_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_cl136_ctrl_field_9_8_mod_precode_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_cl136_frame_cycle_to_lock_attr == 10'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_cl136_prbs_encoder_select_even_attr == SERDES_SHIM_TFL_L0_CFG_CL136_PRBS_ENCODER_SELECT_EVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_cl136_precoder_out_swz_attr == SERDES_SHIM_TFL_L0_CFG_CL136_PRECODER_OUT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_cl136_precoder_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_cl136_stts_field_11_10_mod_precode_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_cl136_stts_field_14_12_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_cl136_stts_field_15_rx_ready_attr == SERDES_SHIM_TFL_L0_CFG_CL136_STTS_FIELD_15_RX_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_cl136_stts_field_2_0_coeff_stts_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_cl136_stts_field_5_3_coeff_sel_echo_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_cl136_stts_field_6_rsvd_attr == SERDES_SHIM_TFL_L0_CFG_CL136_STTS_FIELD_6_RSVD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_cl136_stts_field_7_parity_attr == SERDES_SHIM_TFL_L0_CFG_CL136_STTS_FIELD_7_PARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_cl136_stts_field_8_init_cond_stts_attr == SERDES_SHIM_TFL_L0_CFG_CL136_STTS_FIELD_8_INIT_COND_STTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_cl136_stts_field_9_rx_frame_lock_attr == SERDES_SHIM_TFL_L0_CFG_CL136_STTS_FIELD_9_RX_FRAME_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_cl72_ctrl_field_11_6_rsvd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_cl72_ctrl_field_12_initialize_attr == SERDES_SHIM_TFL_L0_CFG_CL72_CTRL_FIELD_12_INITIALIZE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_cl72_ctrl_field_13_preset_attr == SERDES_SHIM_TFL_L0_CFG_CL72_CTRL_FIELD_13_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_cl72_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_cl72_ctrl_field_1_0_coef_m1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_cl72_ctrl_field_3_2_coef_0_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_cl72_ctrl_field_5_4_coef_p1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_cl72_frame_cycle_to_lock_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_cl72_stts_field_14_6_rsvd_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_cl72_stts_field_15_rcv_ready_attr == SERDES_SHIM_TFL_L0_CFG_CL72_STTS_FIELD_15_RCV_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_cl72_stts_field_1_0_coef_m1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_cl72_stts_field_3_2_coef_0_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_cl72_stts_field_5_4_coef_p1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_frame_boundary_early_attr == SERDES_SHIM_TFL_L0_CFG_FRAME_BOUNDARY_EARLY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_gb_128_80_en_attr == SERDES_SHIM_TFL_L0_CFG_GB_128_80_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_ignore_tfl_en_to_avoid_cut_frame_attr == SERDES_SHIM_TFL_L0_CFG_IGNORE_TFL_EN_TO_AVOID_CUT_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_polynomial_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_prbs11_seed_2_attr == 11'd977
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_prbs11_seed_attr == 11'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_ber_count_snap_lock_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL136_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_ber_counter_clear_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL136_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_clear_one_marker_seen_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL136_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL136_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL136_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL136_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_pam4_modulation_select_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_prbs_ber_en_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL136_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_prbs_seed_force_en_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL136_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_prbs_seed_force_val_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_cl136_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_ber_count_snap_lock_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL72_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_ber_counter_clear_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL72_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_clear_one_marker_seen_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL72_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL72_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL72_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL72_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_prbs_ber_en_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL72_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_prbs_seed_force_en_attr == SERDES_SHIM_TFL_L0_CFG_RX_CL72_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_prbs_seed_force_val_attr == 13'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_cl72_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_gb_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_rx_sync_pulse_attr == SERDES_SHIM_TFL_L0_CFG_RX_SYNC_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_scrambler_force_init_at_each_frame_attr == SERDES_SHIM_TFL_L0_CFG_SCRAMBLER_FORCE_INIT_AT_EACH_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_send_data_attr == SERDES_SHIM_TFL_L0_CFG_SEND_DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_sync_ctrl_stts_word_pulse_attr == SERDES_SHIM_TFL_L0_CFG_SYNC_CTRL_STTS_WORD_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_tfl_prbs13_en_attr == SERDES_SHIM_TFL_L0_CFG_TFL_PRBS13_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_tfl_pulse_sync_attr == SERDES_SHIM_TFL_L0_CFG_TFL_PULSE_SYNC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_tfl_training_enable_rx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_tfl_training_enable_tx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l0_cfg_tx_gb_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_cfg_prbs13_seed_2_attr == 13'd7571
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_cfg_prbs13_seed_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_cfg_tfl_prbs11_en_attr == SERDES_SHIM_TFL_L1_CFG_CFG_TFL_PRBS11_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_cl136_ctrl_field_11_10_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_cl136_ctrl_field_13_12_init_cond_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_cl136_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_cl136_ctrl_field_1_0_coeff_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_cl136_ctrl_field_4_2_coeff_select_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_cl136_ctrl_field_7_5_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_cl136_ctrl_field_9_8_mod_precode_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_cl136_frame_cycle_to_lock_attr == 10'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_cl136_prbs_encoder_select_even_attr == SERDES_SHIM_TFL_L1_CFG_CL136_PRBS_ENCODER_SELECT_EVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_cl136_precoder_out_swz_attr == SERDES_SHIM_TFL_L1_CFG_CL136_PRECODER_OUT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_cl136_precoder_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_cl136_stts_field_11_10_mod_precode_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_cl136_stts_field_14_12_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_cl136_stts_field_15_rx_ready_attr == SERDES_SHIM_TFL_L1_CFG_CL136_STTS_FIELD_15_RX_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_cl136_stts_field_2_0_coeff_stts_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_cl136_stts_field_5_3_coeff_sel_echo_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_cl136_stts_field_6_rsvd_attr == SERDES_SHIM_TFL_L1_CFG_CL136_STTS_FIELD_6_RSVD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_cl136_stts_field_7_parity_attr == SERDES_SHIM_TFL_L1_CFG_CL136_STTS_FIELD_7_PARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_cl136_stts_field_8_init_cond_stts_attr == SERDES_SHIM_TFL_L1_CFG_CL136_STTS_FIELD_8_INIT_COND_STTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_cl136_stts_field_9_rx_frame_lock_attr == SERDES_SHIM_TFL_L1_CFG_CL136_STTS_FIELD_9_RX_FRAME_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_cl72_ctrl_field_11_6_rsvd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_cl72_ctrl_field_12_initialize_attr == SERDES_SHIM_TFL_L1_CFG_CL72_CTRL_FIELD_12_INITIALIZE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_cl72_ctrl_field_13_preset_attr == SERDES_SHIM_TFL_L1_CFG_CL72_CTRL_FIELD_13_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_cl72_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_cl72_ctrl_field_1_0_coef_m1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_cl72_ctrl_field_3_2_coef_0_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_cl72_ctrl_field_5_4_coef_p1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_cl72_frame_cycle_to_lock_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_cl72_stts_field_14_6_rsvd_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_cl72_stts_field_15_rcv_ready_attr == SERDES_SHIM_TFL_L1_CFG_CL72_STTS_FIELD_15_RCV_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_cl72_stts_field_1_0_coef_m1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_cl72_stts_field_3_2_coef_0_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_cl72_stts_field_5_4_coef_p1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_frame_boundary_early_attr == SERDES_SHIM_TFL_L1_CFG_FRAME_BOUNDARY_EARLY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_gb_128_80_en_attr == SERDES_SHIM_TFL_L1_CFG_GB_128_80_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_ignore_tfl_en_to_avoid_cut_frame_attr == SERDES_SHIM_TFL_L1_CFG_IGNORE_TFL_EN_TO_AVOID_CUT_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_polynomial_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_prbs11_seed_2_attr == 11'd977
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_prbs11_seed_attr == 11'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_ber_count_snap_lock_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL136_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_ber_counter_clear_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL136_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_clear_one_marker_seen_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL136_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL136_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL136_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL136_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_pam4_modulation_select_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_prbs_ber_en_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL136_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_prbs_seed_force_en_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL136_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_prbs_seed_force_val_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_cl136_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_ber_count_snap_lock_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL72_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_ber_counter_clear_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL72_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_clear_one_marker_seen_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL72_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL72_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL72_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL72_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_prbs_ber_en_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL72_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_prbs_seed_force_en_attr == SERDES_SHIM_TFL_L1_CFG_RX_CL72_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_prbs_seed_force_val_attr == 13'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_cl72_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_gb_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_rx_sync_pulse_attr == SERDES_SHIM_TFL_L1_CFG_RX_SYNC_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_scrambler_force_init_at_each_frame_attr == SERDES_SHIM_TFL_L1_CFG_SCRAMBLER_FORCE_INIT_AT_EACH_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_send_data_attr == SERDES_SHIM_TFL_L1_CFG_SEND_DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_sync_ctrl_stts_word_pulse_attr == SERDES_SHIM_TFL_L1_CFG_SYNC_CTRL_STTS_WORD_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_tfl_prbs13_en_attr == SERDES_SHIM_TFL_L1_CFG_TFL_PRBS13_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_tfl_pulse_sync_attr == SERDES_SHIM_TFL_L1_CFG_TFL_PULSE_SYNC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_tfl_training_enable_rx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_tfl_training_enable_tx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l1_cfg_tx_gb_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_cfg_prbs13_seed_2_attr == 13'd7571
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_cfg_prbs13_seed_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_cfg_tfl_prbs11_en_attr == SERDES_SHIM_TFL_L2_CFG_CFG_TFL_PRBS11_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_cl136_ctrl_field_11_10_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_cl136_ctrl_field_13_12_init_cond_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_cl136_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_cl136_ctrl_field_1_0_coeff_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_cl136_ctrl_field_4_2_coeff_select_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_cl136_ctrl_field_7_5_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_cl136_ctrl_field_9_8_mod_precode_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_cl136_frame_cycle_to_lock_attr == 10'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_cl136_prbs_encoder_select_even_attr == SERDES_SHIM_TFL_L2_CFG_CL136_PRBS_ENCODER_SELECT_EVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_cl136_precoder_out_swz_attr == SERDES_SHIM_TFL_L2_CFG_CL136_PRECODER_OUT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_cl136_precoder_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_cl136_stts_field_11_10_mod_precode_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_cl136_stts_field_14_12_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_cl136_stts_field_15_rx_ready_attr == SERDES_SHIM_TFL_L2_CFG_CL136_STTS_FIELD_15_RX_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_cl136_stts_field_2_0_coeff_stts_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_cl136_stts_field_5_3_coeff_sel_echo_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_cl136_stts_field_6_rsvd_attr == SERDES_SHIM_TFL_L2_CFG_CL136_STTS_FIELD_6_RSVD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_cl136_stts_field_7_parity_attr == SERDES_SHIM_TFL_L2_CFG_CL136_STTS_FIELD_7_PARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_cl136_stts_field_8_init_cond_stts_attr == SERDES_SHIM_TFL_L2_CFG_CL136_STTS_FIELD_8_INIT_COND_STTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_cl136_stts_field_9_rx_frame_lock_attr == SERDES_SHIM_TFL_L2_CFG_CL136_STTS_FIELD_9_RX_FRAME_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_cl72_ctrl_field_11_6_rsvd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_cl72_ctrl_field_12_initialize_attr == SERDES_SHIM_TFL_L2_CFG_CL72_CTRL_FIELD_12_INITIALIZE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_cl72_ctrl_field_13_preset_attr == SERDES_SHIM_TFL_L2_CFG_CL72_CTRL_FIELD_13_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_cl72_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_cl72_ctrl_field_1_0_coef_m1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_cl72_ctrl_field_3_2_coef_0_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_cl72_ctrl_field_5_4_coef_p1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_cl72_frame_cycle_to_lock_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_cl72_stts_field_14_6_rsvd_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_cl72_stts_field_15_rcv_ready_attr == SERDES_SHIM_TFL_L2_CFG_CL72_STTS_FIELD_15_RCV_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_cl72_stts_field_1_0_coef_m1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_cl72_stts_field_3_2_coef_0_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_cl72_stts_field_5_4_coef_p1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_frame_boundary_early_attr == SERDES_SHIM_TFL_L2_CFG_FRAME_BOUNDARY_EARLY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_gb_128_80_en_attr == SERDES_SHIM_TFL_L2_CFG_GB_128_80_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_ignore_tfl_en_to_avoid_cut_frame_attr == SERDES_SHIM_TFL_L2_CFG_IGNORE_TFL_EN_TO_AVOID_CUT_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_polynomial_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_prbs11_seed_2_attr == 11'd977
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_prbs11_seed_attr == 11'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_ber_count_snap_lock_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL136_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_ber_counter_clear_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL136_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_clear_one_marker_seen_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL136_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL136_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL136_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL136_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_pam4_modulation_select_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_prbs_ber_en_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL136_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_prbs_seed_force_en_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL136_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_prbs_seed_force_val_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_cl136_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_ber_count_snap_lock_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL72_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_ber_counter_clear_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL72_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_clear_one_marker_seen_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL72_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL72_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL72_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL72_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_prbs_ber_en_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL72_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_prbs_seed_force_en_attr == SERDES_SHIM_TFL_L2_CFG_RX_CL72_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_prbs_seed_force_val_attr == 13'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_cl72_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_gb_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_rx_sync_pulse_attr == SERDES_SHIM_TFL_L2_CFG_RX_SYNC_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_scrambler_force_init_at_each_frame_attr == SERDES_SHIM_TFL_L2_CFG_SCRAMBLER_FORCE_INIT_AT_EACH_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_send_data_attr == SERDES_SHIM_TFL_L2_CFG_SEND_DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_sync_ctrl_stts_word_pulse_attr == SERDES_SHIM_TFL_L2_CFG_SYNC_CTRL_STTS_WORD_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_tfl_prbs13_en_attr == SERDES_SHIM_TFL_L2_CFG_TFL_PRBS13_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_tfl_pulse_sync_attr == SERDES_SHIM_TFL_L2_CFG_TFL_PULSE_SYNC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_tfl_training_enable_rx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_tfl_training_enable_tx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l2_cfg_tx_gb_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_cfg_prbs13_seed_2_attr == 13'd7571
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_cfg_prbs13_seed_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_cfg_tfl_prbs11_en_attr == SERDES_SHIM_TFL_L3_CFG_CFG_TFL_PRBS11_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_cl136_ctrl_field_11_10_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_cl136_ctrl_field_13_12_init_cond_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_cl136_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_cl136_ctrl_field_1_0_coeff_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_cl136_ctrl_field_4_2_coeff_select_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_cl136_ctrl_field_7_5_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_cl136_ctrl_field_9_8_mod_precode_req_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_cl136_frame_cycle_to_lock_attr == 10'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_cl136_prbs_encoder_select_even_attr == SERDES_SHIM_TFL_L3_CFG_CL136_PRBS_ENCODER_SELECT_EVEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_cl136_precoder_out_swz_attr == SERDES_SHIM_TFL_L3_CFG_CL136_PRECODER_OUT_SWZ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_cl136_precoder_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_cl136_stts_field_11_10_mod_precode_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_cl136_stts_field_14_12_rsvd_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_cl136_stts_field_15_rx_ready_attr == SERDES_SHIM_TFL_L3_CFG_CL136_STTS_FIELD_15_RX_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_cl136_stts_field_2_0_coeff_stts_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_cl136_stts_field_5_3_coeff_sel_echo_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_cl136_stts_field_6_rsvd_attr == SERDES_SHIM_TFL_L3_CFG_CL136_STTS_FIELD_6_RSVD_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_cl136_stts_field_7_parity_attr == SERDES_SHIM_TFL_L3_CFG_CL136_STTS_FIELD_7_PARITY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_cl136_stts_field_8_init_cond_stts_attr == SERDES_SHIM_TFL_L3_CFG_CL136_STTS_FIELD_8_INIT_COND_STTS_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_cl136_stts_field_9_rx_frame_lock_attr == SERDES_SHIM_TFL_L3_CFG_CL136_STTS_FIELD_9_RX_FRAME_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_cl72_ctrl_field_11_6_rsvd_attr == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_cl72_ctrl_field_12_initialize_attr == SERDES_SHIM_TFL_L3_CFG_CL72_CTRL_FIELD_12_INITIALIZE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_cl72_ctrl_field_13_preset_attr == SERDES_SHIM_TFL_L3_CFG_CL72_CTRL_FIELD_13_PRESET_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_cl72_ctrl_field_15_14_rsvd_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_cl72_ctrl_field_1_0_coef_m1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_cl72_ctrl_field_3_2_coef_0_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_cl72_ctrl_field_5_4_coef_p1_update_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_cl72_frame_cycle_to_lock_attr == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_cl72_stts_field_14_6_rsvd_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_cl72_stts_field_15_rcv_ready_attr == SERDES_SHIM_TFL_L3_CFG_CL72_STTS_FIELD_15_RCV_READY_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_cl72_stts_field_1_0_coef_m1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_cl72_stts_field_3_2_coef_0_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_cl72_stts_field_5_4_coef_p1_stts_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_frame_boundary_early_attr == SERDES_SHIM_TFL_L3_CFG_FRAME_BOUNDARY_EARLY_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_gb_128_80_en_attr == SERDES_SHIM_TFL_L3_CFG_GB_128_80_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_ignore_tfl_en_to_avoid_cut_frame_attr == SERDES_SHIM_TFL_L3_CFG_IGNORE_TFL_EN_TO_AVOID_CUT_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_polynomial_sel_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_prbs11_seed_2_attr == 11'd977
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_prbs11_seed_attr == 11'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_ber_count_snap_lock_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL136_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_ber_counter_clear_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL136_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_clear_one_marker_seen_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL136_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL136_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL136_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL136_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_pam4_modulation_select_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_prbs_ber_en_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL136_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_prbs_seed_force_en_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL136_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_prbs_seed_force_val_attr == 13'd6816
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_cl136_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_ber_count_snap_lock_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL72_BER_COUNT_SNAP_LOCK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_ber_counter_clear_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL72_BER_COUNTER_CLEAR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_clear_one_marker_seen_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL72_CLEAR_ONE_MARKER_SEEN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_control_reg_ff_disable_sc_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL72_CONTROL_REG_FF_DISABLE_SC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_data_align_fast_mode_en_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL72_DATA_ALIGN_FAST_MODE_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_extra_bad_markers_to_shift_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_extra_good_markers_to_lock_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_frame_marker_th_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_marker_valid_before_dme_check_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL72_MARKER_VALID_BEFORE_DME_CHECK_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_polynomial_sel_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_prbs_ber_en_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL72_PRBS_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_prbs_good_frames_th_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_prbs_ignored_last_dwords_attr == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_prbs_lock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_prbs_seed_force_en_attr == SERDES_SHIM_TFL_L3_CFG_RX_CL72_PRBS_SEED_FORCE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_prbs_seed_force_val_attr == 13'd1013
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_cl72_prbs_unlock_th_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_gb_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_rx_sync_pulse_attr == SERDES_SHIM_TFL_L3_CFG_RX_SYNC_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_scrambler_force_init_at_each_frame_attr == SERDES_SHIM_TFL_L3_CFG_SCRAMBLER_FORCE_INIT_AT_EACH_FRAME_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_send_data_attr == SERDES_SHIM_TFL_L3_CFG_SEND_DATA_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_sync_ctrl_stts_word_pulse_attr == SERDES_SHIM_TFL_L3_CFG_SYNC_CTRL_STTS_WORD_PULSE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_tfl_prbs13_en_attr == SERDES_SHIM_TFL_L3_CFG_TFL_PRBS13_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_tfl_pulse_sync_attr == SERDES_SHIM_TFL_L3_CFG_TFL_PULSE_SYNC_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_tfl_training_enable_rx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_tfl_training_enable_tx_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_tfl_l3_cfg_tx_gb_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_top_cfg_broadcast_feature_en_attr == SERDES_SHIM_TOP_CFG_BROADCAST_FEATURE_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_top_cfg_broadcast_type_attr == SERDES_SHIM_TOP_CFG_BROADCAST_TYPE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_top_cfg_fabric_wd_counter_max_attr == 7'd127
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_top_cfg_fec_ber_datawidth_sel_attr == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_top_cfg_fec_ber_en_attr == SERDES_SHIM_TOP_CFG_FEC_BER_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_top_cfg_fec_ber_mask8_attr == 8'd85
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_top_cfg_fec_ber_packet_sel_attr == SERDES_SHIM_TOP_CFG_FEC_BER_PACKET_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_top_cfg_fec_ber_poly_sel_attr == 3'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_top_cfg_fec_ber_rs_type_sel_attr == SERDES_SHIM_TOP_CFG_FEC_BER_RS_TYPE_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_top_cfg_fec_ber_statistic_en_attr == SERDES_SHIM_TOP_CFG_FEC_BER_STATISTIC_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_top_cfg_serdes_irq_enable_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_top_cfg_serdes_irq_mask_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_top_cfg_serdes_irq_reset_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_top_cfg_wdt_clr_attr == SERDES_SHIM_TOP_CFG_WDT_CLR_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_top_cfg_wdt_en_attr == SERDES_SHIM_TOP_CFG_WDT_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_top_cfg_wdt_pre_scale_attr == 32'd256
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_top_cfg_wdt_rst_after_irq_mode_attr == SERDES_SHIM_TOP_CFG_WDT_RST_AFTER_IRQ_MODE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_top_cfg_wdt_swrst_en_attr == SERDES_SHIM_TOP_CFG_WDT_SWRST_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_top_cfg_wdt_time_val_attr == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_apb_cfg_presetn_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_CFG_PRESETN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_apb_lgc_rstn_serdes_ux_lane0_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_LGC_RSTN_SERDES_UX_LANE0_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_apb_lgc_rstn_serdes_ux_lane1_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_LGC_RSTN_SERDES_UX_LANE1_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_apb_lgc_rstn_serdes_ux_lane2_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_LGC_RSTN_SERDES_UX_LANE2_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_apb_lgc_rstn_serdes_ux_lane3_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_LGC_RSTN_SERDES_UX_LANE3_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_apb_mem_rstn_serdes_ux_lane0_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_MEM_RSTN_SERDES_UX_LANE0_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_apb_mem_rstn_serdes_ux_lane1_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_MEM_RSTN_SERDES_UX_LANE1_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_apb_mem_rstn_serdes_ux_lane2_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_MEM_RSTN_SERDES_UX_LANE2_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_apb_mem_rstn_serdes_ux_lane3_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_MEM_RSTN_SERDES_UX_LANE3_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_clkrx_bot_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_CLKRX_BOT_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_clkrx_top_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_CLKRX_TOP_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_lane0_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_LANE0_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_lane1_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_LANE1_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_lane2_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_LANE2_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_lane3_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_LANE3_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_scmng_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_SCMNG_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_srds_ctrl_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_SRDS_CTRL_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_srds_ux_lane0_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_SRDS_UX_LANE0_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_srds_ux_lane1_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_SRDS_UX_LANE1_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_srds_ux_lane2_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_SRDS_UX_LANE2_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_apb_pclk_srds_ux_lane3_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PCLK_SRDS_UX_LANE3_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_clkrx_bot_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_CLKRX_BOT_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_clkrx_top_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_CLKRX_TOP_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_lane0_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_LANE0_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_lane1_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_LANE1_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_lane2_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_LANE2_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_lane3_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_LANE3_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_scmng_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_SCMNG_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_srds_ctrl_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_SRDS_CTRL_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_srds_ux_lane0_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_SRDS_UX_LANE0_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_srds_ux_lane1_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_SRDS_UX_LANE1_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_srds_ux_lane2_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_SRDS_UX_LANE2_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_apb_presetn_srds_ux_lane3_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_APB_PRESETN_SRDS_UX_LANE3_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_car_ux_lane_rst_src_sel_lane0_attr == SERDES_SHIM_WRAP_CAR_CFG_CAR_UX_LANE_RST_SRC_SEL_LANE0_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_car_ux_lane_rst_src_sel_lane1_attr == SERDES_SHIM_WRAP_CAR_CFG_CAR_UX_LANE_RST_SRC_SEL_LANE1_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_car_ux_lane_rst_src_sel_lane2_attr == SERDES_SHIM_WRAP_CAR_CFG_CAR_UX_LANE_RST_SRC_SEL_LANE2_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_car_ux_lane_rst_src_sel_lane3_attr == SERDES_SHIM_WRAP_CAR_CFG_CAR_UX_LANE_RST_SRC_SEL_LANE3_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_clkrx_ref_clk_sel_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_cpu_apb_clocks_ratio_attr == SERDES_SHIM_WRAP_CAR_CFG_CPU_APB_CLOCKS_RATIO_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_cpu_clk_sel_attr == SERDES_SHIM_WRAP_CAR_CFG_CPU_CLK_SEL_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_cpu_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_CPU_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_cpu_runstall_attr == SERDES_SHIM_WRAP_CAR_CFG_CPU_RUNSTALL_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_cpu_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_CPU_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_fast_clk_divn_en_attr == SERDES_SHIM_WRAP_CAR_CFG_FAST_CLK_DIVN_EN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_fast_clk_divn_val_attr == 8'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_fast_clk_lane_sel_attr == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_fb_cpu_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_FB_CPU_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_fb_cpu_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_FB_CPU_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_fb_rx_clken_attr == SERDES_SHIM_WRAP_CAR_CFG_FB_RX_CLKEN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_fb_rx_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_FB_RX_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_fec_ber_lane_select_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_hwrstn_clkrx_bot_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_CLKRX_BOT_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_hwrstn_clkrx_top_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_CLKRX_TOP_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_hwrstn_lane0_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_LANE0_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_hwrstn_lane1_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_LANE1_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_hwrstn_lane2_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_LANE2_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_hwrstn_lane3_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_LANE3_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_hwrstn_scmng_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_SCMNG_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_hwrstn_serdes_ctrl_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_SERDES_CTRL_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_hwrstn_serdes_ux_lane0_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_SERDES_UX_LANE0_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_hwrstn_serdes_ux_lane1_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_SERDES_UX_LANE1_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_hwrstn_serdes_ux_lane2_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_SERDES_UX_LANE2_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_hwrstn_serdes_ux_lane3_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_HWRSTN_SERDES_UX_LANE3_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_lane_car_apb_cfg_presetn_swrstn_lane0_attr == SERDES_SHIM_WRAP_CAR_CFG_LANE_CAR_APB_CFG_PRESETN_SWRSTN_LANE0_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_lane_car_apb_cfg_presetn_swrstn_lane1_attr == SERDES_SHIM_WRAP_CAR_CFG_LANE_CAR_APB_CFG_PRESETN_SWRSTN_LANE1_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_lane_car_apb_cfg_presetn_swrstn_lane2_attr == SERDES_SHIM_WRAP_CAR_CFG_LANE_CAR_APB_CFG_PRESETN_SWRSTN_LANE2_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_lane_car_apb_cfg_presetn_swrstn_lane3_attr == SERDES_SHIM_WRAP_CAR_CFG_LANE_CAR_APB_CFG_PRESETN_SWRSTN_LANE3_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.serdes_shim_wrap_car_cfg_wrap_car_apb_cfg_presetn_swrstn_attr == SERDES_SHIM_WRAP_CAR_CFG_WRAP_CAR_APB_CFG_PRESETN_SWRSTN_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.top_f_fastest_reconfig_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.top_refclk_reconfig_span == TOP_REFCLK_RECONFIG_SPAN_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.top_syspll_refclk_output_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_0_rx_synth_select == UX0_0_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_0_tx_synth_select == UX0_0_TX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_1_rx_synth_select == UX0_1_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_1_tx_synth_select == UX0_1_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_2_rx_synth_select == UX0_2_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_2_tx_synth_select == UX0_2_TX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_3_rx_synth_select == UX0_3_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_3_tx_synth_select == UX0_3_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_4_rx_synth_select == UX0_4_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_4_tx_synth_select == UX0_4_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_0_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_0_hscount == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_0_m_counter_physical == 9'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_0_meascount == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_0_mod_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_0_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_0_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_0_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_0_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_0_refclk_type_select == UX0_CDR_0_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_0_watchdogtmr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_1_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_1_hscount == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_1_m_counter_physical == 9'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_1_meascount == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_1_mod_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_1_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_1_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_1_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_1_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_1_refclk_type_select == UX0_CDR_1_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_1_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_2_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_2_hscount == 8'd180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_2_m_counter_physical == 9'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_2_meascount == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_2_mod_counter == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_2_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_2_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_2_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_2_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_2_refclk_type_select == UX0_CDR_2_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_2_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_3_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_3_hscount == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_3_m_counter_physical == 9'd66
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_3_meascount == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_3_mod_counter == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_3_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_3_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_3_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_3_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_3_refclk_type_select == UX0_CDR_3_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_3_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_4_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_4_hscount == 8'd206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_4_m_counter_physical == 9'd210
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_4_meascount == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_4_mod_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_4_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_4_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_4_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_4_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_4_refclk_type_select == UX0_CDR_4_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_4_watchdogtmr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_bw_sel == UX0_CDR_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_f_mod_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_f_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_hscount_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_is_cascaded == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_is_fractional == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_l_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_l_counter_physical == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_m_counter == 9'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_meascount_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_mod_counter_scratch == 40'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_ppm_driftcount == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_ppm_driftmax == 16'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_ppm_driftmax_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_ppm_driftmax_scratch_denominator == 47'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_ppm_driftmax_scratch_numerator == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_ppm_tolerance == 16'd7600
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_refclk_mux_select == UX0_CDR_REFCLK_MUX_SELECT_REGIONAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_refclk_select == UX0_CDR_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_squelch_sample_count == 10'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_squelch_sample_scratch == 40'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_watchdogtmr_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cmn_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cmn_rx_cdr_refclk_mux_select == UX0_CMN_RX_CDR_REFCLK_MUX_SELECT_REGIONAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cmnrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cmnrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cmnrpu_evdn_delay_lut_entry3 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cmnrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cmnrpu_evup_delay_lut_entry2 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cmnrpu_evup_delay_lut_entry3 == 50'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cmnrpu_evup_delay_lut_entry4 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cmnrpu_evup_delay_lut_entry5 == 50'd62
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cmnrpu_evup_delay_lut_entry6 == 50'd390
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_cmnrpu_evup_delay_lut_entry7 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_core_pll == UX0_CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_core_pll_bw_sel == UX0_CORE_PLL_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_core_pll_refclk_select == UX0_CORE_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_dpma_f_out_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_dpma_n_counter == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_dpma_n_counter_physical == UX0_DPMA_N_COUNTER_PHYSICAL_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_dpma_n_counter_scratch == 40'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_dpma_refclk_source == UX0_DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_dts_ssdiv_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_duplex_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_enable_med_lc_0_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_enable_med_lc_1_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_enable_med_lc_2_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_enable_med_lc_3_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_enable_med_lc_4_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_enable_port_control_of_cdr_ltr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_enable_slow_lc_0_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_enable_slow_lc_1_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_enable_slow_lc_2_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_enable_slow_lc_3_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_enable_slow_lc_4_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_ethernet_source == UX0_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_expose_pcie_gen1_gen6_critical_signals == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_f_cascade_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_feed_forward_gain_scratch == 47'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_feed_forward_temp_one == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_feed_forward_temp_two == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_flux_mode == UX0_FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_kvcc_settle_maxcnt_scratch == 40'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_lane_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_loopback_mode == UX0_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_master_sup_mode == UX0_MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_oversampling_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_primary_use == UX0_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_ref_clk_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_refclk_in_1us_scratch == 40'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rx_adapt_mode == UX0_RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rx_bond_size == UX0_RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rx_cal_dutymeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rx_master_bond_chnl == UX0_RX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rx_o_usr_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rx_o_usr_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rx_onchip_termination == UX0_RX_ONCHIP_TERMINATION_R_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rx_over_sample == UX0_RX_OVER_SAMPLE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rx_protocol == UX0_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rx_term_mode_select == UX0_RX_TERM_MODE_SELECT_GROUNDED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rx_tuning_hint == UX0_RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rx_which_lane_to_copy == UX0_RX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rx_width == UX0_RX_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxeq_ctle_bias_adj == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxeq_ctle_biasboost == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxeq_ctle_lf_gain == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxeq_ctle_midband_zero == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxeq_ctle_stage_1_dcgain == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxeq_ctle_stage_1_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxeq_ctle_stage_2_cap == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxeq_ctle_stage_2_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxeq_ctle_stage_2_reszero == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxeq_ctle_stage_3_dcgain == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxeq_ctle_stage_3_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxeq_dfe_data_tap_10 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxeq_dfe_data_tap_11 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxeq_dfe_data_tap_12 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxeq_dfe_data_tap_13 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxeq_dfe_data_tap_14 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxeq_dfe_data_tap_15 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxeq_dfe_data_tap_16 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxeq_dfe_data_tap_2 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxeq_dfe_data_tap_3 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxeq_dfe_data_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxeq_dfe_data_tap_5 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxeq_dfe_data_tap_6 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxeq_dfe_data_tap_7 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxeq_dfe_data_tap_8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxeq_dfe_data_tap_9 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxeq_dfe_edge_tap_2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxeq_dfe_edge_tap_3 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxeq_dfe_edge_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxeq_iq_clk == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxeq_targ_0_hi == 9'd149
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxeq_targ_0_lo == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxeq_vga_gain == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxratewidth_pd_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxrpu_evup_delay_lut_entry2 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxrpu_evup_delay_lut_entry4 == 50'd78
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxrpu_evup_delay_lut_entry5 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxrpu_evup_delay_lut_entry6 == 50'd1406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_rxrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_select_lc_0_tx_path == UX0_SELECT_LC_0_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_select_lc_1_tx_path == UX0_SELECT_LC_1_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_select_lc_2_tx_path == UX0_SELECT_LC_2_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_select_lc_3_tx_path == UX0_SELECT_LC_3_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_select_lc_4_tx_path == UX0_SELECT_LC_4_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_sup_mode == UX0_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_afc_range == UX0_SYNTH_LC_0_AFC_RANGE_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_afc_refclk_count == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_dtr_prop_coeff == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_f_max_vco_hz == 40'd10500000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_f_min_vco_hz == 40'd8000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_fast_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_fast_tx_postdiv_counter == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_feed_forward_gain == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_fine_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_fine_int_coeff_tmp == 4'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_fine_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_fine_prop_coeff_tmp == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_kvcc_settle_maxcnt == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_m_counter == 9'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_med_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_med_tx_postdiv_counter == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_refclk_in_1us == 8'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_slow_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_slow_tx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_tdc_fine_res_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_tdc_target_count == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_0_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_afc_range == UX0_SYNTH_LC_1_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_feed_forward_gain == 8'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_m_counter == 9'd45
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_1_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_afc_range == UX0_SYNTH_LC_2_AFC_RANGE_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_dtr_int_coeff == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_feed_forward_gain == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_m_counter == 9'd27
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_2_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_afc_range == UX0_SYNTH_LC_3_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_feed_forward_gain == 8'd23
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_m_counter == 9'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_3_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_afc_range == UX0_SYNTH_LC_4_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_afc_refclk_count == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_dtr_int_coeff == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_feed_forward_gain == 8'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_fine_int_coeff == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_kvcc_settle_maxcnt == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_m_counter == 9'd216
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_med_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_refclk_in_1us == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_tdc_refclk_count == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_tdc_target_count == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_4_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_fast_bw_sel == UX0_SYNTH_LC_FAST_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_fast_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_fast_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_fast_primary_use == UX0_SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_fast_refclk_mux_select == UX0_SYNTH_LC_FAST_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_fast_refclk_type_select == UX0_SYNTH_LC_FAST_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_fast_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_fb_div_emb_mult_counter == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_l_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_l_counter_physical == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_med_bw_sel == UX0_SYNTH_LC_MED_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_med_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_med_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_med_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_med_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_med_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_med_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_med_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_med_primary_use == UX0_SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_med_refclk_mux_select == UX0_SYNTH_LC_MED_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_med_refclk_type_select == UX0_SYNTH_LC_MED_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_med_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_slow_bw_sel == UX0_SYNTH_LC_SLOW_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_slow_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_slow_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_slow_primary_use == UX0_SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_slow_refclk_mux_select == UX0_SYNTH_LC_SLOW_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_slow_refclk_type_select == UX0_SYNTH_LC_SLOW_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synth_lc_slow_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlc_0_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlc_0_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlc_0_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlc_0_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlc_1_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlc_1_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlc_1_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlc_1_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlc_2_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlc_2_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlc_2_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlc_2_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlc_3_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlc_3_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlc_3_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlc_3_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlc_4_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlc_4_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlc_4_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlc_4_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlc_dcdmeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlcfastratewidth_pd_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlcfastrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlcfastrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlcfastrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlcfastrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlcfastrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlcfastrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlcfastrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlcfastrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlcfastrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlcfastrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlcfastrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlcmedrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlcmedrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlcmedrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlcmedrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlcmedrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlcmedrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlcmedrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlcmedrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlcmedrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlcmedrpu_evup_delay_lut_entry7 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlcslowrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlcslowrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlcslowrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlcslowrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlcslowrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlcslowrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlcslowrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlcslowrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlcslowrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_synthlcslowrpu_evup_delay_lut_entry7 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tdc_refclk_count_divisor == 40'd850000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tdc_refclk_count_scratch == 40'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tdc_target_count_scratch == 40'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tx_bond_size == UX0_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tx_cal_dutymeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tx_i_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tx_i_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tx_i_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tx_master_bond_chnl == UX0_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tx_o_usr_clk_1_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tx_o_usr_clk_1_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tx_o_usr_clk_2_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tx_over_sample == UX0_TX_OVER_SAMPLE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tx_pll == UX0_TX_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tx_pll_bw_sel == UX0_TX_PLL_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tx_pll_is_downstream_pll == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tx_pll_refclk_mux_select == UX0_TX_PLL_REFCLK_MUX_SELECT_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tx_pll_refclk_select == UX0_TX_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tx_protocol == UX0_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tx_tuning_hint == UX0_TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tx_user_clk1_mux == UX0_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tx_user_clk2_mux == UX0_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tx_user_clk_slow_med_mux == UX0_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tx_which_lane_to_copy == UX0_TX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_tx_width == UX0_TX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_txeq_main_tap == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_txratewidth_rst_b0_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_txrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_txrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_txrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_txrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_txrpu_evup_delay_lut_entry2 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_txrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_txrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_txrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_txrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_txrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_txrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_txrx_channel_operation == UX0_TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_txrx_line_encoding_type == UX0_TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_txrx_xcvr_speed_bucket == UX0_TXRX_XCVR_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux0_vreg_loopen_maxcnt_scratch == 40'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_0_rx_synth_select == UX1_0_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_0_tx_synth_select == UX1_0_TX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_1_rx_synth_select == UX1_1_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_1_tx_synth_select == UX1_1_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_2_rx_synth_select == UX1_2_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_2_tx_synth_select == UX1_2_TX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_3_rx_synth_select == UX1_3_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_3_tx_synth_select == UX1_3_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_4_rx_synth_select == UX1_4_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_4_tx_synth_select == UX1_4_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_0_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_0_hscount == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_0_m_counter_physical == 9'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_0_meascount == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_0_mod_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_0_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_0_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_0_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_0_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_0_refclk_type_select == UX1_CDR_0_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_0_watchdogtmr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_1_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_1_hscount == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_1_m_counter_physical == 9'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_1_meascount == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_1_mod_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_1_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_1_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_1_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_1_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_1_refclk_type_select == UX1_CDR_1_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_1_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_2_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_2_hscount == 8'd180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_2_m_counter_physical == 9'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_2_meascount == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_2_mod_counter == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_2_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_2_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_2_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_2_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_2_refclk_type_select == UX1_CDR_2_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_2_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_3_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_3_hscount == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_3_m_counter_physical == 9'd66
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_3_meascount == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_3_mod_counter == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_3_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_3_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_3_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_3_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_3_refclk_type_select == UX1_CDR_3_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_3_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_4_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_4_hscount == 8'd206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_4_m_counter_physical == 9'd210
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_4_meascount == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_4_mod_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_4_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_4_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_4_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_4_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_4_refclk_type_select == UX1_CDR_4_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_4_watchdogtmr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_bw_sel == UX1_CDR_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_f_mod_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_f_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_hscount_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_is_cascaded == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_is_fractional == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_l_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_l_counter_physical == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_m_counter == 9'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_meascount_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_mod_counter_scratch == 40'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_ppm_driftcount == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_ppm_driftmax == 16'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_ppm_driftmax_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_ppm_driftmax_scratch_denominator == 47'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_ppm_driftmax_scratch_numerator == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_ppm_tolerance == 16'd7600
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_refclk_mux_select == UX1_CDR_REFCLK_MUX_SELECT_REGIONAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_refclk_select == UX1_CDR_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_squelch_sample_count == 10'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_squelch_sample_scratch == 40'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cdr_watchdogtmr_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cmn_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cmn_rx_cdr_refclk_mux_select == UX1_CMN_RX_CDR_REFCLK_MUX_SELECT_REGIONAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cmnrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cmnrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cmnrpu_evdn_delay_lut_entry3 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cmnrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cmnrpu_evup_delay_lut_entry2 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cmnrpu_evup_delay_lut_entry3 == 50'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cmnrpu_evup_delay_lut_entry4 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cmnrpu_evup_delay_lut_entry5 == 50'd62
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cmnrpu_evup_delay_lut_entry6 == 50'd390
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_cmnrpu_evup_delay_lut_entry7 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_core_pll == UX1_CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_core_pll_bw_sel == UX1_CORE_PLL_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_core_pll_refclk_select == UX1_CORE_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_dpma_f_out_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_dpma_n_counter == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_dpma_n_counter_physical == UX1_DPMA_N_COUNTER_PHYSICAL_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_dpma_n_counter_scratch == 40'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_dpma_refclk_source == UX1_DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_dts_ssdiv_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_duplex_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_enable_med_lc_0_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_enable_med_lc_1_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_enable_med_lc_2_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_enable_med_lc_3_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_enable_med_lc_4_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_enable_port_control_of_cdr_ltr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_enable_slow_lc_0_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_enable_slow_lc_1_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_enable_slow_lc_2_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_enable_slow_lc_3_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_enable_slow_lc_4_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_ethernet_source == UX1_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_expose_pcie_gen1_gen6_critical_signals == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_f_cascade_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_feed_forward_gain_scratch == 47'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_feed_forward_temp_one == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_feed_forward_temp_two == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_flux_mode == UX1_FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_kvcc_settle_maxcnt_scratch == 40'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_lane_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_loopback_mode == UX1_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_master_sup_mode == UX1_MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_oversampling_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_primary_use == UX1_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_ref_clk_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_refclk_in_1us_scratch == 40'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rx_adapt_mode == UX1_RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rx_bond_size == UX1_RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rx_cal_dutymeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rx_master_bond_chnl == UX1_RX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rx_o_usr_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rx_o_usr_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rx_onchip_termination == UX1_RX_ONCHIP_TERMINATION_R_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rx_over_sample == UX1_RX_OVER_SAMPLE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rx_protocol == UX1_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rx_term_mode_select == UX1_RX_TERM_MODE_SELECT_GROUNDED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rx_tuning_hint == UX1_RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rx_which_lane_to_copy == UX1_RX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rx_width == UX1_RX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxeq_ctle_bias_adj == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxeq_ctle_biasboost == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxeq_ctle_lf_gain == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxeq_ctle_midband_zero == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxeq_ctle_stage_1_dcgain == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxeq_ctle_stage_1_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxeq_ctle_stage_2_cap == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxeq_ctle_stage_2_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxeq_ctle_stage_2_reszero == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxeq_ctle_stage_3_dcgain == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxeq_ctle_stage_3_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxeq_dfe_data_tap_10 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxeq_dfe_data_tap_11 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxeq_dfe_data_tap_12 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxeq_dfe_data_tap_13 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxeq_dfe_data_tap_14 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxeq_dfe_data_tap_15 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxeq_dfe_data_tap_16 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxeq_dfe_data_tap_2 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxeq_dfe_data_tap_3 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxeq_dfe_data_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxeq_dfe_data_tap_5 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxeq_dfe_data_tap_6 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxeq_dfe_data_tap_7 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxeq_dfe_data_tap_8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxeq_dfe_data_tap_9 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxeq_dfe_edge_tap_2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxeq_dfe_edge_tap_3 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxeq_dfe_edge_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxeq_iq_clk == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxeq_targ_0_hi == 9'd149
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxeq_targ_0_lo == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxeq_vga_gain == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxratewidth_pd_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxrpu_evup_delay_lut_entry2 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxrpu_evup_delay_lut_entry4 == 50'd78
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxrpu_evup_delay_lut_entry5 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxrpu_evup_delay_lut_entry6 == 50'd1406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_rxrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_select_lc_0_tx_path == UX1_SELECT_LC_0_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_select_lc_1_tx_path == UX1_SELECT_LC_1_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_select_lc_2_tx_path == UX1_SELECT_LC_2_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_select_lc_3_tx_path == UX1_SELECT_LC_3_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_select_lc_4_tx_path == UX1_SELECT_LC_4_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_sup_mode == UX1_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_afc_range == UX1_SYNTH_LC_0_AFC_RANGE_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_afc_refclk_count == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_dtr_prop_coeff == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_f_max_vco_hz == 40'd10500000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_f_min_vco_hz == 40'd8000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_fast_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_fast_tx_postdiv_counter == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_feed_forward_gain == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_fine_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_fine_int_coeff_tmp == 4'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_fine_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_fine_prop_coeff_tmp == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_kvcc_settle_maxcnt == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_m_counter == 9'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_med_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_med_tx_postdiv_counter == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_refclk_in_1us == 8'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_slow_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_slow_tx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_tdc_fine_res_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_tdc_target_count == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_0_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_afc_range == UX1_SYNTH_LC_1_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_feed_forward_gain == 8'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_m_counter == 9'd45
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_1_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_afc_range == UX1_SYNTH_LC_2_AFC_RANGE_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_dtr_int_coeff == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_feed_forward_gain == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_m_counter == 9'd27
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_2_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_afc_range == UX1_SYNTH_LC_3_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_feed_forward_gain == 8'd23
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_m_counter == 9'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_3_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_afc_range == UX1_SYNTH_LC_4_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_afc_refclk_count == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_dtr_int_coeff == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_feed_forward_gain == 8'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_fine_int_coeff == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_kvcc_settle_maxcnt == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_m_counter == 9'd216
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_med_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_refclk_in_1us == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_tdc_refclk_count == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_tdc_target_count == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_4_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_fast_bw_sel == UX1_SYNTH_LC_FAST_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_fast_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_fast_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_fast_primary_use == UX1_SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_fast_refclk_mux_select == UX1_SYNTH_LC_FAST_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_fast_refclk_type_select == UX1_SYNTH_LC_FAST_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_fast_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_fb_div_emb_mult_counter == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_l_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_l_counter_physical == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_med_bw_sel == UX1_SYNTH_LC_MED_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_med_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_med_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_med_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_med_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_med_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_med_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_med_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_med_primary_use == UX1_SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_med_refclk_mux_select == UX1_SYNTH_LC_MED_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_med_refclk_type_select == UX1_SYNTH_LC_MED_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_med_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_slow_bw_sel == UX1_SYNTH_LC_SLOW_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_slow_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_slow_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_slow_primary_use == UX1_SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_slow_refclk_mux_select == UX1_SYNTH_LC_SLOW_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_slow_refclk_type_select == UX1_SYNTH_LC_SLOW_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synth_lc_slow_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlc_0_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlc_0_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlc_0_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlc_0_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlc_1_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlc_1_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlc_1_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlc_1_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlc_2_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlc_2_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlc_2_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlc_2_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlc_3_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlc_3_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlc_3_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlc_3_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlc_4_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlc_4_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlc_4_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlc_4_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlc_dcdmeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlcfastratewidth_pd_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlcfastrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlcfastrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlcfastrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlcfastrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlcfastrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlcfastrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlcfastrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlcfastrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlcfastrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlcfastrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlcfastrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlcmedrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlcmedrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlcmedrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlcmedrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlcmedrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlcmedrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlcmedrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlcmedrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlcmedrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlcmedrpu_evup_delay_lut_entry7 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlcslowrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlcslowrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlcslowrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlcslowrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlcslowrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlcslowrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlcslowrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlcslowrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlcslowrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_synthlcslowrpu_evup_delay_lut_entry7 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tdc_refclk_count_divisor == 40'd850000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tdc_refclk_count_scratch == 40'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tdc_target_count_scratch == 40'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tx_bond_size == UX1_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tx_cal_dutymeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tx_i_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tx_i_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tx_i_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tx_master_bond_chnl == UX1_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tx_o_usr_clk_1_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tx_o_usr_clk_1_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tx_o_usr_clk_2_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tx_over_sample == UX1_TX_OVER_SAMPLE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tx_pll == UX1_TX_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tx_pll_bw_sel == UX1_TX_PLL_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tx_pll_is_downstream_pll == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tx_pll_refclk_mux_select == UX1_TX_PLL_REFCLK_MUX_SELECT_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tx_pll_refclk_select == UX1_TX_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tx_protocol == UX1_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tx_tuning_hint == UX1_TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tx_user_clk1_mux == UX1_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tx_user_clk2_mux == UX1_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tx_user_clk_slow_med_mux == UX1_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tx_which_lane_to_copy == UX1_TX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_tx_width == UX1_TX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_txeq_main_tap == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_txratewidth_rst_b0_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_txrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_txrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_txrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_txrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_txrpu_evup_delay_lut_entry2 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_txrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_txrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_txrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_txrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_txrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_txrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_txrx_channel_operation == UX1_TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_txrx_line_encoding_type == UX1_TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_txrx_xcvr_speed_bucket == UX1_TXRX_XCVR_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux1_vreg_loopen_maxcnt_scratch == 40'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_0_rx_synth_select == UX2_0_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_0_tx_synth_select == UX2_0_TX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_1_rx_synth_select == UX2_1_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_1_tx_synth_select == UX2_1_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_2_rx_synth_select == UX2_2_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_2_tx_synth_select == UX2_2_TX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_3_rx_synth_select == UX2_3_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_3_tx_synth_select == UX2_3_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_4_rx_synth_select == UX2_4_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_4_tx_synth_select == UX2_4_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_0_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_0_hscount == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_0_m_counter_physical == 9'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_0_meascount == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_0_mod_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_0_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_0_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_0_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_0_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_0_refclk_type_select == UX2_CDR_0_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_0_watchdogtmr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_1_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_1_hscount == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_1_m_counter_physical == 9'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_1_meascount == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_1_mod_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_1_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_1_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_1_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_1_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_1_refclk_type_select == UX2_CDR_1_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_1_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_2_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_2_hscount == 8'd180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_2_m_counter_physical == 9'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_2_meascount == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_2_mod_counter == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_2_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_2_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_2_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_2_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_2_refclk_type_select == UX2_CDR_2_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_2_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_3_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_3_hscount == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_3_m_counter_physical == 9'd66
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_3_meascount == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_3_mod_counter == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_3_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_3_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_3_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_3_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_3_refclk_type_select == UX2_CDR_3_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_3_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_4_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_4_hscount == 8'd206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_4_m_counter_physical == 9'd210
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_4_meascount == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_4_mod_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_4_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_4_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_4_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_4_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_4_refclk_type_select == UX2_CDR_4_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_4_watchdogtmr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_bw_sel == UX2_CDR_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_f_mod_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_f_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_hscount_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_is_cascaded == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_is_fractional == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_l_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_l_counter_physical == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_m_counter == 9'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_meascount_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_mod_counter_scratch == 40'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_ppm_driftcount == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_ppm_driftmax == 16'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_ppm_driftmax_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_ppm_driftmax_scratch_denominator == 47'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_ppm_driftmax_scratch_numerator == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_ppm_tolerance == 16'd7600
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_refclk_mux_select == UX2_CDR_REFCLK_MUX_SELECT_REGIONAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_refclk_select == UX2_CDR_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_squelch_sample_count == 10'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_squelch_sample_scratch == 40'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cdr_watchdogtmr_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cmn_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cmn_rx_cdr_refclk_mux_select == UX2_CMN_RX_CDR_REFCLK_MUX_SELECT_REGIONAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cmnrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cmnrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cmnrpu_evdn_delay_lut_entry3 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cmnrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cmnrpu_evup_delay_lut_entry2 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cmnrpu_evup_delay_lut_entry3 == 50'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cmnrpu_evup_delay_lut_entry4 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cmnrpu_evup_delay_lut_entry5 == 50'd62
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cmnrpu_evup_delay_lut_entry6 == 50'd390
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_cmnrpu_evup_delay_lut_entry7 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_core_pll == UX2_CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_core_pll_bw_sel == UX2_CORE_PLL_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_core_pll_refclk_select == UX2_CORE_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_dpma_f_out_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_dpma_n_counter == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_dpma_n_counter_physical == UX2_DPMA_N_COUNTER_PHYSICAL_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_dpma_n_counter_scratch == 40'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_dpma_refclk_source == UX2_DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_dts_ssdiv_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_duplex_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_enable_med_lc_0_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_enable_med_lc_1_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_enable_med_lc_2_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_enable_med_lc_3_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_enable_med_lc_4_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_enable_port_control_of_cdr_ltr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_enable_slow_lc_0_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_enable_slow_lc_1_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_enable_slow_lc_2_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_enable_slow_lc_3_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_enable_slow_lc_4_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_ethernet_source == UX2_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_expose_pcie_gen1_gen6_critical_signals == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_f_cascade_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_feed_forward_gain_scratch == 47'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_feed_forward_temp_one == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_feed_forward_temp_two == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_flux_mode == UX2_FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_kvcc_settle_maxcnt_scratch == 40'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_lane_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_loopback_mode == UX2_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_master_sup_mode == UX2_MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_oversampling_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_primary_use == UX2_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_ref_clk_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_refclk_in_1us_scratch == 40'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rx_adapt_mode == UX2_RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rx_bond_size == UX2_RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rx_cal_dutymeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rx_master_bond_chnl == UX2_RX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rx_o_usr_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rx_o_usr_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rx_onchip_termination == UX2_RX_ONCHIP_TERMINATION_R_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rx_over_sample == UX2_RX_OVER_SAMPLE_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rx_protocol == UX2_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rx_term_mode_select == UX2_RX_TERM_MODE_SELECT_GROUNDED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rx_tuning_hint == UX2_RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rx_which_lane_to_copy == UX2_RX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rx_width == UX2_RX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxeq_ctle_bias_adj == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxeq_ctle_biasboost == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxeq_ctle_lf_gain == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxeq_ctle_midband_zero == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxeq_ctle_stage_1_dcgain == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxeq_ctle_stage_1_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxeq_ctle_stage_2_cap == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxeq_ctle_stage_2_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxeq_ctle_stage_2_reszero == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxeq_ctle_stage_3_dcgain == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxeq_ctle_stage_3_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxeq_dfe_data_tap_10 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxeq_dfe_data_tap_11 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxeq_dfe_data_tap_12 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxeq_dfe_data_tap_13 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxeq_dfe_data_tap_14 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxeq_dfe_data_tap_15 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxeq_dfe_data_tap_16 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxeq_dfe_data_tap_2 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxeq_dfe_data_tap_3 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxeq_dfe_data_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxeq_dfe_data_tap_5 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxeq_dfe_data_tap_6 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxeq_dfe_data_tap_7 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxeq_dfe_data_tap_8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxeq_dfe_data_tap_9 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxeq_dfe_edge_tap_2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxeq_dfe_edge_tap_3 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxeq_dfe_edge_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxeq_iq_clk == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxeq_targ_0_hi == 9'd149
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxeq_targ_0_lo == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxeq_vga_gain == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxratewidth_pd_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxrpu_evup_delay_lut_entry2 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxrpu_evup_delay_lut_entry4 == 50'd78
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxrpu_evup_delay_lut_entry5 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxrpu_evup_delay_lut_entry6 == 50'd1406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_rxrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_select_lc_0_tx_path == UX2_SELECT_LC_0_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_select_lc_1_tx_path == UX2_SELECT_LC_1_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_select_lc_2_tx_path == UX2_SELECT_LC_2_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_select_lc_3_tx_path == UX2_SELECT_LC_3_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_select_lc_4_tx_path == UX2_SELECT_LC_4_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_sup_mode == UX2_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_afc_range == UX2_SYNTH_LC_0_AFC_RANGE_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_afc_refclk_count == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_dtr_prop_coeff == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_f_max_vco_hz == 40'd10500000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_f_min_vco_hz == 40'd8000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_fast_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_fast_tx_postdiv_counter == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_feed_forward_gain == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_fine_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_fine_int_coeff_tmp == 4'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_fine_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_fine_prop_coeff_tmp == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_kvcc_settle_maxcnt == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_m_counter == 9'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_med_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_med_tx_postdiv_counter == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_refclk_in_1us == 8'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_slow_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_slow_tx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_tdc_fine_res_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_tdc_target_count == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_0_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_afc_range == UX2_SYNTH_LC_1_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_feed_forward_gain == 8'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_m_counter == 9'd45
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_1_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_afc_range == UX2_SYNTH_LC_2_AFC_RANGE_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_dtr_int_coeff == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_feed_forward_gain == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_m_counter == 9'd27
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_2_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_afc_range == UX2_SYNTH_LC_3_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_feed_forward_gain == 8'd23
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_m_counter == 9'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_3_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_afc_range == UX2_SYNTH_LC_4_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_afc_refclk_count == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_dtr_int_coeff == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_feed_forward_gain == 8'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_fine_int_coeff == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_kvcc_settle_maxcnt == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_m_counter == 9'd216
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_med_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_refclk_in_1us == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_tdc_refclk_count == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_tdc_target_count == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_4_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_fast_bw_sel == UX2_SYNTH_LC_FAST_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_fast_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_fast_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_fast_primary_use == UX2_SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_fast_refclk_mux_select == UX2_SYNTH_LC_FAST_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_fast_refclk_type_select == UX2_SYNTH_LC_FAST_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_fast_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_fb_div_emb_mult_counter == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_l_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_l_counter_physical == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_med_bw_sel == UX2_SYNTH_LC_MED_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_med_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_med_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_med_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_med_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_med_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_med_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_med_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_med_primary_use == UX2_SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_med_refclk_mux_select == UX2_SYNTH_LC_MED_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_med_refclk_type_select == UX2_SYNTH_LC_MED_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_med_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_slow_bw_sel == UX2_SYNTH_LC_SLOW_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_slow_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_slow_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_slow_primary_use == UX2_SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_slow_refclk_mux_select == UX2_SYNTH_LC_SLOW_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_slow_refclk_type_select == UX2_SYNTH_LC_SLOW_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synth_lc_slow_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlc_0_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlc_0_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlc_0_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlc_0_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlc_1_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlc_1_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlc_1_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlc_1_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlc_2_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlc_2_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlc_2_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlc_2_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlc_3_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlc_3_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlc_3_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlc_3_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlc_4_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlc_4_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlc_4_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlc_4_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlc_dcdmeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlcfastratewidth_pd_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlcfastrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlcfastrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlcfastrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlcfastrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlcfastrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlcfastrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlcfastrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlcfastrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlcfastrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlcfastrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlcfastrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlcmedrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlcmedrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlcmedrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlcmedrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlcmedrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlcmedrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlcmedrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlcmedrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlcmedrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlcmedrpu_evup_delay_lut_entry7 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlcslowrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlcslowrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlcslowrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlcslowrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlcslowrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlcslowrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlcslowrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlcslowrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlcslowrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_synthlcslowrpu_evup_delay_lut_entry7 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tdc_refclk_count_divisor == 40'd850000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tdc_refclk_count_scratch == 40'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tdc_target_count_scratch == 40'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tx_bond_size == UX2_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tx_cal_dutymeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tx_i_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tx_i_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tx_i_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tx_master_bond_chnl == UX2_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tx_o_usr_clk_1_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tx_o_usr_clk_1_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tx_o_usr_clk_2_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tx_over_sample == UX2_TX_OVER_SAMPLE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tx_pll == UX2_TX_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tx_pll_bw_sel == UX2_TX_PLL_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tx_pll_is_downstream_pll == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tx_pll_refclk_mux_select == UX2_TX_PLL_REFCLK_MUX_SELECT_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tx_pll_refclk_select == UX2_TX_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tx_protocol == UX2_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tx_tuning_hint == UX2_TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tx_user_clk1_mux == UX2_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tx_user_clk2_mux == UX2_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tx_user_clk_slow_med_mux == UX2_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tx_which_lane_to_copy == UX2_TX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_tx_width == UX2_TX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_txeq_main_tap == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_txratewidth_rst_b0_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_txrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_txrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_txrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_txrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_txrpu_evup_delay_lut_entry2 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_txrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_txrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_txrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_txrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_txrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_txrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_txrx_channel_operation == UX2_TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_txrx_line_encoding_type == UX2_TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_txrx_xcvr_speed_bucket == UX2_TXRX_XCVR_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux2_vreg_loopen_maxcnt_scratch == 40'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_0_rx_synth_select == UX3_0_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_0_tx_synth_select == UX3_0_TX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_1_rx_synth_select == UX3_1_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_1_tx_synth_select == UX3_1_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_2_rx_synth_select == UX3_2_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_2_tx_synth_select == UX3_2_TX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_3_rx_synth_select == UX3_3_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_3_tx_synth_select == UX3_3_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_4_rx_synth_select == UX3_4_RX_SYNTH_SELECT_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_4_tx_synth_select == UX3_4_TX_SYNTH_SELECT_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_0_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_0_hscount == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_0_m_counter_physical == 9'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_0_meascount == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_0_mod_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_0_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_0_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_0_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_0_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_0_refclk_type_select == UX3_CDR_0_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_0_watchdogtmr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_1_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_1_hscount == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_1_m_counter_physical == 9'd84
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_1_meascount == 8'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_1_mod_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_1_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_1_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_1_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_1_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_1_refclk_type_select == UX3_CDR_1_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_1_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_2_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_2_hscount == 8'd180
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_2_m_counter_physical == 9'd48
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_2_meascount == 8'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_2_mod_counter == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_2_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_2_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_2_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_2_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_2_refclk_type_select == UX3_CDR_2_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_2_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_3_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_3_hscount == 8'd171
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_3_m_counter_physical == 9'd66
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_3_meascount == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_3_mod_counter == 6'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_3_n_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_3_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_3_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_3_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_3_refclk_type_select == UX3_CDR_3_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_3_watchdogtmr == 16'd3000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_4_fastref_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_4_hscount == 8'd206
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_4_m_counter_physical == 9'd210
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_4_meascount == 8'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_4_mod_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_4_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_4_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_4_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_4_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_4_refclk_type_select == UX3_CDR_4_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_4_watchdogtmr == 16'd1200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_bw_sel == UX3_CDR_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_f_mod_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_f_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_hscount_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_is_cascaded == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_is_fractional == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_l_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_l_counter_physical == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_m_counter == 9'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_meascount_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_mod_counter_scratch == 40'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_ppm_driftcount == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_ppm_driftmax == 16'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_ppm_driftmax_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_ppm_driftmax_scratch_denominator == 47'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_ppm_driftmax_scratch_numerator == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_ppm_tolerance == 16'd7600
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_refclk_mux_select == UX3_CDR_REFCLK_MUX_SELECT_REGIONAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_refclk_select == UX3_CDR_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_squelch_sample_count == 10'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_squelch_sample_scratch == 40'd225
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cdr_watchdogtmr_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cmn_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cmn_rx_cdr_refclk_mux_select == UX3_CMN_RX_CDR_REFCLK_MUX_SELECT_REGIONAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cmnrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cmnrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cmnrpu_evdn_delay_lut_entry3 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cmnrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cmnrpu_evup_delay_lut_entry2 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cmnrpu_evup_delay_lut_entry3 == 50'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cmnrpu_evup_delay_lut_entry4 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cmnrpu_evup_delay_lut_entry5 == 50'd62
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cmnrpu_evup_delay_lut_entry6 == 50'd390
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_cmnrpu_evup_delay_lut_entry7 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_core_pll == UX3_CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_core_pll_bw_sel == UX3_CORE_PLL_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_core_pll_refclk_select == UX3_CORE_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_dpma_f_out_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_dpma_n_counter == 3'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_dpma_n_counter_physical == UX3_DPMA_N_COUNTER_PHYSICAL_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_dpma_n_counter_scratch == 40'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_dpma_refclk_source == UX3_DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_dts_ssdiv_scratch == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_duplex_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_enable_med_lc_0_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_enable_med_lc_1_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_enable_med_lc_2_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_enable_med_lc_3_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_enable_med_lc_4_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_enable_port_control_of_cdr_ltr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_enable_slow_lc_0_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_enable_slow_lc_1_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_enable_slow_lc_2_path == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_enable_slow_lc_3_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_enable_slow_lc_4_path == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_ethernet_source == UX3_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_expose_pcie_gen1_gen6_critical_signals == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_f_cascade_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_feed_forward_gain_scratch == 47'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_feed_forward_temp_one == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_feed_forward_temp_two == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_flux_mode == UX3_FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_kvcc_settle_maxcnt_scratch == 40'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_lane_ctrl_i_clk_p_hz == 36'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_loopback_mode == UX3_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_master_sup_mode == UX3_MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_oversampling_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_primary_use == UX3_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_ref_clk_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_refclk_in_1us_scratch == 40'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rx_adapt_mode == UX3_RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rx_bond_size == UX3_RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rx_cal_dutymeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rx_master_bond_chnl == UX3_RX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rx_o_usr_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rx_o_usr_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rx_onchip_termination == UX3_RX_ONCHIP_TERMINATION_R_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rx_over_sample == UX3_RX_OVER_SAMPLE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rx_protocol == UX3_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rx_term_mode_select == UX3_RX_TERM_MODE_SELECT_GROUNDED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rx_tuning_hint == UX3_RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rx_which_lane_to_copy == UX3_RX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rx_width == UX3_RX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxeq_ctle_bias_adj == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxeq_ctle_biasboost == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxeq_ctle_lf_gain == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxeq_ctle_midband_zero == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxeq_ctle_stage_1_dcgain == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxeq_ctle_stage_1_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxeq_ctle_stage_2_cap == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxeq_ctle_stage_2_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxeq_ctle_stage_2_reszero == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxeq_ctle_stage_3_dcgain == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxeq_ctle_stage_3_deq == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxeq_dfe_data_tap_10 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxeq_dfe_data_tap_11 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxeq_dfe_data_tap_12 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxeq_dfe_data_tap_13 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxeq_dfe_data_tap_14 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxeq_dfe_data_tap_15 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxeq_dfe_data_tap_16 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxeq_dfe_data_tap_2 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxeq_dfe_data_tap_3 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxeq_dfe_data_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxeq_dfe_data_tap_5 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxeq_dfe_data_tap_6 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxeq_dfe_data_tap_7 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxeq_dfe_data_tap_8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxeq_dfe_data_tap_9 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxeq_dfe_edge_tap_2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxeq_dfe_edge_tap_3 == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxeq_dfe_edge_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxeq_iq_clk == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxeq_targ_0_hi == 9'd149
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxeq_targ_0_lo == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxeq_vga_gain == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxratewidth_pd_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxrpu_evup_delay_lut_entry2 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxrpu_evup_delay_lut_entry4 == 50'd78
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxrpu_evup_delay_lut_entry5 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxrpu_evup_delay_lut_entry6 == 50'd1406
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_rxrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_select_lc_0_tx_path == UX3_SELECT_LC_0_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_select_lc_1_tx_path == UX3_SELECT_LC_1_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_select_lc_2_tx_path == UX3_SELECT_LC_2_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_select_lc_3_tx_path == UX3_SELECT_LC_3_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_select_lc_4_tx_path == UX3_SELECT_LC_4_TX_PATH_SLOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_sup_mode == UX3_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_afc_range == UX3_SYNTH_LC_0_AFC_RANGE_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_afc_refclk_count == 3'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_dtr_prop_coeff == 4'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_f_max_vco_hz == 40'd10500000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_f_min_vco_hz == 40'd8000000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_fast_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_fast_tx_postdiv_counter == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_feed_forward_gain == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_fine_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_fine_int_coeff_tmp == 4'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_fine_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_fine_prop_coeff_tmp == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_kvcc_settle_maxcnt == 8'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_m_counter == 9'd50
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_med_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_med_tx_postdiv_counter == 8'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_refclk_in_1us == 8'd100
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_slow_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_slow_tx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_tdc_fine_res_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_tdc_target_count == 8'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_0_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_afc_range == UX3_SYNTH_LC_1_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_feed_forward_gain == 8'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_m_counter == 9'd45
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_1_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_afc_range == UX3_SYNTH_LC_2_AFC_RANGE_FULL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_dtr_int_coeff == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_feed_forward_gain == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_m_counter == 9'd27
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_2_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_afc_range == UX3_SYNTH_LC_3_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_afc_refclk_count == 3'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_dtr_int_coeff == 5'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_feed_forward_gain == 8'd23
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_fine_int_coeff == 5'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_kvcc_settle_maxcnt == 8'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_m_counter == 9'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_refclk_in_1us == 8'd150
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_tdc_refclk_count == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_tdc_target_count == 8'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_3_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_afc_range == UX3_SYNTH_LC_4_AFC_RANGE_RESTRICTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_afc_refclk_count == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_div2_to_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_dtr_int_coeff == 5'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_dtr_prop_coeff == 4'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_dts_ssdiv == 3'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_f_max_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_f_min_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_fast_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_fast_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_fast_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_fast_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_fast_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_feed_forward_gain == 8'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_fine_int_coeff == 5'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_fine_prop_coeff == 4'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_kvcc_settle_maxcnt == 8'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_m_counter == 9'd216
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_med_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_med_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_med_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_med_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_med_tx_postdiv_counter_physical == 7'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_med_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_refclk_in_1us == 8'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_slow_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_slow_rx_cdr_cascade_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_slow_rx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_slow_rx_postdiv_to_cdr_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_slow_tx_postdiv_counter_physical == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_slow_tx_postdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_slowmed_path_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_tdc_fine_res_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_tdc_refclk_count == 4'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_tdc_target_count == 8'd120
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_vreg_avg_count == 3'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_4_vreg_loopen_maxcnt == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_fast_bw_sel == UX3_SYNTH_LC_FAST_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_fast_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_fast_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_fast_primary_use == UX3_SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_fast_refclk_mux_select == UX3_SYNTH_LC_FAST_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_fast_refclk_type_select == UX3_SYNTH_LC_FAST_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_fast_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_fb_div_emb_mult_counter == 2'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_l_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_l_counter_physical == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_med_bw_sel == UX3_SYNTH_LC_MED_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_med_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_med_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_med_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_med_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_med_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_med_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_med_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_med_primary_use == UX3_SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_med_refclk_mux_select == UX3_SYNTH_LC_MED_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_med_refclk_type_select == UX3_SYNTH_LC_MED_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_med_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_slow_bw_sel == UX3_SYNTH_LC_SLOW_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_slow_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_slow_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_slow_primary_use == UX3_SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_slow_refclk_mux_select == UX3_SYNTH_LC_SLOW_REFCLK_MUX_SELECT_REF_CLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_slow_refclk_type_select == UX3_SYNTH_LC_SLOW_REFCLK_TYPE_SELECT_FROM_REFCLKS_MUX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synth_lc_slow_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlc_0_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlc_0_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlc_0_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlc_0_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlc_1_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlc_1_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlc_1_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlc_1_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlc_2_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlc_2_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlc_2_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlc_2_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlc_3_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlc_3_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlc_3_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlc_3_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlc_4_apb_dwmask == 32'd2851864847
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlc_4_clkout_cb_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlc_4_refclk100div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlc_4_refclk156div_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlc_dcdmeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlcfastratewidth_pd_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlcfastrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlcfastrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlcfastrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlcfastrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlcfastrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlcfastrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlcfastrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlcfastrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlcfastrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlcfastrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlcfastrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlcmedrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlcmedrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlcmedrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlcmedrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlcmedrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlcmedrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlcmedrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlcmedrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlcmedrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlcmedrpu_evup_delay_lut_entry7 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlcslowrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlcslowrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlcslowrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlcslowrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlcslowrpu_evup_delay_lut_entry2 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlcslowrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlcslowrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlcslowrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlcslowrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_synthlcslowrpu_evup_delay_lut_entry7 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tdc_refclk_count_divisor == 40'd850000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tdc_refclk_count_scratch == 40'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tdc_target_count_scratch == 40'd128
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tx_bond_size == UX3_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tx_cal_dutymeas_delay_count == 9'd156
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tx_datarate == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tx_i_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tx_i_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tx_i_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tx_master_bond_chnl == UX3_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tx_o_clk_e2_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tx_o_clk_e4_hz == 36'd34341000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tx_o_clk_p_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tx_o_usr_clk_1_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tx_o_usr_clk_1_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tx_o_usr_clk_2_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tx_o_usr_clk_2_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tx_over_sample == UX3_TX_OVER_SAMPLE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tx_pll == UX3_TX_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tx_pll_bw_sel == UX3_TX_PLL_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tx_pll_is_downstream_pll == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tx_pll_refclk_mux_select == UX3_TX_PLL_REFCLK_MUX_SELECT_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tx_pll_refclk_select == UX3_TX_PLL_REFCLK_SELECT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tx_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tx_protocol == UX3_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tx_tuning_hint == UX3_TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tx_user_clk1_mux == UX3_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tx_user_clk2_mux == UX3_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tx_user_clk_slow_med_mux == UX3_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tx_which_lane_to_copy == UX3_TX_WHICH_LANE_TO_COPY_SELF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_tx_width == UX3_TX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_txeq_main_tap == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_txratewidth_rst_b0_off_delay_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_txrpu_evdn_delay_lut_entry1 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_txrpu_evdn_delay_lut_entry2 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_txrpu_evdn_delay_lut_entry3 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_txrpu_evup_delay_lut_entry1 == 50'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_txrpu_evup_delay_lut_entry2 == 50'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_txrpu_evup_delay_lut_entry3 == 50'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_txrpu_evup_delay_lut_entry4 == 50'd125
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_txrpu_evup_delay_lut_entry5 == 50'd781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_txrpu_evup_delay_lut_entry6 == 50'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_txrpu_evup_delay_lut_entry7 == 50'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_txrpu_evup_delay_lut_entry7_scratch == 47'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_txrx_channel_operation == UX3_TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_txrx_line_encoding_type == UX3_TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_txrx_xcvr_speed_bucket == UX3_TXRX_XCVR_SPEED_BUCKET_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux3_vreg_loopen_maxcnt_scratch == 40'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux_quad_instance == UX_QUAD_INSTANCE_THREE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.flux_top.ux_speed_grade == UX_SPEED_GRADE_DASH2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.all_enabled_refclks_always_running == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.all_ux_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.hard_all_ux_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.refclk0_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.refclk1_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.refclk2_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.refclk3_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.refclk4_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.refclk5_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.refclk6_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.refclk7_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.refclk8_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.refclk9_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_01_st_pt == 6'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_10_st_pt == 6'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_bonding_size_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_bonding_size_cfg_reserved_attr == 14'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ethernet_source == UX0_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_external_dpma_refclk_source == UX0_EXTERNAL_DPMA_REFCLK_SOURCE_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_flux_mode == UX0_FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_loopback_mode == UX0_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_q_dl_cfg_latpls_bw_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_q_dl_cfg_rst_rxbit_cntr_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_q_dl_cfg_sel_rxbit_adder_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_rx_adapt_mode == UX0_RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_rx_protocol == UX0_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_rx_rst_value_pre_user_mode_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_rx_tuning_hint == UX0_RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_standalone_core_clk_mux == UX0_STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_0_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_0_31 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_1_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_2_16to15 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_sv_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_syspll0_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_syspll1_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_syspll2_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_tx_bond_size == UX0_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_tx_master_bond_chnl == UX0_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_tx_protocol == UX0_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_tx_rst_value_pre_user_mode_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_tx_tuning_hint == UX0_TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_tx_user_clk1_mux == UX0_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_tx_user_clk2_mux == UX0_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_tx_user_clk_slow_med_mux == UX0_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_tx_width == UX0_TX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_0_23 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_0_31 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_1_1 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_2_16to15 == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxeiosdetectstat_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxeq_clr_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxeq_precal_code_sel_lx_nt_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxeq_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxeq_static_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxeyediag_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxovrcdrlock2dataen_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxterm_hiz_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_rxwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txbeacon_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txclkdivrate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txdetectrx_req_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txdrv_levn_lx_5to0 == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txdrv_levnm1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txdrv_levnp1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txdrv_levnp2_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txdrv_spare_l0_1to0 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txdrv_spare_l0_3to2 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txdrv_spare_l0_5to4 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txdrv_spare_l0_9to6 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txelecidle_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_en_txwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_0_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_0_31 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_1_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_2_16to15 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_ur_ovr_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux0_vsr_mode == UX0_VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_01_st_pt == 6'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_10_st_pt == 6'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_bonding_size_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_bonding_size_cfg_reserved_attr == 25'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ethernet_source == UX1_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_external_dpma_refclk_source == UX1_EXTERNAL_DPMA_REFCLK_SOURCE_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_flux_mode == UX1_FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_loopback_mode == UX1_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_q_dl_cfg_latpls_bw_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_q_dl_cfg_rst_rxbit_cntr_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_q_dl_cfg_sel_rxbit_adder_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_rx_adapt_mode == UX1_RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_rx_protocol == UX1_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_rx_rst_value_pre_user_mode_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_rx_tuning_hint == UX1_RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_standalone_core_clk_mux == UX1_STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_0_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_0_31 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_1_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_2_16to15 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_sv_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_syspll0_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_syspll1_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_syspll2_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_tx_bond_size == UX1_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_tx_master_bond_chnl == UX1_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_tx_protocol == UX1_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_tx_rst_value_pre_user_mode_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_tx_tuning_hint == UX1_TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_tx_user_clk1_mux == UX1_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_tx_user_clk2_mux == UX1_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_tx_user_clk_slow_med_mux == UX1_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_tx_width == UX1_TX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_0_23 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_0_31 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_1_1 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_2_16to15 == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxeiosdetectstat_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxeq_clr_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxeq_precal_code_sel_lx_nt_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxeq_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxeq_static_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxeyediag_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxovrcdrlock2dataen_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxterm_hiz_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_rxwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txbeacon_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txclkdivrate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txdetectrx_req_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txdrv_levn_lx_5to0 == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txdrv_levnm1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txdrv_levnp1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txdrv_levnp2_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txdrv_spare_l0_1to0 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txdrv_spare_l0_3to2 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txdrv_spare_l0_5to4 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txdrv_spare_l0_9to6 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txelecidle_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_en_txwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_0_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_0_31 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_1_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_2_16to15 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_ur_ovr_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux1_vsr_mode == UX1_VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_01_st_pt == 6'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_10_st_pt == 6'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_bonding_size_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_bonding_size_cfg_reserved_attr == 25'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ethernet_source == UX2_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_external_dpma_refclk_source == UX2_EXTERNAL_DPMA_REFCLK_SOURCE_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_flux_mode == UX2_FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_loopback_mode == UX2_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_q_dl_cfg_latpls_bw_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_q_dl_cfg_rst_rxbit_cntr_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_q_dl_cfg_sel_rxbit_adder_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_rx_adapt_mode == UX2_RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_rx_protocol == UX2_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_rx_rst_value_pre_user_mode_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_rx_tuning_hint == UX2_RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_standalone_core_clk_mux == UX2_STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_0_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_0_31 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_1_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_2_16to15 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_sv_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_syspll0_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_syspll1_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_syspll2_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_tx_bond_size == UX2_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_tx_master_bond_chnl == UX2_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_tx_protocol == UX2_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_tx_rst_value_pre_user_mode_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_tx_tuning_hint == UX2_TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_tx_user_clk1_mux == UX2_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_tx_user_clk2_mux == UX2_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_tx_user_clk_slow_med_mux == UX2_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_tx_width == UX2_TX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_0_23 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_0_31 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_1_1 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_2_16to15 == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxeiosdetectstat_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxeq_clr_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxeq_precal_code_sel_lx_nt_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxeq_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxeq_static_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxeyediag_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxovrcdrlock2dataen_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxterm_hiz_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_rxwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txbeacon_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txclkdivrate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txdetectrx_req_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txdrv_levn_lx_5to0 == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txdrv_levnm1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txdrv_levnp1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txdrv_levnp2_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txdrv_spare_l0_1to0 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txdrv_spare_l0_3to2 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txdrv_spare_l0_5to4 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txdrv_spare_l0_9to6 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txelecidle_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_en_txwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_0_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_0_31 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_1_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_2_16to15 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_ur_ovr_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux2_vsr_mode == UX2_VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_01_st_pt == 6'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_10_st_pt == 6'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_bonding_size_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_bonding_size_cfg_reserved_attr == 25'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ethernet_source == UX3_ETHERNET_SOURCE_E400G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_external_dpma_refclk_source == UX3_EXTERNAL_DPMA_REFCLK_SOURCE_GLOBAL_REFCLK_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_flux_mode == UX3_FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_loopback_mode == UX3_LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_q_dl_cfg_latpls_bw_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_q_dl_cfg_rst_rxbit_cntr_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_q_dl_cfg_sel_rxbit_adder_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_rx_adapt_mode == UX3_RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_rx_protocol == UX3_RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_rx_rst_value_pre_user_mode_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_rx_tuning_hint == UX3_RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_standalone_core_clk_mux == UX3_STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_0_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_0_31 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_1_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_2_16to15 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_sv_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_syspll0_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_syspll1_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_syspll2_refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_tx_bond_size == UX3_TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_tx_master_bond_chnl == UX3_TX_MASTER_BOND_CHNL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_tx_protocol == UX3_TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_tx_rst_value_pre_user_mode_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_tx_tuning_hint == UX3_TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_tx_user_clk1_mux == UX3_TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_tx_user_clk2_mux == UX3_TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_tx_user_clk_slow_med_mux == UX3_TX_USER_CLK_SLOW_MED_MUX_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_tx_width == UX3_TX_WIDTH_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_0_23 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_0_31 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_1_1 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_2_16to15 == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxeiosdetectstat_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxeq_clr_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxeq_precal_code_sel_lx_nt_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxeq_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxeq_static_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxeyediag_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxovrcdrlock2dataen_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxterm_hiz_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_rxwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txbeacon_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txclkdivrate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txdetectrx_req_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txdrv_levn_lx_5to0 == 6'd63
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txdrv_levnm1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txdrv_levnp1_lx_4to0 == 5'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txdrv_levnp2_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txdrv_spare_l0_1to0 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txdrv_spare_l0_3to2 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txdrv_spare_l0_5to4 == 2'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txdrv_spare_l0_9to6 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txelecidle_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txpstate_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txrate_lx_3to0 == 4'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_en_txwidth_lx_2to0 == 3'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_0_23 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_0_31 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_1_1 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_2_13to8 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_2_16to15 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_2_29to24 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxeq_precal_code_sel_lx_nt_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_rxwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txclkdivrate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txdrv_levn_lx_5to0 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txdrv_levnm1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txdrv_levnp1_lx_4to0 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txdrv_levnp2_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txdrv_spare_l0_1to0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txdrv_spare_l0_3to2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txdrv_spare_l0_5to4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txdrv_spare_l0_9to6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txelecidle_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txpstate_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txrate_lx_3to0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_ur_ovr_txwidth_lx_2to0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux3_vsr_mode == UX3_VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_cpi_cmn2_st_pt == 11'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_cpi_lm_addr == 30'd589884
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_cpi_phy_addr == 30'd589888
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_cpi_reserved == 7'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_cpi_seq_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_cpi_timer_max == 16'd500
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_end_pt == 11'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_flux_cpu_freq == 36'd250
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_PCSREF_L0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_PCSREF_L0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_bonding_ctrl_cfg_bonding_ctrl_l0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_bonding_ctrl_cfg_bonding_ctrl_l1_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_bonding_ctrl_cfg_bonding_ctrl_l2_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_bonding_ctrl_cfg_bonding_ctrl_l3_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_bonding_ctrl_cfg_bonding_enable_l0_attr == BONDING_L0_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_bonding_ctrl_cfg_bonding_enable_l1_attr == BONDING_L1_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_bonding_ctrl_cfg_bonding_enable_l2_attr == BONDING_L2_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_bonding_ctrl_cfg_bonding_enable_l3_attr == BONDING_L3_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_ckmux_cpu_attr == CKMUX_CPU_PLL0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_cpi_seq_ctrl_cfg_ctrl_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_datapath_loopback_en_cfg_datapath_loopback_en_l0_attr == LB_L0_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_datapath_loopback_en_cfg_datapath_loopback_en_l1_attr == LB_L1_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_datapath_loopback_en_cfg_datapath_loopback_en_l2_attr == LB_L2_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_datapath_loopback_en_cfg_datapath_loopback_en_l3_attr == LB_L3_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_a_cfg_clk_en_dfd_clk_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_a_cfg_dfd_clk_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_a_cfg_dfd_extrig_muxsel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_a_cfg_dfd_mux_sel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_a_cfg_dfd_rsvd_muxsel_attr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_a_cfg_pattern_cntr_data_sel_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_a_cfg_pattern_cntr_inc_attr == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_a_cfg_pattern_cntr_rst_b_attr == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_b_cfg_apb_rdata_sel_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_dfd_ctrl_b_cfg_rst_dfd_extrig_cntr_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_dl_ctrl_a_l2_cfg_ctrl_reserved_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_dl_ctrl_a_l3_cfg_ctrl_reserved_attr == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_dpma_clk_mux_reserved_attr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e200_rxclk_en_l0_attr == E200_RXCLK_EN_L0_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e200_rxclk_en_l1_attr == E200_RXCLK_EN_L1_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e200_rxclk_en_l2_attr == E200_RXCLK_EN_L2_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e200_rxclk_en_l3_attr == E200_RXCLK_EN_L3_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e200_txclk_en_l0_attr == E200_TXCLK_EN_L0_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e200_txclk_en_l1_attr == E200_TXCLK_EN_L1_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e200_txclk_en_l2_attr == E200_TXCLK_EN_L2_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e200_txclk_en_l3_attr == E200_TXCLK_EN_L3_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_slow_med_l0_attr == E400_CKMUX_SLOW_MED_L0_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_slow_med_l1_attr == E400_CKMUX_SLOW_MED_L1_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_slow_med_l2_attr == E400_CKMUX_SLOW_MED_L2_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_slow_med_l3_attr == E400_CKMUX_SLOW_MED_L3_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser0_l0_attr == E400_CKMUX_TXUSER0_L0_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser0_l1_attr == E400_CKMUX_TXUSER0_L1_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser0_l2_attr == E400_CKMUX_TXUSER0_L2_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser0_l3_attr == E400_CKMUX_TXUSER0_L3_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser1_l0_attr == E400_CKMUX_TXUSER1_L0_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser1_l1_attr == E400_CKMUX_TXUSER1_L1_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser1_l2_attr == E400_CKMUX_TXUSER1_L2_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser1_l3_attr == E400_CKMUX_TXUSER1_L3_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser2_l0_attr == E400_CKMUX_TXUSER2_L0_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser2_l1_attr == E400_CKMUX_TXUSER2_L1_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser2_l2_attr == E400_CKMUX_TXUSER2_L2_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_ckmux_txuser2_l3_attr == E400_CKMUX_TXUSER2_L3_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_rxclk_en_l0_attr == E400_RXCLK_EN_L0_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_rxclk_en_l1_attr == E400_RXCLK_EN_L1_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_rxclk_en_l2_attr == E400_RXCLK_EN_L2_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_rxclk_en_l3_attr == E400_RXCLK_EN_L3_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_rxusrclk_en_l0_attr == E400_RXUSRCLK_EN_L0_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_rxusrclk_en_l1_attr == E400_RXUSRCLK_EN_L1_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_rxusrclk_en_l2_attr == E400_RXUSRCLK_EN_L2_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_rxusrclk_en_l3_attr == E400_RXUSRCLK_EN_L3_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_txclk_en_l0_attr == E400_TXCLK_EN_L0_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_txclk_en_l1_attr == E400_TXCLK_EN_L1_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_txclk_en_l2_attr == E400_TXCLK_EN_L2_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_txclk_en_l3_attr == E400_TXCLK_EN_L3_TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk0_en_l0_attr == E400_USRCLK0_EN_L0_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk0_en_l1_attr == E400_USRCLK0_EN_L1_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk0_en_l2_attr == E400_USRCLK0_EN_L2_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk0_en_l3_attr == E400_USRCLK0_EN_L3_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk1_en_l0_attr == E400_USRCLK1_EN_L0_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk1_en_l1_attr == E400_USRCLK1_EN_L1_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk1_en_l2_attr == E400_USRCLK1_EN_L2_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk1_en_l3_attr == E400_USRCLK1_EN_L3_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk2_en_l0_attr == E400_USRCLK2_EN_L0_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk2_en_l1_attr == E400_USRCLK2_EN_L1_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk2_en_l2_attr == E400_USRCLK2_EN_L2_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e400_usrclk2_en_l3_attr == E400_USRCLK2_EN_L3_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e_rx_dp_pipe_l0_attr == E_RX_DP_PIPE_L0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e_rx_dp_pipe_l1_attr == E_RX_DP_PIPE_L1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e_rx_dp_pipe_l2_attr == E_RX_DP_PIPE_L2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e_rx_dp_pipe_l3_attr == E_RX_DP_PIPE_L3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e_tx_dp_pipe_l0_attr == E_TX_DP_PIPE_L0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e_tx_dp_pipe_l1_attr == E_TX_DP_PIPE_L1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e_tx_dp_pipe_l2_attr == E_TX_DP_PIPE_L2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_e_tx_dp_pipe_l3_attr == E_TX_DP_PIPE_L3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_fw_load_base_l0_cfg_value_attr == 32'd277792
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_fw_load_base_l1_cfg_value_attr == 32'd310560
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_fw_load_base_l2_cfg_value_attr == 32'd343328
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_fw_load_base_l3_cfg_value_attr == 32'd376096
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_i_pll0_hz == 36'd250000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_i_pll1_hz == 36'd250000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_i_pll2_hz == 36'd2831000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_indirect_access_ctrl_cfg_fw_load_disable_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_indirect_access_ctrl_cfg_fw_load_mode_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_indirect_access_ctrl_cfg_mapped_base_attr == 4'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_indirect_access_ctrl_cfg_reserved_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_indirect_access_ctrl_cfg_unmapped_base_attr == 18'd16384
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_mode_ctrl_cfg_func_mode_l0_attr == FUNC_MODE_E400_L0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_mode_ctrl_cfg_func_mode_l1_attr == FUNC_MODE_E400_L1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_mode_ctrl_cfg_func_mode_l2_attr == FUNC_MODE_E400_L2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_mode_ctrl_cfg_func_mode_l3_attr == FUNC_MODE_E400_L3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_medclk_en_l0_attr == PCIE_MEDCLK_EN_L0_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_medclk_en_l1_attr == PCIE_MEDCLK_EN_L1_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_medclk_en_l2_attr == PCIE_MEDCLK_EN_L2_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_medclk_en_l3_attr == PCIE_MEDCLK_EN_L3_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_pclk_en_l0_attr == PCIE_PCLK_EN_L0_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_pclk_en_l1_attr == PCIE_PCLK_EN_L1_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_pclk_en_l2_attr == PCIE_PCLK_EN_L2_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_pclk_en_l3_attr == PCIE_PCLK_EN_L3_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_refclk_en_l0_attr == PCIE_REFCLK_EN_L0_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_refclk_en_l1_attr == PCIE_REFCLK_EN_L1_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_refclk_en_l2_attr == PCIE_REFCLK_EN_L2_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_refclk_en_l3_attr == PCIE_REFCLK_EN_L3_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_rxclk_en_l0_attr == PCIE_RXCLK_EN_L0_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_rxclk_en_l1_attr == PCIE_RXCLK_EN_L1_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_rxclk_en_l2_attr == PCIE_RXCLK_EN_L2_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_rxclk_en_l3_attr == PCIE_RXCLK_EN_L3_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_slowclk_en_l0_attr == PCIE_SLOWCLK_EN_L0_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_slowclk_en_l1_attr == PCIE_SLOWCLK_EN_L1_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_slowclk_en_l2_attr == PCIE_SLOWCLK_EN_L2_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_pcie_slowclk_en_l3_attr == PCIE_SLOWCLK_EN_L3_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_reserved0_attr == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_0_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_10_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_11_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_12_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_13_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_14_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_15_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_16_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_17_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_18_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_19_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_1_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_20_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_21_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_22_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_23_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_24_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_25_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_26_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_27_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_28_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_29_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_2_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_30_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_31_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_32_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_33_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_34_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_35_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_36_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_37_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_38_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_39_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_3_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_40_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_41_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_42_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_43_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_44_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_45_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_46_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_47_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_48_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_49_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_4_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_50_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_51_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_52_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_53_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_54_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_55_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_56_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_57_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_58_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_59_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_5_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_60_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_61_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_62_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_63_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_6_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_7_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_8_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_addr_9_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_ctrl_0_cfg_restart_seq_sm_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_ctrl_0_cfg_skip_rd_seq_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_ctrl_1_cfg_seqen_0to31_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_ctrl_2_cfg_seqen_32to63_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_ctrl_3_cfg_seq_rdwrb_0to31_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_ctrl_4_cfg_seq_rdwrb_32to63_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_0_attr == 32'd32874599
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_10_attr == 32'd41731
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_11_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_12_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_13_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_14_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_15_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_16_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_17_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_18_attr == 32'd41056
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_19_attr == 32'd41200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_1_attr == 32'd41138
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_20_attr == 32'd41456
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_21_attr == 32'd41712
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_22_attr == 32'd41968
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_23_attr == 32'd41060
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_24_attr == 32'd41316
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_25_attr == 32'd41572
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_26_attr == 32'd41828
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_27_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_28_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_29_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_2_attr == 32'd41136
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_30_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_31_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_32_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_33_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_34_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_35_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_36_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_37_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_38_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_39_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_3_attr == 32'd16359439
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_40_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_41_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_42_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_43_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_44_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_45_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_46_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_47_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_48_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_49_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_4_attr == 32'd40963
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_50_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_51_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_52_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_53_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_54_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_55_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_56_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_57_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_58_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_59_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_5_attr == 32'd16359695
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_60_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_61_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_62_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_63_attr == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_6_attr == 32'd41219
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_7_attr == 32'd16359951
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_8_attr == 32'd41475
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_data_9_attr == 32'd16360207
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_0_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_10_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_11_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_12_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_13_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_14_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_15_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_16_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_17_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_18_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_19_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_1_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_20_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_21_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_22_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_23_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_24_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_25_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_26_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_27_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_28_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_29_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_2_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_30_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_31_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_32_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_33_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_34_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_35_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_36_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_37_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_38_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_39_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_3_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_40_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_41_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_42_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_43_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_44_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_45_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_46_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_47_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_48_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_49_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_4_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_50_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_51_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_52_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_53_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_54_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_55_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_56_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_57_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_58_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_59_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_5_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_60_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_61_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_62_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_63_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_6_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_7_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_8_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_q_seq_rdata_unmask_9_attr == 32'd4294967295
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_quad_instance == UX_QUAD_INSTANCE_THREE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.gdr.z1577b.u_ux_quad_3.gdr_ux_quad_avmm_cfgcsr.ux_rst_value_pre_user_mode_reserved_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[0].aib_rx_data_link_net_id == 32'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[0].avmm1_link_net_id == 32'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[0].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[0].ip_data_link_net_id == 32'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[0].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[0].bb.aib_hssi_rx_transfer_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[0].bb.aib_rx_user_clk_hz == 32'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[0].bb.aibadapt_rx_rx_10g_krfec_rx_diag_data_status_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[0].bb.aibadapt_rx_rx_datapath_tb_sel == AIBADAPT_RX_PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[0].bb.aibadapt_rx_rx_pld_8g_wa_boundary_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[0].bb.aibadapt_rx_rx_pld_pma_pcie_sw_done_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[0].bb.aibadapt_rx_rx_pld_pma_reser_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[0].bb.aibadapt_rx_rx_pld_pma_testbus_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[0].bb.aibadapt_rx_rx_pld_test_data_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[0].bb.aibadapt_rx_rx_user_clk_rst_sel == AIBADAPT_RX_RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[0].bb.aibadapt_rx_rx_user_clk_sel == AIBADAPT_RX_RX_USER_CLK_EHIP_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[0].bb.location == AIB11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[1].aib_rx_data_link_net_id == 32'd17
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[1].avmm1_link_net_id == 32'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[1].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[1].ip_data_link_net_id == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[1].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[1].bb.aib_hssi_rx_transfer_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[1].bb.aib_rx_user_clk_hz == 32'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[1].bb.aibadapt_rx_rx_10g_krfec_rx_diag_data_status_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[1].bb.aibadapt_rx_rx_datapath_tb_sel == AIBADAPT_RX_PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[1].bb.aibadapt_rx_rx_pld_8g_wa_boundary_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[1].bb.aibadapt_rx_rx_pld_pma_pcie_sw_done_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[1].bb.aibadapt_rx_rx_pld_pma_reser_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[1].bb.aibadapt_rx_rx_pld_pma_testbus_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[1].bb.aibadapt_rx_rx_pld_test_data_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[1].bb.aibadapt_rx_rx_user_clk_rst_sel == AIBADAPT_RX_RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[1].bb.aibadapt_rx_rx_user_clk_sel == AIBADAPT_RX_RX_USER_CLK_EHIP_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[1].bb.location == AIB16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[2].aib_rx_data_link_net_id == 32'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[2].avmm1_link_net_id == 32'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[2].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[2].ip_data_link_net_id == 32'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[2].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[2].bb.aib_hssi_rx_transfer_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[2].bb.aib_rx_user_clk_hz == 32'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[2].bb.aibadapt_rx_rx_10g_krfec_rx_diag_data_status_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[2].bb.aibadapt_rx_rx_datapath_tb_sel == AIBADAPT_RX_PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[2].bb.aibadapt_rx_rx_pld_8g_wa_boundary_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[2].bb.aibadapt_rx_rx_pld_pma_pcie_sw_done_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[2].bb.aibadapt_rx_rx_pld_pma_reser_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[2].bb.aibadapt_rx_rx_pld_pma_testbus_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[2].bb.aibadapt_rx_rx_pld_test_data_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[2].bb.aibadapt_rx_rx_user_clk_rst_sel == AIBADAPT_RX_RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[2].bb.aibadapt_rx_rx_user_clk_sel == AIBADAPT_RX_RX_USER_CLK_EHIP_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[2].bb.location == AIB14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[3].aib_rx_data_link_net_id == 32'd27
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[3].avmm1_link_net_id == 32'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[3].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[3].ip_data_link_net_id == 32'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[3].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[3].bb.aib_hssi_rx_transfer_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[3].bb.aib_rx_user_clk_hz == 32'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[3].bb.aibadapt_rx_rx_10g_krfec_rx_diag_data_status_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[3].bb.aibadapt_rx_rx_datapath_tb_sel == AIBADAPT_RX_PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[3].bb.aibadapt_rx_rx_pld_8g_wa_boundary_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[3].bb.aibadapt_rx_rx_pld_pma_pcie_sw_done_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[3].bb.aibadapt_rx_rx_pld_pma_reser_in_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[3].bb.aibadapt_rx_rx_pld_pma_testbus_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[3].bb.aibadapt_rx_rx_pld_test_data_polling_bypass == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[3].bb.aibadapt_rx_rx_user_clk_rst_sel == AIBADAPT_RX_RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[3].bb.aibadapt_rx_rx_user_clk_sel == AIBADAPT_RX_RX_USER_CLK_EHIP_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[3].bb.location == AIB8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[4].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[4].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[4].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[4].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[4].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[4].bb.aib_hssi_rx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[4].bb.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[4].bb.aibadapt_rx_rx_10g_krfec_rx_diag_data_status_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[4].bb.aibadapt_rx_rx_datapath_tb_sel == AIBADAPT_RX_AIB_DCC_DLL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[4].bb.aibadapt_rx_rx_pld_8g_wa_boundary_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[4].bb.aibadapt_rx_rx_pld_pma_pcie_sw_done_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[4].bb.aibadapt_rx_rx_pld_pma_reser_in_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[4].bb.aibadapt_rx_rx_pld_pma_testbus_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[4].bb.aibadapt_rx_rx_pld_test_data_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[4].bb.aibadapt_rx_rx_user_clk_rst_sel == AIBADAPT_RX_RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[4].bb.aibadapt_rx_rx_user_clk_sel == AIBADAPT_RX_RX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[4].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[5].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[5].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[5].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[5].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[5].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[5].bb.aib_hssi_rx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[5].bb.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[5].bb.aibadapt_rx_rx_10g_krfec_rx_diag_data_status_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[5].bb.aibadapt_rx_rx_datapath_tb_sel == AIBADAPT_RX_AIB_DCC_DLL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[5].bb.aibadapt_rx_rx_pld_8g_wa_boundary_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[5].bb.aibadapt_rx_rx_pld_pma_pcie_sw_done_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[5].bb.aibadapt_rx_rx_pld_pma_reser_in_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[5].bb.aibadapt_rx_rx_pld_pma_testbus_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[5].bb.aibadapt_rx_rx_pld_test_data_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[5].bb.aibadapt_rx_rx_user_clk_rst_sel == AIBADAPT_RX_RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[5].bb.aibadapt_rx_rx_user_clk_sel == AIBADAPT_RX_RX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[5].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[6].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[6].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[6].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[6].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[6].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[6].bb.aib_hssi_rx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[6].bb.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[6].bb.aibadapt_rx_rx_10g_krfec_rx_diag_data_status_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[6].bb.aibadapt_rx_rx_datapath_tb_sel == AIBADAPT_RX_AIB_DCC_DLL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[6].bb.aibadapt_rx_rx_pld_8g_wa_boundary_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[6].bb.aibadapt_rx_rx_pld_pma_pcie_sw_done_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[6].bb.aibadapt_rx_rx_pld_pma_reser_in_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[6].bb.aibadapt_rx_rx_pld_pma_testbus_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[6].bb.aibadapt_rx_rx_pld_test_data_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[6].bb.aibadapt_rx_rx_user_clk_rst_sel == AIBADAPT_RX_RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[6].bb.aibadapt_rx_rx_user_clk_sel == AIBADAPT_RX_RX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[6].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[7].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[7].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[7].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[7].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[7].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[7].bb.aib_hssi_rx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[7].bb.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[7].bb.aibadapt_rx_rx_10g_krfec_rx_diag_data_status_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[7].bb.aibadapt_rx_rx_datapath_tb_sel == AIBADAPT_RX_AIB_DCC_DLL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[7].bb.aibadapt_rx_rx_pld_8g_wa_boundary_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[7].bb.aibadapt_rx_rx_pld_pma_pcie_sw_done_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[7].bb.aibadapt_rx_rx_pld_pma_reser_in_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[7].bb.aibadapt_rx_rx_pld_pma_testbus_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[7].bb.aibadapt_rx_rx_pld_test_data_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[7].bb.aibadapt_rx_rx_user_clk_rst_sel == AIBADAPT_RX_RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[7].bb.aibadapt_rx_rx_user_clk_sel == AIBADAPT_RX_RX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[7].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[8].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[8].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[8].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[8].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[8].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[8].bb.aib_hssi_rx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[8].bb.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[8].bb.aibadapt_rx_rx_10g_krfec_rx_diag_data_status_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[8].bb.aibadapt_rx_rx_datapath_tb_sel == AIBADAPT_RX_AIB_DCC_DLL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[8].bb.aibadapt_rx_rx_pld_8g_wa_boundary_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[8].bb.aibadapt_rx_rx_pld_pma_pcie_sw_done_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[8].bb.aibadapt_rx_rx_pld_pma_reser_in_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[8].bb.aibadapt_rx_rx_pld_pma_testbus_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[8].bb.aibadapt_rx_rx_pld_test_data_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[8].bb.aibadapt_rx_rx_user_clk_rst_sel == AIBADAPT_RX_RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[8].bb.aibadapt_rx_rx_user_clk_sel == AIBADAPT_RX_RX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[8].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[9].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[9].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[9].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[9].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[9].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[9].bb.aib_hssi_rx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[9].bb.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[9].bb.aibadapt_rx_rx_10g_krfec_rx_diag_data_status_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[9].bb.aibadapt_rx_rx_datapath_tb_sel == AIBADAPT_RX_AIB_DCC_DLL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[9].bb.aibadapt_rx_rx_pld_8g_wa_boundary_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[9].bb.aibadapt_rx_rx_pld_pma_pcie_sw_done_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[9].bb.aibadapt_rx_rx_pld_pma_reser_in_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[9].bb.aibadapt_rx_rx_pld_pma_testbus_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[9].bb.aibadapt_rx_rx_pld_test_data_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[9].bb.aibadapt_rx_rx_user_clk_rst_sel == AIBADAPT_RX_RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[9].bb.aibadapt_rx_rx_user_clk_sel == AIBADAPT_RX_RX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[9].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[10].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[10].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[10].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[10].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[10].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[10].bb.aib_hssi_rx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[10].bb.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[10].bb.aibadapt_rx_rx_10g_krfec_rx_diag_data_status_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[10].bb.aibadapt_rx_rx_datapath_tb_sel == AIBADAPT_RX_AIB_DCC_DLL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[10].bb.aibadapt_rx_rx_pld_8g_wa_boundary_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[10].bb.aibadapt_rx_rx_pld_pma_pcie_sw_done_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[10].bb.aibadapt_rx_rx_pld_pma_reser_in_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[10].bb.aibadapt_rx_rx_pld_pma_testbus_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[10].bb.aibadapt_rx_rx_pld_test_data_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[10].bb.aibadapt_rx_rx_user_clk_rst_sel == AIBADAPT_RX_RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[10].bb.aibadapt_rx_rx_user_clk_sel == AIBADAPT_RX_RX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[10].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[11].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[11].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[11].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[11].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[11].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[11].bb.aib_hssi_rx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[11].bb.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[11].bb.aibadapt_rx_rx_10g_krfec_rx_diag_data_status_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[11].bb.aibadapt_rx_rx_datapath_tb_sel == AIBADAPT_RX_AIB_DCC_DLL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[11].bb.aibadapt_rx_rx_pld_8g_wa_boundary_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[11].bb.aibadapt_rx_rx_pld_pma_pcie_sw_done_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[11].bb.aibadapt_rx_rx_pld_pma_reser_in_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[11].bb.aibadapt_rx_rx_pld_pma_testbus_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[11].bb.aibadapt_rx_rx_pld_test_data_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[11].bb.aibadapt_rx_rx_user_clk_rst_sel == AIBADAPT_RX_RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[11].bb.aibadapt_rx_rx_user_clk_sel == AIBADAPT_RX_RX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[11].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[12].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[12].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[12].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[12].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[12].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[12].bb.aib_hssi_rx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[12].bb.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[12].bb.aibadapt_rx_rx_10g_krfec_rx_diag_data_status_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[12].bb.aibadapt_rx_rx_datapath_tb_sel == AIBADAPT_RX_AIB_DCC_DLL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[12].bb.aibadapt_rx_rx_pld_8g_wa_boundary_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[12].bb.aibadapt_rx_rx_pld_pma_pcie_sw_done_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[12].bb.aibadapt_rx_rx_pld_pma_reser_in_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[12].bb.aibadapt_rx_rx_pld_pma_testbus_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[12].bb.aibadapt_rx_rx_pld_test_data_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[12].bb.aibadapt_rx_rx_user_clk_rst_sel == AIBADAPT_RX_RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[12].bb.aibadapt_rx_rx_user_clk_sel == AIBADAPT_RX_RX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[12].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[13].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[13].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[13].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[13].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[13].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[13].bb.aib_hssi_rx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[13].bb.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[13].bb.aibadapt_rx_rx_10g_krfec_rx_diag_data_status_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[13].bb.aibadapt_rx_rx_datapath_tb_sel == AIBADAPT_RX_AIB_DCC_DLL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[13].bb.aibadapt_rx_rx_pld_8g_wa_boundary_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[13].bb.aibadapt_rx_rx_pld_pma_pcie_sw_done_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[13].bb.aibadapt_rx_rx_pld_pma_reser_in_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[13].bb.aibadapt_rx_rx_pld_pma_testbus_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[13].bb.aibadapt_rx_rx_pld_test_data_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[13].bb.aibadapt_rx_rx_user_clk_rst_sel == AIBADAPT_RX_RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[13].bb.aibadapt_rx_rx_user_clk_sel == AIBADAPT_RX_RX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[13].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[14].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[14].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[14].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[14].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[14].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[14].bb.aib_hssi_rx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[14].bb.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[14].bb.aibadapt_rx_rx_10g_krfec_rx_diag_data_status_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[14].bb.aibadapt_rx_rx_datapath_tb_sel == AIBADAPT_RX_AIB_DCC_DLL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[14].bb.aibadapt_rx_rx_pld_8g_wa_boundary_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[14].bb.aibadapt_rx_rx_pld_pma_pcie_sw_done_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[14].bb.aibadapt_rx_rx_pld_pma_reser_in_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[14].bb.aibadapt_rx_rx_pld_pma_testbus_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[14].bb.aibadapt_rx_rx_pld_test_data_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[14].bb.aibadapt_rx_rx_user_clk_rst_sel == AIBADAPT_RX_RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[14].bb.aibadapt_rx_rx_user_clk_sel == AIBADAPT_RX_RX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[14].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[15].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[15].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[15].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[15].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[15].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[15].bb.aib_hssi_rx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[15].bb.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[15].bb.aibadapt_rx_rx_10g_krfec_rx_diag_data_status_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[15].bb.aibadapt_rx_rx_datapath_tb_sel == AIBADAPT_RX_AIB_DCC_DLL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[15].bb.aibadapt_rx_rx_pld_8g_wa_boundary_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[15].bb.aibadapt_rx_rx_pld_pma_pcie_sw_done_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[15].bb.aibadapt_rx_rx_pld_pma_reser_in_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[15].bb.aibadapt_rx_rx_pld_pma_testbus_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[15].bb.aibadapt_rx_rx_pld_test_data_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[15].bb.aibadapt_rx_rx_user_clk_rst_sel == AIBADAPT_RX_RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[15].bb.aibadapt_rx_rx_user_clk_sel == AIBADAPT_RX_RX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[15].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[16].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[16].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[16].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[16].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[16].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[16].bb.aib_hssi_rx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[16].bb.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[16].bb.aibadapt_rx_rx_10g_krfec_rx_diag_data_status_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[16].bb.aibadapt_rx_rx_datapath_tb_sel == AIBADAPT_RX_AIB_DCC_DLL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[16].bb.aibadapt_rx_rx_pld_8g_wa_boundary_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[16].bb.aibadapt_rx_rx_pld_pma_pcie_sw_done_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[16].bb.aibadapt_rx_rx_pld_pma_reser_in_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[16].bb.aibadapt_rx_rx_pld_pma_testbus_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[16].bb.aibadapt_rx_rx_pld_test_data_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[16].bb.aibadapt_rx_rx_user_clk_rst_sel == AIBADAPT_RX_RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[16].bb.aibadapt_rx_rx_user_clk_sel == AIBADAPT_RX_RX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[16].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[17].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[17].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[17].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[17].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[17].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[17].bb.aib_hssi_rx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[17].bb.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[17].bb.aibadapt_rx_rx_10g_krfec_rx_diag_data_status_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[17].bb.aibadapt_rx_rx_datapath_tb_sel == AIBADAPT_RX_AIB_DCC_DLL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[17].bb.aibadapt_rx_rx_pld_8g_wa_boundary_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[17].bb.aibadapt_rx_rx_pld_pma_pcie_sw_done_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[17].bb.aibadapt_rx_rx_pld_pma_reser_in_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[17].bb.aibadapt_rx_rx_pld_pma_testbus_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[17].bb.aibadapt_rx_rx_pld_test_data_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[17].bb.aibadapt_rx_rx_user_clk_rst_sel == AIBADAPT_RX_RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[17].bb.aibadapt_rx_rx_user_clk_sel == AIBADAPT_RX_RX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[17].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[18].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[18].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[18].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[18].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[18].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[18].bb.aib_hssi_rx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[18].bb.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[18].bb.aibadapt_rx_rx_10g_krfec_rx_diag_data_status_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[18].bb.aibadapt_rx_rx_datapath_tb_sel == AIBADAPT_RX_AIB_DCC_DLL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[18].bb.aibadapt_rx_rx_pld_8g_wa_boundary_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[18].bb.aibadapt_rx_rx_pld_pma_pcie_sw_done_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[18].bb.aibadapt_rx_rx_pld_pma_reser_in_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[18].bb.aibadapt_rx_rx_pld_pma_testbus_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[18].bb.aibadapt_rx_rx_pld_test_data_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[18].bb.aibadapt_rx_rx_user_clk_rst_sel == AIBADAPT_RX_RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[18].bb.aibadapt_rx_rx_user_clk_sel == AIBADAPT_RX_RX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[18].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[19].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[19].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[19].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[19].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[19].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[19].bb.aib_hssi_rx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[19].bb.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[19].bb.aibadapt_rx_rx_10g_krfec_rx_diag_data_status_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[19].bb.aibadapt_rx_rx_datapath_tb_sel == AIBADAPT_RX_AIB_DCC_DLL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[19].bb.aibadapt_rx_rx_pld_8g_wa_boundary_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[19].bb.aibadapt_rx_rx_pld_pma_pcie_sw_done_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[19].bb.aibadapt_rx_rx_pld_pma_reser_in_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[19].bb.aibadapt_rx_rx_pld_pma_testbus_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[19].bb.aibadapt_rx_rx_pld_test_data_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[19].bb.aibadapt_rx_rx_user_clk_rst_sel == AIBADAPT_RX_RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[19].bb.aibadapt_rx_rx_user_clk_sel == AIBADAPT_RX_RX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[19].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[20].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[20].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[20].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[20].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[20].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[20].bb.aib_hssi_rx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[20].bb.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[20].bb.aibadapt_rx_rx_10g_krfec_rx_diag_data_status_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[20].bb.aibadapt_rx_rx_datapath_tb_sel == AIBADAPT_RX_AIB_DCC_DLL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[20].bb.aibadapt_rx_rx_pld_8g_wa_boundary_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[20].bb.aibadapt_rx_rx_pld_pma_pcie_sw_done_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[20].bb.aibadapt_rx_rx_pld_pma_reser_in_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[20].bb.aibadapt_rx_rx_pld_pma_testbus_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[20].bb.aibadapt_rx_rx_pld_test_data_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[20].bb.aibadapt_rx_rx_user_clk_rst_sel == AIBADAPT_RX_RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[20].bb.aibadapt_rx_rx_user_clk_sel == AIBADAPT_RX_RX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[20].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[21].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[21].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[21].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[21].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[21].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[21].bb.aib_hssi_rx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[21].bb.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[21].bb.aibadapt_rx_rx_10g_krfec_rx_diag_data_status_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[21].bb.aibadapt_rx_rx_datapath_tb_sel == AIBADAPT_RX_AIB_DCC_DLL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[21].bb.aibadapt_rx_rx_pld_8g_wa_boundary_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[21].bb.aibadapt_rx_rx_pld_pma_pcie_sw_done_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[21].bb.aibadapt_rx_rx_pld_pma_reser_in_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[21].bb.aibadapt_rx_rx_pld_pma_testbus_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[21].bb.aibadapt_rx_rx_pld_test_data_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[21].bb.aibadapt_rx_rx_user_clk_rst_sel == AIBADAPT_RX_RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[21].bb.aibadapt_rx_rx_user_clk_sel == AIBADAPT_RX_RX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[21].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[22].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[22].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[22].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[22].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[22].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[22].bb.aib_hssi_rx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[22].bb.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[22].bb.aibadapt_rx_rx_10g_krfec_rx_diag_data_status_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[22].bb.aibadapt_rx_rx_datapath_tb_sel == AIBADAPT_RX_AIB_DCC_DLL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[22].bb.aibadapt_rx_rx_pld_8g_wa_boundary_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[22].bb.aibadapt_rx_rx_pld_pma_pcie_sw_done_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[22].bb.aibadapt_rx_rx_pld_pma_reser_in_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[22].bb.aibadapt_rx_rx_pld_pma_testbus_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[22].bb.aibadapt_rx_rx_pld_test_data_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[22].bb.aibadapt_rx_rx_user_clk_rst_sel == AIBADAPT_RX_RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[22].bb.aibadapt_rx_rx_user_clk_sel == AIBADAPT_RX_RX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[22].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[23].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[23].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[23].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[23].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[23].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[23].bb.aib_hssi_rx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[23].bb.aib_rx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[23].bb.aibadapt_rx_rx_10g_krfec_rx_diag_data_status_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[23].bb.aibadapt_rx_rx_datapath_tb_sel == AIBADAPT_RX_AIB_DCC_DLL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[23].bb.aibadapt_rx_rx_pld_8g_wa_boundary_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[23].bb.aibadapt_rx_rx_pld_pma_pcie_sw_done_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[23].bb.aibadapt_rx_rx_pld_pma_reser_in_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[23].bb.aibadapt_rx_rx_pld_pma_testbus_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[23].bb.aibadapt_rx_rx_pld_test_data_polling_bypass == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[23].bb.aibadapt_rx_rx_user_clk_rst_sel == AIBADAPT_RX_RX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[23].bb.aibadapt_rx_rx_user_clk_sel == AIBADAPT_RX_RX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_rx[23].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[0].aib_tx_data_link_net_id == 32'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[0].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[0].ip_data_link_net_id == 32'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[0].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[0].bb.aib_hssi_tx_transfer_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[0].bb.aib_tx_user_clk_hz == 32'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[0].bb.aibadapt_tx_loopback_mode == AIBADAPT_TX_LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[0].bb.aibadapt_tx_sup_mode == AIBADAPT_TX_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[0].bb.aibadapt_tx_tx_latency_src_xcvrif == AIBADAPT_TX_LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[0].bb.aibadapt_tx_tx_user_clk_rst_sel == AIBADAPT_TX_TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[0].bb.aibadapt_tx_tx_user_clk_sel == AIBADAPT_TX_TX_USER_CLK_EHIP_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[0].bb.location == AIB11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[1].aib_tx_data_link_net_id == 32'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[1].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[1].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[1].ip_data_link_net_id == 32'd29
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[1].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[1].bb.aib_hssi_tx_transfer_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[1].bb.aib_tx_user_clk_hz == 32'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[1].bb.aibadapt_tx_loopback_mode == AIBADAPT_TX_LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[1].bb.aibadapt_tx_sup_mode == AIBADAPT_TX_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[1].bb.aibadapt_tx_tx_latency_src_xcvrif == AIBADAPT_TX_LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[1].bb.aibadapt_tx_tx_user_clk_rst_sel == AIBADAPT_TX_TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[1].bb.aibadapt_tx_tx_user_clk_sel == AIBADAPT_TX_TX_USER_CLK_EHIP_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[1].bb.location == AIB10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[2].aib_tx_data_link_net_id == 32'd35
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[2].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[2].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[2].ip_data_link_net_id == 32'd33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[2].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[2].bb.aib_hssi_tx_transfer_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[2].bb.aib_tx_user_clk_hz == 32'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[2].bb.aibadapt_tx_loopback_mode == AIBADAPT_TX_LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[2].bb.aibadapt_tx_sup_mode == AIBADAPT_TX_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[2].bb.aibadapt_tx_tx_latency_src_xcvrif == AIBADAPT_TX_LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[2].bb.aibadapt_tx_tx_user_clk_rst_sel == AIBADAPT_TX_TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[2].bb.aibadapt_tx_tx_user_clk_sel == AIBADAPT_TX_TX_USER_CLK_EHIP_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[2].bb.location == AIB13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[3].aib_tx_data_link_net_id == 32'd39
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[3].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[3].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[3].ip_data_link_net_id == 32'd37
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[3].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[3].bb.aib_hssi_tx_transfer_clk_hz == 32'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[3].bb.aib_tx_user_clk_hz == 32'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[3].bb.aibadapt_tx_loopback_mode == AIBADAPT_TX_LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[3].bb.aibadapt_tx_sup_mode == AIBADAPT_TX_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[3].bb.aibadapt_tx_tx_latency_src_xcvrif == AIBADAPT_TX_LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[3].bb.aibadapt_tx_tx_user_clk_rst_sel == AIBADAPT_TX_TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[3].bb.aibadapt_tx_tx_user_clk_sel == AIBADAPT_TX_TX_USER_CLK_EHIP_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[3].bb.location == AIB8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[4].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[4].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[4].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[4].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[4].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[4].bb.aib_hssi_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[4].bb.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[4].bb.aibadapt_tx_loopback_mode == AIBADAPT_TX_LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[4].bb.aibadapt_tx_sup_mode == AIBADAPT_TX_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[4].bb.aibadapt_tx_tx_latency_src_xcvrif == AIBADAPT_TX_LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[4].bb.aibadapt_tx_tx_user_clk_rst_sel == AIBADAPT_TX_TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[4].bb.aibadapt_tx_tx_user_clk_sel == AIBADAPT_TX_TX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[4].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[5].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[5].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[5].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[5].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[5].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[5].bb.aib_hssi_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[5].bb.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[5].bb.aibadapt_tx_loopback_mode == AIBADAPT_TX_LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[5].bb.aibadapt_tx_sup_mode == AIBADAPT_TX_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[5].bb.aibadapt_tx_tx_latency_src_xcvrif == AIBADAPT_TX_LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[5].bb.aibadapt_tx_tx_user_clk_rst_sel == AIBADAPT_TX_TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[5].bb.aibadapt_tx_tx_user_clk_sel == AIBADAPT_TX_TX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[5].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[6].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[6].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[6].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[6].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[6].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[6].bb.aib_hssi_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[6].bb.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[6].bb.aibadapt_tx_loopback_mode == AIBADAPT_TX_LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[6].bb.aibadapt_tx_sup_mode == AIBADAPT_TX_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[6].bb.aibadapt_tx_tx_latency_src_xcvrif == AIBADAPT_TX_LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[6].bb.aibadapt_tx_tx_user_clk_rst_sel == AIBADAPT_TX_TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[6].bb.aibadapt_tx_tx_user_clk_sel == AIBADAPT_TX_TX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[6].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[7].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[7].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[7].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[7].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[7].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[7].bb.aib_hssi_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[7].bb.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[7].bb.aibadapt_tx_loopback_mode == AIBADAPT_TX_LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[7].bb.aibadapt_tx_sup_mode == AIBADAPT_TX_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[7].bb.aibadapt_tx_tx_latency_src_xcvrif == AIBADAPT_TX_LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[7].bb.aibadapt_tx_tx_user_clk_rst_sel == AIBADAPT_TX_TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[7].bb.aibadapt_tx_tx_user_clk_sel == AIBADAPT_TX_TX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[7].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[8].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[8].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[8].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[8].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[8].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[8].bb.aib_hssi_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[8].bb.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[8].bb.aibadapt_tx_loopback_mode == AIBADAPT_TX_LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[8].bb.aibadapt_tx_sup_mode == AIBADAPT_TX_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[8].bb.aibadapt_tx_tx_latency_src_xcvrif == AIBADAPT_TX_LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[8].bb.aibadapt_tx_tx_user_clk_rst_sel == AIBADAPT_TX_TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[8].bb.aibadapt_tx_tx_user_clk_sel == AIBADAPT_TX_TX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[8].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[9].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[9].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[9].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[9].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[9].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[9].bb.aib_hssi_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[9].bb.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[9].bb.aibadapt_tx_loopback_mode == AIBADAPT_TX_LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[9].bb.aibadapt_tx_sup_mode == AIBADAPT_TX_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[9].bb.aibadapt_tx_tx_latency_src_xcvrif == AIBADAPT_TX_LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[9].bb.aibadapt_tx_tx_user_clk_rst_sel == AIBADAPT_TX_TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[9].bb.aibadapt_tx_tx_user_clk_sel == AIBADAPT_TX_TX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[9].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[10].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[10].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[10].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[10].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[10].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[10].bb.aib_hssi_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[10].bb.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[10].bb.aibadapt_tx_loopback_mode == AIBADAPT_TX_LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[10].bb.aibadapt_tx_sup_mode == AIBADAPT_TX_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[10].bb.aibadapt_tx_tx_latency_src_xcvrif == AIBADAPT_TX_LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[10].bb.aibadapt_tx_tx_user_clk_rst_sel == AIBADAPT_TX_TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[10].bb.aibadapt_tx_tx_user_clk_sel == AIBADAPT_TX_TX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[10].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[11].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[11].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[11].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[11].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[11].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[11].bb.aib_hssi_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[11].bb.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[11].bb.aibadapt_tx_loopback_mode == AIBADAPT_TX_LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[11].bb.aibadapt_tx_sup_mode == AIBADAPT_TX_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[11].bb.aibadapt_tx_tx_latency_src_xcvrif == AIBADAPT_TX_LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[11].bb.aibadapt_tx_tx_user_clk_rst_sel == AIBADAPT_TX_TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[11].bb.aibadapt_tx_tx_user_clk_sel == AIBADAPT_TX_TX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[11].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[12].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[12].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[12].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[12].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[12].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[12].bb.aib_hssi_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[12].bb.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[12].bb.aibadapt_tx_loopback_mode == AIBADAPT_TX_LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[12].bb.aibadapt_tx_sup_mode == AIBADAPT_TX_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[12].bb.aibadapt_tx_tx_latency_src_xcvrif == AIBADAPT_TX_LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[12].bb.aibadapt_tx_tx_user_clk_rst_sel == AIBADAPT_TX_TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[12].bb.aibadapt_tx_tx_user_clk_sel == AIBADAPT_TX_TX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[12].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[13].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[13].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[13].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[13].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[13].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[13].bb.aib_hssi_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[13].bb.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[13].bb.aibadapt_tx_loopback_mode == AIBADAPT_TX_LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[13].bb.aibadapt_tx_sup_mode == AIBADAPT_TX_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[13].bb.aibadapt_tx_tx_latency_src_xcvrif == AIBADAPT_TX_LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[13].bb.aibadapt_tx_tx_user_clk_rst_sel == AIBADAPT_TX_TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[13].bb.aibadapt_tx_tx_user_clk_sel == AIBADAPT_TX_TX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[13].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[14].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[14].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[14].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[14].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[14].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[14].bb.aib_hssi_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[14].bb.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[14].bb.aibadapt_tx_loopback_mode == AIBADAPT_TX_LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[14].bb.aibadapt_tx_sup_mode == AIBADAPT_TX_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[14].bb.aibadapt_tx_tx_latency_src_xcvrif == AIBADAPT_TX_LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[14].bb.aibadapt_tx_tx_user_clk_rst_sel == AIBADAPT_TX_TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[14].bb.aibadapt_tx_tx_user_clk_sel == AIBADAPT_TX_TX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[14].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[15].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[15].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[15].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[15].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[15].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[15].bb.aib_hssi_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[15].bb.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[15].bb.aibadapt_tx_loopback_mode == AIBADAPT_TX_LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[15].bb.aibadapt_tx_sup_mode == AIBADAPT_TX_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[15].bb.aibadapt_tx_tx_latency_src_xcvrif == AIBADAPT_TX_LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[15].bb.aibadapt_tx_tx_user_clk_rst_sel == AIBADAPT_TX_TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[15].bb.aibadapt_tx_tx_user_clk_sel == AIBADAPT_TX_TX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[15].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[16].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[16].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[16].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[16].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[16].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[16].bb.aib_hssi_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[16].bb.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[16].bb.aibadapt_tx_loopback_mode == AIBADAPT_TX_LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[16].bb.aibadapt_tx_sup_mode == AIBADAPT_TX_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[16].bb.aibadapt_tx_tx_latency_src_xcvrif == AIBADAPT_TX_LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[16].bb.aibadapt_tx_tx_user_clk_rst_sel == AIBADAPT_TX_TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[16].bb.aibadapt_tx_tx_user_clk_sel == AIBADAPT_TX_TX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[16].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[17].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[17].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[17].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[17].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[17].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[17].bb.aib_hssi_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[17].bb.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[17].bb.aibadapt_tx_loopback_mode == AIBADAPT_TX_LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[17].bb.aibadapt_tx_sup_mode == AIBADAPT_TX_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[17].bb.aibadapt_tx_tx_latency_src_xcvrif == AIBADAPT_TX_LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[17].bb.aibadapt_tx_tx_user_clk_rst_sel == AIBADAPT_TX_TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[17].bb.aibadapt_tx_tx_user_clk_sel == AIBADAPT_TX_TX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[17].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[18].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[18].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[18].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[18].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[18].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[18].bb.aib_hssi_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[18].bb.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[18].bb.aibadapt_tx_loopback_mode == AIBADAPT_TX_LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[18].bb.aibadapt_tx_sup_mode == AIBADAPT_TX_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[18].bb.aibadapt_tx_tx_latency_src_xcvrif == AIBADAPT_TX_LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[18].bb.aibadapt_tx_tx_user_clk_rst_sel == AIBADAPT_TX_TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[18].bb.aibadapt_tx_tx_user_clk_sel == AIBADAPT_TX_TX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[18].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[19].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[19].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[19].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[19].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[19].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[19].bb.aib_hssi_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[19].bb.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[19].bb.aibadapt_tx_loopback_mode == AIBADAPT_TX_LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[19].bb.aibadapt_tx_sup_mode == AIBADAPT_TX_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[19].bb.aibadapt_tx_tx_latency_src_xcvrif == AIBADAPT_TX_LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[19].bb.aibadapt_tx_tx_user_clk_rst_sel == AIBADAPT_TX_TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[19].bb.aibadapt_tx_tx_user_clk_sel == AIBADAPT_TX_TX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[19].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[20].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[20].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[20].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[20].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[20].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[20].bb.aib_hssi_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[20].bb.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[20].bb.aibadapt_tx_loopback_mode == AIBADAPT_TX_LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[20].bb.aibadapt_tx_sup_mode == AIBADAPT_TX_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[20].bb.aibadapt_tx_tx_latency_src_xcvrif == AIBADAPT_TX_LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[20].bb.aibadapt_tx_tx_user_clk_rst_sel == AIBADAPT_TX_TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[20].bb.aibadapt_tx_tx_user_clk_sel == AIBADAPT_TX_TX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[20].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[21].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[21].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[21].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[21].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[21].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[21].bb.aib_hssi_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[21].bb.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[21].bb.aibadapt_tx_loopback_mode == AIBADAPT_TX_LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[21].bb.aibadapt_tx_sup_mode == AIBADAPT_TX_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[21].bb.aibadapt_tx_tx_latency_src_xcvrif == AIBADAPT_TX_LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[21].bb.aibadapt_tx_tx_user_clk_rst_sel == AIBADAPT_TX_TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[21].bb.aibadapt_tx_tx_user_clk_sel == AIBADAPT_TX_TX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[21].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[22].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[22].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[22].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[22].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[22].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[22].bb.aib_hssi_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[22].bb.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[22].bb.aibadapt_tx_loopback_mode == AIBADAPT_TX_LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[22].bb.aibadapt_tx_sup_mode == AIBADAPT_TX_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[22].bb.aibadapt_tx_tx_latency_src_xcvrif == AIBADAPT_TX_LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[22].bb.aibadapt_tx_tx_user_clk_rst_sel == AIBADAPT_TX_TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[22].bb.aibadapt_tx_tx_user_clk_sel == AIBADAPT_TX_TX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[22].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[23].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[23].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[23].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[23].ip_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[23].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[23].bb.aib_hssi_tx_transfer_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[23].bb.aib_tx_user_clk_hz == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[23].bb.aibadapt_tx_loopback_mode == AIBADAPT_TX_LOOPBACK_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[23].bb.aibadapt_tx_sup_mode == AIBADAPT_TX_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[23].bb.aibadapt_tx_tx_latency_src_xcvrif == AIBADAPT_TX_LATENCY_PLS_E400E200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[23].bb.aibadapt_tx_tx_user_clk_rst_sel == AIBADAPT_TX_TX_USER_CLK_HARD_RST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[23].bb.aibadapt_tx_tx_user_clk_sel == AIBADAPT_TX_TX_USER_CLK_EHIP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_aib_tx[23].bb.location == AIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].xcvr_data2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].xcvr_data3_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.an_mode == AN_MODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.barak_es_limit == BARAK_ES_LIMIT_R1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk0_tx_ffe_output_swizzle == BK0_TXFFE_OUTPUT_SWIZZLE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_bitprog_gray == BK_BITPROG_NOGRAY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_bitprog_invert == BK_BITPROG_NOINVERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_bitprog_lane_mode == BK_BITPROG_LANE_MODE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_bitprog_lane_sel == BK_BITPROG_SEL_L0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_bitprog_opcode == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_bitprog_pllrate_sel == BK_BITPROG_PLLRATE_12G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_bitprog_prbssel_berthld_ppmsrc_pattype_netsel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_bitprog_swl == BK_BITPROG_SWL_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_bitprog_tx_fail_thld == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_bitprog_tx_preset_sel == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_bitprog_tx_test_length == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_bitprog_update_cfg == BK_BITPROG_NOUPDATE_CFG
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_car_tx_clk_src_sel == BK_CAR_TX_CLK_SRC_SEL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_dl_enable == DETLAT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_en_rxdat_profile == RXDAT_PROF_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_lnx_txovf_rxbdstb_inten == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_lnx_txudf_pldrstb_inten == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_pll_fullrate == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_rx_bdst_rcon_en == RX_BADST_RCON_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_rx_lat_bit_for_async == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_rx_ppmd_rcon_en == RX_PPMD_BADST_RCON_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_rxbit_cntr_pma == RXBIT_CNTR_PMADIR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_rxdat_1cnt_thld_high == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_rxdat_1cnt_thld_low == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_sel_tx_user_data == TX_USRDATA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq0_enable == SEQ0_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq10_enable == SEQ10_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq11_enable == SEQ11_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq12_enable == SEQ12_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq13_enable == SEQ13_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq14_enable == SEQ14_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq15_enable == SEQ15_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq16_enable == SEQ16_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq17_enable == SEQ17_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq18_enable == SEQ18_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq19_enable == SEQ19_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq1_enable == SEQ1_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq20_enable == SEQ20_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq21_enable == SEQ21_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq22_enable == SEQ22_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq23_enable == SEQ23_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq24_enable == SEQ24_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq25_enable == SEQ25_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq26_enable == SEQ26_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq27_enable == SEQ27_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq28_enable == SEQ28_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq29_enable == SEQ29_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq2_enable == SEQ2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq30_enable == SEQ30_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq31_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq31_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq31_enable == SEQ31_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq31_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq31_rdwrb == SEQ31_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq32_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq32_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq32_enable == SEQ32_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq32_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq32_rdwrb == SEQ32_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq33_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq33_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq33_enable == SEQ33_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq33_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq33_rdwrb == SEQ33_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq34_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq34_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq34_enable == SEQ34_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq34_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq34_rdwrb == SEQ34_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq35_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq35_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq35_enable == SEQ35_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq35_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq35_rdwrb == SEQ35_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq36_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq36_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq36_enable == SEQ36_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq36_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq36_rdwrb == SEQ36_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq37_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq37_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq37_enable == SEQ37_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq37_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq37_rdwrb == SEQ37_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq38_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq38_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq38_enable == SEQ38_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq38_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq38_rdwrb == SEQ38_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq39_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq39_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq39_enable == SEQ39_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq39_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq39_rdwrb == SEQ39_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq3_enable == SEQ3_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq40_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq40_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq40_enable == SEQ40_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq40_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq40_rdwrb == SEQ40_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq41_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq41_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq41_enable == SEQ41_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq41_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq41_rdwrb == SEQ41_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq42_enable == SEQ42_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq43_enable == SEQ43_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq44_enable == SEQ44_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq45_enable == SEQ45_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq46_enable == SEQ46_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq4_enable == SEQ4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq55_enable == SEQ55_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq56_enable == SEQ56_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq57_enable == SEQ57_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq58_enable == SEQ58_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq59_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq59_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq59_enable == SEQ59_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq59_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq59_rdwrb == SEQ59_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq5_enable == SEQ5_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq60_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq60_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq60_enable == SEQ60_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq60_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq60_rdwrb == SEQ60_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq61_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq61_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq61_enable == SEQ61_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq61_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq61_rdwrb == SEQ61_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq62_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq62_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq62_enable == SEQ62_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq62_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq62_rdwrb == SEQ62_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq63_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq63_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq63_enable == SEQ63_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq63_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq63_rdwrb == SEQ63_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq6_enable == SEQ6_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq7_enable == SEQ7_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq8_enable == SEQ8_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_seq9_enable == SEQ9_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_speed_grade == BK_SPEED_GRADE_DASH1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_tx_lnx_ovf_inten_dirsignal == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_tx_lnx_rxbadst_inten_dirsignal == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_tx_lnx_udf_inten_dirsignal == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_tx_usr_data_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_tx_usr_data_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_tx_usr_data_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bk_tx_usr_data_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.bti_protected == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.channel_type == CHNL_SIMULATION
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.ext_ac_cap == EXTERNAL_AC_CAP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.location == BK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.loopback_mode == LPBK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.package_type == HIGHEND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.pam4_rxgrey_code == PAM4_RXGREY_IS_B4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.pll_n_counter == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.pll_pcs3334_ratio == DIV_33_BY_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.pll_rx_pcs3334_ratio == RX_DIV_33_BY_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.refclk_source_lane_pll == REF_TO_GND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.rx_ber_cnt_limit_lsb == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.rx_ber_cnt_limit_msb == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.rx_ber_cnt_mask_0_31 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.rx_ber_cnt_mask_32_63 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.rx_ber_cnt_mask_64_95 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.rx_ber_cnt_mask_96_127 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.rx_invert_p_and_n == RX_INVERT_PN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.rx_prbs_common_en == RX_PRBS_COMMON_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.rx_prbs_mode == RX_PRBS_7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.rx_precode_en == RX_PRECODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.rx_termination == RXTERM_OFFSET_P0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.rx_user_clk1_en == RX_USRCLK1_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.rx_user_clk1_sel == RX_USRCLK1SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.rx_user_clk2_en == RX_USRCLK2_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.rx_user_clk2_sel == RX_USRCLK2SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.speed_grade == SPEED_GRADE_112G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.tx_bond_size == TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.tx_invert_p_and_n == TX_INVERT_PN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.tx_line_rate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.tx_prbs_en == TX_PRBS_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.tx_prbs_mode == TX_PRBS_7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.tx_precode_en == TX_PRECODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.tx_protocol == TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.tx_termination == TXTERM_OFFSET_P0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.tx_user_clk1_en == TX_USRCLK1_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.tx_user_clk1_sel == TX_USRCLK1SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.tx_user_clk2_en == TX_USRCLK2_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.tx_user_clk2_sel == TX_USRCLK2SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.txeq_main_tap == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.txeq_post_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.txeq_post_tap_2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.txeq_post_tap_3 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.txeq_post_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.txeq_pre_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.txeq_pre_tap_2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.txeq_pre_tap_3 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.txout_tristate_en == TXOUT_TRISTATE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.txrx_line_encoding_type == TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[0].bb.txrx_xcvr_speed_bucket == TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].xcvr_data2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].xcvr_data3_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.an_mode == AN_MODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.barak_es_limit == BARAK_ES_LIMIT_R1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk0_tx_ffe_output_swizzle == BK0_TXFFE_OUTPUT_SWIZZLE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_bitprog_gray == BK_BITPROG_NOGRAY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_bitprog_invert == BK_BITPROG_NOINVERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_bitprog_lane_mode == BK_BITPROG_LANE_MODE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_bitprog_lane_sel == BK_BITPROG_SEL_L0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_bitprog_opcode == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_bitprog_pllrate_sel == BK_BITPROG_PLLRATE_12G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_bitprog_prbssel_berthld_ppmsrc_pattype_netsel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_bitprog_swl == BK_BITPROG_SWL_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_bitprog_tx_fail_thld == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_bitprog_tx_preset_sel == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_bitprog_tx_test_length == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_bitprog_update_cfg == BK_BITPROG_NOUPDATE_CFG
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_car_tx_clk_src_sel == BK_CAR_TX_CLK_SRC_SEL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_dl_enable == DETLAT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_en_rxdat_profile == RXDAT_PROF_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_lnx_txovf_rxbdstb_inten == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_lnx_txudf_pldrstb_inten == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_pll_fullrate == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_rx_bdst_rcon_en == RX_BADST_RCON_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_rx_lat_bit_for_async == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_rx_ppmd_rcon_en == RX_PPMD_BADST_RCON_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_rxbit_cntr_pma == RXBIT_CNTR_PMADIR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_rxdat_1cnt_thld_high == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_rxdat_1cnt_thld_low == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_sel_tx_user_data == TX_USRDATA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq0_enable == SEQ0_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq10_enable == SEQ10_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq11_enable == SEQ11_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq12_enable == SEQ12_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq13_enable == SEQ13_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq14_enable == SEQ14_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq15_enable == SEQ15_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq16_enable == SEQ16_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq17_enable == SEQ17_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq18_enable == SEQ18_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq19_enable == SEQ19_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq1_enable == SEQ1_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq20_enable == SEQ20_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq21_enable == SEQ21_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq22_enable == SEQ22_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq23_enable == SEQ23_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq24_enable == SEQ24_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq25_enable == SEQ25_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq26_enable == SEQ26_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq27_enable == SEQ27_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq28_enable == SEQ28_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq29_enable == SEQ29_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq2_enable == SEQ2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq30_enable == SEQ30_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq31_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq31_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq31_enable == SEQ31_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq31_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq31_rdwrb == SEQ31_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq32_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq32_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq32_enable == SEQ32_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq32_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq32_rdwrb == SEQ32_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq33_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq33_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq33_enable == SEQ33_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq33_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq33_rdwrb == SEQ33_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq34_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq34_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq34_enable == SEQ34_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq34_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq34_rdwrb == SEQ34_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq35_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq35_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq35_enable == SEQ35_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq35_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq35_rdwrb == SEQ35_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq36_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq36_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq36_enable == SEQ36_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq36_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq36_rdwrb == SEQ36_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq37_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq37_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq37_enable == SEQ37_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq37_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq37_rdwrb == SEQ37_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq38_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq38_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq38_enable == SEQ38_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq38_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq38_rdwrb == SEQ38_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq39_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq39_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq39_enable == SEQ39_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq39_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq39_rdwrb == SEQ39_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq3_enable == SEQ3_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq40_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq40_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq40_enable == SEQ40_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq40_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq40_rdwrb == SEQ40_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq41_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq41_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq41_enable == SEQ41_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq41_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq41_rdwrb == SEQ41_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq42_enable == SEQ42_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq43_enable == SEQ43_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq44_enable == SEQ44_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq45_enable == SEQ45_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq46_enable == SEQ46_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq4_enable == SEQ4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq55_enable == SEQ55_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq56_enable == SEQ56_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq57_enable == SEQ57_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq58_enable == SEQ58_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq59_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq59_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq59_enable == SEQ59_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq59_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq59_rdwrb == SEQ59_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq5_enable == SEQ5_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq60_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq60_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq60_enable == SEQ60_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq60_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq60_rdwrb == SEQ60_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq61_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq61_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq61_enable == SEQ61_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq61_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq61_rdwrb == SEQ61_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq62_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq62_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq62_enable == SEQ62_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq62_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq62_rdwrb == SEQ62_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq63_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq63_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq63_enable == SEQ63_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq63_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq63_rdwrb == SEQ63_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq6_enable == SEQ6_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq7_enable == SEQ7_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq8_enable == SEQ8_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_seq9_enable == SEQ9_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_speed_grade == BK_SPEED_GRADE_DASH1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_tx_lnx_ovf_inten_dirsignal == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_tx_lnx_rxbadst_inten_dirsignal == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_tx_lnx_udf_inten_dirsignal == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_tx_usr_data_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_tx_usr_data_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_tx_usr_data_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bk_tx_usr_data_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.bti_protected == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.channel_type == CHNL_SIMULATION
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.ext_ac_cap == EXTERNAL_AC_CAP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.location == BK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.loopback_mode == LPBK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.package_type == HIGHEND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.pam4_rxgrey_code == PAM4_RXGREY_IS_B4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.pll_n_counter == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.pll_pcs3334_ratio == DIV_33_BY_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.pll_rx_pcs3334_ratio == RX_DIV_33_BY_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.refclk_source_lane_pll == REF_TO_GND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.rx_ber_cnt_limit_lsb == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.rx_ber_cnt_limit_msb == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.rx_ber_cnt_mask_0_31 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.rx_ber_cnt_mask_32_63 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.rx_ber_cnt_mask_64_95 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.rx_ber_cnt_mask_96_127 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.rx_invert_p_and_n == RX_INVERT_PN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.rx_prbs_common_en == RX_PRBS_COMMON_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.rx_prbs_mode == RX_PRBS_7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.rx_precode_en == RX_PRECODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.rx_termination == RXTERM_OFFSET_P0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.rx_user_clk1_en == RX_USRCLK1_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.rx_user_clk1_sel == RX_USRCLK1SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.rx_user_clk2_en == RX_USRCLK2_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.rx_user_clk2_sel == RX_USRCLK2SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.speed_grade == SPEED_GRADE_112G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.tx_bond_size == TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.tx_invert_p_and_n == TX_INVERT_PN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.tx_line_rate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.tx_prbs_en == TX_PRBS_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.tx_prbs_mode == TX_PRBS_7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.tx_precode_en == TX_PRECODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.tx_protocol == TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.tx_termination == TXTERM_OFFSET_P0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.tx_user_clk1_en == TX_USRCLK1_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.tx_user_clk1_sel == TX_USRCLK1SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.tx_user_clk2_en == TX_USRCLK2_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.tx_user_clk2_sel == TX_USRCLK2SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.txeq_main_tap == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.txeq_post_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.txeq_post_tap_2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.txeq_post_tap_3 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.txeq_post_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.txeq_pre_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.txeq_pre_tap_2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.txeq_pre_tap_3 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.txout_tristate_en == TXOUT_TRISTATE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.txrx_line_encoding_type == TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[1].bb.txrx_xcvr_speed_bucket == TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].xcvr_data2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].xcvr_data3_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.an_mode == AN_MODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.barak_es_limit == BARAK_ES_LIMIT_R1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk0_tx_ffe_output_swizzle == BK0_TXFFE_OUTPUT_SWIZZLE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_bitprog_gray == BK_BITPROG_NOGRAY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_bitprog_invert == BK_BITPROG_NOINVERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_bitprog_lane_mode == BK_BITPROG_LANE_MODE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_bitprog_lane_sel == BK_BITPROG_SEL_L0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_bitprog_opcode == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_bitprog_pllrate_sel == BK_BITPROG_PLLRATE_12G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_bitprog_prbssel_berthld_ppmsrc_pattype_netsel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_bitprog_swl == BK_BITPROG_SWL_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_bitprog_tx_fail_thld == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_bitprog_tx_preset_sel == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_bitprog_tx_test_length == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_bitprog_update_cfg == BK_BITPROG_NOUPDATE_CFG
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_car_tx_clk_src_sel == BK_CAR_TX_CLK_SRC_SEL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_dl_enable == DETLAT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_en_rxdat_profile == RXDAT_PROF_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_lnx_txovf_rxbdstb_inten == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_lnx_txudf_pldrstb_inten == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_pll_fullrate == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_rx_bdst_rcon_en == RX_BADST_RCON_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_rx_lat_bit_for_async == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_rx_ppmd_rcon_en == RX_PPMD_BADST_RCON_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_rxbit_cntr_pma == RXBIT_CNTR_PMADIR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_rxdat_1cnt_thld_high == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_rxdat_1cnt_thld_low == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_sel_tx_user_data == TX_USRDATA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq0_enable == SEQ0_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq10_enable == SEQ10_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq11_enable == SEQ11_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq12_enable == SEQ12_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq13_enable == SEQ13_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq14_enable == SEQ14_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq15_enable == SEQ15_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq16_enable == SEQ16_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq17_enable == SEQ17_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq18_enable == SEQ18_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq19_enable == SEQ19_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq1_enable == SEQ1_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq20_enable == SEQ20_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq21_enable == SEQ21_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq22_enable == SEQ22_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq23_enable == SEQ23_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq24_enable == SEQ24_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq25_enable == SEQ25_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq26_enable == SEQ26_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq27_enable == SEQ27_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq28_enable == SEQ28_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq29_enable == SEQ29_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq2_enable == SEQ2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq30_enable == SEQ30_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq31_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq31_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq31_enable == SEQ31_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq31_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq31_rdwrb == SEQ31_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq32_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq32_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq32_enable == SEQ32_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq32_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq32_rdwrb == SEQ32_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq33_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq33_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq33_enable == SEQ33_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq33_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq33_rdwrb == SEQ33_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq34_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq34_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq34_enable == SEQ34_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq34_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq34_rdwrb == SEQ34_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq35_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq35_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq35_enable == SEQ35_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq35_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq35_rdwrb == SEQ35_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq36_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq36_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq36_enable == SEQ36_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq36_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq36_rdwrb == SEQ36_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq37_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq37_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq37_enable == SEQ37_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq37_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq37_rdwrb == SEQ37_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq38_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq38_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq38_enable == SEQ38_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq38_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq38_rdwrb == SEQ38_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq39_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq39_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq39_enable == SEQ39_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq39_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq39_rdwrb == SEQ39_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq3_enable == SEQ3_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq40_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq40_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq40_enable == SEQ40_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq40_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq40_rdwrb == SEQ40_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq41_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq41_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq41_enable == SEQ41_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq41_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq41_rdwrb == SEQ41_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq42_enable == SEQ42_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq43_enable == SEQ43_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq44_enable == SEQ44_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq45_enable == SEQ45_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq46_enable == SEQ46_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq4_enable == SEQ4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq55_enable == SEQ55_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq56_enable == SEQ56_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq57_enable == SEQ57_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq58_enable == SEQ58_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq59_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq59_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq59_enable == SEQ59_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq59_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq59_rdwrb == SEQ59_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq5_enable == SEQ5_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq60_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq60_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq60_enable == SEQ60_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq60_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq60_rdwrb == SEQ60_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq61_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq61_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq61_enable == SEQ61_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq61_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq61_rdwrb == SEQ61_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq62_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq62_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq62_enable == SEQ62_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq62_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq62_rdwrb == SEQ62_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq63_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq63_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq63_enable == SEQ63_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq63_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq63_rdwrb == SEQ63_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq6_enable == SEQ6_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq7_enable == SEQ7_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq8_enable == SEQ8_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_seq9_enable == SEQ9_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_speed_grade == BK_SPEED_GRADE_DASH1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_tx_lnx_ovf_inten_dirsignal == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_tx_lnx_rxbadst_inten_dirsignal == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_tx_lnx_udf_inten_dirsignal == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_tx_usr_data_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_tx_usr_data_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_tx_usr_data_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bk_tx_usr_data_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.bti_protected == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.channel_type == CHNL_SIMULATION
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.ext_ac_cap == EXTERNAL_AC_CAP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.location == BK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.loopback_mode == LPBK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.package_type == HIGHEND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.pam4_rxgrey_code == PAM4_RXGREY_IS_B4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.pll_n_counter == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.pll_pcs3334_ratio == DIV_33_BY_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.pll_rx_pcs3334_ratio == RX_DIV_33_BY_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.refclk_source_lane_pll == REF_TO_GND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.rx_ber_cnt_limit_lsb == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.rx_ber_cnt_limit_msb == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.rx_ber_cnt_mask_0_31 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.rx_ber_cnt_mask_32_63 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.rx_ber_cnt_mask_64_95 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.rx_ber_cnt_mask_96_127 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.rx_invert_p_and_n == RX_INVERT_PN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.rx_prbs_common_en == RX_PRBS_COMMON_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.rx_prbs_mode == RX_PRBS_7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.rx_precode_en == RX_PRECODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.rx_termination == RXTERM_OFFSET_P0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.rx_user_clk1_en == RX_USRCLK1_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.rx_user_clk1_sel == RX_USRCLK1SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.rx_user_clk2_en == RX_USRCLK2_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.rx_user_clk2_sel == RX_USRCLK2SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.speed_grade == SPEED_GRADE_112G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.tx_bond_size == TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.tx_invert_p_and_n == TX_INVERT_PN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.tx_line_rate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.tx_prbs_en == TX_PRBS_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.tx_prbs_mode == TX_PRBS_7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.tx_precode_en == TX_PRECODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.tx_protocol == TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.tx_termination == TXTERM_OFFSET_P0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.tx_user_clk1_en == TX_USRCLK1_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.tx_user_clk1_sel == TX_USRCLK1SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.tx_user_clk2_en == TX_USRCLK2_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.tx_user_clk2_sel == TX_USRCLK2SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.txeq_main_tap == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.txeq_post_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.txeq_post_tap_2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.txeq_post_tap_3 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.txeq_post_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.txeq_pre_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.txeq_pre_tap_2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.txeq_pre_tap_3 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.txout_tristate_en == TXOUT_TRISTATE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.txrx_line_encoding_type == TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[2].bb.txrx_xcvr_speed_bucket == TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].xcvr_data2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].xcvr_data3_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.an_mode == AN_MODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.barak_es_limit == BARAK_ES_LIMIT_R1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk0_tx_ffe_output_swizzle == BK0_TXFFE_OUTPUT_SWIZZLE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_bitprog_gray == BK_BITPROG_NOGRAY
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_bitprog_invert == BK_BITPROG_NOINVERT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_bitprog_lane_mode == BK_BITPROG_LANE_MODE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_bitprog_lane_sel == BK_BITPROG_SEL_L0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_bitprog_opcode == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_bitprog_pllrate_sel == BK_BITPROG_PLLRATE_12G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_bitprog_prbssel_berthld_ppmsrc_pattype_netsel == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_bitprog_swl == BK_BITPROG_SWL_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_bitprog_tx_fail_thld == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_bitprog_tx_preset_sel == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_bitprog_tx_test_length == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_bitprog_update_cfg == BK_BITPROG_NOUPDATE_CFG
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_car_tx_clk_src_sel == BK_CAR_TX_CLK_SRC_SEL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_dl_enable == DETLAT_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_en_rxdat_profile == RXDAT_PROF_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_lnx_txovf_rxbdstb_inten == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_lnx_txudf_pldrstb_inten == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_pll_fullrate == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_rx_bdst_rcon_en == RX_BADST_RCON_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_rx_lat_bit_for_async == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_rx_ppmd_rcon_en == RX_PPMD_BADST_RCON_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_rxbit_cntr_pma == RXBIT_CNTR_PMADIR_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_rxbit_rollover == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_rxdat_1cnt_thld_high == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_rxdat_1cnt_thld_low == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_sel_tx_user_data == TX_USRDATA_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq0_enable == SEQ0_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq10_enable == SEQ10_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq11_enable == SEQ11_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq12_enable == SEQ12_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq13_enable == SEQ13_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq14_enable == SEQ14_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq15_enable == SEQ15_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq16_enable == SEQ16_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq17_enable == SEQ17_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq18_enable == SEQ18_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq19_enable == SEQ19_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq1_enable == SEQ1_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq20_enable == SEQ20_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq21_enable == SEQ21_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq22_enable == SEQ22_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq23_enable == SEQ23_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq24_enable == SEQ24_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq25_enable == SEQ25_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq26_enable == SEQ26_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq27_enable == SEQ27_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq28_enable == SEQ28_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq29_enable == SEQ29_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq2_enable == SEQ2_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq30_enable == SEQ30_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq31_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq31_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq31_enable == SEQ31_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq31_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq31_rdwrb == SEQ31_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq32_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq32_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq32_enable == SEQ32_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq32_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq32_rdwrb == SEQ32_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq33_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq33_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq33_enable == SEQ33_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq33_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq33_rdwrb == SEQ33_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq34_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq34_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq34_enable == SEQ34_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq34_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq34_rdwrb == SEQ34_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq35_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq35_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq35_enable == SEQ35_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq35_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq35_rdwrb == SEQ35_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq36_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq36_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq36_enable == SEQ36_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq36_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq36_rdwrb == SEQ36_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq37_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq37_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq37_enable == SEQ37_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq37_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq37_rdwrb == SEQ37_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq38_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq38_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq38_enable == SEQ38_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq38_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq38_rdwrb == SEQ38_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq39_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq39_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq39_enable == SEQ39_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq39_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq39_rdwrb == SEQ39_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq3_enable == SEQ3_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq40_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq40_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq40_enable == SEQ40_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq40_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq40_rdwrb == SEQ40_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq41_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq41_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq41_enable == SEQ41_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq41_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq41_rdwrb == SEQ41_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq42_enable == SEQ42_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq43_enable == SEQ43_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq44_enable == SEQ44_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq45_enable == SEQ45_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq46_enable == SEQ46_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq4_enable == SEQ4_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq55_enable == SEQ55_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq56_enable == SEQ56_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq57_enable == SEQ57_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq58_enable == SEQ58_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq59_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq59_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq59_enable == SEQ59_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq59_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq59_rdwrb == SEQ59_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq5_enable == SEQ5_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq60_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq60_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq60_enable == SEQ60_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq60_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq60_rdwrb == SEQ60_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq61_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq61_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq61_enable == SEQ61_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq61_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq61_rdwrb == SEQ61_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq62_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq62_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq62_enable == SEQ62_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq62_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq62_rdwrb == SEQ62_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq63_addr == 20'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq63_data == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq63_enable == SEQ63_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq63_rdata_unmask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq63_rdwrb == SEQ63_WR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq6_enable == SEQ6_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq7_enable == SEQ7_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq8_enable == SEQ8_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_seq9_enable == SEQ9_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_speed_grade == BK_SPEED_GRADE_DASH1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_tx_lnx_ovf_inten_dirsignal == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_tx_lnx_rxbadst_inten_dirsignal == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_tx_lnx_udf_inten_dirsignal == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_tx_usr_data_0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_tx_usr_data_1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_tx_usr_data_2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bk_tx_usr_data_3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.bti_protected == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.channel_type == CHNL_SIMULATION
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.ext_ac_cap == EXTERNAL_AC_CAP_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.location == BK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.loopback_mode == LPBK_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.package_type == HIGHEND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.pam4_rxgrey_code == PAM4_RXGREY_IS_B4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.pll_n_counter == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.pll_pcs3334_ratio == DIV_33_BY_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.pll_rx_pcs3334_ratio == RX_DIV_33_BY_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.refclk_source_lane_pll == REF_TO_GND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.rx_ber_cnt_limit_lsb == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.rx_ber_cnt_limit_msb == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.rx_ber_cnt_mask_0_31 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.rx_ber_cnt_mask_32_63 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.rx_ber_cnt_mask_64_95 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.rx_ber_cnt_mask_96_127 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.rx_invert_p_and_n == RX_INVERT_PN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.rx_prbs_common_en == RX_PRBS_COMMON_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.rx_prbs_mode == RX_PRBS_7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.rx_precode_en == RX_PRECODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.rx_termination == RXTERM_OFFSET_P0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.rx_user_clk1_en == RX_USRCLK1_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.rx_user_clk1_sel == RX_USRCLK1SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.rx_user_clk2_en == RX_USRCLK2_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.rx_user_clk2_sel == RX_USRCLK2SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.speed_grade == SPEED_GRADE_112G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.tx_bond_size == TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.tx_invert_p_and_n == TX_INVERT_PN_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.tx_line_rate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.tx_prbs_en == TX_PRBS_EN_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.tx_prbs_mode == TX_PRBS_7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.tx_precode_en == TX_PRECODE_DIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.tx_protocol == TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.tx_termination == TXTERM_OFFSET_P0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.tx_user_clk1_en == TX_USRCLK1_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.tx_user_clk1_sel == TX_USRCLK1SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.tx_user_clk2_en == TX_USRCLK2_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.tx_user_clk2_sel == TX_USRCLK2SEL_DIV3334
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.txeq_main_tap == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.txeq_post_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.txeq_post_tap_2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.txeq_post_tap_3 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.txeq_post_tap_4 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.txeq_pre_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.txeq_pre_tap_2 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.txeq_pre_tap_3 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.txout_tristate_en == TXOUT_TRISTATE_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.txrx_line_encoding_type == TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk[3].bb.txrx_xcvr_speed_bucket == TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk_cmnpll[0].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk_cmnpll[0].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk_cmnpll[0].refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk_cmnpll[0].bb.bk_clk_en_cmos_refclk_out == CLKEN_CMOS_REFCLKO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk_cmnpll[0].bb.cfg_kvcc_vreg_offset_en_val == CFG_KVCC_VREG_OFFSET_EN_VAL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk_cmnpll[0].bb.location == BK_COMMON_PLL_A
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk_cmnpll[0].bb.xtensa_clk == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk_cmnpll[1].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk_cmnpll[1].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk_cmnpll[1].refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk_cmnpll[1].bb.bk_clk_en_cmos_refclk_out == CLKEN_CMOS_REFCLKO_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk_cmnpll[1].bb.cfg_kvcc_vreg_offset_en_val == CFG_KVCC_VREG_OFFSET_EN_VAL_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk_cmnpll[1].bb.location == BK_COMMON_PLL_A
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk_cmnpll[1].bb.xtensa_clk == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk_refclk[0].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk_refclk[0].refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk_refclk[0].bb.freq == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk_refclk[0].bb.location == BK_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk_refclk[1].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk_refclk[1].refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk_refclk[1].bb.freq == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_bk_refclk[1].bb.location == BK_REFCLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].avmm1_link_net_id == 32'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].ip_data_link_0_net_id == 32'd6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].pll_link_net_id == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].xcvr_data_link_0_net_id == 32'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_PLL_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_RX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.duplex_mode == DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.e400g_ptp0_aib2_div2_clk == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.e400g_ptp1_aib2_div2_clk == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.location == E400G_25G_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.rx_aib_if_fifo_mode == RX_AIB_IF_FIFO_MODE_REGISTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.rx_datarate == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.rx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.rx_primary_use == RX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.rx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.rx_word_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.rx_xcvr_width == RX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.speed_map == SPEED_MAP_MAP_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.sys_clk_src == SYS_CLK_SRC_PLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.xcvr_mode == XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[0].bb.xcvr_type == XCVR_TYPE_UX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].avmm1_link_net_id == 32'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].ip_data_link_0_net_id == 32'd15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].pll_link_net_id == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].xcvr_data_link_0_net_id == 32'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_PLL_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_RX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.duplex_mode == DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.e400g_ptp0_aib2_div2_clk == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.e400g_ptp1_aib2_div2_clk == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.fec_clk_src == FEC_CLK_SRC_PLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.location == E400G_25G_7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.rx_aib_if_fifo_mode == RX_AIB_IF_FIFO_MODE_REGISTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.rx_datarate == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.rx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.rx_primary_use == RX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.rx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.rx_word_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.rx_xcvr_width == RX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.speed_map == SPEED_MAP_MAP_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.sys_clk_src == SYS_CLK_SRC_PLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.xcvr_mode == XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[1].bb.xcvr_type == XCVR_TYPE_UX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].avmm1_link_net_id == 32'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].ip_data_link_0_net_id == 32'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].pll_link_net_id == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].xcvr_data_link_0_net_id == 32'd21
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_PLL_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_RX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.duplex_mode == DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.e400g_ptp0_aib2_div2_clk == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.e400g_ptp1_aib2_div2_clk == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.fec_clk_src == FEC_CLK_SRC_PLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.location == E400G_25G_9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.rx_aib_if_fifo_mode == RX_AIB_IF_FIFO_MODE_REGISTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.rx_datarate == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.rx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.rx_primary_use == RX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.rx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.rx_word_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.rx_xcvr_width == RX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.speed_map == SPEED_MAP_MAP_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.sys_clk_src == SYS_CLK_SRC_PLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.xcvr_mode == XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[2].bb.xcvr_type == XCVR_TYPE_UX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].avmm1_link_net_id == 32'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].ip_data_link_0_net_id == 32'd25
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].pll_link_net_id == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].xcvr_data_link_0_net_id == 32'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_PLL_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_RX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.duplex_mode == DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.e400g_ptp0_aib2_div2_clk == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.e400g_ptp1_aib2_div2_clk == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.fec_clk_src == FEC_CLK_SRC_PLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.location == E400G_25G_15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.rx_aib_if_fifo_mode == RX_AIB_IF_FIFO_MODE_REGISTER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.rx_datarate == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.rx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.rx_primary_use == RX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.rx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.rx_word_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.rx_xcvr_width == RX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.speed_map == SPEED_MAP_MAP_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.sys_clk_src == SYS_CLK_SRC_PLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.xcvr_mode == XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[3].bb.xcvr_type == XCVR_TYPE_UX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.rx_aib_if_fifo_mode == RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.rx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.rx_xcvr_width == RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[4].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.rx_aib_if_fifo_mode == RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.rx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.rx_xcvr_width == RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[5].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.rx_aib_if_fifo_mode == RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.rx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.rx_xcvr_width == RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[6].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.rx_aib_if_fifo_mode == RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.rx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.rx_xcvr_width == RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[7].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.rx_aib_if_fifo_mode == RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.rx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.rx_xcvr_width == RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[8].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.rx_aib_if_fifo_mode == RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.rx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.rx_xcvr_width == RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[9].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.rx_aib_if_fifo_mode == RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.rx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.rx_xcvr_width == RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[10].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.rx_aib_if_fifo_mode == RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.rx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.rx_xcvr_width == RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[11].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.rx_aib_if_fifo_mode == RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.rx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.rx_xcvr_width == RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[12].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.rx_aib_if_fifo_mode == RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.rx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.rx_xcvr_width == RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[13].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.rx_aib_if_fifo_mode == RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.rx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.rx_xcvr_width == RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[14].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.rx_aib_if_fifo_mode == RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.rx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.rx_xcvr_width == RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[15].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.rx_aib_if_fifo_mode == RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.rx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.rx_xcvr_width == RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[16].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.rx_aib_if_fifo_mode == RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.rx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.rx_xcvr_width == RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[17].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.rx_aib_if_fifo_mode == RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.rx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.rx_xcvr_width == RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[18].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.rx_aib_if_fifo_mode == RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.rx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.rx_xcvr_width == RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[19].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.rx_aib_if_fifo_mode == RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.rx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.rx_xcvr_width == RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[20].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.rx_aib_if_fifo_mode == RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.rx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.rx_xcvr_width == RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[21].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.rx_aib_if_fifo_mode == RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.rx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.rx_xcvr_width == RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[22].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.aib2_rx_st_clk_en == AIB2_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.aib3_rx_st_clk_en == AIB3_RX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.pcs_ber_mon_mode == PCS_BER_MON_MODE_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.rx_aib_if_fifo_mode == RX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.rx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.rx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.rx_excvr_gb_ratio_mode == RX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.rx_excvr_if_fifo_mode == RX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.rx_fec_enable == RX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.rx_pcs_mode == RX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.rx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.rx_primary_use == RX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.rx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.rx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.rx_xcvr_width == RX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_rx[23].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].ip_data_link_0_net_id == 32'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].pll_link_net_id == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].xcvr_data_link_0_net_id == 32'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_PLL_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_TX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.duplex_mode == DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.e400g_ptp0_aib2_div2_clk == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.e400g_ptp1_aib2_div2_clk == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.location == E400G_25G_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.speed_map == SPEED_MAP_MAP_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.sys_clk_src == SYS_CLK_SRC_PLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_PHASECOMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.tx_datarate == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.tx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.tx_primary_use == TX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.tx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.tx_word_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.tx_xcvr_width == TX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.xcvr_mode == XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[0].bb.xcvr_type == XCVR_TYPE_UX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].ip_data_link_0_net_id == 32'd29
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].pll_link_net_id == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].xcvr_data_link_0_net_id == 32'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_PLL_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_TX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.duplex_mode == DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.e400g_ptp0_aib2_div2_clk == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.e400g_ptp1_aib2_div2_clk == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.fec_clk_src == FEC_CLK_SRC_PLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.location == E400G_25G_13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.speed_map == SPEED_MAP_MAP_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.sys_clk_src == SYS_CLK_SRC_PLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_PHASECOMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.tx_datarate == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.tx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.tx_primary_use == TX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.tx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.tx_word_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.tx_xcvr_width == TX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.xcvr_mode == XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[1].bb.xcvr_type == XCVR_TYPE_UX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].ip_data_link_0_net_id == 32'd33
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].pll_link_net_id == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].xcvr_data_link_0_net_id == 32'd34
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_PLL_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_TX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.duplex_mode == DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.e400g_ptp0_aib2_div2_clk == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.e400g_ptp1_aib2_div2_clk == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.fec_clk_src == FEC_CLK_SRC_PLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.location == E400G_25G_10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.speed_map == SPEED_MAP_MAP_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.sys_clk_src == SYS_CLK_SRC_PLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_PHASECOMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.tx_datarate == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.tx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.tx_primary_use == TX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.tx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.tx_word_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.tx_xcvr_width == TX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.xcvr_mode == XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[2].bb.xcvr_type == XCVR_TYPE_UX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].ip_data_link_0_net_id == 32'd37
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].pll_link_net_id == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].xcvr_data_link_0_net_id == 32'd38
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_PLL_DIV2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_TX_USER_CLK1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.duplex_mode == DUPLEX_MODE_SYSTEM_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.e400g_ptp0_aib2_div2_clk == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.e400g_ptp1_aib2_div2_clk == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.fec_clk_src == FEC_CLK_SRC_PLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.location == E400G_25G_15
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_ipg_removed_per_am_period == 16'd20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_keep_rx_crc == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_pause_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_pfc_holdoff_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_pfc_holdoff_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_pfc_holdoff_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_pfc_holdoff_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_pfc_holdoff_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_pfc_holdoff_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_pfc_holdoff_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_pfc_holdoff_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_pfc_pause_quanta_0 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_pfc_pause_quanta_1 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_pfc_pause_quanta_2 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_pfc_pause_quanta_3 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_pfc_pause_quanta_4 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_pfc_pause_quanta_5 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_pfc_pause_quanta_6 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_pfc_pause_quanta_7 == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_rx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_rx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_tx_mac_data_flow == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_tx_max_frame_size == 16'd1518
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_tx_pause_daddr == 48'd1652522221569
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_tx_pause_saddr == 48'd247393538562781
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_txmac_saddr == 48'd73588229205
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_uniform_holdoff_quanta == 16'd65535
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.speed_map == SPEED_MAP_MAP_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.sys_clk_src == SYS_CLK_SRC_PLL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_PHASECOMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.tx_datarate == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.tx_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_ELASTIC
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.tx_primary_use == TX_PRIMARY_USE_DIRECT_BUNDLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.tx_total_xcvr == 5'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.tx_word_clk_hz == 37'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.tx_xcvr_width == TX_XCVR_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.xcvr_mode == XCVR_MODE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[3].bb.xcvr_type == XCVR_TYPE_UX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.tx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.tx_xcvr_width == TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[4].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.tx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.tx_xcvr_width == TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[5].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.tx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.tx_xcvr_width == TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[6].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.tx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.tx_xcvr_width == TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[7].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.tx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.tx_xcvr_width == TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[8].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.tx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.tx_xcvr_width == TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[9].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.tx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.tx_xcvr_width == TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[10].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.tx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.tx_xcvr_width == TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[11].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.tx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.tx_xcvr_width == TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[12].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.tx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.tx_xcvr_width == TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[13].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.tx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.tx_xcvr_width == TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[14].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.tx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.tx_xcvr_width == TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[15].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.tx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.tx_xcvr_width == TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[16].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.tx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.tx_xcvr_width == TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[17].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.tx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.tx_xcvr_width == TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[18].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.tx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.tx_xcvr_width == TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[19].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.tx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.tx_xcvr_width == TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[20].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.tx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.tx_xcvr_width == TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[21].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.tx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.tx_xcvr_width == TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[22].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.aib2_tx_st_clk_en == AIB2_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.aib3_tx_st_clk_en == AIB3_TX_ST_CLK_EN_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.aibif_data_valid == AIBIF_DATA_VALID_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.duplex_mode == DUPLEX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.e400g_ptp0_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.e400g_ptp1_aib2_div2_clk == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.fec_802p3ck == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.fec_clk_src == FEC_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.fec_error == FEC_ERROR_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.fec_mode == FEC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.fec_spec == FEC_SPEC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.frac_size == F25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.is_fec_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.is_ptp_part_of_reconfig == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.location == E400G_25G_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.lpbk_mode == LPBK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_disable_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_enforce_max_frame_size == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_flow_control == MAC_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_flow_control_holdoff_mode == MAC_PER_QUEUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_force_link_fault_rf == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_forward_rx_pause_requests == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_ipg_removed_per_am_period == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_keep_rx_crc == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_link_fault_mode == MAC_LF_OFF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_mode == MAC_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_pause_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_pfc_holdoff_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_pfc_holdoff_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_pfc_holdoff_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_pfc_holdoff_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_pfc_holdoff_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_pfc_holdoff_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_pfc_holdoff_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_pfc_holdoff_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_pfc_pause_quanta_0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_pfc_pause_quanta_1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_pfc_pause_quanta_2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_pfc_pause_quanta_3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_pfc_pause_quanta_4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_pfc_pause_quanta_5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_pfc_pause_quanta_6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_pfc_pause_quanta_7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_remove_pads == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_request_tx_pause == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_rx_length_checking == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_rx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_rx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_rx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_rx_ptp_dbg_master_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_rx_ptp_phy_lane_num == MAC_E25G_X1_RX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_rx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_rxcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_source_address_insertion == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_strict_preamble_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_strict_sfd_checking == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_tx_ipg_size == MAC_IPG_12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_tx_mac_data_flow == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_tx_max_frame_size == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_tx_pause_daddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_tx_pause_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_tx_preamble_passthrough == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_tx_ptp_extra_latency == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_tx_ptp_phy_lane_num == MAC_E25G_X1_TX_LN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_tx_vlan_detection == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_txcrc_covers_preamble == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_txmac_saddr == 48'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_uniform_holdoff_quanta == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.mac_use_am_insert == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.ptp_mode == PTP_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.speed_map == SPEED_MAP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.sys_clk_src == SYS_CLK_SRC_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.tx_datarate == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.tx_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.tx_excvr_gb_ratio_mode == TX_EXCVR_GB_RATIO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.tx_fec_enable == TX_FEC_ENABLE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.tx_pcs_mode == TX_PCS_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.tx_pmadirect_single_width == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.tx_primary_use == TX_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.tx_total_xcvr == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.tx_word_clk_hz == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.tx_xcvr_width == TX_XCVR_WIDTH_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.xcvr_mode == XCVR_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ehip_tx[23].bb.xcvr_type == XCVR_TYPE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].avmm2_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].avmm2_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].avmm2_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].avmm2_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].ip_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].ip_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].ip_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].ip_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].ip_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].ip_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].ip_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].ip_data_link_16_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].ip_data_link_17_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].ip_data_link_18_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].ip_data_link_19_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].ip_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].ip_data_link_20_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].ip_data_link_21_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].ip_data_link_22_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].ip_data_link_23_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].ip_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].ip_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].ip_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].ip_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].ip_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].ip_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].ip_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].ip_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].xcvr_data_link_0_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].xcvr_data_link_10_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].xcvr_data_link_11_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].xcvr_data_link_12_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].xcvr_data_link_13_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].xcvr_data_link_14_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].xcvr_data_link_15_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].xcvr_data_link_1_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].xcvr_data_link_2_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].xcvr_data_link_3_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].xcvr_data_link_4_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].xcvr_data_link_5_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].xcvr_data_link_6_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].xcvr_data_link_7_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].xcvr_data_link_8_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].xcvr_data_link_9_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_cfg_bad_dllp_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_cfg_bad_tlp_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_cfg_corrected_internal_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_cfg_dl_protocol_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_cfg_fc_protocol_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_cfg_mlf_tlp_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_cfg_ptm_local_clock_adj_lsb == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_cfg_ptm_local_clock_adj_msb == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_cfg_rcvr_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_cfg_rcvr_overflow_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_cfg_replay_number_rollover_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_cfg_replay_timer_timeout_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_cfg_surprise_down_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_cfg_uncor_internal_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_clrhip_not_rst_sticky == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_cvp_data_compressed == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_cvp_data_encrypted == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_cvp_irq_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_cvp_jtag0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_cvp_user_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_ecrc_strip == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_ats_pagealignreq_pf0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_ats_pagealignreq_pf1 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_ats_pagealignreq_pf2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_ats_pagealignreq_pf3 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_ats_pagealignreq_pf4 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_ats_pagealignreq_pf5 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_ats_pagealignreq_pf6 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_ats_pagealignreq_pf7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msix_tablesize_pf0 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msix_tablesize_pf1 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msix_tablesize_pf2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msix_tablesize_pf3 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msix_tablesize_pf4 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msix_tablesize_pf5 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msix_tablesize_pf6 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msix_tablesize_pf7 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msixpba_bir_pf0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msixpba_bir_pf1 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msixpba_bir_pf2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msixpba_bir_pf3 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msixpba_bir_pf4 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msixpba_bir_pf5 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msixpba_bir_pf6 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msixpba_bir_pf7 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msixpba_offset_pf0 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msixpba_offset_pf1 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msixpba_offset_pf2 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msixpba_offset_pf3 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msixpba_offset_pf4 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msixpba_offset_pf5 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msixpba_offset_pf6 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msixpba_offset_pf7 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msixtable_bir_pf0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msixtable_bir_pf1 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msixtable_bir_pf2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msixtable_bir_pf3 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msixtable_bir_pf4 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msixtable_bir_pf5 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msixtable_bir_pf6 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msixtable_bir_pf7 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msixtable_offset_pf0 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msixtable_offset_pf1 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msixtable_offset_pf2 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msixtable_offset_pf3 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msixtable_offset_pf4 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msixtable_offset_pf5 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msixtable_offset_pf6 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_msixtable_offset_pf7 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_subsysid_pf0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_subsysid_pf1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_subsysid_pf2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_subsysid_pf3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_subsysid_pf4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_subsysid_pf5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_subsysid_pf6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_subsysid_pf7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_tph_sttablelocation_pf0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_tph_sttablelocation_pf1 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_tph_sttablelocation_pf2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_tph_sttablelocation_pf3 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_tph_sttablelocation_pf4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_tph_sttablelocation_pf5 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_tph_sttablelocation_pf6 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_tph_sttablelocation_pf7 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_tph_sttablesize_pf0 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_tph_sttablesize_pf1 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_tph_sttablesize_pf2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_tph_sttablesize_pf3 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_tph_sttablesize_pf4 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_tph_sttablesize_pf5 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_tph_sttablesize_pf6 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_exvf_tph_sttablesize_pf7 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_gpio_irq == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_irq_misc_ctrl == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_nonsriov_mode == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pcie_parity_bypass == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_acs_cap_acs_at_block == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_acs_cap_acs_direct_translated_p2p == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_acs_cap_acs_egress_ctrl_size == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_acs_cap_acs_p2p_cpl_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_acs_cap_acs_p2p_egress_control == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_acs_cap_acs_p2p_req_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_acs_cap_acs_src_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_acs_cap_acs_usp_forwarding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_adv_err_int_msg_num == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_ari_acs_fun_grp_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_auto_lane_flip_ctrl_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_aux_curr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_bar0_type == CTOP_CORE16_PF0_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_bar2_type == CTOP_CORE16_PF0_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_bar4_type == CTOP_CORE16_PF0_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_base_class_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_cardbus_cis_pointer == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_config_phy_tx_change == CTOP_CORE16_PF0_FULL_SWING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsi == CTOP_CORE16_PF0_NOT_REQUIRED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_16g_tx_preset0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_16g_tx_preset1 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_16g_tx_preset10 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_16g_tx_preset11 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_16g_tx_preset12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_16g_tx_preset13 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_16g_tx_preset14 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_16g_tx_preset15 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_16g_tx_preset2 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_16g_tx_preset3 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_16g_tx_preset4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_16g_tx_preset5 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_16g_tx_preset6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_16g_tx_preset7 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_16g_tx_preset8 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_16g_tx_preset9 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_rx_preset_hint0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_rx_preset_hint1 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_rx_preset_hint10 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_rx_preset_hint11 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_rx_preset_hint12 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_rx_preset_hint13 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_rx_preset_hint14 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_rx_preset_hint15 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_rx_preset_hint2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_rx_preset_hint3 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_rx_preset_hint4 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_rx_preset_hint5 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_rx_preset_hint6 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_rx_preset_hint7 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_rx_preset_hint8 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_rx_preset_hint9 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_tx_preset0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_tx_preset1 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_tx_preset10 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_tx_preset11 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_tx_preset12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_tx_preset13 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_tx_preset14 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_tx_preset15 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_tx_preset2 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_tx_preset3 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_tx_preset4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_tx_preset5 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_tx_preset6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_tx_preset7 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_tx_preset8 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_dsp_tx_preset9 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_eq_redo == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_eq_redo_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_fast_link_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_gen3_eq_pset_req_vec == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_gen3_eq_pset_req_vec_atg4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_int_pin == CTOP_CORE16_PF0_INTA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_invalidate_q_depth == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_loopback_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_no_soft_rst == CTOP_CORE16_PF0_INTERNALLY_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_page_aligned_req == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pasid_cap_execute_permission_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pasid_cap_max_pasid_width == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pasid_cap_privileged_mode_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pci_msi_64_bit_addr_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pci_msi_ext_data_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pci_msi_ext_data_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pci_msi_multiple_msg_cap == CTOP_CORE16_PF0_MSI_VEC_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pci_msix_bir == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pci_msix_pba == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pci_msix_pba_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pci_msix_table_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pci_msix_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pci_msix_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pci_type0_bar0_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pci_type0_bar0_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pci_type0_bar1_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pci_type0_bar1_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pci_type0_bar2_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pci_type0_bar2_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pci_type0_bar3_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pci_type0_bar3_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pci_type0_bar4_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pci_type0_bar4_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pci_type0_bar5_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pci_type0_bar5_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pci_type0_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pci_type0_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pcie_cap_attention_indicator == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pcie_cap_attention_indicator_button == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pcie_cap_crs_sw_visibility == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pcie_cap_electromech_interlock == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pcie_cap_ep_l0s_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pcie_cap_ep_l1_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pcie_cap_ext_tag_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pcie_cap_flr_cap == CTOP_CORE16_PF0_CAPABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pcie_cap_hot_plug_capable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pcie_cap_hot_plug_surprise == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pcie_cap_l0s_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pcie_cap_l1_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pcie_cap_link_auto_bw_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pcie_cap_link_bw_man_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pcie_cap_mrl_sensor == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pcie_cap_no_cmd_cpl_support == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pcie_cap_phy_slot_num == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pcie_cap_port_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pcie_cap_power_controller == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pcie_cap_power_indicator == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pcie_cap_sel_deemphasis == CTOP_CORE16_PF0_MINUS_6DB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pcie_cap_slot_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pcie_cap_slot_power_limit_scale == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pcie_cap_slot_power_limit_value == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pcie_int_msg_num == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pcie_slot_imp == CTOP_CORE16_PF0_NOT_IMPLEMENTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_pme_support == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_program_interface == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_prs_outstanding_capacity == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_ras_des_cap_force_detect_lane == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_ras_des_cap_force_detect_lane_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_revision_id == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_rom_bar_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_rp_rom_bar_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_rp_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_sel_deemphasis == CTOP_CORE16_PF0_MINUS_3DB_CTL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_shadow_sriov_vf_stride_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_sn_ser_num_reg_1_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_sn_ser_num_reg_2_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_sriov_sup_page_size == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_sriov_vf_bar0_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_sriov_vf_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_sriov_vf_bar0_type == CTOP_CORE16_PF0_SRIOV_VF_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_sriov_vf_bar1_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_sriov_vf_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_sriov_vf_bar2_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_sriov_vf_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_sriov_vf_bar2_type == CTOP_CORE16_PF0_SRIOV_VF_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_sriov_vf_bar3_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_sriov_vf_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_sriov_vf_bar4_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_sriov_vf_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_sriov_vf_bar4_type == CTOP_CORE16_PF0_SRIOV_VF_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_sriov_vf_bar5_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_sriov_vf_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_sriov_vf_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_sriov_vf_offset_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_sriov_vf_offset_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_sriov_vf_stride_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_subclass_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_subsys_dev_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_subsys_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_tph_req_cap_int_vec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_tph_req_cap_int_vec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_tph_req_cap_st_table_loc_0_vfcomm_cs2 == CTOP_CORE16_PF0_IN_TPH_STRUCT_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_tph_req_cap_st_table_loc_1 == CTOP_CORE16_PF0_NOT_IN_MSIX_TABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_tph_req_cap_st_table_loc_1_vfcomm_cs2 == CTOP_CORE16_PF0_NOT_IN_MSIX_TABLE_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_tph_req_cap_st_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_tph_req_cap_st_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_tph_req_device_spec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_tph_req_device_spec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_16g_tx_preset0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_16g_tx_preset1 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_16g_tx_preset10 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_16g_tx_preset11 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_16g_tx_preset12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_16g_tx_preset13 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_16g_tx_preset14 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_16g_tx_preset15 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_16g_tx_preset2 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_16g_tx_preset3 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_16g_tx_preset4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_16g_tx_preset5 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_16g_tx_preset6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_16g_tx_preset7 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_16g_tx_preset8 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_16g_tx_preset9 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_rx_preset_hint0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_rx_preset_hint1 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_rx_preset_hint10 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_rx_preset_hint11 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_rx_preset_hint12 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_rx_preset_hint13 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_rx_preset_hint14 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_rx_preset_hint15 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_rx_preset_hint2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_rx_preset_hint3 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_rx_preset_hint4 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_rx_preset_hint5 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_rx_preset_hint6 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_rx_preset_hint7 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_rx_preset_hint8 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_rx_preset_hint9 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_tx_preset0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_tx_preset1 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_tx_preset10 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_tx_preset11 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_tx_preset12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_tx_preset13 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_tx_preset14 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_tx_preset15 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_tx_preset2 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_tx_preset3 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_tx_preset4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_tx_preset5 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_tx_preset6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_tx_preset7 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_tx_preset8 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf0_usp_tx_preset9 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_acs_cap_acs_at_block == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_acs_cap_acs_direct_translated_p2p == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_acs_cap_acs_egress_ctrl_size == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_acs_cap_acs_p2p_cpl_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_acs_cap_acs_p2p_egress_control == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_acs_cap_acs_p2p_req_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_acs_cap_acs_src_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_acs_cap_acs_usp_forwarding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_aux_curr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_bar0_type == CTOP_CORE16_PF1_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_bar2_type == CTOP_CORE16_PF1_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_bar4_type == CTOP_CORE16_PF1_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_base_class_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_cardbus_cis_pointer == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_dsi == CTOP_CORE16_PF1_NOT_REQUIRED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_int_pin == CTOP_CORE16_PF1_INTA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_invalidate_q_depth == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_no_soft_rst == CTOP_CORE16_PF1_INTERNALLY_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_page_aligned_req == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_pasid_cap_execute_permission_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_pasid_cap_max_pasid_width == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_pasid_cap_privileged_mode_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_pci_msi_64_bit_addr_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_pci_msi_ext_data_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_pci_msi_ext_data_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_pci_msi_multiple_msg_cap == CTOP_CORE16_PF1_MSI_VEC_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_pci_msix_bir == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_pci_msix_pba == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_pci_msix_pba_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_pci_msix_table_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_pci_msix_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_pci_msix_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_pci_type0_bar0_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_pci_type0_bar0_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_pci_type0_bar1_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_pci_type0_bar1_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_pci_type0_bar2_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_pci_type0_bar2_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_pci_type0_bar3_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_pci_type0_bar3_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_pci_type0_bar4_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_pci_type0_bar4_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_pci_type0_bar5_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_pci_type0_bar5_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_pci_type0_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_pci_type0_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_pcie_cap_ep_l0s_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_pcie_cap_ep_l1_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_pcie_cap_ext_tag_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_pcie_cap_flr_cap == CTOP_CORE16_PF1_CAPABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_pcie_cap_l0s_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_pcie_cap_l1_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_pcie_cap_port_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_pcie_cap_slot_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_pme_support == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_program_interface == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_prs_outstanding_capacity == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_ras_des_cap_force_detect_lane == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_ras_des_cap_force_detect_lane_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_revision_id == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_rom_bar_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_shadow_sriov_vf_stride_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_sn_ser_num_reg_1_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_sn_ser_num_reg_2_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_sriov_sup_page_size == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_sriov_vf_bar0_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_sriov_vf_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_sriov_vf_bar0_type == CTOP_CORE16_PF1_SRIOV_VF_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_sriov_vf_bar1_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_sriov_vf_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_sriov_vf_bar2_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_sriov_vf_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_sriov_vf_bar2_type == CTOP_CORE16_PF1_SRIOV_VF_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_sriov_vf_bar3_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_sriov_vf_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_sriov_vf_bar4_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_sriov_vf_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_sriov_vf_bar4_type == CTOP_CORE16_PF1_SRIOV_VF_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_sriov_vf_bar5_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_sriov_vf_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_sriov_vf_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_sriov_vf_offset_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_sriov_vf_offset_position_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_sriov_vf_stride_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_subclass_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_subsys_dev_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_subsys_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_tph_req_cap_int_vec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_tph_req_cap_int_vec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_tph_req_cap_st_table_loc_0_vfcomm_cs2 == CTOP_CORE16_PF1_IN_TPH_STRUCT_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_tph_req_cap_st_table_loc_1 == CTOP_CORE16_PF1_NOT_IN_MSIX_TABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_tph_req_cap_st_table_loc_1_vfcomm_cs2 == CTOP_CORE16_PF1_NOT_IN_MSIX_TABLE_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_tph_req_cap_st_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_tph_req_cap_st_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_tph_req_device_spec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf1_tph_req_device_spec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_acs_cap_acs_at_block == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_acs_cap_acs_direct_translated_p2p == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_acs_cap_acs_egress_ctrl_size == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_acs_cap_acs_p2p_cpl_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_acs_cap_acs_p2p_egress_control == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_acs_cap_acs_p2p_req_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_acs_cap_acs_src_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_acs_cap_acs_usp_forwarding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_aux_curr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_bar0_type == CTOP_CORE16_PF2_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_bar2_type == CTOP_CORE16_PF2_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_bar4_type == CTOP_CORE16_PF2_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_base_class_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_cardbus_cis_pointer == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_dsi == CTOP_CORE16_PF2_NOT_REQUIRED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_int_pin == CTOP_CORE16_PF2_INTA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_invalidate_q_depth == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_no_soft_rst == CTOP_CORE16_PF2_INTERNALLY_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_page_aligned_req == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_pasid_cap_execute_permission_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_pasid_cap_max_pasid_width == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_pasid_cap_privileged_mode_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_pci_msi_64_bit_addr_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_pci_msi_ext_data_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_pci_msi_ext_data_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_pci_msi_multiple_msg_cap == CTOP_CORE16_PF2_MSI_VEC_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_pci_msix_bir == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_pci_msix_pba == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_pci_msix_pba_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_pci_msix_table_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_pci_msix_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_pci_msix_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_pci_type0_bar0_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_pci_type0_bar0_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_pci_type0_bar1_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_pci_type0_bar1_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_pci_type0_bar2_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_pci_type0_bar2_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_pci_type0_bar3_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_pci_type0_bar3_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_pci_type0_bar4_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_pci_type0_bar4_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_pci_type0_bar5_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_pci_type0_bar5_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_pci_type0_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_pci_type0_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_pcie_cap_ep_l0s_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_pcie_cap_ep_l1_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_pcie_cap_ext_tag_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_pcie_cap_flr_cap == CTOP_CORE16_PF2_CAPABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_pcie_cap_l0s_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_pcie_cap_l1_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_pcie_cap_port_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_pcie_cap_slot_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_pme_support == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_program_interface == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_prs_outstanding_capacity == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_ras_des_cap_force_detect_lane == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_ras_des_cap_force_detect_lane_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_revision_id == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_rom_bar_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_shadow_sriov_vf_stride_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_sn_ser_num_reg_1_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_sn_ser_num_reg_2_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_sriov_sup_page_size == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_sriov_vf_bar0_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_sriov_vf_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_sriov_vf_bar0_type == CTOP_CORE16_PF2_SRIOV_VF_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_sriov_vf_bar1_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_sriov_vf_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_sriov_vf_bar2_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_sriov_vf_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_sriov_vf_bar2_type == CTOP_CORE16_PF2_SRIOV_VF_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_sriov_vf_bar3_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_sriov_vf_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_sriov_vf_bar4_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_sriov_vf_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_sriov_vf_bar4_type == CTOP_CORE16_PF2_SRIOV_VF_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_sriov_vf_bar5_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_sriov_vf_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_sriov_vf_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_sriov_vf_offset_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_sriov_vf_offset_position_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_sriov_vf_stride_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_subclass_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_subsys_dev_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_subsys_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_tph_req_cap_int_vec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_tph_req_cap_int_vec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_tph_req_cap_st_table_loc_0_vfcomm_cs2 == CTOP_CORE16_PF2_IN_TPH_STRUCT_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_tph_req_cap_st_table_loc_1 == CTOP_CORE16_PF2_NOT_IN_MSIX_TABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_tph_req_cap_st_table_loc_1_vfcomm_cs2 == CTOP_CORE16_PF2_NOT_IN_MSIX_TABLE_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_tph_req_cap_st_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_tph_req_cap_st_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_tph_req_device_spec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf2_tph_req_device_spec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_acs_cap_acs_at_block == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_acs_cap_acs_direct_translated_p2p == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_acs_cap_acs_egress_ctrl_size == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_acs_cap_acs_p2p_cpl_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_acs_cap_acs_p2p_egress_control == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_acs_cap_acs_p2p_req_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_acs_cap_acs_src_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_acs_cap_acs_usp_forwarding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_aux_curr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_bar0_type == CTOP_CORE16_PF3_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_bar2_type == CTOP_CORE16_PF3_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_bar4_type == CTOP_CORE16_PF3_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_base_class_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_cardbus_cis_pointer == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_dsi == CTOP_CORE16_PF3_NOT_REQUIRED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_int_pin == CTOP_CORE16_PF3_INTA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_invalidate_q_depth == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_no_soft_rst == CTOP_CORE16_PF3_INTERNALLY_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_page_aligned_req == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_pasid_cap_execute_permission_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_pasid_cap_max_pasid_width == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_pasid_cap_privileged_mode_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_pci_msi_64_bit_addr_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_pci_msi_ext_data_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_pci_msi_ext_data_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_pci_msi_multiple_msg_cap == CTOP_CORE16_PF3_MSI_VEC_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_pci_msix_bir == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_pci_msix_pba == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_pci_msix_pba_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_pci_msix_table_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_pci_msix_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_pci_msix_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_pci_type0_bar0_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_pci_type0_bar0_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_pci_type0_bar1_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_pci_type0_bar1_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_pci_type0_bar2_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_pci_type0_bar2_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_pci_type0_bar3_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_pci_type0_bar3_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_pci_type0_bar4_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_pci_type0_bar4_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_pci_type0_bar5_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_pci_type0_bar5_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_pci_type0_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_pci_type0_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_pcie_cap_ep_l0s_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_pcie_cap_ep_l1_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_pcie_cap_ext_tag_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_pcie_cap_flr_cap == CTOP_CORE16_PF3_CAPABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_pcie_cap_l0s_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_pcie_cap_l1_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_pcie_cap_port_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_pcie_cap_slot_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_pme_support == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_program_interface == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_prs_outstanding_capacity == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_ras_des_cap_force_detect_lane == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_ras_des_cap_force_detect_lane_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_revision_id == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_rom_bar_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_shadow_sriov_vf_stride_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_sn_ser_num_reg_1_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_sn_ser_num_reg_2_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_sriov_sup_page_size == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_sriov_vf_bar0_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_sriov_vf_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_sriov_vf_bar0_type == CTOP_CORE16_PF3_SRIOV_VF_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_sriov_vf_bar1_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_sriov_vf_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_sriov_vf_bar2_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_sriov_vf_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_sriov_vf_bar2_type == CTOP_CORE16_PF3_SRIOV_VF_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_sriov_vf_bar3_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_sriov_vf_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_sriov_vf_bar4_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_sriov_vf_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_sriov_vf_bar4_type == CTOP_CORE16_PF3_SRIOV_VF_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_sriov_vf_bar5_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_sriov_vf_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_sriov_vf_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_sriov_vf_offset_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_sriov_vf_offset_position_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_sriov_vf_stride_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_subclass_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_subsys_dev_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_subsys_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_tph_req_cap_int_vec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_tph_req_cap_int_vec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_tph_req_cap_st_table_loc_0_vfcomm_cs2 == CTOP_CORE16_PF3_IN_TPH_STRUCT_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_tph_req_cap_st_table_loc_1 == CTOP_CORE16_PF3_NOT_IN_MSIX_TABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_tph_req_cap_st_table_loc_1_vfcomm_cs2 == CTOP_CORE16_PF3_NOT_IN_MSIX_TABLE_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_tph_req_cap_st_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_tph_req_cap_st_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_tph_req_device_spec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf3_tph_req_device_spec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_acs_cap_acs_at_block == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_acs_cap_acs_direct_translated_p2p == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_acs_cap_acs_egress_ctrl_size == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_acs_cap_acs_p2p_cpl_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_acs_cap_acs_p2p_egress_control == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_acs_cap_acs_p2p_req_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_acs_cap_acs_src_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_acs_cap_acs_usp_forwarding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_aux_curr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_bar0_type == CTOP_CORE16_PF4_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_bar2_type == CTOP_CORE16_PF4_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_bar4_type == CTOP_CORE16_PF4_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_base_class_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_cardbus_cis_pointer == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_dsi == CTOP_CORE16_PF4_NOT_REQUIRED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_int_pin == CTOP_CORE16_PF4_INTA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_invalidate_q_depth == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_no_soft_rst == CTOP_CORE16_PF4_INTERNALLY_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_page_aligned_req == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_pasid_cap_execute_permission_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_pasid_cap_max_pasid_width == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_pasid_cap_privileged_mode_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_pci_msi_64_bit_addr_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_pci_msi_ext_data_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_pci_msi_ext_data_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_pci_msi_multiple_msg_cap == CTOP_CORE16_PF4_MSI_VEC_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_pci_msix_bir == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_pci_msix_pba == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_pci_msix_pba_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_pci_msix_table_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_pci_msix_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_pci_msix_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_pci_type0_bar0_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_pci_type0_bar0_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_pci_type0_bar1_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_pci_type0_bar1_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_pci_type0_bar2_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_pci_type0_bar2_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_pci_type0_bar3_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_pci_type0_bar3_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_pci_type0_bar4_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_pci_type0_bar4_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_pci_type0_bar5_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_pci_type0_bar5_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_pci_type0_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_pci_type0_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_pcie_cap_ep_l0s_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_pcie_cap_ep_l1_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_pcie_cap_ext_tag_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_pcie_cap_flr_cap == CTOP_CORE16_PF4_CAPABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_pcie_cap_l0s_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_pcie_cap_l1_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_pcie_cap_port_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_pcie_cap_slot_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_pme_support == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_program_interface == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_prs_outstanding_capacity == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_ras_des_cap_force_detect_lane == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_ras_des_cap_force_detect_lane_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_revision_id == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_rom_bar_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_shadow_sriov_vf_stride_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_sn_ser_num_reg_1_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_sn_ser_num_reg_2_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_sriov_sup_page_size == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_sriov_vf_bar0_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_sriov_vf_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_sriov_vf_bar0_type == CTOP_CORE16_PF4_SRIOV_VF_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_sriov_vf_bar1_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_sriov_vf_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_sriov_vf_bar2_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_sriov_vf_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_sriov_vf_bar2_type == CTOP_CORE16_PF4_SRIOV_VF_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_sriov_vf_bar3_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_sriov_vf_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_sriov_vf_bar4_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_sriov_vf_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_sriov_vf_bar4_type == CTOP_CORE16_PF4_SRIOV_VF_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_sriov_vf_bar5_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_sriov_vf_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_sriov_vf_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_sriov_vf_offset_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_sriov_vf_offset_position_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_sriov_vf_stride_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_subclass_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_subsys_dev_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_subsys_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_tph_req_cap_int_vec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_tph_req_cap_int_vec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_tph_req_cap_st_table_loc_0_vfcomm_cs2 == CTOP_CORE16_PF4_IN_TPH_STRUCT_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_tph_req_cap_st_table_loc_1 == CTOP_CORE16_PF4_NOT_IN_MSIX_TABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_tph_req_cap_st_table_loc_1_vfcomm_cs2 == CTOP_CORE16_PF4_NOT_IN_MSIX_TABLE_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_tph_req_cap_st_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_tph_req_cap_st_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_tph_req_device_spec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf4_tph_req_device_spec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_acs_cap_acs_at_block == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_acs_cap_acs_direct_translated_p2p == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_acs_cap_acs_egress_ctrl_size == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_acs_cap_acs_p2p_cpl_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_acs_cap_acs_p2p_egress_control == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_acs_cap_acs_p2p_req_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_acs_cap_acs_src_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_acs_cap_acs_usp_forwarding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_aux_curr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_bar0_type == CTOP_CORE16_PF5_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_bar2_type == CTOP_CORE16_PF5_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_bar4_type == CTOP_CORE16_PF5_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_base_class_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_cardbus_cis_pointer == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_dsi == CTOP_CORE16_PF5_NOT_REQUIRED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_int_pin == CTOP_CORE16_PF5_INTA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_invalidate_q_depth == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_no_soft_rst == CTOP_CORE16_PF5_INTERNALLY_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_page_aligned_req == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_pasid_cap_execute_permission_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_pasid_cap_max_pasid_width == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_pasid_cap_privileged_mode_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_pci_msi_64_bit_addr_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_pci_msi_ext_data_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_pci_msi_ext_data_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_pci_msi_multiple_msg_cap == CTOP_CORE16_PF5_MSI_VEC_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_pci_msix_bir == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_pci_msix_pba == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_pci_msix_pba_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_pci_msix_table_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_pci_msix_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_pci_msix_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_pci_type0_bar0_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_pci_type0_bar0_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_pci_type0_bar1_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_pci_type0_bar1_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_pci_type0_bar2_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_pci_type0_bar2_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_pci_type0_bar3_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_pci_type0_bar3_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_pci_type0_bar4_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_pci_type0_bar4_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_pci_type0_bar5_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_pci_type0_bar5_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_pci_type0_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_pci_type0_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_pcie_cap_ep_l0s_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_pcie_cap_ep_l1_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_pcie_cap_ext_tag_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_pcie_cap_flr_cap == CTOP_CORE16_PF5_CAPABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_pcie_cap_l0s_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_pcie_cap_l1_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_pcie_cap_port_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_pcie_cap_slot_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_pme_support == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_program_interface == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_prs_outstanding_capacity == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_ras_des_cap_force_detect_lane == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_ras_des_cap_force_detect_lane_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_revision_id == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_rom_bar_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_shadow_sriov_vf_stride_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_sn_ser_num_reg_1_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_sn_ser_num_reg_2_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_sriov_sup_page_size == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_sriov_vf_bar0_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_sriov_vf_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_sriov_vf_bar0_type == CTOP_CORE16_PF5_SRIOV_VF_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_sriov_vf_bar1_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_sriov_vf_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_sriov_vf_bar2_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_sriov_vf_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_sriov_vf_bar2_type == CTOP_CORE16_PF5_SRIOV_VF_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_sriov_vf_bar3_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_sriov_vf_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_sriov_vf_bar4_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_sriov_vf_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_sriov_vf_bar4_type == CTOP_CORE16_PF5_SRIOV_VF_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_sriov_vf_bar5_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_sriov_vf_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_sriov_vf_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_sriov_vf_offset_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_sriov_vf_offset_position_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_sriov_vf_stride_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_subclass_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_subsys_dev_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_subsys_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_tph_req_cap_int_vec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_tph_req_cap_int_vec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_tph_req_cap_st_table_loc_0_vfcomm_cs2 == CTOP_CORE16_PF5_IN_TPH_STRUCT_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_tph_req_cap_st_table_loc_1 == CTOP_CORE16_PF5_NOT_IN_MSIX_TABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_tph_req_cap_st_table_loc_1_vfcomm_cs2 == CTOP_CORE16_PF5_NOT_IN_MSIX_TABLE_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_tph_req_cap_st_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_tph_req_cap_st_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_tph_req_device_spec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf5_tph_req_device_spec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_acs_cap_acs_at_block == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_acs_cap_acs_direct_translated_p2p == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_acs_cap_acs_egress_ctrl_size == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_acs_cap_acs_p2p_cpl_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_acs_cap_acs_p2p_egress_control == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_acs_cap_acs_p2p_req_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_acs_cap_acs_src_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_acs_cap_acs_usp_forwarding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_aux_curr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_bar0_type == CTOP_CORE16_PF6_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_bar2_type == CTOP_CORE16_PF6_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_bar4_type == CTOP_CORE16_PF6_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_base_class_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_cardbus_cis_pointer == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_dsi == CTOP_CORE16_PF6_NOT_REQUIRED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_int_pin == CTOP_CORE16_PF6_INTA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_invalidate_q_depth == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_no_soft_rst == CTOP_CORE16_PF6_INTERNALLY_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_page_aligned_req == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_pasid_cap_execute_permission_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_pasid_cap_max_pasid_width == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_pasid_cap_privileged_mode_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_pci_msi_64_bit_addr_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_pci_msi_ext_data_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_pci_msi_ext_data_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_pci_msi_multiple_msg_cap == CTOP_CORE16_PF6_MSI_VEC_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_pci_msix_bir == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_pci_msix_pba == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_pci_msix_pba_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_pci_msix_table_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_pci_msix_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_pci_msix_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_pci_type0_bar0_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_pci_type0_bar0_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_pci_type0_bar1_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_pci_type0_bar1_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_pci_type0_bar2_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_pci_type0_bar2_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_pci_type0_bar3_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_pci_type0_bar3_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_pci_type0_bar4_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_pci_type0_bar4_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_pci_type0_bar5_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_pci_type0_bar5_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_pci_type0_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_pci_type0_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_pcie_cap_ep_l0s_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_pcie_cap_ep_l1_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_pcie_cap_ext_tag_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_pcie_cap_flr_cap == CTOP_CORE16_PF6_CAPABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_pcie_cap_l0s_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_pcie_cap_l1_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_pcie_cap_port_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_pcie_cap_slot_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_pme_support == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_program_interface == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_prs_outstanding_capacity == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_ras_des_cap_force_detect_lane == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_ras_des_cap_force_detect_lane_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_revision_id == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_rom_bar_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_shadow_sriov_vf_stride_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_sn_ser_num_reg_1_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_sn_ser_num_reg_2_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_sriov_sup_page_size == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_sriov_vf_bar0_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_sriov_vf_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_sriov_vf_bar0_type == CTOP_CORE16_PF6_SRIOV_VF_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_sriov_vf_bar1_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_sriov_vf_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_sriov_vf_bar2_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_sriov_vf_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_sriov_vf_bar2_type == CTOP_CORE16_PF6_SRIOV_VF_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_sriov_vf_bar3_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_sriov_vf_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_sriov_vf_bar4_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_sriov_vf_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_sriov_vf_bar4_type == CTOP_CORE16_PF6_SRIOV_VF_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_sriov_vf_bar5_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_sriov_vf_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_sriov_vf_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_sriov_vf_offset_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_sriov_vf_offset_position_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_sriov_vf_stride_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_subclass_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_subsys_dev_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_subsys_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_tph_req_cap_int_vec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_tph_req_cap_int_vec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_tph_req_cap_st_table_loc_0_vfcomm_cs2 == CTOP_CORE16_PF6_IN_TPH_STRUCT_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_tph_req_cap_st_table_loc_1 == CTOP_CORE16_PF6_NOT_IN_MSIX_TABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_tph_req_cap_st_table_loc_1_vfcomm_cs2 == CTOP_CORE16_PF6_NOT_IN_MSIX_TABLE_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_tph_req_cap_st_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_tph_req_cap_st_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_tph_req_device_spec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf6_tph_req_device_spec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_acs_cap_acs_at_block == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_acs_cap_acs_direct_translated_p2p == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_acs_cap_acs_egress_ctrl_size == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_acs_cap_acs_p2p_cpl_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_acs_cap_acs_p2p_egress_control == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_acs_cap_acs_p2p_req_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_acs_cap_acs_src_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_acs_cap_acs_usp_forwarding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_aux_curr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_bar0_type == CTOP_CORE16_PF7_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_bar2_type == CTOP_CORE16_PF7_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_bar4_type == CTOP_CORE16_PF7_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_base_class_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_cardbus_cis_pointer == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_dsi == CTOP_CORE16_PF7_NOT_REQUIRED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_int_pin == CTOP_CORE16_PF7_INTA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_invalidate_q_depth == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_no_soft_rst == CTOP_CORE16_PF7_INTERNALLY_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_page_aligned_req == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_pasid_cap_execute_permission_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_pasid_cap_max_pasid_width == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_pasid_cap_privileged_mode_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_pci_msi_64_bit_addr_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_pci_msi_ext_data_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_pci_msi_ext_data_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_pci_msi_multiple_msg_cap == CTOP_CORE16_PF7_MSI_VEC_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_pci_msix_bir == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_pci_msix_pba == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_pci_msix_pba_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_pci_msix_table_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_pci_msix_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_pci_msix_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_pci_type0_bar0_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_pci_type0_bar0_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_pci_type0_bar1_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_pci_type0_bar1_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_pci_type0_bar2_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_pci_type0_bar2_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_pci_type0_bar3_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_pci_type0_bar3_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_pci_type0_bar4_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_pci_type0_bar4_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_pci_type0_bar5_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_pci_type0_bar5_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_pci_type0_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_pci_type0_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_pcie_cap_ep_l0s_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_pcie_cap_ep_l1_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_pcie_cap_ext_tag_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_pcie_cap_flr_cap == CTOP_CORE16_PF7_CAPABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_pcie_cap_l0s_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_pcie_cap_l1_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_pcie_cap_port_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_pcie_cap_slot_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_pme_support == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_program_interface == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_prs_outstanding_capacity == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_ras_des_cap_force_detect_lane == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_ras_des_cap_force_detect_lane_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_revision_id == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_rom_bar_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_shadow_sriov_vf_stride_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_sn_ser_num_reg_1_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_sn_ser_num_reg_2_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_sriov_sup_page_size == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_sriov_vf_bar0_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_sriov_vf_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_sriov_vf_bar0_type == CTOP_CORE16_PF7_SRIOV_VF_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_sriov_vf_bar1_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_sriov_vf_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_sriov_vf_bar2_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_sriov_vf_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_sriov_vf_bar2_type == CTOP_CORE16_PF7_SRIOV_VF_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_sriov_vf_bar3_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_sriov_vf_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_sriov_vf_bar4_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_sriov_vf_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_sriov_vf_bar4_type == CTOP_CORE16_PF7_SRIOV_VF_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_sriov_vf_bar5_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_sriov_vf_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_sriov_vf_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_sriov_vf_offset_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_sriov_vf_offset_position_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_sriov_vf_stride_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_subclass_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_subsys_dev_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_subsys_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_tph_req_cap_int_vec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_tph_req_cap_int_vec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_tph_req_cap_st_table_loc_0_vfcomm_cs2 == CTOP_CORE16_PF7_IN_TPH_STRUCT_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_tph_req_cap_st_table_loc_1 == CTOP_CORE16_PF7_NOT_IN_MSIX_TABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_tph_req_cap_st_table_loc_1_vfcomm_cs2 == CTOP_CORE16_PF7_NOT_IN_MSIX_TABLE_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_tph_req_cap_st_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_tph_req_cap_st_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_tph_req_device_spec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pf7_tph_req_device_spec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_pld_crs_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_rx_lane_flip_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_rxbuf_limit_bypass == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_shadow_select == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_test_in_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_tx_lane_flip_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_vf_select == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_drop_vendor0_msg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_drop_vendor1_msg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_ep_native == CTOP_CORE16_NATIVE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_link_rate == CTOP_CORE16_GEN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_maxpayload_size == CTOP_CORE16_MAX_PAYLOAD_1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_num_of_lanes == CTOP_CORE16_NUM_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf0_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf0_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf0_bar1_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf0_bar3_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf0_bar5_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf0_dlink_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf0_exvf_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf0_exvf_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf0_exvf_msix_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf0_exvf_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf0_exvf_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf0_io_decode == CTOP_CORE16_IO32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf0_ltr_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf0_msi_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf0_msix_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf0_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf0_prefetch_decode == CTOP_CORE16_PREF64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf0_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf0_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf0_sn_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf0_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf0_sriov_num_vf_non_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf0_sriov_vf_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf0_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf0_sriov_vf_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf0_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf0_sriov_vf_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf0_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf0_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf0_user_vsec_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf0_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf1_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf1_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf1_bar1_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf1_bar3_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf1_bar5_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf1_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf1_exvf_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf1_exvf_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf1_exvf_msix_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf1_exvf_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf1_exvf_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf1_msi_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf1_msix_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf1_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf1_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf1_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf1_sn_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf1_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf1_sriov_num_vf_non_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf1_sriov_vf_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf1_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf1_sriov_vf_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf1_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf1_sriov_vf_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf1_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf1_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf1_user_vsec_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf1_user_vsec_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf1_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf2_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf2_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf2_bar1_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf2_bar3_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf2_bar5_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf2_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf2_exvf_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf2_exvf_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf2_exvf_msix_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf2_exvf_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf2_exvf_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf2_msi_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf2_msix_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf2_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf2_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf2_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf2_sn_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf2_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf2_sriov_num_vf_non_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf2_sriov_vf_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf2_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf2_sriov_vf_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf2_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf2_sriov_vf_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf2_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf2_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf2_user_vsec_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf2_user_vsec_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf2_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf3_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf3_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf3_bar1_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf3_bar3_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf3_bar5_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf3_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf3_exvf_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf3_exvf_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf3_exvf_msix_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf3_exvf_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf3_exvf_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf3_msi_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf3_msix_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf3_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf3_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf3_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf3_sn_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf3_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf3_sriov_num_vf_non_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf3_sriov_vf_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf3_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf3_sriov_vf_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf3_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf3_sriov_vf_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf3_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf3_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf3_user_vsec_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf3_user_vsec_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf3_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf4_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf4_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf4_bar1_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf4_bar3_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf4_bar5_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf4_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf4_exvf_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf4_exvf_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf4_exvf_msix_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf4_exvf_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf4_exvf_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf4_msi_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf4_msix_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf4_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf4_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf4_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf4_sn_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf4_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf4_sriov_num_vf_non_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf4_sriov_vf_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf4_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf4_sriov_vf_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf4_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf4_sriov_vf_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf4_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf4_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf4_user_vsec_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf4_user_vsec_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf4_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf5_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf5_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf5_bar1_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf5_bar3_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf5_bar5_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf5_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf5_exvf_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf5_exvf_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf5_exvf_msix_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf5_exvf_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf5_exvf_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf5_msi_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf5_msix_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf5_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf5_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf5_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf5_sn_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf5_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf5_sriov_num_vf_non_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf5_sriov_vf_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf5_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf5_sriov_vf_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf5_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf5_sriov_vf_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf5_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf5_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf5_user_vsec_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf5_user_vsec_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf5_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf6_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf6_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf6_bar1_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf6_bar3_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf6_bar5_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf6_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf6_exvf_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf6_exvf_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf6_exvf_msix_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf6_exvf_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf6_exvf_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf6_msi_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf6_msix_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf6_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf6_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf6_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf6_sn_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf6_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf6_sriov_num_vf_non_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf6_sriov_vf_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf6_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf6_sriov_vf_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf6_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf6_sriov_vf_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf6_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf6_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf6_user_vsec_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf6_user_vsec_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf6_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf7_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf7_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf7_bar1_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf7_bar3_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf7_bar5_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf7_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf7_exvf_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf7_exvf_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf7_exvf_msix_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf7_exvf_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf7_exvf_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf7_msi_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf7_msix_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf7_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf7_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf7_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf7_sn_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf7_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf7_sriov_num_vf_non_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf7_sriov_vf_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf7_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf7_sriov_vf_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf7_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf7_sriov_vf_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf7_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf7_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf7_user_vsec_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf7_user_vsec_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pf7_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_phase23_txpreset == CTOP_CORE16_PRESET7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_phase23_txpreset_atg4 == CTOP_CORE16_GEN4_PRESET7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_pldclk_rate == CTOP_CORE16_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_ptm_autoupdate == CTOP_CORE16_AUTOUPDATE_10MS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_virtual_rp_ep_mode == CTOP_CORE16_EP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_vsec_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core16_vsec_select == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_cfg_bad_dllp_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_cfg_bad_tlp_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_cfg_corrected_internal_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_cfg_dl_protocol_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_cfg_ecrc_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_cfg_fc_protocol_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_cfg_mlf_tlp_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_cfg_rcvr_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_cfg_rcvr_overflow_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_cfg_replay_number_rollover_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_cfg_replay_timer_timeout_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_cfg_surprise_down_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_cfg_uncor_internal_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_clrhip_not_rst_sticky == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_cvp_data_compressed == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_cvp_data_encrypted == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_cvp_irq_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_cvp_jtag0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_cvp_jtag1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_cvp_jtag2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_cvp_jtag3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_cvp_user_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_ecrc_strip == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_gpio_irq == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_irq_misc_ctrl == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pcie_parity_bypass == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_acs_cap_acs_at_block == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_acs_cap_acs_direct_translated_p2p == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_acs_cap_acs_egress_ctrl_size == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_acs_cap_acs_p2p_cpl_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_acs_cap_acs_p2p_egress_control == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_acs_cap_acs_p2p_req_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_acs_cap_acs_src_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_acs_cap_acs_usp_forwarding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_adv_err_int_msg_num == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_ari_acs_fun_grp_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_auto_lane_flip_ctrl_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_aux_curr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_bar0_type == CTOP_CORE4_0_PF0_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_bar2_type == CTOP_CORE4_0_PF0_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_bar4_type == CTOP_CORE4_0_PF0_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_base_class_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_cardbus_cis_pointer == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_config_phy_tx_change == CTOP_CORE4_0_PF0_FULL_SWING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsi == CTOP_CORE4_0_PF0_NOT_REQUIRED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_16g_tx_preset0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_16g_tx_preset1 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_16g_tx_preset10 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_16g_tx_preset11 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_16g_tx_preset12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_16g_tx_preset13 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_16g_tx_preset14 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_16g_tx_preset15 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_16g_tx_preset2 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_16g_tx_preset3 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_16g_tx_preset4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_16g_tx_preset5 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_16g_tx_preset6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_16g_tx_preset7 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_16g_tx_preset8 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_16g_tx_preset9 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_rx_preset_hint0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_rx_preset_hint1 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_rx_preset_hint10 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_rx_preset_hint11 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_rx_preset_hint12 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_rx_preset_hint13 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_rx_preset_hint14 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_rx_preset_hint15 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_rx_preset_hint2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_rx_preset_hint3 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_rx_preset_hint4 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_rx_preset_hint5 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_rx_preset_hint6 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_rx_preset_hint7 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_rx_preset_hint8 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_rx_preset_hint9 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_tx_preset0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_tx_preset1 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_tx_preset10 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_tx_preset11 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_tx_preset12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_tx_preset13 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_tx_preset14 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_tx_preset15 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_tx_preset2 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_tx_preset3 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_tx_preset4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_tx_preset5 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_tx_preset6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_tx_preset7 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_tx_preset8 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_dsp_tx_preset9 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_eq_redo == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_eq_redo_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_fast_link_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_gen3_eq_pset_req_vec == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_gen3_eq_pset_req_vec_atg4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_int_pin == CTOP_CORE4_0_PF0_INTA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_invalidate_q_depth == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_loopback_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_no_soft_rst == CTOP_CORE4_0_PF0_INTERNALLY_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_page_aligned_req == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pasid_cap_execute_permission_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pasid_cap_max_pasid_width == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pasid_cap_privileged_mode_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pci_msi_64_bit_addr_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pci_msi_ext_data_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pci_msi_ext_data_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pci_msi_multiple_msg_cap == CTOP_CORE4_0_PF0_MSI_VEC_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pci_msix_bir == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pci_msix_pba == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pci_msix_pba_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pci_msix_table_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pci_msix_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pci_msix_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pci_type0_bar0_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pci_type0_bar0_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pci_type0_bar1_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pci_type0_bar1_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pci_type0_bar2_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pci_type0_bar2_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pci_type0_bar3_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pci_type0_bar3_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pci_type0_bar4_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pci_type0_bar4_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pci_type0_bar5_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pci_type0_bar5_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pci_type0_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pci_type0_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pcie_cap_attention_indicator == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pcie_cap_attention_indicator_button == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pcie_cap_crs_sw_visibility == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pcie_cap_electromech_interlock == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pcie_cap_ep_l0s_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pcie_cap_ep_l1_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pcie_cap_ext_tag_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pcie_cap_ext_tag_supp == CTOP_CORE4_0_PF0_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pcie_cap_flr_cap == CTOP_CORE4_0_PF0_CAPABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pcie_cap_hot_plug_capable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pcie_cap_hot_plug_surprise == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pcie_cap_l0s_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pcie_cap_l1_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pcie_cap_link_auto_bw_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pcie_cap_link_bw_man_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pcie_cap_mrl_sensor == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pcie_cap_no_cmd_cpl_support == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pcie_cap_phy_slot_num == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pcie_cap_port_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pcie_cap_power_controller == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pcie_cap_power_indicator == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pcie_cap_sel_deemphasis == CTOP_CORE4_0_PF0_MINUS_6DB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pcie_cap_slot_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pcie_cap_slot_power_limit_scale == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pcie_cap_slot_power_limit_value == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pcie_int_msg_num == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pcie_slot_imp == CTOP_CORE4_0_PF0_NOT_IMPLEMENTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_pme_support == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_program_interface == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_prs_outstanding_capacity == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_ras_des_cap_force_detect_lane == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_ras_des_cap_force_detect_lane_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_revision_id == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_rom_bar_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_rp_rom_bar_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_rp_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_sel_deemphasis == CTOP_CORE4_0_PF0_MINUS_3DB_CTL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_shadow_sriov_vf_stride_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_sn_ser_num_reg_1_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_sn_ser_num_reg_2_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_sriov_sup_page_size == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_sriov_vf_bar0_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_sriov_vf_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_sriov_vf_bar0_type == CTOP_CORE4_0_PF0_SRIOV_VF_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_sriov_vf_bar1_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_sriov_vf_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_sriov_vf_bar2_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_sriov_vf_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_sriov_vf_bar2_type == CTOP_CORE4_0_PF0_SRIOV_VF_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_sriov_vf_bar3_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_sriov_vf_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_sriov_vf_bar4_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_sriov_vf_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_sriov_vf_bar4_type == CTOP_CORE4_0_PF0_SRIOV_VF_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_sriov_vf_bar5_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_sriov_vf_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_sriov_vf_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_sriov_vf_offset_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_sriov_vf_offset_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_sriov_vf_stride_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_subclass_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_subsys_dev_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_subsys_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_tph_req_cap_int_vec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_tph_req_cap_int_vec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_tph_req_cap_st_table_loc_0_vfcomm_cs2 == CTOP_CORE4_0_PF0_IN_TPH_STRUCT_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_tph_req_cap_st_table_loc_1 == CTOP_CORE4_0_PF0_NOT_IN_MSIX_TABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_tph_req_cap_st_table_loc_1_vfcomm_cs2 == CTOP_CORE4_0_PF0_NOT_IN_MSIX_TABLE_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_tph_req_cap_st_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_tph_req_cap_st_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_tph_req_device_spec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_tph_req_device_spec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_16g_tx_preset0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_16g_tx_preset1 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_16g_tx_preset10 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_16g_tx_preset11 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_16g_tx_preset12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_16g_tx_preset13 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_16g_tx_preset14 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_16g_tx_preset15 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_16g_tx_preset2 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_16g_tx_preset3 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_16g_tx_preset4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_16g_tx_preset5 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_16g_tx_preset6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_16g_tx_preset7 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_16g_tx_preset8 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_16g_tx_preset9 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_rx_preset_hint0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_rx_preset_hint1 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_rx_preset_hint10 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_rx_preset_hint11 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_rx_preset_hint12 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_rx_preset_hint13 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_rx_preset_hint14 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_rx_preset_hint15 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_rx_preset_hint2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_rx_preset_hint3 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_rx_preset_hint4 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_rx_preset_hint5 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_rx_preset_hint6 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_rx_preset_hint7 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_rx_preset_hint8 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_rx_preset_hint9 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_tx_preset0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_tx_preset1 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_tx_preset10 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_tx_preset11 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_tx_preset12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_tx_preset13 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_tx_preset14 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_tx_preset15 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_tx_preset2 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_tx_preset3 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_tx_preset4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_tx_preset5 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_tx_preset6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_tx_preset7 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_tx_preset8 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pf0_usp_tx_preset9 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_pld_crs_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_rx_lane_flip_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_rxbuf_limit_bypass == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_shadow_select == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_test_in_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_tx_lane_flip_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_vf_select == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_drop_vendor0_msg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_drop_vendor1_msg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_ep_native == CTOP_CORE4_0_NATIVE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_link_rate == CTOP_CORE4_0_GEN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_maxpayload_size == CTOP_CORE4_0_MAX_PAYLOAD_1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_num_of_lanes == CTOP_CORE4_0_NUM_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf0_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf0_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf0_bar1_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf0_bar3_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf0_bar5_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf0_dlink_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf0_io_decode == CTOP_CORE4_0_IO32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf0_ltr_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf0_msi_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf0_msix_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf0_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf0_pl16g_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf0_prefetch_decode == CTOP_CORE4_0_PREF64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf0_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf0_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf0_sn_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf0_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf0_sriov_vf_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf0_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf0_sriov_vf_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf0_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf0_sriov_vf_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf0_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf0_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf0_user_vsec_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf1_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf1_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf1_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf1_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf2_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf2_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf2_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf2_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf3_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf3_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf3_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf3_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf4_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf4_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf4_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf4_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf5_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf5_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf5_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf5_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf6_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf6_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf6_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf6_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf7_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf7_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf7_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pf7_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_phase23_txpreset == CTOP_CORE4_0_PRESET7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_phase23_txpreset_atg4 == CTOP_CORE4_0_GEN4_PRESET7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_pldclk_rate == CTOP_CORE4_0_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_virtual_rp_ep_mode == CTOP_CORE4_0_EP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_vsec_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_0_vsec_select == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_cfg_bad_dllp_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_cfg_bad_tlp_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_cfg_corrected_internal_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_cfg_dl_protocol_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_cfg_ecrc_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_cfg_fc_protocol_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_cfg_mlf_tlp_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_cfg_rcvr_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_cfg_rcvr_overflow_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_cfg_replay_number_rollover_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_cfg_replay_timer_timeout_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_cfg_surprise_down_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_cfg_uncor_internal_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_clrhip_not_rst_sticky == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_cvp_data_compressed == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_cvp_data_encrypted == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_cvp_irq_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_cvp_jtag0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_cvp_jtag1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_cvp_jtag2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_cvp_jtag3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_cvp_user_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_ecrc_strip == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_gpio_irq == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_irq_misc_ctrl == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pcie_parity_bypass == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_acs_cap_acs_at_block == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_acs_cap_acs_direct_translated_p2p == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_acs_cap_acs_egress_ctrl_size == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_acs_cap_acs_p2p_cpl_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_acs_cap_acs_p2p_egress_control == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_acs_cap_acs_p2p_req_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_acs_cap_acs_src_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_acs_cap_acs_usp_forwarding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_adv_err_int_msg_num == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_ari_acs_fun_grp_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_auto_lane_flip_ctrl_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_aux_curr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_bar0_type == CTOP_CORE4_1_PF0_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_bar2_type == CTOP_CORE4_1_PF0_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_bar4_type == CTOP_CORE4_1_PF0_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_base_class_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_cardbus_cis_pointer == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_config_phy_tx_change == CTOP_CORE4_1_PF0_FULL_SWING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsi == CTOP_CORE4_1_PF0_NOT_REQUIRED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_16g_tx_preset0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_16g_tx_preset1 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_16g_tx_preset10 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_16g_tx_preset11 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_16g_tx_preset12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_16g_tx_preset13 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_16g_tx_preset14 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_16g_tx_preset15 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_16g_tx_preset2 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_16g_tx_preset3 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_16g_tx_preset4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_16g_tx_preset5 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_16g_tx_preset6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_16g_tx_preset7 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_16g_tx_preset8 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_16g_tx_preset9 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_rx_preset_hint0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_rx_preset_hint1 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_rx_preset_hint10 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_rx_preset_hint11 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_rx_preset_hint12 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_rx_preset_hint13 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_rx_preset_hint14 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_rx_preset_hint15 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_rx_preset_hint2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_rx_preset_hint3 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_rx_preset_hint4 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_rx_preset_hint5 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_rx_preset_hint6 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_rx_preset_hint7 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_rx_preset_hint8 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_rx_preset_hint9 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_tx_preset0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_tx_preset1 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_tx_preset10 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_tx_preset11 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_tx_preset12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_tx_preset13 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_tx_preset14 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_tx_preset15 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_tx_preset2 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_tx_preset3 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_tx_preset4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_tx_preset5 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_tx_preset6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_tx_preset7 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_tx_preset8 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_dsp_tx_preset9 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_eq_redo == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_eq_redo_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_fast_link_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_gen3_eq_pset_req_vec == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_gen3_eq_pset_req_vec_atg4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_int_pin == CTOP_CORE4_1_PF0_INTA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_invalidate_q_depth == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_loopback_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_no_soft_rst == CTOP_CORE4_1_PF0_INTERNALLY_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_page_aligned_req == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pasid_cap_execute_permission_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pasid_cap_max_pasid_width == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pasid_cap_privileged_mode_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pci_msi_64_bit_addr_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pci_msi_ext_data_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pci_msi_ext_data_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pci_msi_multiple_msg_cap == CTOP_CORE4_1_PF0_MSI_VEC_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pci_msix_bir == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pci_msix_pba == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pci_msix_pba_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pci_msix_table_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pci_msix_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pci_msix_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pci_type0_bar0_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pci_type0_bar0_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pci_type0_bar1_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pci_type0_bar1_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pci_type0_bar2_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pci_type0_bar2_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pci_type0_bar3_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pci_type0_bar3_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pci_type0_bar4_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pci_type0_bar4_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pci_type0_bar5_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pci_type0_bar5_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pci_type0_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pci_type0_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pcie_cap_attention_indicator == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pcie_cap_attention_indicator_button == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pcie_cap_crs_sw_visibility == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pcie_cap_electromech_interlock == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pcie_cap_ep_l0s_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pcie_cap_ep_l1_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pcie_cap_ext_tag_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pcie_cap_ext_tag_supp == CTOP_CORE4_1_PF0_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pcie_cap_flr_cap == CTOP_CORE4_1_PF0_CAPABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pcie_cap_hot_plug_capable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pcie_cap_hot_plug_surprise == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pcie_cap_l0s_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pcie_cap_l1_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pcie_cap_link_auto_bw_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pcie_cap_link_bw_man_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pcie_cap_mrl_sensor == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pcie_cap_no_cmd_cpl_support == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pcie_cap_phy_slot_num == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pcie_cap_port_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pcie_cap_power_controller == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pcie_cap_power_indicator == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pcie_cap_sel_deemphasis == CTOP_CORE4_1_PF0_MINUS_6DB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pcie_cap_slot_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pcie_cap_slot_power_limit_scale == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pcie_cap_slot_power_limit_value == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pcie_int_msg_num == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pcie_slot_imp == CTOP_CORE4_1_PF0_NOT_IMPLEMENTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_pme_support == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_program_interface == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_prs_outstanding_capacity == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_ras_des_cap_force_detect_lane == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_ras_des_cap_force_detect_lane_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_revision_id == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_rom_bar_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_rp_rom_bar_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_rp_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_sel_deemphasis == CTOP_CORE4_1_PF0_MINUS_3DB_CTL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_shadow_sriov_vf_stride_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_sn_ser_num_reg_1_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_sn_ser_num_reg_2_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_sriov_sup_page_size == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_sriov_vf_bar0_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_sriov_vf_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_sriov_vf_bar0_type == CTOP_CORE4_1_PF0_SRIOV_VF_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_sriov_vf_bar1_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_sriov_vf_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_sriov_vf_bar2_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_sriov_vf_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_sriov_vf_bar2_type == CTOP_CORE4_1_PF0_SRIOV_VF_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_sriov_vf_bar3_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_sriov_vf_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_sriov_vf_bar4_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_sriov_vf_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_sriov_vf_bar4_type == CTOP_CORE4_1_PF0_SRIOV_VF_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_sriov_vf_bar5_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_sriov_vf_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_sriov_vf_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_sriov_vf_offset_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_sriov_vf_offset_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_sriov_vf_stride_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_subclass_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_subsys_dev_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_subsys_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_tph_req_cap_int_vec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_tph_req_cap_int_vec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_tph_req_cap_st_table_loc_0_vfcomm_cs2 == CTOP_CORE4_1_PF0_IN_TPH_STRUCT_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_tph_req_cap_st_table_loc_1 == CTOP_CORE4_1_PF0_NOT_IN_MSIX_TABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_tph_req_cap_st_table_loc_1_vfcomm_cs2 == CTOP_CORE4_1_PF0_NOT_IN_MSIX_TABLE_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_tph_req_cap_st_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_tph_req_cap_st_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_tph_req_device_spec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_tph_req_device_spec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_16g_tx_preset0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_16g_tx_preset1 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_16g_tx_preset10 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_16g_tx_preset11 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_16g_tx_preset12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_16g_tx_preset13 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_16g_tx_preset14 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_16g_tx_preset15 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_16g_tx_preset2 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_16g_tx_preset3 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_16g_tx_preset4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_16g_tx_preset5 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_16g_tx_preset6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_16g_tx_preset7 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_16g_tx_preset8 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_16g_tx_preset9 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_rx_preset_hint0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_rx_preset_hint1 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_rx_preset_hint10 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_rx_preset_hint11 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_rx_preset_hint12 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_rx_preset_hint13 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_rx_preset_hint14 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_rx_preset_hint15 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_rx_preset_hint2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_rx_preset_hint3 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_rx_preset_hint4 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_rx_preset_hint5 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_rx_preset_hint6 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_rx_preset_hint7 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_rx_preset_hint8 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_rx_preset_hint9 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_tx_preset0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_tx_preset1 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_tx_preset10 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_tx_preset11 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_tx_preset12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_tx_preset13 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_tx_preset14 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_tx_preset15 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_tx_preset2 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_tx_preset3 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_tx_preset4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_tx_preset5 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_tx_preset6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_tx_preset7 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_tx_preset8 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pf0_usp_tx_preset9 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_pld_crs_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_rx_lane_flip_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_rxbuf_limit_bypass == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_shadow_select == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_test_in_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_tx_lane_flip_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_vf_select == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_drop_vendor0_msg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_drop_vendor1_msg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_ep_native == CTOP_CORE4_1_NATIVE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_link_rate == CTOP_CORE4_1_GEN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_maxpayload_size == CTOP_CORE4_1_MAX_PAYLOAD_1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_num_of_lanes == CTOP_CORE4_1_NUM_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf0_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf0_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf0_bar1_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf0_bar3_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf0_bar5_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf0_dlink_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf0_io_decode == CTOP_CORE4_1_IO32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf0_ltr_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf0_msi_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf0_msix_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf0_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf0_pl16g_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf0_prefetch_decode == CTOP_CORE4_1_PREF64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf0_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf0_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf0_sn_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf0_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf0_sriov_vf_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf0_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf0_sriov_vf_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf0_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf0_sriov_vf_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf0_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf0_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf0_user_vsec_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf1_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf1_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf1_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf1_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf2_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf2_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf2_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf2_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf3_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf3_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf3_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf3_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf4_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf4_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf4_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf4_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf5_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf5_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf5_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf5_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf6_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf6_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf6_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf6_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf7_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf7_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf7_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pf7_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_phase23_txpreset == CTOP_CORE4_1_PRESET7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_phase23_txpreset_atg4 == CTOP_CORE4_1_GEN4_PRESET7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_pldclk_rate == CTOP_CORE4_1_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_virtual_rp_ep_mode == CTOP_CORE4_1_EP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_vsec_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core4_1_vsec_select == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_cfg_bad_dllp_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_cfg_bad_tlp_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_cfg_corrected_internal_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_cfg_dl_protocol_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_cfg_ecrc_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_cfg_fc_protocol_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_cfg_mlf_tlp_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_cfg_ptm_local_clock_adj_lsb == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_cfg_ptm_local_clock_adj_msb == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_cfg_rcvr_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_cfg_rcvr_overflow_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_cfg_replay_number_rollover_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_cfg_replay_timer_timeout_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_cfg_surprise_down_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_cfg_uncor_internal_err_sts_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_clrhip_not_rst_sticky == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_cvp_data_compressed == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_cvp_data_encrypted == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_cvp_irq_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_cvp_jtag0 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_cvp_jtag1 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_cvp_jtag2 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_cvp_jtag3 == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_cvp_user_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_ecrc_strip == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_ats_pagealignreq_pf0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_ats_pagealignreq_pf1 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_ats_pagealignreq_pf2 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_ats_pagealignreq_pf3 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_ats_pagealignreq_pf4 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_ats_pagealignreq_pf5 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_ats_pagealignreq_pf6 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_ats_pagealignreq_pf7 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msix_tablesize_pf0 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msix_tablesize_pf1 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msix_tablesize_pf2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msix_tablesize_pf3 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msix_tablesize_pf4 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msix_tablesize_pf5 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msix_tablesize_pf6 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msix_tablesize_pf7 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msixpba_bir_pf0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msixpba_bir_pf1 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msixpba_bir_pf2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msixpba_bir_pf3 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msixpba_bir_pf4 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msixpba_bir_pf5 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msixpba_bir_pf6 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msixpba_bir_pf7 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msixpba_offset_pf0 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msixpba_offset_pf1 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msixpba_offset_pf2 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msixpba_offset_pf3 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msixpba_offset_pf4 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msixpba_offset_pf5 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msixpba_offset_pf6 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msixpba_offset_pf7 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msixtable_bir_pf0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msixtable_bir_pf1 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msixtable_bir_pf2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msixtable_bir_pf3 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msixtable_bir_pf4 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msixtable_bir_pf5 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msixtable_bir_pf6 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msixtable_bir_pf7 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msixtable_offset_pf0 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msixtable_offset_pf1 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msixtable_offset_pf2 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msixtable_offset_pf3 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msixtable_offset_pf4 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msixtable_offset_pf5 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msixtable_offset_pf6 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_msixtable_offset_pf7 == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_subsysid_pf0 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_subsysid_pf1 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_subsysid_pf2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_subsysid_pf3 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_subsysid_pf4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_subsysid_pf5 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_subsysid_pf6 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_subsysid_pf7 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_tph_sttablelocation_pf0 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_tph_sttablelocation_pf1 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_tph_sttablelocation_pf2 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_tph_sttablelocation_pf3 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_tph_sttablelocation_pf4 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_tph_sttablelocation_pf5 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_tph_sttablelocation_pf6 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_tph_sttablelocation_pf7 == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_tph_sttablesize_pf0 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_tph_sttablesize_pf1 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_tph_sttablesize_pf2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_tph_sttablesize_pf3 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_tph_sttablesize_pf4 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_tph_sttablesize_pf5 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_tph_sttablesize_pf6 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_exvf_tph_sttablesize_pf7 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_gpio_irq == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_irq_misc_ctrl == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_nonsriov_mode == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pcie_parity_bypass == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_acs_cap_acs_at_block == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_acs_cap_acs_direct_translated_p2p == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_acs_cap_acs_egress_ctrl_size == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_acs_cap_acs_p2p_cpl_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_acs_cap_acs_p2p_egress_control == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_acs_cap_acs_p2p_req_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_acs_cap_acs_src_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_acs_cap_acs_usp_forwarding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_adv_err_int_msg_num == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_ari_acs_fun_grp_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_auto_lane_flip_ctrl_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_aux_curr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_bar0_type == CTOP_CORE8_PF0_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_bar2_type == CTOP_CORE8_PF0_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_bar4_type == CTOP_CORE8_PF0_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_base_class_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_cardbus_cis_pointer == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_config_phy_tx_change == CTOP_CORE8_PF0_FULL_SWING
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsi == CTOP_CORE8_PF0_NOT_REQUIRED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_16g_tx_preset0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_16g_tx_preset1 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_16g_tx_preset10 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_16g_tx_preset11 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_16g_tx_preset12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_16g_tx_preset13 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_16g_tx_preset14 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_16g_tx_preset15 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_16g_tx_preset2 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_16g_tx_preset3 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_16g_tx_preset4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_16g_tx_preset5 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_16g_tx_preset6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_16g_tx_preset7 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_16g_tx_preset8 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_16g_tx_preset9 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_rx_preset_hint0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_rx_preset_hint1 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_rx_preset_hint10 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_rx_preset_hint11 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_rx_preset_hint12 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_rx_preset_hint13 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_rx_preset_hint14 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_rx_preset_hint15 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_rx_preset_hint2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_rx_preset_hint3 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_rx_preset_hint4 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_rx_preset_hint5 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_rx_preset_hint6 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_rx_preset_hint7 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_rx_preset_hint8 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_rx_preset_hint9 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_tx_preset0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_tx_preset1 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_tx_preset10 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_tx_preset11 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_tx_preset12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_tx_preset13 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_tx_preset14 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_tx_preset15 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_tx_preset2 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_tx_preset3 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_tx_preset4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_tx_preset5 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_tx_preset6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_tx_preset7 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_tx_preset8 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_dsp_tx_preset9 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_eq_redo == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_eq_redo_atg4 == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_fast_link_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_gen3_eq_pset_req_vec == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_gen3_eq_pset_req_vec_atg4 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_int_pin == CTOP_CORE8_PF0_INTA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_invalidate_q_depth == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_loopback_enable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_no_soft_rst == CTOP_CORE8_PF0_INTERNALLY_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_page_aligned_req == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pasid_cap_execute_permission_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pasid_cap_max_pasid_width == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pasid_cap_privileged_mode_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pci_msi_64_bit_addr_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pci_msi_ext_data_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pci_msi_ext_data_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pci_msi_multiple_msg_cap == CTOP_CORE8_PF0_MSI_VEC_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pci_msix_bir == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pci_msix_pba == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pci_msix_pba_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pci_msix_table_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pci_msix_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pci_msix_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pci_type0_bar0_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pci_type0_bar0_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pci_type0_bar1_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pci_type0_bar1_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pci_type0_bar2_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pci_type0_bar2_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pci_type0_bar3_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pci_type0_bar3_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pci_type0_bar4_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pci_type0_bar4_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pci_type0_bar5_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pci_type0_bar5_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pci_type0_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pci_type0_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pcie_cap_attention_indicator == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pcie_cap_attention_indicator_button == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pcie_cap_crs_sw_visibility == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pcie_cap_electromech_interlock == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pcie_cap_ep_l0s_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pcie_cap_ep_l1_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pcie_cap_ext_tag_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pcie_cap_ext_tag_supp == CTOP_CORE8_PF0_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pcie_cap_flr_cap == CTOP_CORE8_PF0_CAPABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pcie_cap_hot_plug_capable == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pcie_cap_hot_plug_surprise == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pcie_cap_l0s_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pcie_cap_l1_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pcie_cap_link_auto_bw_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pcie_cap_link_bw_man_int_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pcie_cap_mrl_sensor == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pcie_cap_no_cmd_cpl_support == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pcie_cap_phy_slot_num == 13'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pcie_cap_port_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pcie_cap_power_controller == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pcie_cap_power_indicator == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pcie_cap_sel_deemphasis == CTOP_CORE8_PF0_MINUS_6DB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pcie_cap_slot_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pcie_cap_slot_power_limit_scale == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pcie_cap_slot_power_limit_value == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pcie_int_msg_num == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pcie_slot_imp == CTOP_CORE8_PF0_NOT_IMPLEMENTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_pme_support == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_program_interface == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_prs_outstanding_capacity == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_ras_des_cap_force_detect_lane == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_ras_des_cap_force_detect_lane_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_revision_id == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_rom_bar_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_rp_rom_bar_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_rp_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_sel_deemphasis == CTOP_CORE8_PF0_MINUS_3DB_CTL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_shadow_sriov_vf_stride_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_sn_ser_num_reg_1_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_sn_ser_num_reg_2_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_sriov_sup_page_size == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_sriov_vf_bar0_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_sriov_vf_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_sriov_vf_bar0_type == CTOP_CORE8_PF0_SRIOV_VF_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_sriov_vf_bar1_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_sriov_vf_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_sriov_vf_bar2_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_sriov_vf_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_sriov_vf_bar2_type == CTOP_CORE8_PF0_SRIOV_VF_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_sriov_vf_bar3_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_sriov_vf_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_sriov_vf_bar4_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_sriov_vf_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_sriov_vf_bar4_type == CTOP_CORE8_PF0_SRIOV_VF_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_sriov_vf_bar5_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_sriov_vf_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_sriov_vf_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_sriov_vf_offset_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_sriov_vf_offset_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_sriov_vf_stride_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_subclass_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_subsys_dev_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_subsys_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_tph_req_cap_int_vec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_tph_req_cap_int_vec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_tph_req_cap_st_table_loc_0_vfcomm_cs2 == CTOP_CORE8_PF0_IN_TPH_STRUCT_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_tph_req_cap_st_table_loc_1 == CTOP_CORE8_PF0_NOT_IN_MSIX_TABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_tph_req_cap_st_table_loc_1_vfcomm_cs2 == CTOP_CORE8_PF0_NOT_IN_MSIX_TABLE_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_tph_req_cap_st_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_tph_req_cap_st_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_tph_req_device_spec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_tph_req_device_spec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_16g_tx_preset0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_16g_tx_preset1 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_16g_tx_preset10 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_16g_tx_preset11 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_16g_tx_preset12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_16g_tx_preset13 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_16g_tx_preset14 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_16g_tx_preset15 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_16g_tx_preset2 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_16g_tx_preset3 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_16g_tx_preset4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_16g_tx_preset5 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_16g_tx_preset6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_16g_tx_preset7 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_16g_tx_preset8 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_16g_tx_preset9 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_rx_preset_hint0 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_rx_preset_hint1 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_rx_preset_hint10 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_rx_preset_hint11 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_rx_preset_hint12 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_rx_preset_hint13 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_rx_preset_hint14 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_rx_preset_hint15 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_rx_preset_hint2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_rx_preset_hint3 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_rx_preset_hint4 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_rx_preset_hint5 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_rx_preset_hint6 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_rx_preset_hint7 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_rx_preset_hint8 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_rx_preset_hint9 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_tx_preset0 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_tx_preset1 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_tx_preset10 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_tx_preset11 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_tx_preset12 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_tx_preset13 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_tx_preset14 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_tx_preset15 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_tx_preset2 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_tx_preset3 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_tx_preset4 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_tx_preset5 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_tx_preset6 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_tx_preset7 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_tx_preset8 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf0_usp_tx_preset9 == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_acs_cap_acs_at_block == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_acs_cap_acs_direct_translated_p2p == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_acs_cap_acs_egress_ctrl_size == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_acs_cap_acs_p2p_cpl_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_acs_cap_acs_p2p_egress_control == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_acs_cap_acs_p2p_req_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_acs_cap_acs_src_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_acs_cap_acs_usp_forwarding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_aux_curr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_bar0_type == CTOP_CORE8_PF1_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_bar2_type == CTOP_CORE8_PF1_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_bar4_type == CTOP_CORE8_PF1_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_base_class_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_cardbus_cis_pointer == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_dsi == CTOP_CORE8_PF1_NOT_REQUIRED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_int_pin == CTOP_CORE8_PF1_INTA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_invalidate_q_depth == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_no_soft_rst == CTOP_CORE8_PF1_INTERNALLY_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_page_aligned_req == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pasid_cap_execute_permission_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pasid_cap_max_pasid_width == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pasid_cap_privileged_mode_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pci_msi_64_bit_addr_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pci_msi_ext_data_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pci_msi_ext_data_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pci_msi_multiple_msg_cap == CTOP_CORE8_PF1_MSI_VEC_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pci_msix_bir == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pci_msix_pba == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pci_msix_pba_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pci_msix_table_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pci_msix_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pci_msix_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pci_type0_bar0_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pci_type0_bar0_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pci_type0_bar1_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pci_type0_bar1_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pci_type0_bar2_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pci_type0_bar2_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pci_type0_bar3_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pci_type0_bar3_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pci_type0_bar4_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pci_type0_bar4_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pci_type0_bar5_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pci_type0_bar5_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pci_type0_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pci_type0_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pcie_cap_ep_l0s_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pcie_cap_ep_l1_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pcie_cap_ext_tag_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pcie_cap_ext_tag_supp == CTOP_CORE8_PF1_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pcie_cap_flr_cap == CTOP_CORE8_PF1_CAPABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pcie_cap_l0s_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pcie_cap_l1_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pcie_cap_port_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pcie_cap_slot_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_pme_support == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_program_interface == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_prs_outstanding_capacity == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_ras_des_cap_force_detect_lane == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_ras_des_cap_force_detect_lane_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_revision_id == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_rom_bar_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_shadow_sriov_vf_stride_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_sn_ser_num_reg_1_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_sn_ser_num_reg_2_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_sriov_sup_page_size == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_sriov_vf_bar0_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_sriov_vf_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_sriov_vf_bar0_type == CTOP_CORE8_PF1_SRIOV_VF_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_sriov_vf_bar1_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_sriov_vf_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_sriov_vf_bar2_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_sriov_vf_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_sriov_vf_bar2_type == CTOP_CORE8_PF1_SRIOV_VF_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_sriov_vf_bar3_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_sriov_vf_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_sriov_vf_bar4_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_sriov_vf_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_sriov_vf_bar4_type == CTOP_CORE8_PF1_SRIOV_VF_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_sriov_vf_bar5_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_sriov_vf_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_sriov_vf_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_sriov_vf_offset_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_sriov_vf_offset_position_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_sriov_vf_stride_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_subclass_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_subsys_dev_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_subsys_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_tph_req_cap_int_vec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_tph_req_cap_int_vec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_tph_req_cap_st_table_loc_0_vfcomm_cs2 == CTOP_CORE8_PF1_IN_TPH_STRUCT_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_tph_req_cap_st_table_loc_1 == CTOP_CORE8_PF1_NOT_IN_MSIX_TABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_tph_req_cap_st_table_loc_1_vfcomm_cs2 == CTOP_CORE8_PF1_NOT_IN_MSIX_TABLE_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_tph_req_cap_st_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_tph_req_cap_st_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_tph_req_device_spec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf1_tph_req_device_spec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_acs_cap_acs_at_block == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_acs_cap_acs_direct_translated_p2p == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_acs_cap_acs_egress_ctrl_size == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_acs_cap_acs_p2p_cpl_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_acs_cap_acs_p2p_egress_control == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_acs_cap_acs_p2p_req_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_acs_cap_acs_src_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_acs_cap_acs_usp_forwarding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_aux_curr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_bar0_type == CTOP_CORE8_PF2_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_bar2_type == CTOP_CORE8_PF2_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_bar4_type == CTOP_CORE8_PF2_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_base_class_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_cardbus_cis_pointer == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_dsi == CTOP_CORE8_PF2_NOT_REQUIRED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_int_pin == CTOP_CORE8_PF2_INTA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_invalidate_q_depth == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_no_soft_rst == CTOP_CORE8_PF2_INTERNALLY_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_page_aligned_req == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pasid_cap_execute_permission_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pasid_cap_max_pasid_width == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pasid_cap_privileged_mode_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pci_msi_64_bit_addr_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pci_msi_ext_data_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pci_msi_ext_data_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pci_msi_multiple_msg_cap == CTOP_CORE8_PF2_MSI_VEC_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pci_msix_bir == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pci_msix_pba == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pci_msix_pba_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pci_msix_table_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pci_msix_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pci_msix_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pci_type0_bar0_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pci_type0_bar0_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pci_type0_bar1_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pci_type0_bar1_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pci_type0_bar2_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pci_type0_bar2_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pci_type0_bar3_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pci_type0_bar3_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pci_type0_bar4_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pci_type0_bar4_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pci_type0_bar5_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pci_type0_bar5_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pci_type0_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pci_type0_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pcie_cap_ep_l0s_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pcie_cap_ep_l1_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pcie_cap_ext_tag_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pcie_cap_ext_tag_supp == CTOP_CORE8_PF2_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pcie_cap_flr_cap == CTOP_CORE8_PF2_CAPABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pcie_cap_l0s_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pcie_cap_l1_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pcie_cap_port_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pcie_cap_slot_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_pme_support == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_program_interface == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_prs_outstanding_capacity == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_ras_des_cap_force_detect_lane == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_ras_des_cap_force_detect_lane_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_revision_id == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_rom_bar_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_shadow_sriov_vf_stride_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_sn_ser_num_reg_1_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_sn_ser_num_reg_2_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_sriov_sup_page_size == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_sriov_vf_bar0_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_sriov_vf_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_sriov_vf_bar0_type == CTOP_CORE8_PF2_SRIOV_VF_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_sriov_vf_bar1_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_sriov_vf_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_sriov_vf_bar2_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_sriov_vf_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_sriov_vf_bar2_type == CTOP_CORE8_PF2_SRIOV_VF_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_sriov_vf_bar3_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_sriov_vf_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_sriov_vf_bar4_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_sriov_vf_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_sriov_vf_bar4_type == CTOP_CORE8_PF2_SRIOV_VF_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_sriov_vf_bar5_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_sriov_vf_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_sriov_vf_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_sriov_vf_offset_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_sriov_vf_offset_position_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_sriov_vf_stride_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_subclass_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_subsys_dev_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_subsys_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_tph_req_cap_int_vec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_tph_req_cap_int_vec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_tph_req_cap_st_table_loc_0_vfcomm_cs2 == CTOP_CORE8_PF2_IN_TPH_STRUCT_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_tph_req_cap_st_table_loc_1 == CTOP_CORE8_PF2_NOT_IN_MSIX_TABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_tph_req_cap_st_table_loc_1_vfcomm_cs2 == CTOP_CORE8_PF2_NOT_IN_MSIX_TABLE_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_tph_req_cap_st_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_tph_req_cap_st_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_tph_req_device_spec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf2_tph_req_device_spec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_acs_cap_acs_at_block == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_acs_cap_acs_direct_translated_p2p == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_acs_cap_acs_egress_ctrl_size == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_acs_cap_acs_p2p_cpl_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_acs_cap_acs_p2p_egress_control == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_acs_cap_acs_p2p_req_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_acs_cap_acs_src_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_acs_cap_acs_usp_forwarding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_aux_curr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_bar0_type == CTOP_CORE8_PF3_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_bar2_type == CTOP_CORE8_PF3_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_bar4_type == CTOP_CORE8_PF3_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_base_class_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_cardbus_cis_pointer == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_dsi == CTOP_CORE8_PF3_NOT_REQUIRED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_int_pin == CTOP_CORE8_PF3_INTA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_invalidate_q_depth == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_no_soft_rst == CTOP_CORE8_PF3_INTERNALLY_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_page_aligned_req == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pasid_cap_execute_permission_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pasid_cap_max_pasid_width == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pasid_cap_privileged_mode_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pci_msi_64_bit_addr_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pci_msi_ext_data_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pci_msi_ext_data_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pci_msi_multiple_msg_cap == CTOP_CORE8_PF3_MSI_VEC_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pci_msix_bir == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pci_msix_pba == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pci_msix_pba_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pci_msix_table_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pci_msix_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pci_msix_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pci_type0_bar0_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pci_type0_bar0_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pci_type0_bar1_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pci_type0_bar1_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pci_type0_bar2_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pci_type0_bar2_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pci_type0_bar3_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pci_type0_bar3_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pci_type0_bar4_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pci_type0_bar4_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pci_type0_bar5_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pci_type0_bar5_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pci_type0_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pci_type0_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pcie_cap_ep_l0s_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pcie_cap_ep_l1_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pcie_cap_ext_tag_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pcie_cap_ext_tag_supp == CTOP_CORE8_PF3_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pcie_cap_flr_cap == CTOP_CORE8_PF3_CAPABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pcie_cap_l0s_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pcie_cap_l1_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pcie_cap_port_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pcie_cap_slot_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_pme_support == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_program_interface == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_prs_outstanding_capacity == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_ras_des_cap_force_detect_lane == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_ras_des_cap_force_detect_lane_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_revision_id == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_rom_bar_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_shadow_sriov_vf_stride_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_sn_ser_num_reg_1_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_sn_ser_num_reg_2_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_sriov_sup_page_size == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_sriov_vf_bar0_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_sriov_vf_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_sriov_vf_bar0_type == CTOP_CORE8_PF3_SRIOV_VF_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_sriov_vf_bar1_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_sriov_vf_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_sriov_vf_bar2_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_sriov_vf_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_sriov_vf_bar2_type == CTOP_CORE8_PF3_SRIOV_VF_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_sriov_vf_bar3_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_sriov_vf_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_sriov_vf_bar4_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_sriov_vf_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_sriov_vf_bar4_type == CTOP_CORE8_PF3_SRIOV_VF_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_sriov_vf_bar5_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_sriov_vf_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_sriov_vf_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_sriov_vf_offset_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_sriov_vf_offset_position_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_sriov_vf_stride_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_subclass_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_subsys_dev_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_subsys_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_tph_req_cap_int_vec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_tph_req_cap_int_vec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_tph_req_cap_st_table_loc_0_vfcomm_cs2 == CTOP_CORE8_PF3_IN_TPH_STRUCT_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_tph_req_cap_st_table_loc_1 == CTOP_CORE8_PF3_NOT_IN_MSIX_TABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_tph_req_cap_st_table_loc_1_vfcomm_cs2 == CTOP_CORE8_PF3_NOT_IN_MSIX_TABLE_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_tph_req_cap_st_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_tph_req_cap_st_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_tph_req_device_spec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf3_tph_req_device_spec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_acs_cap_acs_at_block == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_acs_cap_acs_direct_translated_p2p == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_acs_cap_acs_egress_ctrl_size == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_acs_cap_acs_p2p_cpl_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_acs_cap_acs_p2p_egress_control == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_acs_cap_acs_p2p_req_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_acs_cap_acs_src_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_acs_cap_acs_usp_forwarding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_aux_curr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_bar0_type == CTOP_CORE8_PF4_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_bar2_type == CTOP_CORE8_PF4_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_bar4_type == CTOP_CORE8_PF4_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_base_class_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_cardbus_cis_pointer == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_dsi == CTOP_CORE8_PF4_NOT_REQUIRED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_int_pin == CTOP_CORE8_PF4_INTA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_invalidate_q_depth == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_no_soft_rst == CTOP_CORE8_PF4_INTERNALLY_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_page_aligned_req == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pasid_cap_execute_permission_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pasid_cap_max_pasid_width == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pasid_cap_privileged_mode_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pci_msi_64_bit_addr_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pci_msi_ext_data_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pci_msi_ext_data_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pci_msi_multiple_msg_cap == CTOP_CORE8_PF4_MSI_VEC_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pci_msix_bir == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pci_msix_pba == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pci_msix_pba_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pci_msix_table_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pci_msix_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pci_msix_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pci_type0_bar0_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pci_type0_bar0_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pci_type0_bar1_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pci_type0_bar1_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pci_type0_bar2_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pci_type0_bar2_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pci_type0_bar3_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pci_type0_bar3_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pci_type0_bar4_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pci_type0_bar4_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pci_type0_bar5_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pci_type0_bar5_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pci_type0_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pci_type0_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pcie_cap_ep_l0s_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pcie_cap_ep_l1_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pcie_cap_ext_tag_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pcie_cap_ext_tag_supp == CTOP_CORE8_PF4_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pcie_cap_flr_cap == CTOP_CORE8_PF4_CAPABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pcie_cap_l0s_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pcie_cap_l1_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pcie_cap_port_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pcie_cap_slot_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_pme_support == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_program_interface == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_prs_outstanding_capacity == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_ras_des_cap_force_detect_lane == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_ras_des_cap_force_detect_lane_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_revision_id == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_rom_bar_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_shadow_sriov_vf_stride_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_sn_ser_num_reg_1_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_sn_ser_num_reg_2_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_sriov_sup_page_size == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_sriov_vf_bar0_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_sriov_vf_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_sriov_vf_bar0_type == CTOP_CORE8_PF4_SRIOV_VF_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_sriov_vf_bar1_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_sriov_vf_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_sriov_vf_bar2_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_sriov_vf_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_sriov_vf_bar2_type == CTOP_CORE8_PF4_SRIOV_VF_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_sriov_vf_bar3_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_sriov_vf_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_sriov_vf_bar4_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_sriov_vf_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_sriov_vf_bar4_type == CTOP_CORE8_PF4_SRIOV_VF_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_sriov_vf_bar5_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_sriov_vf_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_sriov_vf_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_sriov_vf_offset_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_sriov_vf_offset_position_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_sriov_vf_stride_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_subclass_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_subsys_dev_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_subsys_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_tph_req_cap_int_vec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_tph_req_cap_int_vec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_tph_req_cap_st_table_loc_0_vfcomm_cs2 == CTOP_CORE8_PF4_IN_TPH_STRUCT_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_tph_req_cap_st_table_loc_1 == CTOP_CORE8_PF4_NOT_IN_MSIX_TABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_tph_req_cap_st_table_loc_1_vfcomm_cs2 == CTOP_CORE8_PF4_NOT_IN_MSIX_TABLE_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_tph_req_cap_st_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_tph_req_cap_st_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_tph_req_device_spec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf4_tph_req_device_spec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_acs_cap_acs_at_block == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_acs_cap_acs_direct_translated_p2p == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_acs_cap_acs_egress_ctrl_size == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_acs_cap_acs_p2p_cpl_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_acs_cap_acs_p2p_egress_control == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_acs_cap_acs_p2p_req_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_acs_cap_acs_src_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_acs_cap_acs_usp_forwarding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_aux_curr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_bar0_type == CTOP_CORE8_PF5_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_bar2_type == CTOP_CORE8_PF5_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_bar4_type == CTOP_CORE8_PF5_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_base_class_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_cardbus_cis_pointer == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_dsi == CTOP_CORE8_PF5_NOT_REQUIRED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_int_pin == CTOP_CORE8_PF5_INTA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_invalidate_q_depth == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_no_soft_rst == CTOP_CORE8_PF5_INTERNALLY_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_page_aligned_req == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pasid_cap_execute_permission_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pasid_cap_max_pasid_width == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pasid_cap_privileged_mode_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pci_msi_64_bit_addr_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pci_msi_ext_data_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pci_msi_ext_data_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pci_msi_multiple_msg_cap == CTOP_CORE8_PF5_MSI_VEC_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pci_msix_bir == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pci_msix_pba == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pci_msix_pba_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pci_msix_table_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pci_msix_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pci_msix_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pci_type0_bar0_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pci_type0_bar0_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pci_type0_bar1_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pci_type0_bar1_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pci_type0_bar2_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pci_type0_bar2_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pci_type0_bar3_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pci_type0_bar3_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pci_type0_bar4_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pci_type0_bar4_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pci_type0_bar5_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pci_type0_bar5_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pci_type0_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pci_type0_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pcie_cap_ep_l0s_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pcie_cap_ep_l1_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pcie_cap_ext_tag_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pcie_cap_ext_tag_supp == CTOP_CORE8_PF5_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pcie_cap_flr_cap == CTOP_CORE8_PF5_CAPABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pcie_cap_l0s_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pcie_cap_l1_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pcie_cap_port_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pcie_cap_slot_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_pme_support == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_program_interface == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_prs_outstanding_capacity == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_ras_des_cap_force_detect_lane == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_ras_des_cap_force_detect_lane_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_revision_id == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_rom_bar_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_shadow_sriov_vf_stride_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_sn_ser_num_reg_1_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_sn_ser_num_reg_2_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_sriov_sup_page_size == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_sriov_vf_bar0_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_sriov_vf_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_sriov_vf_bar0_type == CTOP_CORE8_PF5_SRIOV_VF_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_sriov_vf_bar1_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_sriov_vf_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_sriov_vf_bar2_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_sriov_vf_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_sriov_vf_bar2_type == CTOP_CORE8_PF5_SRIOV_VF_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_sriov_vf_bar3_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_sriov_vf_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_sriov_vf_bar4_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_sriov_vf_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_sriov_vf_bar4_type == CTOP_CORE8_PF5_SRIOV_VF_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_sriov_vf_bar5_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_sriov_vf_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_sriov_vf_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_sriov_vf_offset_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_sriov_vf_offset_position_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_sriov_vf_stride_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_subclass_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_subsys_dev_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_subsys_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_tph_req_cap_int_vec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_tph_req_cap_int_vec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_tph_req_cap_st_table_loc_0_vfcomm_cs2 == CTOP_CORE8_PF5_IN_TPH_STRUCT_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_tph_req_cap_st_table_loc_1 == CTOP_CORE8_PF5_NOT_IN_MSIX_TABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_tph_req_cap_st_table_loc_1_vfcomm_cs2 == CTOP_CORE8_PF5_NOT_IN_MSIX_TABLE_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_tph_req_cap_st_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_tph_req_cap_st_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_tph_req_device_spec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf5_tph_req_device_spec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_acs_cap_acs_at_block == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_acs_cap_acs_direct_translated_p2p == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_acs_cap_acs_egress_ctrl_size == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_acs_cap_acs_p2p_cpl_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_acs_cap_acs_p2p_egress_control == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_acs_cap_acs_p2p_req_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_acs_cap_acs_src_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_acs_cap_acs_usp_forwarding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_aux_curr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_bar0_type == CTOP_CORE8_PF6_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_bar2_type == CTOP_CORE8_PF6_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_bar4_type == CTOP_CORE8_PF6_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_base_class_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_cardbus_cis_pointer == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_dsi == CTOP_CORE8_PF6_NOT_REQUIRED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_int_pin == CTOP_CORE8_PF6_INTA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_invalidate_q_depth == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_no_soft_rst == CTOP_CORE8_PF6_INTERNALLY_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_page_aligned_req == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pasid_cap_execute_permission_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pasid_cap_max_pasid_width == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pasid_cap_privileged_mode_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pci_msi_64_bit_addr_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pci_msi_ext_data_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pci_msi_ext_data_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pci_msi_multiple_msg_cap == CTOP_CORE8_PF6_MSI_VEC_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pci_msix_bir == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pci_msix_pba == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pci_msix_pba_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pci_msix_table_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pci_msix_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pci_msix_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pci_type0_bar0_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pci_type0_bar0_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pci_type0_bar1_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pci_type0_bar1_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pci_type0_bar2_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pci_type0_bar2_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pci_type0_bar3_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pci_type0_bar3_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pci_type0_bar4_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pci_type0_bar4_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pci_type0_bar5_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pci_type0_bar5_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pci_type0_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pci_type0_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pcie_cap_ep_l0s_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pcie_cap_ep_l1_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pcie_cap_ext_tag_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pcie_cap_ext_tag_supp == CTOP_CORE8_PF6_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pcie_cap_flr_cap == CTOP_CORE8_PF6_CAPABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pcie_cap_l0s_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pcie_cap_l1_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pcie_cap_port_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pcie_cap_slot_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_pme_support == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_program_interface == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_prs_outstanding_capacity == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_ras_des_cap_force_detect_lane == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_ras_des_cap_force_detect_lane_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_revision_id == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_rom_bar_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_shadow_sriov_vf_stride_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_sn_ser_num_reg_1_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_sn_ser_num_reg_2_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_sriov_sup_page_size == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_sriov_vf_bar0_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_sriov_vf_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_sriov_vf_bar0_type == CTOP_CORE8_PF6_SRIOV_VF_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_sriov_vf_bar1_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_sriov_vf_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_sriov_vf_bar2_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_sriov_vf_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_sriov_vf_bar2_type == CTOP_CORE8_PF6_SRIOV_VF_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_sriov_vf_bar3_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_sriov_vf_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_sriov_vf_bar4_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_sriov_vf_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_sriov_vf_bar4_type == CTOP_CORE8_PF6_SRIOV_VF_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_sriov_vf_bar5_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_sriov_vf_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_sriov_vf_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_sriov_vf_offset_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_sriov_vf_offset_position_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_sriov_vf_stride_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_subclass_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_subsys_dev_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_subsys_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_tph_req_cap_int_vec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_tph_req_cap_int_vec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_tph_req_cap_st_table_loc_0_vfcomm_cs2 == CTOP_CORE8_PF6_IN_TPH_STRUCT_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_tph_req_cap_st_table_loc_1 == CTOP_CORE8_PF6_NOT_IN_MSIX_TABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_tph_req_cap_st_table_loc_1_vfcomm_cs2 == CTOP_CORE8_PF6_NOT_IN_MSIX_TABLE_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_tph_req_cap_st_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_tph_req_cap_st_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_tph_req_device_spec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf6_tph_req_device_spec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_acs_cap_acs_at_block == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_acs_cap_acs_direct_translated_p2p == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_acs_cap_acs_egress_ctrl_size == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_acs_cap_acs_p2p_cpl_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_acs_cap_acs_p2p_egress_control == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_acs_cap_acs_p2p_req_redirect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_acs_cap_acs_src_valid == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_acs_cap_acs_usp_forwarding == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_aux_curr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_bar0_type == CTOP_CORE8_PF7_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_bar2_type == CTOP_CORE8_PF7_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_bar4_type == CTOP_CORE8_PF7_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_base_class_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_cardbus_cis_pointer == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_dsi == CTOP_CORE8_PF7_NOT_REQUIRED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_int_pin == CTOP_CORE8_PF7_INTA
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_invalidate_q_depth == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_no_soft_rst == CTOP_CORE8_PF7_INTERNALLY_RESET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_page_aligned_req == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pasid_cap_execute_permission_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pasid_cap_max_pasid_width == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pasid_cap_privileged_mode_supported == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pci_msi_64_bit_addr_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pci_msi_ext_data_cap == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pci_msi_ext_data_en == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pci_msi_multiple_msg_cap == CTOP_CORE8_PF7_MSI_VEC_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pci_msix_bir == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pci_msix_pba == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pci_msix_pba_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pci_msix_table_offset == 29'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pci_msix_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pci_msix_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pci_type0_bar0_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pci_type0_bar0_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pci_type0_bar1_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pci_type0_bar1_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pci_type0_bar2_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pci_type0_bar2_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pci_type0_bar3_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pci_type0_bar3_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pci_type0_bar4_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pci_type0_bar4_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pci_type0_bar5_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pci_type0_bar5_mask_31_1 == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pci_type0_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pci_type0_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pcie_cap_ep_l0s_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pcie_cap_ep_l1_accpt_latency == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pcie_cap_ext_tag_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pcie_cap_ext_tag_supp == CTOP_CORE8_PF7_SUPPORTED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pcie_cap_flr_cap == CTOP_CORE8_PF7_CAPABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pcie_cap_l0s_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pcie_cap_l1_exit_latency_commclk_dis == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pcie_cap_port_num == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pcie_cap_slot_clk_config == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_pme_support == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_program_interface == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_prs_outstanding_capacity == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_ras_des_cap_force_detect_lane == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_ras_des_cap_force_detect_lane_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_revision_id == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_rom_bar_enabled == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_rom_mask == 21'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_shadow_sriov_vf_stride_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_sn_ser_num_reg_1_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_sn_ser_num_reg_2_dw == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_sriov_sup_page_size == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_sriov_vf_bar0_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_sriov_vf_bar0_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_sriov_vf_bar0_type == CTOP_CORE8_PF7_SRIOV_VF_BAR0_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_sriov_vf_bar1_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_sriov_vf_bar1_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_sriov_vf_bar2_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_sriov_vf_bar2_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_sriov_vf_bar2_type == CTOP_CORE8_PF7_SRIOV_VF_BAR2_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_sriov_vf_bar3_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_sriov_vf_bar3_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_sriov_vf_bar4_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_sriov_vf_bar4_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_sriov_vf_bar4_type == CTOP_CORE8_PF7_SRIOV_VF_BAR4_MEM32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_sriov_vf_bar5_mask == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_sriov_vf_bar5_prefetch == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_sriov_vf_device_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_sriov_vf_offset_ari_cs2 == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_sriov_vf_offset_position_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_sriov_vf_stride_nonari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_subclass_code == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_subsys_dev_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_subsys_vendor_id == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_tph_req_cap_int_vec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_tph_req_cap_int_vec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_tph_req_cap_st_table_loc_0_vfcomm_cs2 == CTOP_CORE8_PF7_IN_TPH_STRUCT_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_tph_req_cap_st_table_loc_1 == CTOP_CORE8_PF7_NOT_IN_MSIX_TABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_tph_req_cap_st_table_loc_1_vfcomm_cs2 == CTOP_CORE8_PF7_NOT_IN_MSIX_TABLE_VF
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_tph_req_cap_st_table_size == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_tph_req_cap_st_table_size_vfcomm_cs2 == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_tph_req_device_spec == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pf7_tph_req_device_spec_vfcomm_cs2 == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_pld_crs_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_powerdown_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_rx_lane_flip_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_rxbuf_limit_bypass == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_shadow_select == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_test_in_override == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_tx_lane_flip_en == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_vf_select == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_drop_vendor0_msg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_drop_vendor1_msg == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_ep_native == CTOP_CORE8_NATIVE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_link_rate == CTOP_CORE8_GEN3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_maxpayload_size == CTOP_CORE8_MAX_PAYLOAD_1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_num_of_lanes == CTOP_CORE8_NUM_16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf0_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf0_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf0_bar1_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf0_bar3_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf0_bar5_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf0_dlink_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf0_exvf_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf0_exvf_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf0_exvf_msix_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf0_exvf_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf0_exvf_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf0_io_decode == CTOP_CORE8_IO32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf0_ltr_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf0_msi_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf0_msix_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf0_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf0_prefetch_decode == CTOP_CORE8_PREF64
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf0_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf0_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf0_sn_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf0_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf0_sriov_num_vf_non_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf0_sriov_vf_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf0_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf0_sriov_vf_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf0_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf0_sriov_vf_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf0_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf0_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf0_user_vsec_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf0_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf1_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf1_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf1_bar1_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf1_bar3_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf1_bar5_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf1_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf1_exvf_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf1_exvf_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf1_exvf_msix_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf1_exvf_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf1_exvf_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf1_msi_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf1_msix_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf1_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf1_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf1_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf1_sn_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf1_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf1_sriov_num_vf_non_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf1_sriov_vf_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf1_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf1_sriov_vf_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf1_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf1_sriov_vf_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf1_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf1_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf1_user_vsec_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf1_user_vsec_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf1_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf2_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf2_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf2_bar1_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf2_bar3_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf2_bar5_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf2_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf2_exvf_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf2_exvf_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf2_exvf_msix_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf2_exvf_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf2_exvf_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf2_msi_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf2_msix_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf2_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf2_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf2_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf2_sn_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf2_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf2_sriov_num_vf_non_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf2_sriov_vf_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf2_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf2_sriov_vf_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf2_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf2_sriov_vf_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf2_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf2_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf2_user_vsec_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf2_user_vsec_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf2_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf3_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf3_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf3_bar1_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf3_bar3_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf3_bar5_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf3_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf3_exvf_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf3_exvf_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf3_exvf_msix_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf3_exvf_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf3_exvf_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf3_msi_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf3_msix_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf3_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf3_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf3_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf3_sn_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf3_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf3_sriov_num_vf_non_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf3_sriov_vf_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf3_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf3_sriov_vf_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf3_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf3_sriov_vf_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf3_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf3_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf3_user_vsec_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf3_user_vsec_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf3_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf4_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf4_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf4_bar1_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf4_bar3_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf4_bar5_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf4_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf4_exvf_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf4_exvf_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf4_exvf_msix_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf4_exvf_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf4_exvf_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf4_msi_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf4_msix_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf4_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf4_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf4_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf4_sn_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf4_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf4_sriov_num_vf_non_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf4_sriov_vf_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf4_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf4_sriov_vf_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf4_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf4_sriov_vf_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf4_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf4_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf4_user_vsec_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf4_user_vsec_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf4_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf5_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf5_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf5_bar1_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf5_bar3_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf5_bar5_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf5_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf5_exvf_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf5_exvf_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf5_exvf_msix_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf5_exvf_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf5_exvf_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf5_msi_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf5_msix_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf5_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf5_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf5_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf5_sn_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf5_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf5_sriov_num_vf_non_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf5_sriov_vf_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf5_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf5_sriov_vf_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf5_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf5_sriov_vf_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf5_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf5_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf5_user_vsec_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf5_user_vsec_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf5_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf6_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf6_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf6_bar1_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf6_bar3_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf6_bar5_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf6_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf6_exvf_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf6_exvf_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf6_exvf_msix_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf6_exvf_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf6_exvf_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf6_msi_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf6_msix_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf6_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf6_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf6_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf6_sn_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf6_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf6_sriov_num_vf_non_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf6_sriov_vf_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf6_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf6_sriov_vf_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf6_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf6_sriov_vf_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf6_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf6_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf6_user_vsec_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf6_user_vsec_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf6_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf7_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf7_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf7_bar1_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf7_bar3_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf7_bar5_mask_bit0 == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf7_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf7_exvf_acs_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf7_exvf_ats_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf7_exvf_msix_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf7_exvf_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf7_exvf_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf7_msi_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf7_msix_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf7_pasid_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf7_prs_ext_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf7_ras_des_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf7_sn_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf7_sriov_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf7_sriov_num_vf_non_ari == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf7_sriov_vf_bar0_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf7_sriov_vf_bar1_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf7_sriov_vf_bar2_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf7_sriov_vf_bar3_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf7_sriov_vf_bar4_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf7_sriov_vf_bar5_enabled == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf7_tph_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf7_user_vsec_cap_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf7_user_vsec_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pf7_virtio_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_phase23_txpreset == CTOP_CORE8_PRESET7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_phase23_txpreset_atg4 == CTOP_CORE8_GEN4_PRESET7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_pldclk_rate == CTOP_CORE8_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_ptm_autoupdate == CTOP_CORE8_AUTOUPDATE_10MS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_virtual_rp_ep_mode == CTOP_CORE8_EP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_vsec_next_offset == 12'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_core8_vsec_select == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_ecc_ctrl_bypass_ecc_all_aib_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_ecc_ctrl_clr_stat_n_attr == CTOP_CTRLTOP_ECC_CTRL_CLR_STAT_N_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_ecc_ctrl_ecc_mask_attr == 24'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_pctrl_port_x16_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_pctrl_port_x4_0_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_pctrl_port_x4_1_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_pctrl_port_x8_attr == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_pctrl_rate_x16_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_pctrl_rate_x4_0_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_pctrl_rate_x4_1_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_pctrl_rate_x8_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_powerdown_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_arb_ctrl_k_hrc_arb_disable_attr == CTOP_CTRLTOP_R_HRC_ARB_CTRL_K_HRC_ARB_DISABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_arb_ctrl_k_hrc_arb_timeslot_interval_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_bp_ctrl_x16_bypass_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_bp_ctrl_x16_platform_rst_req_attr == CTOP_CTRLTOP_R_HRC_BP_CTRL_X16_PLATFORM_RST_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_bp_ctrl_x16_rst_cold_n_attr == CTOP_CTRLTOP_R_HRC_BP_CTRL_X16_RST_COLD_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_bp_ctrl_x16_rst_n_attr == CTOP_CTRLTOP_R_HRC_BP_CTRL_X16_RST_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_bp_ctrl_x16_rst_perst_n_attr == CTOP_CTRLTOP_R_HRC_BP_CTRL_X16_RST_PERST_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_bp_ctrl_x16_rst_pldclrhip_n_attr == CTOP_CTRLTOP_R_HRC_BP_CTRL_X16_RST_PLDCLRHIP_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_bp_ctrl_x4_0_bypass_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_bp_ctrl_x4_0_platform_rst_req_attr == CTOP_CTRLTOP_R_HRC_BP_CTRL_X4_0_PLATFORM_RST_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_bp_ctrl_x4_0_rst_cold_n_attr == CTOP_CTRLTOP_R_HRC_BP_CTRL_X4_0_RST_COLD_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_bp_ctrl_x4_0_rst_n_attr == CTOP_CTRLTOP_R_HRC_BP_CTRL_X4_0_RST_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_bp_ctrl_x4_0_rst_perst_n_attr == CTOP_CTRLTOP_R_HRC_BP_CTRL_X4_0_RST_PERST_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_bp_ctrl_x4_0_rst_pldclrhip_n_attr == CTOP_CTRLTOP_R_HRC_BP_CTRL_X4_0_RST_PLDCLRHIP_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_bp_ctrl_x4_1_bypass_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_bp_ctrl_x4_1_platform_rst_req_attr == CTOP_CTRLTOP_R_HRC_BP_CTRL_X4_1_PLATFORM_RST_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_bp_ctrl_x4_1_rst_cold_n_attr == CTOP_CTRLTOP_R_HRC_BP_CTRL_X4_1_RST_COLD_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_bp_ctrl_x4_1_rst_n_attr == CTOP_CTRLTOP_R_HRC_BP_CTRL_X4_1_RST_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_bp_ctrl_x4_1_rst_perst_n_attr == CTOP_CTRLTOP_R_HRC_BP_CTRL_X4_1_RST_PERST_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_bp_ctrl_x4_1_rst_pldclrhip_n_attr == CTOP_CTRLTOP_R_HRC_BP_CTRL_X4_1_RST_PLDCLRHIP_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_bp_ctrl_x8_bypass_mode_attr == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_bp_ctrl_x8_platform_rst_req_attr == CTOP_CTRLTOP_R_HRC_BP_CTRL_X8_PLATFORM_RST_REQ_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_bp_ctrl_x8_rst_cold_n_attr == CTOP_CTRLTOP_R_HRC_BP_CTRL_X8_RST_COLD_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_bp_ctrl_x8_rst_n_attr == CTOP_CTRLTOP_R_HRC_BP_CTRL_X8_RST_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_bp_ctrl_x8_rst_perst_n_attr == CTOP_CTRLTOP_R_HRC_BP_CTRL_X8_RST_PERST_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_bp_ctrl_x8_rst_pldclrhip_n_attr == CTOP_CTRLTOP_R_HRC_BP_CTRL_X8_RST_PLDCLRHIP_N_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_bp_pcs_ctrl_pipeb_a_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_bp_pcs_ctrl_por_b_a_attr == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_rst_ctrl_k_hrc_pin_perst_is_full_rst_attr == CTOP_CTRLTOP_R_HRC_RST_CTRL_K_HRC_PIN_PERST_IS_FULL_RST_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_stagger_ctrl_k_hrc_phy_stagger_disable_attr == CTOP_CTRLTOP_R_HRC_STAGGER_CTRL_K_HRC_PHY_STAGGER_DISABLE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_top_ctrl_k_hrc_dw16_perstn_overwrite_attr == CTOP_CTRLTOP_R_HRC_TOP_CTRL_K_HRC_DW16_PERSTN_OVERWRITE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_top_ctrl_k_hrc_dw16_perstn_overwrite_shadow_attr == CTOP_CTRLTOP_R_HRC_TOP_CTRL_K_HRC_DW16_PERSTN_OVERWRITE_SHADOW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_top_ctrl_k_hrc_dw40_perstn_overwrite_attr == CTOP_CTRLTOP_R_HRC_TOP_CTRL_K_HRC_DW40_PERSTN_OVERWRITE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_top_ctrl_k_hrc_dw40_perstn_overwrite_shadow_attr == CTOP_CTRLTOP_R_HRC_TOP_CTRL_K_HRC_DW40_PERSTN_OVERWRITE_SHADOW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_top_ctrl_k_hrc_dw41_perstn_overwrite_attr == CTOP_CTRLTOP_R_HRC_TOP_CTRL_K_HRC_DW41_PERSTN_OVERWRITE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_top_ctrl_k_hrc_dw41_perstn_overwrite_shadow_attr == CTOP_CTRLTOP_R_HRC_TOP_CTRL_K_HRC_DW41_PERSTN_OVERWRITE_SHADOW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_top_ctrl_k_hrc_dw8_perstn_overwrite_attr == CTOP_CTRLTOP_R_HRC_TOP_CTRL_K_HRC_DW8_PERSTN_OVERWRITE_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ctrltop_r_hrc_top_ctrl_k_hrc_dw8_perstn_overwrite_shadow_attr == CTOP_CTRLTOP_R_HRC_TOP_CTRL_K_HRC_DW8_PERSTN_OVERWRITE_SHADOW_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_ippwrmod_freq == CTOP_CLK1G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_virtual_pcie_rate == CTOP_PCIE_GEN4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_virtual_ptm == CTOP_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_virtual_x16_perst_sel == CTOP_CMN_HARD_X16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_virtual_x40_perst_sel == CTOP_CMN_HARD_X40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_virtual_x41_perst_sel == CTOP_CMN_HARD_X41
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ctop_virtual_x8_perst_sel == CTOP_CMN_HARD_X8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.dfd_enable == DFD_IS_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.location == PCIE0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.pcie_cvp_attr == PCIE_CVP_ATTR_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.pcie_gen_capable == GEN4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.pcie_hw_decode_attr == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.pcie_use_pin_perstn_attr == PCIE_USE_PIN_PERSTN_ATTR
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ptop_pcslane0_pctrl_srisenable_attr == PTOP_PCSLANE0_PCTRL_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ptop_pcslane10_pctrl_srisenable_attr == PTOP_PCSLANE10_PCTRL_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ptop_pcslane11_pctrl_srisenable_attr == PTOP_PCSLANE11_PCTRL_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ptop_pcslane12_pctrl_srisenable_attr == PTOP_PCSLANE12_PCTRL_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ptop_pcslane13_pctrl_srisenable_attr == PTOP_PCSLANE13_PCTRL_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ptop_pcslane14_pctrl_srisenable_attr == PTOP_PCSLANE14_PCTRL_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ptop_pcslane15_pctrl_srisenable_attr == PTOP_PCSLANE15_PCTRL_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ptop_pcslane1_pctrl_srisenable_attr == PTOP_PCSLANE1_PCTRL_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ptop_pcslane2_pctrl_srisenable_attr == PTOP_PCSLANE2_PCTRL_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ptop_pcslane3_pctrl_srisenable_attr == PTOP_PCSLANE3_PCTRL_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ptop_pcslane4_pctrl_srisenable_attr == PTOP_PCSLANE4_PCTRL_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ptop_pcslane5_pctrl_srisenable_attr == PTOP_PCSLANE5_PCTRL_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ptop_pcslane6_pctrl_srisenable_attr == PTOP_PCSLANE6_PCTRL_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ptop_pcslane7_pctrl_srisenable_attr == PTOP_PCSLANE7_PCTRL_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ptop_pcslane8_pctrl_srisenable_attr == PTOP_PCSLANE8_PCTRL_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.ptop_pcslane9_pctrl_srisenable_attr == PTOP_PCSLANE9_PCTRL_SRISENABLE_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.topology == PCIE_X16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.virtual_port_type == EP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.virtual_powerdown_mode == POWER_UP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.virtual_sim_mode == DISABLE_VSIM_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.virtual_sris_enable == DISABLE_SRIS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.virtual_sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_pcie[0].bb.virtual_tlp_bypass_en == ENABLE_TLBP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[0].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[0].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[0].refclk_link_net_id == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[0].bb.c0_counter == 11'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[0].bb.c0_output_enable == C0_OUTPUT_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[0].bb.c1_counter == 11'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[0].bb.c1_output_enable == C1_OUTPUT_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[0].bb.c2_counter == 11'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[0].bb.c2_output_enable == C2_OUTPUT_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[0].bb.dts_ctrl_f_en_attr == DTS_CTRL_F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[0].bb.eth_flux_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[0].bb.ethernet_preset == ETHERNET_FREQ_OTHER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[0].bb.f_out_c0_hz == 36'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[0].bb.f_out_c1_hz == 36'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[0].bb.f_out_c2_hz == 36'd250000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[0].bb.f_pfd_hz == 36'd31250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[0].bb.f_ref_hz == 36'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[0].bb.f_vco_hz == 36'd4500000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[0].bb.fractional_enable == FRACTIONAL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[0].bb.location == SYS_PLL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[0].bb.m_counter == 10'd144
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[0].bb.n_counter == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[0].bb.pcie_preset == PCIE_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[0].bb.primary_dfd_power_off_attr == PRIMARY_DFD_POWER_OFF_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[0].bb.primary_use == ETHERNET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[0].bb.refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[0].bb.sup_mode == ADVANCED_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[1].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[1].pll_link_net_id == 32'd3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[1].refclk_link_net_id == 32'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[1].bb.c0_counter == 11'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[1].bb.c0_output_enable == C0_OUTPUT_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[1].bb.c1_counter == 11'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[1].bb.c1_output_enable == C1_OUTPUT_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[1].bb.c2_counter == 11'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[1].bb.c2_output_enable == C2_OUTPUT_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[1].bb.dts_ctrl_f_en_attr == DTS_CTRL_F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[1].bb.eth_flux_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[1].bb.ethernet_preset == ETHERNET_FREQ_OTHER
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[1].bb.f_out_c0_hz == 36'd900000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[1].bb.f_out_c1_hz == 36'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[1].bb.f_out_c2_hz == 36'd250000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[1].bb.f_pfd_hz == 36'd31250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[1].bb.f_ref_hz == 36'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[1].bb.f_vco_hz == 36'd4500000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[1].bb.fractional_enable == FRACTIONAL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[1].bb.location == SYS_PLL_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[1].bb.m_counter == 10'd144
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[1].bb.n_counter == 5'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[1].bb.pcie_preset == PCIE_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[1].bb.primary_dfd_power_off_attr == PRIMARY_DFD_POWER_OFF_ATTR_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[1].bb.primary_use == ETHERNET
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[1].bb.refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[1].bb.sup_mode == ADVANCED_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[2].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[2].pll_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[2].refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[2].bb.c0_counter == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[2].bb.c0_output_enable == C0_OUTPUT_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[2].bb.c1_counter == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[2].bb.c1_output_enable == C1_OUTPUT_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[2].bb.c2_counter == 11'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[2].bb.c2_output_enable == C2_OUTPUT_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[2].bb.dts_ctrl_f_en_attr == DTS_CTRL_F_EN_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[2].bb.eth_flux_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[2].bb.ethernet_preset == ETHERNET_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[2].bb.f_out_c0_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[2].bb.f_out_c1_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[2].bb.f_out_c2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[2].bb.f_pfd_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[2].bb.f_ref_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[2].bb.f_vco_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[2].bb.fractional_enable == FRACTIONAL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[2].bb.location == SYS_PLL_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[2].bb.m_counter == 10'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[2].bb.n_counter == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[2].bb.pcie_preset == PCIE_UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[2].bb.primary_dfd_power_off_attr == PRIMARY_DFD_POWER_OFF_ATTR_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[2].bb.primary_use == UNUSED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[2].bb.refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_system_pll[2].bb.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[0].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[0].passthru_refclkin_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[0].refclk_link_net_id == 32'd4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[0].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[0].bb.f_fastest_reconfig_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[0].bb.location == UX_REFCLK3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[0].bb.passthru_clk_type == PASSTHRU_PAD2CMOS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[0].bb.refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[0].bb.refclk_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[0].bb.refclk_reconfig_span == REFCLK_RECONFIG_SPAN_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[0].bb.syspll_refclk_output_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[1].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[1].passthru_refclkin_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[1].refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[1].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[1].bb.f_fastest_reconfig_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[1].bb.location == UX_REFCLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[1].bb.passthru_clk_type == PASSTHRU_PAD2CMOS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[1].bb.refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[1].bb.refclk_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[1].bb.refclk_reconfig_span == REFCLK_RECONFIG_SPAN_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[1].bb.syspll_refclk_output_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[2].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[2].passthru_refclkin_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[2].refclk_link_net_id == 32'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[2].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[2].bb.f_fastest_reconfig_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[2].bb.location == UX_REFCLK2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[2].bb.passthru_clk_type == PASSTHRU_PAD2CMOS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[2].bb.refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[2].bb.refclk_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[2].bb.refclk_reconfig_span == REFCLK_RECONFIG_SPAN_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[2].bb.syspll_refclk_output_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[3].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[3].passthru_refclkin_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[3].refclk_link_net_id == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[3].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[3].bb.f_fastest_reconfig_refclk_hz == 40'd800000001
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[3].bb.location == UX_REFCLK4
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[3].bb.passthru_clk_type == PASSTHRU_PAD2CMOS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[3].bb.refclk_available_at_poweron == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[3].bb.refclk_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[3].bb.refclk_reconfig_span == REFCLK_RECONFIG_SPAN_TWO_RIGHT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[3].bb.syspll_refclk_output_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[4].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[4].passthru_refclkin_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[4].refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[4].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[4].bb.f_fastest_reconfig_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[4].bb.location == UX_REFCLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[4].bb.passthru_clk_type == PASSTHRU_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[4].bb.refclk_available_at_poweron == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[4].bb.refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[4].bb.refclk_reconfig_span == REFCLK_RECONFIG_SPAN_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[4].bb.syspll_refclk_output_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[5].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[5].passthru_refclkin_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[5].refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[5].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[5].bb.f_fastest_reconfig_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[5].bb.location == UX_REFCLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[5].bb.passthru_clk_type == PASSTHRU_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[5].bb.refclk_available_at_poweron == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[5].bb.refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[5].bb.refclk_reconfig_span == REFCLK_RECONFIG_SPAN_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[5].bb.syspll_refclk_output_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[6].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[6].passthru_refclkin_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[6].refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[6].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[6].bb.f_fastest_reconfig_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[6].bb.location == UX_REFCLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[6].bb.passthru_clk_type == PASSTHRU_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[6].bb.refclk_available_at_poweron == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[6].bb.refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[6].bb.refclk_reconfig_span == REFCLK_RECONFIG_SPAN_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[6].bb.syspll_refclk_output_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[7].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[7].passthru_refclkin_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[7].refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[7].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[7].bb.f_fastest_reconfig_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[7].bb.location == UX_REFCLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[7].bb.passthru_clk_type == PASSTHRU_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[7].bb.refclk_available_at_poweron == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[7].bb.refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[7].bb.refclk_reconfig_span == REFCLK_RECONFIG_SPAN_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[7].bb.syspll_refclk_output_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[8].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[8].passthru_refclkin_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[8].refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[8].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[8].bb.f_fastest_reconfig_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[8].bb.location == UX_REFCLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[8].bb.passthru_clk_type == PASSTHRU_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[8].bb.refclk_available_at_poweron == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[8].bb.refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[8].bb.refclk_reconfig_span == REFCLK_RECONFIG_SPAN_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[8].bb.syspll_refclk_output_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[9].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[9].passthru_refclkin_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[9].refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[9].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[9].bb.f_fastest_reconfig_refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[9].bb.location == UX_REFCLK0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[9].bb.passthru_clk_type == PASSTHRU_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[9].bb.refclk_available_at_poweron == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[9].bb.refclk_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[9].bb.refclk_reconfig_span == REFCLK_RECONFIG_SPAN_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_refclk[9].bb.syspll_refclk_output_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].rx_cdr_refclk_link_net_id == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].xcvr_data0_link_net_id == 32'd7
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.cdr_bw_sel == CDR_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.cdr_f_out_hz == 40'd5940000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.cdr_f_pfd_hz == 40'd29700000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.cdr_f_postdiv_hz == 40'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.cdr_f_ref_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.cdr_f_vco_hz == 40'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.cdr_l_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.cdr_m_counter == 9'd200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.cdr_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.cdr_postdiv_counter == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.cdr_ppm_driftcount == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.core_pll == CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.dpma_refclk_source == DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.enable_port_control_of_cdr_ltr_ltd == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.fec_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.flux_mode == FLUX_MODE_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.location == UX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.loopback_mode == LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.master_pll_pair_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.master_sup_mode == MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.primary_use == PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.rx_ac_couple_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.rx_adapt_mode == RX_ADAPT_MODE_STATIC_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.rx_bond_size == RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.rx_line_rate_bps == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.rx_onchip_termination == RX_ONCHIP_TERMINATION_R_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.rx_protocol == RX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.rx_term_mode_select == RX_TERM_MODE_SELECT_DIFFERENTIAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.rx_tuning_hint == RX_TUNING_HINT_SDI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.rx_user_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.rx_width == RX_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.rxeq_vga_gain == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.standalone_core_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.standalone_core_clk_mux == STANDALONE_CORE_CLK_MUX_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.synth_lc_fb_div_emb_mult_counter == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.synth_lc_fb_div_n_frac_mode == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.txrx_channel_operation == TXRX_CHANNEL_OPERATION_DUAL_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.txrx_line_encoding_type == TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.txrx_xcvr_speed_bucket == TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.ur_en_rxbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.ur_en_rxeiosdetectstat_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.ur_en_rxeq_clr_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.ur_en_rxeq_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.ur_en_rxeq_static_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.ur_en_rxeyediag_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.ur_en_rxovrcdrlock2dataen_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.ur_en_rxterm_hiz_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK1_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.ux_speed_grade == UX_SPEED_GRADE_DASH2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[0].bb.vsr_mode == VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].rx_cdr_refclk_link_net_id == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].xcvr_data0_link_net_id == 32'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.cdr_bw_sel == CDR_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.cdr_f_out_hz == 40'd5940000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.cdr_f_pfd_hz == 40'd29700000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.cdr_f_postdiv_hz == 40'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.cdr_f_ref_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.cdr_f_vco_hz == 40'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.cdr_l_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.cdr_m_counter == 9'd200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.cdr_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.cdr_postdiv_counter == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.cdr_ppm_driftcount == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.core_pll == CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.dpma_refclk_source == DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.enable_port_control_of_cdr_ltr_ltd == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.fec_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.flux_mode == FLUX_MODE_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.location == UX8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.loopback_mode == LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.master_pll_pair_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.master_sup_mode == MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.primary_use == PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.rx_adapt_mode == RX_ADAPT_MODE_UX_RX_ADAPT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.rx_bond_size == RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.rx_line_rate_bps == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.rx_onchip_termination == RX_ONCHIP_TERMINATION_R_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.rx_protocol == RX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.rx_term_mode_select == RX_TERM_MODE_SELECT_DIFFERENTIAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.rx_tuning_hint == RX_TUNING_HINT_SDI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.rx_user_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.rx_width == RX_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.rxeq_vga_gain == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.standalone_core_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.standalone_core_clk_mux == STANDALONE_CORE_CLK_MUX_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.synth_lc_fb_div_emb_mult_counter == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.synth_lc_fb_div_n_frac_mode == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.txrx_channel_operation == TXRX_CHANNEL_OPERATION_DUAL_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.txrx_line_encoding_type == TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.txrx_xcvr_speed_bucket == TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.ur_en_rxbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.ur_en_rxeiosdetectstat_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.ur_en_rxeq_clr_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.ur_en_rxeq_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.ur_en_rxeq_static_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.ur_en_rxeyediag_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.ur_en_rxovrcdrlock2dataen_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.ur_en_rxterm_hiz_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK1_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.ux_speed_grade == UX_SPEED_GRADE_DASH2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[1].bb.vsr_mode == VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].rx_cdr_refclk_link_net_id == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].xcvr_data0_link_net_id == 32'd21
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.cdr_bw_sel == CDR_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.cdr_f_out_hz == 40'd5940000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.cdr_f_pfd_hz == 40'd29700000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.cdr_f_postdiv_hz == 40'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.cdr_f_ref_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.cdr_f_vco_hz == 40'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.cdr_l_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.cdr_m_counter == 9'd200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.cdr_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.cdr_postdiv_counter == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.cdr_ppm_driftcount == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.core_pll == CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.dpma_refclk_source == DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.enable_port_control_of_cdr_ltr_ltd == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.fec_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.flux_mode == FLUX_MODE_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.location == UX6
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.loopback_mode == LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.master_pll_pair_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.master_sup_mode == MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.primary_use == PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.rx_adapt_mode == RX_ADAPT_MODE_UX_RX_ADAPT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.rx_bond_size == RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.rx_line_rate_bps == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.rx_onchip_termination == RX_ONCHIP_TERMINATION_R_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.rx_protocol == RX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.rx_term_mode_select == RX_TERM_MODE_SELECT_DIFFERENTIAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.rx_tuning_hint == RX_TUNING_HINT_SDI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.rx_user_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.rx_width == RX_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.rxeq_vga_gain == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.standalone_core_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.standalone_core_clk_mux == STANDALONE_CORE_CLK_MUX_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.synth_lc_fb_div_emb_mult_counter == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.synth_lc_fb_div_n_frac_mode == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.txrx_channel_operation == TXRX_CHANNEL_OPERATION_DUAL_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.txrx_line_encoding_type == TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.txrx_xcvr_speed_bucket == TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.ur_en_rxbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.ur_en_rxeiosdetectstat_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.ur_en_rxeq_clr_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.ur_en_rxeq_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.ur_en_rxeq_static_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.ur_en_rxeyediag_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.ur_en_rxovrcdrlock2dataen_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.ur_en_rxterm_hiz_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.ux_speed_grade == UX_SPEED_GRADE_DASH2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[2].bb.vsr_mode == VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].rx_cdr_refclk_link_net_id == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].xcvr_data0_link_net_id == 32'd26
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.cdr_bw_sel == CDR_BW_SEL_LOW
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.cdr_f_out_hz == 40'd5940000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.cdr_f_pfd_hz == 40'd29700000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.cdr_f_postdiv_hz == 40'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.cdr_f_ref_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.cdr_f_vco_hz == 40'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.cdr_l_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.cdr_m_counter == 9'd200
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.cdr_n_counter == 6'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.cdr_postdiv_counter == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.cdr_ppm_driftcount == 16'd1024
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.core_pll == CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.dpma_refclk_source == DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.enable_port_control_of_cdr_ltr_ltd == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.fec_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.flux_mode == FLUX_MODE_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.location == UX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.loopback_mode == LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.master_pll_pair_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.master_sup_mode == MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.primary_use == PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.rx_ac_couple_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.rx_adapt_mode == RX_ADAPT_MODE_STATIC_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.rx_bond_size == RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.rx_line_rate_bps == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.rx_onchip_termination == RX_ONCHIP_TERMINATION_R_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.rx_protocol == RX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.rx_term_mode_select == RX_TERM_MODE_SELECT_DIFFERENTIAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.rx_tuning_hint == RX_TUNING_HINT_SDI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.rx_user_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.rx_width == RX_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.rxeq_vga_gain == 7'd60
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.standalone_core_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.standalone_core_clk_mux == STANDALONE_CORE_CLK_MUX_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.synth_lc_fb_div_emb_mult_counter == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.synth_lc_fb_div_n_frac_mode == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.txrx_channel_operation == TXRX_CHANNEL_OPERATION_DUAL_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.txrx_line_encoding_type == TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.txrx_xcvr_speed_bucket == TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.ur_en_rxbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.ur_en_rxeiosdetectstat_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.ur_en_rxeq_clr_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.ur_en_rxeq_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.ur_en_rxeq_static_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.ur_en_rxeyediag_start_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.ur_en_rxovrcdrlock2dataen_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.ur_en_rxterm_hiz_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK1_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.ux_speed_grade == UX_SPEED_GRADE_DASH2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[3].bb.vsr_mode == VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].rx_cdr_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.cdr_bw_sel == CDR_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.cdr_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.cdr_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.cdr_f_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.cdr_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.cdr_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.cdr_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.cdr_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.cdr_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.cdr_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.cdr_ppm_driftcount == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.core_pll == CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.dpma_refclk_source == DPMA_REFCLK_SOURCE_RX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.enable_port_control_of_cdr_ltr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.external_dpma_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.flux_mode == FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.location == UX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.loopback_mode == LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.master_pll_pair_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.master_sup_mode == MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.primary_use == PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.rx_adapt_mode == RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.rx_bond_size == RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.rx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.rx_onchip_termination == RX_ONCHIP_TERMINATION_R_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.rx_protocol == RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.rx_term_mode_select == RX_TERM_MODE_SELECT_GROUNDED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.rx_tuning_hint == RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.rx_width == RX_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.rxeq_vga_gain == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.standalone_core_clk_mux == STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.synth_lc_fb_div_emb_mult_counter == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.txrx_channel_operation == TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.txrx_line_encoding_type == TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.txrx_xcvr_speed_bucket == TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.ur_en_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.ur_en_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.ur_en_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.ur_en_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.ur_en_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.ur_en_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.ur_en_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.ur_en_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.ur_en_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.ur_en_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.ur_en_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.ur_en_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.ur_en_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.ux_speed_grade == UX_SPEED_GRADE_DASH1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[4].bb.vsr_mode == VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].rx_cdr_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.cdr_bw_sel == CDR_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.cdr_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.cdr_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.cdr_f_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.cdr_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.cdr_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.cdr_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.cdr_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.cdr_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.cdr_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.cdr_ppm_driftcount == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.core_pll == CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.dpma_refclk_source == DPMA_REFCLK_SOURCE_RX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.enable_port_control_of_cdr_ltr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.external_dpma_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.flux_mode == FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.location == UX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.loopback_mode == LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.master_pll_pair_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.master_sup_mode == MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.primary_use == PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.rx_adapt_mode == RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.rx_bond_size == RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.rx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.rx_onchip_termination == RX_ONCHIP_TERMINATION_R_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.rx_protocol == RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.rx_term_mode_select == RX_TERM_MODE_SELECT_GROUNDED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.rx_tuning_hint == RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.rx_width == RX_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.rxeq_vga_gain == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.standalone_core_clk_mux == STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.synth_lc_fb_div_emb_mult_counter == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.txrx_channel_operation == TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.txrx_line_encoding_type == TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.txrx_xcvr_speed_bucket == TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.ur_en_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.ur_en_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.ur_en_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.ur_en_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.ur_en_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.ur_en_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.ur_en_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.ur_en_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.ur_en_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.ur_en_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.ur_en_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.ur_en_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.ur_en_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.ux_speed_grade == UX_SPEED_GRADE_DASH1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[5].bb.vsr_mode == VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].rx_cdr_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.cdr_bw_sel == CDR_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.cdr_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.cdr_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.cdr_f_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.cdr_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.cdr_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.cdr_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.cdr_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.cdr_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.cdr_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.cdr_ppm_driftcount == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.core_pll == CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.dpma_refclk_source == DPMA_REFCLK_SOURCE_RX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.enable_port_control_of_cdr_ltr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.external_dpma_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.flux_mode == FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.location == UX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.loopback_mode == LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.master_pll_pair_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.master_sup_mode == MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.primary_use == PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.rx_adapt_mode == RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.rx_bond_size == RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.rx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.rx_onchip_termination == RX_ONCHIP_TERMINATION_R_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.rx_protocol == RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.rx_term_mode_select == RX_TERM_MODE_SELECT_GROUNDED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.rx_tuning_hint == RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.rx_width == RX_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.rxeq_vga_gain == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.standalone_core_clk_mux == STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.synth_lc_fb_div_emb_mult_counter == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.txrx_channel_operation == TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.txrx_line_encoding_type == TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.txrx_xcvr_speed_bucket == TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.ur_en_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.ur_en_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.ur_en_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.ur_en_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.ur_en_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.ur_en_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.ur_en_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.ur_en_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.ur_en_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.ur_en_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.ur_en_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.ur_en_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.ur_en_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.ux_speed_grade == UX_SPEED_GRADE_DASH1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[6].bb.vsr_mode == VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].rx_cdr_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.cdr_bw_sel == CDR_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.cdr_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.cdr_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.cdr_f_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.cdr_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.cdr_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.cdr_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.cdr_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.cdr_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.cdr_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.cdr_ppm_driftcount == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.core_pll == CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.dpma_refclk_source == DPMA_REFCLK_SOURCE_RX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.enable_port_control_of_cdr_ltr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.external_dpma_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.flux_mode == FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.location == UX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.loopback_mode == LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.master_pll_pair_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.master_sup_mode == MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.primary_use == PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.rx_adapt_mode == RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.rx_bond_size == RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.rx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.rx_onchip_termination == RX_ONCHIP_TERMINATION_R_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.rx_protocol == RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.rx_term_mode_select == RX_TERM_MODE_SELECT_GROUNDED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.rx_tuning_hint == RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.rx_width == RX_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.rxeq_vga_gain == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.standalone_core_clk_mux == STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.synth_lc_fb_div_emb_mult_counter == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.txrx_channel_operation == TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.txrx_line_encoding_type == TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.txrx_xcvr_speed_bucket == TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.ur_en_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.ur_en_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.ur_en_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.ur_en_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.ur_en_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.ur_en_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.ur_en_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.ur_en_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.ur_en_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.ur_en_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.ur_en_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.ur_en_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.ur_en_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.ux_speed_grade == UX_SPEED_GRADE_DASH1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[7].bb.vsr_mode == VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].rx_cdr_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.cdr_bw_sel == CDR_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.cdr_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.cdr_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.cdr_f_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.cdr_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.cdr_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.cdr_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.cdr_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.cdr_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.cdr_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.cdr_ppm_driftcount == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.core_pll == CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.dpma_refclk_source == DPMA_REFCLK_SOURCE_RX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.enable_port_control_of_cdr_ltr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.external_dpma_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.flux_mode == FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.location == UX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.loopback_mode == LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.master_pll_pair_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.master_sup_mode == MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.primary_use == PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.rx_adapt_mode == RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.rx_bond_size == RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.rx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.rx_onchip_termination == RX_ONCHIP_TERMINATION_R_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.rx_protocol == RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.rx_term_mode_select == RX_TERM_MODE_SELECT_GROUNDED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.rx_tuning_hint == RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.rx_width == RX_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.rxeq_vga_gain == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.standalone_core_clk_mux == STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.synth_lc_fb_div_emb_mult_counter == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.txrx_channel_operation == TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.txrx_line_encoding_type == TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.txrx_xcvr_speed_bucket == TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.ur_en_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.ur_en_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.ur_en_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.ur_en_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.ur_en_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.ur_en_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.ur_en_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.ur_en_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.ur_en_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.ur_en_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.ur_en_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.ur_en_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.ur_en_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.ux_speed_grade == UX_SPEED_GRADE_DASH1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[8].bb.vsr_mode == VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].rx_cdr_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.cdr_bw_sel == CDR_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.cdr_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.cdr_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.cdr_f_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.cdr_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.cdr_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.cdr_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.cdr_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.cdr_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.cdr_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.cdr_ppm_driftcount == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.core_pll == CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.dpma_refclk_source == DPMA_REFCLK_SOURCE_RX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.enable_port_control_of_cdr_ltr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.external_dpma_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.flux_mode == FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.location == UX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.loopback_mode == LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.master_pll_pair_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.master_sup_mode == MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.primary_use == PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.rx_adapt_mode == RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.rx_bond_size == RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.rx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.rx_onchip_termination == RX_ONCHIP_TERMINATION_R_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.rx_protocol == RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.rx_term_mode_select == RX_TERM_MODE_SELECT_GROUNDED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.rx_tuning_hint == RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.rx_width == RX_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.rxeq_vga_gain == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.standalone_core_clk_mux == STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.synth_lc_fb_div_emb_mult_counter == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.txrx_channel_operation == TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.txrx_line_encoding_type == TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.txrx_xcvr_speed_bucket == TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.ur_en_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.ur_en_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.ur_en_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.ur_en_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.ur_en_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.ur_en_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.ur_en_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.ur_en_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.ur_en_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.ur_en_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.ur_en_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.ur_en_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.ur_en_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.ux_speed_grade == UX_SPEED_GRADE_DASH1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[9].bb.vsr_mode == VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].rx_cdr_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.cdr_bw_sel == CDR_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.cdr_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.cdr_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.cdr_f_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.cdr_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.cdr_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.cdr_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.cdr_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.cdr_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.cdr_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.cdr_ppm_driftcount == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.core_pll == CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.dpma_refclk_source == DPMA_REFCLK_SOURCE_RX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.enable_port_control_of_cdr_ltr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.external_dpma_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.flux_mode == FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.location == UX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.loopback_mode == LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.master_pll_pair_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.master_sup_mode == MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.primary_use == PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.rx_adapt_mode == RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.rx_bond_size == RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.rx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.rx_onchip_termination == RX_ONCHIP_TERMINATION_R_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.rx_protocol == RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.rx_term_mode_select == RX_TERM_MODE_SELECT_GROUNDED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.rx_tuning_hint == RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.rx_width == RX_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.rxeq_vga_gain == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.standalone_core_clk_mux == STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.synth_lc_fb_div_emb_mult_counter == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.txrx_channel_operation == TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.txrx_line_encoding_type == TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.txrx_xcvr_speed_bucket == TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.ur_en_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.ur_en_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.ur_en_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.ur_en_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.ur_en_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.ur_en_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.ur_en_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.ur_en_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.ur_en_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.ur_en_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.ur_en_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.ur_en_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.ur_en_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.ux_speed_grade == UX_SPEED_GRADE_DASH1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[10].bb.vsr_mode == VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].rx_cdr_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.cdr_bw_sel == CDR_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.cdr_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.cdr_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.cdr_f_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.cdr_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.cdr_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.cdr_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.cdr_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.cdr_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.cdr_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.cdr_ppm_driftcount == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.core_pll == CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.dpma_refclk_source == DPMA_REFCLK_SOURCE_RX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.enable_port_control_of_cdr_ltr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.external_dpma_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.flux_mode == FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.location == UX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.loopback_mode == LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.master_pll_pair_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.master_sup_mode == MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.primary_use == PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.rx_adapt_mode == RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.rx_bond_size == RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.rx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.rx_onchip_termination == RX_ONCHIP_TERMINATION_R_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.rx_protocol == RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.rx_term_mode_select == RX_TERM_MODE_SELECT_GROUNDED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.rx_tuning_hint == RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.rx_width == RX_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.rxeq_vga_gain == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.standalone_core_clk_mux == STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.synth_lc_fb_div_emb_mult_counter == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.txrx_channel_operation == TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.txrx_line_encoding_type == TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.txrx_xcvr_speed_bucket == TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.ur_en_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.ur_en_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.ur_en_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.ur_en_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.ur_en_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.ur_en_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.ur_en_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.ur_en_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.ur_en_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.ur_en_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.ur_en_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.ur_en_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.ur_en_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.ux_speed_grade == UX_SPEED_GRADE_DASH1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[11].bb.vsr_mode == VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].rx_cdr_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.cdr_bw_sel == CDR_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.cdr_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.cdr_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.cdr_f_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.cdr_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.cdr_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.cdr_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.cdr_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.cdr_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.cdr_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.cdr_ppm_driftcount == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.core_pll == CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.dpma_refclk_source == DPMA_REFCLK_SOURCE_RX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.enable_port_control_of_cdr_ltr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.external_dpma_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.flux_mode == FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.location == UX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.loopback_mode == LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.master_pll_pair_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.master_sup_mode == MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.primary_use == PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.rx_adapt_mode == RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.rx_bond_size == RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.rx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.rx_onchip_termination == RX_ONCHIP_TERMINATION_R_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.rx_protocol == RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.rx_term_mode_select == RX_TERM_MODE_SELECT_GROUNDED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.rx_tuning_hint == RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.rx_width == RX_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.rxeq_vga_gain == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.standalone_core_clk_mux == STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.synth_lc_fb_div_emb_mult_counter == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.txrx_channel_operation == TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.txrx_line_encoding_type == TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.txrx_xcvr_speed_bucket == TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.ur_en_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.ur_en_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.ur_en_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.ur_en_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.ur_en_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.ur_en_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.ur_en_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.ur_en_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.ur_en_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.ur_en_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.ur_en_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.ur_en_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.ur_en_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.ux_speed_grade == UX_SPEED_GRADE_DASH1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[12].bb.vsr_mode == VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].rx_cdr_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.cdr_bw_sel == CDR_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.cdr_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.cdr_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.cdr_f_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.cdr_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.cdr_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.cdr_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.cdr_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.cdr_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.cdr_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.cdr_ppm_driftcount == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.core_pll == CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.dpma_refclk_source == DPMA_REFCLK_SOURCE_RX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.enable_port_control_of_cdr_ltr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.external_dpma_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.flux_mode == FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.location == UX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.loopback_mode == LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.master_pll_pair_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.master_sup_mode == MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.primary_use == PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.rx_adapt_mode == RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.rx_bond_size == RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.rx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.rx_onchip_termination == RX_ONCHIP_TERMINATION_R_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.rx_protocol == RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.rx_term_mode_select == RX_TERM_MODE_SELECT_GROUNDED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.rx_tuning_hint == RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.rx_width == RX_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.rxeq_vga_gain == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.standalone_core_clk_mux == STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.synth_lc_fb_div_emb_mult_counter == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.txrx_channel_operation == TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.txrx_line_encoding_type == TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.txrx_xcvr_speed_bucket == TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.ur_en_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.ur_en_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.ur_en_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.ur_en_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.ur_en_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.ur_en_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.ur_en_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.ur_en_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.ur_en_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.ur_en_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.ur_en_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.ur_en_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.ur_en_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.ux_speed_grade == UX_SPEED_GRADE_DASH1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[13].bb.vsr_mode == VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].rx_cdr_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.cdr_bw_sel == CDR_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.cdr_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.cdr_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.cdr_f_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.cdr_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.cdr_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.cdr_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.cdr_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.cdr_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.cdr_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.cdr_ppm_driftcount == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.core_pll == CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.dpma_refclk_source == DPMA_REFCLK_SOURCE_RX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.enable_port_control_of_cdr_ltr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.external_dpma_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.flux_mode == FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.location == UX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.loopback_mode == LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.master_pll_pair_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.master_sup_mode == MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.primary_use == PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.rx_adapt_mode == RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.rx_bond_size == RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.rx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.rx_onchip_termination == RX_ONCHIP_TERMINATION_R_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.rx_protocol == RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.rx_term_mode_select == RX_TERM_MODE_SELECT_GROUNDED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.rx_tuning_hint == RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.rx_width == RX_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.rxeq_vga_gain == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.standalone_core_clk_mux == STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.synth_lc_fb_div_emb_mult_counter == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.txrx_channel_operation == TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.txrx_line_encoding_type == TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.txrx_xcvr_speed_bucket == TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.ur_en_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.ur_en_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.ur_en_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.ur_en_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.ur_en_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.ur_en_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.ur_en_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.ur_en_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.ur_en_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.ur_en_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.ur_en_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.ur_en_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.ur_en_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.ux_speed_grade == UX_SPEED_GRADE_DASH1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[14].bb.vsr_mode == VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].rx_cdr_divclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].rx_cdr_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.cdr_bw_sel == CDR_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.cdr_clkdiv_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.cdr_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.cdr_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.cdr_f_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.cdr_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.cdr_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.cdr_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.cdr_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.cdr_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.cdr_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.cdr_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.cdr_ppm_driftcount == 16'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.core_pll == CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.dpma_refclk_source == DPMA_REFCLK_SOURCE_RX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.enable_port_control_of_cdr_ltr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.external_dpma_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.flux_mode == FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.force_cdr_ltd == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.force_cdr_ltr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.location == UX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.loopback_mode == LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.master_pll_pair_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.master_sup_mode == MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.prbs_mon_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.primary_use == PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.rx_ac_couple_enable == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.rx_adapt_mode == RX_ADAPT_MODE_NO_EQ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.rx_bond_size == RX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.rx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.rx_onchip_termination == RX_ONCHIP_TERMINATION_R_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.rx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.rx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.rx_protocol == RX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.rx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.rx_term_mode_select == RX_TERM_MODE_SELECT_GROUNDED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.rx_tuning_hint == RX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.rx_user_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.rx_width == RX_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.rxeq_dfe_data_tap_1 == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.rxeq_hf_boost == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.rxeq_vga_gain == 7'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.squelch_detect == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.standalone_core_clk_mux == STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.sv_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.sv_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.sv_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.sv_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.sv_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.sv_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.sv_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.sv_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.sv_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.synth_lc_fb_div_emb_mult_counter == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.txrx_channel_operation == TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.txrx_line_encoding_type == TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.txrx_xcvr_speed_bucket == TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.ur_en_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.ur_en_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.ur_en_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.ur_en_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.ur_en_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.ur_en_rx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.ur_en_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.ur_en_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.ur_en_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.ur_en_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.ur_en_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.ur_en_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.ur_en_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.ur_en_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.ur_ovr_rx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.ur_ovr_rxbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.ur_ovr_rxeiosdetectstat_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.ur_ovr_rxeq_clr_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.ur_ovr_rxeq_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.ur_ovr_rxeq_static_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.ur_ovr_rxeyediag_start_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.ur_ovr_rxovrcdrlock2dataen_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.ur_ovr_rxterm_hiz_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.ux_speed_grade == UX_SPEED_GRADE_DASH1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_rx[15].bb.vsr_mode == VSR_MODE_DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].core_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].lc_cascade_out_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].passthru_refclkout_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].tx_pll_refclk_link_net_id == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].xcvr_data0_link_net_id == 32'd11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.core_pll == CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.dpma_refclk_source == DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.fec_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.flux_mode == FLUX_MODE_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.location == UX3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.loopback_mode == LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.master_pll_pair_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.master_sup_mode == MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.primary_use == PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.standalone_core_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.standalone_core_clk_mux == STANDALONE_CORE_CLK_MUX_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_0_feed_forward_gain == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_fast_primary_use == SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_fb_div_emb_mult_counter == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_fb_div_n_frac_mode == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_med_f_out_hz == 40'd5940000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_med_f_ref_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_med_f_tx_postdiv_hz == 40'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_med_f_vco_hz == 40'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_med_l_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_med_m_counter == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_med_primary_use == SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_med_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_med_tx_postdiv_counter == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_slow_primary_use == SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.tx_bond_size == TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.tx_line_rate_bps == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.tx_o_clk_e2_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.tx_o_clk_e4_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.tx_pll == TX_PLL_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.tx_pll_bw_sel == TX_PLL_BW_SEL_MEDIUM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.tx_protocol == TX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.tx_tuning_hint == TX_TUNING_HINT_SDI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.tx_user_clk1_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.tx_user_clk1_mux == TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.tx_user_clk2_mux == TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.tx_width == TX_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.txeq_main_tap == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.txrx_channel_operation == TXRX_CHANNEL_OPERATION_DUAL_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.txrx_line_encoding_type == TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.txrx_xcvr_speed_bucket == TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.ur_en_txbeacon_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.ur_en_txbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.ur_en_txdetectrx_req_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK1_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[0].bb.ux_speed_grade == UX_SPEED_GRADE_DASH2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].core_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].lc_cascade_out_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].passthru_refclkout_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].tx_pll_refclk_link_net_id == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].xcvr_data0_link_net_id == 32'd30
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.core_pll == CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.dpma_refclk_source == DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.fec_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.flux_mode == FLUX_MODE_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.location == UX2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.loopback_mode == LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.master_pll_pair_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.master_sup_mode == MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.primary_use == PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.standalone_core_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.standalone_core_clk_mux == STANDALONE_CORE_CLK_MUX_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_0_feed_forward_gain == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_fast_primary_use == SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_fb_div_emb_mult_counter == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_fb_div_n_frac_mode == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_med_f_out_hz == 40'd5940000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_med_f_ref_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_med_f_tx_postdiv_hz == 40'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_med_f_vco_hz == 40'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_med_l_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_med_m_counter == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_med_primary_use == SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_med_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_med_tx_postdiv_counter == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_slow_primary_use == SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.tx_bond_size == TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.tx_line_rate_bps == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.tx_o_clk_e2_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.tx_o_clk_e4_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.tx_pll == TX_PLL_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.tx_pll_bw_sel == TX_PLL_BW_SEL_MEDIUM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.tx_protocol == TX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.tx_tuning_hint == TX_TUNING_HINT_SDI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.tx_user_clk1_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.tx_user_clk1_mux == TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.tx_user_clk2_mux == TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.tx_width == TX_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.txeq_main_tap == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.txrx_channel_operation == TXRX_CHANNEL_OPERATION_DUAL_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.txrx_line_encoding_type == TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.txrx_xcvr_speed_bucket == TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.ur_en_txbeacon_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.ur_en_txbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.ur_en_txdetectrx_req_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK1_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[1].bb.ux_speed_grade == UX_SPEED_GRADE_DASH2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].core_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].lc_cascade_out_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].passthru_refclkout_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].tx_pll_refclk_link_net_id == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].xcvr_data0_link_net_id == 32'd34
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.core_pll == CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.dpma_refclk_source == DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.fec_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.flux_mode == FLUX_MODE_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.location == UX5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.loopback_mode == LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.master_pll_pair_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.master_sup_mode == MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.primary_use == PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.standalone_core_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.standalone_core_clk_mux == STANDALONE_CORE_CLK_MUX_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_0_feed_forward_gain == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_fast_primary_use == SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_fb_div_emb_mult_counter == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_fb_div_n_frac_mode == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_med_f_out_hz == 40'd5940000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_med_f_ref_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_med_f_tx_postdiv_hz == 40'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_med_f_vco_hz == 40'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_med_l_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_med_m_counter == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_med_primary_use == SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_med_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_med_tx_postdiv_counter == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_slow_primary_use == SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.tx_bond_size == TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.tx_line_rate_bps == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.tx_o_clk_e2_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.tx_o_clk_e4_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.tx_pll == TX_PLL_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.tx_pll_bw_sel == TX_PLL_BW_SEL_MEDIUM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.tx_protocol == TX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.tx_tuning_hint == TX_TUNING_HINT_SDI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.tx_user_clk1_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.tx_user_clk1_mux == TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.tx_user_clk2_mux == TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.tx_width == TX_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.txeq_main_tap == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.txrx_channel_operation == TXRX_CHANNEL_OPERATION_DUAL_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.txrx_line_encoding_type == TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.txrx_xcvr_speed_bucket == TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.ur_en_txbeacon_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.ur_en_txbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.ur_en_txdetectrx_req_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK1_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[2].bb.ux_speed_grade == UX_SPEED_GRADE_DASH2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].core_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].lc_cascade_out_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].passthru_refclkout_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].tx_pll_refclk_link_net_id == 32'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].xcvr_data0_link_net_id == 32'd38
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.core_pll == CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.dpma_refclk_source == DPMA_REFCLK_SOURCE_EXTERNAL
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.external_dpma_f_ref_hz == 40'd156250000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.fec_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.flux_mode == FLUX_MODE_BYPASS
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.location == UX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.loopback_mode == LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.master_pll_pair_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.master_sup_mode == MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.primary_use == PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.standalone_core_clk_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.standalone_core_clk_mux == STANDALONE_CORE_CLK_MUX_FAST
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_0_feed_forward_gain == 8'd16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_fast_primary_use == SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_fb_div_emb_mult_counter == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_fb_div_n_frac_mode == 2'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_med_f_out_hz == 40'd5940000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_med_f_ref_hz == 40'd148500000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_med_f_tx_postdiv_hz == 40'd297000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_med_f_vco_hz == 40'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_med_l_counter == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_med_m_counter == 9'd80
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_med_n_counter == 6'd1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_med_primary_use == SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_med_rx_postdiv_counter == 8'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_med_tx_postdiv_counter == 8'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_slow_primary_use == SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.tx_bond_size == TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.tx_line_rate_bps == 37'd11880000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.tx_o_clk_e2_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.tx_o_clk_e4_hz == 36'd594000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.tx_pll == TX_PLL_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.tx_pll_bw_sel == TX_PLL_BW_SEL_MEDIUM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.tx_protocol == TX_PROTOCOL_PMA_DIRECT_SYS_CLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.tx_tuning_hint == TX_TUNING_HINT_SDI
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.tx_user_clk1_en == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.tx_user_clk1_mux == TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.tx_user_clk2_mux == TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.tx_width == TX_WIDTH_20
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.txeq_main_tap == 6'd47
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.txrx_channel_operation == TXRX_CHANNEL_OPERATION_DUAL_SIMPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.txrx_line_encoding_type == TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.txrx_xcvr_speed_bucket == TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.ur_en_andme_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.ur_en_lfps_en_lx_nt == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.ur_en_pcie_l1d1_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.ur_en_pcie_l1d2_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.ur_en_pcs_lock == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.ur_en_txbeacon_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.ur_en_txbist_en_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.ur_en_txdetectrx_req_lx_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK1_3
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[3].bb.ux_speed_grade == UX_SPEED_GRADE_DASH2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].core_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].lc_cascade_out_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].passthru_refclkout_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].tx_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.core_pll == CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.dpma_refclk_source == DPMA_REFCLK_SOURCE_RX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.external_dpma_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.flux_mode == FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.location == UX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.loopback_mode == LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.master_pll_pair_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.master_sup_mode == MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.primary_use == PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.standalone_core_clk_mux == STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_0_feed_forward_gain == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_fast_primary_use == SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_fb_div_emb_mult_counter == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_med_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_med_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_med_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_med_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_med_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_med_primary_use == SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_slow_primary_use == SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.tx_bond_size == TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.tx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.tx_o_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.tx_o_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.tx_pll == TX_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.tx_pll_bw_sel == TX_PLL_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.tx_protocol == TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.tx_tuning_hint == TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.tx_user_clk1_mux == TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.tx_user_clk2_mux == TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.tx_width == TX_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.txeq_main_tap == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.txrx_channel_operation == TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.txrx_line_encoding_type == TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.txrx_xcvr_speed_bucket == TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.ur_en_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.ur_en_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.ur_en_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.ur_en_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.ur_en_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.ur_en_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.ur_en_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.ur_en_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[4].bb.ux_speed_grade == UX_SPEED_GRADE_DASH1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].core_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].lc_cascade_out_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].passthru_refclkout_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].tx_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.core_pll == CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.dpma_refclk_source == DPMA_REFCLK_SOURCE_RX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.external_dpma_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.flux_mode == FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.location == UX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.loopback_mode == LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.master_pll_pair_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.master_sup_mode == MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.primary_use == PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.standalone_core_clk_mux == STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_0_feed_forward_gain == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_fast_primary_use == SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_fb_div_emb_mult_counter == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_med_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_med_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_med_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_med_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_med_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_med_primary_use == SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_slow_primary_use == SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.tx_bond_size == TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.tx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.tx_o_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.tx_o_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.tx_pll == TX_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.tx_pll_bw_sel == TX_PLL_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.tx_protocol == TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.tx_tuning_hint == TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.tx_user_clk1_mux == TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.tx_user_clk2_mux == TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.tx_width == TX_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.txeq_main_tap == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.txrx_channel_operation == TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.txrx_line_encoding_type == TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.txrx_xcvr_speed_bucket == TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.ur_en_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.ur_en_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.ur_en_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.ur_en_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.ur_en_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.ur_en_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.ur_en_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.ur_en_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[5].bb.ux_speed_grade == UX_SPEED_GRADE_DASH1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].core_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].lc_cascade_out_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].passthru_refclkout_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].tx_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.core_pll == CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.dpma_refclk_source == DPMA_REFCLK_SOURCE_RX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.external_dpma_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.flux_mode == FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.location == UX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.loopback_mode == LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.master_pll_pair_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.master_sup_mode == MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.primary_use == PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.standalone_core_clk_mux == STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_0_feed_forward_gain == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_fast_primary_use == SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_fb_div_emb_mult_counter == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_med_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_med_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_med_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_med_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_med_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_med_primary_use == SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_slow_primary_use == SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.tx_bond_size == TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.tx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.tx_o_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.tx_o_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.tx_pll == TX_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.tx_pll_bw_sel == TX_PLL_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.tx_protocol == TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.tx_tuning_hint == TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.tx_user_clk1_mux == TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.tx_user_clk2_mux == TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.tx_width == TX_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.txeq_main_tap == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.txrx_channel_operation == TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.txrx_line_encoding_type == TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.txrx_xcvr_speed_bucket == TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.ur_en_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.ur_en_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.ur_en_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.ur_en_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.ur_en_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.ur_en_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.ur_en_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.ur_en_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[6].bb.ux_speed_grade == UX_SPEED_GRADE_DASH1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].core_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].lc_cascade_out_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].passthru_refclkout_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].tx_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.core_pll == CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.dpma_refclk_source == DPMA_REFCLK_SOURCE_RX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.external_dpma_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.flux_mode == FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.location == UX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.loopback_mode == LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.master_pll_pair_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.master_sup_mode == MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.primary_use == PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.standalone_core_clk_mux == STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_0_feed_forward_gain == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_fast_primary_use == SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_fb_div_emb_mult_counter == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_med_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_med_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_med_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_med_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_med_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_med_primary_use == SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_slow_primary_use == SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.tx_bond_size == TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.tx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.tx_o_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.tx_o_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.tx_pll == TX_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.tx_pll_bw_sel == TX_PLL_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.tx_protocol == TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.tx_tuning_hint == TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.tx_user_clk1_mux == TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.tx_user_clk2_mux == TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.tx_width == TX_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.txeq_main_tap == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.txrx_channel_operation == TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.txrx_line_encoding_type == TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.txrx_xcvr_speed_bucket == TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.ur_en_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.ur_en_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.ur_en_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.ur_en_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.ur_en_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.ur_en_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.ur_en_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.ur_en_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[7].bb.ux_speed_grade == UX_SPEED_GRADE_DASH1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].core_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].lc_cascade_out_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].passthru_refclkout_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].tx_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.core_pll == CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.dpma_refclk_source == DPMA_REFCLK_SOURCE_RX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.external_dpma_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.flux_mode == FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.location == UX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.loopback_mode == LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.master_pll_pair_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.master_sup_mode == MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.primary_use == PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.standalone_core_clk_mux == STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_0_feed_forward_gain == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_fast_primary_use == SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_fb_div_emb_mult_counter == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_med_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_med_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_med_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_med_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_med_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_med_primary_use == SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_slow_primary_use == SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.tx_bond_size == TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.tx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.tx_o_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.tx_o_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.tx_pll == TX_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.tx_pll_bw_sel == TX_PLL_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.tx_protocol == TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.tx_tuning_hint == TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.tx_user_clk1_mux == TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.tx_user_clk2_mux == TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.tx_width == TX_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.txeq_main_tap == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.txrx_channel_operation == TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.txrx_line_encoding_type == TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.txrx_xcvr_speed_bucket == TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.ur_en_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.ur_en_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.ur_en_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.ur_en_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.ur_en_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.ur_en_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.ur_en_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.ur_en_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[8].bb.ux_speed_grade == UX_SPEED_GRADE_DASH1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].core_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].lc_cascade_out_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].passthru_refclkout_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].tx_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.core_pll == CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.dpma_refclk_source == DPMA_REFCLK_SOURCE_RX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.external_dpma_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.flux_mode == FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.location == UX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.loopback_mode == LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.master_pll_pair_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.master_sup_mode == MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.primary_use == PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.standalone_core_clk_mux == STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_0_feed_forward_gain == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_fast_primary_use == SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_fb_div_emb_mult_counter == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_med_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_med_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_med_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_med_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_med_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_med_primary_use == SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_slow_primary_use == SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.tx_bond_size == TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.tx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.tx_o_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.tx_o_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.tx_pll == TX_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.tx_pll_bw_sel == TX_PLL_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.tx_protocol == TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.tx_tuning_hint == TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.tx_user_clk1_mux == TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.tx_user_clk2_mux == TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.tx_width == TX_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.txeq_main_tap == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.txrx_channel_operation == TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.txrx_line_encoding_type == TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.txrx_xcvr_speed_bucket == TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.ur_en_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.ur_en_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.ur_en_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.ur_en_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.ur_en_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.ur_en_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.ur_en_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.ur_en_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[9].bb.ux_speed_grade == UX_SPEED_GRADE_DASH1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].core_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].lc_cascade_out_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].passthru_refclkout_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].tx_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.core_pll == CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.dpma_refclk_source == DPMA_REFCLK_SOURCE_RX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.external_dpma_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.flux_mode == FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.location == UX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.loopback_mode == LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.master_pll_pair_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.master_sup_mode == MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.primary_use == PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.standalone_core_clk_mux == STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_0_feed_forward_gain == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_fast_primary_use == SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_fb_div_emb_mult_counter == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_med_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_med_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_med_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_med_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_med_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_med_primary_use == SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_slow_primary_use == SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.tx_bond_size == TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.tx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.tx_o_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.tx_o_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.tx_pll == TX_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.tx_pll_bw_sel == TX_PLL_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.tx_protocol == TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.tx_tuning_hint == TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.tx_user_clk1_mux == TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.tx_user_clk2_mux == TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.tx_width == TX_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.txeq_main_tap == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.txrx_channel_operation == TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.txrx_line_encoding_type == TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.txrx_xcvr_speed_bucket == TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.ur_en_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.ur_en_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.ur_en_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.ur_en_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.ur_en_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.ur_en_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.ur_en_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.ur_en_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[10].bb.ux_speed_grade == UX_SPEED_GRADE_DASH1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].core_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].lc_cascade_out_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].passthru_refclkout_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].tx_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.core_pll == CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.dpma_refclk_source == DPMA_REFCLK_SOURCE_RX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.external_dpma_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.flux_mode == FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.location == UX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.loopback_mode == LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.master_pll_pair_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.master_sup_mode == MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.primary_use == PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.standalone_core_clk_mux == STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_0_feed_forward_gain == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_fast_primary_use == SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_fb_div_emb_mult_counter == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_med_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_med_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_med_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_med_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_med_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_med_primary_use == SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_slow_primary_use == SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.tx_bond_size == TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.tx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.tx_o_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.tx_o_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.tx_pll == TX_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.tx_pll_bw_sel == TX_PLL_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.tx_protocol == TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.tx_tuning_hint == TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.tx_user_clk1_mux == TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.tx_user_clk2_mux == TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.tx_width == TX_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.txeq_main_tap == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.txrx_channel_operation == TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.txrx_line_encoding_type == TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.txrx_xcvr_speed_bucket == TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.ur_en_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.ur_en_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.ur_en_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.ur_en_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.ur_en_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.ur_en_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.ur_en_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.ur_en_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[11].bb.ux_speed_grade == UX_SPEED_GRADE_DASH1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].core_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].lc_cascade_out_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].passthru_refclkout_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].tx_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.core_pll == CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.dpma_refclk_source == DPMA_REFCLK_SOURCE_RX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.external_dpma_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.flux_mode == FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.location == UX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.loopback_mode == LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.master_pll_pair_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.master_sup_mode == MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.primary_use == PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.standalone_core_clk_mux == STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_0_feed_forward_gain == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_fast_primary_use == SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_fb_div_emb_mult_counter == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_med_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_med_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_med_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_med_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_med_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_med_primary_use == SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_slow_primary_use == SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.tx_bond_size == TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.tx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.tx_o_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.tx_o_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.tx_pll == TX_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.tx_pll_bw_sel == TX_PLL_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.tx_protocol == TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.tx_tuning_hint == TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.tx_user_clk1_mux == TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.tx_user_clk2_mux == TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.tx_width == TX_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.txeq_main_tap == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.txrx_channel_operation == TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.txrx_line_encoding_type == TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.txrx_xcvr_speed_bucket == TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.ur_en_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.ur_en_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.ur_en_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.ur_en_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.ur_en_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.ur_en_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.ur_en_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.ur_en_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[12].bb.ux_speed_grade == UX_SPEED_GRADE_DASH1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].core_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].lc_cascade_out_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].passthru_refclkout_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].tx_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.core_pll == CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.dpma_refclk_source == DPMA_REFCLK_SOURCE_RX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.external_dpma_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.flux_mode == FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.location == UX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.loopback_mode == LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.master_pll_pair_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.master_sup_mode == MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.primary_use == PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.standalone_core_clk_mux == STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_0_feed_forward_gain == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_fast_primary_use == SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_fb_div_emb_mult_counter == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_med_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_med_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_med_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_med_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_med_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_med_primary_use == SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_slow_primary_use == SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.tx_bond_size == TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.tx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.tx_o_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.tx_o_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.tx_pll == TX_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.tx_pll_bw_sel == TX_PLL_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.tx_protocol == TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.tx_tuning_hint == TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.tx_user_clk1_mux == TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.tx_user_clk2_mux == TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.tx_width == TX_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.txeq_main_tap == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.txrx_channel_operation == TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.txrx_line_encoding_type == TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.txrx_xcvr_speed_bucket == TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.ur_en_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.ur_en_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.ur_en_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.ur_en_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.ur_en_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.ur_en_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.ur_en_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.ur_en_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[13].bb.ux_speed_grade == UX_SPEED_GRADE_DASH1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].core_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].lc_cascade_out_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].passthru_refclkout_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].tx_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.core_pll == CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.dpma_refclk_source == DPMA_REFCLK_SOURCE_RX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.external_dpma_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.flux_mode == FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.location == UX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.loopback_mode == LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.master_pll_pair_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.master_sup_mode == MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.primary_use == PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.standalone_core_clk_mux == STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_0_feed_forward_gain == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_fast_primary_use == SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_fb_div_emb_mult_counter == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_med_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_med_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_med_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_med_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_med_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_med_primary_use == SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_slow_primary_use == SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.tx_bond_size == TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.tx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.tx_o_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.tx_o_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.tx_pll == TX_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.tx_pll_bw_sel == TX_PLL_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.tx_protocol == TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.tx_tuning_hint == TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.tx_user_clk1_mux == TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.tx_user_clk2_mux == TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.tx_width == TX_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.txeq_main_tap == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.txrx_channel_operation == TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.txrx_line_encoding_type == TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.txrx_xcvr_speed_bucket == TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.ur_en_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.ur_en_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.ur_en_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.ur_en_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.ur_en_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.ur_en_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.ur_en_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.ur_en_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[14].bb.ux_speed_grade == UX_SPEED_GRADE_DASH1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].core_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].dpma_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].duplex_bond_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].lc_cascade_out_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].next_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].passthru_refclkout_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].prev_bonding_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].tx_pll_refclk_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].xcvr_data0_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].xcvr_data1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.core_pll == CORE_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.dl_enable == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.dpma_refclk_source == DPMA_REFCLK_SOURCE_RX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.dynamic_pcie_speed_choice == DYNAMIC_PCIE_SPEED_CHOICE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.enable_static_refclk_network == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.engineered_link_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.external_dpma_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.fec_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.flux_mode == FLUX_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.force_refclk_power_to_specific_value == FORCE_REFCLK_POWER_TO_SPECIFIC_VALUE_NONE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.full_quad_master_pll_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.location == UX0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.loopback_mode == LOOPBACK_MODE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.master_pll_pair_mode == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.master_sup_mode == MASTER_SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.prbs_gen_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.prbs_pattern == 4'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.primary_use == PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.q_dl_cfg_rx_lat_bit_for_async_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.q_dl_cfg_rxbit_cntr_pma_attr == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.q_dl_cfg_rxbit_rollover_attr == 18'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.quad_pcie_mode == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.sim_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.sr_custom == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.standalone_core_clk_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.standalone_core_clk_mux == STANDALONE_CORE_CLK_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.sup_mode == SUP_MODE_USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.sv_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.sv_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.sv_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.sv_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.sv_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.sv_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.sv_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.sv_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.sv_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_0_feed_forward_gain == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_fast_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_fast_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_fast_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_fast_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_fast_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_fast_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_fast_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_fast_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_fast_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_fast_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_fast_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_fast_primary_use == SYNTH_LC_FAST_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_fast_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_fast_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_fast_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_fb_div_emb_mult_counter == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_fb_div_n_frac_mode == 2'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_med_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_med_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_med_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_med_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_med_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_med_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_med_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_med_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_med_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_med_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_med_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_med_primary_use == SYNTH_LC_MED_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_med_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_med_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_med_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_slow_f_out_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_slow_f_pfd_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_slow_f_ref_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_slow_f_rx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_slow_f_tx_postdiv_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_slow_f_vco_hz == 40'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_slow_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_slow_k_counter == 22'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_slow_l_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_slow_m_counter == 9'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_slow_n_counter == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_slow_primary_use == SYNTH_LC_SLOW_PRIMARY_USE_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_slow_rx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_slow_tx_postdiv_counter == 8'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.synth_lc_slow_tx_postdiv_fractional_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.tx_bond_size == TX_BOND_SIZE_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.tx_line_rate_bps == 37'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.tx_o_clk_e2_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.tx_o_clk_e4_hz == 36'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.tx_pam4_graycode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.tx_pam4_precode_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.tx_pll == TX_PLL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.tx_pll_bw_sel == TX_PLL_BW_SEL_DEFAULT
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.tx_protocol == TX_PROTOCOL_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.tx_protocol_hard_pcie_lowloss == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.tx_spread_spectrum_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.tx_tuning_hint == TX_TUNING_HINT_DISABLED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.tx_user_clk1_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.tx_user_clk1_mux == TX_USER_CLK1_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.tx_user_clk2_en == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.tx_user_clk2_mux == TX_USER_CLK2_MUX_SLOW_MED
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.tx_width == TX_WIDTH_32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.txeq_main_tap == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.txeq_post_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.txeq_pre_tap_1 == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.txeq_pre_tap_2 == 3'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.txrx_channel_operation == TXRX_CHANNEL_OPERATION_FULL_DUPLEX
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.txrx_line_encoding_type == TXRX_LINE_ENCODING_TYPE_NRZ
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.txrx_xcvr_speed_bucket == TXRX_XCVR_SPEED_BUCKET_25G
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.ur_en_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.ur_en_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.ur_en_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.ur_en_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.ur_en_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.ur_en_tx_lx_b_a == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.ur_en_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.ur_en_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.ur_en_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.ur_ovr_andme_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.ur_ovr_lfps_en_lx_nt == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.ur_ovr_pcie_l1d1_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.ur_ovr_pcie_l1d2_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.ur_ovr_pcs_lock == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.ur_ovr_tx_lx_b_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.ur_ovr_txbeacon_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.ur_ovr_txbist_en_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.ur_ovr_txdetectrx_req_lx_a == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.ux_q_10_to_1_ckmux_0_attr == CKMUX0_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.ux_q_10_to_1_ckmux_0_en_attr == CKMUX0_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.ux_q_10_to_1_ckmux_1_attr == CKMUX1_10_TO_1_CMOSCLK0_0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.ux_q_10_to_1_ckmux_1_en_attr == CKMUX1_10_TO_1_EN_FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_f_ux_tx[15].bb.ux_speed_grade == UX_SPEED_GRADE_DASH1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[0].adapt_rx_data_link_net_id == 32'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[0].aib_rx_data_link_net_id == 32'd8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[0].avmm1_link_net_id == 32'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[0].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[0].bb.location == MAIB11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[0].bb.op_mode == RX_DLL_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[1].adapt_rx_data_link_net_id == 32'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[1].aib_rx_data_link_net_id == 32'd17
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[1].avmm1_link_net_id == 32'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[1].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[1].bb.location == MAIB16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[1].bb.op_mode == RX_DLL_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[2].adapt_rx_data_link_net_id == 32'd23
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[2].aib_rx_data_link_net_id == 32'd22
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[2].avmm1_link_net_id == 32'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[2].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[2].bb.location == MAIB14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[2].bb.op_mode == RX_DLL_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[3].adapt_rx_data_link_net_id == 32'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[3].aib_rx_data_link_net_id == 32'd27
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[3].avmm1_link_net_id == 32'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[3].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[3].bb.location == MAIB8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[3].bb.op_mode == RX_DLL_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[4].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[4].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[4].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[4].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[4].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[4].bb.op_mode == PWR_DOWN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[5].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[5].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[5].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[5].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[5].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[5].bb.op_mode == PWR_DOWN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[6].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[6].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[6].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[6].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[6].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[6].bb.op_mode == PWR_DOWN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[7].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[7].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[7].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[7].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[7].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[7].bb.op_mode == PWR_DOWN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[8].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[8].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[8].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[8].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[8].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[8].bb.op_mode == PWR_DOWN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[9].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[9].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[9].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[9].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[9].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[9].bb.op_mode == PWR_DOWN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[10].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[10].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[10].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[10].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[10].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[10].bb.op_mode == PWR_DOWN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[11].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[11].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[11].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[11].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[11].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[11].bb.op_mode == PWR_DOWN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[12].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[12].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[12].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[12].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[12].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[12].bb.op_mode == PWR_DOWN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[13].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[13].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[13].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[13].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[13].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[13].bb.op_mode == PWR_DOWN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[14].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[14].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[14].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[14].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[14].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[14].bb.op_mode == PWR_DOWN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[15].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[15].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[15].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[15].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[15].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[15].bb.op_mode == PWR_DOWN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[16].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[16].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[16].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[16].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[16].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[16].bb.op_mode == PWR_DOWN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[17].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[17].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[17].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[17].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[17].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[17].bb.op_mode == PWR_DOWN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[18].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[18].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[18].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[18].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[18].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[18].bb.op_mode == PWR_DOWN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[19].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[19].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[19].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[19].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[19].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[19].bb.op_mode == PWR_DOWN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[20].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[20].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[20].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[20].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[20].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[20].bb.op_mode == PWR_DOWN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[21].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[21].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[21].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[21].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[21].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[21].bb.op_mode == PWR_DOWN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[22].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[22].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[22].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[22].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[22].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[22].bb.op_mode == PWR_DOWN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[23].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[23].aib_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[23].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[23].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[23].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_rx[23].bb.op_mode == PWR_DOWN
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[0].adapt_tx_data_link_net_id == 32'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[0].aib_tx_data_link_net_id == 32'd12
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[0].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[0].bb.location == MAIB11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[0].bb.op_mode == TX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[0].bb.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[1].adapt_tx_data_link_net_id == 32'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[1].aib_tx_data_link_net_id == 32'd31
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[1].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[1].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[1].bb.location == MAIB10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[1].bb.op_mode == TX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[1].bb.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[2].adapt_tx_data_link_net_id == 32'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[2].aib_tx_data_link_net_id == 32'd35
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[2].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[2].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[2].bb.location == MAIB13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[2].bb.op_mode == TX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[2].bb.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[3].adapt_tx_data_link_net_id == 32'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[3].aib_tx_data_link_net_id == 32'd39
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[3].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[3].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[3].bb.location == MAIB8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[3].bb.op_mode == TX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[3].bb.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[4].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[4].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[4].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[4].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[4].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[4].bb.op_mode == TX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[4].bb.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[5].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[5].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[5].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[5].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[5].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[5].bb.op_mode == TX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[5].bb.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[6].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[6].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[6].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[6].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[6].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[6].bb.op_mode == TX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[6].bb.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[7].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[7].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[7].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[7].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[7].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[7].bb.op_mode == TX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[7].bb.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[8].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[8].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[8].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[8].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[8].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[8].bb.op_mode == TX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[8].bb.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[9].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[9].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[9].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[9].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[9].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[9].bb.op_mode == TX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[9].bb.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[10].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[10].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[10].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[10].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[10].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[10].bb.op_mode == TX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[10].bb.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[11].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[11].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[11].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[11].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[11].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[11].bb.op_mode == TX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[11].bb.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[12].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[12].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[12].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[12].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[12].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[12].bb.op_mode == TX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[12].bb.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[13].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[13].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[13].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[13].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[13].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[13].bb.op_mode == TX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[13].bb.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[14].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[14].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[14].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[14].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[14].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[14].bb.op_mode == TX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[14].bb.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[15].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[15].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[15].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[15].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[15].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[15].bb.op_mode == TX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[15].bb.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[16].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[16].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[16].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[16].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[16].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[16].bb.op_mode == TX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[16].bb.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[17].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[17].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[17].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[17].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[17].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[17].bb.op_mode == TX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[17].bb.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[18].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[18].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[18].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[18].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[18].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[18].bb.op_mode == TX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[18].bb.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[19].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[19].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[19].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[19].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[19].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[19].bb.op_mode == TX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[19].bb.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[20].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[20].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[20].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[20].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[20].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[20].bb.op_mode == TX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[20].bb.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[21].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[21].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[21].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[21].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[21].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[21].bb.op_mode == TX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[21].bb.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[22].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[22].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[22].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[22].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[22].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[22].bb.op_mode == TX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[22].bb.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[23].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[23].aib_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[23].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[23].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[23].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[23].bb.op_mode == TX_DCC_ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_aib_tx[23].bb.sup_mode == USER_MODE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[0].avmm1_link_net_id == 32'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[0].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[0].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[0].bb.hdpldadapt_pld_avmm1_clk_rowclk_hz == 31'd35996493
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[0].bb.location == MAIB11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[1].avmm1_link_net_id == 32'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[1].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[1].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[1].bb.hdpldadapt_pld_avmm1_clk_rowclk_hz == 31'd35996493
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[1].bb.location == MAIB16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[2].avmm1_link_net_id == 32'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[2].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[2].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[2].bb.hdpldadapt_pld_avmm1_clk_rowclk_hz == 31'd35996493
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[2].bb.location == MAIB14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[3].avmm1_link_net_id == 32'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[3].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[3].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[3].bb.hdpldadapt_pld_avmm1_clk_rowclk_hz == 31'd35996493
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[3].bb.location == MAIB8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[4].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[4].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[4].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[4].bb.hdpldadapt_pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[4].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[5].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[5].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[5].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[5].bb.hdpldadapt_pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[5].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[6].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[6].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[6].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[6].bb.hdpldadapt_pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[6].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[7].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[7].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[7].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[7].bb.hdpldadapt_pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[7].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[8].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[8].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[8].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[8].bb.hdpldadapt_pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[8].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[9].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[9].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[9].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[9].bb.hdpldadapt_pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[9].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[10].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[10].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[10].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[10].bb.hdpldadapt_pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[10].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[11].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[11].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[11].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[11].bb.hdpldadapt_pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[11].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[12].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[12].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[12].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[12].bb.hdpldadapt_pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[12].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[13].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[13].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[13].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[13].bb.hdpldadapt_pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[13].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[14].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[14].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[14].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[14].bb.hdpldadapt_pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[14].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[15].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[15].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[15].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[15].bb.hdpldadapt_pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[15].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[16].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[16].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[16].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[16].bb.hdpldadapt_pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[16].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[17].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[17].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[17].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[17].bb.hdpldadapt_pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[17].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[18].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[18].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[18].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[18].bb.hdpldadapt_pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[18].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[19].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[19].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[19].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[19].bb.hdpldadapt_pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[19].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[20].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[20].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[20].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[20].bb.hdpldadapt_pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[20].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[21].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[21].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[21].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[21].bb.hdpldadapt_pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[21].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[22].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[22].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[22].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[22].bb.hdpldadapt_pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[22].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[23].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[23].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[23].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[23].bb.hdpldadapt_pld_avmm1_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm1[23].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[0].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[0].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[0].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[0].bb.hdpldadapt_pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[0].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[1].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[1].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[1].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[1].bb.hdpldadapt_pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[1].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[2].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[2].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[2].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[2].bb.hdpldadapt_pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[2].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[3].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[3].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[3].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[3].bb.hdpldadapt_pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[3].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[4].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[4].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[4].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[4].bb.hdpldadapt_pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[4].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[5].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[5].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[5].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[5].bb.hdpldadapt_pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[5].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[6].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[6].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[6].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[6].bb.hdpldadapt_pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[6].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[7].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[7].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[7].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[7].bb.hdpldadapt_pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[7].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[8].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[8].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[8].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[8].bb.hdpldadapt_pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[8].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[9].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[9].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[9].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[9].bb.hdpldadapt_pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[9].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[10].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[10].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[10].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[10].bb.hdpldadapt_pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[10].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[11].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[11].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[11].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[11].bb.hdpldadapt_pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[11].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[12].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[12].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[12].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[12].bb.hdpldadapt_pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[12].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[13].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[13].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[13].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[13].bb.hdpldadapt_pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[13].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[14].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[14].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[14].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[14].bb.hdpldadapt_pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[14].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[15].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[15].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[15].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[15].bb.hdpldadapt_pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[15].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[16].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[16].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[16].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[16].bb.hdpldadapt_pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[16].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[17].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[17].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[17].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[17].bb.hdpldadapt_pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[17].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[18].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[18].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[18].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[18].bb.hdpldadapt_pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[18].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[19].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[19].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[19].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[19].bb.hdpldadapt_pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[19].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[20].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[20].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[20].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[20].bb.hdpldadapt_pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[20].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[21].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[21].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[21].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[21].bb.hdpldadapt_pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[21].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[22].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[22].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[22].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[22].bb.hdpldadapt_pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[22].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[23].avmm2_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[23].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[23].bb.auto_profile_id == NOT_SENT_TO_CONSTRA_IP_INST_ID_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[23].bb.hdpldadapt_pld_avmm2_clk_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_avmm2[23].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[0].adapt_rx_data_link_net_id == 32'd9
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[0].avmm1_link_net_id == 32'd5
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[0].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[0].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[0].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[0].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[0].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[0].bb.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[0].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[0].bb.hdpldadapt_pld_rx_clk1_dcm_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[0].bb.hdpldadapt_pld_rx_clk1_rowclk_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[0].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[0].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[0].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[0].bb.location == MAIB11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[0].bb.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[0].bb.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[0].bb.rxfifo_pempty == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[0].bb.rxfifo_pfull == 6'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[1].adapt_rx_data_link_net_id == 32'd18
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[1].avmm1_link_net_id == 32'd14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[1].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[1].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[1].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[1].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[1].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[1].bb.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[1].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[1].bb.hdpldadapt_pld_rx_clk1_dcm_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[1].bb.hdpldadapt_pld_rx_clk1_rowclk_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[1].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[1].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[1].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[1].bb.location == MAIB16
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[1].bb.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[1].bb.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[1].bb.rxfifo_pempty == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[1].bb.rxfifo_pfull == 6'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[2].adapt_rx_data_link_net_id == 32'd23
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[2].avmm1_link_net_id == 32'd19
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[2].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[2].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[2].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[2].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[2].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[2].bb.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[2].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[2].bb.hdpldadapt_pld_rx_clk1_dcm_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[2].bb.hdpldadapt_pld_rx_clk1_rowclk_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[2].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[2].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[2].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[2].bb.location == MAIB14
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[2].bb.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[2].bb.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[2].bb.rxfifo_pempty == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[2].bb.rxfifo_pfull == 6'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[3].adapt_rx_data_link_net_id == 32'd28
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[3].avmm1_link_net_id == 32'd24
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[3].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[3].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[3].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[3].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[3].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[3].bb.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[3].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[3].bb.hdpldadapt_pld_rx_clk1_dcm_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[3].bb.hdpldadapt_pld_rx_clk1_rowclk_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[3].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[3].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[3].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[3].bb.location == MAIB8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[3].bb.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[3].bb.rx_datapath_tb_sel == PCS_CHNL_TB
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[3].bb.rxfifo_pempty == 6'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[3].bb.rxfifo_pfull == 6'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[4].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[4].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[4].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[4].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[4].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[4].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[4].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[4].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[4].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[4].bb.hdpldadapt_pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[4].bb.hdpldadapt_pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[4].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[4].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[4].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[4].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[4].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[4].bb.rx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[4].bb.rxfifo_pempty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[4].bb.rxfifo_pfull == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[5].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[5].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[5].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[5].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[5].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[5].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[5].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[5].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[5].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[5].bb.hdpldadapt_pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[5].bb.hdpldadapt_pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[5].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[5].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[5].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[5].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[5].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[5].bb.rx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[5].bb.rxfifo_pempty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[5].bb.rxfifo_pfull == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[6].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[6].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[6].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[6].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[6].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[6].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[6].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[6].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[6].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[6].bb.hdpldadapt_pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[6].bb.hdpldadapt_pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[6].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[6].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[6].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[6].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[6].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[6].bb.rx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[6].bb.rxfifo_pempty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[6].bb.rxfifo_pfull == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[7].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[7].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[7].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[7].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[7].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[7].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[7].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[7].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[7].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[7].bb.hdpldadapt_pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[7].bb.hdpldadapt_pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[7].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[7].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[7].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[7].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[7].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[7].bb.rx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[7].bb.rxfifo_pempty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[7].bb.rxfifo_pfull == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[8].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[8].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[8].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[8].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[8].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[8].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[8].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[8].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[8].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[8].bb.hdpldadapt_pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[8].bb.hdpldadapt_pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[8].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[8].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[8].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[8].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[8].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[8].bb.rx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[8].bb.rxfifo_pempty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[8].bb.rxfifo_pfull == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[9].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[9].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[9].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[9].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[9].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[9].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[9].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[9].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[9].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[9].bb.hdpldadapt_pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[9].bb.hdpldadapt_pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[9].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[9].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[9].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[9].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[9].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[9].bb.rx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[9].bb.rxfifo_pempty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[9].bb.rxfifo_pfull == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[10].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[10].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[10].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[10].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[10].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[10].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[10].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[10].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[10].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[10].bb.hdpldadapt_pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[10].bb.hdpldadapt_pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[10].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[10].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[10].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[10].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[10].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[10].bb.rx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[10].bb.rxfifo_pempty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[10].bb.rxfifo_pfull == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[11].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[11].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[11].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[11].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[11].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[11].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[11].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[11].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[11].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[11].bb.hdpldadapt_pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[11].bb.hdpldadapt_pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[11].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[11].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[11].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[11].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[11].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[11].bb.rx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[11].bb.rxfifo_pempty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[11].bb.rxfifo_pfull == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[12].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[12].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[12].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[12].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[12].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[12].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[12].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[12].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[12].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[12].bb.hdpldadapt_pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[12].bb.hdpldadapt_pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[12].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[12].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[12].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[12].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[12].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[12].bb.rx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[12].bb.rxfifo_pempty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[12].bb.rxfifo_pfull == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[13].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[13].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[13].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[13].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[13].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[13].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[13].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[13].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[13].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[13].bb.hdpldadapt_pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[13].bb.hdpldadapt_pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[13].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[13].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[13].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[13].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[13].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[13].bb.rx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[13].bb.rxfifo_pempty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[13].bb.rxfifo_pfull == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[14].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[14].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[14].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[14].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[14].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[14].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[14].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[14].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[14].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[14].bb.hdpldadapt_pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[14].bb.hdpldadapt_pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[14].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[14].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[14].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[14].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[14].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[14].bb.rx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[14].bb.rxfifo_pempty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[14].bb.rxfifo_pfull == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[15].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[15].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[15].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[15].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[15].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[15].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[15].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[15].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[15].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[15].bb.hdpldadapt_pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[15].bb.hdpldadapt_pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[15].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[15].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[15].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[15].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[15].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[15].bb.rx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[15].bb.rxfifo_pempty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[15].bb.rxfifo_pfull == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[16].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[16].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[16].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[16].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[16].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[16].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[16].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[16].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[16].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[16].bb.hdpldadapt_pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[16].bb.hdpldadapt_pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[16].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[16].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[16].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[16].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[16].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[16].bb.rx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[16].bb.rxfifo_pempty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[16].bb.rxfifo_pfull == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[17].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[17].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[17].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[17].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[17].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[17].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[17].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[17].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[17].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[17].bb.hdpldadapt_pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[17].bb.hdpldadapt_pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[17].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[17].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[17].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[17].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[17].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[17].bb.rx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[17].bb.rxfifo_pempty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[17].bb.rxfifo_pfull == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[18].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[18].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[18].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[18].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[18].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[18].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[18].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[18].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[18].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[18].bb.hdpldadapt_pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[18].bb.hdpldadapt_pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[18].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[18].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[18].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[18].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[18].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[18].bb.rx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[18].bb.rxfifo_pempty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[18].bb.rxfifo_pfull == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[19].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[19].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[19].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[19].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[19].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[19].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[19].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[19].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[19].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[19].bb.hdpldadapt_pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[19].bb.hdpldadapt_pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[19].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[19].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[19].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[19].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[19].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[19].bb.rx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[19].bb.rxfifo_pempty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[19].bb.rxfifo_pfull == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[20].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[20].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[20].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[20].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[20].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[20].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[20].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[20].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[20].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[20].bb.hdpldadapt_pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[20].bb.hdpldadapt_pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[20].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[20].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[20].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[20].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[20].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[20].bb.rx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[20].bb.rxfifo_pempty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[20].bb.rxfifo_pfull == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[21].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[21].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[21].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[21].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[21].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[21].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[21].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[21].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[21].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[21].bb.hdpldadapt_pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[21].bb.hdpldadapt_pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[21].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[21].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[21].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[21].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[21].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[21].bb.rx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[21].bb.rxfifo_pempty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[21].bb.rxfifo_pfull == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[22].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[22].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[22].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[22].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[22].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[22].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[22].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[22].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[22].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[22].bb.hdpldadapt_pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[22].bb.hdpldadapt_pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[22].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[22].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[22].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[22].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[22].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[22].bb.rx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[22].bb.rxfifo_pempty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[22].bb.rxfifo_pfull == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[23].adapt_rx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[23].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[23].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[23].ptp_master_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[23].ptp_pairing_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[23].ptp_slave_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[23].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[23].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[23].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[23].bb.hdpldadapt_pld_rx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[23].bb.hdpldadapt_pld_rx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[23].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[23].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[23].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[23].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[23].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[23].bb.rx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[23].bb.rxfifo_pempty == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_rx[23].bb.rxfifo_pfull == 6'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[0].adapt_tx_data_link_net_id == 32'd13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[0].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[0].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[0].bb.duplex_mode == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[0].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[0].bb.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[0].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[0].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[0].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[0].bb.hdpldadapt_pld_tx_clk1_dcm_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[0].bb.hdpldadapt_pld_tx_clk1_rowclk_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[0].bb.hdpldadapt_pld_tx_clk2_dcm_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[0].bb.hdpldadapt_pld_tx_clk2_rowclk_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[0].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[0].bb.location == MAIB11
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[0].bb.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[0].bb.pld_clk2_sel == PLD_CLK2_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[0].bb.tx_datapath_tb_sel == TX_FIFO_TB1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[0].bb.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[0].bb.txfifo_pfull == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[1].adapt_tx_data_link_net_id == 32'd32
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[1].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[1].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[1].bb.duplex_mode == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[1].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[1].bb.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[1].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[1].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[1].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[1].bb.hdpldadapt_pld_tx_clk1_dcm_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[1].bb.hdpldadapt_pld_tx_clk1_rowclk_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[1].bb.hdpldadapt_pld_tx_clk2_dcm_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[1].bb.hdpldadapt_pld_tx_clk2_rowclk_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[1].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[1].bb.location == MAIB10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[1].bb.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[1].bb.pld_clk2_sel == PLD_CLK2_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[1].bb.tx_datapath_tb_sel == TX_FIFO_TB1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[1].bb.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[1].bb.txfifo_pfull == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[2].adapt_tx_data_link_net_id == 32'd36
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[2].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[2].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[2].bb.duplex_mode == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[2].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[2].bb.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[2].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[2].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[2].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[2].bb.hdpldadapt_pld_tx_clk1_dcm_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[2].bb.hdpldadapt_pld_tx_clk1_rowclk_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[2].bb.hdpldadapt_pld_tx_clk2_dcm_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[2].bb.hdpldadapt_pld_tx_clk2_rowclk_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[2].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[2].bb.location == MAIB13
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[2].bb.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[2].bb.pld_clk2_sel == PLD_CLK2_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[2].bb.tx_datapath_tb_sel == TX_FIFO_TB1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[2].bb.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[2].bb.txfifo_pfull == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[3].adapt_tx_data_link_net_id == 32'd40
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[3].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[3].is_used == TRUE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[3].bb.duplex_mode == ENABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[3].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[3].bb.fifo_width == FIFO_DOUBLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[3].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[3].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[3].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[3].bb.hdpldadapt_pld_tx_clk1_dcm_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[3].bb.hdpldadapt_pld_tx_clk1_rowclk_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[3].bb.hdpldadapt_pld_tx_clk2_dcm_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[3].bb.hdpldadapt_pld_tx_clk2_rowclk_hz == 31'd450000000
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[3].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[3].bb.location == MAIB8
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[3].bb.pld_clk1_sel == PLD_CLK1_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[3].bb.pld_clk2_sel == PLD_CLK2_DCM
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[3].bb.tx_datapath_tb_sel == TX_FIFO_TB1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[3].bb.txfifo_pempty == 5'd2
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[3].bb.txfifo_pfull == 5'd10
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[4].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[4].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[4].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[4].bb.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[4].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[4].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[4].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[4].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[4].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[4].bb.hdpldadapt_pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[4].bb.hdpldadapt_pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[4].bb.hdpldadapt_pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[4].bb.hdpldadapt_pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[4].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[4].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[4].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[4].bb.pld_clk2_sel == PLD_CLK2_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[4].bb.tx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[4].bb.txfifo_pempty == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[4].bb.txfifo_pfull == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[5].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[5].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[5].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[5].bb.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[5].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[5].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[5].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[5].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[5].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[5].bb.hdpldadapt_pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[5].bb.hdpldadapt_pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[5].bb.hdpldadapt_pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[5].bb.hdpldadapt_pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[5].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[5].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[5].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[5].bb.pld_clk2_sel == PLD_CLK2_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[5].bb.tx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[5].bb.txfifo_pempty == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[5].bb.txfifo_pfull == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[6].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[6].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[6].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[6].bb.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[6].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[6].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[6].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[6].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[6].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[6].bb.hdpldadapt_pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[6].bb.hdpldadapt_pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[6].bb.hdpldadapt_pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[6].bb.hdpldadapt_pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[6].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[6].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[6].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[6].bb.pld_clk2_sel == PLD_CLK2_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[6].bb.tx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[6].bb.txfifo_pempty == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[6].bb.txfifo_pfull == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[7].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[7].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[7].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[7].bb.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[7].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[7].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[7].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[7].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[7].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[7].bb.hdpldadapt_pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[7].bb.hdpldadapt_pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[7].bb.hdpldadapt_pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[7].bb.hdpldadapt_pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[7].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[7].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[7].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[7].bb.pld_clk2_sel == PLD_CLK2_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[7].bb.tx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[7].bb.txfifo_pempty == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[7].bb.txfifo_pfull == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[8].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[8].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[8].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[8].bb.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[8].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[8].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[8].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[8].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[8].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[8].bb.hdpldadapt_pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[8].bb.hdpldadapt_pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[8].bb.hdpldadapt_pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[8].bb.hdpldadapt_pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[8].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[8].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[8].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[8].bb.pld_clk2_sel == PLD_CLK2_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[8].bb.tx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[8].bb.txfifo_pempty == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[8].bb.txfifo_pfull == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[9].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[9].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[9].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[9].bb.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[9].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[9].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[9].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[9].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[9].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[9].bb.hdpldadapt_pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[9].bb.hdpldadapt_pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[9].bb.hdpldadapt_pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[9].bb.hdpldadapt_pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[9].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[9].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[9].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[9].bb.pld_clk2_sel == PLD_CLK2_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[9].bb.tx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[9].bb.txfifo_pempty == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[9].bb.txfifo_pfull == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[10].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[10].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[10].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[10].bb.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[10].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[10].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[10].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[10].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[10].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[10].bb.hdpldadapt_pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[10].bb.hdpldadapt_pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[10].bb.hdpldadapt_pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[10].bb.hdpldadapt_pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[10].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[10].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[10].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[10].bb.pld_clk2_sel == PLD_CLK2_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[10].bb.tx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[10].bb.txfifo_pempty == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[10].bb.txfifo_pfull == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[11].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[11].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[11].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[11].bb.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[11].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[11].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[11].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[11].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[11].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[11].bb.hdpldadapt_pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[11].bb.hdpldadapt_pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[11].bb.hdpldadapt_pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[11].bb.hdpldadapt_pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[11].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[11].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[11].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[11].bb.pld_clk2_sel == PLD_CLK2_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[11].bb.tx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[11].bb.txfifo_pempty == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[11].bb.txfifo_pfull == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[12].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[12].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[12].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[12].bb.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[12].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[12].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[12].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[12].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[12].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[12].bb.hdpldadapt_pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[12].bb.hdpldadapt_pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[12].bb.hdpldadapt_pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[12].bb.hdpldadapt_pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[12].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[12].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[12].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[12].bb.pld_clk2_sel == PLD_CLK2_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[12].bb.tx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[12].bb.txfifo_pempty == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[12].bb.txfifo_pfull == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[13].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[13].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[13].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[13].bb.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[13].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[13].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[13].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[13].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[13].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[13].bb.hdpldadapt_pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[13].bb.hdpldadapt_pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[13].bb.hdpldadapt_pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[13].bb.hdpldadapt_pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[13].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[13].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[13].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[13].bb.pld_clk2_sel == PLD_CLK2_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[13].bb.tx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[13].bb.txfifo_pempty == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[13].bb.txfifo_pfull == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[14].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[14].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[14].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[14].bb.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[14].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[14].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[14].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[14].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[14].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[14].bb.hdpldadapt_pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[14].bb.hdpldadapt_pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[14].bb.hdpldadapt_pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[14].bb.hdpldadapt_pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[14].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[14].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[14].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[14].bb.pld_clk2_sel == PLD_CLK2_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[14].bb.tx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[14].bb.txfifo_pempty == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[14].bb.txfifo_pfull == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[15].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[15].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[15].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[15].bb.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[15].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[15].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[15].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[15].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[15].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[15].bb.hdpldadapt_pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[15].bb.hdpldadapt_pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[15].bb.hdpldadapt_pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[15].bb.hdpldadapt_pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[15].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[15].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[15].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[15].bb.pld_clk2_sel == PLD_CLK2_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[15].bb.tx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[15].bb.txfifo_pempty == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[15].bb.txfifo_pfull == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[16].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[16].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[16].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[16].bb.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[16].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[16].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[16].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[16].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[16].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[16].bb.hdpldadapt_pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[16].bb.hdpldadapt_pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[16].bb.hdpldadapt_pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[16].bb.hdpldadapt_pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[16].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[16].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[16].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[16].bb.pld_clk2_sel == PLD_CLK2_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[16].bb.tx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[16].bb.txfifo_pempty == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[16].bb.txfifo_pfull == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[17].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[17].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[17].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[17].bb.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[17].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[17].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[17].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[17].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[17].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[17].bb.hdpldadapt_pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[17].bb.hdpldadapt_pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[17].bb.hdpldadapt_pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[17].bb.hdpldadapt_pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[17].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[17].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[17].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[17].bb.pld_clk2_sel == PLD_CLK2_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[17].bb.tx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[17].bb.txfifo_pempty == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[17].bb.txfifo_pfull == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[18].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[18].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[18].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[18].bb.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[18].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[18].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[18].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[18].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[18].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[18].bb.hdpldadapt_pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[18].bb.hdpldadapt_pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[18].bb.hdpldadapt_pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[18].bb.hdpldadapt_pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[18].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[18].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[18].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[18].bb.pld_clk2_sel == PLD_CLK2_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[18].bb.tx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[18].bb.txfifo_pempty == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[18].bb.txfifo_pfull == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[19].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[19].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[19].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[19].bb.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[19].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[19].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[19].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[19].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[19].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[19].bb.hdpldadapt_pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[19].bb.hdpldadapt_pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[19].bb.hdpldadapt_pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[19].bb.hdpldadapt_pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[19].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[19].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[19].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[19].bb.pld_clk2_sel == PLD_CLK2_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[19].bb.tx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[19].bb.txfifo_pempty == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[19].bb.txfifo_pfull == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[20].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[20].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[20].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[20].bb.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[20].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[20].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[20].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[20].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[20].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[20].bb.hdpldadapt_pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[20].bb.hdpldadapt_pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[20].bb.hdpldadapt_pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[20].bb.hdpldadapt_pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[20].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[20].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[20].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[20].bb.pld_clk2_sel == PLD_CLK2_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[20].bb.tx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[20].bb.txfifo_pempty == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[20].bb.txfifo_pfull == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[21].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[21].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[21].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[21].bb.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[21].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[21].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[21].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[21].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[21].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[21].bb.hdpldadapt_pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[21].bb.hdpldadapt_pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[21].bb.hdpldadapt_pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[21].bb.hdpldadapt_pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[21].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[21].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[21].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[21].bb.pld_clk2_sel == PLD_CLK2_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[21].bb.tx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[21].bb.txfifo_pempty == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[21].bb.txfifo_pfull == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[22].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[22].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[22].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[22].bb.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[22].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[22].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[22].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[22].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[22].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[22].bb.hdpldadapt_pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[22].bb.hdpldadapt_pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[22].bb.hdpldadapt_pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[22].bb.hdpldadapt_pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[22].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[22].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[22].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[22].bb.pld_clk2_sel == PLD_CLK2_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[22].bb.tx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[22].bb.txfifo_pempty == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[22].bb.txfifo_pfull == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[23].adapt_tx_data_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[23].avmm1_link_net_id == 32'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[23].is_used == FALSE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[23].bb.duplex_mode == DISABLE
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[23].bb.fifo_mode == PHASE_COMP
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[23].bb.fifo_width == FIFO_SINGLE_WIDTH
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[23].bb.hdpldadapt_aib_fabric_pld_pma_hclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[23].bb.hdpldadapt_pld_sclk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[23].bb.hdpldadapt_pld_sclk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[23].bb.hdpldadapt_pld_tx_clk1_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[23].bb.hdpldadapt_pld_tx_clk1_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[23].bb.hdpldadapt_pld_tx_clk2_dcm_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[23].bb.hdpldadapt_pld_tx_clk2_rowclk_hz == 31'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[23].bb.hdpldadapt_speed_grade == HDPLDADAPT_DASH_1
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[23].bb.location == MAIB0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[23].bb.pld_clk1_sel == PLD_CLK1_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[23].bb.pld_clk2_sel == PLD_CLK2_ROWCLK
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[23].bb.tx_datapath_tb_sel == CP_BOND
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[23].bb.txfifo_pempty == 5'd0
sdi_ii_agi_demo_auto_tiles.z1577b_x393_y0_n0.user.bb_m_hdpldadapt_tx[23].bb.txfifo_pfull == 5'd0
